WARNING: Logging before InitGoogleLogging() is written to STDERR
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:303] Vitis AI EP Load ONNX Model Success
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:304] Graph Input Node Name/Shape (3)
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:308] 	 input_ids : [1x128]
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:308] 	 attention_mask : [1x128]
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:308] 	 position_ids : [1x128]
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:314] Graph Output Node Name/Shape (1)
I20230929 20:31:17.686592 17136 vitisai_compile_model.cpp:318] 	 logits : [1x128x1000]
I20230929 20:31:17.716929 17136 pass_imp.cpp:366] save const info to "C:\\temp\\Felix\\vaip\\.cache\\7cbda979b60d8f5a28446d3d5ea476d8\\const_info_before_const_folding.txt"
I20230929 20:31:17.814642 17136 pass_imp.cpp:275] save fix info to "C:\\temp\\Felix\\vaip\\.cache\\7cbda979b60d8f5a28446d3d5ea476d8\\fix_info.txt"
I20230929 20:31:17.814642 17136 pass_imp.cpp:366] save const info to "C:\\temp\\Felix\\vaip\\.cache\\7cbda979b60d8f5a28446d3d5ea476d8\\const_info_after_const_folding.txt"
I20230929 20:31:17.814642 17136 pass_imp.cpp:393] save const info to "C:\\temp\\Felix\\vaip\\.cache\\7cbda979b60d8f5a28446d3d5ea476d8\\const.bin"
W20230929 20:31:17.814642 17136 to_xir_ops_pass.cpp:212] cancal xir ops conversion, xir not support data type: 6 node : @36 [/transformer/Reshape_output_0:(ty=6,shape=[1,128])] Reshape [input_ids:(ty=6,shape=[1,128]),ortshared_7_1_2_2_token_426:(ty=7,shape=[2])]
W20230929 20:31:17.814642 17136 to_xir_ops_pass.cpp:212] cancal xir ops conversion, xir not support data type: 6 node : @31 [/transformer/Reshape_1_output_0:(ty=6,shape=[1,128])] Reshape [position_ids:(ty=6,shape=[1,128]),ortshared_7_1_2_2_token_426:(ty=7,shape=[2])]
W20230929 20:31:17.819464 17136 to_xir_ops_pass.cpp:212] cancal xir ops conversion, xir not support data type: 6 node : @84 [/transformer/Reshape_2_output_0:(ty=6,shape=[1,128])] Reshape [attention_mask:(ty=6,shape=[1,128]),ortshared_7_1_2_1_token_416:(ty=7,shape=[2])]
W20230929 20:31:17.819464 17136 to_xir_ops_pass.cpp:212] cancal xir ops conversion, xir not support data type: 6 node : @85 [/transformer/Unsqueeze_output_0:(ty=6,shape=[1,1,128])] Unsqueeze [/transformer/Reshape_2_output_0:(ty=6,shape=[1,128]),ortshared_7_1_1_0_token_409:(ty=7,shape=[1])]
W20230929 20:31:17.819464 17136 to_xir_ops_pass.cpp:212] cancal xir ops conversion, xir not support data type: 6 node : @86 [/transformer/Unsqueeze_1_output_0:(ty=6,shape=[1,1,1,128])] Unsqueeze [/transformer/Unsqueeze_output_0:(ty=6,shape=[1,1,128]),ortshared_7_1_1_1_token_423:(ty=7,shape=[1])]
W20230929 20:31:17.977519 17136 tool_function.cpp:171] The operator named /transformer/h.0/attn/Split_output_0, type: Selector, is not defined in XIR. XIR creates the definition of this operator automatically. You should specify the shape and the data_type of the output tensor of this operation by set_attr("shape", std::vector<int>) and set_attr("data_type", std::string)
I20230929 20:31:18.785475 17136 compile_pass_manager.cpp:354] Compile mode: aie
I20230929 20:31:18.785475 17136 compile_pass_manager.cpp:355] Debug mode: performance
I20230929 20:31:18.785475 17136 compile_pass_manager.cpp:359] Target architecture: AMD_AIE2_Nx4_Overlay
I20230929 20:31:18.785475 17136 compile_pass_manager.cpp:519] Graph name: torch_jit, with op num: 820
I20230929 20:31:18.785475 17136 compile_pass_manager.cpp:532] Begin to compile...
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_88_vaip_106_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_88, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_86_vaip_87_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_86, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_84_vaip_68_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_84, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_82_vaip_49_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_token_82, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output_vaip_29_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated_vaip_28_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_2_token_167_DequantizeLinear_Output/duplicated, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = transformer.wpe.weight_DequantizeLinear_Output_vaip_22_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = transformer.wpe.weight_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = transformer.wte.weight_DequantizeLinear_Output_vaip_21_const, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = transformer.wte.weight_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_2_2_token_426_copy_1, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_3_token_402_copy_4, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_3_token_402_copy_3, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_3_token_402_copy_2, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_3_token_402_copy_1, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_3_0_token_398_copy_4, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_3_0_token_398_copy_3, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_3_0_token_398_copy_2, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_3_0_token_398_copy_1, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_10, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_9, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_8, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_7, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_6, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_5, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_4, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_3, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_2, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420_copy_1, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_7_token_407_copy_4, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_7_token_407_copy_3, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_7_token_407_copy_2, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_7_token_407_copy_1, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Reshape_output_0, type = :Reshape} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/wte/Gather_output_0, type = :Gather} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/wte/Gather_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_2_2_token_426, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Reshape_1_output_0, type = :Reshape} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/wpe/Gather_output_0, type = :Gather} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/wpe/Gather_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Add_output_0_DequantizeLinear_Output/duplicated_token_0_/transformer/h.0/ln_1/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Add_output_0_DequantizeLinear_Output/duplicated_token_0_/transformer/h.0/ln_1/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_15_token_420, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/ln_1/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/ln_1/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/ln_1/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Add_output_0_DequantizeLinear_Output_/transformer/h.0/ln_1/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_1/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/ln_1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/ln_1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/ln_1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/c_attn/Reshape_1_output_0_DequantizeLinear_Output_:/transformer/h.0/attn/Split_output_0:/transformer/h.0/attn/Split_output_1:/transformer/h.0/attn/Split_output_2, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_3_0_token_398, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = :/transformer/h.0/attn/Split_output_0:/transformer/h.0/attn/Split_output_1:/transformer/h.0/attn/Split_output_2, type = :Split} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_0, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Transpose_output_0_DequantizeLinear_Output_fix_/transformer/h.0/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_1, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_1_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Transpose_2_output_0_DequantizeLinear_Output_fix_/transformer/h.0/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/MatMul_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/MatMul_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_2, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Split_output_2_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Transpose_1_output_0_DequantizeLinear_Output_fix_/transformer/h.0/attn/MatMul_1_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_3_token_402, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Constant_7_output_0, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Where_output_0, type = :Where} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Where_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_1_1_token_423, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_1_0_token_409, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_7_1_2_1_token_416, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Reshape_2_output_0, type = :Reshape} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Unsqueeze_output_0, type = :Unsqueeze} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Unsqueeze_1_output_0, type = :Unsqueeze} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Cast_output_0, type = :Cast} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/Sub_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Add_1_output_0_DequantizeLinear_Output_/transformer/h.0/attn/Softmax_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Softmax_output_0, type = softmax} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/Softmax_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/MatMul_1_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/attn/MatMul_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/Add_output_0_DequantizeLinear_Output/duplicated_token_104_/transformer/h.0/ln_2/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/Add_output_0_DequantizeLinear_Output/duplicated_token_104_/transformer/h.0/ln_2/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/ln_2/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/ln_2/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/ln_2/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Add_output_0_DequantizeLinear_Output_/transformer/h.0/ln_2/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/ln_2/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/ln_2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/ln_2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/ln_2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/c_fc/Reshape_1_output_0_DequantizeLinear_Output/duplicated_token_112_/transformer/h.0/mlp/act/Pow_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = ortshared_1_0_1_7_token_407, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/act/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/act/Pow_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/mlp/act/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/mlp/act/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/mlp/act/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/act/Mul_2_output_0_DequantizeLinear_Output_/transformer/h.0/mlp/act/Tanh_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/act/Tanh_output_0, type = tanh} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/mlp/act/Tanh_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/mlp/act/Add_1_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/mlp/act/Add_1_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/mlp/act/Add_1_output_0_new_new , has input tensor of dimension 3].
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/mlp/act/Mul_3_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/mlp/act/Mul_3_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/mlp/act/Mul_3_output_0_new , has input tensor of dimension 3].
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.0/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.0/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.0/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/Add_1_output_0_DequantizeLinear_Output/duplicated_token_132_/transformer/h.1/ln_1/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.0/Add_1_output_0_DequantizeLinear_Output/duplicated_token_132_/transformer/h.1/ln_1/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/ln_1/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/ln_1/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/ln_1/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Add_output_0_DequantizeLinear_Output_/transformer/h.1/ln_1/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_1/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/ln_1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/ln_1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/ln_1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/c_attn/Reshape_1_output_0_DequantizeLinear_Output_:/transformer/h.1/attn/Split_output_0:/transformer/h.1/attn/Split_output_1:/transformer/h.1/attn/Split_output_2, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = :/transformer/h.1/attn/Split_output_0:/transformer/h.1/attn/Split_output_1:/transformer/h.1/attn/Split_output_2, type = :Split} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_0, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Transpose_output_0_DequantizeLinear_Output_fix_/transformer/h.1/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_1, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_1_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Transpose_2_output_0_DequantizeLinear_Output_fix_/transformer/h.1/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/MatMul_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/MatMul_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_2, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Split_output_2_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Transpose_1_output_0_DequantizeLinear_Output_fix_/transformer/h.1/attn/MatMul_1_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Constant_7_output_0, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Where_output_0, type = :Where} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Where_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Add_1_output_0_DequantizeLinear_Output_/transformer/h.1/attn/Softmax_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Softmax_output_0, type = softmax} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/Softmax_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/MatMul_1_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/attn/MatMul_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/Add_output_0_DequantizeLinear_Output/duplicated_token_134_/transformer/h.1/ln_2/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/Add_output_0_DequantizeLinear_Output/duplicated_token_134_/transformer/h.1/ln_2/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/ln_2/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/ln_2/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/ln_2/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Add_output_0_DequantizeLinear_Output_/transformer/h.1/ln_2/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/ln_2/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/ln_2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/ln_2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/ln_2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/c_fc/Reshape_1_output_0_DequantizeLinear_Output/duplicated_token_136_/transformer/h.1/mlp/act/Pow_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/act/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/act/Pow_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/mlp/act/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/mlp/act/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/mlp/act/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/act/Mul_2_output_0_DequantizeLinear_Output_/transformer/h.1/mlp/act/Tanh_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/act/Tanh_output_0, type = tanh} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/mlp/act/Tanh_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/mlp/act/Add_1_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/mlp/act/Add_1_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/mlp/act/Add_1_output_0_new_new , has input tensor of dimension 3].
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/mlp/act/Mul_3_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/mlp/act/Mul_3_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/mlp/act/Mul_3_output_0_new , has input tensor of dimension 3].
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/Add_1_output_0_DequantizeLinear_Output/duplicated_token_138_/transformer/h.2/ln_1/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.1/Add_1_output_0_DequantizeLinear_Output/duplicated_token_138_/transformer/h.2/ln_1/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/ln_1/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/ln_1/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/ln_1/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Add_output_0_DequantizeLinear_Output_/transformer/h.2/ln_1/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.968061 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_1/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/ln_1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.968061 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/ln_1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/ln_1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/c_attn/Reshape_1_output_0_DequantizeLinear_Output_:/transformer/h.2/attn/Split_output_0:/transformer/h.2/attn/Split_output_1:/transformer/h.2/attn/Split_output_2, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = :/transformer/h.2/attn/Split_output_0:/transformer/h.2/attn/Split_output_1:/transformer/h.2/attn/Split_output_2, type = :Split} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_0, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Transpose_output_0_DequantizeLinear_Output_fix_/transformer/h.2/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_1, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_1_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Transpose_2_output_0_DequantizeLinear_Output_fix_/transformer/h.2/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/MatMul_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/MatMul_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_2, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Split_output_2_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Transpose_1_output_0_DequantizeLinear_Output_fix_/transformer/h.2/attn/MatMul_1_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Constant_7_output_0, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Where_output_0, type = :Where} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Where_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Add_1_output_0_DequantizeLinear_Output_/transformer/h.2/attn/Softmax_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Softmax_output_0, type = softmax} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/Softmax_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/MatMul_1_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/attn/MatMul_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/Add_output_0_DequantizeLinear_Output/duplicated_token_140_/transformer/h.2/ln_2/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/Add_output_0_DequantizeLinear_Output/duplicated_token_140_/transformer/h.2/ln_2/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/ln_2/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/ln_2/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/ln_2/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Add_output_0_DequantizeLinear_Output_/transformer/h.2/ln_2/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/ln_2/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/ln_2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/ln_2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/ln_2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/c_fc/Reshape_1_output_0_DequantizeLinear_Output/duplicated_token_142_/transformer/h.2/mlp/act/Pow_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/act/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/act/Pow_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/mlp/act/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/mlp/act/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/mlp/act/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/act/Mul_2_output_0_DequantizeLinear_Output_/transformer/h.2/mlp/act/Tanh_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/act/Tanh_output_0, type = tanh} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/mlp/act/Tanh_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/mlp/act/Add_1_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/mlp/act/Add_1_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/mlp/act/Add_1_output_0_new_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/mlp/act/Mul_3_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/mlp/act/Mul_3_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/mlp/act/Mul_3_output_0_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/Add_1_output_0_DequantizeLinear_Output/duplicated_token_144_/transformer/h.3/ln_1/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.2/Add_1_output_0_DequantizeLinear_Output/duplicated_token_144_/transformer/h.3/ln_1/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/ln_1/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/ln_1/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/ln_1/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Add_output_0_DequantizeLinear_Output_/transformer/h.3/ln_1/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_1/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/ln_1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/ln_1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/ln_1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/c_attn/Reshape_1_output_0_DequantizeLinear_Output_:/transformer/h.3/attn/Split_output_0:/transformer/h.3/attn/Split_output_1:/transformer/h.3/attn/Split_output_2, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = :/transformer/h.3/attn/Split_output_0:/transformer/h.3/attn/Split_output_1:/transformer/h.3/attn/Split_output_2, type = :Split} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_0, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Transpose_output_0_DequantizeLinear_Output_fix_/transformer/h.3/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_1, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_1_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Transpose_2_output_0_DequantizeLinear_Output_fix_/transformer/h.3/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/MatMul_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/MatMul_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_2, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Split_output_2_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Transpose_1_output_0_DequantizeLinear_Output_fix_/transformer/h.3/attn/MatMul_1_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Constant_7_output_0, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Where_output_0, type = :Where} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Where_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Add_1_output_0_DequantizeLinear_Output_/transformer/h.3/attn/Softmax_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Softmax_output_0, type = softmax} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/Softmax_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/MatMul_1_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/attn/MatMul_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/Add_output_0_DequantizeLinear_Output/duplicated_token_146_/transformer/h.3/ln_2/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/Add_output_0_DequantizeLinear_Output/duplicated_token_146_/transformer/h.3/ln_2/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/ln_2/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/ln_2/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/ln_2/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Add_output_0_DequantizeLinear_Output_/transformer/h.3/ln_2/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/ln_2/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/ln_2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/ln_2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/ln_2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/c_fc/Reshape_1_output_0_DequantizeLinear_Output/duplicated_token_148_/transformer/h.3/mlp/act/Pow_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/act/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/act/Pow_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/mlp/act/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/mlp/act/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/mlp/act/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/act/Mul_2_output_0_DequantizeLinear_Output_/transformer/h.3/mlp/act/Tanh_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/act/Tanh_output_0, type = tanh} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/mlp/act/Tanh_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/mlp/act/Add_1_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/mlp/act/Add_1_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/mlp/act/Add_1_output_0_new_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/mlp/act/Mul_3_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/mlp/act/Mul_3_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/mlp/act/Mul_3_output_0_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.3/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.3/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.3/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/Add_1_output_0_DequantizeLinear_Output/duplicated_token_150_/transformer/h.4/ln_1/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.3/Add_1_output_0_DequantizeLinear_Output/duplicated_token_150_/transformer/h.4/ln_1/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/ln_1/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/ln_1/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/ln_1/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Add_output_0_DequantizeLinear_Output_/transformer/h.4/ln_1/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_1/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/ln_1/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/ln_1/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/ln_1/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/c_attn/Reshape_1_output_0_DequantizeLinear_Output_:/transformer/h.4/attn/Split_output_0:/transformer/h.4/attn/Split_output_1:/transformer/h.4/attn/Split_output_2, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = :/transformer/h.4/attn/Split_output_0:/transformer/h.4/attn/Split_output_1:/transformer/h.4/attn/Split_output_2, type = :Split} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_0, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Transpose_output_0_DequantizeLinear_Output_fix_/transformer/h.4/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_1, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_1_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Transpose_2_output_0_DequantizeLinear_Output_fix_/transformer/h.4/attn/MatMul_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/MatMul_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/MatMul_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_2, type = Selector} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Split_output_2_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Transpose_1_output_0_DequantizeLinear_Output_fix_/transformer/h.4/attn/MatMul_1_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Constant_7_output_0, type = const} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Where_output_0, type = :Where} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Where_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Add_1_output_0_DequantizeLinear_Output_/transformer/h.4/attn/Softmax_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Softmax_output_0, type = softmax} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/Softmax_output_0_DequantizeLinear_Output, type = fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/MatMul_1_output_0, type = matmul} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/attn/MatMul_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/Add_output_0_DequantizeLinear_Output/duplicated_token_152_/transformer/h.4/ln_2/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/Add_output_0_DequantizeLinear_Output/duplicated_token_152_/transformer/h.4/ln_2/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/ln_2/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/ln_2/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/ln_2/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Add_output_0_DequantizeLinear_Output_/transformer/h.4/ln_2/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/ln_2/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/ln_2/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/ln_2/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/ln_2/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/c_fc/Reshape_1_output_0_DequantizeLinear_Output/duplicated_token_154_/transformer/h.4/mlp/act/Pow_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/act/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/act/Pow_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/mlp/act/Add_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/mlp/act/Add_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/mlp/act/Add_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/act/Mul_2_output_0_DequantizeLinear_Output_/transformer/h.4/mlp/act/Tanh_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/act/Tanh_output_0, type = tanh} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/mlp/act/Tanh_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/mlp/act/Add_1_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/mlp/act/Add_1_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/mlp/act/Add_1_output_0_new_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/mlp/act/Mul_3_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/mlp/act/Mul_3_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/mlp/act/Mul_3_output_0_new , has input tensor of dimension 3].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/h.4/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/h.4/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/h.4/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/Add_1_output_0_DequantizeLinear_Output/duplicated_/transformer/ln_f/ReduceMean_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/ReduceMean_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/h.4/Add_1_output_0_DequantizeLinear_Output/duplicated_/transformer/ln_f/Sub_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Sub_output_0, type = sub} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Pow_output_0, type = :Pow} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/ReduceMean_1_output_0, type = reduction_mean} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/ReduceMean_1_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/ln_f/Add_output_0_new_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/ln_f/Add_output_0_new_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/ln_f/Add_output_0_new_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Add_output_0_DequantizeLinear_Output_/transformer/ln_f/Sqrt_output_0, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Sqrt_output_0, type = :Sqrt} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Div_output_0, type = div} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = /transformer/ln_f/Div_output_0_DequantizeLinear_Output, type = float2fix} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4403] IPU prefers xir::Op{name = /transformer/ln_f/Add_1_output_0_new, type = eltwise-fix}'s input to be 4-D, but it's 3-D now. So it will be assigned to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4816] xir::Op{name = /transformer/ln_f/Add_1_output_0_new, type = eltwise-fix} has been assigned to CPU: [element wise only support 4-D input layout (NHWC) but this elew /transformer/ln_f/Add_1_output_0_new , has input tensor of dimension 3].
I20230929 20:31:47.983688 17136 PartitionPass.cpp:4891] xir::Op{name = logits_, type = fix2float} is not supported by current target. Target name: AMD_AIE2_Nx4_Overlay, target type: IPU_PHX. Assign it to CPU.
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_74_vaip_122(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_70_vaip_111(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_66_vaip_103(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_62_vaip_92(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_58_vaip_84(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_54_vaip_73(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_50_vaip_65(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_46_vaip_54(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_42_vaip_46(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output/duplicated_token_38_vaip_35(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = transformer.h.0.ln_1.bias_DequantizeLinear_Output_vaip_25(MergeDataReshape), type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_18_vaip_120_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output/duplicated_token_96_vaip_116_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_16_vaip_109_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_14_vaip_101_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output/duplicated_token_94_vaip_97_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_12_vaip_90_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_10_vaip_82_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output/duplicated_token_92_vaip_78_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_8_vaip_71_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_6_vaip_63_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output/duplicated_token_90_vaip_59_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_4_vaip_52_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_token_2_vaip_44_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_6_token_175_DequantizeLinear_Output/duplicated_vaip_40_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output/duplicated_vaip_33_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
W20230929 20:31:47.983688 17136 PartitionPass.cpp:4847] xir::Op{name = ortshared_1_0_1_4_token_172_DequantizeLinear_Output_vaip_23_new, type = const-fix} has been assigned to CPU: [Has no fanout or at least one fanout is out of DPU subgraph.].
F20230929 20:31:48.739473 17136 KernelParamGenPass.cpp:1815] Check failed: shift_bias_ >= low_bound && shift_bias_ < 16 xir::Op{name = /transformer/h.0/attn/c_proj/Gemm_output_0(TransferMatMulToConv2d), type = conv2d-fix} shift_bias only support [-7,16). shift_bias is:  20.   Please check the fix-point info and may re-quantize this model.
I20230929 20:31:48.770743 17136 vitisai_compile_model.cpp:335] Catch fatal exception, skip this subgraph. Set XLNX_ENABLE_SKIP_FATAL=0 to stop skip.
attrs_create_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
create_graph_runner_subgraph_cif
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: virtual char const * __ptr64 __cdecl pybind11::error_already_set::what(void)const __ptr64
public: class pybind11::object const & __ptr64 __cdecl pybind11::error_already_set::type(void)const __ptr64
public: void __cdecl pybind11::error_already_set::clear(void) __ptr64
public: void __cdecl pybind11::error_already_set::clear(void) __ptr64
public: void __cdecl pybind11::error_already_set::clear(void) __ptr64
class vaip_core::DllSafe<class std::vector<class std::unique_ptr<class vaip_core::ExecutionProvider,struct std::default_delete<class vaip_core::ExecutionProvider> >,class std::allocator<class std::unique_ptr<class vaip_core::ExecutionProvider,struct std:
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
PyInit_onnxruntime_pybind11_state
public: void __cdecl pybind11::error_already_set::discard_as_unraisable(class pybind11::object) __ptr64
_PyArg_ParseTuple_SizeT
my env C:\Users\Felix\Downloads\voe-4.0-win-amd64\voe-4.0-win_amd64\1x4.xclbin
after load
['!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!']
['!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!']