rtl-llm
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qwen2.5coder-7b-origen-vhdl-verilog

Text Generation

text-generation-inference

Model card Files Files and versions

qwen2.5coder-7b-origen-vhdl-verilog / model-00004-of-00004.safetensors

Commit History

Upload Qwen2ForCausalLM

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charleshong3 commited on May 27