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#include <bits/stdc++.h> using namespace std; char A[3][3], B[3][3]; int main() { scanf( %s , A[0]); scanf( %s , A[1]); scanf( %s , B[0]); scanf( %s , B[1]); string a = A[0], b = B[0]; a += A[1][1]; a += A[1][0]; b += B[1][1]; b += B[1][0]; for (int i = 0; i < a.length(); i++) if (a[i] == X ) a.erase(a.begin() + i); for (int i = 0; i < b.length(); i++) if (b[i] == X ) b.erase(b.begin() + i); for (int i = 0; i < 3; i++) { a += a[0]; a.erase(a.begin()); if (a == b) { puts( YES ); return 0; } } puts( NO ); return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2020 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module t (/*AUTOARG*/);
import "DPI-C" function void dpii_nullptr();
// verilator lint_off UNDRIVEN
int i_int_u3 [2:-2] [-3:3] [4:-4];
import "DPI-C" function void dpii_int_u3(input int i [] [] []);
real i_real_u1 [1:0];
import "DPI-C" function void dpii_real_u1(input real i []);
bit i_u6 [2][2][2][2][2][2];
import "DPI-C" function void dpii_bit_u6(input bit i [][][][][][]);
real i_real_u6 [2][2][2][2][2][2];
import "DPI-C" function void dpii_real_u6(input real i [][][][][][]);
initial begin
i_int_u3[0][0][0] = 32'hbad;
i_real_u1[0] = 1.1;
i_u6[0][0][0][0][0][0] = 1'b1;
dpii_nullptr();
dpii_int_u3(i_int_u3);
dpii_real_u1(i_real_u1);
dpii_bit_u6(i_u6);
dpii_real_u6(i_real_u6);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
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#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); const int N = 19; int g[N]; unsigned long long dp[1 << N][N + 1]; unsigned long long ok[1 << N]; unsigned long long slen[N + 1][1 << N]; unsigned long long cur[N + 1][1 << N]; unsigned long long val[1 << N]; unsigned long long ans[1 << N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { char c; cin >> c; if (c == 1 ) { g[i] |= (1 << j); } } } for (int i = 0; i < n; i++) { dp[1 << i][i] = 1; } for (int mask = 0; mask < (1 << n); mask++) { for (int i = 0; i < n; i++) { int cands = g[i] & (~mask); for (int j = 0; j < n; j++) { if ((cands >> j) & 1) { dp[mask | (1 << j)][j] += dp[mask][i]; } } ok[mask] += dp[mask][i]; } } for (int len = 1; len <= n; len++) { for (int mask = 0; mask < (1 << n); mask++) { if (__builtin_popcount(mask) == len) { slen[len][mask] += ok[mask]; } } for (int i = 0; i < n; i++) { for (int mask = 0; mask < (1 << n); mask++) { if ((mask >> i) & 1) { slen[len][mask] += slen[len][mask ^ (1 << i)]; } } } } map<vector<int>, vector<int> > ok; for (int mask = 0; mask < (1 << (n - 1)); mask++) { int x = 0; vector<int> t; while (x < n) { int len = 1; while ((mask >> x) & 1) { x++; len++; } t.push_back(len); x++; } sort(t.begin(), t.end()); ok[t].push_back(mask); } vector<int> a; for (int mask = 0; mask < (1 << n); mask++) val[mask] = 1; function<void(int, int)> f = [&](int s, int last) { if (s == n) { unsigned long long ret = 0; int x = (1 << n) - 1; for (int mask = 0; mask < (1 << n); mask++) { if (__builtin_popcount(mask) % 2 == 0) ret += val[x ^ mask]; else ret -= val[x ^ mask]; } for (auto c : ok[a]) { ans[c] += ret; } return; } if (s + last > n) { return; } for (int mask = 0; mask < (1 << n); mask++) { cur[s][mask] = val[mask]; } for (int i = last; s + i <= n; i++) { if (s + i != n && s + i + i > n) continue; a.push_back(i); for (int mask = 0; mask < (1 << n); mask++) { val[mask] *= slen[i][mask]; } f(s + i, i); for (int mask = 0; mask < (1 << n); mask++) { val[mask] = cur[s][mask]; } a.pop_back(); } }; f(0, 1); for (int i = 0; i < (n - 1); i++) { for (int mask = 0; mask < (1 << (n - 1)); mask++) { if (!((mask >> i) & 1)) { ans[mask] -= ans[mask + (1 << i)]; } } } for (int mask = 0; mask < (1 << (n - 1)); mask++) { cout << ans[mask] << ; } cout << endl; }
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// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "includes.v"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
//`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h00000035); //115200bps from 100 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, {24'h000000, char});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!testbench.uart0_int)
@(posedge testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h0, testbench.read_word);
$display("TASK: UART Read = %c @ %d", testbench.read_word, $time);
if (testbench.read_word != expected)
begin
$display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[7:0], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge testbench.CLK_IN);
end
endtask // uart_read_char
endmodule // uart_tasks
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_1_V
`define SKY130_FD_SC_HDLL__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_2_V
`define SKY130_FD_SC_LP__DLRBP_2_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_2_V
|
#include <bits/stdc++.h> using namespace std; int a[1000][1000]; int w, h; int fastMax(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ y; } int fastMin(int x, int y) { return (((y - x) >> (32 - 1)) & (x ^ y)) ^ x; } int main() { scanf( %d%d , &h, &w); for (int y = 0; y < h; y++) for (int x = 0; x < w; x++) scanf( %d , &a[y][x]); int ans = -1; for (int y1 = 0; y1 < h; y1++) for (int y2 = y1 + 1; y2 < h; y2++) { int m1 = -1, m2 = -1; for (int x = 0; x < w; x++) { const int v = fastMin(a[y1][x], a[y2][x]); if (m1 < v) { m2 = m1; m1 = v; } else if (m2 < v) { m2 = v; } } ans = fastMax(ans, m2); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int MOD = 1000000007; const long long int ll_MAX = 1e15; long long int fast_expo(long long int x, long long int p) { if (p == 0) return 1; else if (p % 2 == 0) { long long int t = fast_expo(x, p / 2) % MOD; return (t * t) % MOD; } else return (x * (fast_expo(x, p - 1)) % MOD) % MOD; } long long int invMod(long long int num) { return fast_expo(num, MOD - 2) % MOD; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int t_c; t_c = 1; for (long long int t_i = 0; t_i < t_c; ++t_i) { string str; cin >> str; long long int n = str.size(); long long int mini[27][n], maxi[27][n]; memset(mini, -1, sizeof(mini)); memset(maxi, -1, sizeof(maxi)); for (long long int k = 1; k < 27; ++k) { long long int cnt[26]{}, num = 0, j = 0; for (long long int i = 0; i < n; ++i) { while (j < n && num != k) { long long int pos = str[j] - a ; if (cnt[pos] == 0) { num++; } cnt[pos]++; j++; } if (num == k) mini[k][i] = j - 1; long long int pos = str[i] - a ; if (cnt[pos] == 1) { num--; } cnt[pos]--; } } for (long long int k = 1; k < 27; ++k) { long long int cnt[26]{}, num = 0, j = 0; for (long long int i = 0; i < n; ++i) { while (j < n && num != k + 1) { long long int pos = str[j] - a ; if (cnt[pos] == 0) { num++; } cnt[pos]++; j++; } if (num == k + 1) maxi[k][i] = j - 2; else if (num == k) maxi[k][i] = n - 1; long long int pos = str[i] - a ; if (cnt[pos] == 1) { num--; } cnt[pos]--; } } long long int ans[27]{}, num = 0; for (long long int k = 1; k < 27; ++k) { for (long long int i = 0; i < n; ++i) { if (mini[k][i] != -1) ans[k] += maxi[k][i] - mini[k][i] + 1; } if (ans[k] > 0) { num = k; } } cout << num << endl; for (long long int i = 1; i <= num; ++i) cout << ans[i] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> A; int F(int q, int w, int pr) { if (w - q <= 2) return w - q; int s = q; int g = 0; int ans = 2; while (s < w) { int f = s; int st = 1; while (st <= (A[s] - pr)) st <<= 1; st = pr + (st >> 1); while (f < w && (A[f] & st) == st) f++; ans = max(ans, F(s, f, st) + g + ((f == w) ? 0 : 1)); s = f; g++; } return ans; } int main() { int n; scanf( %d , &n); A.resize(n); for (int i = 0; i < n; i++) scanf( %d , &A[i]); sort(A.begin(), A.end()); reverse(A.begin(), A.end()); printf( %d n , n - F(0, n, 0)); return 0; }
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#include <bits/stdc++.h> const int INF = 1e9 + 7; int ds[100]; int hs[100]; int solve() { int N, X; scanf( %d %d , &N, &X); for (int i = 0; i < N; i++) { scanf( %d %d , &ds[i], &hs[i]); } int last = *std::max_element(ds, ds + N); if (last >= X) return 1; int dec = 0; for (int i = 0; i < N; i++) { dec = std::max(dec, ds[i] - hs[i]); } if (dec == 0) return -1; return (X - last + dec - 1) / dec + 1; } int main() { int T; scanf( %d , &T); while (T--) { printf( %d n , solve()); } }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using pil = pair<int, ll>; using pli = pair<ll, int>; using pll = pair<ll, ll>; const ll MOD = 1e9 + 7; const int inf = (1 << 30) - 1; const ll INF = (1LL << 60) - 1; const ld EPS = 1e-10; template <typename T> bool chmax(T &x, const T &y) { return (x < y) ? (x = y, true) : false; }; template <typename T> bool chmin(T &x, const T &y) { return (x > y) ? (x = y, true) : false; }; int main() { int T; cin >> T; while (T--) { int N, K, L; cin >> N >> K >> L; int d[N]; for (int i = 0; i < N; i++) { cin >> d[i]; d[i] = L - d[i]; } int pos = -inf; bool ans = true; for (int i = 0; i < N; i++) { if (d[i] < 0) { ans = false; break; } else if (d[i] >= K) pos = -inf; else if (pos == -inf) pos = -d[i]; else if (d[i] <= pos) { ans = false; break; } else if (pos < -d[i]) pos = -d[i]; else pos++; } cout << (ans ? Yes : No ) << endl; } }
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#include <bits/stdc++.h> using namespace std; int a, c, d[205], f, n, b, x, i; string s, s1, s11, s12; char i1, i2, j; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> s1; b = s1.size(); c = c + b; s = s + % ; s = s + s1; } c = c + n - 1; for (i1 = a ; i1 <= z ; i1++) { s1 = i1; x = s.find(s1); if (x == -1) { cout << s1; return 0; } } for (i1 = a ; i1 <= z ; i1++) { for (i2 = a ; i2 <= z ; i2++) { s11 = i1; s12 = i2; s1 = s11 + s12; x = s.find(s1); if (x == -1) { cout << s1; return 0; } } } }
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//////////////////////////////////////////////////////////////////
// //
// Main memory for simulations. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Non-synthesizable main memory. Holds 128MBytes //
// The memory path in this module is purely combinational. //
// Addresses and write_cmd_req data are registered as //
// the leave the execute module and read data is registered //
// as it enters the instruction_decode module. //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module main_mem#(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
input i_clk,
input i_mem_ctrl, // 0=128MB, 1=32MB
// Wishbone Bus
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
`include "memory_configuration.v"
reg [127:0] ram [2**(MAIN_MSB-2)-1:0];
wire start_write;
wire start_read;
reg start_read_d1;
reg start_read_d2;
wire [127:0] rd_data;
wire [127:0] masked_wdata;
reg wr_en = 'd0;
reg [15:0] wr_mask = 'd0;
reg [127:0] wr_data = 'd0;
reg [27:0] addr_d1 = 'd0;
wire busy;
genvar i;
assign start_write = i_wb_stb && i_wb_we && !busy;
assign start_read = i_wb_stb && !i_wb_we && !busy;
assign busy = start_read_d1 || start_read_d2;
assign o_wb_err = 'd0;
generate
if (WB_DWIDTH == 128)
begin : wb128
reg [127:0] wb_rdata128 = 'd0;
// ------------------------------------------------------
// Write for 32-bit wishbone
// ------------------------------------------------------
always @( posedge i_clk )
begin
wr_en <= start_write;
wr_mask <= ~ i_wb_sel;
wr_data <= i_wb_dat;
// Wrap the address at 32 MB, or full width
addr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
if ( wr_en )
ram [addr_d1[27:2]] <= masked_wdata;
end
for (i=0;i<16;i=i+1) begin : masked
assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
end
// ------------------------------------------------------
// Read for 32-bit wishbone
// ------------------------------------------------------
assign rd_data = ram [addr_d1[27:2]];
always @( posedge i_clk )
begin
start_read_d1 <= start_read;
start_read_d2 <= start_read_d1;
if ( start_read_d1 )
begin
wb_rdata128 <= rd_data;
end
end
assign o_wb_dat = wb_rdata128 ;
assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
end
else
begin : wb32
reg [31:0] wb_rdata32 = 'd0;
// ------------------------------------------------------
// Write for 32-bit wishbone
// ------------------------------------------------------
always @( posedge i_clk )
begin
wr_en <= start_write;
wr_mask <= i_wb_adr[3:2] == 2'd0 ? { 12'hfff, ~i_wb_sel } :
i_wb_adr[3:2] == 2'd1 ? { 8'hff, ~i_wb_sel, 4'hf } :
i_wb_adr[3:2] == 2'd2 ? { 4'hf, ~i_wb_sel, 8'hff } :
{ ~i_wb_sel, 12'hfff } ;
wr_data <= {4{i_wb_dat}};
// Wrap the address at 32 MB, or full width
addr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:2]} : i_wb_adr[29:2];
if ( wr_en )
begin
ram [addr_d1[27:2]] <= masked_wdata;
`ifdef AMBER_MEMIF_DEBUG
$write("%09d ", `U_TB.clk_count);
$display("Main memory write: address %h, data %h, be %d%d%d%d",
{2'd0, addr_d1, 2'd0}, wr_data[31:0],
~wr_mask[addr_d1[1:0]*4+3],
~wr_mask[addr_d1[1:0]*4+2],
~wr_mask[addr_d1[1:0]*4+1],
~wr_mask[addr_d1[1:0]*4+0] );
`endif
end
end
for (i=0;i<16;i=i+1) begin : masked
assign masked_wdata[8*i+7:8*i] = wr_mask[i] ? rd_data[8*i+7:8*i] : wr_data[8*i+7:8*i];
end
// ------------------------------------------------------
// Read for 32-bit wishbone
// ------------------------------------------------------
assign rd_data = ram [addr_d1[27:2]];
always @( posedge i_clk )
begin
start_read_d1 <= start_read;
start_read_d2 <= start_read_d1;
if ( start_read_d1 )
begin
wb_rdata32 <= addr_d1[1:0] == 2'd0 ? rd_data[ 31: 0] :
addr_d1[1:0] == 2'd1 ? rd_data[ 63:32] :
addr_d1[1:0] == 2'd2 ? rd_data[ 95:64] :
rd_data[127:96] ;
end
end
assign o_wb_dat = wb_rdata32 ;
assign o_wb_ack = i_wb_stb && ( start_write || start_read_d2 );
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, in[100010], sum1, sum2; int main() { cin >> n >> m; for (int i = 1; i <= m; i++) { int x, y; cin >> x >> y; in[x]++; in[y]++; } for (int i = 1; i <= n + 1; i++) if (in[i] == 1) sum1++; else if (in[i] == 2) sum2++; if (sum1 == 2 && sum2 == n - 2) { cout << bus topology ; return 0; } sum1 = sum2 = 0; for (int i = 1; i <= n; i++) if (in[i] == 2) sum1++; if (sum1 == n) { cout << ring topology ; return 0; } sum1 = sum2 = 0; for (int i = 1; i <= n + 1; i++) if (in[i] == 1) sum1++; else if (in[i] == n - 1) sum2++; if (sum1 == n - 1 && sum2 == 1) { cout << star topology ; return 0; } cout << unknown topology ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_TB_V
`define SKY130_FD_SC_HD__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_TB_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_double_ll (
clock,
resetn,
dataa,
datab,
result,
enable);
input enable;
input clock, resetn;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
// Latency 10
acl_fp_custom_add_core_double core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.HIGH_LATENCY = 0;
defparam core.ROUNDING_MODE = 0;
endmodule
|
module axi_slave_stub(
output S2M_AXI_ACLK,
// Read interface
input S2M_AXI_ARVALID,
output S2M_AXI_ARREADY,
input [31:0] S2M_AXI_ARADDR,
input [11:0] S2M_AXI_ARID,
output S2M_AXI_RVALID,
input S2M_AXI_RREADY,
output S2M_AXI_RLAST,
output [31:0] S2M_AXI_RDATA,
output [11:0] S2M_AXI_RID,
output [1:0] S2M_AXI_RRESP,
//write interface
input S2M_AXI_AWVALID,
output S2M_AXI_AWREADY,
input [31:0] S2M_AXI_AWADDR,
input [11:0] S2M_AXI_AWID,
input S2M_AXI_WVALID,
output S2M_AXI_WREADY,
input [31:0] S2M_AXI_WDATA,
input [3:0] S2M_AXI_WSTRB,
output S2M_AXI_BVALID,
input S2M_AXI_BREADY,
output [1:0] S2M_AXI_BRESP,
output [11:0] S2M_AXI_BID
);
assign S2M_AXI_ACLK = 1'b0;
// Read interface
assign S2M_AXI_ARREADY = 1'b0;
assign S2M_AXI_RVALID = 1'b0;
assign S2M_AXI_RLAST = 1'b0;
assign S2M_AXI_RDATA = 32'b0;
assign S2M_AXI_RID = 12'b0;
assign S2M_AXI_RRESP = 2'b0;
//write interface
assign S2M_AXI_AWREADY = 1'b0;
assign S2M_AXI_WREADY = 1'b0;
assign S2M_AXI_BVALID = 1'b0;
assign S2M_AXI_BRESP = 2'b0;
assign S2M_AXI_BID = 12'b0;
endmodule : axi_slave_stub
/*
axi_slave_stub axi_slave_XXX_stub(
.S2M_AXI_ACLK\(S2M_XXX_AXI_ACLK),
// Read interface
.S2M_AXI_ARVALID(S2M_XXX_AXI_ARVALID),
.S2M_AXI_ARREADY(S2M_XXX_AXI_ARREADY),
.S2M_AXI_ARADDR(S2M_XXX_AXI_ARADDR[31:0]),
.S2M_AXI_ARID(S2M_XXX_AXI_ARID[11:0]),
.S2M_AXI_RVALID(S2M_XXX_AXI_RVALID),
.S2M_AXI_RREADY(S2M_XXX_AXI_RREADY),
.S2M_AXI_RLAST(S2M_XXX_AXI_RLAST),
.S2M_AXI_RDATA(S2M_XXX_AXI_RDATA[31:0]),
.S2M_AXI_RID(S2M_XXX_AXI_RID[11:0]),
.S2M_AXI_RRESP(S2M_XXX_AXI_RRESP[1:0]),
//write interface
.S2M_AXI_AWVALID(S2M_XXX_AXI_AWVALID),
.S2M_AXI_AWREADY(S2M_XXX_AXI_AWREADY),
.S2M_AXI_AWADDR(S2M_XXX_AXI_AWADDR[31:0]),
.S2M_AXI_AWID(S2M_XXX_AXI_AWID[11:0]),
.S2M_AXI_WVALID(S2M_XXX_AXI_WVALID),
.S2M_AXI_WREADY(S2M_XXX_AXI_WREADY),
.S2M_AXI_WDATA(S2M_XXX_AXI_WDATA[31:0]),
.S2M_AXI_WSTRB(S2M_XXX_AXI_WSTRB[3:0]),
.S2M_AXI_BVALID(S2M_XXX_AXI_BVALID),
.S2M_AXI_BREADY(S2M_XXX_AXI_BREADY),
.S2M_AXI_BRESP(S2M_XXX_AXI_BRESP[1:0]),
.S2M_AXI_BID(S2M_XXX_AXI_BID[11:0])
);
*/
|
#include <bits/stdc++.h> void print(int n) { if (n == 4) { printf( 1 * 2 = 2 n ); printf( 3 * 4 = 12 n ); printf( 2 * 12 = 24 n ); } else if (n == 5) { printf( 5 * 4 = 20 n ); printf( 3 + 2 = 5 n ); printf( 5 - 1 = 4 n ); printf( 20 + 4 = 24 n ); } } int main() { int n; while (~scanf( %d , &n)) { if (n <= 3) { printf( NO n ); continue; } printf( YES n ); if (n == 4) print(4); else if (n == 5) print(5); else if (n % 2) { print(5); for (int i = n; i > 5; i = i - 2) { printf( %d - %d = 1 n , i, i - 1); printf( 24 * 1 = 24 n ); } } else { print(4); for (int i = n; i > 4; i = i - 2) { printf( %d - %d = 1 n , i, i - 1); printf( 24 * 1 = 24 n ); } } } return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_adl5904_rst (
input sys_cpu_clk,
input rf_peak_det_n,
output rf_peak_rst);
// internal registers
reg rf_peak_det_n_d = 'd0;
reg rf_peak_det_enb_d = 'd0;
reg rf_peak_rst_enb = 'd0;
reg rf_peak_rst_int = 'd0;
// internal signals
wire rf_peak_det_enb_s;
wire rf_peak_rst_1_s;
wire rf_peak_rst_0_s;
// adl5904 input protection
assign rf_peak_rst = rf_peak_rst_int;
assign rf_peak_det_enb_s = ~(rf_peak_det_n_d & rf_peak_det_n);
assign rf_peak_rst_1_s = ~rf_peak_det_enb_d & rf_peak_det_enb_s;
assign rf_peak_rst_0_s = rf_peak_det_enb_d & ~rf_peak_det_enb_s;
always @(posedge sys_cpu_clk) begin
rf_peak_det_n_d <= rf_peak_det_n;
rf_peak_det_enb_d <= rf_peak_det_enb_s;
if (rf_peak_rst_1_s == 1'b1) begin
rf_peak_rst_enb <= 1'b1;
end else if (rf_peak_rst_0_s == 1'b1) begin
rf_peak_rst_enb <= 1'b0;
end
rf_peak_rst_int = ~rf_peak_rst_int & rf_peak_rst_enb;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long a[200020]; long long va[200020]; long long b[200020]; long long c[200020]; char ans[200020]; char ansstring[200020]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; va[a[i]] = i; } for (int i = 1; i <= n; i++) { cin >> b[i]; c[i] = va[b[i]]; } char ch = a ; for (int i = 1; i <= n; i++) { long long reach = c[i]; if (ch > z ) { ch--; } for (int j = i; j <= reach; j++) { reach = max(reach, c[j]); ans[j] = ch; } i = reach; ch++; } if (ch - a < k) { cout << NO ; return 0; } for (int i = 1; i <= n; i++) { ansstring[b[i]] = ans[i]; } cout << YES n ; for (int i = 1; i <= n; i++) { cout << ansstring[i]; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m, xx; cin >> n >> m >> xx; map<char, long long int> mp; vector<char> v[n]; for (long long int i = 0; i < n; i++) { string s; cin >> s; for (auto j : s) v[i].push_back(j); for (long long int j = 0; j < m; j++) mp[s[j]]++; } if (mp[ S ] > 0) { mp[ S ] = 0; for (auto i : mp) { char c = i.first - 32; if (i.first != S ) mp[c]++; } } long long int q; cin >> q; string s; cin >> s; for (long long int i = 0; i < q; i++) { if (mp[s[i]] == 0) { cout << -1 ; return 0; } } vector<pair<long long int, long long int>> shift; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { if (v[i][j] == S ) shift.push_back({i, j}); } } vector<long long int> chk[200]; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < m; j++) { for (auto m : shift) { long long int x = m.first; long long int y = m.second; long long int ans = ((x - i) * (x - i)) + ((y - j) * (y - j)); if (ans <= (xx * xx)) chk[v[i][j] - 32].push_back(ans); } } } long long int c = 0; for (long long int i = 0; i < q; i++) { if (s[i] >= A && s[i] <= Z ) { for (auto j : chk[s[i]]) { if (j <= (xx * xx)) goto done; } c++; } done: 1; } cout << c; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const long long mod = 1e9 + 7; const int inf = 1 << 30; const int maxn = 600500; const double EPS = 1e-7; void solve() { int q; scanf( %d , &q); while (q--) { long long n; scanf( %lld , &n); int a, b; scanf( %d%d , &a, &b); if (b < 2LL * a) { printf( %lld n , (n / 2LL) * 1LL * b + a * (n % 2)); } else printf( %lld n , a * 1LL * n); } } int main() { int tc = 1; for (int tt = 0; tt < (int)(tc); ++tt) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int n, a, b, k; long long MOD = 1000000007; long long pref[5005][2], dp[5005][2]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> a >> b >> k; for (int i = 0; i < n + 5; i++) { pref[i][0] = pref[i][1] = dp[i][0] = dp[i][1] = 0; } if (b < a) { a = n + 1 - a; b = n + 1 - b; } dp[a][0] = 1; for (int i = a; i < b; i++) pref[i][0] = 1; for (int j = 1; j <= k; j++) { for (int i = 1; i < b; i++) { dp[i][j % 2] = (pref[(b + i - 1) / 2][(j - 1) % 2] - dp[i][(j - 1) % 2] + MOD) % MOD; pref[i][j % 2] = (pref[i - 1][j % 2] + dp[i][j % 2]) % MOD; } } cout << pref[b - 1][k % 2] << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
typedef integer q_t[$];
initial begin
q_t iq;
iq.push_back(42);
end
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
// Very simple test using bit
bit q[$];
bit x;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 1);
// $bits is unsupported in several other simulators, see bug1646
// Unsup: `checkh($bits(q), 0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 0);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), 0);
`checkh($size(q), 1);
`checkh($dimensions(q), 1);
// Unsup: `checkh($bits(q), 2);
`checkh(q.size(), 1);
q.push_back(1'b1);
q.push_back(1'b0);
q.push_back(1'b1);
`checkh($left(q), 0);
`checkh($right(q), 3);
`checkh($low(q), 0);
`checkh($high(q), 3);
`checkh($size(q), 4);
// Unsup: `checkh($bits(q), 4);
`checkh(q.size(), 4);
x = q.pop_back(); `checkh(x, 1'b1);
`checkh($left(q), 0);
`checkh($right(q), 2);
`checkh($low(q), 0);
`checkh($high(q), 2);
`checkh($size(q), 3);
// sure those are working now..
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b1);
x = q.pop_front(); `checkh(x, 1'b0);
`checkh(q.size(), 0);
end
begin
// Simple test using integer
typedef bit [3:0] nibble_t;
nibble_t q[$];
nibble_t v;
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
i = q.size(); `checkh(i, 0);
q.push_back(4'd1); // 1
q.push_front(4'd2); // 2 1
q.push_back(4'd3); // 2 1 3
i = q.size; `checkh(i, 3); // Also checks no parens
end
begin
// Strings
string q[$];
string v;
int j = 0;
// Empty queue checks
`checkh($left(q), 0);
`checkh($right(q), -1);
`checkh($increment(q), -1);
`checkh($low(q), 0);
`checkh($high(q), -1);
`checkh($size(q), 0);
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
q.push_front("f1");
//Unsup: `checkh($bits(q), 16);
q.push_back("b1");
q.push_front("f2");
q.push_back("b2");
i = q.size(); `checkh(i, 4);
v = q[0]; `checks(v, "f2");
v = q[1]; `checks(v, "f1");
v = q[2]; `checks(v, "b1");
v = q[3]; `checks(v, "b2");
v = q[4]; `checks(v, "");
//Unsup: `checkh(q[$], "b2");
v = $sformatf("%p", q); `checks(v, "'{\"f2\", \"f1\", \"b1\", \"b2\"} ");
//Unsup: q.delete(1);
//Unsup: v = q[1]; `checks(v, "b1");
//Unsup: q.insert(0, "ins0");
//Unsup: q.insert(3, "ins3");
//v = q[0]; `checks(v, "ins0");
//v = q[3]; `checks(v, "ins3");
foreach (q[i]) begin
j++;
v = q[i];
if (i == 0) `checks(v, "f2");
if (i == 1) `checks(v, "f1");
if (i == 2) `checks(v, "b1");
if (i == 3) `checks(v, "b2");
end
`checkh(j,4);
q.pop_front();
v = q.pop_front(); `checks(v, "f1");
v = q.pop_back(); `checks(v, "b2");
v = q.pop_back(); `checks(v, "b1");
i = q.size(); `checkh(i, 0);
// Empty queue, this should be 0
foreach (q[i]) begin
j++;
end
`checkh(j,4);
q.push_front("non-empty");
i = q.size(); `checkh(i, 1);
q.delete();
i = q.size(); `checkh(i, 0);
v = q.pop_front(); `checks(v, ""); // Was empty, optional warning
v = q.pop_back(); `checks(v, ""); // Was empty, optional warning
// Conversion of insert/delete with zero to operator
q.push_front("front");
q.insert(0, "newfront");
i = q.size(); `checkh(i, 2);
q.delete(0);
i = q.size(); `checkh(i, 1);
`checks(q[0], "front");
//Unsup: `checks(q[$], "front");
end
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction q[$];
`checkh($dimensions(q), 2);
//Unsup: `checkh($bits(q), 0);
end
// testing a wide queue
begin
typedef struct packed {
bit [7:0] opcode;
bit [23:0] addr;
bit [127:0] data;
} instructionW; // named structure type
instructionW inst_push;
instructionW inst_pop;
instructionW q[$];
`checkh($dimensions(q), 2);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
inst_push.opcode = 1;
inst_push.addr = 42;
inst_push.data = {4{32'hdeadbeef}};
q.push_back(inst_push);
`checkh(q[0].opcode, 1);
`checkh(q[0].addr, 42);
`checkh(q[0].data, {4{32'hdeadbeef}});
inst_pop = q.pop_front();
`checkh(inst_pop.opcode, 1);
`checkh(inst_pop.addr, 42);
`checkh(inst_pop.data, {4{32'hdeadbeef}});
`checkh(q.size(), 0);
`checkh(q[0].opcode, 0);
`checkh(q[0].addr, 0);
`checkh(q[0].data, 0);
end
/* Unsup:
begin
int q[4][$];
q[0].push_back(0);
q[0].push_back(1);
q[1].push_back(2);
q[2].push_back(3);
end
*/
// See t_queue_unsup_bad for more unsupported stuff
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:29:32 03/26/2014
// Design Name:
// Module Name: mul
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mul(/*AUTOARG*/
// Outputs
data_c,
// Inputs
data_a, data_b, sign
);
input [31:0] data_a, data_b;
input sign;
output [63:0] data_c;
wire [63:0] tmp_data_a, tmp_data_c, tmp_data_cu;
reg [31:0] tmp_data_b;
reg [4:0] i;
/*AUTOWIRE*/
/*AUTOREG*/
/*
always @ * begin
tmp_data_a = ({32'h00000000, data_a});
tmp_data_b = data_b;
tmp_data_c = 0;
for (i=0; i<5'b10000; i=i+1) begin
if ((tmp_data_b & 1) == 1)
tmp_data_c = tmp_data_c + tmp_data_a;
tmp_data_a = tmp_data_a << 1;
tmp_data_b = tmp_data_b >> 1;
end
end // always @ *
*/
wire [31:0] ab0 = data_b[0] ? data_a : 32'b0;
wire [31:0] ab1 = data_b[1] ? data_a : 32'b0;
wire [31:0] ab2 = data_b[2] ? data_a : 32'b0;
wire [31:0] ab3 = data_b[3] ? data_a : 32'b0;
wire [31:0] ab4 = data_b[4] ? data_a : 32'b0;
wire [31:0] ab5 = data_b[5] ? data_a : 32'b0;
wire [31:0] ab6 = data_b[6] ? data_a : 32'b0;
wire [31:0] ab7 = data_b[7] ? data_a : 32'b0;
wire [31:0] ab8 = data_b[8] ? data_a : 32'b0;
wire [31:0] ab9 = data_b[9] ? data_a : 32'b0;
wire [31:0] ab10 = data_b[10] ? data_a : 32'b0;
wire [31:0] ab11 = data_b[11] ? data_a : 32'b0;
wire [31:0] ab12 = data_b[12] ? data_a : 32'b0;
wire [31:0] ab13 = data_b[13] ? data_a : 32'b0;
wire [31:0] ab14 = data_b[14] ? data_a : 32'b0;
wire [31:0] ab15 = data_b[15] ? data_a : 32'b0;
wire [31:0] ab16 = data_b[16] ? data_a : 32'b0;
wire [31:0] ab17 = data_b[17] ? data_a : 32'b0;
wire [31:0] ab18 = data_b[18] ? data_a : 32'b0;
wire [31:0] ab19 = data_b[19] ? data_a : 32'b0;
wire [31:0] ab20 = data_b[20] ? data_a : 32'b0;
wire [31:0] ab21 = data_b[21] ? data_a : 32'b0;
wire [31:0] ab22 = data_b[22] ? data_a : 32'b0;
wire [31:0] ab23 = data_b[23] ? data_a : 32'b0;
wire [31:0] ab24 = data_b[24] ? data_a : 32'b0;
wire [31:0] ab25 = data_b[25] ? data_a : 32'b0;
wire [31:0] ab26 = data_b[26] ? data_a : 32'b0;
wire [31:0] ab27 = data_b[27] ? data_a : 32'b0;
wire [31:0] ab28 = data_b[28] ? data_a : 32'b0;
wire [31:0] ab29 = data_b[29] ? data_a : 32'b0;
wire [31:0] ab30 = data_b[30] ? data_a : 32'b0;
wire [31:0] ab31 = data_b[31] ? data_a : 32'b0;
assign tmp_data_cu = (((({32'b0, ab0[31:0]} +
{31'b0, ab1[31:0], 1'b0}) +
({30'b0, ab2[31:0], 2'b0} +
{29'b0, ab3[31:0], 3'b0})) +
(({28'b0, ab4[31:0], 4'b0} +
{27'b0, ab5[31:0], 5'b0}) +
({26'b0, ab6[31:0], 6'b0} +
{25'b0, ab7[31:0], 7'b0}))) +
((({24'b0, ab8[31:0], 8'b0} +
{23'b0, ab9[31:0], 9'b0}) +
({22'b0, ab10[31:0], 10'b0} +
{21'b0, ab11[31:0], 11'b0})) +
(({20'b0, ab12[31:0], 12'b0} +
{19'b0, ab13[31:0], 13'b0}) +
({18'b0, ab14[31:0], 14'b0} +
{17'b0, ab15[31:0], 15'b0})))) +
(((({16'b0, ab16[31:0], 16'b0} +
{15'b0, ab17[31:0], 17'b0}) +
({14'b0, ab18[31:0], 18'b0} +
{13'b0, ab19[31:0], 19'b0})) +
(({12'b0, ab20[31:0], 20'b0} +
{11'b0, ab21[31:0], 21'b0}) +
({10'b0, ab22[31:0], 22'b0} +
{ 9'b0, ab23[31:0], 23'b0})))+
((({ 8'b0, ab24[31:0], 24'b0} +
{ 7'b0, ab25[31:0], 25'b0}) +
({ 6'b0, ab26[31:0], 26'b0} +
{ 5'b0, ab27[31:0], 27'b0})) +
(({ 4'b0, ab28[31:0], 28'b0} +
{ 3'b0, ab29[31:0], 29'b0}) +
({ 2'b0, ab30[31:0], 30'b0} +
{ 1'b0, ab31[31:0], 31'b0}))));
assign tmp_data_c = (((({32'b1, ~ab0[31], ab0[30:0]} +
{31'b0, ~ab1[31], ab1[30:0], 1'b0}) +
({30'b0, ~ab2[31], ab2[30:0], 2'b0} +
{29'b0, ~ab3[31], ab3[30:0], 3'b0})) +
(({28'b0, ~ab4[31], ab4[30:0], 4'b0} +
{27'b0, ~ab5[31], ab5[30:0], 5'b0}) +
({26'b0, ~ab6[31], ab6[30:0], 6'b0} +
{25'b0, ~ab7[31], ab7[30:0], 7'b0}))) +
((({24'b0, ~ab8[31], ab8[30:0], 8'b0} +
{23'b0, ~ab9[31], ab9[30:0], 9'b0}) +
({22'b0, ~ab10[31], ab10[30:0], 10'b0} +
{21'b0, ~ab11[31], ab11[30:0], 11'b0})) +
(({20'b0, ~ab12[31], ab12[30:0], 12'b0} +
{19'b0, ~ab13[31], ab13[30:0], 13'b0}) +
({18'b0, ~ab14[31], ab14[30:0], 14'b0} +
{17'b0, ~ab15[31], ab15[30:0], 15'b0})))) +
(((({16'b0, ~ab16[31], ab16[30:0], 16'b0} +
{15'b0, ~ab17[31], ab17[30:0], 17'b0}) +
({14'b0, ~ab18[31], ab18[30:0], 18'b0} +
{13'b0, ~ab19[31], ab19[30:0], 19'b0})) +
(({12'b0, ~ab20[31], ab20[30:0], 20'b0} +
{11'b0, ~ab21[31], ab21[30:0], 21'b0}) +
({10'b0, ~ab22[31], ab22[30:0], 22'b0} +
{ 9'b0, ~ab23[31], ab23[30:0], 23'b0})))+
((({ 8'b0, ~ab24[31], ab24[30:0], 24'b0} +
{ 7'b0, ~ab25[31], ab25[30:0], 25'b0}) +
({ 6'b0, ~ab26[31], ab26[30:0], 26'b0} +
{ 5'b0, ~ab27[31], ab27[30:0], 27'b0})) +
(({ 4'b0, ~ab28[31], ab28[30:0], 28'b0} +
{ 3'b0, ~ab29[31], ab29[30:0], 29'b0}) +
({ 2'b0, ~ab30[31], ab30[30:0], 30'b0} +
{ 1'b1, ab31[31], ~ab31[30:0], 31'b0}))));
assign data_c = sign ? tmp_data_c : tmp_data_cu;
endmodule
|
#include <bits/stdc++.h> using namespace std; string simplify(string s) { string a; for (int i = 0; i < s.length(); i++) { if (isalpha(s[i])) { s[i] = tolower(s[i]); a.push_back(s[i]); } } return a; } int main() { ios::sync_with_stdio(0); cin.tie(NULL); string s1, s2, s3; cin >> s1 >> s2 >> s3; s1 = simplify(s1); s2 = simplify(s2); s3 = simplify(s3); int x = s1.length(), y = s2.length(), z = s3.length(); int n; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; s = simplify(s); if (s.length() == x + y + z && (s == s1 + s2 + s3 || s == s1 + s3 + s2 || s == s2 + s1 + s3 || s == s2 + s3 + s1 || s == s3 + s1 + s2 || s == s3 + s2 + s1)) cout << ACC n ; else cout << WA n ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [15:-16] sel2 = crc[31:0];
wire [80:-10] sel3 = {crc[26:0],crc};
wire [3:0] out21 = sel2[-3 : -6];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4];
wire [3:0] out31 = sel3[-3 : -6];
wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4];
wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33};
reg [15:-16] sel1;
initial begin
// Path clearing
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[-13 : -16] != 4'h8) $stop;
if (sel1[3:0] != 4'h4) $stop;
if (sel1[4 +: 4] != 4'h3) $stop;
if (sel1[11 -: 4] != 4'h2) $stop;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x %x,%x,%x\n", $time, out21,out22,out23, out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hba7fe1e7ac128362
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2 * 1e6; int a[N]; int main() { std::ios::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; ++i) { int tmp; cin >> tmp; a[tmp]++; } int res = 0; for (int i = 0; i < N; ++i) { if (a[i] % 2) ++res; a[i + 1] += (a[i] / 2); } cout << res << endl; return 0; }
|
/**
* bsg_nonsynth_non_blocking_dma_model.v
*
* There is nothing non-blocking about the DMA model,
* Rather this is only to be used with bsg_cache_non_blocking.
*
*/
module bsg_nonsynth_non_blocking_dma_model
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter read_delay_p=16
,parameter write_delay_p=16
,parameter dma_req_delay_p=16
,parameter dma_data_delay_p=16
,parameter data_mask_width_lp=(data_width_p>>3)
,parameter lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp)
,parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p)
,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
,parameter dma_pkt_width_lp=`bsg_cache_non_blocking_dma_pkt_width(addr_width_p)
)
(
input clk_i
,input reset_i
,input [dma_pkt_width_lp-1:0] dma_pkt_i
,input logic dma_pkt_v_i
,output logic dma_pkt_yumi_o
,output logic [data_width_p-1:0] dma_data_o
,output logic dma_data_v_o
,input dma_data_ready_i
,input [data_width_p-1:0] dma_data_i
,input dma_data_v_i
,output logic dma_data_yumi_o
);
logic [data_width_p-1:0] mem [els_p-1:0];
`declare_bsg_cache_non_blocking_dma_pkt_s(addr_width_p);
bsg_cache_non_blocking_dma_pkt_s dma_pkt;
assign dma_pkt = dma_pkt_i;
typedef enum logic [1:0] {
WAIT
,DELAY
,BUSY
} state_e;
wire start_read = ~dma_pkt.write_not_read & dma_pkt_v_i;
wire start_write = dma_pkt.write_not_read & dma_pkt_v_i;
// read channel
//
logic [addr_width_p-1:0] rd_addr_r, rd_addr_n;
state_e rd_state_r, rd_state_n;
logic [lg_block_size_in_words_lp-1:0] rd_counter_r, rd_counter_n;
integer rd_delay_r, rd_delay_n;
integer rd_data_delay_r, rd_data_delay_n;
wire rd_data_delay_zero = (rd_data_delay_r == 0);
integer rd_req_delay_r, rd_req_delay_n;
wire rd_req_delay_zero = rd_req_delay_r == 0;
logic rd_req_ready;
logic [lg_els_lp-lg_block_size_in_words_lp-1:0] rd_upper_addr;
assign rd_upper_addr = rd_addr_r[lg_data_mask_width_lp+lg_block_size_in_words_lp+:lg_els_lp-lg_block_size_in_words_lp];
assign dma_data_o = mem[{rd_upper_addr, rd_counter_r}];
always_comb begin
dma_data_v_o = 1'b0;
rd_addr_n = rd_addr_r;
rd_counter_n = rd_counter_r;
rd_delay_n = rd_delay_r;
rd_data_delay_n = rd_data_delay_r;
rd_req_delay_n = rd_req_delay_r;
rd_req_ready = 1'b0;
case (rd_state_r)
WAIT: begin
rd_req_ready = start_read & rd_req_delay_zero;
rd_req_delay_n = start_read
? (rd_req_delay_zero
? $urandom_range(dma_req_delay_p,0)
: rd_req_delay_r - 1)
: rd_req_delay_r;
rd_addr_n = start_read & rd_req_delay_zero
? dma_pkt.addr
: rd_addr_r;
rd_counter_n = start_read & rd_req_delay_zero
? '0
: rd_counter_r;
rd_state_n = start_read & rd_req_delay_zero
? DELAY
: WAIT;
rd_delay_n = start_read & rd_req_delay_zero
? $urandom_range(dma_data_delay_p, 0)
: rd_delay_r;
end
DELAY: begin
rd_delay_n = rd_delay_r - 1;
rd_state_n = rd_delay_r == 0
? BUSY
: DELAY;
rd_data_delay_n = (rd_delay_r == 0)
? $urandom_range(dma_data_delay_p, 0)
: rd_data_delay_r;
end
BUSY: begin
rd_data_delay_n = rd_data_delay_zero
? (dma_data_ready_i ? $urandom_range(dma_data_delay_p, 0) : 0)
: rd_data_delay_r - 1;
dma_data_v_o = rd_data_delay_zero;
rd_counter_n = rd_data_delay_zero & dma_data_ready_i
? rd_counter_r + 1
: rd_counter_r;
rd_state_n = rd_data_delay_zero & dma_data_ready_i & (rd_counter_r == block_size_in_words_p-1)
? WAIT
: BUSY;
end
endcase
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
rd_state_r <= WAIT;
rd_addr_r <= '0;
rd_counter_r <= '0;
rd_delay_r <= '0;
rd_data_delay_r <= '0;
rd_req_delay_r <= '0;
end
else begin
rd_state_r <= rd_state_n;
rd_addr_r <= rd_addr_n;
rd_counter_r <= rd_counter_n;
rd_delay_r <= rd_delay_n;
rd_data_delay_r <= rd_data_delay_n;
rd_req_delay_r <= rd_req_delay_n;
end
end
// write channel
//
logic [addr_width_p-1:0] wr_addr_r, wr_addr_n;
state_e wr_state_r, wr_state_n;
logic [lg_block_size_in_words_lp-1:0] wr_counter_r, wr_counter_n;
integer wr_delay_r, wr_delay_n;
integer wr_data_delay_r, wr_data_delay_n;
wire wr_data_delay_zero = wr_data_delay_r == 0;
integer wr_req_delay_r, wr_req_delay_n;
wire wr_req_delay_zero = wr_req_delay_r == 0;
logic wr_req_ready;
logic [lg_els_lp-lg_block_size_in_words_lp-1:0] wr_upper_addr;
assign wr_upper_addr = wr_addr_r[lg_data_mask_width_lp+lg_block_size_in_words_lp+:lg_els_lp-lg_block_size_in_words_lp];
always_comb begin
wr_addr_n = wr_addr_r;
wr_data_delay_n = wr_data_delay_r;
wr_req_delay_n = wr_req_delay_r;
wr_req_ready = 1'b0;
dma_data_yumi_o = 1'b0;
case (wr_state_r)
WAIT: begin
wr_req_ready = start_write & wr_req_delay_zero;
wr_req_delay_n = start_write
? (wr_req_delay_zero
? $urandom_range(dma_req_delay_p,0)
: wr_req_delay_r - 1)
: wr_req_delay_r;
wr_addr_n = start_write & wr_req_delay_zero
? dma_pkt.addr
: wr_addr_r;
wr_counter_n = start_write & wr_req_delay_zero
? '0
: wr_counter_r;
wr_state_n = start_write & wr_req_delay_zero
? DELAY
: WAIT;
wr_delay_n = start_write & wr_req_delay_zero
? $urandom_range(dma_data_delay_p,0)
: wr_delay_r;
end
DELAY: begin
wr_delay_n = wr_delay_r - 1;
wr_state_n = wr_delay_r == 0
? BUSY
: DELAY;
wr_data_delay_n = (wr_delay_r == 0)
? $urandom_range(dma_data_delay_p, 0)
: wr_data_delay_r;
end
BUSY: begin
wr_data_delay_n = wr_data_delay_zero
? (dma_data_v_i ? $urandom_range(dma_data_delay_p, 0) : 0)
: wr_data_delay_r - 1;
dma_data_yumi_o = dma_data_v_i & wr_data_delay_zero;
wr_counter_n = (dma_data_v_i & wr_data_delay_zero)
? wr_counter_r + 1
: wr_counter_r;
wr_state_n = (wr_counter_r == block_size_in_words_p-1) & dma_data_v_i & wr_data_delay_zero
? WAIT
: BUSY;
end
endcase
end
assign dma_pkt_yumi_o = (start_read & rd_req_ready) | (start_write & wr_req_ready);
// sequential
//
always_ff @ (posedge clk_i) begin
if (reset_i) begin
wr_state_r <= WAIT;
wr_addr_r <= '0;
wr_counter_r <= '0;
wr_delay_r <= '0;
wr_data_delay_r <= '0;
wr_req_delay_r <= '0;
for (integer i = 0; i < els_p; i++) begin
mem[i] <= '0;
end
end
else begin
wr_state_r <= wr_state_n;
wr_addr_r <= wr_addr_n;
wr_counter_r <= wr_counter_n;
wr_delay_r <= wr_delay_n;
wr_data_delay_r <= wr_data_delay_n;
wr_req_delay_r <= wr_req_delay_n;
if ((wr_state_r == BUSY) & dma_data_v_i & dma_data_yumi_o) begin
mem[{wr_upper_addr, wr_counter_r}] <= dma_data_i;
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_non_blocking_dma_model)
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e18; const long long MAX = 100100; void pre() {} void solve() { long long n; cin >> n; vector<long long> p(n), c(n); for (long long i = 0; i < n; ++i) cin >> p[i] >> c[i]; for (long long i = 0; i < n; ++i) { if (c[i] > p[i]) { cout << NO << n ; return; } } for (long long i = 1; i < n; ++i) { if (p[i] < p[i - 1]) { cout << NO << n ; return; } if (c[i] < c[i - 1]) { cout << NO << n ; return; } if ((p[i] - p[i - 1]) < (c[i] - c[i - 1])) { cout << NO << n ; return; } } cout << YES << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); pre(); long long t = 1; cin >> t; for (long long CASE = 1; CASE <= t; ++CASE) { solve(); } {}; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k, dp[2000 + 10][2000 + 10]; bool v[2000 + 10][2000 + 10]; vector<int> vec[2000 + 10]; int solve(int curr, int kk) { if (kk > k) return 0; if (kk == k) return 1; if (v[curr][kk]) return dp[curr][kk]; for (int i = 0; i < vec[curr].size(); i++) { dp[curr][kk] += (solve(vec[curr][i], kk + 1)) % 1000000007; dp[curr][kk] %= 1000000007; } v[curr][kk] = true; return dp[curr][kk]; } int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j += i) { if (!(j % i)) vec[i].push_back(j); } } cout << solve(1, 0) << n ; return 0; }
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:48:27 2016
/////////////////////////////////////////////////////////////
module LOAGDA_St_N16_M4_P8 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire intadd_17_CI, intadd_17_n4, intadd_17_n3, intadd_17_n2, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53,
n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65;
CMPR32X2TS intadd_17_U4 ( .A(in1[13]), .B(in2[13]), .C(intadd_17_n4), .CO(
intadd_17_n3), .S(res[13]) );
CMPR32X2TS intadd_17_U3 ( .A(in1[14]), .B(in2[14]), .C(intadd_17_n3), .CO(
intadd_17_n2), .S(res[14]) );
CMPR32X2TS intadd_17_U2 ( .A(in1[15]), .B(in2[15]), .C(intadd_17_n2), .CO(
res[16]), .S(res[15]) );
NOR2X1TS U47 ( .A(in1[5]), .B(in2[5]), .Y(n54) );
NAND2X1TS U48 ( .A(in2[10]), .B(in1[10]), .Y(n44) );
OAI2BB1X2TS U49 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n40), .Y(n41) );
NOR2X2TS U50 ( .A(n56), .B(n55), .Y(n58) );
OAI2BB2X1TS U51 ( .B0(n38), .B1(n37), .A0N(in2[2]), .A1N(in1[2]), .Y(n39) );
NOR2X1TS U52 ( .A(in1[9]), .B(in2[9]), .Y(n45) );
OR2X1TS U53 ( .A(in1[0]), .B(in2[0]), .Y(res[0]) );
OR2X2TS U54 ( .A(in1[3]), .B(in2[3]), .Y(res[3]) );
OR2X2TS U55 ( .A(in2[4]), .B(in1[4]), .Y(n51) );
OAI22X2TS U56 ( .A0(n64), .A1(n60), .B0(in2[10]), .B1(in1[10]), .Y(n61) );
NOR2X4TS U57 ( .A(n54), .B(n53), .Y(n52) );
OAI21X2TS U58 ( .A0(in2[8]), .A1(in1[8]), .B0(n57), .Y(n46) );
OR2X2TS U59 ( .A(in2[2]), .B(in1[2]), .Y(res[2]) );
ADDFHX2TS U60 ( .A(in2[8]), .B(in1[8]), .CI(n59), .CO(n65), .S(res[8]) );
OAI2BB1X4TS U61 ( .A0N(in2[11]), .A1N(in1[11]), .B0(n49), .Y(intadd_17_CI)
);
OAI22X4TS U62 ( .A0(in1[11]), .A1(in2[11]), .B0(n60), .B1(n48), .Y(n49) );
OAI21X4TS U63 ( .A0(in2[4]), .A1(in1[4]), .B0(n50), .Y(n53) );
AO22X4TS U64 ( .A0(in1[3]), .A1(in2[3]), .B0(res[3]), .B1(n39), .Y(n50) );
OAI2BB2X4TS U65 ( .B0(n56), .B1(n43), .A0N(in1[7]), .A1N(in2[7]), .Y(n57) );
AOI22X4TS U66 ( .A0(in1[6]), .A1(in2[6]), .B0(n42), .B1(n41), .Y(n43) );
OR2X2TS U67 ( .A(in1[1]), .B(in2[1]), .Y(res[1]) );
AOI22X1TS U68 ( .A0(in1[1]), .A1(in2[1]), .B0(in1[0]), .B1(in2[0]), .Y(n38)
);
NAND2X1TS U69 ( .A(res[1]), .B(res[2]), .Y(n37) );
OR2X2TS U70 ( .A(in1[6]), .B(in2[6]), .Y(n42) );
NAND2X2TS U71 ( .A(n52), .B(n42), .Y(n55) );
OA21XLTS U72 ( .A0(n52), .A1(n42), .B0(n55), .Y(res[6]) );
INVX2TS U73 ( .A(n44), .Y(n60) );
AOI22X1TS U74 ( .A0(in2[8]), .A1(in1[8]), .B0(in1[9]), .B1(in2[9]), .Y(n47)
);
NOR2X2TS U75 ( .A(in1[7]), .B(in2[7]), .Y(n56) );
OAI211X1TS U76 ( .A0(in2[5]), .A1(in1[5]), .B0(in1[4]), .C0(in2[4]), .Y(n40)
);
OAI21X1TS U77 ( .A0(in2[10]), .A1(in1[10]), .B0(n44), .Y(n63) );
AOI211X1TS U78 ( .A0(n47), .A1(n46), .B0(n45), .C0(n63), .Y(n48) );
OA21XLTS U79 ( .A0(n51), .A1(n50), .B0(n53), .Y(res[4]) );
AOI21X1TS U80 ( .A0(n54), .A1(n53), .B0(n52), .Y(res[5]) );
AOI21X1TS U81 ( .A0(n56), .A1(n55), .B0(n58), .Y(res[7]) );
OR2X2TS U82 ( .A(n58), .B(n57), .Y(n59) );
XOR2X1TS U83 ( .A(in2[11]), .B(in1[11]), .Y(n62) );
XNOR2X1TS U84 ( .A(n62), .B(n61), .Y(res[11]) );
XNOR2X1TS U85 ( .A(n64), .B(n63), .Y(res[10]) );
CMPR32X2TS U86 ( .A(in1[9]), .B(in2[9]), .C(n65), .CO(n64), .S(res[9]) );
CMPR32X2TS U87 ( .A(in1[12]), .B(in2[12]), .C(intadd_17_CI), .CO(
intadd_17_n4), .S(res[12]) );
initial $sdf_annotate("LOAGDA_St_N16_M4_P8_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a, b; int main() { cin >> n; a = (n + 2) * (n + 1) / 2 * n / 3; b = (n + 4) * (n + 3) / 2 * (n + 2) / 3 * (n + 1) / 4 * n / 5; cout << a * b; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s, t; getline(cin, s); getline(cin, t); int x = -1, y = -1; for (int i = 0, j = 0; j < t.length(); j++) { i += s[i] == t[j]; if (i == s.length()) { x = j; break; } } for (int i = s.length() - 1, j = t.length() - 1; j >= 0; j--) { i -= s[i] == t[j]; if (i == -1) { y = j; break; } } if (x != -1 && y != -1 && x < y) { printf( %d , y - x); } else { printf( 0 ); } return 0; }
|
#include <bits/stdc++.h> int main() { int num; scanf( %d , &num); int res = 0; for (int i = 0; i < num; i++) { char shape[30]; scanf( %s , shape); switch (shape[0]) { case T : res += 4; break; case C : res += 6; break; case O : res += 8; break; case D : res += 12; break; case I : res += 20; break; } } printf( %d n , res); return 0; }
|
// ************************Declaration*************************************** //
// File name: decoders38.v //
// Author: firedom //
// //
// Abstract: //
// dedocder38 for verilog. //
// [0:2]in is 3-port select input. //
// [0:7]out is 7-port select output. //
// [0:2]en is enable port. //
// Send 3'b100 to enable port and send 3'bxxx(000~111 3-bit binary code) //
// to select input can be accessed by the corresponding select output. //
// //
// Reference: //
// http://www.ti.com/lit/ds/symlink/sn74ls138.pdf //
// https://en.wikibooks.org/wiki/VHDL_for_FPGA_Design/Decoder //
// //
// Modification history:(including time, version, author and abstract) //
// 2016-08-30 22:14 version 1.0 //
// 2016-08-31 10:23 change wire name. //
// ************************Declaration*************************************** //
module decoders38(in, out, en);
input [0:2]in;
input [0:2]en;
output [0:7]out;
wire enableWire;
and
andGateEnable(enableWire, en[0], ~en[1], ~en[2]);
nand
nandGate0(out[0], ~in[2], ~in[1], ~in[0], enableWire),
nandGate1(out[1], ~in[2], ~in[1], in[0], enableWire),
nandGate2(out[2], ~in[2], in[1], ~in[0], enableWire),
nandGate3(out[3], ~in[2], in[1], in[0], enableWire),
nandGate4(out[4], in[2], ~in[1], ~in[0], enableWire),
nandGate5(out[5], in[2], ~in[1], in[0], enableWire),
nandGate6(out[6], in[2], in[1], ~in[0], enableWire),
nandGate7(out[7], in[2], in[1], in[0], enableWire);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1000004]; int main(void) { int n; scanf( %d , &n); int s = 1000000 + 1; printf( %d n , n); int p = 0; for (int i = 0; i < n; i++) { int t; scanf( %d , &t); a[t] = 1; if (a[s - t] == 1) p++; } for (int i = 1; i <= s; i++) { if (p > 0 && a[i] == 0 && a[s - i] == 0) { printf( %d %d , i, s - i); p--; } if (a[i] == 1 && a[s - i] == 0) printf( %d , s - i); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; string queue_[6] = { , Sheldon , Leonard , Penny , Rajesh , Howard }; int main() { cin >> n; double count = 1; bool used = false; while (count * 5 < n) { n -= count * 5; count *= 2; used = true; } int x = ceil(n / count); cout << queue_[x]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd3 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; bool good(long long int a, long long int b) { while (a and b) { if (a % 2 == 0 and b % 2 == 1) return false; a /= 2; b /= 2; } return true; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<pair<long long int, long long int>> s(n); for (int i = 0; i < n; i++) cin >> s[i].first; for (int i = 0; i < n; i++) cin >> s[i].second; sort(s.rbegin(), s.rend()); vector<bool> used(n, false); int nb = 0; long long int knw = 0; long long int ans = 0; for (int i = 1; i < n; i++) { if (s[i].first == s[i - 1].first) { knw |= s[i].first; if (!used[i]) { nb++; ans += s[i].second; used[i] = true; } if (!used[i - 1]) { nb++; ans += s[i - 1].second; used[i - 1] = true; } } } for (int i = 0; i < n; i++) { if (used[i]) continue; for (int j = 0; j < n; j++) { if (used[j] and (s[i].first | s[j].first) == s[j].first) { ans += s[i].second; nb++; used[i] = true; break; } } } if (nb < 2) ans = 0; cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n; long long nim[N], prefnim[N]; vector<pair<long long, long long> > sum[N]; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { long long cur = i; for (long long j = i + 1; j <= n; j++) { cur += j; if (cur > n) break; sum[cur].push_back({i, j}); } } for (long long i = 1; i <= n; i++) { unordered_set<long long> s; for (auto &it : sum[i]) s.insert(prefnim[it.second] ^ prefnim[it.first - 1]); long long val = 0; while (s.find(val) != s.end()) val++; nim[i] = val; prefnim[i] = prefnim[i - 1] ^ nim[i]; } if (nim[n] == 0) cout << -1 ; else { long long ans = 1e9; for (auto &it : sum[n]) { if ((prefnim[it.second] ^ prefnim[it.first - 1]) == 0) ans = min(ans, it.second - it.first + 1); } cout << ans; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INVLP_FUNCTIONAL_V
/**
* invlp: Low Power Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__invlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int a[100005]; map<int, int> s; int main(void) { long long ans = 0, z = 0; int k, b, n; scanf( %d%d%d , &k, &b, &n); int zcnt = 0; s[0]++; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); zcnt = (a[i] ? 0 : zcnt + 1); z += zcnt; a[i] = (a[i] + a[i - 1]) % (k - 1); int P = (a[i] - b + k - 1) % (k - 1); ans += s[P]; s[a[i]]++; } if (b == 0) ans = z; else if (b == k - 1) ans -= z; printf( %I64d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_PP_V
|
// --------------------------------------------------------------------
// Copyright (c) 2015 by Semillero ADT.
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
//
// web: https://sites.google.com/site/semilleroadt/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions: BE-MICRO MAX10 TOP
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author:Fabian Humberto Castillo Pineda | Mod. Date :18-May-2015 7:16:08 PM
//| Changes Made:
// --------------------------------------------------------------------
module practica4( //CLOCKS
CLK_50,
USER_CLK,
//LED
LED,
//SW
SW,
//FLASH
SFLASH_DCLK,
SFLASH_ASDI,
SFLASH_CSn,
SFLASH_DATA,
//SDRAM
SDRAM_A,
SDRAM_BA,
SDRAM_CASn,
SDRAM_CKE,
SDRAM_CLK,
SDRAM_CSn,
SDRAM_DQ,
SDRAM_RASn,
SDRAM_WEn,
SDRAM_DQM,
//PMOD_A
PMOD_A,
//PMOD_B
PMOD_B,
//PMOD_C
PMOD_C,
//PMOD_D
PMOD_D,
//GPIO_0/DIFF
GPIO_0,
);
//CLOCKS
input CLK_50;
input USER_CLK;
//LED
output [7:0]LED;
//SW
input [3:0]SW;
//FLASH
output SFLASH_DCLK;
output SFLASH_ASDI;
output SFLASH_CSn;
input SFLASH_DATA;
//SDRAM
output [12:0]SDRAM_A;
output [1:0]SDRAM_BA;
output SDRAM_CASn;
output SDRAM_CKE;
output SDRAM_CLK;
output SDRAM_CSn;
inout [15:0]SDRAM_DQ;
output SDRAM_RASn;
output SDRAM_WEn;
output [1:0]SDRAM_DQM;
//PMOD_A
inout [3:0]PMOD_A;
//PMOD_B
inout [3:0]PMOD_B;
//PMOD_C
inout [3:0]PMOD_C;
//PMOD_D
inout [3:0]PMOD_D;
//GPIO_0/DIFF/J3
inout [35:0]GPIO_0;
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
mi_nios u0 (
.clk_clk (CLK_50), // clk.clk
.reset_reset_n (1'b1), // reset.reset_n
//Flash
.flash_dclk (SFLASH_DCLK), // flash.dclk
.flash_sce (SFLASH_CSn), // .sce
.flash_sdo (SFLASH_ASDI), // .sdo
.flash_data0 (SFLASH_DATA), // .data0
//LED AND SW
.led_export (LED[7:0]), // led.export
.sw_export (SW[3:0]), // sw.export
//SDRAM
.sdram_addr (SDRAM_A), // sdram.addr
.sdram_ba (SDRAM_BA), // .ba
.sdram_cas_n (SDRAM_CASn), // .cas_n
.sdram_cke (SDRAM_CKE), // .cke
.sdram_cs_n (SDRAM_CSn), // .cs_n
.sdram_dq (SDRAM_DQ), // .dq
.sdram_dqm (SDRAM_DQM), // .dqm
.sdram_ras_n (SDRAM_RASn), // .ras_n
.sdram_we_n (SDRAM_WEn), // .we_n
.sdram_clk_clk (SDRAM_CLK) // sdram_clk.clk
);
endmodule
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; int main() { int t; cin >> t; while(t--) { string s; cin >> s; char c = a ; int n = s.size(); if(n&1) { for(int i=0;i<=n/2;i++) { if(s[n-i-1]!= a ) { s = s.substr(0,i)+c+s.substr(i); break; } } if(s.size()==n+1) { cout << YES << endl; cout << s << endl; } else{ bool p = true; for(int i=0;i<n/2;i++) { if(s[n-i-1]!=s[i]) { p = false; break; } } if(!p) { cout << YES << endl; cout << s+c << endl; } else { cout << NO << endl; } } } else{ for(int i=0;i<n/2;i++) { if(s[n-i-1]!= a ) { s = s.substr(0,i)+c+s.substr(i); break; } } if(s.size()==n+1) { cout << YES << endl; cout << s << endl; } else{ bool p = true; for(int i=0;i<n/2;i++) { if(s[n-i-1]!=s[i]) { p = false; break; } } if(!p) { cout << YES << endl; cout << s+c << endl; } else { cout << NO << endl; } } } } }
|
#include <bits/stdc++.h> using namespace std; const long long inf = (1ll << 60); int n, k, p; int a[2005], b[2005]; long long dp[2005][2005]; long long rec(int pos, int key) { if (pos == n) { return 0; } if (key == k) return inf; long long &ret = dp[pos][key]; if (ret != -1) return ret; long long sum = abs(a[pos] - b[key]) + abs(b[key] - p); ret = max(sum, rec(pos + 1, key + 1)); ret = min(ret, rec(pos, key + 1)); return ret; } int main() { cin >> n >> k >> p; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < k; i++) cin >> b[i]; sort(a, a + n); sort(b, b + k); memset(dp, -1, sizeof dp); cout << rec(0, 0) << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_2_V
`define SKY130_FD_SC_HD__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, n, ch = 0; string s, g; cin >> n >> k >> s; for (int i = 1; i <= n && ch == 0; i++) { string t = s.substr(0, i); string temp = 0 ; int count; (n % i == 0) ? count = n / i : count = (n / i) + 1; for (int j = 0; j < count; j++) temp += t; if (temp.find(s) == 0) { g = t; ch++; } } string l = 0 ; for (int i = 0; i < k - 1; i++) l += g; l += s; cout << l << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_4_V
`define SKY130_FD_SC_HD__DECAP_4_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_4_V
|
module linked_fifo_gold(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full, count);
parameter WIDTH = 8;
parameter DEPTH = 32;
parameter FIFOS = 8;
parameter FIFO_LOG2 = log2(FIFOS-1);
parameter DEPTH_LOG2 = log2(DEPTH-1);
input rst, clk, push;
input [FIFO_LOG2-1:0] push_fifo;
input pop;
input [FIFO_LOG2-1:0] pop_fifo;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
output reg empty, full;
output reg [(DEPTH_LOG2+1)*FIFOS-1:0] count;
reg [WIDTH-1:0] memory [0:FIFOS-1][0:DEPTH-1];
reg [DEPTH_LOG2:0] r_beg [0:FIFOS-1];
reg [DEPTH_LOG2:0] r_end [0:FIFOS-1];
integer i;
always @(posedge clk) begin
if(rst) begin
for(i=0; i < FIFOS; i=i+1) begin
r_beg[i] <= 0;
r_end[i] <= 0;
end
end else begin
if(push) begin
r_end[push_fifo] <= r_end[push_fifo] + 1;
end
if(pop) begin
r_beg[pop_fifo] <= r_beg[pop_fifo] + 1;
end
end
q <= memory[pop_fifo][r_beg[pop_fifo][DEPTH_LOG2-1:0]];
memory[push_fifo][r_end[push_fifo][DEPTH_LOG2-1:0]] <= d;
end
always @* begin
empty = r_beg[pop_fifo] == r_end[pop_fifo];
//TODO: full
full = 0;
//TODO: count
count = 0;
end
always @(posedge clk) begin
if(empty && pop) begin
$display("ERROR: underflow: %m");
$finish;
end
end
//TODO finish
`include "log2.vh"
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int n, m; struct node { int from, to, w; } edge[maxn]; int in[maxn]; vector<int> e[maxn]; int top[maxn]; bool topsort(int mid) { memset(in, 0, sizeof(in)); int cnt = 0; queue<int> q; for (int i = 1; i <= n; ++i) e[i].clear(); for (int i = 1; i <= m; ++i) { if (edge[i].w > mid) e[edge[i].from].push_back(edge[i].to), in[edge[i].to]++; } for (int i = 1; i <= n; ++i) { if (!in[i]) { q.push(i); top[i] = ++cnt; } } while (!q.empty()) { int u = q.front(); q.pop(); for (auto it : e[u]) { int v = it; in[v]--; if (!in[v]) { q.push(v); top[v] = ++cnt; } } } for (int i = 1; i <= n; ++i) { if (in[i]) return false; } return true; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= m; ++i) { cin >> edge[i].from >> edge[i].to >> edge[i].w; } int l = 0, r = 0x3f3f3f3f; int ret = 0; while (l <= r) { int mid = (l + r) >> 1; if (topsort(mid)) { ret = mid; r = mid - 1; } else l = mid + 1; } topsort(ret); vector<int> ans; for (int i = 1; i <= m; ++i) { if (edge[i].w <= ret && top[edge[i].from] > top[edge[i].to]) { ans.push_back(i); } } cout << ret << << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { cout << ans[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = 0; cin >> n; ans = (n * (n + 1)) / 2; if (ans & 1) cout << 1 << endl; else cout << 0 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { int res[100]; memset(res, 0, sizeof(res)); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { int r; cin >> r; if (i < j) continue; switch (r) { case 1: ++res[i]; break; case 2: ++res[j]; break; case 3: ++res[i]; ++res[j]; default: break; } } } int count = 0; for (int i = 0; i < n; ++i) { if (res[i] == 0) { res[count++] = i + 1; } } cout << count << endl; if (count > 0) { for (int i = 0; i < count; ++i) { cout << res[i] << ; } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n, m; char c[2000][2000]; int rowcount[2000]; int colcount[2000], wallcount = 0; for (int i = 0; i < 2000; i++) { rowcount[i] = 0; colcount[i] = 0; } scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < n; i++) scanf( %s , c[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (c[i][j] == * ) { rowcount[i]++; colcount[j]++; wallcount++; } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (c[i][j] == * && rowcount[i] + colcount[j] - 1 == wallcount || c[i][j] == . && rowcount[i] + colcount[j] == wallcount) { printf( YES n ); printf( %d %d n , i + 1, j + 1); return 0; } } } printf( NO n ); return 0; }
|
module tester;
reg rrst;
reg [88:0] rsetup_data;
reg [1047:0]rdata;
reg [23:0] rtoken;
reg [31:0] rsync2;
reg [7:0] rsync;
wire [1047:0]wdata_out;
wire [7:0]wtoken_out;
reg [4:0] crc_cero =0;
wire [4:0] sum_crc;
reg [10:0] rtoken_mensaje;
reg [7:0]pid ;
reg [7:0]pid2 ;
reg [6:0]addr ;
reg [63:0]setup_mesage;
reg [3:0] endp ;
reg rbusy = 0;
reg rclk = 0;
always #1 rclk = !rclk;
always @ (*)
begin
rtoken[23:16]= pid[7:0] ;
rtoken[15:9] = addr[6:0] ;
rtoken[8:5] = endp[3:0] ;
rtoken [4:0] = sum_crc [4:0];
rsetup_data [88:80] = pid2;
rsetup_data [79:15] = setup_mesage[63:0];
rsetup_data [14:0] = 0 ;
end
initial begin
$dumpfile("tester.vcd");
$dumpvars(0,tester);
rrst = 1;
#5
rrst =0 ;
rsync = 8'b01010100;
pid = 8'b11010010;
addr = 7'b1111111;
endp = 0;
#7
rrst =0 ;
setup_mesage =64'b1111 ;
rsync = 8'b01010100;
pid = 8'b00111100;
pid2 = 8'b00111100;
addr = 7'b1111111;
endp = 0;
# 513 $finish;
end
CRC5_D11 CRC5_D11_intance2 (
.Data (rtoken[15:5]),
.crc (crc_cero),
.nextCRC5_D11 (sum_crc)
);
TS TS_instance (
.sync (rsync),
.sync2 (rsync2),
.clk (rclk),
.rst (rrst),
.data (rdata),
.token (rtoken),
.busy (rbusy),
.data_out (wdata_out),
.setup_data (rsetup_data),
.token_out (wtoken_out)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_e_e
//
// Generated
// by: wig
// on: Tue Mar 30 18:39:52 2004
// cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_e_e.v,v 1.2 2006/01/19 08:50:42 wig Exp $
// $Date: 2006/01/19 08:50:42 $
// $Log: inst_e_e.v,v $
// Revision 1.2 2006/01/19 08:50:42 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
// Revision 1.1 2004/04/06 11:19:55 wig
// Adding result/autoopen
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
//
// Generator: mix_0.pl Revision: 1.28 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_e_e
//
// No `defines in this module
module inst_e_e
//
// Generated module inst_e
//
(
p_mix_s_eo3_go,
s_eo1,
s_eo2,
s_eo4,
s_eo5,
s_outname
);
// Generated Module Inputs:
input s_outname;
// Generated Module Outputs:
output p_mix_s_eo3_go;
output s_eo1;
output s_eo2;
output s_eo4;
output s_eo5;
// Generated Wires:
wire p_mix_s_eo3_go;
wire s_eo1;
wire s_eo2;
wire s_eo4;
wire s_eo5;
wire s_outname;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire s_eo3; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_s_eo3_go = s_eo3; // __I_O_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ea
inst_ea_e inst_ea(
.p_mix_s_eo1_go(s_eo1),
.p_mix_s_eo2_go(s_eo2),
.p_mix_s_eo3_go(s_eo3),
.p_mix_s_eo4_gi(s_eo4),
.p_mix_s_eo5_go(s_eo5)
);
// End of Generated Instance Port Map for inst_ea
// Generated Instance Port Map for inst_eb
inst_eb_e inst_eb(
.p_mix_s_eo2_gi(s_eo2)
);
// End of Generated Instance Port Map for inst_eb
endmodule
//
// End of Generated Module rtl of inst_e_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > adj(601); vector<int> unvisited, even, odd; int d[601], parent[601]; bool visited[601]; map<vector<int>, int> M; void RemoveFromUnvisited(int v) { int i = 0; for (; i < unvisited.size() && unvisited[i] != v; ++i) ; unvisited.erase(unvisited.begin() + i); } void PrintQueryOrAnswer(char c, vector<int> &A) { printf( %c %lu n , c, A.size()); for (auto x : A) { printf( %d , x); } printf( n ); fflush(stdout); } int PrintQuery(vector<int> A) { sort(A.begin(), A.end()); if (M.find(A) != M.end()) { return M[A]; } PrintQueryOrAnswer( ? , A); int m; scanf( %d , &m); M[A] = m; return m; } int Query(vector<int> &A, int s = 0) { if (s) { A.push_back(s); } int m = PrintQuery(A); if (s) { A.pop_back(); } return m; } int NextChild(int i, vector<int> A) { if (A.size() == 0) { return 0; } int m1 = Query(A, i); if (m1 == 0) { return 0; } if (A.size() == 1) { return A.back(); } int m2 = Query(A); if (m2 == m1) { return 0; } int j = NextChild(i, vector<int>(A.begin(), A.begin() + (A.size() / 2))); if (j == 0) { j = NextChild(i, vector<int>(A.begin() + (A.size() / 2), A.end())); } return j; } void AddEdge(int i, int j) { adj[i].push_back(j); adj[j].push_back(i); } void AddEdgeDFS(int i, bool markEvenOdd) { RemoveFromUnvisited(i); if (markEvenOdd) { if (d[i]) { odd.push_back(i); } else { even.push_back(i); } } for (int j = NextChild(i, unvisited); j > 0; j = NextChild(i, unvisited)) { AddEdge(i, j); if (markEvenOdd) { d[j] = 1 - d[i]; } AddEdgeDFS(j, markEvenOdd); } } pair<int, int> BipartiteDFS(int i, int p) { parent[i] = p; d[i] = 1 + d[p]; visited[i] = 1; pair<int, int> ans = make_pair(0, 0); for (auto j : adj[i]) { if (j == p) { continue; } if (visited[j]) { if ((d[i] - d[j]) % 2 == 0 && d[i] > d[j]) { return make_pair(i, j); } continue; } ans = max(ans, BipartiteDFS(j, i)); } return ans; } void AddEdges(vector<int> v, bool markEvenOdd) { unvisited = vector<int>(v); while (unvisited.size()) { AddEdgeDFS(unvisited.back(), markEvenOdd); } } int main() { int n; vector<int> V; scanf( %d , &n); for (int i = 1; i <= n; ++i) { V.push_back(i); } AddEdges(V, true); AddEdges(even, false); AddEdges(odd, false); pair<int, int> p = make_pair(0, 0); for (int i = 1; i <= n; ++i) { if (visited[i]) { continue; } p = max(p, BipartiteDFS(i, 0)); } int u, v; tie(u, v) = p; vector<int> ans; if (u == 0) { for (int i = 1; i <= n; ++i) { if (d[i] % 2) { ans.push_back(i); } } } else { for (; u != parent[v]; u = parent[u]) { ans.push_back(u); } } PrintQueryOrAnswer(v ? N : Y , ans); return 0; }
|
/*
******************************************************************************
* File Name : tb_ada_core.v
* Project : ADA processor
* Version : 0.1
* Date : Sept 2nd, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright (c) 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Testbench for the EXU (execution unit)
******************************************************************************
*/
`timescale 1ns / 1ns
`include "ada_defines.v"
`define cycle 10
module tb_ada_core;
reg clk;
reg rst;
reg [31:0] io_interrupt; //
reg [31:0] io_data_i; // data from device
reg io_ready; // device is ready
reg [31:0] eimem_cache_data_i; // Data from memory
reg eimem_cache_ready; // memory is ready
reg [31:0] edmem_cache_data_i; // Data from memory
reg edmem_cache_ready; // memory is ready
wire [31:0] io_address; // device address
wire [31:0] io_data_o; // data to device
wire io_we; // write to device
wire io_enable; // enable operation
wire [31:0] eimem_cache_address; // data address
wire eimem_cache_wr; // write = 1, read = 0,
wire eimem_cache_enable; // enable operation
wire [31:0] edmem_cache_address; // data address
wire [31:0] edmem_cache_data_o; // data to memory
wire edmem_cache_wr; // write = 1, read = 0,
wire edmem_cache_enable; // enable operation
wire icache_flush;
wire dcache_flush;
//--------------------------------------------------------------------------
// UUT
//--------------------------------------------------------------------------
ada_core uut(
.clk(clk),
.rst(rst),
.io_interrupt(io_interrupt),
.io_data_i(io_data_i),
.io_ready(io_ready),
.io_address(io_address),
.io_data_o(io_data_o),
.io_we(io_we),
.io_enable(io_enable),
.eimem_cache_data_i(eimem_cache_data_i),
.eimem_cache_ready(eimem_cache_ready),
.eimem_cache_address(eimem_cache_address),
.eimem_cache_wr(eimem_cache_wr),
.eimem_cache_enable(eimem_cache_enable),
.edmem_cache_data_i(edmem_cache_data_i),
.edmem_cache_ready(edmem_cache_ready),
.edmem_cache_address(edmem_cache_address),
.edmem_cache_data_o(edmem_cache_data_o),
.edmem_cache_wr(edmem_cache_wr),
.edmem_cache_enable(edmem_cache_enable),
.icache_flush(icache_flush),
.dcache_flush(dcache_flush)
);
//--------------------------------------------------------------------------
// Setup
//--------------------------------------------------------------------------
initial begin
// Initialize regs
clk <= 1;
rst <= 1;
io_interrupt <= 0;
io_data_i <= 0;
io_ready <= 0;
eimem_cache_data_i <= 0;
eimem_cache_ready <= 0;
edmem_cache_data_i <= 0;
edmem_cache_ready <= 0;
// dump the wave file
$dumpfile("tb_core.vcd");
$dumpvars;
end
//--------------------------------------------------------------------------
// clock
//--------------------------------------------------------------------------
always begin
#(`cycle/2) clk = !clk;
end
//--------------------------------------------------------------------------
// simulation
//--------------------------------------------------------------------------
initial begin
rst = #(4.5*`cycle)0;
$display("Testing the ADA Core: begin");
//--------------------------------------------------------------------------
rst = #(10*`cycle)0;
@(posedge clk)
//--------------------------------------------------------------------------
@(posedge clk)
//--------------------------------------------------------------------------
$display("Testing the ADA Core: finished");
$finish;
end
endmodule
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//
// Wishbone wrapper for seven-segment LED display controller
//
// Copyright (C) 2015 Andrzej <>
//
// Redistribution and use in source and non-source forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in non-source form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// Register map (assuming 32b access):
// 00 [1] - IRQ mask. 1 - IRQ enabled.
// [0] - Enable display controller
// 04 [15:0] - Clock divider for multiplexing.
// To obtain a scanning rate further divide by 256 (for PWM) and by n_digits.
// 08 [7:0] - Brightness control. 0 - minimum brightness (non-zero), 255 - maximum.
// Logarithmic progression (percepted).
// 0c [0] - (Write) Write '1' to clear IRQ flag.
// 0c [0] - (Read) IRQ Flag.
// 20 [n_segs-1:0] - First digit (or column)
// 24 [n_segs-1:0] - Second digit (or column)
// ...
//
// Example of instantiation:
// // open-drain output with logic inversion
// wire [7:0] sseg_disp_seg_oe;
// generate
// for (i = 0; i < 8; i = i+1) begin: sseg_disp_seg_tris
// assign sseg_disp_seg_o [i] = sseg_disp_seg_oe[i] ? 1'b0 : 1'bz;
// end
// endgenerate
//
// wire [7:0] sseg_disp_seg_sel;
// assign sseg_disp_an_o = ~sseg_disp_seg_sel;
//
// wb_sseg_ctrl
// #(
// .n_digits (8),
//`ifdef SIM
// .def_clk_div(4) // speed up simulation time
//`else
// .def_clk_div(128)
//`endif
// )
// sseg_ctrl
// (
// .wb_clk_i (wb_clk),
// .wb_rst_i (wb_rst),
// .async_rst_i (async_rst),
// // Wishbone slave interface
// .wb_adr_i (wb_m2s_sseg_ctrl_adr[5:2]),
// .wb_dat_i (wb_m2s_sseg_ctrl_dat),
// .wb_sel_i (wb_m2s_sseg_ctrl_sel),
// .wb_we_i (wb_m2s_sseg_ctrl_we),
// .wb_cyc_i (wb_m2s_sseg_ctrl_cyc),
// .wb_stb_i (wb_m2s_sseg_ctrl_stb),
// .wb_cti_i (wb_m2s_sseg_ctrl_cti),
// .wb_bte_i (wb_m2s_sseg_ctrl_bte),
// .wb_dat_o (wb_s2m_sseg_ctrl_dat),
// .wb_ack_o (wb_s2m_sseg_ctrl_ack),
// .wb_err_o (wb_s2m_sseg_ctrl_err),
// .wb_rty_o (wb_s2m_sseg_ctrl_rty),
// // display i/f
// .seg_o (sseg_disp_seg_oe),
// .seg_sel_o (sseg_disp_seg_sel),
// // frame sync irq
// .irq_o (sseg_didp_irq)
// );
module wb_sseg_ctrl
#(
parameter n_digits = 8,
parameter n_segs = 8,
parameter def_clk_div = 128,
//parameter def_clk_div = 4,
parameter dw = 16,
parameter aw = 4
)
(
input wb_clk_i,
input wb_rst_i,
input async_rst_i,
// Wishbone Interface
input [aw-1:0] wb_adr_i,
input [dw-1:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [dw-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
// display i/f
output [n_segs-1:0] seg_o,
output [n_digits-1:0] seg_sel_o,
// frame sync irq (end of the sweep)
output irq_o
);
wire sync;
// address decoder
reg [2**aw-1:0] sel;
integer i;
always @(*)
begin
sel = {2**aw{1'b0}};
for (i = 0; i < 2**aw; i = i + 1)
if (wb_adr_i == i)
sel[i] = 1'b1;
end
// enable register
reg enable_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
enable_reg <= 1'b0;
else if (wb_rst_i)
enable_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
enable_reg <= wb_dat_i[0];
// mask IRQ register
reg IRQ_mask_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_mask_reg <= 1'b0;
else if (wb_rst_i)
IRQ_mask_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[0])
IRQ_mask_reg <= wb_dat_i[1];
// clock divider register
reg [15:0] clk_div_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_rst_i)
clk_div_reg <= def_clk_div;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[1])
clk_div_reg <= wb_dat_i[15:0];
// brightness register
reg [7:0] brightness_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
brightness_reg <= 8'hff;
else if (wb_rst_i)
brightness_reg <= 8'hff;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[2])
brightness_reg <= wb_dat_i[7:0];
// data to display
reg [n_digits*n_segs-1:0] segments_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
segments_reg <= 0;
else if (wb_rst_i)
segments_reg <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i)
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
segments_reg[n_segs*(i+1)-1 -: n_segs] <= wb_dat_i[n_segs-1:0];
// IRQ flag
// write '1' to clear it
reg IRQ_flag_reg;
always @(posedge wb_clk_i or posedge async_rst_i)
if (async_rst_i)
IRQ_flag_reg <= 1'b0;
else if (wb_rst_i)
IRQ_flag_reg <= 1'b0;
else if (wb_cyc_i & wb_stb_i & wb_we_i & sel[3] & wb_dat_i[0])
IRQ_flag_reg <= 1'b0;
else if (sync)
IRQ_flag_reg <= 1'b1;
assign irq_o = IRQ_flag_reg & IRQ_mask_reg;
// read back register values
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_dat_o <= 32'b0;
else if (wb_cyc_i)
begin
wb_dat_o <= 0;
if (sel[0]) wb_dat_o[1:0] <= {IRQ_mask_reg, enable_reg};
if (sel[1]) wb_dat_o[15:0] <= clk_div_reg;
if (sel[2]) wb_dat_o[7:0] <= brightness_reg;
if (sel[3]) wb_dat_o[0] <= IRQ_flag_reg;
for (i = 0; i < n_digits; i = i + 1)
if (sel[i+8])
wb_dat_o[n_segs-1:0] <= segments_reg[n_segs*(i+1)-1 -: n_segs];
end
// Ack generation
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
// instantiate the controller
sseg_ctrl #(.n_digits(n_digits)) ctrl
(
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.async_rst_i (async_rst_i),
// config registers
.enable_i (enable_reg),
.clk_div_i (clk_div_reg),
.brightness_i (brightness_reg),
.segments_i (segments_reg),
// display i/f
.seg_o (seg_o),
.seg_sel_o (seg_sel_o),
// sync irq
.sync_o (sync)
);
endmodule
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#include <bits/stdc++.h> using namespace std; void File() { freopen( CF1045H.in , r , stdin); freopen( CF1045H.out , w , stdout); } template <typename T> void read(T &_) { _ = 0; T f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) _ = (_ << 1) + (_ << 3) + (c ^ 0 ); _ *= f; } const int maxn = 5e5 + 10; const int mod = 1e9 + 7; const int N = 1e5; long long fac[maxn], ifac[maxn]; int c[5]; long long qpow(long long x, long long y) { long long ret = 1; x %= mod; while (y) { if (y & 1) ret = ret * x % mod; x = x * x % mod; y >>= 1; } return ret; } void math_init() { fac[0] = 1; for (int i = 1, i_end_ = N; i <= i_end_; ++i) fac[i] = fac[i - 1] * i % mod; ifac[N] = qpow(fac[N], mod - 2); for (int i = N - 1, i_end_ = 0; i >= i_end_; --i) ifac[i] = ifac[i + 1] * (i + 1) % mod; } long long C(int x, int y) { if (x < 0 || y < 0 || x < y) return 0; return fac[x] * ifac[y] % mod * ifac[x - y] % mod; } long long calc(int x, int y) { if (!x && !y) return 1; return C(x + y - 1, y - 1); } long long solve(char *s, bool type) { long long ret = 0; int len = strlen(s + 1), lim = 0, res[5]; for (int i = 0, i_end_ = 3; i <= i_end_; ++i) lim += c[i], res[i] = c[i]; ++lim; if (len < lim) return 0; if (len > lim) { type = 1; len = lim; for (int i = 1, i_end_ = len; i <= i_end_; ++i) s[i] = 1 ; } for (int i = 1, i_end_ = len; i <= i_end_; ++i) { if (i > 2) --res[(s[i - 2] ^ 0 ) << 1 | (s[i - 1] ^ 0 )]; if (s[i] == 0 || i == 1) continue; if (i > 1) --res[(s[i - 1] ^ 0 ) << 1]; if (res[2] >= res[1] - 1 && res[2] <= res[1]) { ret = (ret + calc(res[0], res[2] + 1) * calc(res[3], res[1])) % mod; } if (i > 1) ++res[(s[i - 1] ^ 0 ) << 1]; } if (type) { if (len > 1) --res[(s[len - 1] ^ 0 ) << 1 | (s[len] ^ 0 )]; if (!res[0] && !res[1] && !res[2] && !res[3]) ++ret; } return ret; } int main() { char L[maxn], R[maxn]; math_init(); scanf( %s%s , L + 1, R + 1); for (int i = 0, i_end_ = 3; i <= i_end_; ++i) read(c[i]); printf( %lld n , ((solve(R, 1) - solve(L, 0)) % mod + mod) % mod); return 0; }
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#include <bits/stdc++.h> using namespace std; char mp[1001][1001]; int visit[1001][1001]; int dist[1001][1001]; int N, M; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; bool chk(int x, int y) { return 0 <= x && x < N && 0 <= y && y < M; } void dfs(int x, int y, bool isfirst) { visit[x][y] = 1; if (!isfirst) dist[x][y] = 1; for (int i = 0; i < 4; i++) { int nx = x + dx[i]; int ny = y + dy[i]; if (chk(nx, ny) && mp[x][y] == mp[nx][ny] && visit[nx][ny] == 0) { dist[x][y] = 1; dfs(nx, ny, false); } } } int main(int argc, char *argv[]) { int Q; scanf( %d %d %d , &N, &M, &Q); for (int i = 0; i < N; i++) scanf( %s , mp[i]); for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { if (visit[i][j] == 0) dfs(i, j, true); } } queue<pair<int, int> > q; for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { if (dist[i][j] == 1) q.push({i, j}); } } while (!q.empty()) { auto [x, y] = q.front(); q.pop(); for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (chk(nx, ny) && dist[nx][ny] == 0) { dist[nx][ny] = dist[x][y] + 1; q.push({nx, ny}); } } } while (Q--) { long long x, y, t; scanf( %lld %lld %lld , &x, &y, &t); printf( %lld n , dist[x - 1][y - 1] ? ((mp[x - 1][y - 1] - 0 ) + max(t - (dist[x - 1][y - 1] - 1), 0LL)) % 2 : mp[x - 1][y - 1] - 0 ); } }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:03:21 10/28/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
input clk,
input reset,
input rxin,
output txout,
output [7:0] Led
);
`define TXREG 3'b001
`define CONTROLTX 3'b011
`define RXREG 3'b101
`define CONTROLRX 3'b111
`define TXR 2'b00
`define CTX 2'b01
`define RXR 2'b10
`define CRX 2'b11
`define START 3'b000
`define WAITRX 3'b001
`define PASSTX 3'b010
`define WRTX 3'b011
`define WAITTX 3'b100
`define CLRTX 3'b101
`define WAITWRTX 3'b110
`define STOP 3'b111//used for debug
`define RXREADY to_tx[1]
`define TXREADY tx_out[1]
`define TXWRRDY tx_out[0]
wire [7:0] to_tx;
wire [1:0] tx_out;
reg [2:0] addr, pstate, nstate;
reg [1:0] addmux;
reg [3:0] din;
reg [7:0] cache, leds;
reg wr_rx, rd_rx, wr_tx, rd_tx, ld, cl;
uart_rx #(.PERIOD(8'h0C)) RX(
.clk (clk),
.reset (reset),
.wren (wr_rx),
.rden (rd_rx),
.din (1'b1),
.dout (to_tx),
.rxin (rxin),
.addr (addr)
);
uart_tx #(.PERIOD(8'h0C)) TX(
.clk (clk),
.reset (reset),
.wren (wr_tx),
.rden (rd_tx),
.din (cache),
.dout (tx_out),
.txout (txout),
.addr (addr)
);
assign Led = leds;
always @* begin
addr = 3'b010;
case(addmux)
`TXR:
addr = `TXREG;
`CTX:
addr = `CONTROLTX;
`RXR:
addr = `RXREG;
`CRX:
addr = `CONTROLRX;
endcase
end
always @(posedge clk or posedge reset) begin
if(reset) begin
cache <= 8'b11111111;
leds <= 8'b11111111;
end
else begin
if(ld)
cache <= to_tx + 1;
if(cl) begin
cache <= 8'b00000000;
leds <= cache;
end
end
end
always @(posedge clk or posedge reset) begin
if(reset)
pstate <= `START;
else begin
pstate <= nstate;
end
end
always @* begin
wr_rx = 0; rd_rx = 0;
wr_tx = 0; rd_tx = 0;
ld = 0; cl = 0;
addmux = `CRX;
nstate = pstate;
case(pstate)
`START: begin
wr_rx = 1;
nstate = `WAITRX;
end
`WAITRX: begin
rd_rx = 1;
if(`RXREADY)
nstate = `PASSTX;
end
`PASSTX: begin
rd_rx = 1;
addmux = `RXR;
ld = 1;
nstate = `WAITWRTX;
end
`WAITWRTX: begin
rd_tx = 1;
addmux = `CTX;
if(~`TXWRRDY)
nstate = `WRTX;
end
`WRTX: begin
wr_tx = 1;
addmux = `TXR;
nstate = `WAITTX;
end
`WAITTX: begin
rd_tx = 1;
addmux = `CTX;
if(`TXREADY) begin
cl = 1;
nstate = `CLRTX;
end
end
`CLRTX: begin
wr_tx = 1;
addmux = `CTX;
nstate = `WAITRX;
end
`STOP: begin
nstate = `STOP;
end
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int MOD = 1e9 + 7; const int N = 1e5 + 7; int n, m, x, L, R; long long pre[N][6]; long long sum[N << 2][6]; int laz[N << 2]; inline void pushup(int rt) { for (int i = int(0); i <= int(5); ++i) sum[rt][i] = sum[rt << 1][i] + sum[rt << 1 | 1][i], sum[rt][i] %= MOD; } inline void pushdown(int rt, int l, int r) { if (laz[rt] != -1) { int m = (l + r) >> 1; for (int i = int(0); i <= int(5); ++i) { sum[rt << 1][i] = ((pre[m][i] - pre[l - 1][i]) % MOD + MOD) % MOD * laz[rt] % MOD; sum[rt << 1 | 1][i] = ((pre[r][i] - pre[m][i]) % MOD + MOD) % MOD * laz[rt] % MOD; } laz[rt << 1] = laz[rt << 1 | 1] = laz[rt]; laz[rt] = -1; } } void build(int rt, int l, int r) { laz[rt] = -1; if (l == r) { scanf( %d , &x); sum[rt][0] = (long long)x; for (int i = int(1); i <= int(5); ++i) sum[rt][i] = sum[rt][i - 1] * l % MOD; return; } int m = (l + r) >> 1; build(rt << 1, l, m); build(rt << 1 | 1, m + 1, r); pushup(rt); } void setv(int rt, int l, int r) { if (L <= l && r <= R) { laz[rt] = x; for (int i = int(0); i <= int(5); ++i) { sum[rt][i] = ((pre[r][i] - pre[l - 1][i]) % MOD + MOD) % MOD * x % MOD; } return; } pushdown(rt, l, r); int m = (l + r) >> 1; if (L <= m) setv(rt << 1, l, m); if (R > m) setv(rt << 1 | 1, m + 1, r); pushup(rt); } long long query(int d, int rt, int l, int r) { if (L <= l && r <= R) { return sum[rt][d]; } pushdown(rt, l, r); int m = (l + r) >> 1; long long ret = 0; if (L <= m) ret += query(d, rt << 1, l, m); if (R > m) ret += query(d, rt << 1 | 1, m + 1, r); ret %= MOD; pushup(rt); return ret; } long long solve() { long long ret; long long u = (long long)L - 1; if (x == 0) ret = query(0, 1, 1, n); if (x == 1) { ret = query(1, 1, 1, n) - u * query(0, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; return ret; } if (x == 2) { ret = query(2, 1, 1, n) - 2LL * u * query(1, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + (long long)u * u % MOD * query(0, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; } if (x == 3) { ret = query(3, 1, 1, n) - 3LL * u * query(2, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + 3LL * u * u % MOD * query(1, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret - u * u % MOD * u % MOD * query(0, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; } if (x == 4) { ret = query(4, 1, 1, n) - 4LL * u * query(3, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + 6LL * u * u % MOD * query(2, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret - 4LL * u * u % MOD * u % MOD * query(1, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + u * u % MOD * u % MOD * u % MOD * query(0, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; } if (x == 5) { ret = query(5, 1, 1, n) - 5LL * u * query(4, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + 10LL * u * u % MOD * query(3, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret - 10LL * u * u % MOD * u % MOD * query(2, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret + 5LL * u * u % MOD * u % MOD * u % MOD * query(1, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; ret = ret - u * u % MOD * u % MOD * u % MOD * u % MOD * query(0, 1, 1, n) % MOD; ret = (ret % MOD + MOD) % MOD; } return ret; } int main() { scanf( %d%d , &n, &m); for (int i = int(1); i <= int(n); ++i) { long long t = 1; for (int j = int(0); j <= int(5); ++j) { pre[i][j] = pre[i - 1][j] + t, pre[i][j] %= MOD; t = t * i % MOD; } } build(1, 1, n); char s[5]; for (int i = int(1); i <= int(m); ++i) { scanf( %s%d%d%d , s, &L, &R, &x); if (s[0] == = ) { setv(1, 1, n); } else { printf( %I64d n , solve()); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int mark[201000 << 2]; int A[201000], n, m; struct ST { int val[2], las, len; void update(ST a, ST b) { b.val[1] -= a.las; b.val[0] += a.las; if (b.len & 1) b.las -= a.las; else b.las += a.las; val[0] = min(a.val[0], b.val[a.len & 1]); val[1] = min(a.val[1], b.val[(a.len & 1) ^ 1]); las = b.las; len = a.len + b.len; return; } } node[201000 << 2]; void build(int u, int L, int R) { if (L == R) { node[u].val[0] = 0; node[u].val[1] = node[u].las = A[L]; node[u].len = 1; return; } build((u << 1), L, ((L + R) >> 1)); build(((u << 1) | 1), (((L + R) >> 1) + 1), R); node[u].update(node[(u << 1)], node[((u << 1) | 1)]); } void down(int u, int L, int R) { if (!mark[u]) return; node[u].val[1] += mark[u]; if (node[u].len & 1) node[u].las += mark[u]; if (L < R) mark[(u << 1)] += mark[u], mark[((u << 1) | 1)] += mark[u]; mark[u] = 0; return; } void change(int u, int L, int R, int l, int r, int k) { down(u, L, R); if (L == l && R == r) { mark[u] += k; down(u, L, R); return; } if (r < (((L + R) >> 1) + 1)) down(((u << 1) | 1), (((L + R) >> 1) + 1), R), change((u << 1), L, ((L + R) >> 1), l, r, k); else if (l > ((L + R) >> 1)) down((u << 1), L, ((L + R) >> 1)), change(((u << 1) | 1), (((L + R) >> 1) + 1), R, l, r, k); else { change((u << 1), L, ((L + R) >> 1), l, ((L + R) >> 1), k); change(((u << 1) | 1), (((L + R) >> 1) + 1), R, (((L + R) >> 1) + 1), r, k); } node[u].update(node[(u << 1)], node[((u << 1) | 1)]); } ST query(int u, int L, int R, int l, int r) { down(u, L, R); if (L == l && R == r) return node[u]; if (r < (((L + R) >> 1) + 1)) return query((u << 1), L, ((L + R) >> 1), l, r); else if (l > ((L + R) >> 1)) return query(((u << 1) | 1), (((L + R) >> 1) + 1), R, l, r); else { ST a = query((u << 1), L, ((L + R) >> 1), l, ((L + R) >> 1)); ST b = query(((u << 1) | 1), (((L + R) >> 1) + 1), R, (((L + R) >> 1) + 1), r); a.update(a, b); return a; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); build(1, 1, n); for (scanf( %d , &m); m; m--) { int t, L, R, k; scanf( %d %d %d , &t, &L, &R); L++, R++; if (t == 1) { scanf( %d , &k); change(1, 1, n, L, R, k); } else { ST ans = query(1, 1, n, L, R); if (ans.val[0] >= 0 && ans.val[1] >= 1 && ans.las - (ans.len & 1) == 0) printf( 1 n ); else printf( 0 n ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKBUF_PP_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDLCLKP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_2_V
`define SKY130_FD_SC_HS__O21AI_2_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5e6 + 5; int a, b, c; long long gcd(long long a, long long b, long long& x, long long& y) { if (!b) { x = 0; y = 1; return a; } long long x1, y1; long long d = gcd(b, a % b, x1, y1); x = y1 - (a / b) * x1; y = x1; return d; } int main() { scanf( %d%d%d , &a, &b, &c); long long x, y, d; d = gcd(a, b, x, y); if (c % d != 0) puts( -1 ); else cout << -y * c / d << << -x * c / d << endl; }
|
#include <bits/stdc++.h> using namespace std; template <class T> struct node { T val; T lazy; int l, r; node* left; node* right; node(int l, int r) { this->l = l; this->r = r; this->left = nullptr; this->right = nullptr; } }; template <class T, int SZ> struct segtree { T combIdentity = -1e9; T comb(T l, T r) { return max(l, r); } T pushIdentity = 0; void push(node<T>* n) { n->val += n->lazy; if (n->l != n->r) { n->left->lazy += n->lazy; n->right->lazy += n->lazy; } n->lazy = pushIdentity; } node<T>* root; segtree() { int ub = 1; while (ub < SZ) ub *= 2; root = new node<T>(0, ub - 1); root->val = pushIdentity; root->lazy = pushIdentity; } void propagate(node<T>* n) { if (n->l != n->r) { int mid = ((n->l) + (n->r)) / 2; if (n->left == nullptr) { n->left = new node<T>(n->l, mid); n->left->val = pushIdentity; n->left->lazy = pushIdentity; } if (n->right == nullptr) { n->right = new node<T>(mid + 1, n->r); n->right->val = pushIdentity; n->right->lazy = pushIdentity; } } push(n); } void updN(node<T>* n, int i1, int i2, T val) { propagate(n); if (i2 < n->l || i1 > n->r) return; if (i1 <= n->l && i2 >= n->r) { n->lazy = val; push(n); return; } updN(n->left, i1, i2, val); updN(n->right, i1, i2, val); n->val = comb(n->left->val, n->right->val); } void upd(int i1, int i2, T val) { updN(root, i1, i2, val); } T queryN(node<T>* n, int i1, int i2) { propagate(n); if (i2 < n->l || i1 > n->r) return combIdentity; if (n->l >= i1 && n->r <= i2) return n->val; T a = combIdentity; if (n->left != nullptr) a = comb(a, queryN(n->left, i1, i2)); if (n->right != nullptr) a = comb(a, queryN(n->right, i1, i2)); return a; } T query(int i1, int i2) { return queryN(root, i1, i2); } }; const int MAX_M = 20020; const int MAX_N = 52; int n, m, k; int arr[MAX_N][MAX_M]; int pref[MAX_N][MAX_M]; int dp[MAX_N][MAX_M]; int getsum(int i, int j) { if (j == 0) return pref[i][j + k - 1]; else { return pref[i][j + k - 1] - pref[i][j - 1]; } } int get(int i, int j) { return getsum(i, j) + getsum(i + 1, j); } pair<int, int> getBounds(int j) { int l = j - k + 1; int r = j; l = max(0, l); r = min(m - k, r); return make_pair(l, r); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> arr[i][j]; for (int i = 0; i < n; i++) { pref[i][0] = arr[i][0]; for (int j = 1; j < m; j++) pref[i][j] = pref[i][j - 1] + arr[i][j]; } for (int i = 0; i < m - k + 1; i++) dp[0][i] = get(0, i); for (int i = 1; i < n; i++) { segtree<int, MAX_M> st; for (int j = 0; j < m - k + 1; j++) st.upd(j, j, dp[i - 1][j]); for (int j = 0; j < k; j++) { pair<int, int> b = getBounds(j); st.upd(b.first, b.second, -arr[i][j]); } for (int j = 0; j < m - k + 1; j++) { dp[i][j] = st.query(0, m - k) + get(i, j); pair<int, int> b = getBounds(j); st.upd(b.first, b.second, arr[i][j]); b = getBounds(j + k); st.upd(b.first, b.second, -arr[i][j + k]); } } int res = 0; for (int i = 0; i < m - k + 1; i++) res = max(res, dp[n - 1][i]); return cout << res << n , 0; ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND4BB_FUNCTIONAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int input; vector<int> ret; cin >> input; for (int i = 1; i < input; i += 2) { ret.push_back(i + 1); ret.push_back(i); } if (ret.empty() || ret.size() != input) ret = {-1}; for (auto &d : ret) { cout << d << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; long long gcd(long long a, long long b) { while (b > 0) { long long p = a % b; a = b; b = p; } return a; } long long bexp(long long a, int b) { long long res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } long long bexpM(long long a, int b) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % M; a = (a * a) % M; b >>= 1; } return res; } long long nCk(int n, int k) { long long res = 1; for (int i = k + 1; i < n + 1; i++) res = res * i; long long p = 1; for (int i = 2; i < n - k + 1; i++) p = p * i; res = res / p; return res; } long long nCkM(int n, int k) { long long res = 1; for (int i = k + 1; i < n + 1; i++) res = (res * i) % M; long long p = 1; for (int i = 2; i < n - k + 1; i++) p = (p * i) % M; res = (res * bexpM(p, M - 2)) % M; return res; } const int N = 2e5; long long st[N][18]; long long q(int l, int s, int n) { int i = 0; while ((1 << (i + 1)) < s) i++; return gcd(st[l][i], st[l - (1 << i) + s][i]); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int u; cin >> u; for (int g = 0; g < u; g++) { int n; cin >> n; long long a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } n--; for (int i = 0; i < n; i++) { st[i][0] = abs(a[i + 1] - a[i]); } for (int i = 1; i < log2(n); i++) { for (int j = 0; j < n - (1 << (i - 1)); j++) { st[j][i] = gcd(st[j][i - 1], st[j + (1 << (i - 1))][i - 1]); } } int l = 1; int r = n; while (l < r) { int m = (l + r + 1) / 2; long long b[n - m + 1]; for (int i = 0; i < n - m + 1; i++) { b[i] = q(i, m, n); } bool bo = 1; for (int i = 0; i < n - m + 1; i++) { if (b[i] != 1) bo = 0; } if (bo) r = m - 1; else l = m; } bool bo = 1; for (int i = 0; i < n; i++) { if (st[i][0] > 1) bo = 0; } if (bo) cout << 1 n ; else cout << l + 1 << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_PP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_clkgen (
// mmcm reset
mmcm_rst,
// drp interface
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00040063;
parameter PCORE_ID = 0;
// mmcm reset
output mmcm_rst;
// drp interface
output up_drp_sel;
output up_drp_wr;
output [11:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [15:0] up_drp_rdata;
input up_drp_ready;
input up_drp_locked;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_drp_sel = 'd0;
reg up_drp_wr = 'd0;
reg up_drp_status = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] up_drp_rdata_hold = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_mmcm_preset_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_drp_sel <= 'd0;
up_drp_wr <= 'd0;
up_drp_status <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
up_drp_rdata_hold <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel <= 1'b1;
up_drp_wr <= ~up_wdata[28];
end else begin
up_drp_sel <= 1'b0;
up_drp_wr <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold <= up_drp_rdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h17: up_rdata <= {31'd0, up_drp_locked};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(up_clk), .rst(mmcm_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long a[100005]; deque<long long> q; long long mi[100005]; void add_q(long long ae) { while (!q.empty() && q.back() > ae) q.pop_back(); q.push_back(ae); } void pop_q(long long re) { if (!q.empty() && q.front() == re) q.pop_front(); } void solve() { long long n, c, sum = 0; cin >> n >> c; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } for (int i = 0; i < c; i++) { add_q(a[i]); } mi[0] = q.front(); for (int i = c; i < n; i++) { pop_q(a[i - c]); add_q(a[i]); mi[i - c + 1] = q.front(); } long long maxc = 0; long long res = 0; for (int i = 0; i < c; i++) res = max(res, mi[i]); for (int i = c; i < n; i++) { maxc = max(maxc, mi[i - c]); mi[i] += maxc; res = max(res, mi[i]); } cout << sum - res; } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; if (n == 2 || n == 3 || n == 4 || n == 5 || n == 6 || n == 7) cout << 1 << endl; else if (n % 7 == 1) cout << ((n - 1) / 7) + 1 << endl; else cout << (n / 7) + 1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; int dp[510][510]; long long MOD; vector<string> v; long long nc2(long long num) { return (num * (num - 1)) / 2; } int recur(int ones, int zeros) { if (ones == 0 and zeros == 0) return 1; if (dp[ones][zeros] != -1) { return dp[ones][zeros] % MOD; } long long ret = 0; if (ones > 1) { ret = (ret + ((recur(ones - 2, zeros) * nc2(ones)) % MOD)) % MOD; } if (zeros > 1) { ret = (ret + ((recur(ones + 2, zeros - 2) * nc2(zeros)) % MOD)) % MOD; } if (ones >= 1 && zeros >= 1) { ret = (ret + ((recur(ones, zeros - 1) * ((ones * zeros) % MOD)) % MOD)) % MOD; } dp[ones][zeros] = ret % MOD; return dp[ones][zeros]; } int solve(int n, int m) { int ones = 0; int zeros = 0; for (int i = 0; i < n; i++) { int cnt = 0; for (int j = 0; j < m; j++) { if (v[j][i] == 1 ) cnt++; } if (cnt == 1) ones++; if (cnt == 0) zeros++; } memset(dp, -1, sizeof(dp)); int res = recur(ones, zeros); return res; } int main() { int n, m; cin >> n >> m >> MOD; string line = ; for (int i = 0; i < m; i++) { cin >> line; v.push_back(line); } int res = solve(n, m); cout << res << endl; return 0; }
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8)
)(
input clk,
input rst,
//Write Address Channel
input AXIML_AWVALID,
input [ADDR_WIDTH - 1: 0] AXIML_AWADDR,
output AXIML_AWREADY,
//Write Data Channel
input AXIML_WVALID,
output AXIML_WREADY,
input [STROBE_WIDTH - 1:0] AXIML_WSTRB,
input [DATA_WIDTH - 1: 0] AXIML_WDATA,
//Write Response Channel
output AXIML_BVALID,
input AXIML_BREADY,
output [1:0] AXIML_BRESP,
//Read Address Channel
input AXIML_ARVALID,
output AXIML_ARREADY,
input [ADDR_WIDTH - 1: 0] AXIML_ARADDR,
//Read Data Channel
output AXIML_RVALID,
input AXIML_RREADY,
output [1:0] AXIML_RRESP,
output [DATA_WIDTH - 1: 0] AXIML_RDATA
);
//Parameters
//Registers
reg r_rst;
always @ (*) r_rst = rst;
reg [3:0] test_id = 0;
//submodules
axi_lite_demo #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.INVERT_AXI_RESET (0 )
) dut (
.clk (clk ),
.rst (r_rst ),
.i_awvalid (AXIML_AWVALID ),
.i_awaddr (AXIML_AWADDR ),
.o_awready (AXIML_AWREADY ),
.i_wvalid (AXIML_WVALID ),
.o_wready (AXIML_WREADY ),
.i_wdata (AXIML_WDATA ),
.o_bvalid (AXIML_BVALID ),
.i_bready (AXIML_BREADY ),
.o_bresp (AXIML_BRESP ),
.i_arvalid (AXIML_ARVALID ),
.o_arready (AXIML_ARREADY ),
.i_araddr (AXIML_ARADDR ),
.o_rvalid (AXIML_RVALID ),
.i_rready (AXIML_RREADY ),
.o_rresp (AXIML_RRESP ),
.o_rdata (AXIML_RDATA )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; string s; cin >> s; vector<long long int> col; int zero = 0, one = 0; col.push_back(0); for (int i = 1; i < s.size(); i++) { if (s[i] >= s[zero]) { col.push_back(0); zero = i; } else { if (s[i] < s[one] && one != 0) { cout << NO ; return 0; } else { col.push_back(1); one = i; } } } cout << YES << n ; for (auto i : col) cout << i; return 0; }
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
// CLK is 24Mhz. MCLK is divided by two (12Mhz). 24Mhz divide by 16 produces SCLK.
// Divide by 48 produces LRCK.
// produce LRCK = 32kHz. We output 16-bit samples, but internally the DAC
// is in 24-bit mode. SCLK ratio is 48 * 32kHz.
module SoundDriver(input CLK, input [15:0] write_data, input write_left, input write_right,
output AUD_MCLK, output AUD_LRCK, output AUD_SCK, output AUD_SDIN);
reg lrck;
reg [15:0] leftbuf;
reg [15:0] rightbuf;
reg [16:0] currbuf;
reg [3:0] sclk_div;
reg [4:0] bitcnt_24; // Counts 0-23
wire [4:0] bitcnt_24_new = bitcnt_24 + 1;
always @(posedge CLK) begin
// Buffer one sample of each channel.
if (write_left) leftbuf <= write_data;
if (write_right) rightbuf <= write_data;
// Divide 24MHz by 16 to produce the SCLK frequency (48 * 32000) as well
// as the 12MHz MCLK frequency.
sclk_div <= sclk_div + 1;
// Output new bits on the falling edge of MCLK so that values are
// stable once MCLK rises.
if (sclk_div == 4'b1111) begin
// This runs at the SCLK frequency. Output next bit.
currbuf <= {currbuf[15:0], 1'b0};
bitcnt_24 <= bitcnt_24_new;
if (bitcnt_24_new[4:3] == 2'b11) begin
bitcnt_24[4:3] <= 2'b00; // 24 -> 0
lrck <= !lrck;
currbuf[15:0] <= lrck ? leftbuf : rightbuf;
end
end
end
assign AUD_MCLK = sclk_div[0];
assign AUD_SCK = 1; // Internal emphasis turned off
assign AUD_SDIN = currbuf[16];
assign AUD_LRCK = lrck;
endmodule
|
module memory (inout [31:0] Data, output reg MFC, input MFA, ReadWrite, input [7:0] Address, input wordByte,Reset);
//dataOut: bus to return value for Load instruction
//dataIn: bus to input value to store fot Store instruction
//MFA: memory function active (memory on)
//MFC: memory function complete (memory finished)
//readWrite: load or store, 1 for load/read, 0 for store/write
//byteWord: 1 for byte, 0 for word
//halfDoubleWord: 1 for halfword, 0 for doubleword
reg [31:0] Data_Buff;
reg [7:0] Mem[0:255];///////////////////////////////////////////////////////////////////
//Mem represents the 256 spaces available in memory, 1 byte each
wire [7:0] dataByte[0:3];
//4 bytes to store a 32 bit value
reg [7:0] tempAddress;
assign dataByte[0] = Data[31:24];
assign dataByte[1] = Data[23:16];
assign dataByte[2] = Data[15:8];
assign dataByte[3] = Data[7:0];
assign Data = Data_Buff;
integer i;
//****************for testing purposes ***********************
integer fd, code, index;
reg [7:0] data[3:0];
always@(posedge Reset) begin
$display("Dumping ROM...");
index = 0;
while (index < 255) begin
$display("%d Memory Content Binary=%b Decimal=%d,Hex=%h",index,Mem[index],Mem[index],Mem[index]);
index = index + 1;
end
$display("Loading test program to ROM...");
fd = $fopen("memory.dat","r");
index = 0;
while (!($feof(fd))) begin
code = $fscanf(fd, "%b %b %b %b\n", data[0],data[1],data[2],data[3]);
Mem[index]=data[0];
Mem[index+1]=data[1];
Mem[index+2]=data[2];
Mem[index+3]=data[3];
$display("%d Reading from file=%b %b %b %b, Memory Content=%b",index,data[0],data[1],data[2],data[3],Mem[index]);
index = index + 4;
end
while (index < 255) begin
Mem[index]=0;
index = index + 1;
end
$fclose(fd);
$display("Test Program loaded in ROM...");
$display("Memory");
index = 0;
while (index < 255) begin
$display("%d Memory Content Binary=%b Decimal=%d,Hex=%h",index,Mem[index],Mem[index],Mem[index]);
index = index + 1;
end
$display("Finished");
Data_Buff = 32'hzzzz_zzzz;
end
//*************************************************************
always @ (posedge MFA)//********************************
if(MFA) begin
$display("Memory Function Active");
MFC = 0;Data_Buff = 32'hzzzz_zzzz;
$display("Memory Function Complete: %b", MFC);
//---0--Store/Write to memory------
if(ReadWrite==0)begin
//------Byte------
if(!wordByte) begin
$display("Store a byte");
Mem[Address] <= dataByte[3];
Mem[Address+1] <= 8'b0;
Mem[Address+2] <= 8'b0;
Mem[Address+3] <= 8'b0;
$display("Storing Least significant byte %h in address %d", dataByte[3], Address);
$display("Mem[Address]: %h", Mem[Address]);
end
//------Word------
else begin
$display("Store a word");
Mem[Address] <= dataByte[3];
Mem[Address+1] <= dataByte[2];
Mem[Address+2] <= dataByte[1];
Mem[Address+3] <= dataByte[0];
$display("Mem[Address]: %h", Mem[Address]);
$display("Mem[Address+1]: %h", Mem[Address+1]);
$display("Mem[Address+2]: %h", Mem[Address+2]);
$display("Mem[Address+3]: %h", Mem[Address+3]);
end
//--1---Load/Read from memory------
end else begin
if(wordByte) begin
Data_Buff[31:24] <= Mem[Address];
Data_Buff[23:16] <= Mem[Address+1];
Data_Buff[15:8] <= Mem[Address+2];
Data_Buff[7:0] <= Mem[Address+3];
end else begin
Data_Buff[7:0] <= Mem[Address];
Data_Buff[15:8] <= 8'b0;
Data_Buff[23:16] <= 8'b0;
Data_Buff[31:24] <= 8'b0;
end
end
//Finished writing to memory
$display("Memory Function Complete: %b", MFC);
while(MFA==1)begin
#1 MFC = 1;
end // busy waiting
MFC = 0;
Data_Buff = 32'hzzzz_zzzz; // errase value from memory
end
endmodule
//iverilog -o memory MYMEM256B.v
|
#include <bits/stdc++.h> using namespace std; size_t ham_dist(const string &a, const string &b) { size_t ct = 0; for (size_t i = 0; i < a.size(); ++i) if (a[i] != b[i]) ++ct; return ct; } string opp(const string &a) { string r = ; for (size_t i = 0; i < a.size(); ++i) r += (a[i] == 0 ? 1 : 0 ); return r; } string read_line(size_t m) { string r; for (size_t j = 0; j < m; ++j) { char c[2]; cin >> c; r += string(c); } return r; } string string_from_int(size_t len, size_t z) { string o; for (size_t i = 0; i < len; ++i) { if (z & (1 << i)) o += 1 ; else o += 0 ; } return o; } int main() { size_t n, m, k; cin >> n >> m >> k; map<string, size_t> counts; vector<string> mat; mat.reserve(n); for (size_t i = 0; i < n; ++i) { string l = read_line(m); mat.push_back(l); } if (n < m) { vector<string> newmat = mat; swap(n, m); mat.clear(); mat.reserve(n); for (size_t i = 0; i < n; ++i) { string p; for (size_t j = 0; j < m; ++j) { p += newmat[j][i]; } mat.push_back(p); } } for (size_t i = 0; i < n; ++i) { string &l = mat[i]; if (counts.find(l) == counts.end()) counts[l] = 0; ++counts[l]; } bool feasible = false; if (counts.size() <= k + 2) { if (n <= k) { for (size_t z = 0; z < ((size_t)1 << m); ++z) { string l = string_from_int(m, z); if (counts.find(l) == counts.end()) counts[l] = 0; } } for (map<string, size_t>::iterator it = counts.begin(); it != counts.end(); ++it) { size_t cost = 0; for (map<string, size_t>::iterator jt = counts.begin(); jt != counts.end(); ++jt) { if (jt->second == 0) continue; size_t cost_per = ham_dist(it->first, jt->first); cost_per = min(cost_per, ham_dist(opp(it->first), jt->first)); cost += cost_per * jt->second; } if (cost <= k) { feasible = true; k = cost; } } } if (!feasible) { cout << -1 << endl; } else { cout << k << endl; } return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v2_3_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int pos[100010]; int dx[] = {0, 1, 0, -1}, dy[] = {1, 0, -1, 0}; bool check(int i, int j) { int x = (i - 1) / m + 1, y = (i - 1) % m + 1; int x2 = (j - 1) / m + 1, y2 = (j - 1) % m + 1; for (int k = 0; k < 4; k++) if (x + dx[k] == x2 && y + dy[k] == y2) return true; return false; } bool dfs(int i) { if (i == n * m + 1) return true; int x = (i - 1) / m + 1, y = (i - 1) % m + 1; for (int j = i; j <= n * m; j++) { swap(pos[i], pos[j]); if (x != 1 && check(pos[i], pos[(x - 2) * m + y])) continue; if (y != 1 && check(pos[i], pos[(x - 1) * m + y - 1])) continue; if (dfs(i + 1)) return true; swap(pos[i], pos[j]); } return false; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) pos[(i - 1) * m + j] = (i - 1) * m + j; if (!dfs(1)) { puts( NO ); return 0; } puts( YES ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) printf( %d , pos[(i - 1) * m + j]); putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int sub_tern(int c, int a) { int temp_c; int temp_a; int diff; long sum = 0; int three_power = 1; while (c > 0 || a > 0) { temp_c = c % 3; c = c / 3; temp_a = a % 3; a = a / 3; diff = temp_c - temp_a; if (diff < 0) { diff += 3; } sum += (long)diff * (long)three_power; three_power *= 3; } return sum; } int main() { int a; int c; cin >> a >> c; if (a == c) { cout << 0 n ; return 0; } cout << sub_tern(c, a) << n ; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize(3) using namespace std; const int Mod = 1e9 + 7; const int N = 5e5 + 100; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; inline long long dpow(long long a, long long b) { long long r = 1, t = a; while (b) { if (b & 1) r = (r * t) % Mod; b >>= 1; t = (t * t) % Mod; } return r; } inline long long fpow(long long a, long long b) { long long r = 1, t = a; while (b) { if (b & 1) r = (r * t); b >>= 1; t = (t * t); } return r; } struct node { int id, w; bool operator<(const node &oth) const { return w > oth.w; } }; struct Ask { int op, x; } qi[N]; pair<int, int> eg[N]; set<node> s[N]; int fa[N], sz[N], n, m, q; int a[N]; bool vis[N]; stack<pair<int, int> > st; void Init() { for (int i = 1; i <= n; i++) fa[i] = i, sz[i] = 1; } int Find(int x) { while (x != fa[x]) x = fa[x]; return x; } void Merge(int x, int y) { x = Find(x); y = Find(y); if (x == y) { st.push({0, 0}); return; } if (sz[x] > sz[y]) swap(x, y); fa[x] = y; st.push({x, y}); sz[y] += sz[x]; for (auto it : s[x]) s[y].insert(it); } void Cancle() { int x = st.top().first, y = st.top().second; st.pop(); if (!x && !y) return; fa[x] = x; sz[y] -= sz[x]; for (auto it : s[x]) { if (s[y].find(it) != s[y].end()) s[y].erase(it); } } int main() { cin >> n >> m >> q; Init(); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), s[i].insert({i, a[i]}); for (int i = 1; i <= m; i++) scanf( %d %d , &eg[i].first, &eg[i].second); for (int i = 1; i <= q; i++) { scanf( %d %d , &qi[i].op, &qi[i].x); if (qi[i].op == 2) vis[qi[i].x] = true; } for (int i = 1; i <= m; i++) if (!vis[i]) Merge(eg[i].first, eg[i].second); for (int i = q; i >= 1; i--) { if (qi[i].op == 1) continue; int u = eg[qi[i].x].first; int v = eg[qi[i].x].second; Merge(u, v); } for (int i = 1; i <= q; i++) { int op = qi[i].op, x = qi[i].x; if (op == 1) { int u = Find(x); while (!s[u].empty() && !a[s[u].begin()->id]) s[u].erase(s[u].begin()); if (s[u].empty()) puts( 0 ); else { printf( %d n , s[u].begin()->w); a[s[u].begin()->id] = 0; } } else Cancle(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[4] = {-1, 0, 0, 1}; int dy[4] = {0, -1, 1, 0}; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { if (a.first == b.first) return a.second < b.second; return (a.first < b.first); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long x, y, t, c; cin >> x >> y; if (y == 0) { cout << No << endl; return 0; } if (y == 1) { if (x > 0) { cout << No << endl; return 0; } } t = y - 1; t = x - t; if (t % 2 == 0 && t >= 0) { cout << Yes << endl; return 0; } cout << No << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_BLACKBOX_V
`define SKY130_FD_SC_LS__O41A_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
);
wire mode_vcchib;
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
supply1 vccd;
supply1 vcchib;
supply1 vdda;
supply1 vddio;
supply1 vddio_q;
supply0 vssa;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply1 vswitch;
wire pwr_good_xres_tmp = 1;
wire pwr_good_xres_h_n = 1;
wire pwr_good_pullup = 1;
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, vddio);
buf p5 (TIE_LO_ESD, vssio);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
$setuphold (posedge ENABLE_VDDIO, posedge ENABLE_H, tsetup, thold, notifier_enable_h);
$setuphold (negedge ENABLE_H, negedge ENABLE_VDDIO, tsetup, thold, notifier_enable_h);
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(0), cin.tie(0); ; int n, m; cin >> n >> m; vector<vector<char>> v(n, vector<char>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> v[i][j]; bool st = 1; int mx = 0; set<int> se; for (int i = 0; i < n; i++) { int s = -1, g = -1; for (int j = 0; j < m; j++) { if (v[i][j] == G ) g = j; else if (v[i][j] == S ) s = j; } if (s < g) st = 0; else se.insert(s - g); } if (st) cout << se.size(); else cout << -1; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(time(0)); const long long N = 3e5 + 7; const long long MOD = 1e9 + 7; long long pw(long long b, long long p) { b %= MOD; long long res = 1; while (p > 0) { if (p & 1) res = res * b % MOD; b = b * b % MOD; p >>= 1; } return res; } long long n, m, cur; vector<vector<pair<long long, char>>> g(107); bool vis[107][107][26], dp[107][107][26]; bool dfs(long long u, long long v, char ch) { if (vis[u][v][ch - a ]) return dp[u][v][ch - a ]; for (auto i : g[u]) { if (i.second >= ch && !dfs(v, i.first, i.second)) dp[u][v][ch - a ] = 1; } vis[u][v][ch - a ] = 1; return dp[u][v][ch - a ]; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; long long u, v; char ch; for (long long i = 1; i < m + 1; i++) { cin >> u >> v >> ch; g[u].emplace_back(v, ch); } for (long long i = 1; i < n + 1; i++) { for (long long j = 1; j < n + 1; j++) { if (dfs(i, j, a )) cout << A ; else cout << B ; } cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFBBN_BLACKBOX_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int p[100003]; int n; int main() { int i; scanf( %d , &n); if (n == 1) { printf( 1 n ); return 0; } if (n == 2) { printf( -1 n ); return 0; } if (n % 2 != 0) p[n / 2 + 1] = n / 2 + 1; p[1] = 2; p[2] = n; p[n] = n - 1; p[n - 1] = 1; for (i = 3; i < n / 2 + 1; i++) { if (i % 2 != 0) p[i] = p[i - 2] + 2; else p[i] = p[i - 2] - 2; } int coun = 0; if (n % 2 == 0) { for (i = n - 2; i > n / 2; i--) { if (coun % 2 == 0) p[i] = p[i + 2] - 2; else p[i] = p[i + 2] + 2; coun++; } } else { for (i = n - 2; i > n / 2 + 1; i--) { if (coun % 2 == 0) p[i] = p[i + 2] - 2; else p[i] = p[i + 2] + 2; coun++; } } bool fl = true; for (i = 1; i <= n; i++) if (p[p[i]] != n - i + 1) fl = false; if (fl) { printf( %d , p[1]); for (i = 2; i <= n; i++) printf( %d , p[i]); printf( n ); } else printf( -1 n ); return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : (-x); } template <class T> T sqr(T x) { return x * x; } int a[100000][2]; void save() { printf( -1 n ); exit(0); } const int n = 65536; int tree[57000 * 4 + 10]; int delta[57000 * 4 + 10]; void Set(int pos, int newval, int i = 1, int l = 0, int r = n - 1) { if (l == r) { tree[i] = newval; return; } int m = (l + r) / 2; if (pos <= m) Set(pos, newval, i * 2, l, m); else Set(pos, newval, i * 2 + 1, m + 1, r); tree[i] = min(tree[2 * i], tree[2 * i + 1]); } void multiinc(int l0, int r0, int val, int i = 1, int l = 0, int r = n - 1) { if (l >= l0 && r <= r0) { delta[i] += val; return; } if (min(r, r0) < max(l, l0)) return; int m = (l + r) / 2; multiinc(l0, r0, val, 2 * i, l, m); multiinc(l0, r0, val, 2 * i + 1, m + 1, r); tree[i] = min(tree[2 * i] + delta[2 * i], tree[2 * i + 1] + delta[2 * i + 1]); } int get(int l0, int r0, int i = 1, int l = 0, int r = n - 1) { if (min(r, r0) < max(l, l0)) return 100000000; if (l >= l0 && r <= r0) return tree[i] + delta[i]; int m = (l + r) / 2; return delta[i] + min(get(l0, r0, 2 * i, l, m), get(l0, r0, 2 * i + 1, m + 1, r)); } int main() { memset(tree, 0, sizeof(tree)); string s; cin >> s; for (int i = 0; i < ((int)((s).size())); i++) { if (s[i] != ? ) continue; scanf( %d%d , &a[i][0], &a[i][1]); } set<pair<int, int> > up, down; int cur = 0; long long cost = 0; for (int i = 0; i < ((int)((s).size())); i++) { if (s[i] == ? ) { if (a[i][0] < a[i][1]) { s[i] = ( ; cost += a[i][0]; down.insert(pair<int, int>(a[i][1] - a[i][0], i)); cur++; } else { s[i] = ) ; cost += a[i][1]; up.insert(pair<int, int>(a[i][0] - a[i][1], i)); cur--; } } else { cur += s[i] == ( ? 1 : -1; } if (cur < 0) { if (up.empty()) save(); set<pair<int, int> >::iterator it = up.begin(); cost += it->first; s[it->second] = ( ; cur += 2; up.erase(it); down.clear(); } } int ss = 0; for (int i = 0; i < ((int)((s).size())); i++) { ss += s[i] == ( ? 1 : -1; Set(i + 1, ss); } while (cur > 0) { if (down.empty()) save(); set<pair<int, int> >::iterator it = down.begin(); int delt = it->first; int ind = it->second; down.erase(it); multiinc(ind + 1, ((int)((s).size())), -2); int opt = get(1, ((int)((s).size()))); if (opt < 0) { multiinc(ind + 1, ((int)((s).size())), 2); continue; } cur -= 2; s[ind] = ) ; cost += delt; } cout << cost << n << s << n ; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// ======================================================================
module sub
(
input clk,
input fastclk,
input reset_l
);
// Example counter/flop
reg [31:0] count_f;
always_ff @ (posedge fastclk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_f <= 32'h0;
// End of automatics
end
else begin
count_f <= count_f + 1;
end
end
// Another example flop
reg [31:0] count_c;
always_ff @ (posedge clk) begin
if (!reset_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
count_c <= 32'h0;
// End of automatics
end
else begin
count_c <= count_c + 1;
if (count_c >= 3) begin
$display("[%0t] fastclk is %0d times faster than clk\n",
$time, count_f/count_c);
// This write is a magic value the Makefile uses to make sure the
// test completes successfully.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// An example assertion
always_ff @ (posedge clk) begin
AssertionExample: assert (!reset_l || count_c<100);
end
// And example coverage analysis
cover property (@(posedge clk) count_c==3);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:02:57 01/08/2017
// Design Name:
// Module Name: number
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module number(
input clk,
input rst,
input [3:0] num,
input [10:0] x,
input [10:0] y,
input [10:0] poX,
input [10:0] poY,
output reg pic
);
wire [5:0] n00,n01,n02,n03,n04,n05;
wire [5:0] n10,n11,n12,n13,n14,n15;
wire [5:0] n20,n21,n22,n23,n24,n25;
wire [5:0] n30,n31,n32,n33,n34,n35;
wire [5:0] n40,n41,n42,n43,n44,n45;
wire [5:0] n50,n51,n52,n53,n54,n55;
wire [5:0] n60,n61,n62,n63,n64,n65;
wire [5:0] n70,n71,n72,n73,n74,n75;
wire [5:0] n80,n81,n82,n83,n84,n85;
wire [5:0] n90,n91,n92,n93,n94,n95;
//0
assign n00 = 30;
assign n01 = 18;
assign n02 = 18;
assign n03 = 18;
assign n04 = 18;
assign n05 = 30;
//1
assign n10 = 4;
assign n11 = 12;
assign n12 = 4;
assign n13 = 4;
assign n14 = 4;
assign n15 = 4;
//2
assign n20 = 12;
assign n21 = 18;
assign n22 = 1;
assign n23 = 2;
assign n24 = 12;
assign n25 = 63;
//3
assign n30 = 28;
assign n31 = 18;
assign n32 = 2;
assign n33 = 12;
assign n34 = 2;
assign n35 = 28;
//4
assign n40 = 10;
assign n41 = 18;
assign n42 = 18;
assign n43 = 31;
assign n44 = 2;
assign n45 = 2;
//5
assign n50 = 30;
assign n51 = 16;
assign n52 = 30;
assign n53 = 2;
assign n54 = 2;
assign n55 = 30;
//6
assign n60 = 12;
assign n61 = 18;
assign n62 = 16;
assign n63 = 30;
assign n64 = 18;
assign n65 = 30;
//7
assign n70 = 30;
assign n71 = 18;
assign n72 = 6;
assign n73 = 4;
assign n74 = 12;
assign n75 = 8;
//8
assign n80 = 30;
assign n81 = 18;
assign n82 = 30;
assign n83 = 18;
assign n84 = 18;
assign n85 = 30;
//9
assign n90 = 30;
assign n91 = 18;
assign n92 = 18;
assign n93 = 30;
assign n94 = 2;
assign n95 = 2;
// pic
always@(posedge clk, posedge rst)
begin
if(rst) pic <= 0;
else begin
if(poX>=x && poX<=x+5) begin
case(num)
0: begin
case(y-poY)
0:pic <= n00[poX-x];
1:pic <= n01[poX-x];
2:pic <= n02[poX-x];
3:pic <= n03[poX-x];
4:pic <= n04[poX-x];
5:pic <= n05[poX-x];
default:pic<=0;
endcase
end
1: begin
case(y-poY)
0:pic <= n10[poX-x];
1:pic <= n11[poX-x];
2:pic <= n12[poX-x];
3:pic <= n13[poX-x];
4:pic <= n14[poX-x];
5:pic <= n15[poX-x];
default:pic<=0;
endcase
end
2: begin
case(y-poY)
0:pic <= n20[poX-x];
1:pic <= n21[poX-x];
2:pic <= n22[poX-x];
3:pic <= n23[poX-x];
4:pic <= n24[poX-x];
5:pic <= n25[poX-x];
default:pic<=0;
endcase
end
3: begin
case(y-poY)
0:pic <= n30[poX-x];
1:pic <= n31[poX-x];
2:pic <= n32[poX-x];
3:pic <= n33[poX-x];
4:pic <= n34[poX-x];
5:pic <= n35[poX-x];
default:pic<=0;
endcase
end
4: begin
case(y-poY)
0:pic <= n40[poX-x];
1:pic <= n41[poX-x];
2:pic <= n42[poX-x];
3:pic <= n43[poX-x];
4:pic <= n44[poX-x];
5:pic <= n45[poX-x];
default:pic<=0;
endcase
end
5: begin
case(y-poY)
0:pic <= n50[poX-x];
1:pic <= n51[poX-x];
2:pic <= n52[poX-x];
3:pic <= n53[poX-x];
4:pic <= n54[poX-x];
5:pic <= n55[poX-x];
default:pic<=0;
endcase
end
6: begin
case(y-poY)
0:pic <= n60[poX-x];
1:pic <= n61[poX-x];
2:pic <= n62[poX-x];
3:pic <= n63[poX-x];
4:pic <= n64[poX-x];
5:pic <= n65[poX-x];
default:pic<=0;
endcase
end
7: begin
case(y-poY)
0:pic <= n70[poX-x];
1:pic <= n71[poX-x];
2:pic <= n72[poX-x];
3:pic <= n73[poX-x];
4:pic <= n74[poX-x];
5:pic <= n75[poX-x];
default:pic<=0;
endcase
end
8: begin
case(y-poY)
0:pic <= n80[poX-x];
1:pic <= n81[poX-x];
2:pic <= n82[poX-x];
3:pic <= n83[poX-x];
4:pic <= n84[poX-x];
5:pic <= n85[poX-x];
default:pic<=0;
endcase
end
9: begin
case(y-poY)
0:pic <= n90[poX-x];
1:pic <= n91[poX-x];
2:pic <= n92[poX-x];
3:pic <= n93[poX-x];
4:pic <= n94[poX-x];
5:pic <= n95[poX-x];
default:pic<=0;
endcase
end
default: pic <= 0;
endcase
end else pic<=0;
end
end
endmodule
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