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/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xfcp_switch
*/
module test_xfcp_switch_4;
// Parameters
parameter PORTS = 4;
parameter XFCP_ID_TYPE = 16'h0100;
parameter XFCP_ID_STR = "XFCP Switch";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg [PORTS*8-1:0] down_xfcp_in_tdata = 0;
reg [PORTS-1:0] down_xfcp_in_tvalid = 0;
reg [PORTS-1:0] down_xfcp_in_tlast = 0;
reg [PORTS-1:0] down_xfcp_in_tuser = 0;
reg [PORTS-1:0] down_xfcp_out_tready = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [PORTS-1:0] down_xfcp_in_tready;
wire [PORTS*8-1:0] down_xfcp_out_tdata;
wire [PORTS-1:0] down_xfcp_out_tvalid;
wire [PORTS-1:0] down_xfcp_out_tlast;
wire [PORTS-1:0] down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
up_xfcp_in_tdata,
up_xfcp_in_tvalid,
up_xfcp_in_tlast,
up_xfcp_in_tuser,
up_xfcp_out_tready,
down_xfcp_in_tdata,
down_xfcp_in_tvalid,
down_xfcp_in_tlast,
down_xfcp_in_tuser,
down_xfcp_out_tready
);
$to_myhdl(
up_xfcp_in_tready,
up_xfcp_out_tdata,
up_xfcp_out_tvalid,
up_xfcp_out_tlast,
up_xfcp_out_tuser,
down_xfcp_in_tready,
down_xfcp_out_tdata,
down_xfcp_out_tvalid,
down_xfcp_out_tlast,
down_xfcp_out_tuser
);
// dump file
$dumpfile("test_xfcp_switch_4.lxt");
$dumpvars(0, test_xfcp_switch_4);
end
xfcp_switch #(
.PORTS(PORTS),
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR)
)
UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if ((n == 1 && k > 0) || (k == 0 && n > 1) || k < n / 2) cout << -1; else if (k == 0) cout << 1; else { int x = k - (n - 2) / 2; cout << x << << x * 2 << ; for (int i = 1; i <= n - 2; ++i) cout << x * 2 + i << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int z[(int)1e6 + 3]; string z_algo(string s) { int x = 0, y = 0; int T = 0, M = (int)1e6 + 3; for (int i = 1; i < s.size(); i++) { z[i] = max(0, min(z[i - x], y - i + 1)); while (i + z[i] < s.size() && s[z[i]] == s[i + z[i]]) { x = i, y = i + z[i]; z[i]++; } } int maxz = 0, res = 0, n = s.size(); int ans = 0; for (int i = 0; i < n; i++) { if (i + z[i] == n && maxz >= z[i]) { ans = max(ans, z[i]); } maxz = max(maxz, z[i]); } string t; for (int i = 0; i < ans; i++) t.push_back(s[i]); if (!ans) return Just a legend ; return t; } int main() { int t, tc = 0; string s, ans; cin >> s; ans = z_algo(s); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, a, b, c, ans, t1; int main() { scanf( %d , &t); while (t--) { scanf( %d%d%d , &a, &b, &c); ans = 0; t1 = c / 2; t1 = min(t1, b); ans += t1 * 3; b -= t1; t1 = b / 2; t1 = min(t1, a); ans += t1 * 3; printf( %d n , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int ques[50005]; int ma[26]; int main() { string s; cin >> s; int i, j; memset(ques, 0, sizeof(ques)); int br = 1; for (i = 0; i < (s.size()); i++) { if (i != 0) ques[i] = ques[i] + ques[i - 1]; if (s[i] == ? ) ques[i] += 1; } for (i = 0; i < 26; i++) ma[i] = -100; vector<char> second_bag; int first_ind = 0; for (i = 0; i < s.size(); i++) { ma[s[i] - A ] = i; if (i >= 25) { int t; int char_count = 0; vector<char> bag; for (t = 0; t < 26; t++) { if (!(ma[t] >= (i - 25) && (ma[t] <= i))) { char_count++; char ss = A + t; bag.push_back(ss); } } int ques_count = ques[i]; if ((i - 25) > 0) ques_count = ques_count - ques[i - 26]; if (char_count > ques_count) bag.clear(); else { int tt; first_ind = i - 25; int vc_count = 0; for (tt = (i - 25); tt <= i; tt++) { if (s[tt] == ? ) { second_bag.push_back(bag[vc_count]); vc_count++; } else { second_bag.push_back(s[tt]); } } br = 0; break; } } } if (br == 0) { i = 0; while (i < s.size()) { if (i != first_ind) { if (s[i] != ? ) cout << s[i]; else cout << A ; } else { int temp1 = i - i; for (temp1 = 0; temp1 < 26; temp1++) { cout << second_bag[temp1]; i = i + 1; } i = i - 1; } i = i + 1; } } if (br == 1) cout << -1 << endl; return 0; }
|
// phase_selector.v
`timescale 1 ns / 1 ps
module phase_selector
(
input CLK400,
input CLK80,
input reset,
input [3:0]phsel,
input [7:0]serin,
output serout
);
// --- expand fron 8 to 16 phases (serin -> ser) -------------------------
reg [7:0]serdel;
wire [15:0]ser = {serin, serdel};
always @(posedge CLK400 or posedge reset)
begin
if (reset) serdel <= 0;
else serdel <= serin;
end
// --- 4:16 decoder (phsel -> pos) ---------------------------------------
reg [15:0]pos;
always @(posedge CLK80)
begin
case (phsel)
4'd0: pos <= 16'b0000_0000_0000_0001;
4'd1: pos <= 16'b0000_0000_0000_0010;
4'd2: pos <= 16'b0000_0000_0000_0100;
4'd3: pos <= 16'b0000_0000_0000_1000;
4'd4: pos <= 16'b0000_0000_0001_0000;
4'd5: pos <= 16'b0000_0000_0010_0000;
4'd6: pos <= 16'b0000_0000_0100_0000;
4'd7: pos <= 16'b0000_0000_1000_0000;
4'd8: pos <= 16'b0000_0001_0000_0000;
4'd9: pos <= 16'b0000_0010_0000_0000;
4'd10: pos <= 16'b0000_0100_0000_0000;
4'd11: pos <= 16'b0000_1000_0000_0000;
4'd12: pos <= 16'b0001_0000_0000_0000;
4'd13: pos <= 16'b0010_0000_0000_0000;
4'd14: pos <= 16'b0100_0000_0000_0000;
4'd15: pos <= 16'b1000_0000_0000_0000;
endcase
end
// --- demultiplexer 16:1 (3 stage pipeline) -----------------------------
reg [15:0]stage1;
reg [3:0]stage2;
reg stage3;
always @(posedge CLK400 or posedge reset)
begin
if (reset)
begin
stage1 <= 0;
stage2 <= 0;
stage3 <= 0;
end
else
begin
stage1 <= ser & pos; // clock crossing (pos)
stage2 <= {|stage1[15:12], |stage1[11:8], |stage1[7:4], |stage1[3:0]};
stage3 <= |stage2;
end
end
assign serout = stage3;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, x, f[101][101][101], g[101]; char s[101]; int main() { scanf( %I64d%I64d%s , &n, &x, s + 1); for (long long i = 1; i <= n; i++) f[s[i] - 0 ][i][i] = 1; g[0] = g[1] = 2; for (long long i = 2; i <= x; i++) g[i] = g[i - 1] * g[i - 2] % 1000000007; for (long long i = 2; i <= x; i++) for (long long l = 1; l <= n; l++) for (long long r = l; r <= n; r++) { for (long long m = l; m < r; m++) f[i][l][r] += f[i - 1][l][m] * f[i - 2][m + 1][r] % 1000000007, f[i][l][r] %= 1000000007; f[i][l][r] += f[i - 1][l][r] * (r == n ? g[i - 2] : 1) % 1000000007, f[i][l][r] %= 1000000007; f[i][l][r] += f[i - 2][l][r] * (l == 1 ? g[i - 1] : 1) % 1000000007, f[i][l][r] %= 1000000007; } return printf( %I64d n , f[x][1][n]), 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_TB_V
`define SKY130_FD_SC_HS__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 B2 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 B2 = 1'b0;
#380 C1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 C1 = 1'b1;
#500 B2 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 C1 = 1'bx;
#640 B2 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_TB_V
|
#include <bits/stdc++.h> using namespace std; char inp[5]; void try_catch(long long int l, long long int r) { long long int mid = l + rand() % (r - l + 1); printf( %lld %lld n , mid, mid); fflush(stdout); scanf( %s , inp); if (inp[0] == Y ) exit(0); } int main() { srand(time(NULL)); long long int n, k; cin >> n >> k; long long int l = 1, r = n; while (1) { while (r - l < 60) { try_catch(max(1LL, l - k), min(n, r + k)); l = max(1LL, l - 2 * k); r = min(n, r + 2 * k); } long long int mid = (l + r) / 2; printf( %lld %lld n , l, mid); fflush(stdout); scanf( %s , inp); if (inp[0] == Y ) { if (l == mid) exit(0); r = min(n, mid + k); l = max(1LL, l - k); } else { l = max(1LL, mid - k); r = min(n, r + k); } } return 0; }
|
`timescale 1ns / 1ps
module mux4to1_beh_1_tb;
// Inputs
reg [3:0] data_in;
reg [1:0] ctrl_sel;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
mux4to1_beh_1 uut (
.data_in(data_in),
.ctrl_sel(ctrl_sel),
.data_out(data_out)
);
task expect;
input exp_out;
if (data_out !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
$display("data_out should be %b", exp_out);
$finish;
end
else begin
$display("At time %0d data_in=%b, ctrl_sel=%b, data_out=%b",
$time, data_in, ctrl_sel, data_out);
end
endtask
initial begin
data_in = 4'b1010;
ctrl_sel = 2'b00;
#10 expect(1'b0);
ctrl_sel = 2'b01;
#10 expect(1'b1);
ctrl_sel = 2'b10;
#10 expect(1'b0);
ctrl_sel = 2'b11;
#10 expect(1'b1);
$display("TEST PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int sc1() { int x; scanf( %d , &x); return x; } long long sc2() { long long x; scanf( %lld , &x); return x; } int bs; int n, q; int arr[100007]; int cnt[100007]; int ans = 0; int answer[100007]; struct A { int l, r, id; } node[100007]; bool cmp(A a, A b) { int x = a.l / bs; int y = b.l / bs; if (x != y) return x < y; return a.r < b.r; } void add(int x) { if (x <= n) { if (cnt[x] == x) ans--; cnt[x]++; if (cnt[x] == x) ans++; } } void rmv(int x) { if (x <= n) { if (cnt[x] == x) ans--; cnt[x]--; if (cnt[x] == x) ans++; } } int main() { n = sc1(), q = sc1(); bs = sqrt(n); for (int i = 0; i < n; i++) arr[i] = sc1(); for (int i = 0; i < q; i++) { int a = sc1(), b = sc1(); node[i].l = --a; node[i].r = --b; node[i].id = i; } sort(node, node + q, cmp); int mo_left = 0, mo_right = -1; for (int i = 0; i < q; i++) { int left = node[i].l; int right = node[i].r; while (mo_right < right) { mo_right++; add(arr[mo_right]); } while (mo_right > right) { rmv(arr[mo_right]); mo_right--; } while (mo_left < left) { rmv(arr[mo_left]); mo_left++; } while (mo_left > left) { mo_left--; add(arr[mo_left]); } answer[node[i].id] = ans; } for (int i = 0; i < q; i++) { cout << answer[i] << endl; } return 0; }
|
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
wire RW = CNTRL_bus_in[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus_in[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus_in[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus_in[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
reg [DR_WIDTH-1:0] i;
always@(posedge CLK) begin
if (RST)
for (i=3'b0;i<2**DR_WIDTH-3'b1;i = i + 3'b1) begin
SYNC_RAM1[i] <= 0;
SYNC_RAM0[i] <= 0;
end
else if(RW) begin
SYNC_RAM0[DA] <= D_bus_in;
SYNC_RAM1[DA] <= D_bus_in;
end
end
always@(*) begin
ADDR_bus_out <= SYNC_RAM0[AA];
B_data_out <= SYNC_RAM1[BA];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, j, k, n, v[200010], m, a, b, x, y, h, w, l, p, ans, numitor, aux, mini, sum, poz; string s1, s2, second; char c; map<long long, long long> mip; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> x; for (long long i = 1; i <= n; i++) { cin >> v[i]; if (v[i] < x) v[i] = -1; else if (v[i] > x) v[i] = 1; else { v[i] = 0; poz = i; } } mip[0] = 1; sum = 0; for (long long i = 1; i <= n; i++) { sum += v[i]; if (i >= poz) { if (mip.find(sum) != mip.end()) ans += mip[sum]; if (mip.find(sum - 1) != mip.end()) ans += mip[sum - 1]; } else { mip[sum] += 1; v[i] = sum; } } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_TB_V
`define SKY130_FD_SC_HD__O311A_TB_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o311a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_TB_V
|
#include <bits/stdc++.h> using namespace std; long long n, q, ans[50005], sum[50005], a[50005], p[50005], x[50005], cont, pos, us[50005]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> q; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 2; i <= n; i++) cin >> p[i]; for (int i = 0; i < q; i++) cin >> x[i]; for (int i = 1; i <= n; i++) { pos = i; cont = 1; while (pos != 1) { us[pos] = cont; cont++; pos = p[pos]; } us[pos] = cont; for (int j = 0; j < q; j++) { sum[j] += us[x[j]]; if (us[x[j]]) { ans[j]++; j += a[i] - 1; } } pos = i; cont = 1; while (pos != 1) { us[pos] = 0; cont++; pos = p[pos]; } us[pos] = 0; } for (int i = 0; i < q; i++) cout << sum[i] - ans[i] << << ans[i] << n ; return 0; }
|
// psi2c_control
`timescale 1 ps / 1 ps
/*
-- registers b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
-- 0 w: tbm go
-- 0 r: ful tbm run
-- 1 w: send raw S P D7 D6 D5 D4 !D4 D3 D2 D1 D0 !D0
-- 2 w: send D7 D6 D5 D4 D3 D2 D1 D0
-- 3 w: send S D7 D6 D5 D4 D3 D2 D1 D0
-- 4 w: send P D7 D6 D5 D4 D3 D2 D1 D0
-- 5 w: send SP D7 D6 D5 D4 D3 D2 D1 D0
-- 1 r: rdb raw run 0 0 _s3 _rw _d4 _d0 S ha4 ha3 ha2 ha1 ha0 pa2 pa1 pa0
-- ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0
--
-- tbm = read back on
-- ful = fifo full
-- go = start transmission
-- run = i2c running
-- S = Start Bit, P = Stop Bit
-- D = Send Data
-- ha = Hub Address
-- pa = Port Address
-- ra = Register Address
-- rd = Register Data
*/
module i2c_control
(
// avalon slave
input clk,
input reset,
// avalon slave interface
input [2:0]address,
input write,
input [31:0]writedata,
input read,
output reg [31:0]readdata,
output go,
input full,
output reg [11:0]memd,
output memw,
input busy,
output tbm,
input [31:0]rda
);
wire [9:0]i2c_data;
reg rdbff;
assign memw = write & (address>=1) & (address<=5);
assign i2c_data = {writedata[7:4], !writedata[4],
writedata[3:0], !writedata[0]};
always @(*)
case (address)
2: memd <= {2'b00, i2c_data};
3: memd <= {2'b10, i2c_data}; // S
4: memd <= {2'b01, i2c_data}; // P
5: memd <= {2'b11, i2c_data}; // SP
default: memd <= writedata[11:0];
endcase
always @(*)
case (address)
1: readdata <= rda;
default readdata <= {1'b0, full, rdbff, busy || rda[31]};
endcase
// tbm mode
always @(posedge clk or posedge reset)
begin
if (reset) rdbff <= 0;
else if (write && (address == 0))
rdbff = writedata[1];
end
assign tbm = rdbff;
// go signal
assign go = write & writedata[0] & (address == 0);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; void solve() { int n, m; cin >> n >> m; for (int i = 0; i < 200; i++) cout << 9 ; cout << endl; for (int i = 0; i < 200; i++) cout << 9 ; for (int i = 0; i < 199; i++) cout << 0 ; cout << 1 ; } int main() { ios_base::sync_with_stdio(false); int t = 1, num = 1; while (t--) { ; ; solve(); ; } return 0; }
|
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapadt7410.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [7:0] I2C_ReadCount_s;
wire [15:0] PeriodCounterPreset_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [15:0] WaitCounterPreset_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetEnable_s;
wire ParamThresholdEnable_s;
wire ParamWaitCounterPresetEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 5 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
ADT7410 ADT7410_0 (
.I2C_Busy_i(I2C_Busy_i),
.I2C_Data_o(I2C_DataIn_o),
.I2C_Data_i(I2C_DataOut_i),
.I2C_Error_i(I2C_Error_i),
.I2C_FIFOReadNext_o(I2C_FIFOReadNext_o),
.I2C_FIFOWrite_o(I2C_FIFOWrite_o),
.I2C_ReadCount_o(I2C_ReadCount_s),
.I2C_ReceiveSend_n_o(I2C_ReceiveSend_n_o),
.I2C_StartProcess_o(I2C_StartProcess_o),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPreset_i(PeriodCounterPreset_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s),
.WaitCounterPreset_i(WaitCounterPreset_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_F100_400_n_o = 1'b1;
assign I2C_ReadCount_o = I2C_ReadCount_s[3:0];
assign Outputs_o[0] = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_DataIn_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SPI_ReadNext_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign SPI_Write_o = 1'b0;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPreset_s),
.Enable_i(ParamPeriodCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_WaitCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(WaitCounterPreset_s),
.Enable_i(ParamWaitCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetEnable_s = TODO: implement;
/* Address $03 */
assign ParamThresholdEnable_s = TODO: implement;
/* Address $04 */
assign ParamWaitCounterPresetEnable_s = TODO: implement;
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arriagx_dmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arriagx_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Arria GX",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arriagx_dmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pcie_bram_7x.v
// Version : 3.0
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFBBN_FUNCTIONAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_FUNCTIONAL_PP_V
|
//////////////////////////////////////////////////////////////////////////////////
// TimeCounter for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: TimeCounter
// Module Name: TimeCounter
// File Name: TimeCounter.v
//
// Version: v1.0.0
//
// Description: Time counter
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module TimeCounter
#
(
parameter TimerWidth = 32 ,
parameter DefaultPeriod = 100000000
)
(
iClock ,
iReset ,
iEnabled ,
iPeriodSetting ,
iSettingValid ,
iProbe ,
oCountValue
);
input iClock ;
input iReset ;
input iEnabled ;
input [TimerWidth - 1:0] iPeriodSetting ;
input iSettingValid ;
input iProbe ;
output [TimerWidth - 1:0] oCountValue ;
reg [TimerWidth - 1:0] rPeriod ;
reg [TimerWidth - 1:0] rSampledCount ;
reg [TimerWidth - 1:0] rCounter ;
reg [TimerWidth - 1:0] rTimeCount ;
always @ (posedge iClock)
if (iReset | !iEnabled | rTimeCount == rPeriod)
rCounter <= {(TimerWidth){1'b0}};
else
if (iEnabled & iProbe)
rCounter <= rCounter + 1'b1;
always @ (posedge iClock)
if (iReset | !iEnabled | rTimeCount == rPeriod)
rTimeCount <= {(TimerWidth){1'b0}};
else
if (iEnabled)
rTimeCount <= rTimeCount + 1'b1;
always @ (posedge iClock)
if (iReset)
rSampledCount <= {(TimerWidth){1'b0}};
else
if (rTimeCount == rPeriod)
rSampledCount <= rCounter;
always @ (posedge iClock)
if (iReset)
rPeriod <= DefaultPeriod;
else
if (iSettingValid)
rPeriod <= iPeriodSetting;
assign oCountValue = rSampledCount;
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int X = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c >= 0 && c <= 9 ) X = X * 10 + c - 0 , c = getchar(); return X * w; } const int N = 125000 + 10; int n, m; char s[N], t[N]; int bl[N], ans[N]; int nxt[N]; void getnext() { for (int i = 2, j = 0; i <= m; ++i) { while (j && bl[t[j + 1]] != bl[t[i]]) j = nxt[j]; if (bl[t[j + 1]] == bl[t[i]]) ++j; nxt[i] = j; } } void calc(int w) { getnext(); for (int i = 1, j = 0; i <= n; ++i) { while (j && bl[t[j + 1]] != bl[s[i]]) j = nxt[j]; if (bl[t[j + 1]] == bl[s[i]]) ++j; if (j == m) ans[i - m + 1] = min(ans[i - m + 1], w); } } void dfs(char c, int tot) { if (c > f ) { calc(6 - tot); return; } for (int i = 1; i <= tot; ++i) bl[c] = i, dfs(c + 1, tot); bl[c] = tot + 1, dfs(c + 1, tot + 1); } int main() { scanf( %s%s , s + 1, t + 1), n = strlen(s + 1), m = strlen(t + 1); memset(ans, 0x3f, sizeof(ans)); dfs( a , 0); for (int i = 1; i <= n - m + 1; ++i) printf( %d , ans[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> arr(n); for (int i = 0; i < n; ++i) cin >> arr[i]; vector<bool> used(n, false); int count = 0; int marked = 0; while (marked < n) { int min = 101; for (int i = 0; i < n; ++i) { if (arr[i] < min && !used[i]) min = arr[i]; } for (int i = 0; i < n; ++i) if (arr[i] % min == 0) { if (!used[i]) ++marked; used[i] = true; } ++count; } cout << count; }
|
`include "cpu_data.v"
module Alu(single, value1, value2, operator, bus_out, alu_flags, alu_flags8, old_carry);
input single;
input [15:0] value1, value2;
input [3:0] operator;
input old_carry;
reg carry; wire overflow, zero, negative;
wire carry8, overflow8, zero8, negative8;
output [3:0] alu_flags;
output [3:0] alu_flags8;
output reg [15:0] bus_out;
assign overflow = value1[15] ^ bus_out[15];
assign zero = ~|bus_out;
assign negative = bus_out[15];
assign alu_flags = {carry, overflow, zero, negative};
assign carry8 = bus_out[8];
assign overflow8 = value1[7] ^ bus_out[7];
assign zero8 = ~|bus_out[7:0];
assign negative8 = bus_out[7];
assign alu_flags8 = {carry8, overflow8, zero8, negative8};
initial carry = 1'b0;
initial bus_out = 16'b0;
always @* begin
if (!single)
(* parallel_case *) case(operator)
`OP_ADD: {carry, bus_out} = {1'b0, value1} + {1'b0, value2};
`OP_SUB, `OP_CMP: {carry, bus_out} = {1'b0, value1} - {1'b0, value2};
`OP_ADC: {carry, bus_out} = {1'b0, value1} + {1'b0, value2} + {15'b0, old_carry};
`OP_SBC: {carry, bus_out} = {1'b0, value1} - {1'b0, value2} - {15'b0, old_carry};
`OP_AND: bus_out = value1 & value2;
`OP_OR: bus_out = value1 | value2;
`OP_XOR: bus_out = value1 ^ value2;
`OP_MOV: bus_out = value2;
default: bus_out = 16'hAAAA;
endcase
else
(* parallel_case *) case (operator)
`OP_NEG: bus_out = 16'h0000 - value1;
`OP_COM: bus_out = 16'hFFFF - value1;
`OP_LSL: {carry, bus_out} = {value1, 1'b0};
`OP_LSR: {bus_out, carry} = {1'b0, value1};
`OP_ROL: bus_out = {value1[14:0], value1[15]};
`OP_ROR: bus_out = {value1[0], value1[15:1]};
`OP_RLC: {carry, bus_out} = {value1, old_carry};
`OP_RRC: {bus_out, carry} = {old_carry, value1};
`OP_INC: {carry, bus_out} = {1'b0, value1} + {1'b0, 16'h01};
`OP_DEC: {carry, bus_out} = {1'b0, value1} - {1'b0, 16'h01};
default: bus_out = 16'h0000;
endcase
end
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end
else if(cnt && !timer_top) timer <= timer + 7'd1;
end
endmodule
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module tcm_mem
(
// Inputs
input clk_i
,input rst_i
,input mem_i_rd_i
,input mem_i_flush_i
,input mem_i_invalidate_i
,input [ 31:0] mem_i_pc_i
,input [ 31:0] mem_d_addr_i
,input [ 31:0] mem_d_data_wr_i
,input mem_d_rd_i
,input [ 3:0] mem_d_wr_i
,input mem_d_cacheable_i
,input [ 10:0] mem_d_req_tag_i
,input mem_d_invalidate_i
,input mem_d_writeback_i
,input mem_d_flush_i
,input axi_awvalid_i
,input [ 31:0] axi_awaddr_i
,input [ 3:0] axi_awid_i
,input [ 7:0] axi_awlen_i
,input [ 1:0] axi_awburst_i
,input axi_wvalid_i
,input [ 31:0] axi_wdata_i
,input [ 3:0] axi_wstrb_i
,input axi_wlast_i
,input axi_bready_i
,input axi_arvalid_i
,input [ 31:0] axi_araddr_i
,input [ 3:0] axi_arid_i
,input [ 7:0] axi_arlen_i
,input [ 1:0] axi_arburst_i
,input axi_rready_i
// Outputs
,output mem_i_accept_o
,output mem_i_valid_o
,output mem_i_error_o
,output [ 31:0] mem_i_inst_o
,output [ 31:0] mem_d_data_rd_o
,output mem_d_accept_o
,output mem_d_ack_o
,output mem_d_error_o
,output [ 10:0] mem_d_resp_tag_o
,output axi_awready_o
,output axi_wready_o
,output axi_bvalid_o
,output [ 1:0] axi_bresp_o
,output [ 3:0] axi_bid_o
,output axi_arready_o
,output axi_rvalid_o
,output [ 31:0] axi_rdata_o
,output [ 1:0] axi_rresp_o
,output [ 3:0] axi_rid_o
,output axi_rlast_o
);
//-------------------------------------------------------------
// AXI -> PMEM Interface
//-------------------------------------------------------------
wire ext_accept_w;
wire ext_ack_w;
wire [ 31:0] ext_read_data_w;
wire [ 3:0] ext_wr_w;
wire ext_rd_w;
wire [ 7:0] ext_len_w;
wire [ 31:0] ext_addr_w;
wire [ 31:0] ext_write_data_w;
tcm_mem_pmem
u_conv
(
// Inputs
.clk_i(clk_i),
.rst_i(rst_i),
.axi_awvalid_i(axi_awvalid_i),
.axi_awaddr_i(axi_awaddr_i),
.axi_awid_i(axi_awid_i),
.axi_awlen_i(axi_awlen_i),
.axi_awburst_i(axi_awburst_i),
.axi_wvalid_i(axi_wvalid_i),
.axi_wdata_i(axi_wdata_i),
.axi_wstrb_i(axi_wstrb_i),
.axi_wlast_i(axi_wlast_i),
.axi_bready_i(axi_bready_i),
.axi_arvalid_i(axi_arvalid_i),
.axi_araddr_i(axi_araddr_i),
.axi_arid_i(axi_arid_i),
.axi_arlen_i(axi_arlen_i),
.axi_arburst_i(axi_arburst_i),
.axi_rready_i(axi_rready_i),
.ram_accept_i(ext_accept_w),
.ram_ack_i(ext_ack_w),
.ram_error_i(1'b0),
.ram_read_data_i(ext_read_data_w),
// Outputs
.axi_awready_o(axi_awready_o),
.axi_wready_o(axi_wready_o),
.axi_bvalid_o(axi_bvalid_o),
.axi_bresp_o(axi_bresp_o),
.axi_bid_o(axi_bid_o),
.axi_arready_o(axi_arready_o),
.axi_rvalid_o(axi_rvalid_o),
.axi_rdata_o(axi_rdata_o),
.axi_rresp_o(axi_rresp_o),
.axi_rid_o(axi_rid_o),
.axi_rlast_o(axi_rlast_o),
.ram_wr_o(ext_wr_w),
.ram_rd_o(ext_rd_w),
.ram_len_o(ext_len_w),
.ram_addr_o(ext_addr_w),
.ram_write_data_o(ext_write_data_w)
);
//-------------------------------------------------------------
// Dual Port RAM
//-------------------------------------------------------------
// Mux access to the 2nd port between external access and CPU data access
wire [13:0] muxed_addr_w = ext_accept_w ? ext_addr_w[15:2] : mem_d_addr_i[15:2];
wire [31:0] muxed_data_w = ext_accept_w ? ext_write_data_w : mem_d_data_wr_i;
wire [3:0] muxed_wr_w = ext_accept_w ? ext_wr_w : mem_d_wr_i;
wire [31:0] data_r_w;
tcm_mem_ram
u_ram
(
// Instruction fetch
.clk0_i(clk_i)
,.rst0_i(rst_i)
,.addr0_i(mem_i_pc_i[15:2])
,.data0_i(32'b0)
,.wr0_i(4'b0)
// External access / Data access
,.clk1_i(clk_i)
,.rst1_i(rst_i)
,.addr1_i(muxed_addr_w)
,.data1_i(muxed_data_w)
,.wr1_i(muxed_wr_w)
// Outputs
,.data0_o(mem_i_inst_o)
,.data1_o(data_r_w)
);
assign ext_read_data_w = data_r_w;
//-------------------------------------------------------------
// Instruction Fetch
//-------------------------------------------------------------
reg mem_i_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_i_valid_q <= 1'b0;
else
mem_i_valid_q <= mem_i_rd_i;
assign mem_i_accept_o = 1'b1;
assign mem_i_valid_o = mem_i_valid_q;
assign mem_i_error_o = 1'b0;
//-------------------------------------------------------------
// Data Access / Incoming external access
//-------------------------------------------------------------
reg mem_d_accept_q;
reg [10:0] mem_d_tag_q;
reg mem_d_ack_q;
reg ext_ack_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
mem_d_accept_q <= 1'b1;
// External request, do not accept internal requests in next cycle
else if (ext_rd_w || ext_wr_w != 4'b0)
mem_d_accept_q <= 1'b0;
else
mem_d_accept_q <= 1'b1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
mem_d_ack_q <= 1'b0;
mem_d_tag_q <= 11'b0;
end
else if ((mem_d_rd_i || mem_d_wr_i != 4'b0 || mem_d_flush_i || mem_d_invalidate_i || mem_d_writeback_i) && mem_d_accept_o)
begin
mem_d_ack_q <= 1'b1;
mem_d_tag_q <= mem_d_req_tag_i;
end
else
mem_d_ack_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
ext_ack_q <= 1'b0;
// External request accepted
else if ((ext_rd_w || ext_wr_w != 4'b0) && ext_accept_w)
ext_ack_q <= 1'b1;
else
ext_ack_q <= 1'b0;
assign mem_d_ack_o = mem_d_ack_q;
assign mem_d_resp_tag_o = mem_d_tag_q;
assign mem_d_data_rd_o = data_r_w;
assign mem_d_error_o = 1'b0;
assign mem_d_accept_o = mem_d_accept_q;
assign ext_accept_w = !mem_d_accept_q;
assign ext_ack_w = ext_ack_q;
`ifdef verilator
//-------------------------------------------------------------
// write: Write byte into memory
//-------------------------------------------------------------
function write; /*verilator public*/
input [31:0] addr;
input [7:0] data;
begin
case (addr[1:0])
2'd0: u_ram.ram[addr/4][7:0] = data;
2'd1: u_ram.ram[addr/4][15:8] = data;
2'd2: u_ram.ram[addr/4][23:16] = data;
2'd3: u_ram.ram[addr/4][31:24] = data;
endcase
end
endfunction
//-------------------------------------------------------------
// read: Read byte from memory
//-------------------------------------------------------------
function [7:0] read; /*verilator public*/
input [31:0] addr;
begin
case (addr[1:0])
2'd0: read = u_ram.ram[addr/4][7:0];
2'd1: read = u_ram.ram[addr/4][15:8];
2'd2: read = u_ram.ram[addr/4][23:16];
2'd3: read = u_ram.ram[addr/4][31:24];
endcase
end
endfunction
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100010]; int main() { int T; cin >> T; while (T--) { int n, sum = 0; int z = 0; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; sum = sum + a[i]; if (a[i] == 0) { z++; } } int ans = 0; if (sum == 0) { ans = 1; sum++; } if (z != 0) { ans = max(ans, z); if (sum == 1) { sum = sum + ans - 1; } else { sum = sum + ans; } } if (sum == 0) { ans++; } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int a, n2 = 0, n1 = 0; for (int i = 0; i < n; i++) cin >> a, a - 1 ? n2++ : n1++; if (n2) cout << 2 << ; if (n1) cout << 1 << ; for (int i = 0; i < n2 - 1; i++) cout << 2 << ; for (int i = 0; i < n1 - 1; i++) cout << 1 << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int mod = 1000000007; long long int store[2002][2002] = {0}; long long int ncrModp(long long int n, long long int r, long long int p) { long long int value[9999] = {0}; value[0] = 1; for (long long int e = 1; e <= n; e++) { store[e][0] = 1; for (long long int f = e; f > 0; f--) { value[f] = (value[f] + value[f - 1]) % p; store[e][f] = value[f]; } } return (value[r]); } int bin(long long int n) { long long int r = n; long long int one = 0; while (r != 0) { one += r % 2; r = r / 2; } return (one); } int main() { long long int dp[1111] = {0}; dp[1] = 0; dp[2] = 1; for (int e = 3; e <= 1001; e++) { long long int k = bin(e); dp[e] = 1 + dp[k]; } string s; long long int n; cin >> s; cin >> n; ncrModp(s.length() + 1, s.length() + 1, mod); long long int ones = 0; for (int u = 0; u < s.length(); u++) { if (s[u] == 1 ) ++ones; } int q = s.length() - 1; long long int qar[1111] = {0}; for (int u = 1; u <= q; u++) { qar[u] = store[q][u]; } long long int u = 0, ct = 0; long long int h = 0; long long int t = 0; qar[ones] += 1; for (int w = q; w > 0; w--) { if (s[w] == 1 ) { ++t; long long int u = ones - t; if (w != q) for (int h = 0; h <= ct; h++) { qar[h + ones - t] += store[ct][h]; } else { qar[ones - t] += 1; } } ++ct; } long long int ans = 0; for (int p = 1; p < s.length(); p++) if (dp[p] == n - 1) ans += qar[p] % mod; if (n == 1 && s != 1 ) ans -= 1; if (n != 0) cout << ans % mod; else cout << 1 ; }
|
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
`include "include_module_a.v"
`include "include_module_b.v"
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_reg.v
//
// Description:
// This is just a general register. It has two write enables and two data ins
// to simplify the operation. Typically one write enable (we) comes from the
// external interface and the second write enable is used for internal writing
// to the register. A mask parameter is used to only write to the bits that
// are used in the register.
//
// Specifications:
//
// Structure:
// axi_ctrl_top
// axi_ctrl_write
// axi_ctrl_addr_decode
// axi_ctrl_read
// axi_ctrl_addr_decode
// axi_ctrl_reg_bank
// axi_ctrl_reg
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_ctrl_reg #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_REG_WIDTH = 32,
parameter integer C_DATA_WIDTH = 32,
parameter C_INIT = 32'h0,
parameter C_MASK = 32'h1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_REG_WIDTH-1:0] data_in ,
input wire we ,
input wire we_int ,
input wire [C_REG_WIDTH-1:0] data_in_int ,
output wire [C_DATA_WIDTH-1:0] data_out
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [C_REG_WIDTH-1:0] data;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
data <= C_INIT[0+:C_REG_WIDTH];
end
else if (we) begin
data <= data_in;
end
else if (we_int) begin
data <= data_in_int;
end
else begin
data <= data;
end
end
// Does not supprot case where P_MASK_LSB > 0
generate
if (C_REG_WIDTH == C_DATA_WIDTH) begin : assign_no_zero_pad
assign data_out = data;
end
else begin : assign_zero_pad
assign data_out = {{C_DATA_WIDTH-C_REG_WIDTH{1'b0}}, data};
end
endgenerate
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } int r, c, k, n, a[15][15]; int main() { scanf( %d%d%d%d , &r, &c, &n, &k); for (int i = (1); i <= (n); ++i) { int x, y; scanf( %d%d , &x, &y); a[x][y] = 1; } int ans = 0; for (int x1 = (1); x1 <= (r); ++x1) { for (int y1 = (1); y1 <= (c); ++y1) { for (int x2 = (x1); x2 <= (r); ++x2) { for (int y2 = (y1); y2 <= (c); ++y2) { int sum = 0; for (int x = (x1); x <= (x2); ++x) { for (int y = (y1); y <= (y2); ++y) sum += a[x][y]; } if (sum >= k) ++ans; } } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline T1 max(T1 a, T2 b) { return a < b ? b : a; } template <typename T1, typename T2> inline T1 min(T1 a, T2 b) { return a < b ? a : b; } const char lf = n ; namespace ae86 { const int bufl = 1 << 15; char buf[bufl], *s = buf, *t = buf; inline int fetch() { if (s == t) { t = (s = buf) + fread(buf, 1, bufl, stdin); if (s == t) return EOF; } return *s++; } inline int ty() { int a = 0; int b = 1, c = fetch(); while (!isdigit(c)) b ^= c == - , c = fetch(); while (isdigit(c)) a = a * 10 + c - 48, c = fetch(); return b ? a : -a; } } // namespace ae86 using ae86::ty; const int _ = 2007, __ = 100007; const long long linf = 0x3f3f3f3f3f3f3f3f; vector<pair<int, int>> e[_]; inline void adde(int a, int b, int c) { e[a].emplace_back(b, c); } inline void addde(int a, int b, int c) { adde(a, b, c), adde(b, a, c); } int n, m, sa, sb; long long val[_] = {0}; int ed[_] = {0}; void dijks(int s, long long dis[]) { for (int i = 1; i <= n; i++) dis[i] = linf, ed[i] = 0; queue<int> q; dis[s] = 0, ed[s] = 1, q.emplace(s); while (!q.empty()) { int a = q.front(); q.pop(), ed[a] = 0; for (auto [b, c] : e[a]) { if (dis[b] <= dis[a] + c) continue; dis[b] = dis[a] + c; if (!ed[b]) q.emplace(b), ed[b] = 1; } } } long long disa[_], disb[_]; long long ha[_] = {0}; int lha = 0, lhb = 0; struct cxk { int x, y; long long v; cxk(int x_ = 0, int y_ = 0, long long v_ = 0) { x = x_, y = y_, v = v_; } } ps[_]; int hx[_] = {0}, hy[_] = {0}; long long sval[_][_] = {0}, f[2][_][_] = {0}, sf[2][_] = {0}, fs[_] = {0}; int main() { ios::sync_with_stdio(0), cout.tie(nullptr); n = ty(), m = ty(); sa = ty(), sb = ty(); for (int i = 1; i <= n; i++) val[i] = ty(); for (int i = 1, a, b, c; i <= m; i++) a = ty(), b = ty(), c = ty(), addde(a, b, c); dijks(sa, disa), dijks(sb, disb); lha = 0; for (int i = 1; i <= n; i++) ha[++lha] = disa[i]; sort(ha + 1, ha + lha + 1), lha = unique(ha + 1, ha + lha + 1) - ha - 1; for (int i = 1; i <= n; i++) disa[i] = lower_bound(ha + 1, ha + lha + 1, disa[i]) - ha; lhb = 0; for (int i = 1; i <= n; i++) ha[++lhb] = disb[i]; sort(ha + 1, ha + lhb + 1), lhb = unique(ha + 1, ha + lhb + 1) - ha - 1; for (int i = 1; i <= n; i++) disb[i] = lower_bound(ha + 1, ha + lhb + 1, disb[i]) - ha; for (int i = 1; i <= n; i++) ps[i] = cxk(disa[i], disb[i], val[i]); for (int i = 1; i <= n; i++) hx[ps[i].y] = max(hx[ps[i].y], ps[i].x), hy[ps[i].x] = max(hy[ps[i].x], ps[i].y); for (int i = 1; i <= lha; i++) { for (int j = 1; j <= n; j++) if (ps[j].x >= i) sval[i][ps[j].y] += ps[j].v; for (int j = lhb - 1; j >= 1; j--) sval[i][j] += sval[i][j + 1]; } for (int i = lha; i >= 1; i--) for (int j = lhb; j >= 1; j--) { if (hx[j] >= i) f[1][i][j] = sf[1][i] + sval[i][j]; if (hy[i] >= j) f[0][i][j] = sf[0][j] + sval[i][j]; if (hx[j] >= i) sf[0][j] = max(sf[0][j], -f[1][i][j] - sval[i][j]); else sf[0][j] = max(sf[0][j], sf[0][j + 1]); if (hy[i] >= j) sf[1][i] = max(sf[1][i], -f[0][i][j] - sval[i][j]); else sf[1][i] = max(sf[1][i], fs[j]); fs[j] = sf[1][i]; } if (f[0][1][1] > 0) cout << Break a heart << lf; else if (f[0][1][1] == 0) cout << Flowers << lf; else cout << Cry << lf; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline T1 max(T1 a, T2 b) { return a < b ? b : a; } template <typename T1, typename T2> inline T1 min(T1 a, T2 b) { return a < b ? a : b; } const char lf = n ; namespace ae86 { const int bufl = 1 << 15; char buf[bufl], *s = buf, *t = buf; inline int fetch() { if (s == t) { t = (s = buf) + fread(buf, 1, bufl, stdin); if (s == t) return EOF; } return *s++; } inline int ty() { int a = 0; int b = 1, c = fetch(); while (!isdigit(c)) b ^= c == - , c = fetch(); while (isdigit(c)) a = a * 10 + c - 48, c = fetch(); return b ? a : -a; } } // namespace ae86 using ae86::ty; const int _ = 123, mo = 1000000007; int n, m, ps, cnts[_] = {0}; long long ans = 0; bitset<_> alls; inline bitset<_> rshl(bitset<_> a, int d) { d %= m; return ((a << d) | (a >> (m - d))) & alls; } inline bitset<_> rshr(bitset<_> a, int d) { d %= m; return ((a >> d) | (a << (m - d))) & alls; } void dfs(bitset<_> now, int las, long long d) { ans = (ans + d) % mo; for (int i = las; i + i <= m; i++) if (cnts[i] && !now[i] && !now[m - i]) dfs(now | rshl(now, i) | rshr(now, i), i + 1, d * cnts[i] % mo); } int main() { ios::sync_with_stdio(0), cout.tie(nullptr); n = ty(), m = ty(), ps = ty(); for (int i = 1; i <= ps; i++) { int a = ty() % m; cnts[min(a, m - a)]++; } bitset<_> temp = 0; temp[0] = 1; alls = 0; for (int i = 0; i < m; i++) alls[i] = 1; dfs(temp, 0, 1), cout << ans << lf; return 0; }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module fast_spi_rx_core
#(
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 4'b0001
)(
input wire SCLK,
input wire SDI,
input wire SEN,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD
);
localparam VERSION = 0;
//output format #ID (as parameter IDENTYFIER + 12 id-frame + 16 bit data)
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg CONF_EN;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
end
end
reg [7:0] LOST_DATA_CNT;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= LOST_DATA_CNT;
else
BUS_DATA_OUT <= 8'b0;
end
end
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SCLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire CONF_EN_SYNC;
assign CONF_EN_SYNC = CONF_EN;
reg [7:0] sync_cnt;
always@(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
reg [11:0] frame_cnt;
wire SEN_START, SEN_FINISH;
reg SEN_DLY;
always@(posedge SCLK) begin
SEN_DLY <= SEN;
end
assign SEN_START = (SEN_DLY ==0 && SEN == 1);
assign SEN_FINISH = (SEN_DLY ==1 && SEN == 0);
always@(posedge SCLK) begin
if(RST_SYNC)
frame_cnt <= 0;
else if(SEN_FINISH && CONF_EN_SYNC)
frame_cnt <= frame_cnt + 1;
end
wire cdc_fifo_write;
reg [4:0] bit_cnt;
always@(posedge SCLK) begin
if(RST_SYNC | SEN_START)
bit_cnt <= 0;
else if(cdc_fifo_write)
bit_cnt <= 0;
else if(SEN)
bit_cnt <= bit_cnt + 1;
end
assign cdc_fifo_write = ( (bit_cnt == 15) || SEN_FINISH ) && CONF_EN_SYNC;
reg [15:0] spi_data;
always@(posedge SCLK) begin
if(RST_SYNC | SEN_FINISH)
spi_data <= 0;
else if(cdc_fifo_write)
spi_data <= {15'b0, SDI};
else if(SEN)
spi_data <= {spi_data[14:0], SDI};
end
wire fifo_full,cdc_fifo_empty;
wire wfull;
always@(posedge SCLK) begin
if(RST_SYNC)
LOST_DATA_CNT <= 0;
else if (wfull && cdc_fifo_write && LOST_DATA_CNT != -1)
LOST_DATA_CNT <= LOST_DATA_CNT +1;
end
wire [31:0] cdc_data;
assign cdc_data = {IDENTYFIER, frame_cnt[11:0], spi_data};
wire [31:0] cdc_data_out;
cdc_syncfifo #(.DSIZE(32), .ASIZE(2)) cdc_syncfifo_i
(
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(cdc_data),
.winc(cdc_fifo_write), .wclk(SCLK), .wrst(RST_LONG),
.rinc(!fifo_full), .rclk(BUS_CLK), .rrst(RST_LONG)
);
gerneric_fifo #(.DATA_SIZE(32), .DEPTH(1024)) fifo_i
( .clk(BUS_CLK), .reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]), .size()
);
//assign FIFO_DATA[31:30] = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)2 * 1e9; const long long MOD = (long long)1e9 + 7; const long long P = 239; const long long MAX_N = 100000; const long long ABC = 26; const long double pi = 3.1415926535897932384626; const long double eps = 1e-6; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(20); long long c, h1, h2, w1, w2; cin >> c >> h1 >> h2 >> w1 >> w2; if (w2 > w1) { swap(h1, h2); swap(w1, w2); } if (w1 * w1 >= c) { long long ans = 0; for (long long i = 0; i * w1 <= c; i++) ans = max(ans, i * h1 + (c - i * w1) / w2 * h2); cout << ans; } else { if (h1 * w2 < h2 * w1) { swap(h1, h2); swap(w1, w2); } long long ans = 0; for (long long i = 0; i < w1 && i * w2 <= c; i++) ans = max(ans, i * h2 + (c - i * w2) / w1 * h1); cout << ans; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n, m; cin >> n >> m; vector<vector<int> > file(n); for (int i = (0); i < ((m)); ++i) { int tmp; cin >> tmp; vector<int> f(tmp); for (int j = (0); j < ((tmp)); ++j) cin >> f[j]; file.push_back(f); } vector<int> v; for (int i = (0); i < ((file.size())); ++i) for (int j = (0); j < ((file[i].size())); ++j) v.push_back(file[i][j]); sort((v).begin(), (v).end()); int emp = v.size() + 1; for (int i = (0); i < ((v.size())); ++i) { if (i + 1 != v[i]) { emp = i + 1; break; } } int index = 1; vector<pair<int, int> > res; for (int i = (0); i < ((file.size())); ++i) { for (int j = (0); j < ((file[i].size())); ++j) { for (int k = (0); k < ((file.size())); ++k) { for (int l = (0); l < ((file[k].size())); ++l) { if (file[k][l] == index) { if (i != k || j != l) { int tmp; res.push_back(make_pair(file[k][l], emp)); res.push_back(make_pair(file[i][j], index)); tmp = file[k][l]; file[k][l] = emp; emp = file[i][j]; file[i][j] = tmp; } ++index; goto NEXT; } } } res.push_back(make_pair(file[i][j], index)); emp = file[i][j]; file[i][j] = index; ++index; NEXT:; } } cout << res.size() << endl; for (int i = (0); i < ((res.size())); ++i) cout << res[i].first << << res[i].second << endl; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_app_v6.v
// Version : 2.4
//--
//-- Description: PCI Express Endpoint sample application
//-- design.
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define PCI_EXP_EP_OUI 24'h000A35
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
`define PCI_EXP_EP_DSN_2 32'h00000001
module pcie_app_v6#(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
)(
input user_clk,
input user_reset,
input user_lnk_up,
// Tx
input [5:0] tx_buf_av,
input tx_cfg_req,
input tx_err_drop,
output tx_cfg_gnt,
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
// Rx
output rx_np_ok,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
// CFG
input [31:0] cfg_do,
input cfg_rd_wr_done,
output [31:0] cfg_di,
output [3:0] cfg_byte_en,
output [9:0] cfg_dwaddr,
output cfg_wr_en,
output cfg_rd_en,
output cfg_err_cor,
output cfg_err_ur,
output cfg_err_ecrc,
output cfg_err_cpl_timeout,
output cfg_err_cpl_abort,
output cfg_err_cpl_unexpect,
output cfg_err_posted,
output cfg_err_locked,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok,
input cfg_to_turnoff,
output cfg_trn_pending,
output cfg_pm_wake,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_link_width,
input pl_sel_link_rate,
input pl_link_gen2_capable,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_capable,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [63:0] cfg_dsn
);
//
// Core input tie-offs
//
assign fc_sel = 3'b0;
assign rx_np_ok = 1'b1;
assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6
assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet
assign s_axis_tx_tuser[2] = 1'b0; // Stream packet
assign tx_cfg_gnt = 1'b1;
assign cfg_err_cor = 1'b0;
assign cfg_err_ur = 1'b0;
assign cfg_err_ecrc = 1'b0;
assign cfg_err_cpl_timeout = 1'b0;
assign cfg_err_cpl_abort = 1'b0;
assign cfg_err_cpl_unexpect = 1'b0;
assign cfg_err_posted = 1'b0;
assign cfg_err_locked = 1'b0;
assign cfg_pm_wake = 1'b0;
assign cfg_trn_pending = 1'b0;
assign cfg_interrupt_assert = 1'b0;
assign cfg_interrupt = 1'b0;
assign cfg_dwaddr = 0;
assign cfg_rd_en = 0;
assign pl_directed_link_change = 0;
assign pl_directed_link_width = 0;
assign pl_directed_link_speed = 0;
assign pl_directed_link_auton = 0;
assign pl_upstream_prefer_deemph = 1'b1;
assign cfg_interrupt_di = 8'b0;
assign cfg_err_tlp_cpl_header = 48'h0;
assign cfg_di = 0;
assign cfg_byte_en = 4'h0;
assign cfg_wr_en = 0;
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};
//
// Programmable I/O Module
//
wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
wire cfg_bus_mstr_enable = cfg_command[2];
PIO #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) PIO (
.user_clk ( user_clk ), // I
.user_reset ( user_reset ), // I
.user_lnk_up ( user_lnk_up ), // I
.s_axis_tx_tready ( s_axis_tx_tready ), // I
.s_axis_tx_tdata ( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast ( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O
.tx_src_dsc ( s_axis_tx_tuser[3] ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.cfg_to_turnoff ( cfg_to_turnoff ), // I
.cfg_turnoff_ok ( cfg_turnoff_ok ), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable (cfg_bus_mstr_enable ) // I
);
endmodule // pcie_app
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module block_design_xlconstant_0_0 (
dout
);
output wire [1-1 : 0] dout;
xlconstant #(
.CONST_VAL(1'd1),
.CONST_WIDTH(1)
) inst (
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, d, m, a[100001], id; long long sum[100001]; int main() { scanf( %d%d%d , &n, &d, &m); for (int i = 1; i <= n; ++i) scanf( %d , a + i); sort(a + 1, a + 1 + n); id = upper_bound(a + 1, a + 1 + n, m) - a; for (int i = 1; i <= n; ++i) sum[i] = sum[i - 1] + a[i]; if (id == n + 1) { printf( %lld n , sum[n]); return 0; } long long ans = 0; for (int i = 0; i <= n - id; ++i) { if ((d + 1) * i > n - 1) break; int k = min(n - 1 - (d + 1) * i, id - 1); ans = max(ans, sum[id - 1] - sum[id - 1 - k] + sum[n - 1] - sum[n - 1 - i]); } ans += a[n]; printf( %lld n , ans); return 0; }
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long cnt(long long a, long long b, long long c) { if (a > b || b > c) return 0LL; if (a == b && b == c) return 1LL; if (a == b && b < c) return 3LL; if (a < b && b == c) return 3LL; if (a < b && b < c) return 6LL; } int main() { long long n; scanf( %lld , &n); if (n % 3LL) printf( 0 n ); else { long long ans = 0LL; n /= 3LL; for (long long sab = 1LL; sab * sab * sab <= n; sab++) if (n % sab == 0LL) { for (long long a = 1LL; a <= sab - a; a++) { long long b = sab - a; long long det = sab * sab - 4LL * a * b + 4LL * n / sab; if (det < 0LL) continue; long long sqdet = 0LL, dd = 1LL << 30LL; while (dd) { long long nsqdet = sqdet + dd; if (nsqdet * nsqdet <= det) sqdet = nsqdet; dd >>= 1LL; } if (sqdet * sqdet == det) { long long c = sqdet - sab; if (c % 2LL == 0) { c /= 2LL; ans += cnt(a, b, c); } } } } printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> int main() { long long int n, m, i, c = 0; scanf( %lld %lld , &n, &m); long long int a[m]; for (i = 0; i < m; i++) { scanf( %lld , &a[i]); } for (i = 0; i < m - 1; i++) { if (a[i + 1] > a[i]) { c = c + a[i + 1] - a[i]; } else if (a[i] == a[i + 1]) { c = c; } else { c = c + n + a[i + 1] - a[i]; } } c = a[0] + c - 1; printf( %lld , c); return 0; }
|
//
// Generated by Bluespec Compiler, version 2011.03.beta1 (build 23381, 2011-03-08)
//
// On Tue Apr 26 10:52:10 EDT 2011
//
//
// Ports:
// Name I/O size props
// pcie_tx O 4
// led O 8
// p200clk O 1
// CLK_GATE_p200clk O 1 const
// p200rst O 1
// sys0_clk I 1
// sys0_rstn I 1
// pcie_clk I 1 clock
// pcie_rstn I 1 reset
// pcie_rx_i I 4
// usr_sw_i I 8 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkFTop_htgs4(sys0_clk,
sys0_rstn,
pcie_clk,
pcie_rstn,
pcie_rx_i,
pcie_tx,
usr_sw_i,
led,
p200clk,
CLK_GATE_p200clk,
p200rst);
input sys0_clk;
input sys0_rstn;
input pcie_clk;
input pcie_rstn;
// action method pcie_rx
input [3 : 0] pcie_rx_i;
// value method pcie_tx
output [3 : 0] pcie_tx;
// action method usr_sw
input [7 : 0] usr_sw_i;
// value method led
output [7 : 0] led;
// oscillator and gates for output clock p200clk
output p200clk;
output CLK_GATE_p200clk;
// output resets
output p200rst;
// signals for module outputs
wire [7 : 0] led;
wire [3 : 0] pcie_tx;
wire CLK_GATE_p200clk, p200clk, p200rst;
// register freeCnt
reg [31 : 0] freeCnt;
wire [31 : 0] freeCnt$D_IN;
wire freeCnt$EN;
// register swReg
reg [7 : 0] swReg;
wire [7 : 0] swReg$D_IN;
wire swReg$EN;
// ports of submodule aliveLed_sb
wire aliveLed_sb$dD_OUT, aliveLed_sb$sD_IN, aliveLed_sb$sEN;
// ports of submodule linkLed_sb
wire linkLed_sb$dD_OUT, linkLed_sb$sD_IN, linkLed_sb$sEN;
// ports of submodule pciw_pcie_ep
wire [127 : 0] pciw_pcie_ep$tx_st_data0;
wire [3 : 0] pciw_pcie_ep$pcie_rx_in, pciw_pcie_ep$pcie_tx_out;
wire pciw_pcie_ep$ava_alive,
pciw_pcie_ep$ava_core_clk_out,
pciw_pcie_ep$ava_lnk_up,
pciw_pcie_ep$ava_srstn,
pciw_pcie_ep$rx_st_mask0,
pciw_pcie_ep$rx_st_ready0,
pciw_pcie_ep$tx_st_empty0,
pciw_pcie_ep$tx_st_eop0,
pciw_pcie_ep$tx_st_err0,
pciw_pcie_ep$tx_st_sop0,
pciw_pcie_ep$tx_st_valid0;
// remaining internal signals
wire swParity__h135, z__h559, z__h566, z__h573, z__h580, z__h587, z__h594;
// oscillator and gates for output clock p200clk
assign p200clk = sys0_clk ;
assign CLK_GATE_p200clk = 1'd1 ;
// output resets
assign p200rst = sys0_rstn ;
// value method pcie_tx
assign pcie_tx = pciw_pcie_ep$pcie_tx_out ;
// value method led
assign led =
{ ~swParity__h135,
swParity__h135,
aliveLed_sb$dD_OUT,
linkLed_sb$dD_OUT,
freeCnt[29:26] } ;
// submodule aliveLed_sb
SyncBit #(.init(1'd0)) aliveLed_sb(.sCLK(pciw_pcie_ep$ava_core_clk_out),
.dCLK(sys0_clk),
.sRST_N(pciw_pcie_ep$ava_srstn),
.sD_IN(aliveLed_sb$sD_IN),
.sEN(aliveLed_sb$sEN),
.dD_OUT(aliveLed_sb$dD_OUT));
// submodule linkLed_sb
SyncBit #(.init(1'd0)) linkLed_sb(.sCLK(pciw_pcie_ep$ava_core_clk_out),
.dCLK(sys0_clk),
.sRST_N(pciw_pcie_ep$ava_srstn),
.sD_IN(linkLed_sb$sD_IN),
.sEN(linkLed_sb$sEN),
.dD_OUT(linkLed_sb$dD_OUT));
// submodule pciw_pcie_ep
pcie_hip_s4gx_gen2_x4_128_wrapper pciw_pcie_ep(.sys0_clk(sys0_clk),
.sys0_rstn(sys0_rstn),
.pcie_clk(pcie_clk),
.pcie_rstn(pcie_rstn),
.pcie_rx_in(pciw_pcie_ep$pcie_rx_in),
.rx_st_mask0(pciw_pcie_ep$rx_st_mask0),
.rx_st_ready0(pciw_pcie_ep$rx_st_ready0),
.tx_st_data0(pciw_pcie_ep$tx_st_data0),
.tx_st_empty0(pciw_pcie_ep$tx_st_empty0),
.tx_st_eop0(pciw_pcie_ep$tx_st_eop0),
.tx_st_err0(pciw_pcie_ep$tx_st_err0),
.tx_st_sop0(pciw_pcie_ep$tx_st_sop0),
.tx_st_valid0(pciw_pcie_ep$tx_st_valid0),
.pcie_tx_out(pciw_pcie_ep$pcie_tx_out),
.ava_alive(pciw_pcie_ep$ava_alive),
.ava_lnk_up(pciw_pcie_ep$ava_lnk_up),
.rx_st_valid0(),
.rx_st_bardec0(),
.rx_st_be0(),
.rx_st_data0(),
.rx_st_sop0(),
.rx_st_eop0(),
.rx_st_empty0(),
.rx_st_err0(),
.tx_cred0(),
.tx_fifo_empty0(),
.ava_core_clk_out(pciw_pcie_ep$ava_core_clk_out),
.ava_srstn(pciw_pcie_ep$ava_srstn));
// register freeCnt
assign freeCnt$D_IN = freeCnt + 32'd1 ;
assign freeCnt$EN = 1'd1 ;
// register swReg
assign swReg$D_IN = usr_sw_i ;
assign swReg$EN = 1'd1 ;
// submodule aliveLed_sb
assign aliveLed_sb$sD_IN = pciw_pcie_ep$ava_alive ;
assign aliveLed_sb$sEN = 1'd1 ;
// submodule linkLed_sb
assign linkLed_sb$sD_IN = pciw_pcie_ep$ava_lnk_up ;
assign linkLed_sb$sEN = 1'd1 ;
// submodule pciw_pcie_ep
assign pciw_pcie_ep$pcie_rx_in = pcie_rx_i ;
assign pciw_pcie_ep$rx_st_mask0 = 1'b0 ;
assign pciw_pcie_ep$rx_st_ready0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_data0 = 128'h0 ;
assign pciw_pcie_ep$tx_st_empty0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_eop0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_err0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_sop0 = 1'b0 ;
assign pciw_pcie_ep$tx_st_valid0 = 1'b0 ;
// remaining internal signals
assign swParity__h135 = z__h594 ^ swReg[7] ;
assign z__h559 = swReg[0] ^ swReg[1] ;
assign z__h566 = z__h559 ^ swReg[2] ;
assign z__h573 = z__h566 ^ swReg[3] ;
assign z__h580 = z__h573 ^ swReg[4] ;
assign z__h587 = z__h580 ^ swReg[5] ;
assign z__h594 = z__h587 ^ swReg[6] ;
// handling of inlined registers
always@(posedge sys0_clk)
begin
if (!sys0_rstn)
begin
freeCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
swReg <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (freeCnt$EN) freeCnt <= `BSV_ASSIGNMENT_DELAY freeCnt$D_IN;
if (swReg$EN) swReg <= `BSV_ASSIGNMENT_DELAY swReg$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
freeCnt = 32'hAAAAAAAA;
swReg = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkFTop_htgs4
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n >> s; int cont = 0; for (int i = 0; i < n && s[i] == < ; i++, cont++) ; for (int i = n - 1; i >= 0 && s[i] == > ; i--, cont++) ; cout << cont << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long a[200010]; int main() { int n; long long sum = 0, MAX = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %I64d , a + i); sum += a[i]; MAX = max(a[i], MAX); } long long ans; if (sum % (n - 1) == 0) ans = sum / (n - 1); else ans = sum / (n - 1) + 1; ans = max(MAX, ans); printf( %I64d n , ans); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const ll MAX = 1e18 + 1; const int NN = 1e5 + 5; const int mod = 1e9 + 7; void solve() { string s1; cin >> s1; char vow[] = { a , e , o , u , i }; vector<int> ans; int i = 0; while (i < s1.size()) { set<char> s; for (int j = i; j < min(i + 3, (int)s1.size()); j++) { s.insert(s1[j]); } int cnt = 0; if (s.size() != 1) { for (auto ch : s) { for (int y = 0; y < 5; y++) { if (ch == vow[y]) cnt++; } } if (cnt == 0) { ans.push_back(i + 1); i++; } } i++; } int k = 0; for (int y = 0; y < s1.size(); y++) { cout << s1[y]; if (k < ans.size() && y == ans[k]) { cout << ; k++; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt = 1; while (tt--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int F[30030]; int n; int mod; int a[30030], id[30030]; int nxt[30030]; bool cmp(int i, int j) { return a[i] < a[j]; } int m; struct pnt { int l, r, i; pnt(int l = 0, int r = 0, int i = 0) : l(l), r(r), i(i){}; } q[30030]; bool operator<(pnt a, pnt b) { return b.l != a.l ? a.l < b.l : a.r < b.r; } int answer[30030]; int calc(int l, int r) { int s = 0, m = 0; for (int j, i = 1; i <= n; i++) { j = id[i]; if (j >= l && j <= r) { s = (s + F[++m] * a[j]) % mod; i = nxt[i]; } } return s; } int main() { scanf( %d %d , &n, &mod); F[1] = F[2] = 1 % mod; for (int i = 3; i <= n; i++) { F[i] = (F[i - 1] + F[i - 2]) % mod; } for (int i = 1; i <= n; i++) { scanf( %d , a + i); id[i] = i; } sort(id + 1, id + n + 1, cmp); nxt[n] = n; for (int j = n - 1; j >= 1; j--) { if (a[id[j]] == a[id[j + 1]]) { nxt[j] = nxt[j + 1]; } else { nxt[j] = j; } } for (int j = 1; j <= n; j++) { a[j] %= mod; } scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d %d , &q[i].l, &q[i].r); q[i].i = i; } sort(q + 1, q + m + 1); for (int i = 1; i <= m; i++) { if (i > 1 && q[i].l == q[i - 1].l && q[i].r == q[i - 1].r) { answer[q[i].i] = answer[q[i - 1].i]; } else { answer[q[i].i] = calc(q[i].l, q[i].r); } } for (int i = 1; i <= m; i++) { printf( %d n , answer[i]); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_SYMBOL_V
/**
* udp_dff$PR_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; struct edge { int u, v, st, nt; } e[MAXN * 2]; vector<int> lis; int hd[MAXN], etot, used[MAXN], in[MAXN], u[MAXN], v[MAXN]; void addedge(int u, int v, int st) { e[etot].u = u; e[etot].v = v; e[etot].st = st; e[etot].nt = hd[u]; hd[u] = etot++; } void dfs(int p) { used[p] = 1; lis.push_back(p); for (int i = hd[p]; ~i; i = e[i].nt) { if (used[e[i].v]) continue; dfs(e[i].v); } } queue<int> Q; int topsort() { for (int i = 0; i < (int)lis.size(); i++) if (!in[lis[i]]) Q.push(lis[i]); int cnt = 0, u; for (; !Q.empty();) { cnt++; u = Q.front(); Q.pop(); for (int i = hd[u]; ~i; i = e[i].nt) { if (!e[i].st) continue; in[e[i].v]--; if (!in[e[i].v]) Q.push(e[i].v); } } return cnt == (int)lis.size(); } int main() { int n, m; scanf( %d%d , &n, &m); etot = 0; memset(hd, -1, sizeof(hd)); for (int i = 0; i < m; i++) { scanf( %d%d , u + i, v + i); addedge(u[i], v[i], 1); addedge(v[i], u[i], 0); in[v[i]]++; } int ans = 0; for (int i = 1; i < n + 1; i++) { lis.clear(); if (!used[i]) dfs(i); if ((int)lis.size() == 0) continue; ans += (int)lis.size() - topsort(); } printf( %d n , ans); return 0; }
|
`default_nettype none
`include "common.h"
module mmu_if(
input wire iCLOCK,
input wire inRESET,
input wire iFREE_TLB_FLUSH,
/*************************
To Core
*************************/
//Core -> This
input wire iCORE_REQ,
output wire oCORE_LOCK,
input wire iCORE_DATA_STORE_ACK,
input wire [1:0] iCORE_MMU_MODE, //0=NoConvertion 1=none 2=1LevelConvertion 3=2LevelConvertion
input wire [31:0] iCORE_PDT, //Page Table Register
input wire [1:0] iCORE_ORDER,
input wire [3:0] iCORE_MASK,
input wire iCORE_RW,
input wire [31:0] iCORE_ADDR,
input wire [31:0] iCORE_DATA,
//This -> Core
output wire oCORE_REQ,
input wire iCORE_LOCK,
output wire oCORE_STORE_ACK,
output wire oCORE_PAGE_FAULT,
output wire oCORE_QUEUE_FLUSH,
output wire [63:0] oCORE_DATA,
output wire [27:0] oCORE_MMU_FLAGS,
/************************
To Memory
************************/
//This -> Memory
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire [1:0] oMEMORY_ORDER,
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW,
output wire [31:0] oMEMORY_ADDR,
output wire [31:0] oMEMORY_DATA,
//Memory -> This
input wire iMEMORY_REQ,
output wire oMEMORY_LOCK,
input wire [63:0] iMEMORY_DATA
);
localparam L_PARAM_STT_PFAULT_IDLE = 2'h0;
localparam L_PARAM_STT_PFAULT_QUEUEWAIT = 2'h1;
localparam L_PARAM_STT_PFAULT_TOCORE = 2'h2;
/********************************************************************************
Wire and Register
********************************************************************************/
//MMU <-> Memory
wire mmu2memory_req;
wire mmu2memory_lock;
wire mmu2memory_data_store_ack;
wire mmu2memory_rw;
//MMU <-> Matching
wire matching2mmu_full;
wire mmu2matching_type;
wire matching2coreout_type;
wire matching2mmu_empty;
//MMU Flags
wire mmu2mmufifo_req;
wire mmufifo2mmu_lock;
wire [27:0] mmu2mmufifo_flags;
wire [27:0] mmufifo2coreout_flags;
//Page Fault
wire mmu2core_pagefault;
reg [1:0] b_pagefault_state;
//Core Output Latch
reg b_coreout_req;
reg [63:0] b_coreout_data;
reg [27:0] b_coreout_mmu_flags;
//Condition
wire mmu2core_data_write_ack_condition = mmu2memory_req && mmu2memory_data_store_ack && !iMEMORY_LOCK;
wire mmu2memory_req_condition = mmu2memory_req && !iMEMORY_LOCK && !matching2mmu_full && !mmufifo2mmu_lock;
wire memory2mmu_lock_condition = iMEMORY_LOCK || matching2mmu_full || mmufifo2mmu_lock || (b_pagefault_state == L_PARAM_STT_PFAULT_QUEUEWAIT);
/********************************************************************************
Memory Management Unit
Dorect, 1level, 2level Address Convertion
********************************************************************************/
//MMU
mmu mmu(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//TLB Flash
.iTLB_FLASH(iFREE_TLB_FLUSH),
/***********************
Logic Addres Request
***********************/
.iLOGIC_REQ(iCORE_REQ),
.oLOGIC_LOCK(oCORE_LOCK),
.iLOGIC_DATA_STORE_ACK(iCORE_DATA_STORE_ACK),
.iLOGIC_MODE(iCORE_MMU_MODE), //0=NoConvertion 1=none 2=1LevelConvertion 3=2LevelConvertion
.iLOGIC_PDT(iCORE_PDT), //Page Directory Table
.iLOGIC_ORDER(iCORE_ORDER),
.iLOGIC_MASK(iCORE_MASK),
.iLOGIC_RW(iCORE_RW), //0=Read 1=Write
.iLOGIC_ADDR(iCORE_ADDR),
.iLOGIC_DATA(iCORE_DATA),
/***********************
MMU Flags Output
***********************/
.oMMUFLAGS_REQ(mmu2mmufifo_req),
.iMMUFLAGS_LOCK(mmufifo2mmu_lock),
.oMMUFLAGS_FLAGS(mmu2mmufifo_flags),
/***********************
Page Fault
***********************/
.oPAGEFAULT_VALID(mmu2core_pagefault),
/***********************
To Memory
***********************/
//MMU -> Memory
.oMEMORY_REQ(mmu2memory_req),
.iMEMORY_LOCK(memory2mmu_lock_condition),
.oMEMORY_DATA_STORE_ACK(mmu2memory_data_store_ack),
.oMEMORY_MMU_USE(mmu2matching_type),
.oMEMORY_ORDER(oMEMORY_ORDER),
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(mmu2memory_rw),
.oMEMORY_ADDR(oMEMORY_ADDR),
.oMEMORY_DATA(oMEMORY_DATA),
//Memory -> MMU
.iMEMORY_VALID(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oMEMORY_LOCK(mmu2memory_lock),
.iMEMORY_DATA(iMEMORY_DATA)
);
/********************************************************************************
Page Fault
********************************************************************************/
wire pagefault_condition = (b_pagefault_state == L_PARAM_STT_PFAULT_TOCORE);
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_pagefault_state <= L_PARAM_STT_PFAULT_IDLE;
end
else begin
case(b_pagefault_state)
L_PARAM_STT_PFAULT_IDLE:
begin
if(mmu2core_pagefault)begin
b_pagefault_state <= L_PARAM_STT_PFAULT_QUEUEWAIT;
end
end
L_PARAM_STT_PFAULT_QUEUEWAIT:
begin
if(matching2mmu_empty)begin
b_pagefault_state <= L_PARAM_STT_PFAULT_TOCORE;
end
end
L_PARAM_STT_PFAULT_TOCORE:
begin
if(!iCORE_LOCK)begin
b_pagefault_state <= L_PARAM_STT_PFAULT_IDLE;
end
end
endcase
end
end
/********************************************************************************
Memory Matching Queue
Memory access type queue.
Type 0 : Core Use
1 : MMU Use
********************************************************************************/
mist1032sa_arbiter_matching_queue #(16, 4, 1) MEM_MATCHING_QUEUE( //Queue deep : 16, Queue deep_n : 4, Flag_n : 2
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(pagefault_condition),
//Write
.iWR_REQ(mmu2memory_req_condition && !mmu2memory_data_store_ack),
.iWR_FLAG(mmu2matching_type),
.oWR_FULL(matching2mmu_full),
//Read
.iRD_REQ(iMEMORY_REQ && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oRD_VALID(),
.oRD_FLAG(matching2coreout_type),
.oRD_EMPTY(matching2mmu_empty)
);
/********************************************************************************
MMU Flags Queue
********************************************************************************/
`ifdef MIST1032ISA_ALTERA_PRIMITIVE
//FIFO Mode : Show Ahead Synchronous FIFO Mode
//Width : 8bit
//Depth : 16Word
//Asynchronous Reset : Use
//Synchronous Reset : Use
//Usedw : Use
//Full : Use
//Empty : Use
//Almost Full : Use(Value=2)
//Almost Empty : Use(Value=14)
//Overflow Checking : Disable
//Undesflow Checking : Disable
altera_primitive_sync_fifo_28in_28out_16depth MMUFLAGS_QUEUE(
.aclr(!inRESET), //Asynchronous Reset
.clock(iCLOCK), //Clock
.data(mmu2mmufifo_flags), //Data-In
.rdreq(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition), //Read Data Request
.sclr(pagefault_condition), //Synchthronous Reset
.wrreq(mmu2mmufifo_req && !memory2mmu_lock_condition), //Write Req
.almost_empty(),
.almost_full(),
.empty(),
.full(mmufifo2mmu_lock),
.q(mmufifo2coreout_flags), //Dataout
.usedw()
);
`elsif MIST1032ISA_XILINX_PRIMITIVE
`else
mist1032sa_sync_fifo #(28, 16, 4) MMUFLAGS_QUEUE(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(pagefault_condition),
.oCOUNT(),
.iWR_EN(mmu2mmufifo_req && !memory2mmu_lock_condition),
.iWR_DATA(mmu2mmufifo_flags),
.oWR_FULL(mmufifo2mmu_lock),
.iRD_EN(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oRD_DATA(mmufifo2coreout_flags),
.oRD_EMPTY()
);
`endif
/********************************************************************************
Core Output Latch
********************************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_coreout_req <= 1'b0;
b_coreout_data <= {64{1'b0}};
b_coreout_mmu_flags <= {28{1'b0}};
end
//Page Fault
else if(pagefault_condition)begin
b_coreout_req <= 1'b0;
b_coreout_data <= {64{1'b0}};
b_coreout_mmu_flags <= {28{1'b0}};
end
else begin
if(!iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition)begin
b_coreout_req <= iMEMORY_REQ && !matching2coreout_type;
b_coreout_data <= iMEMORY_DATA;
b_coreout_mmu_flags <= mmufifo2coreout_flags;
end
end
end
/********************************************************************************
Assign
********************************************************************************/
assign oCORE_REQ = b_coreout_req || mmu2core_data_write_ack_condition || pagefault_condition;
assign oCORE_STORE_ACK = mmu2core_data_write_ack_condition;
assign oCORE_PAGE_FAULT = pagefault_condition;
assign oCORE_QUEUE_FLUSH = pagefault_condition;
assign oCORE_DATA = b_coreout_data;
assign oCORE_MMU_FLAGS = b_coreout_mmu_flags;
assign oMEMORY_REQ = mmu2memory_req_condition;
assign oMEMORY_RW = mmu2memory_rw;
assign oMEMORY_LOCK = iCORE_LOCK || mmu2memory_lock || mmu2core_data_write_ack_condition;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const int maxn = 300009; long long fac[maxn], invfac[maxn], A[33], B[33], in[maxn], idx[maxn]; vector<int> L[maxn], R[maxn]; int n, m; long long mpw(long long a, long long b) { long long c = 1; while (b) { if (b & 1ll) c = c * a % mod; a = a * a % mod; b >>= 1; } return c; } void init() { fac[0] = 1; for (int i = 1; i < maxn; ++i) fac[i] = fac[i - 1] * i % mod; invfac[maxn - 1] = mpw(fac[maxn - 1], mod - 2); for (int i = maxn - 2; i >= 0; --i) invfac[i] = invfac[i + 1] * (i + 1) % mod; } long long C(int a, int b) { if (a < b || b < 0) return 0; return fac[a] * invfac[b] % mod * invfac[a - b] % mod; }; int main() { ios_base::sync_with_stdio(false), cout.tie(0), cin.tie(0); cin >> n >> m; vector<std::vector<int>> add(n + 1), del(n + 1); for (int i = 1; i <= n; ++i) { int l, r; cin >> l >> r; L[l].push_back(i); R[r].push_back(i); add[l].push_back(i - 1); del[r].push_back(i - 1); } int idxtot = 0, cc = 0; memset(idx, -1, sizeof idx); std::vector<int> a(m), b(m); std::vector<int> id(n, -1); for (int i = 0; i < m; ++i) { cin >> A[i] >> B[i]; a[i] = A[i] - 1; b[i] = B[i] - 1; if (idx[A[i]] == -1) idx[A[i]] = idxtot++; if (idx[B[i]] == -1) idx[B[i]] = idxtot++; if (id[a[i]] == -1) id[a[i]] = cc++; if (id[b[i]] == -1) id[b[i]] = cc++; } init(); long long premask = 0, tot = 0, masktot = 0, curmask = 0, res = 0; vector<long long> cnt(m + 1); cnt[0] = 1; std::vector<int> ways(m + 1); std::vector<int> in2(n); ways[0] = 1; long long mask = 0; int tot2 = 0, tp = 0; int ans = 0; for (int i = 1; i <= n; ++i) { for (int j : L[i]) { in[j] = 1; if (idx[j] == -1) tot++; else masktot++; } for (auto x : add[i]) { in2[x] = 1; ++(id[x] == -1 ? tot2 : tp); } curmask = 0; for (int j = 0; j < m; ++j) { if (in[A[j]]) curmask |= 1ll << idx[A[j]]; if (in[B[j]]) curmask |= 1ll << idx[B[j]]; } long long nMask = 0; for (int j = 0; j < m; ++j) { if (in2[a[j]]) nMask |= 1ll << id[a[j]]; if (in2[b[j]]) nMask |= 1ll << id[b[j]]; } if (nMask != curmask) { cout << 1 << n ; return 0; } if (mask != premask) { cout << 3; return 0; } if (tp != masktot) { cout << 4; return 0; } if (nMask != mask) { mask = nMask; std::fill(ways.begin(), ways.end(), 0); std::function<void(int, int64_t, int)> dfs1 = [&](int x, int64_t s, int coef) { if (x == m) { int p = __builtin_popcountll(s); for (int j = 0; j <= m; ++j) ways[j] = (ways[j] + 1ll * coef * C(tp - p, j - p)) % mod; return; } if (in2[a[x]] && in2[b[x]]) dfs1(x + 1, s | 1ll << id[a[x]] | 1ll << id[b[x]], mod - coef); dfs1(x + 1, s, coef); }; dfs1(0, 0, 1); } if (premask != curmask) { for (int j = 0; j <= m; ++j) cnt[j] = 0; std::function<void(int, int64_t, int)> dfs1 = [&](int x, int64_t s, int coef) { if (x == m) { int p = __builtin_popcountll(s); for (int j = 0; j <= m; ++j) cnt[j] = (cnt[j] + 1ll * coef * C(tp - p, j - p)) % mod; return; } if (in[A[x]] && in[B[x]]) dfs1(x + 1, s | 1ll << idx[A[x]] | 1ll << idx[B[x]], mod - coef); dfs1(x + 1, s, coef); }; dfs1(0, 0, 1); } premask = curmask; for (int j = 0; j <= m; ++j) if (cnt[j] != ways[j]) { for (int x = 0; x < n; ++x) assert(in[x + 1] == in2[x]); cout << 2; return 0; } for (int j = 0; j <= m; ++j) ans = (ans + 1ll * ways[j] * C(tot2, i - j)) % mod; for (int j = 0; j <= m; ++j) res = (res + cnt[j] * C(tot, i - j) % mod) % mod; assert(ans == res); for (int j : R[i]) { in[j] = 0; if (idx[j] == -1) tot--; else masktot--; } for (auto x : del[i]) { in2[x] = 0; --(id[x] == -1 ? tot2 : tp); } } cout << res; return 0; }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1ns / 10ps
//
// CY7C1356
// Simulatiom of Verilog model
//
//
//
// test bench for US vector input
//
//
// define speed 166MHz
`define tx10 #6
`define tx08 #4.8
`define tx05 #3
`define tx04 #2.4
`define tx02 #1.2
/*
`define tx10 #4.0 // period
`define tx08 #3.2 //0.8 period
`define tx05 #2.0 //0.5 period 250MHZ
`define tx04 #1.6 //0.4 period
`define tx02 #0.8 //0.2 period
`define tx10 #4.4 // period
`define tx08 #3.52 //0.8 period
`define tx05 #2.2 //0.5 period 225MHZ
`define tx04 #1.76 //0.4 period
`define tx02 #0.88 //0.2 period
`define tx10 #5 // period
`define tx08 #4 //0.8 period
`define tx05 #2.5 //0.5 period 200MHZ
`define tx04 #2.0 //0.4 period
`define tx02 #1.0 //0.2 period
*/
module rw_test;
`define num_vectors 126
`define impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb}
reg [57:1] lsim_vectors [1:`num_vectors];
reg clk;
reg adv_lb;
reg ce1b; //cs1b
reg ce2; //cs2
reg ce3b; //cs3b
reg [1:0] bwb;
reg bweb;
reg oeb;
reg ftb;
reg mode; //lbob
reg cenb; //zz
reg tp42; //sclk
reg tp39; //se
reg tp38; //tm
reg [19:0] a;
reg [17:0] io;
reg [17:0] tsti;
reg vddq;
reg vssqr;
reg iosel;
wire [17:0] d = iosel ? io[17:0] : 18'bz;
reg noti3;
reg strb,j;
integer vector,i;
cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);
initial
begin
$dumpfile("dumpfile.dump");
$dumpvars(0,rw_test);
end
initial
begin
io = 18'bz;
ftb = 1;
oeb = 0;
a[19:16] = 4'h0;
mode = 0;
strb = 0;
tp38 = 0;
tp39 = 0;
tp42 = 0;
`tx02;
forever `tx05 strb = ~strb;
end
initial
begin
clk = 0;
forever `tx05 clk =~clk;
end
initial
begin
$readmemb("cy1356.inp", lsim_vectors); //load input vector file
`impi = lsim_vectors[1]; //apply 1st test vector
for (vector = 2; vector <= `num_vectors; vector = vector + 1)
@(posedge strb)
begin
`impi = lsim_vectors[vector];
io[16:13] = io[07:04];
io[12:09] = io[07:04];
io[07:04] = io[03:00];
io[03:00] = io[03:00];
io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9];
io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0];
tsti[16:13] = tsti[07:04];
tsti[12:09] = tsti[07:04];
tsti[07:04] = tsti[03:00];
tsti[03:00] = tsti[03:00];
tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9];
tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0];
if (io === 18'hxxxxx)
iosel = `tx05 0;
else
iosel = `tx05 1;
end
#15 $finish; // This prevents simulation beyond end of test patterns
end
always@(posedge clk)
begin
if (io !== 18'hxxxxx) //input cycle
begin
$display("NOTICE : 001 : line = %d OK",vector -1);
end
else //do the test
begin
if (d == tsti)
begin
$display("NOTICE : 002 : line = %d OK",vector -1);
end
else
begin
j =0;
for (i =0;i< 18; i=i+1)
begin
if(tsti[i] !== 1'bx)
begin
if (d[i] !== tsti[i]) j = 1;
end
else
j = 0;
end
if (j)
$display("ERROR *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti);
else
$display("NOTICE : 003 : line = %d OK",vector -1);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int A[N]; long long sum = 0, ans = 0; bool state; map<int, int> cnt; int main() { cnt[0] = 1; int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> A[i]; } for (int i = 0; i < n; i++) { if (A[i] > m) sum++; else if (A[i] < m) sum--; state = state | (A[i] == m); if (state) { ans += (cnt[sum] + cnt[sum - 1]); continue; } cnt[sum]++; } cout << ans << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MM_T_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_MM_T_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_MM_T
);
localparam N = 6; // Para definir el número de bits del contador (hasta 59->6 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 6'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 9)
begin
if (enUP)
begin
if (q_act >= 6'd59) q_next = 6'd0;
else q_next = q_act + 6'd1;
end
else if (enDOWN)
begin
if (q_act == 6'd0) q_next = 6'd59;
else q_next = q_act - 6'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
6'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
6'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
6'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
6'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
6'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
6'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
6'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
6'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
6'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
6'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
6'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
6'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
6'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
6'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
6'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
6'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
6'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
6'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
6'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
6'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
6'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
6'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
6'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
6'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
6'd24: begin digit1 = 4'b0010; digit0 = 4'b0100; end
6'd25: begin digit1 = 4'b0010; digit0 = 4'b0101; end
6'd26: begin digit1 = 4'b0010; digit0 = 4'b0110; end
6'd27: begin digit1 = 4'b0010; digit0 = 4'b0111; end
6'd28: begin digit1 = 4'b0010; digit0 = 4'b1000; end
6'd29: begin digit1 = 4'b0010; digit0 = 4'b1001; end
6'd30: begin digit1 = 4'b0011; digit0 = 4'b0000; end
6'd31: begin digit1 = 4'b0011; digit0 = 4'b0001; end
6'd32: begin digit1 = 4'b0011; digit0 = 4'b0010; end
6'd33: begin digit1 = 4'b0011; digit0 = 4'b0011; end
6'd34: begin digit1 = 4'b0011; digit0 = 4'b0100; end
6'd35: begin digit1 = 4'b0011; digit0 = 4'b0101; end
6'd36: begin digit1 = 4'b0011; digit0 = 4'b0110; end
6'd37: begin digit1 = 4'b0011; digit0 = 4'b0111; end
6'd38: begin digit1 = 4'b0011; digit0 = 4'b1000; end
6'd39: begin digit1 = 4'b0011; digit0 = 4'b1001; end
6'd40: begin digit1 = 4'b0100; digit0 = 4'b0000; end
6'd41: begin digit1 = 4'b0100; digit0 = 4'b0001; end
6'd42: begin digit1 = 4'b0100; digit0 = 4'b0010; end
6'd43: begin digit1 = 4'b0100; digit0 = 4'b0011; end
6'd44: begin digit1 = 4'b0100; digit0 = 4'b0100; end
6'd45: begin digit1 = 4'b0100; digit0 = 4'b0101; end
6'd46: begin digit1 = 4'b0100; digit0 = 4'b0110; end
6'd47: begin digit1 = 4'b0100; digit0 = 4'b0111; end
6'd48: begin digit1 = 4'b0100; digit0 = 4'b1000; end
6'd49: begin digit1 = 4'b0100; digit0 = 4'b1001; end
6'd50: begin digit1 = 4'b0101; digit0 = 4'b0000; end
6'd51: begin digit1 = 4'b0101; digit0 = 4'b0001; end
6'd52: begin digit1 = 4'b0101; digit0 = 4'b0010; end
6'd53: begin digit1 = 4'b0101; digit0 = 4'b0011; end
6'd54: begin digit1 = 4'b0101; digit0 = 4'b0100; end
6'd55: begin digit1 = 4'b0101; digit0 = 4'b0101; end
6'd56: begin digit1 = 4'b0101; digit0 = 4'b0110; end
6'd57: begin digit1 = 4'b0101; digit0 = 4'b0111; end
6'd58: begin digit1 = 4'b0101; digit0 = 4'b1000; end
6'd59: begin digit1 = 4'b0101; digit0 = 4'b1001; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_MM_T = {digit1,digit0};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int max(long long int a, long long int b) { if (a > b) return a; return b; } long long int min(long long int a, long long int b) { if (a < b) return a; return b; } long long int msb(long long int n) { long long int ans; for (long long int i = 31; i >= 0; i--) if ((1LL << i) & (n)) { ans = i; break; } return ans; } long long power(long long x, int y, int p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int modFact(long long int n, long long int p) { if (n >= p) return 0; long long int result = 1; for (long long int i = 1; i <= n; i++) result = (result * i) % p; return result; } long long modInverse(long long n, int p) { return power(n, p - 2, p); } long long nCrModPFermat(long long n, int r, int p) { if (r == 0) return 1; long long fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } vector<long long int> primes; void sieve(long long int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long int p = 2; p <= n; p++) { if (prime[p] == true) { for (long long int i = p * p; i <= n; i += p) prime[i] = false; } } for (long long int p = 2; p <= n; p++) if (prime[p]) primes.push_back(p); } vector<long long int> adj[100001], rev[100001]; bool vis[100001], recur[100001]; void init(long long int n) { for (long long int i = 0; i <= n; i++) { adj[i].clear(); rev[i].clear(); vis[i] = false; recur[i] = false; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n, x, k; cin >> n >> x >> k; long long int ar[n]; for (int i = 0; i < n; i++) cin >> ar[i]; if (x > k) cout << n << endl; else { int ct = 0; for (int i = 0; i < n; i++) { if (ar[i] <= x) ct++; } double ans = double(ct) / 2.0; cout << ceil(ans) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int m, x, p[100005], h[100005], cnt; long long n; int ksm(int a, long long k) { if (!k) return 1; int p = ksm(a, k / 2); if (k & 1) return (long long)p * p % 1000000007 * a % 1000000007; return (long long)p * p % 1000000007; } int Getval(long long n, int x) { int ret = 1; while (n) { n /= x; ret = (long long)ret * ksm(x, n) % 1000000007; } return ret; } int main() { scanf( %d%I64d , &x, &n); int m = int(sqrt(x)) + 1, ans = 1; for (int i = 2; i <= m; i++) { if (x % i == 0) { while (x % i == 0) x /= i; ans = (long long)ans * Getval(n, i) % 1000000007; } } if (x > 1) ans = (long long)ans * Getval(n, x) % 1000000007; printf( %d n , ans); }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex4_pmem.v when simulating
// the core, virtex4_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex4_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex4"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex4"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex4_pmem is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 55; int n, num, h[N], siz[N], e[N << 1], pre[N << 1]; double g[N], C[N][N], f[N][N]; inline void add(int x, int y) { e[++num] = y, pre[num] = h[x], h[x] = num; } void dfs(int u, int fa = 0) { memset(f[u], 0, sizeof f[u]), f[u][0] = siz[u] = 1; for (int i = h[u]; i; i = pre[i]) if (e[i] != fa) { dfs(e[i], u), siz[u] += siz[e[i]]; memset(g, 0, sizeof g); for (int j = 0; j < siz[e[i]]; ++j) g[j] = f[e[i]][j] * (siz[e[i]] - j); for (int j = 1; j <= siz[e[i]]; ++j) for (int k = 0; k < j; ++k) g[j] += f[e[i]][k] / 2; for (int j = siz[u]; j--;) { f[u][j] = f[u][j] * g[0] * C[siz[u] - 1 - j][siz[e[i]]]; for (int k = 1; k <= siz[e[i]]; ++k) f[u][j] += f[u][j - k] * g[k] * C[siz[u] - 1 - j][siz[e[i]] - k] * C[j][k]; } } } int main() { scanf( %d , &n); for (int i = 1, x, y; i < n; ++i) scanf( %d%d , &x, &y), add(x, y), add(y, x); C[0][0] = 1; for (int i = 1; i <= n; ++i) for (int j = 0; j <= i; ++j) C[i][j] = (j ? C[i - 1][j - 1] : 0) + C[i - 1][j]; double k = 1; for (int i = 1; i < n; ++i) k /= i; for (int i = 1; i <= n; ++i) dfs(i), printf( %.10lf n , f[i][n - 1] * k); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// i2cSlaveTopAltera.v ////
//// ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// You will need to modify this file to implement your
//// interface.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"
module i2cSlaveTopAltera (
clk,
sda,
scl,
LED
);
input clk;
inout sda;
input scl;
output LED;
//local wires and regs
reg [1:0] rstReg;
wire rst;
wire pll_locked;
wire [7:0] myReg0;
assign LED = myReg0[0];
i2cSlave u_i2cSlave(
.clk(clk),
.rst(rst),
.sda(sda),
.scl(scl),
.myReg0(myReg0),
.myReg1(),
.myReg2(),
.myReg3(),
.myReg4(8'h12),
.myReg5(8'h34),
.myReg6(8'h56),
.myReg7(8'h78)
);
pll_48MHz pll_48MHz_inst (
.inclk0 ( clk ),
.locked( pll_locked)
);
//generate sync reset from pll lock signal
always @(posedge clk) begin
rstReg[1:0] <= {rstReg[0], ~pll_locked};
end
assign rst = rstReg[1];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300300; int n, k, uf[2 * MAXN], cnt[2 * MAXN], ans; vector<int> f[MAXN]; char s[MAXN]; int find(int x) { return (uf[x] != -1 ? uf[x] = find(uf[x]) : x); } void join(int x, int y) { if ((x = find(x)) == (y = find(y))) return; cnt[x] += cnt[y]; uf[y] = x; } int main() { scanf( %d %d %s , &n, &k, s + 1); memset(uf, -1, sizeof uf); cnt[1] = MAXN; for (int i = 1, c; i <= k; ++i) { cnt[2 * i + 1] = 1; scanf( %d , &c); for (int j = 1, x; j <= c; ++j) scanf( %d , &x), f[x].push_back(i); } for (int i = 1; i <= n; ++i) { if (!f[i].empty()) { if (f[i].size() == 1) f[i].push_back(0); bool b = s[i] == 0 ; if (find(2 * f[i][0]) != find(2 * f[i][1] ^ b)) { ans -= min(cnt[find(2 * f[i][0])], cnt[find(2 * f[i][0] + 1)]); ans -= min(cnt[find(2 * f[i][1])], cnt[find(2 * f[i][1] + 1)]); join(2 * f[i][0], 2 * f[i][1] ^ b), join(2 * f[i][0] + 1, 2 * f[i][1] + 1 ^ b); ans += min(cnt[find(2 * f[i][0])], cnt[find(2 * f[i][0] + 1)]); } } printf( %d n , ans); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 100 * 1000 + 5; int xs, ys, xt, yt, n, a[N], b[N], r[N]; map<pair<int, int>, int> mark; map<pair<int, int>, int> dist; int dx[] = {1, -1, 0, 0, 1, 1, -1, -1}; int dy[] = {0, 0, 1, -1, 1, -1, 1, -1}; void bfs(int x, int y) { queue<pair<int, int> > q; dist[{x, y}] = 0; q.push({x, y}); while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); x = p.first, y = p.second; for (int i = 0; i < 8; i++) { int nx = x + dx[i], ny = y + dy[i]; if (!mark[{nx, ny}]) continue; else if (dist[{nx, ny}] > dist[{x, y}] + 1) { dist[{nx, ny}] = dist[{x, y}] + 1; q.push({nx, ny}); } } } } void input() { cin >> xs >> ys >> xt >> yt >> n; for (int i = 0; i < n; i++) cin >> r[i] >> a[i] >> b[i]; } void solve() { for (int i = 0; i < n; i++) { for (int j = a[i]; j <= b[i]; j++) { mark[{r[i], j}] = true; dist[{r[i], j}] = 1e9; } } bfs(xs, ys); } void output() { int ans = dist[{xt, yt}]; if (ans == 1e9) cout << -1 << n ; else cout << ans << n ; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); input(); solve(); output(); }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the select of a memory word in a continuous assignment.
*/
module main;
reg [1:0] a [3:0];
reg [1:0] s = 0;
wire [1:0] b = a[s];
initial begin
a[0] = 3;
a[1] = 2;
a[2] = 1;
a[3] = 0;
end
initial begin
#1 if (b !== 3) begin
$display("FAILED -- s=%b, b=%b", s, b);
$finish;
end
s = 1;
#1 if (b !== 2) begin
$display("FAILED -- s=%b, b=%b", s, b);
$finish;
end
s = 2;
#1 if (b !== 1) begin
$display("FAILED -- s=%b, b=%b", s, b);
$finish;
end
s = 3;
#1 if (b !== 0) begin
$display("FAILED -- s=%b, b=%b", s, b);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int x, x0, y, y0; cin >> x >> y >> x0 >> y0; char s[100013]; cin >> s; int a[513][513] = {}; int num = 0; for (int i = 0; s[i] != 0 ; i++) { if (a[x0][y0] != 1) { cout << 1 ; num++; } else { cout << 0 ; } a[x0][y0] = 1; if (s[i] == U && x0 > 1) { x0--; } if (s[i] == D && x0 < x) { x0++; } if (s[i] == L && y0 > 1) { y0--; } if (s[i] == R && y0 < y) { y0++; } } cout << (x * y) - num; return 0; }
|
module cov_tl_stage
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input ld_st_miss
, input mhu_miss_match
, input dma_miss_match
, input ld_st_hit
, input data_mem_pkt_ready_i
, input stat_mem_pkt_ready_i
, input v_i
, input bsg_cache_non_blocking_decode_s decode_i
, input miss_fifo_ready_i
, input recover_i
, input v_tl_r
, input mhu_tag_mem_pkt_v_i
, input mhu_idle_i
);
wire decode_mgmt_op = decode_i.mgmt_op;
covergroup cg_miss_match @ (negedge clk_i iff ld_st_miss);
coverpoint mhu_miss_match;
coverpoint dma_miss_match;
cross mhu_miss_match, dma_miss_match {
ignore_bins both_match = binsof(mhu_miss_match) intersect {1'b1}
&& binsof(dma_miss_match) intersect {1'b1};
}
endgroup
covergroup cg_ld_st_hit @ (negedge clk_i iff ld_st_hit);
coverpoint v_i;
coverpoint data_mem_pkt_ready_i;
coverpoint stat_mem_pkt_ready_i;
coverpoint decode_mgmt_op;
cross v_i, data_mem_pkt_ready_i, stat_mem_pkt_ready_i, decode_mgmt_op {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
}
endgroup
covergroup cg_ld_st_miss @ (negedge clk_i iff ld_st_miss);
coverpoint miss_fifo_ready_i;
coverpoint v_i;
coverpoint decode_mgmt_op;
cross v_i, miss_fifo_ready_i, decode_mgmt_op {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
}
endgroup
covergroup cg_tl_empty @ (negedge clk_i iff ~v_tl_r);
coverpoint recover_i;
coverpoint mhu_tag_mem_pkt_v_i;
coverpoint decode_mgmt_op;
coverpoint v_i;
coverpoint mhu_idle_i;
cross v_i, recover_i, mhu_tag_mem_pkt_v_i, decode_mgmt_op, mhu_idle_i {
ignore_bins invalid_mgmt_op = binsof(v_i) intersect {1'b0}
&& binsof(decode_mgmt_op) intersect {1'b1};
ignore_bins recover_mhu_pkt = binsof(recover_i) intersect {1'b1}
&& binsof(mhu_tag_mem_pkt_v_i) intersect {1'b1};
ignore_bins mhu_idle = (binsof(recover_i) intersect {1'b1} || binsof(mhu_tag_mem_pkt_v_i) intersect {1'b1})
&& binsof(mhu_idle_i) intersect {1'b1};
}
endgroup
initial begin
cg_miss_match mm = new;
cg_ld_st_hit ls = new;
cg_ld_st_miss lsm = new;
cg_tl_empty te = new;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; string s, t; int lenX, lenY; long long dp[5009][5009]; inline long long go(int x, int y) { if (x < 0 || y < 0) return 0LL; long long &ret = dp[x][y]; if (ret != -1) return ret; ret = 0; if (y > 0) ret = go(x, y - 1); if (ret >= MOD) ret -= MOD; if (s[x] == t[y]) { ret++; if (x > 0 && y > 0) ret = (ret + go(x - 1, y - 1)) % MOD; } return ret; } int main() { memset(dp, -1, sizeof(dp)); cin >> s >> t; lenX = (int)s.length(); lenY = (int)t.length(); long long ans = 0; for (int i = 0; i < lenX; ++i) { ans += go(i, lenY - 1); if (ans >= MOD) ans -= MOD; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1 << 30; const int N = 100100; char a[N], b[N]; int n, m, k, p[27]; int Par(int i) { return p[i] = (i == p[i]) ? i : Par(p[i]); } bool same(int i, int j) { return Par(i) == Par(j); } int comp[27]; void mrg(int i, int j) { if (same(i, j)) return; i = Par(i); j = Par(j); p[i] = p[j]; comp[i] += comp[j]; } vector<pair<char, char> > v; int main() { scanf( %d , &n); scanf( %s , a); scanf( %s , b); for (int i = 0; i < 26; i++) { p[i] = i; comp[i] = 1; } for (int i = 0; i < n; i++) { if (same(b[i] - a , a[i] - a )) continue; mrg(b[i] - a , a[i] - a ); v.push_back({a[i], b[i]}); } printf( %d n , v.size()); for (auto x : v) printf( %c %c n , x.first, x.second); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double Pi = acos(-1); namespace { template <typename T> inline void read(T &x) { x = 0; T f = 1; char s = getchar(); for (; !isdigit(s); s = getchar()) if (s == - ) f = -1; for (; isdigit(s); s = getchar()) x = (x << 3) + (x << 1) + (s ^ 48); x *= f; } } // namespace long long fun(long long x) { switch (x % 4) { case 0: return x; case 1: return 1; case 2: return x + 1; case 3: return 0; } } int main() { int n; read(n); long long xi, mi; long long ans = 0; for (int i = 1; i <= n; i++) { read(xi); read(mi); ans ^= fun(xi + mi - 1) ^ fun(xi - 1); } if (ans) cout << tolik << endl; else cout << bolik << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000023; long long int power(long long int a, long long int b) { long long int ans = 1; while (b) { if (b & 1) ans = (ans * a); b /= 2; a = (a * a); } return ans; } bool sortbysec(const pair<long long int, long long int> &a, const pair<long long int, long long int> &b) { if (a.first > b.first) return 1; else if (a.first == b.first) return (a.second < b.second); else return 0; } long long int hash1[N]; long long int p_pow[N]; string str; long long int n; void cal_pow() { long long int p = 31; for (long long int i = 0; i < N; i++) { if (i != 0) p_pow[i] = (p_pow[i - 1] * p) % 1000000007; else p_pow[i] = 1; } } void calc() { hash1[0] = str[0] - a + 1; for (long long int i = 1; i <= str.size() - 1; i++) { hash1[i] = (hash1[i - 1] + (p_pow[i] * (str[i] - a + 1)) % 1000000007) % 1000000007; } } long long int check(long long int val, long long int len) { for (long long int i = 1; i < n - len; i++) { long long int temp = (p_pow[n - 1 - i] * (hash1[i + len - 1] - hash1[i - 1] + 1000000007) % 1000000007) % 1000000007; if (temp == val) return 1; } return 0; } void solve() { cin >> str; cal_pow(); calc(); vector<pair<long long int, long long int>> v; n = str.size(); for (long long int i = 0; i < n - 1; i++) { long long int f = (p_pow[n - 1] * hash1[i]) % 1000000007; long long int s = (p_pow[i] * (hash1[n - 1] - hash1[n - i - 2] + 1000000007) % 1000000007) % 1000000007; if (f == s) v.push_back({i + 1, f}); } if (!v.size()) { cout << Just a legend << endl; return; } sort((v).begin(), (v).end()); v.push_back({n + 3, 1}); long long int l = 0, r = v.size() - 1; if (!check(v[0].second, v[0].first)) { cout << Just a legend << endl; return; } while ((l + 1) < r) { long long int mid = (l + r) / 2; if (check(v[mid].second, v[mid].first)) l = mid; else r = mid; } long long int idx = 0, len = v[l].first; while (len--) { cout << str[idx]; idx++; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int Test; Test = 1; long long int t = 0; while (t++ < Test) { solve(); } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`include "verilated.v"
module t;
// Note $sscanf already tested elsewhere
reg [3:0] n;
reg [63:0] q;
reg [16*8:1] wide;
reg [48*8:1] str;
reg [48*8:1] str2;
real r;
initial begin
n = 4'b1100;
q = 64'h1234_5678_abcd_0123;
wide = "hello-there12345";
$sformat(str, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
q = {q[62:0],1'b1};
$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
$swrite(str2, "e=%e", r);
$swrite(str2, "e=%f", r);
$swrite(str2, "e=%g", r);
r = 0.01;
$swrite(str2, "e=%e f=%f g=%g", r, r, r);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
$swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator
if (str2 !== "mod=top.v") $stop;
`else
if (str2 !== "mod=top.t") $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[200001]; int main() { int n, w; cin >> n >> w; for (int i = 0; i < 2 * n; i++) { cin >> a[i]; } sort(a, a + 2 * n); double x = min((double)a[0], (double)a[n] / 2); double ans = min((double)w, (double)3 * n * x); cout.precision(10); cout << fixed; cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_FUNCTIONAL_V
|
module register_ctrl_top(
input I_sys_clk ,
input I_sys_rst ,
//=====================System usb_uart_if===========================
output O_usb_uart_tx_req ,
output [7 : 0] O_usb_uart_tx_data ,
input I_usb_uart_tx_full ,
output O_usb_uart_rx_req ,
input [7 : 0] I_usb_uart_rx_data ,
input I_usb_uart_rx_empty ,
//==================================================================
output O_usb_dir ,
output O_motor_start ,
output tp ,
input I_key_start
);
//=======================================================================
reg R_usb_uart_rx_req ;
reg R_usb_uart_rx_req_d1 ;
reg R_tx_en ;
reg [7 : 0] R_tx_data ;
reg R_rx_en ;
reg [7 : 0] R_rx_data ;
reg R_usb_dir ;
reg R_motor_start ;
//=======================================================================
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_usb_uart_rx_req <= 1'd0 ;
end
else if(I_usb_uart_rx_empty == 1'b0) // if has data .then read
begin
R_usb_uart_rx_req <= 1'd1 ;
end
else
begin
R_usb_uart_rx_req <= 1'd0 ;
end
//
R_usb_uart_rx_req_d1 <= R_usb_uart_rx_req;
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_rx_en <= 1'd0 ;
R_rx_data <= 8'd0 ;
end
else if(R_usb_uart_rx_req_d1 == 1'b1)
begin
R_rx_en <= 1'd1 ;
R_rx_data <= I_usb_uart_rx_data ;
end
else
begin
R_rx_en <= 1'd0 ;
end
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_tx_en <= 1'd0 ;
R_tx_data <= 8'd0 ;
end
else if(I_usb_uart_tx_full==1'b0) // not full
begin
if(I_key_start==1'b1)
begin
R_tx_en <= 1'b1 ;//R_rx_en;
R_tx_data <= 8'h55 ;//R_rx_data;
end
else
begin
R_tx_en <= 1'b0 ;//R_rx_en;
end
end
else
begin
R_tx_en <= 1'b0 ;
end
end
always@(posedge I_sys_clk)
begin
if(I_sys_rst)
begin
R_usb_dir <= 1'd0; //目前采用了默认值
R_motor_start <= 1'b0;
end
else if(R_rx_en)
begin
case(R_rx_data)
8'h00:
begin
R_usb_dir <= 1'b0; //wr TO USB
end
8'hff:
begin
R_usb_dir <= 1'b1; // rd FROM USB
end
8'h02:
begin
R_motor_start <= 1'b1; // motor
end
endcase
end
else
begin
R_motor_start <= 1'b0;
end
end
assign O_usb_uart_rx_req = R_usb_uart_rx_req;
assign O_usb_uart_tx_req = R_tx_en ;
assign O_usb_uart_tx_data = R_tx_data;
assign O_usb_dir = R_usb_dir ;
assign O_motor_start = R_motor_start;
assign tp = R_rx_en & (&R_rx_data) & O_motor_start & O_usb_dir;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_BEHAVIORAL_V
|
//==================================================================================================
// Filename : antares_load_store_unit.v
// Created On : Sat Sep 5 10:38:09 2015
// Last Modified : Sat Nov 07 12:09:07 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Handle memory access; using a 4-way handshaking protocol:
// 1.- Assert enable signal.
// 2.- Ready goes high when data is available.
// 3.- If Ready is high; enable signal goes low.
// 4.- Next cycle; if enable is low, clear Ready signal.
//
// Time diagram:
//
// Clock Tick: | | | | | | | | | | |
// ______ ___
// Enable: __| |_______| |______
// __ __
// Ready: _____| |________| |____
//==================================================================================================
`include "antares_defines.v"
module antares_load_store_unit (
input clk, // Clock
input rst, // Reset
// Instruction interface: LSU <-> CPU
input [31:0] imem_address, // Instruction address
output reg [31:0] imem_data, // Instruction data
// MEM interface: LSU <-> CPU
input [31:0] dmem_address, // Data address
input [31:0] dmem_data_i, // Data to memory
input dmem_halfword, // halfword access
input dmem_byte, // byte access
input dmem_read, // read data memory
input dmem_write, // write data memory
input dmem_sign_extend, // read data (byte/half) with sign extended
output reg [31:0] dmem_data_o, // data from memory
// Instruction Port: LSU <-> MEM[instruction]
input [31:0] iport_data_i, // Data from memory
input iport_ready, // memory is ready
input iport_error, // Bus error
output [31:0] iport_address, // data address
output [3:0] iport_wr, // write = byte select, read = 0000,
output iport_enable, // enable operation
// Data Port : LSU <-> (MEM[data], I/O)
input [31:0] dport_data_i, // Data from memory
input dport_ready, // memory is ready
input dport_error, // Bus error
output [31:0] dport_address, // data address
output [31:0] dport_data_o, // data to memory
output reg [3:0] dport_wr, // write = byte select, read = 0000,
output dport_enable, // enable operation
// pipeline signals
input exception_ready,
input mem_kernel_mode, // For exception logic
input mem_llsc, // Atomic operation
input id_eret, // for llsc1
output exc_address_if, // panic
output exc_address_l_mem, // panic
output exc_address_s_mem, // panic
output imem_request_stall, // long operation
output dmem_request_stall // long operation
);
//--------------------------------------------------------------------------
// wire and registers
//--------------------------------------------------------------------------
wire exc_invalid_word_iaddress; // Not word-aligned instructions address
wire exc_invalid_space_iaddress; // try to access I/O space
wire exc_invalid_word_maddress; // Not word-aligned data address
wire exc_invalid_half_maddress; // Not halfword-aligned data address
wire exc_invalid_space_maddress; // try to access kernel space
wire dmem_operation; // Read or Write?
wire data_word; // LW/SW operation
wire exc_invalid_maddress;
wire write_enable;
wire read_enable;
reg [29:0] llsc_address;
reg llsc_atomic;
wire llsc_mem_write_mask;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
// Check for invalid access from instruction port.
assign exc_invalid_word_iaddress = imem_address[1] | imem_address[0];
assign exc_invalid_space_iaddress = 0; // TODO: check for invalid IM access.
// Check for invalid access from data port.
assign exc_invalid_word_maddress = (dmem_address[1] | dmem_address[0]) & data_word;
assign exc_invalid_half_maddress = dmem_address[0] & dmem_halfword;
assign exc_invalid_space_maddress = ~mem_kernel_mode & (dmem_address < `ANTARES_SEG_2_SPACE_LOW);
assign exc_invalid_maddress = exc_invalid_space_maddress | exc_invalid_word_maddress | exc_invalid_half_maddress;
// Exception signals.
assign exc_address_if = exc_invalid_word_iaddress | exc_invalid_space_iaddress;
assign exc_address_l_mem = dmem_read & exc_invalid_maddress;
assign exc_address_s_mem = dmem_write & exc_invalid_maddress;
assign write_enable = dmem_write & ~exc_invalid_maddress & ~llsc_mem_write_mask;
assign read_enable = dmem_read & ~exc_invalid_maddress;
assign dmem_operation = (write_enable ^ read_enable) | mem_llsc;
assign data_word = ~(dmem_halfword | dmem_byte);
assign imem_request_stall = iport_enable;
assign dmem_request_stall = dport_enable;
assign iport_enable = (~rst & ~iport_ready & ~exception_ready & ~iport_error);
assign dport_enable = ~dport_ready & dmem_operation & ~dport_error;
//--------------------------------------------------------------------------
// Load Linked and Store Conditional logic
//--------------------------------------------------------------------------
/*
From XUM project:
A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
operations. This register can be updated during stalls since it is not visible to
forward stages. It does not need to be flushed during exceptions, since ERET destroys
the atomicity condition and there are no detrimental effects in an exception handler.
The atomic condition is set with a Load Linked instruction, and cleared on an ERET
instruction or when any store instruction writes to one or more bytes covered by
the word address register. It does not update on a stall condition.
The MIPS32 spec states that an ERET instruction between LL and SC will cause the
atomicity condition to fail. This implementation uses the ERET signal from the ID
stage, which means instruction sequences such as "LL SC" could appear to have an
ERET instruction between them even though they don't. One way to fix this is to pass
the ERET signal through the pipeline to the MEM stage. However, because of the nature
of LL/SC operations (they occur in a loop which checks the result at each iteration),
an ERET will normally never be inserted into the pipeline programmatically until the
LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
they can still cause them in the LL SC sequence as well). In other words, by not passing
ERET through the pipeline, the only possible effect is a performance penalty. Also this
may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
which includes LL and SC.
*/
always @(posedge clk) begin
llsc_address <= (rst) ? 30'b0 : ( (dmem_read & mem_llsc) ? dmem_address[31:2] : llsc_address );
end
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
llsc_atomic <= 1'h0;
// End of automatics
end
else if (dmem_read) begin
llsc_atomic <= (mem_llsc) ? 1'b1 : llsc_atomic;
end
else if (id_eret | (~dmem_request_stall & dmem_write & (dmem_address[31:2] == llsc_address))) begin
llsc_atomic <= 1'b0;
end
else begin
llsc_atomic <= llsc_atomic;
end
end // always @ (posedge clk)
// If atomic and using the same address: enable the write. Else, ignore.
assign llsc_mem_write_mask = (mem_llsc & dmem_write & (~llsc_atomic | (dmem_address[31:2] != llsc_address)));
//--------------------------------------------------------------------------
// Map address and I/O ports
//--------------------------------------------------------------------------
assign iport_address = imem_address[31:0]; // full assign
assign dport_address = dmem_address[31:0]; // full assign
//--------------------------------------------------------------------------
// Read instruction memory
//--------------------------------------------------------------------------
assign iport_wr = 4'b0000; // DO NOT WRITE
always @(*) begin
imem_data = iport_data_i; // simple
end
//--------------------------------------------------------------------------
// Read from data data port.
//--------------------------------------------------------------------------
always @(*) begin
if (dmem_byte) begin
case (dmem_address[1:0])
2'b00 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[7]} }, dport_data_i[7:0] } : {24'b0, dport_data_i[7:0]};
2'b01 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[15]} }, dport_data_i[15:8] } : {24'b0, dport_data_i[15:8]};
2'b10 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[23]} }, dport_data_i[23:16] } : {24'b0, dport_data_i[23:16]};
2'b11 : dmem_data_o = (dmem_sign_extend) ? { {24{dport_data_i[31]} }, dport_data_i[31:24] } : {24'b0, dport_data_i[31:24]};
default : dmem_data_o = 32'hx;
endcase // case (dmem_address[1:0])
end
else if (dmem_halfword) begin
case (dmem_address[1])
1'b0 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[15]} }, dport_data_i[15:0] } : {16'b0, dport_data_i[15:0]};
1'b1 : dmem_data_o = (dmem_sign_extend) ? { {16{dport_data_i[31]} }, dport_data_i[31:16] } : {16'b0, dport_data_i[31:16]};
default : dmem_data_o = 32'hx;
endcase // case (dmem_address[1])
end
else if (mem_llsc & dmem_write) begin
dmem_data_o = (llsc_atomic & (dmem_address[31:2] == llsc_address)) ? 32'h0000_0001 : 32'h0000_0000;
end
else begin
dmem_data_o = dport_data_i;
end
end // always @ (*)
//--------------------------------------------------------------------------
// Write to data port
// Format data:
// byte : {b, b, b, b}
// half : {h, h}
// word : {w}
//
// Modify to implement Reverse Endian
//--------------------------------------------------------------------------
always @(*) begin
dport_wr = 4'b0000;
if (write_enable) begin
dport_wr[3] = (dmem_byte & (dmem_address[1:0] == 2'b11)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[2] = (dmem_byte & (dmem_address[1:0] == 2'b10)) | (dmem_halfword & dmem_address[1]) | data_word;
dport_wr[1] = (dmem_byte & (dmem_address[1:0] == 2'b01)) | (dmem_halfword & ~dmem_address[1]) | data_word;
dport_wr[0] = (dmem_byte & (dmem_address[1:0] == 2'b00)) | (dmem_halfword & ~dmem_address[1]) | data_word;
end
end
assign dport_data_o[31:24] = (dmem_byte) ? dmem_data_i[7:0] : ((dmem_halfword) ? dmem_data_i[15:8] : dmem_data_i[31:24]);
assign dport_data_o[23:16] = (dmem_byte | dmem_halfword) ? dmem_data_i[7:0] : dmem_data_i[23:16];
assign dport_data_o[15:8] = (dmem_byte) ? dmem_data_i[7:0]: dmem_data_i[15:8];
assign dport_data_o[7:0] = dmem_data_i[7:0];
endmodule // antares_load_store_unit
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } vector<pair<int, string> > ar[10005]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { int a, b; string s; cin >> s >> a >> b; ar[a].push_back({-b, s}); } for (int i = 1; i <= m; i++) { sort(ar[i].begin(), ar[i].end()); if ((int)(ar[i].size()) == 2) cout << ar[i][0].second << << ar[i][1].second << n ; else if (ar[i][1].first != ar[i][2].first) cout << ar[i][0].second << << ar[i][1].second << n ; else cout << ? n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__MAJ3_BEHAVIORAL_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__maj3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X, and1_out, and0_out);
buf buf0 (X , or1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, a[200001]; const double esl = 1e-11; double cal(double x) { double t = 0; double ans = 0; for (int i = 1; i <= n; i++) { if (t + a[i] - x < 0) { ans = max(ans, t); t = 0; } else { t += ((double)a[i] - x); ans = max(ans, t); } } ans = max(ans, t); double t1 = 0; for (int i = 1; i <= n; i++) { if (t1 + a[i] - x > 0) { ans = max(ans, -t1); t1 = 0; } else { t1 += ((double)a[i] - x); ans = max(ans, -t1); } } ans = max(ans, -t1); return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } double l = -(1e5); double r = 1e5; for (int i = 1; i <= 500; i++) { double d = (2.0 * l + r) / 3; double c = (2.0 * r + l) / 3; if (cal(d) > cal(c)) { l = d; } else r = c; } printf( %.10f , cal(l)); return 0; }
|
//------------------------------------------------------------------------------
// File : axi_mux.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: A simple axi mux
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module axi_mux (
input mux_select,
// mux inputs
input [7:0] tdata0,
input tvalid0,
input tlast0,
output reg tready0,
input [7:0] tdata1,
input tvalid1,
input tlast1,
output reg tready1,
// mux outputs
output reg [7:0] tdata,
output reg tvalid,
output reg tlast,
input tready
);
always @(mux_select or tdata0 or tvalid0 or tlast0 or tdata1 or
tvalid1 or tlast1)
begin
if (mux_select) begin
tdata = tdata1;
tvalid = tvalid1;
tlast = tlast1;
end
else begin
tdata = tdata0;
tvalid = tvalid0;
tlast = tlast0;
end
end
always @(mux_select or tready)
begin
if (mux_select) begin
tready0 = 1'b1;
end
else begin
tready0 = tready;
end
tready1 = tready;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
`define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d};
bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06};
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
bit [9*32-1:0] w9 = {32'hca800ac1,
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
bit [17*32-1:0] w17 = {32'hf1e322ac,
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
function [7:0] bytehash (input [32*32-1:0] data);
integer i;
bytehash = 0;
for (i=0; i<32*32; ++i) begin
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
end
return bytehash;
endfunction
// Aggregate outputs into a single result vector
// verilator lint_off WIDTH
wire [63:0] result = (bytehash(w4)
^ bytehash(w8m)
^ bytehash(w8)
^ bytehash(w8p)
^ bytehash(w9)
^ bytehash(w16m)
^ bytehash(w16)
^ bytehash(w16p)
^ bytehash(w17));
// verilator lint_on WIDTH
`define EXPECTED_SUM 64'hb6fdb64085fc17f5
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
// verilator lint_off SELRANGE
`checkhw(w4,3,32'h7c709753);
`checkhw(w4,2,32'hbc8f6059);
`checkhw(w4,1,32'h3b0db464);
`checkhw(w4,0,32'h721a8fad);
`checkhw(w8m,7,31'h7146e1bf);
`checkhw(w8m,6,32'ha8549e42);
`checkhw(w8m,5,32'hca6960bd);
`checkhw(w8m,4,32'h191b7f9b);
`checkhw(w8m,3,32'h93d79866);
`checkhw(w8m,2,32'hf4489e2b);
`checkhw(w8m,1,32'h8e9a3236);
`checkhw(w8m,0,32'h1d2a2d1d);
`checkhw(w8,7,32'hc211addc);
`checkhw(w8,6,32'he5d4a057);
`checkhw(w8,5,32'h5cbf88fe);
`checkhw(w8,4,32'h42cf42e2);
`checkhw(w8,3,32'heb584263);
`checkhw(w8,2,32'ha585f118);
`checkhw(w8,1,32'h231531c8);
`checkhw(w8,0,32'hc73f7b06);
`checkhw(w8p,8,1'b1);
`checkhw(w8p,7,32'h096aa54b);
`checkhw(w8p,6,32'h48aae18e);
`checkhw(w8p,5,32'hf9502cea);
`checkhw(w8p,4,32'h518c8b61);
`checkhw(w8p,3,32'h9e8641a2);
`checkhw(w8p,2,32'h0dc0249c);
`checkhw(w8p,1,32'hd421a87a);
`checkhw(w8p,0,32'hb8ee9199);
`checkhw(w9,8,32'hca800ac1);
`checkhw(w9,7,32'h0de4823a);
`checkhw(w9,6,32'ha51663ac);
`checkhw(w9,5,32'h96351446);
`checkhw(w9,4,32'h6b0bbcd5);
`checkhw(w9,3,32'h4a64b530);
`checkhw(w9,2,32'h4967d59a);
`checkhw(w9,1,32'hfcc17292);
`checkhw(w9,0,32'h57926621);
`checkhw(w16m,15,31'h77ad72c7);
`checkhw(w16m,14,32'h73aa9cbb);
`checkhw(w16m,13,32'h7ecf026d);
`checkhw(w16m,12,32'h985a3ed2);
`checkhw(w16m,11,32'hfe961c1d);
`checkhw(w16m,10,32'h7a01df72);
`checkhw(w16m,9,32'h79e13d71);
`checkhw(w16m,8,32'hb69e2e32);
`checkhw(w16m,7,32'h09fcbc45);
`checkhw(w16m,6,32'hcfd738c1);
`checkhw(w16m,5,32'hc197ac7c);
`checkhw(w16m,4,32'hc316d727);
`checkhw(w16m,3,32'h903034e4);
`checkhw(w16m,2,32'h92a047d1);
`checkhw(w16m,1,32'h6a5357af);
`checkhw(w16m,0,32'ha82ce9c8);
// verilator lint_on SELRANGE
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w4 = w4 >>> 1;
w8m = w8m >>> 1;
w8 = w8 >>> 1;
w8p = w8p >>> 1;
w9 = w9 >>> 1;
w16m = w16m >>> 1;
w16 = w16 >>> 1;
w16p = w16p >>> 1;
w17 = w17 >>> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module mvs_cart(
input nRESET,
input CLK_24M, CLK_12M, CLK_8M, CLK_68KCLKB, CLK_4MB,
input nAS, M68K_RW,
input [19:1] M68K_ADDR,
inout [15:0] M68K_DATA,
input nROMOE, nROMOEL, nROMOEU,
input nPORTADRS, nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU,
output nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
input nSLOTCS,
input [23:0] PBUS,
input CA4,
input S2H1,
input PCK1B,
input PCK2B,
output [31:0] CR,
output [7:0] FIXD,
inout [7:0] SDRAD,
input [9:8] SDRA_L,
input [23:20] SDRA_U,
input SDRMPX, nSDROE,
inout [7:0] SDPAD,
input [11:8] SDPA,
input SDPMPX, nSDPOE,
input SDRD0, SDRD1, nSDROM, nSDMRD,
input [15:0] SDA,
inout [7:0] SDD
);
mvs_prog PROG(nSDROE, SDRMPX, SDRA_U, SDRA_L, nSDPOE, SDPMPX, SDPA, nSLOTCS, nPORTADRS, nPORTWEL, nPORTWEU,
nPORTOEL, nPORTOEU, nROMOEL, nROMOEU, nAS, M68K_RW, M68K_DATA, M68K_ADDR, CLK_68KCLKB, nROMWAIT,
nPWAIT0, nPWAIT1, PDTACK, nROMOE, CLK_4MB, nRESET, SDPAD, SDRAD);
mvs_cha CHA(SDA, nSLOTCS, CR, CA4, S2H1, PCK2B, PCK1B, PBUS, CLK_24M, CLK_12M, CLK_8M, nRESET, FIXD,
SDRD0, SDRD1, nSDROM, nSDMRD, SDD);
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : rom_1p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Single Port Rom Model
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module rom_1p (
clk ,
cen_i ,
oen_i ,
addr_i ,
data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width = 32;
parameter Addr_Width = 8;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk; // clock input
input cen_i; // chip enable, low active
input oen_i; // data output enable, low active
input [Addr_Width-1:0] addr_i; // address input
output [Word_Width-1:0] data_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] data_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(posedge clk) begin
if (!cen_i)
data_r <= mem_array[addr_i];
else
data_r <= 'bx;
end
assign data_o = oen_i ? 'bz : data_r;
endmodule
|
#include <bits/stdc++.h> using namespace std; int T, n, a[100005], b[100005], f[22], F[22], u[22], m, dp[2222222], cnt[2222222], C; void ope(int x) { dp[x] = 0; for (int i = 1; i <= 20; ++i) { if ((1 << i) & x) { int y = x ^ (1 << i); if (dp[y] == -1) ope(y); if (!(y & f[i])) dp[x] |= dp[y]; } } if (dp[x]) C = max(C, cnt[x]); } void dfs(int x) { u[x] = 1; m |= (1 << x); for (int i = 1; i <= 20; ++i) if (!u[i] && (F[x] & (1 << i))) dfs(i); } int main() { for (int i = 1; i < 2222000; ++i) { if (i & 1) cnt[i] = cnt[i >> 1] + 1; else cnt[i] = cnt[i >> 1]; } scanf( %d , &T); while (T--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) { char c; scanf( %c , &c); a[i] = c - 96; } for (int i = 1; i <= n; ++i) { char c; scanf( %c , &c); b[i] = c - 96; } memset(f, 0, sizeof(f)); memset(F, 0, sizeof(F)); for (int i = 1; i <= n; ++i) if (a[i] != b[i]) f[a[i]] |= (1 << b[i]), F[b[i]] |= (1 << a[i]); for (int i = 1; i <= 20; ++i) F[i] |= f[i]; memset(u, 0, sizeof(u)); memset(dp, -1, sizeof(dp)); dp[0] = 1; int ans = 0; for (int i = 1; i <= 20; ++i) { if (!u[i]) { m = 0; C = 0; dfs(i); ope(m); ans += cnt[m] * 2 - 1 - C; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const int mod = 1e9 + 7; int a[N]; long long fac[30]; long long sum[N]; long long Contor(int* a, int n) { long long res = 0; for (int i = 1; i <= n; i++) { int cnt = 0; for (int j = i + 1; j <= n; j++) if (a[i] > a[j]) cnt++; res += cnt * fac[n - i]; } return res; } void ReContor(int* a, int n, long long k, int ed) { int vis[30] = {0}; for (int i = 1; i <= n; i++) { int cnt = k / fac[n - i], j; for (j = 1; j <= n; j++) if (!vis[j]) { if (!cnt) break; cnt--; } vis[j] = 1; a[i] = ed + j; k %= fac[n - i]; } } void init() { fac[0] = 1; for (int i = 1; i <= 20; i++) fac[i] = fac[i - 1] * i; } int main() { init(); int n, q; scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + i; int m = 15, ed = n - 15; if (n < 15) m = n, ed = 0; for (int i = 1; i <= m; i++) a[i] = ed + i; long long cnt = 0; while (q--) { int op; scanf( %d , &op); if (op == 1) { int l, r; scanf( %d%d , &l, &r); printf( %lld n , sum[r] - sum[l - 1]); } else { int x; scanf( %d , &x); cnt += x; ReContor(a, m, cnt, ed); for (int i = 1; i <= m; i++) sum[ed + i] = sum[ed + i - 1] + a[i]; for (int i = 1; i <= m; i++) a[i] = ed + i; } } return 0; }
|
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (9.125),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = ~resetn;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
`include "mem_beh.v"
`include "regfile_beh.v"
`include "components.v"
`include "control_units.v"
`include "alu_beh.v"
`include "mux2to1_beh.v"
module kustar;
reg clock, clear;
wire Zero;
// Signal //
/*
//Ex
[8:7] ALUOp
[6] ALUSrc
[5] RegDst,
//M
[4] Branch
[3] MemRead
[2] MemWrite
//WB
[1] RegWrite
[0] MemtoReg
*/
// IF_ID
reg [31:0] IF_ID_AddedPC;
reg [31:0] IF_ID_Inst;
// ID_EX
reg [31:0] ID_EX_AddedPC;
reg [31:0] ID_EX_ReadData1;
reg [31:0] ID_EX_ReadData2;
reg [31:0] ID_EX_ExtendedAddr;
reg [4:0] ID_EX_Inst20_16;
reg [4:0] ID_EX_Inst15_11;
reg [8:0] ID_EX_Signal;
// EX_MEM
reg [31:0] EX_MEM_AddedPC;
reg EX_MEM_Zero;
reg [31:0] EX_MEM_ALU_Result;
reg [31:0] EX_MEM_ReadData2;
reg [4:0] EX_MEM_RegWriteDst;
reg [4:0] EX_MEM_Signal;
// MEM_WB
reg [31:0] MEM_WB_MemReadData;
reg [31:0] MEM_WB_ALU_Result;
reg [4:0] MEM_WB_RegWriteDst;
reg [2:0] MEM_WB_Signal;
wire [31:0] MuxToPC, PCToInstMem, AddToIF_ID, InstMemToIF_ID, IF_ID_AddedPC_To_ID_EX;
wire [31:0] RegtoA, RegtoB, MuxtoWriteData, ExtendToID_EX, ShifttoConcat, JumpAddress;
wire [31:0] EX_MEM_TO_PC_MUX;
wire [4:0] MuxToRegDst;
wire [31:0] MuxToALU, ShiftToAdd, AddToEX_MEM_AddedPC, ALUOut;
wire [2:0] ALUcontrol;
wire [31:0] DataMemResult;
wire MemRead, MemWrite, MemtoReg, ALUSrc, RegWrite, RegDst, Branch;
wire [1:0] ALUOp;
wire JumpSignal;
reg [31:0] four;
reg yesItAlwaysTure;
reg yesItAlwyasFalse;
reg [31:0] unused;
mux4to1 PrePCMux (AddToIF_ID, EX_MEM_AddedPC, JumpAddress, JumpAddress, MuxToPC, {JumpSignal,{EX_MEM_Signal[4] & EX_MEM_Zero}});
single_register PC (MuxToPC, PCToInstMem, clock, clear, yesItAlwaysTure);
Adder PCAdder (PCToInstMem, four, AddToIF_ID);
mem InstMem (PCToInstMem, unused, InstMemToIF_ID, yesItAlwyasFalse, yesItAlwaysTure, clock);
shiftleft2 JumpShift (IF_ID_Inst, ShifttoConcat);
concatenate4to28 PCConcat (ShifttoConcat, PCToInstMem, JumpAddress);
registerfile Registers ({IF_ID_Inst[25:21]}, RegtoA, {IF_ID_Inst[20:16]}, RegtoB, MEM_WB_RegWriteDst, MuxtoWriteData, clock, yesItAlwyasFalse, MEM_WB_Signal[1]);
signextd SignExtend ({IF_ID_Inst[15:0]}, ExtendToID_EX);
mcu YesThisIsMCU (clock, clear, {IF_ID_Inst[31:26]},
MemRead, MemWrite, MemtoReg, ALUOp, ALUSrc, RegWrite, RegDst, Branch,
JumpSignal);
mux2to1 ALUMux (ID_EX_ReadData2, ID_EX_ExtendedAddr, MuxToALU, {ID_EX_Signal[6]});
mux2to1for5bit RegDstMux (ID_EX_Inst20_16, ID_EX_Inst15_11, MuxToRegDst, ID_EX_Signal[5]);
shiftleft2 Shift (ID_EX_ExtendedAddr, ShiftToAdd);
Adder BranchAdder (ID_EX_AddedPC, ShiftToAdd, AddToEX_MEM_AddedPC);
ALU YesThisIsALU (ID_EX_ReadData1, MuxToALU, ALUcontrol, ALUOut, Zero);
acu YesThisIsACU (ID_EX_ExtendedAddr[5:0], ID_EX_Signal[8:7], ALUcontrol);
mem DataMem (EX_MEM_ALU_Result, EX_MEM_ReadData2, DataMemResult, EX_MEM_Signal[2], EX_MEM_Signal[1], clock);
mux2to1 MemToRegMux (MEM_WB_ALU_Result, MEM_WB_MemReadData, MuxtoWriteData, MEM_WB_Signal[0]);
/*
module acu(funct, ALUOp, ALUcontrol);
input [5:0] funct;
input [1:0] ALUOp;
output [2:0] ALUcontrol;
-------------------------------------------------------
module mcu(clk, clr, OP, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst);
input clk, clr;
input [5:0] OP;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
output [1:0] PCSource, ALUOp, ALUSrcB;
-------------------------------------------------------------
// concatenate pcin[31-28] with datain[27-0] to form a jump address
module concatenate4to28(datain, pcin, pcout);
input [31:0] datain, pcin;
output [31:0] pcout;
-------------------------------------------------------------
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
output zero;
---------------------------------------------------------------
module mux4to1(datain0, datain1, datain2, datain3, dataout, select);
input [31:0] datain0, datain1, datain2, datain3;
input[1:0] select;
output [31:0] dataout;
-------------------------------------------
module shiftleft2(datain, dataout);
input [31:0] datain;
output [31:0] dataout;
-----------------------------------------------------------
module signextd(datain, dataout);
input [15:0] datain;
output [31:0] dataout;
------------------------------------------------------------
module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE);
input [4:0] ADDA,ADDB, ADDC;
input [31:0] DATAC;
input clk, clr, WE;
output [31:0] DATAA, DATAB;
---------------------------------------------
module single_register(datain, dataout, clk, clr, WE);
input [31:0] datain;
output [31:0] dataout;
input clk, clr, WE;
----------------
module mem(addr,datain,dataout, MemWrite, MemRead, clk);
input clk;
input [31:0] addr, datain;
output [31:0] dataout;
input MemWrite, MemRead;
------------------------------
module mux2to1(datain0,datain1, dataout, select);
input [31:0] datain0, datain1;
input select;
output [31:0] dataout;
*/
initial
forever #50 clock = ~clock;
initial
begin
clock = 1;
#5;
four = 4;
yesItAlwaysTure = 1;
yesItAlwyasFalse = 0;
clear = 1;
EX_MEM_Signal[4] = 0;
EX_MEM_Zero = 0;
/* we may not connect clear to register file and memory because we don't want our initial data get cleared*/
#10 clear = 0;
end
always @(negedge clock)
begin
#10
MEM_WB_MemReadData = DataMemResult;
MEM_WB_Signal = EX_MEM_Signal[1:0];
MEM_WB_ALU_Result = EX_MEM_ALU_Result;
MEM_WB_RegWriteDst = EX_MEM_RegWriteDst;
EX_MEM_Signal = ID_EX_Signal[4:0];
EX_MEM_Zero = Zero;
EX_MEM_AddedPC = AddToEX_MEM_AddedPC;
EX_MEM_ReadData2 = ID_EX_ReadData2;
EX_MEM_ALU_Result = ALUOut;
EX_MEM_RegWriteDst = MuxToRegDst;
ID_EX_AddedPC = IF_ID_AddedPC;
ID_EX_ReadData1 = RegtoA;
ID_EX_ReadData2 = RegtoB;
ID_EX_ExtendedAddr = ExtendToID_EX;
ID_EX_Inst20_16 = IF_ID_Inst[20:16];
ID_EX_Inst15_11 = IF_ID_Inst[15:11];
ID_EX_Signal = {ALUOp[1:0],ALUSrc,RegDst,Branch,MemRead,MemWrite,RegWrite,MemtoReg};
IF_ID_Inst = InstMemToIF_ID;
IF_ID_AddedPC = AddToIF_ID;
end
initial
#10000 $stop;
endmodule
|
// A verilog master that has a register array of data it uses to write to a slave.
// Each data is written to different address, and then read to verify it worked.
// Address space is assumed to be contiguous.
module wb_master #(
parameter BASE_ADDRESS = 0, // The first referable address. Is substracted from input address.
parameter DATA_WIDTH = 16, // The width of the both transferred and inputted data.
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_COUNT = 16, // How many values there are in the register array.
parameter AU_IN_DATA = 1
)(
input clk, // The mandatory clock, as this is synchronous logic.
input rst, // The mandatory reset, as this is synchronous logic.
input start, // Input used to signal that is is ok to start the masters.
output reg done, // Output used to signal that the masters are done sending.
output reg cyc_o, // Asserted by master for transfer.
output reg stb_o, // Asserted by master for transfer.
input ack_i, // Slave asserts acknowledge.
output reg we_o, // Write = 1, Read = 0.
output reg [DATA_WIDTH-1:0] dat_o, // Data from master to slave.
input [DATA_WIDTH-1:0] dat_i, // Data from slave to master.
output reg [ADDR_WIDTH-1:0] adr_o // The address of the data.
);
// We have as data to send as parameterized.
reg [DATA_WIDTH-1:0] dat [0:DATA_COUNT-1];
// Used to iterate dat.
reg [3:0] iterator;
// Status of start during the last cycle.
reg start_old;
// The current state.
reg [2:0] state;
// The available states.
parameter [2:0]
S_WAIT_START = 3'd0, // Waiting for start-signal
S_WRITE_INIT = 3'd1, // Initiating a write to slave.
S_WAIT_WRITE_ACK = 3'd2, // Waiting ack for wrtite from slave.
S_READ_INIT = 3'd3, // Initiating a read to slave.
S_WAIT_READ_ACK = 3'd4; // Waiting ack for wrtite from slave.
always @(posedge clk or posedge rst) begin
if(rst == 1'b0) begin
// Initialize dat with data.
dat[0] = 32'h00000000;
dat[1] = 32'h10001111;
dat[2] = 32'h20002222;
dat[3] = 32'h30003333;
dat[4] = 32'h40004444;
dat[5] = 32'h50005555;
dat[6] = 32'h60006666;
dat[7] = 32'h70007777;
dat[8] = 32'h80008888;
dat[9] = 32'h90009999;
dat[10] = 32'hA000AAAA;
dat[11] = 32'hB000BBBB;
dat[12] = 32'hC000CCCC;
dat[13] = 32'hD000DDDD;
dat[14] = 32'hE000EEEE;
dat[15] = 32'hF000FFFF;
// Initally waiting for start signal.
state <= S_WAIT_START;
// Everything else is zero.
dat_o <= 0;
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
done <= 0;
iterator <= 0;
adr_o <= 0;
start_old <= 0;
end
else begin
// Refresh the registers.
start_old <= start;
if (state == S_WAIT_START) begin
// Wait for the falling edge of the start.
if (start == 1'b0 && start_old == 1'b1) begin
// Once it has started, initiate a write.
state <= S_WRITE_INIT;
// Nothing is done yet.
done <= 0;
// Reset iterator, so that we may go through the array.
iterator <= 0;
end
end
else if (state == S_WRITE_INIT) begin
// Assert signals indicating we are ready to transfer.
cyc_o <= 1;
stb_o <= 1;
// We are writing to slave.
we_o <= 1;
// Take output data from the register array.
dat_o <= dat[iterator];
// Offset our base address by the iterator, thus placing each iteration on separate location on slave.
// Also, multiply with addressable units, so that the iterations wont overlap.
adr_o <= ( iterator * AU_IN_DATA ) + BASE_ADDRESS;
// Next we shall wait for acknowledgement.
state <= S_WAIT_WRITE_ACK;
end
else if(state == S_WAIT_WRITE_ACK) begin
if (ack_i == 1'b1) begin
// Acknowledgement received! Deassert initiator signals.
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
// Next we will read.
state <= S_READ_INIT;
end
end
else if(state == S_READ_INIT) begin
// Assert signals indicating we are ready to transfer.
cyc_o <= 1;
stb_o <= 1;
// We are reading from slave.
we_o <= 0;
// Next we shall wait for acknowledgement.
state <= S_WAIT_READ_ACK;
end
else if(state == S_WAIT_READ_ACK) begin
if (ack_i == 1'b1) begin
// Acknowledgement received! Deassert initiator signals.
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
// It was read from the same address as was written, so it should be the same data.
if (dat[iterator] != dat_i) begin
$display("ERROR: Wrong answer from slave: %X", dat_i);
$stop;
end
if (iterator == DATA_COUNT-1) begin
// We have gone through the whole register array, means we are done.
done <= 1;
// But we will wait for signal to start again.
state <= S_WAIT_START;
end
else begin
// More data to send, means we increase iterator...
iterator <= iterator + 1;
// ...and initiate next write.
state <= S_WRITE_INIT;
end
end
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, k; string s; cin >> k; vector<long long> cnt(10, 0); for (long long i = 0; i < 4; i++) { cin >> s; for (long long j = 0; s[j]; j++) { if (s[j] >= 0 && s[j] <= 9 ) cnt[s[j] - 0 ]++; } } for (long long i = 0; i < 10; i++) { if (cnt[i] > 2 * k) { cout << NO ; return; } } cout << YES ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1, n, a, b, m; while (t--) solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; b %= n; int p = ((a - 1 + b) % n + n) % (n) + 1; cout << p << endl; }
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 14.1 cbx_altiobuf_out 2014:12:03:18:04:04:SJ cbx_mgl 2014:12:03:18:06:09:SJ cbx_stratixiii 2014:12:03:18:04:04:SJ cbx_stratixv 2014:12:03:18:04:04:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 410; int cnt[N]; int temp[N]; long long cost[N][N]; long long dp[N][N]; long long n, m, k; const long long INF = (1LL) << 60; vector<int> v[200]; int main() { while (cin >> n >> m >> k) { memset(dp, 0, sizeof(dp)); for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) { cost[i][j] = INF; dp[i][j] = INF; } for (long long i = 0; i < m; i++) { long long l, r, c; cin >> l >> r >> c; cost[l - 1][r] = min(cost[l - 1][r], c); } for (long long i = 0; i <= n; i++) for (long long j = n; j >= i; j--) { cost[i][j - 1] = min(cost[i][j - 1], cost[i][j]); cost[i + 1][j] = min(cost[i + 1][j], cost[i][j]); } dp[0][0] = 0; for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= i; j++) { dp[i][j] = dp[i - 1][j]; for (long long k = 0; k < i; k++) { if (j - i + k >= 0) dp[i][j] = min(dp[i][j], dp[k][j - i + k] + cost[k][i]); } } } long long ans = INF; for (long long i = k; i <= n; i++) ans = min(ans, dp[n][i]); if (ans == INF) cout << -1 << endl; else cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); mp[a]++; } int res = n; while (!mp.empty()) { for (auto itr = mp.begin(); itr != mp.end();) { if (--itr->second == 0) mp.erase(itr++); else itr++; } res--; } printf( %d n , res); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2_1_V
`define SKY130_FD_SC_LS__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2_1_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_mask(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [17:0] tex_hmask,
input [17:0] tex_vmask,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx_f,
output reg signed [11:0] dy_f,
output reg signed [17:0] tx_m,
output reg signed [17:0] ty_m
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
dx_f <= dx;
dy_f <= dy;
tx_m <= tx & tex_hmask;
ty_m <= ty & tex_vmask;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; double EPS = 1e-9; long long INF = 1000000000000000005ll; double PI = acos(-1); inline string IntToString(long long int a) { char x[100]; sprintf(x, %lld , a); string s = x; return s; } inline long long int StringToInt(string a) { char x[100]; long long int res; strcpy(x, a.c_str()); sscanf(x, %lld , &res); return res; } inline string uppercase(string s) { int n = (int)s.size(); for (long long int i = 0; i < n; i++) if (s[i] >= a && s[i] <= z ) s[i] = s[i] - a + A ; return s; } inline string lowercase(string s) { int n = (int)s.size(); for (long long int i = 0; i < n; i++) if (s[i] >= A && s[i] <= Z ) s[i] = s[i] - A + a ; return s; } bool sortcol(const vector<long long int>& v1, const vector<long long int>& v2) { return v1[0] > v2[0]; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int n; cin >> n; long long int c[n]; string r[n]; string s[n]; for (long long int i = 0; i < n; i++) cin >> c[i]; for (long long int i = 0; i < n; i++) { cin >> r[i]; s[i] = r[i]; reverse(r[i].begin(), r[i].end()); } long long int dp[n + 1][2]; memset(dp, 0, sizeof(dp)); dp[0][1] = c[0]; for (long long int i = 1; i < n; i++) { dp[i][0] = INF; dp[i][1] = INF; if (s[i] >= s[i - 1]) { dp[i][0] = min(dp[i - 1][0], dp[i][0]); } if (s[i] >= r[i - 1]) { dp[i][0] = min(dp[i - 1][1], dp[i][0]); } if (r[i] >= s[i - 1]) { dp[i][1] = min(dp[i - 1][0] + c[i], dp[i][1]); } if (r[i] >= r[i - 1]) { dp[i][1] = min(dp[i - 1][1] + c[i], dp[i][1]); } } long long int mi = min(dp[n - 1][0], dp[n - 1][1]); if (mi != INF) cout << min(dp[n - 1][0], dp[n - 1][1]) << n ; else cout << -1 << n ; return 0; }
|
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