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module GatedLatch (
input wire enable, // Enable signal to control the latch
input wire data_in, // Input data to be stored in the latch
input wire clock, // Clock signal
output reg data_out // Output data from the latch
);
always @(posedge clock) begin
if (enable) begin
data_out <= data_in;
end
end
endmodule
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module signExt(IMM, sextIMM);
input [5:0] IMM;
output [7:0] sextIMM;
assign sextIMM[5:0] = IMM;
assign sextIMM[7:6] = IMM[5] ? 2'b11 : 2'b00;
endmodule
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2010-2013 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// SVN Information
//
// Checked In : $Date: 2013-01-09 12:55:25 +0000 (Wed, 09 Jan 2013) $
//
// Revision : $Revision: 233070 $
//
// Release Information : Cortex-M System Design Kit-r1p0-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : APB time out monitor module, used to monitor the slave's PREADY singal.
// When the PREADY signal is not active for a pre-defined cycle, the time out
// monitor will issue an error response to the master and block the access to
// the slave. The timeout monitor will unblock the slave if a ready signal is
// issued from the slave
//-----------------------------------------------------------------------------
module cmsdk_apb_timeout_mon #(
//--------------------------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------------------------
parameter ADDRWIDTH = 12, //APB slave address width
parameter TIME_OUT_VALUE = 16) //The number of cycles of wait state to triger the timeout, must be greater
// than 2 and less than 1024
(
//--------------------------------------------------------------------------------------------
// IO delcaration
//--------------------------------------------------------------------------------------------
input wire PCLK,
input wire PRESETn,
//Signals connect APB master to timeout monitor
input wire PSELS,
input wire PENABLES,
input wire [ADDRWIDTH-1:0] PADDRS,
input wire [2:0] PPROTS, //APB protect signal
input wire PWRITES,
input wire [31:0] PWDATAS,
input wire [3:0] PSTRBS, //APB byte strobe signal
output wire PREADYS, //slave ready signal
output wire PSLVERRS, //slave error siganl
//Signals connect timeout monitor to APB slave
output wire PSELM,
output wire PENABLEM,
output wire [ADDRWIDTH-1:0] PADDRM,
output wire [2:0] PPROTM, //APB protect signal
output wire PWRITEM,
output wire [31:0] PWDATAM,
output wire [3:0] PSTRBM, //APB byte strobe signal
input wire PREADYM, //slave ready signal
input wire PSLVERRM, //slave error signals
//TIMEOUT indicator
output wire TIMEOUT); //Timeout signal, indicate slave is in timeout state
//--------------------------------------------------------------------------------------------
// Local Parameters
//--------------------------------------------------------------------------------------------
localparam ARM_TIMEOUT_COUNT_WIDTH = //Timout counter width, maximum 10
(TIME_OUT_VALUE <= 16) ? 4 :
(TIME_OUT_VALUE <= 32) ? 5 :
(TIME_OUT_VALUE <= 64) ? 6 :
(TIME_OUT_VALUE <= 128) ? 7 :
(TIME_OUT_VALUE <= 256) ? 8 :
(TIME_OUT_VALUE <= 512) ? 9 : 10;
//--------------------------------------------------------------------------------------------
// Internal signals
//--------------------------------------------------------------------------------------------
//Local parameter for main control FSM
localparam ARM_TIMEOUT_WAIT_IDLE = 2'b00,
ARM_TIMEOUT_WAIT_CNT = 2'b01,
ARM_TIMEOUT_WAIT_TIMEOUT = 2'b10,
ARM_TIMEOUT_WAIT_TIMEOUT_DELAY = 2'b11;
//Locked APB transfer control signals from master to slvae
wire lock_en; //Lock enable signal, only valid for the first
// cycle when the main control FSM enter TIMEOUT state
reg locked_psels;
reg locked_penables;
reg[ADDRWIDTH-1:0] locked_paddrs;
reg[2:0] locked_pprots; //APB protect signal
reg locked_pwrites;
reg[31:0] locked_pwdatas;
reg[3:0] locked_pstrbs; //APB byte strobe signal
//Muxing control signals
wire timeout_sel_s; //timeout control signal for muxing the correct
// slave output signal to master
wire timeout_sel_m; //timeout control signal for muxing the correct
// master output signal to slave
//wait state counter FSM and counter signals
reg [1:0] timeout_fsm_state; //wait state FSM current state register
reg [1:0] timeout_fsm_state_nxt; //wait state FSM next state register
reg [ARM_TIMEOUT_COUNT_WIDTH-1:0] timeout_cnt; // wait state counter
reg [ARM_TIMEOUT_COUNT_WIDTH-1:0] nxt_timeout_cnt; // next state for wait state counter
wire[ARM_TIMEOUT_COUNT_WIDTH-1:0] timeout_cnt_inc1; // wait state counter increase 1
wire reach_timeout_thrhold; // Counter reach the timeout threshhold
wire enter_timeout; // Enter timeout state control signal
//Error response signal generated by timeout monitor
wire err_resp_ready; //Fake ready signal from timeout monitor
wire err_resp_slverr; //Fake response signal from timeout monitor
//timeout signals
wire timeout_main; //indicate main ctonrl FSM in TIMEOUT state
wire timeout_delay; //indicate main ctonrl FSM in TIMEOUT Delay state
//--------------------------------------------------------------------------------------------
// module logic start
//--------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------
// Main control FSM
//--------------------------------------------------------------------------------------------
assign reach_timeout_thrhold = (timeout_cnt== (TIME_OUT_VALUE-1))? 1'b1:1'b0;
assign enter_timeout = ((reach_timeout_thrhold)&(PREADYS==1'b0));
//Reach the time out threshhold and no ready signal
//WAIT STATE FSM, state update
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
timeout_fsm_state <= ARM_TIMEOUT_WAIT_IDLE;
else
timeout_fsm_state <= timeout_fsm_state_nxt;
end
//WAIT STATE FSM, next state generation
always @(timeout_fsm_state or PSELS or PENABLES or enter_timeout or PREADYM)
begin
case (timeout_fsm_state)
ARM_TIMEOUT_WAIT_IDLE: //Current IDLE state
begin
timeout_fsm_state_nxt = ((PSELS==1'b1) & (PENABLES==1'b0)) ?
ARM_TIMEOUT_WAIT_CNT : //If there is a active transfer request, jump to WAIT_CNT
ARM_TIMEOUT_WAIT_IDLE; //If false, stay in the IDLE state
end
ARM_TIMEOUT_WAIT_CNT: //Currrent WAIT_CNT state
begin
timeout_fsm_state_nxt = (PREADYM == 1'b1) ? ARM_TIMEOUT_WAIT_IDLE:
(enter_timeout == 1'b1)? ARM_TIMEOUT_WAIT_TIMEOUT:
ARM_TIMEOUT_WAIT_CNT;
end
ARM_TIMEOUT_WAIT_TIMEOUT: //Currrent TIMEOUT state
begin
timeout_fsm_state_nxt = (PREADYM == 1'b1)? // When slave give a reaady signal, Jump to IDLE
// state, or DELAY state,
(((PSELS==1'b1) &(PENABLES==1'b0)) ? // if APB is on its SETUP phase, jump to DELAY state
ARM_TIMEOUT_WAIT_TIMEOUT_DELAY:
ARM_TIMEOUT_WAIT_IDLE):
ARM_TIMEOUT_WAIT_TIMEOUT;
end
ARM_TIMEOUT_WAIT_TIMEOUT_DELAY: //Currrent TIMEOUT DELAY state, go to IDLE next cycle
begin
timeout_fsm_state_nxt = ARM_TIMEOUT_WAIT_IDLE;
end
default:
timeout_fsm_state_nxt = 2'bxx; //default next state
endcase
end
//--------------------------------------------------------------------------------------------
// Wait cycles counter
//--------------------------------------------------------------------------------------------
assign timeout_cnt_inc1 = timeout_cnt + 1'b1; //Increasement counter
// Generate next state for timeout_cnt
always @(timeout_fsm_state or reach_timeout_thrhold or PREADYM or timeout_cnt_inc1)
begin
if ((timeout_fsm_state == ARM_TIMEOUT_WAIT_CNT) // Counter will only be enabled in the WAIT_CNT state
& (reach_timeout_thrhold == 1'b0))
begin
if ((PREADYM==1'b1) ) // If transfer is finishing, reset counter
nxt_timeout_cnt = ({ARM_TIMEOUT_COUNT_WIDTH{1'b0}});
else // transfer is on going, increment counter
nxt_timeout_cnt = timeout_cnt_inc1;
end
else // No transfer going on
nxt_timeout_cnt = ({ARM_TIMEOUT_COUNT_WIDTH{1'b0}});
end
// Registering timeout_cnt
always @ (posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
timeout_cnt <= {ARM_TIMEOUT_COUNT_WIDTH{1'b0}};
else
timeout_cnt <= nxt_timeout_cnt;
end
//--------------------------------------------------------------------------------------------
//Faked error response from timeout monitor
//--------------------------------------------------------------------------------------------
//always response ready signal when in TIMEOUT state and a valid APB transfer occure
assign err_resp_ready = PSELS & PENABLES & TIMEOUT;
//always response error when err_resp_ready is valid
assign err_resp_slverr= err_resp_ready;
//--------------------------------------------------------------------------------------------
// Lock control signals when entering TIMEOUT state
//--------------------------------------------------------------------------------------------
//lock the APB master to slave signals when entering TIMEOUT state
assign lock_en = enter_timeout;
always @(posedge PCLK or negedge PRESETn)
begin
if (~PRESETn)
begin
locked_psels <= 1'b0;
locked_penables <= 1'b0;
locked_paddrs <= {ADDRWIDTH{1'b0}};
locked_pprots <= {3{1'b0}};
locked_pwrites <= 1'b0;
locked_pwdatas <= {32{1'b0}};
locked_pstrbs <= {4{1'b0}};
end
else if (lock_en) //Lock the current APB slave control signals
begin
locked_psels <= PSELS;
locked_penables <= PENABLES;
locked_paddrs <= PADDRS;
locked_pprots <= PPROTS;
locked_pwrites <= PWRITES;
locked_pwdatas <= PWDATAS;
locked_pstrbs <= PSTRBS;
end
end
//--------------------------------------------------------------------------------------------
// Signal select when in time out state
//--------------------------------------------------------------------------------------------
//TIMEOUT control signals
assign timeout_main = (timeout_fsm_state == ARM_TIMEOUT_WAIT_TIMEOUT) ? 1'b1:1'b0;
assign timeout_delay = (timeout_fsm_state == ARM_TIMEOUT_WAIT_TIMEOUT_DELAY) ? 1'b1:1'b0;
assign TIMEOUT = (timeout_main | timeout_delay);
//muxing control signal generation for the signals to APB slave
assign timeout_sel_s = (TIMEOUT); // when in TIMEOUT and TIMEOUT_DELAY state
//muxing control signal generation for the signals to APB master
assign timeout_sel_m = (timeout_main); // When in TIMEOUT state
//Assign signals to slave
assign PSELM = (timeout_delay==1'b1)? 1'b0:((timeout_sel_m==1'b1)?
locked_psels : PSELS);
// Force to 0 when in TIMEOUT Delay state
assign PENABLEM = (timeout_sel_m==1'b1)? locked_penables : PENABLES;
assign PADDRM = (timeout_sel_m==1'b1)? locked_paddrs : PADDRS;
assign PPROTM = (timeout_sel_m==1'b1)? locked_pprots : PPROTS;
assign PWRITEM = (timeout_sel_m==1'b1)? locked_pwrites : PWRITES;
assign PWDATAM = (timeout_sel_m==1'b1)? locked_pwdatas : PWDATAS;
assign PSTRBM = (timeout_sel_m==1'b1)? locked_pstrbs : PSTRBS;
//Assign signals to master
assign PREADYS = (timeout_sel_s==1'b1)? err_resp_ready: PREADYM;
assign PSLVERRS = (timeout_sel_s==1'b1)? err_resp_slverr: PSLVERRM;
//--------------------------------------------------------------------------------------------
// Module logic end
//--------------------------------------------------------------------------------------------
`ifdef ARM_APB_ASSERT_ON
`include "std_ovl_defines.h"
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
//Check when TIMEOUT is assert, the timeout monitor will give error response
assert_implication
#(`OVL_ERROR,
`OVL_ASSERT,
"when TIMEOUT is valid, timeout monitor shoud give error response"
)
u_ovl_apb_timeout_err_resp
(.clk (PCLK),
.reset_n (PRESETn),
.antecedent_expr ( (TIMEOUT==1'b1) & PSELS & PENABLES & PREADYS ),
.consequent_expr ( PSLVERRS==1'b1)
);
//Check when TIMEOUT is assert, if PREADYM is valid, the TIMEOUT shoudl be deasserted after 1 or 2 cycles
assert_next
#(`OVL_ERROR, 2,1,0,
`OVL_ASSERT,
"when TIMEOUT is valid, slave PREADYM signal can trigger the timeout monitor jump out timeout state after 1 or 2 cycles"
)
u_ovl_apb_timeout_deassert
(.clk (PCLK ),
.reset_n (PRESETn),
.start_event ((TIMEOUT==1'b1) & (PREADYM == 1'b1)),
.test_expr (TIMEOUT==1'b0)
);
//Internal coutner value will not greater than timeout threshhold
assert_never
#(`OVL_ERROR,
`OVL_ASSERT,
"Timeout counter exceed threshhold value!")
u_ovl_apb_timeout_cnt_exceed
(.clk (PCLK),
.reset_n (PRESETn),
.test_expr ((timeout_cnt >= TIME_OUT_VALUE))
);
// Time out configuration range check
assert_never
#(`OVL_FATAL,`OVL_ASSERT,
"Time Out configuration (TIME_OUT_VALUE) should be >2 and <=1024")
u_ovl_timeout_cfg
(.clk(PCLK), .reset_n(PRESETn),
.test_expr((TIME_OUT_VALUE>1024)|(TIME_OUT_VALUE<2))
);
`endif
endmodule
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/* =====================================================================
* DoCE Transport Layer Wrapper
*
* Author: Ran Zhao (zhaoran@ict.ac.cn)
* Date: 03/02/2017
* Version: v0.0.1
*=======================================================================
*/
`timescale 1ns / 1ps
module mac_id_table
(
input reset,
input clk,
input [3:0] trans_axis_txd_tuser,
output reg [47:0] tx_dst_mac_addr,
input [47:0] rx_dst_mac_addr,
output reg [3:0] trans_axis_rxd_tuser_i,
input [31:0] s_axi_lite_awaddr,
input s_axi_lite_awvalid,
output s_axi_lite_awready,
input [31:0] s_axi_lite_araddr,
input s_axi_lite_arvalid,
output s_axi_lite_arready,
input [31:0] s_axi_lite_wdata,
input [3:0] s_axi_lite_wstrb,
input s_axi_lite_wvalid,
output s_axi_lite_wready,
output reg [31:0] s_axi_lite_rdata,
output [1:0] s_axi_lite_rresp,
output reg s_axi_lite_rvalid,
input s_axi_lite_rready,
output [1:0] s_axi_lite_bresp,
output reg s_axi_lite_bvalid,
input s_axi_lite_bready
);
reg [31:0] mac_0_low = 32'd0;
reg [31:0] mac_0_high = 32'd0;
reg [31:0] mac_1_low = 32'd0;
reg [31:0] mac_1_high = 32'd0;
reg [31:0] mac_2_low = 32'd0;
reg [31:0] mac_2_high = 32'd0;
reg [31:0] mac_3_low = 32'd0;
reg [31:0] mac_3_high = 32'd0;
reg [47:0] ip_0 = 32'd0;
reg [47:0] ip_1 = 32'd0;
reg [47:0] ip_2 = 32'd0;
reg [47:0] ip_3 = 32'd0;
reg [3:0] mac_valid = 4'd0;
reg aw_valid = 1'b0;
reg ar_valid = 1'b0;
reg w_valid = 1'b0;
assign s_axi_lite_awready = ~(reset | aw_valid | s_axi_lite_bvalid);
assign s_axi_lite_arready = ~(reset | ar_valid | s_axi_lite_rvalid);
assign s_axi_lite_wready = ~(reset | w_valid | s_axi_lite_bvalid);
assign s_axi_lite_bresp = 2'd0;
assign s_axi_lite_rresp = 2'd0;
reg [9:0] aw_addr = 10'd0;
reg [9:0] ar_addr = 10'd0;
reg [31:0] w_data = 32'd0;
reg [3:0] w_strb = 4'd0;
always @(posedge clk)
begin
if (reset)
begin
aw_valid <= 1'b0;
ar_valid <= 1'b0;
w_valid <= 1'b0;
s_axi_lite_rvalid <= 1'b0;
s_axi_lite_bvalid <= 1'b0;
mac_0_low <= 32'd0;
mac_0_high <= 32'd0;
mac_1_low <= 32'd1;
mac_1_high <= 32'd1;
mac_2_low <= 32'd2;
mac_2_high <= 32'd2;
mac_3_low <= 32'd3;
mac_3_high <= 32'd3;
ip_0 <= 32'd0;
ip_1 <= 32'd1;
ip_2 <= 32'd2;
ip_3 <= 32'd3;
mac_valid <= 4'd0;
end
else
begin
if (s_axi_lite_awready & s_axi_lite_awvalid)
begin
aw_addr <= s_axi_lite_awaddr[9:0];
aw_valid <= 1'b1;
end
if (s_axi_lite_arready & s_axi_lite_arvalid)
begin
ar_addr <= s_axi_lite_araddr[9:0];
ar_valid <= 1'b1;
end
if (s_axi_lite_wready & s_axi_lite_wvalid)
begin
w_data <= s_axi_lite_wdata;
w_strb <= s_axi_lite_wstrb;
w_valid <= 1'b1;
end
if (s_axi_lite_bvalid & s_axi_lite_bready)
s_axi_lite_bvalid <= 1'b0;
if (aw_valid & w_valid & (~s_axi_lite_bvalid))
begin
aw_valid <= 1'b0;
w_valid <= 1'b0;
s_axi_lite_bvalid <= 1'b1;
if (aw_addr == 10'h200)
mac_0_low <= (mac_0_low & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h204)
mac_0_high <= (mac_0_high & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h208)
mac_1_low <= (mac_1_low & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h20C)
mac_1_high <= (mac_1_high & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h210)
mac_2_low <= (mac_2_low & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h214)
mac_2_high <= (mac_2_high & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h218)
mac_3_low <= (mac_3_low & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h21C)
mac_3_high <= (mac_3_high & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h220)
ip_0 <= (ip_0 & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h224)
ip_1 <= (ip_1 & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h228)
ip_2 <= (ip_2 & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h22C)
ip_3 <= (ip_3 & {{8{~w_strb[3]}},{8{~w_strb[2]}},{8{~w_strb[1]}},{8{~w_strb[0]}}}) | (w_data & {{8{w_strb[3]}},{8{w_strb[2]}},{8{w_strb[1]}},{8{w_strb[0]}}});
else if (aw_addr == 10'h230)
mac_valid <= (mac_valid & {4{~w_strb[0]}}) | (w_data[3:0] & {4{w_strb[0]}});
end
if (s_axi_lite_rvalid & s_axi_lite_rready)
s_axi_lite_rvalid <= 1'b0;
if (ar_valid & (~s_axi_lite_rvalid))
begin
ar_valid <= 1'b0;
s_axi_lite_rvalid <= 1'b1;
if (ar_addr == 10'h200)
s_axi_lite_rdata <= mac_0_low;
else if (ar_addr == 10'h204)
s_axi_lite_rdata <= mac_0_high;
else if (ar_addr == 10'h208)
s_axi_lite_rdata <= mac_1_low;
else if (ar_addr == 10'h20C)
s_axi_lite_rdata <= mac_1_high;
else if (ar_addr == 10'h210)
s_axi_lite_rdata <= mac_2_low;
else if (ar_addr == 10'h214)
s_axi_lite_rdata <= mac_2_high;
else if (ar_addr == 10'h218)
s_axi_lite_rdata <= mac_3_low;
else if (ar_addr == 10'h21C)
s_axi_lite_rdata <= mac_3_high;
else if (ar_addr == 10'h220)
s_axi_lite_rdata <= ip_0;
else if (ar_addr == 10'h224)
s_axi_lite_rdata <= ip_1;
else if (ar_addr == 10'h228)
s_axi_lite_rdata <= ip_2;
else if (ar_addr == 10'h22C)
s_axi_lite_rdata <= ip_3;
else if (ar_addr == 10'h230)
s_axi_lite_rdata <= {{28{1'b0}}, mac_valid};
else
s_axi_lite_rdata <= 32'b0;
end
end
end
always @(posedge clk)
begin
if (reset)
begin
tx_dst_mac_addr <= 48'd0;
end
else
begin
case(trans_axis_txd_tuser)
4'd0: tx_dst_mac_addr <= mac_valid[0] ? ({mac_0_high[15:0], mac_0_low}) : 48'hffffffff;
4'd1: tx_dst_mac_addr <= mac_valid[1] ? ({mac_1_high[15:0], mac_1_low}) : 48'hffffffff;
4'd2: tx_dst_mac_addr <= mac_valid[2] ? ({mac_2_high[15:0], mac_2_low}) : 48'hffffffff;
4'd3: tx_dst_mac_addr <= mac_valid[3] ? ({mac_3_high[15:0], mac_3_low}) : 48'hffffffff;
default: tx_dst_mac_addr <= 48'd0;
endcase
end
end
wire [3:0] trans_axis_rxd_tuser;
assign trans_axis_rxd_tuser[0] = ~|({mac_0_high[15:0], mac_0_low} ^ rx_dst_mac_addr);
assign trans_axis_rxd_tuser[1] = ~|({mac_1_high[15:0], mac_1_low} ^ rx_dst_mac_addr);
assign trans_axis_rxd_tuser[2] = ~|({mac_2_high[15:0], mac_2_low} ^ rx_dst_mac_addr);
assign trans_axis_rxd_tuser[3] = ~|({mac_3_high[15:0], mac_3_low} ^ rx_dst_mac_addr);
always @(posedge clk)
begin
if (reset)
begin
trans_axis_rxd_tuser_i <= 4'd0;
end
else
begin
case(trans_axis_rxd_tuser)
4'd1: trans_axis_rxd_tuser_i <= 4'd0;
4'd2: trans_axis_rxd_tuser_i <= 4'd1;
4'd4: trans_axis_rxd_tuser_i <= 4'd2;
4'd8: trans_axis_rxd_tuser_i <= 4'd3;
default: trans_axis_rxd_tuser_i <= 4'd4;
endcase
end
end
endmodule
|
|
module seg7 (clk_1k,rst_n,data_in,sel,seg);
input clk_1k; // Clock
input rst_n; // Asynchronous reset active low
input [23:0] data_in;
// reg [23:0] data_in = 24'b0000_0001_0010_0011_0100_0101;
//parameter [23:0] data_in = 24'b0000_0001_0010_0011_0100_0101;
output reg [7:0] seg;
output reg [2:0] sel;
reg [3:0] temp;
// reg [23:0] data_in_temmp;
always @(posedge clk_1k or negedge rst_n)
begin
if(~rst_n)
begin
// data_in_temmp <= data_in;
// // seg <= 8'd0;
sel <= 3'd0;
end
else
begin
if(sel < 5)
begin
sel <= sel + 1;
end
else
begin
sel <= 0;
end
end
end
always @ (*)
begin
if(~rst_n)
begin
temp <= 0;
end
else
begin
case(sel)
0 : temp = data_in[23:20];
1 : temp = data_in[19:16];
2 : temp = data_in[15:12];
3 : temp = data_in[11:8];
4 : temp = data_in[7:4];
5 : temp = data_in[3:0];
default : temp = data_in[23:20];
endcase
end
end
// always @( posedge clk_1k ) //segtempsel
always @(*)
begin : proc_2
begin
case(temp)
4'd0 : seg = 8'b1000_1001;//h
4'd1 : seg = 8'b10000110;//e
4'd2 : seg = 8'b1100_0111;//l
4'd3 : seg = 8'b1100_0111;//l
4'd4 : seg = 8'b1100_0000;//o
4'd5 : seg = 8'b1111_1111;//
// 4'd0 : seg = 8'b1100_0000;
// 4'd1 : seg = 8'b11111001; //1
// 4'd2 : seg = 8'b10100100; //2
// 4'd3 : seg = 8'b10110000; //3
// 4'd4 : seg = 8'b10011001; //4
// 4'd5 : seg = 8'b10010010; //5
// 4'd6 : seg = 8'b10000010; //6
// 4'd7 : seg = 8'b11111000; //7
// 4'd8 : seg = 8'b10000000; //8
// 4'd9 : seg = 8'b10010000; //9
// 4'd10 : seg = 8'b10001000; //a
// 4'd11 : seg = 8'b10000011; //b
// 4'd12 : seg = 8'b10000110; //c
// 4'd13 : seg = 8'b10100001; //d
// 4'd14 : seg = 8'b10000110; //e
// 4'd15 : seg = 8'b10001110; //f
endcase
end
end
//
// always @(posedge clk_1k)
// begin
// if(~rst_n)
// begin
// data_in_temmp <= data_in;
// temp <= data_in[23:20];
// end
// else
// begin
// if(sel == 0)
// begin
// data_in_temmp <= data_in;
// // temp <= 4'd0;
// temp <= data_in_temmp[23:20]
// end
// else
// begin
// data_in_temmp <= {data_in_temmp[3:0],data_in_temmp[23:4]};
// temp <= data_in_temmp[23:20];
// end
// end
// end
// always @(posedge clk_1k or negedge rst_n)
// begin : proc_1
// if(~rst_n)
// begin
// data_in_temmp <= data_in;
// // seg <= 8'd0;
// sel <= 3'd0;
// end
// else
// begin
// data_in_temmp <= {data_in_temmp[3:0],data_in_temmp[23:20]};
// temp <= data_in_temmp[23:20];
// if(sel < 5)
// begin
// // data_in_temmp <= {data_in_temmp[3:0],data_in_temmp[23:20]};
// // temp <= data_in_temmp[23:20];
// sel <= sel +1;
// // case(temp)
// // 4'd0 : seg <= 8'b1100_0000;
// // 4'd1 : seg <= 8'b11111001; //1
// // 4'd2 : seg <= 8'b10100100; //2
// // 4'd3 : seg <= 8'b10110000; //3
// // 4'd4 : seg <= 8'b10011001; //4
// // 4'd5 : seg <= 8'b10010010; //5
// // 4'd6 : seg <= 8'b10000010; //6
// // 4'd7 : seg <= 8'b11111000; //7
// // 4'd8 : seg <= 8'b10000000; //8
// // 4'd9 : seg <= 8'b10010000; //9
// // 4'd10 : seg <= 8'b10001000; //a
// // 4'd11 : seg <= 8'b10000011; //b
// // 4'd12 : seg <= 8'b10000110; //c
// // 4'd13 : seg <= 8'b10100001; //d
// // 4'd14 : seg <= 8'b10000110; //e
// // 4'd15 : seg <= 8'b10001110; //f
// // endcase
// end
// else
// begin
// // data_in_temmp <= data_in;
// // temp <= data_in_temmp[23:20];
// sel <= 0;
// // case(temp)
// // 4'd0 : seg <= 8'b1100_0000;
// // 4'd1 : seg <= 8'b11111001; //1
// // 4'd2 : seg <= 8'b10100100; //2
// // 4'd3 : seg <= 8'b10110000; //3
// // 4'd4 : seg <= 8'b10011001; //4
// // 4'd5 : seg <= 8'b10010010; //5
// // 4'd6 : seg <= 8'b10000010; //6
// // 4'd7 : seg <= 8'b11111000; //7
// // 4'd8 : seg <= 8'b10000000; //8
// // 4'd9 : seg <= 8'b10010000; //9
// // 4'd10 : seg <= 8'b10001000; //a
// // 4'd11 : seg <= 8'b10000011; //b
// // 4'd12 : seg <= 8'b10000110; //c
// // 4'd13 : seg <= 8'b10100001; //d
// // 4'd14 : seg <= 8'b10000110; //e
// // 4'd15 : seg <= 8'b10001110; //f
// // endcase
// end
// /* code */
// // case (sel)
// // 3'd0: begin
// // temp <= data_in[23:20];
// // sel <= sel+1;
// // end
// // 3'd1: begin
// // temp <= data_in[19:16];
// // sel <= sel+1;
// // end
// // 3'd2: begin
// // temp <= data_in[15:12];
// // sel <= sel+1;
// // end
// // 3'd3: begin
// // temp <= data_in[11:8];
// // sel <= sel+1;
// // end
// // 3'd4: begin
// // temp <= data_in[7:4];
// // sel <= sel+1;
// // end
// // 3'd5: begin
// // temp <= data_in[3:0];
// // sel <= 3'd0;
// // end
// // default
// // begin
// // temp <= data_in[23:20];
// // sel <= 3'd0;
// // end
// // endcase
// end
// end //proc_1
endmodule
|
|
`timescale 1ns / 1ps
module Mux2(input wire a,input wire b,input wire sel,output wire out);
wire temp[1:0];
and( temp[1] , a , sel );
and( temp[0] , b , ~sel );
or( out , temp[1] , temp[0] );
endmodule
module Mux4(input wire [3:0] a,input wire [1:0] sel,output wire out);
wire temp[1:0];
Mux2 m1 (a[3],a[2],sel[0],temp[1]);
Mux2 m2 (a[1],a[0],sel[0],temp[0]);
Mux2 m3 (temp[1],temp[0],sel[1],out);
endmodule
module Mux8(input wire [7:0] a,input wire [2:0] sel,output wire out);
wire temp[1:0];
Mux4 m1 (a[7:4],sel[1:0],temp[1]);
Mux4 m2 (a[3:0],sel[1:0],temp[0]);
Mux2 m3 (temp[1],temp[0],sel[2],out);
endmodule
|
|
module sdram_write(
// system signals
input sclk ,
input s_rst_n ,
// Communicate with TOP
input wr_en ,
output wire wr_req ,
output reg flag_wr_end ,
// Others
input ref_req ,
input wr_trig ,
// write interfaces
output reg [ 3:0] wr_cmd ,
output reg [11:0] wr_addr ,
output wire [ 1:0] bank_addr ,
output wire [15:0] wr_data ,
// WFIFO Interfaces
output wire wfifo_rd_en ,
input [ 7:0] wfifo_rd_data
);
//===================================================================\\
// ********* Define Parameter and Internal Signals *********
//===================================================================/
// Define State
localparam S_IDLE = 5'b0_0001 ;
localparam S_REQ = 5'b0_0010 ;
localparam S_ACT = 5'b0_0100 ;
localparam S_WR = 5'b0_1000 ;
localparam S_PRE = 5'b1_0000 ;
// SDRAM Command
localparam CMD_NOP = 4'b0111 ;
localparam CMD_PRE = 4'b0010 ;
localparam CMD_AREF = 4'b0001 ;
localparam CMD_ACT = 4'b0011 ;
localparam CMD_WR = 4'b0100 ;
reg flag_wr ;
reg [ 4:0] state ;
//-----------------------------------------------------------------
reg flag_act_end ;
reg flag_pre_end ;
reg sd_row_end ;
reg [ 1:0] burst_cnt ;
reg [ 1:0] burst_cnt_t ;
reg wr_data_end ;
//-----------------------------------------------------------------
reg [ 3:0] act_cnt ;
reg [ 3:0] break_cnt ;
reg [ 6:0] col_cnt ;
//-----------------------------------------------------------------
reg [11:0] row_addr ;
wire [ 8:0] col_addr ;
//==========================================================================
// **************** Main Code **************
//==========================================================================
//flag_wr
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
flag_wr <= 1'b0;
else if(wr_trig == 1'b1 && flag_wr == 1'b0)
flag_wr <= 1'b1;
else if(wr_data_end == 1'b1)
flag_wr <= 1'b0;
end
// burst_cnt
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
burst_cnt <= 'd0;
else if(state == S_WR)
burst_cnt <= burst_cnt + 1'b1;
else
burst_cnt <= 'd0;
end
// burst_cnt_t
always @(posedge sclk) begin
burst_cnt_t <= burst_cnt;
end
//------------------------- STATE ------------------------------------------
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
state <= S_IDLE;
else case(state)
S_IDLE:
if(wr_trig == 1'b1)
state <= S_REQ;
else
state <= S_IDLE;
S_REQ:
if(wr_en == 1'b1)
state <= S_ACT;
else
state <= S_REQ;
S_ACT:
if(flag_act_end == 1'b1)
state <= S_WR;
else
state <= S_ACT;
S_WR:
if(wr_data_end == 1'b1)
state <= S_PRE;
else if(ref_req == 1'b1 && burst_cnt_t == 'd2 && flag_wr == 1'b1)
state <= S_PRE;
else if(sd_row_end == 1'b1 && flag_wr == 1'b1)
state <= S_PRE;
S_PRE:
if(ref_req == 1'b1 && flag_wr == 1'b1)
state <= S_REQ;
else if(flag_pre_end == 1'b1 && flag_wr == 1'b1)
state <= S_ACT;
else if(flag_wr == 1'b0)
state <= S_IDLE;
default:
state <= S_IDLE;
endcase
end
// wr_cmd
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
wr_cmd <= CMD_NOP;
else case(state)
S_ACT:
if(act_cnt == 'd0)
wr_cmd <= CMD_ACT;
else
wr_cmd <= CMD_NOP;
S_WR:
if(burst_cnt == 'd0)
wr_cmd <= CMD_WR;
else
wr_cmd <= CMD_NOP;
S_PRE:
if(break_cnt == 'd0)
wr_cmd <= CMD_PRE;
else
wr_cmd <= CMD_NOP;
default:
wr_cmd <= CMD_NOP;
endcase
end
// wr_addr
always @(*) begin
case(state)
S_ACT:
if(act_cnt == 'd0)
wr_addr <= row_addr;
else
wr_addr <= 'd0;
S_WR: wr_addr <= {3'b000, col_addr};
S_PRE: if(break_cnt == 'd0)
wr_addr <= {12'b0100_0000_0000};
else
wr_addr <= 'd0;
default:
wr_addr <= 'd0;
endcase
end
//-------------------------------------------------------------------
// flag_act_end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
flag_act_end <= 1'b0;
else if(act_cnt == 'd3)
flag_act_end <= 1'b1;
else
flag_act_end <= 1'b0;
end
// act_cnt
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
act_cnt <= 'd0;
else if(state == S_ACT)
act_cnt <= act_cnt + 1'b1;
else
act_cnt <= 'd0;
end
// flag_pre_end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
flag_pre_end <= 1'b0;
else if(break_cnt == 'd3)
flag_pre_end <= 1'b1;
else
flag_pre_end <= 1'b0;
end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
flag_wr_end <= 1'b0;
else if((state == S_PRE && ref_req == 1'b1) || //refresh
state == S_PRE && flag_wr == 1'b0)
flag_wr_end <= 1'b1;
else
flag_wr_end <= 1'b0;
end
// break_cnt
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
break_cnt <= 'd0;
else if(state == S_PRE)
break_cnt <= break_cnt + 1'b1;
else
break_cnt <= 'd0;
end
// wr_data_end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
wr_data_end <= 1'b0;
else if(row_addr == 'd0 && col_addr == 'd1)
wr_data_end <= 1'b1;
else
wr_data_end <= 1'b0;
end
// col_cnt
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
col_cnt <= 'd0;
else if(col_addr == 'd511)
col_cnt <= 'd0;
else if(burst_cnt_t == 'd3)
col_cnt <= col_cnt + 1'b1;
end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
row_addr <= 'd0;
else if(sd_row_end == 1'b1)
row_addr <= row_addr + 1'b1;
end
always @(posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
sd_row_end <= 1'b0;
else if(col_addr == 'd509)
sd_row_end <= 1'b1;
else
sd_row_end <= 1'b0;
end
//----------------------------------------------------------------
/* always @(*) begin
case(burst_cnt_t)
0: wr_data <= 'd3;
1: wr_data <= 'd5;
2: wr_data <= 'd7;
3: wr_data <= 'd9;
endcase
end */
//----------------------------------------------------------------
//assign col_addr = {col_cnt, burst_cnt_t};
assign col_addr = {7'd0, burst_cnt_t};
assign bank_addr = 2'b00;
assign wr_req = state[1];
assign wfifo_rd_en = state[3];
assign wr_data = wfifo_rd_data;
endmodule
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:46:06 06/12/2019
// Design Name:
// Module Name: Timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Timer(
input [3:0] Value,
input oneHz_enable,
input start_timer,
input clk,
input Reset_Sync,
output reg expired
);
reg [3:0] time_left;
reg change =1; // Since Value is set by the time parameter module Value should be assinged to time_left after a one clock cycle
always@(posedge clk) begin
if (!change) begin
change = 1;
time_left = Value-1;
end
if (Reset_Sync)begin
change = 0;
end
if (start_timer) begin
change =0;
end
expired = 0;
if (oneHz_enable) begin
if (!time_left) begin
expired = 1;
end
else begin
time_left = time_left - 1;
end
end
end
endmodule
|
|
module iiitb_pwm_gen
(
clk, // 100MHz clock input
increase_duty, // input to increase 10% duty cycle
decrease_duty, // input to decrease 10% duty cycle
reset,
PWM_OUT // 10MHz PWM output signal
);
input clk,reset;
input increase_duty;
input decrease_duty;
output PWM_OUT;
wire slow_clk_enable; // slow clock enable signal for debouncing FFs(40MHz)
reg[27:0] counter_debounce;// counter for creating slow clock enable signals
reg tmp1,tmp2;// temporary flip-flop signals for debouncing the increasing button
reg tmp3,tmp4;// temporary flip-flop signals for debouncing the decreasing button
wire duty_inc, duty_dec;
reg[3:0] counter_PWM;
reg[3:0] DUTY_CYCLE;
// Debouncing 2 buttons for inc/dec duty cycle
// Firstly generate slow clock enable for debouncing flip-flop
always @(posedge clk or posedge reset)
begin
if(reset) begin
counter_debounce<=28'd0;
counter_PWM<=4'd0;// counter for creating 10Mhz PWM signal
DUTY_CYCLE<=4'd5;// initial duty cycle is 50%
tmp1 <= 0;
tmp2 <= 0;
tmp3<=0;
tmp4<=0;
end
else begin
counter_debounce <= counter_debounce>=28'd1 ? 28'd0 : counter_debounce + 28'd1;
if(duty_inc==1 && DUTY_CYCLE <= 9) begin
DUTY_CYCLE <= DUTY_CYCLE + 4'd1;// increase duty cycle by 10%
end
else if(duty_dec==1 && DUTY_CYCLE>=1) begin
//else begin
DUTY_CYCLE <= DUTY_CYCLE - 4'd1;
end//decrease duty cycle by 10%
counter_PWM <= counter_PWM + 4'd1;
if(counter_PWM>=9) begin
counter_PWM <= 0;
end
if(slow_clk_enable==1) begin// slow clock enable signal
tmp1 <= increase_duty;
tmp2 <= tmp1;
tmp3 <= decrease_duty;
tmp4 <= tmp3;
end
end
end
assign slow_clk_enable = counter_debounce == 1 ?1:0;
assign duty_inc = tmp1 & (~ tmp2) & slow_clk_enable;
assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable;
assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
endmodule
|
|
// ---------------------
// Guia 05 - Exercicio 02
// Nome: Bruno Csar Lopes Silva
// Matricula: 415985
// ---------------------
//--- Module Meia Diferena---
module meiadiferenca (s, s1, p, q);
output s, s1;
input p, q;
xor XOR1(s, p, q);
not NOT1(s2, p);
and AND1(s1, s2, q);
endmodule // meiadiferenca
module diferencacompleta (s, s1, p, q, vemum);
output s, s1;
input p, q, vemum;
wire s2, s3, s4;
meiadiferenca M1(s2, s3, p, q);
meiadiferenca M2(s, s4, s2, vemum);
or OR1(s1, s3, s4);
endmodule // diferencacompleta
//--- Module Teste ---
module testediferenca4bits;
reg [2:0]A;
reg [2:0]B;
wire [3:0]S;
wire [1:0]W;
meiadiferenca M1(S[0], W[0], A[0], B[0]);
diferencacompleta S1(S[1], W[1], A[1], B[1], W[0]);
diferencacompleta S2(S[2], S[3], A[2], B[2], W[1]);
// parte principal
initial begin
$display("Guia 05 - Exercicio 01");
$display("Bruno Cesar Lopes Silva - 415985");
$display("Diferenca Completa com 3 bits");
$display("\\n a - b = s \\n");
A = 0;
B = 0;
while(A != 7)
begin
A = (B == 0)? A : A + 1;
B = 0;
#1 $display("%b - %b = %b", A, B, S);
while(B != 7)
begin
B = B + 1;
#1 $display("%b - %b = %b", A, B, S);
end
end
end
endmodule // testediferenca4bits
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/11/2023 06:16:24 PM
// Design Name:
// Module Name: sp_sram
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sp_sram
# (
parameter WIDTH = 10,
parameter DEPTH = 128,
parameter ADDRB = $clog2(DEPTH)
)
(
input i_clk,
input ena,
input wea,
input rea,
input [ADDRB-1:0] addr_i,
input [ADDRB-1:0] addr_o,
input [WIDTH-1:0] dina_0,
input [WIDTH-1:0] dina_1,
input [WIDTH-1:0] dina_2,
input [WIDTH-1:0] dina_3,
output reg [WIDTH-1:0] douta
);
//===============================================================================
// REGISTER/WIRE
//===============================================================================
reg [WIDTH-1:0] mem [DEPTH-1:0];
//===============================================================================
// MODULE BODY
//===============================================================================
always @ (posedge i_clk)
begin
// if (ena & rea)
begin
if (addr_o < DEPTH) begin
douta <= mem[addr_o-1];
end
end
end
always @ (posedge i_clk)
begin
if (ena & wea) begin
if (addr_i < DEPTH) begin
mem[addr_i] <= dina_0;
mem[addr_i+1] <= dina_1;
mem[addr_i+2] <= dina_2;
mem[addr_i+3] <= dina_3;
end
end
end
endmodule
|
|
`define EXPONENT 5
`define MANTISSA 10
`define ACTUAL_MANTISSA 11
`define EXPONENT_LSB 10
`define EXPONENT_MSB 14
`define MANTISSA_LSB 0
`define MANTISSA_MSB 9
`define MANTISSA_MUL_SPLIT_LSB 3
`define MANTISSA_MUL_SPLIT_MSB 9
`define SIGN 1
`define SIGN_LOC 15
`define DWIDTH (`SIGN+`EXPONENT+`MANTISSA)
`define IEEE_COMPLIANCE 1
module td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0
#(parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 5,
BufferCount = 2,
MemLatency = 1,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [DataWidth-1:0] i_d0,
output wire [DataWidth-1:0] i_q0,
input wire i_ce1,
input wire i_we1,
input wire [AddressWidth-1:0] i_address1,
input wire [DataWidth-1:0] i_d1,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [DataWidth-1:0] t_d0,
output wire [DataWidth-1:0] t_q0,
input wire t_ce1,
input wire t_we1,
input wire [AddressWidth-1:0] t_address1,
input wire [DataWidth-1:0] t_d1
);
//------------------------Local signal-------------------
// control/status
reg [IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [IndexWidth-1:0] tptr = 1'b0; // target index
reg [IndexWidth-1:0] prev_iptr = 1'b0; // previous initiator index
reg [IndexWidth-1:0] prev_tptr = 1'b0; // previous target index
reg [DataWidth-1:0] reg_q0 = 1'b0; // buffer used if reader is stalled
reg reg_valid0 = 1'b0; // buffer has valid data
reg [DataWidth-1:0] reg_q1 = 1'b0; // buffer used if reader is stalled
reg reg_valid1 = 1'b0; // buffer has valid data
reg [IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
// buffer signals
wire [BufferCount-1:0] buf_ce0;
wire [BufferCount-1:0] buf_we0;
wire [AddressWidth-1:0] buf_a0_0, buf_a0_1;
wire [DataWidth-1:0] buf_d0_0, buf_d0_1;
wire [DataWidth-1:0] buf_q0_0, buf_q0_1;
wire [BufferCount-1:0] buf_ce1;
wire [BufferCount-1:0] buf_we1;
wire [AddressWidth-1:0] buf_a1_0, buf_a1_1;
wire [DataWidth-1:0] buf_d1_0, buf_d1_1;
//------------------------Instantiation------------------
//genvar i;
td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore_U_0 (
.reset ( reset ),
.clk ( clk ),
.address0 ( buf_a0_0 ),
.ce0 ( buf_ce0[ 0 ] ),
.we0 ( buf_we0[ 0 ] ),
.d0 ( buf_d0_0 ),
.q0 ( buf_q0_0 ),
.address1 ( buf_a1_0 ),
.ce1 ( buf_ce1[ 0 ] ),
.we1 ( buf_we1[ 0 ] ),
.d1 ( buf_d1_0 )
);
td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore_U_1 (
.reset ( reset ),
.clk ( clk ),
.address0 ( buf_a0_1 ),
.ce0 ( buf_ce0[ 1 ] ),
.we0 ( buf_we0[ 1 ] ),
.d0 ( buf_d0_1 ),
.q0 ( buf_q0_1 ),
.address1 ( buf_a1_1 ),
.ce1 ( buf_ce1[ 1 ] ),
.we1 ( buf_we1[ 1 ] ),
.d1 ( buf_d1_1 )
);
//++++++++++++++++++++++++buffer signals+++++++++++++++++
assign buf_ce0[ 0 ] = (tptr == 0 && empty_n) ? t_ce0
: (iptr == 0 ) ? i_ce0 : 1'b0;
assign buf_a0_0 = (tptr == 0 && empty_n) ? t_address0 : i_address0;
assign buf_we0[ 0 ] = (tptr == 0 && empty_n) ? t_we0
: (iptr == 0 ) ? i_we0 : 1'b0;
assign buf_d0_0 = (tptr == 0 && empty_n) ? t_d0 : i_d0;
assign buf_ce1[ 0 ] = (tptr == 0 && empty_n) ? t_ce1
: (iptr == 0 ) ? i_ce1 : 1'b0;
assign buf_a1_0 = (tptr == 0 && empty_n) ? t_address1 : i_address1;
assign buf_we1[ 0 ] = (tptr == 0 && empty_n) ? t_we1
: (iptr == 0 ) ? i_we1 : 1'b0;
assign buf_d1_0 = (tptr == 0 && empty_n) ? t_d1 : i_d1;
assign buf_ce0[ 1 ] = (tptr == 1 && empty_n) ? t_ce0
: (iptr == 1 ) ? i_ce0 : 1'b0;
assign buf_a0_1 = (tptr == 1 && empty_n) ? t_address0 : i_address0;
assign buf_we0[ 1 ] = (tptr == 1 && empty_n) ? t_we0
: (iptr == 1 ) ? i_we0 : 1'b0;
assign buf_d0_1 = (tptr == 1 && empty_n) ? t_d0 : i_d0;
assign buf_ce1[ 1 ] = (tptr == 1 && empty_n) ? t_ce1
: (iptr == 1 ) ? i_ce1 : 1'b0;
assign buf_a1_1 = (tptr == 1 && empty_n) ? t_address1 : i_address1;
assign buf_we1[ 1 ] = (tptr == 1 && empty_n) ? t_we1
: (iptr == 1 ) ? i_we1 : 1'b0;
assign buf_d1_1 = (tptr == 1 && empty_n) ? t_d1 : i_d1;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//------------------------Body---------------------------
assign i_q0 = (prev_iptr == 1'b1 ? buf_q0_1 : buf_q0_0);
assign t_q0 = reg_valid0 ? reg_q0 : (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0);
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1)
iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1)
iptr <= 1'b0;
else
iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1)
tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1)
tptr <= 1'b0;
else
tptr <= tptr + 1'b1;
end
end
// prev_iptr
always @(posedge clk) begin
if (reset == 1'b1)
prev_iptr <= 1'b0;
else begin
prev_iptr <= iptr;
end
end
// prev_tptr
always @(posedge clk) begin
if (reset == 1'b1)
prev_tptr <= 1'b0;
else begin
prev_tptr <= tptr;
end
end
// reg_q0 and reg_valid0
always @(posedge clk) begin
if (reset == 1'b1) begin
reg_q0 <= 1'b0;
reg_valid0 <= 1'b0;
end else if (!t_ce0 && !reg_valid0) begin
reg_q0 <= (prev_tptr == 1'b1 ? buf_q0_1 : buf_q0_0);
reg_valid0 <= 1'b1;
end else if (t_ce0) begin
reg_valid0 <= 1'b0;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1)
count <= 1'b0;
else if (push_buf && !pop_buf)
count <= count + 1'b1;
else if (!push_buf && pop_buf)
count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1)
full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2)
full_n <= 1'b0;
else if (!push_buf && pop_buf)
full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1)
empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1)
|| (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf)
empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
module td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.we0( we0 ),
.d0( d0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.we1( we1 ),
.d1( d1 )
);
endmodule
module td_fused_top_dataflow_in_loop_TOP_LOOP48628_ifmap_vec_0_0_memcore_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0) begin
if (we0)
ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1) begin
if (we1)
ram[addr1] <= d1;
end
end
endmodule
|
|
module control(opCode, RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUsrc, RegWrite);
input [5:0] opCode;
output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, RegWrite, ALUsrc;
assign RegDst = (opCode == 6'h0);
assign Jump = (opCode == 6'h2);
assign Branch = (opCode == 6'h4);
assign MemRead = (opCode == 6'h23);
assign MemtoReg = (opCode == 6'h23);
assign ALUsrc = (opCode == 6'h8 || opCode == 6'h23 || opCode == 6'h2b);
assign RegWrite = (opCode == 6'h0 || opCode == 6'h8 || opCode == 6'h23);
assign MemWrite = (opCode == 6'h2b);
endmodule
|
|
module figure2_42(x1, x2, s, f);
input x1, x2, s;
output f;
reg f;
always @(x1 or x2 or s)
if (s==0)
f = x1;
else
f = x2;
endmodule
|
|
/* ----------------------------------------------------------------------------
Projeto: modulo conversor Float 32 - 16
UFABC - universidade Federal do ABC
Verso: 1.0 Data: 02.10.2017
Prog: Carolina Zambelli
Descrio: converte um fp single precision (32bits) para um half precision
(16bits)
-----------------------------------------------------------------------------*/
module Conv_F32_F16
(
input [31:0] Fin,
output [15:0] Fout
);
reg [4:0] Exp_tmp;
reg [9:0] Man_tmp;
always @(Fin)
begin
if (Fin[30:23]>8'd142) // se exp32 > 142, mostra infinity F16
begin
Exp_tmp = 5'b11111; // exp = max (rep +- INF)
Man_tmp = 10'b0000000000; // mant = 0
end
else if ((Fin[30:23]==8'd0) && (Fin[22:0]==23'd0)) // caso ZERO
begin
Exp_tmp = 5'b00000; // exp16 sai 00000
Man_tmp = 10'b0000000000; // mant = 0,0000000000
end
// normal: se 2^-14 <= exp32 <2^15 (ou seja, 103 <= exp32 <= 142)
else if (Fin[30:23]>=8'd113) // se 113 <= exp32 <= 142 normal F16
begin
Exp_tmp = Fin[30:23] - 8'd112; // subtrair exp32 - 112!
Man_tmp = Fin[22:13]; // mant = Fin[22:13]
end
// subnormal: se 2^-24 <= exp32 <2^-15 (ou seja, 103 <= exp32 <= 112)
else if (Fin[30:23]>=8'd103) // se >103 e mant!=0
begin
Exp_tmp = 5'b00000; // exp16 sai 00000
// para cada exp < 2^-14, deslocar a mantissa
if (Fin[30:23]==8'd112 && (9'b0|Fin[22:14]))
begin
Man_tmp = {1'b1,Fin[22:14]}; // mant = Fin[22:14]
end
else if (Fin[30:23]==8'd112 && ~(9'b0|Fin[22:14]))
begin
Man_tmp = {1'b1,9'b0}; // mant = 0,1000000000
end
else if (Fin[30:23]==8'd111 && (8'b0|Fin[22:15]))
begin
Man_tmp = {2'b01,Fin[22:15]}; // mant = Fin[22:15]
end
else if (Fin[30:23]==8'd111 && ~(8'b0|Fin[22:15]))
begin
Man_tmp = {2'b01,8'b0}; // mant = 0,01000000
end
else if (Fin[30:23]==8'd110 && (7'b0|Fin[22:16]))
begin
Man_tmp = {3'b001,Fin[22:16]}; // mant = Fin[22:16]
end
else if (Fin[30:23]==8'd110 && ~(7'b0|Fin[22:16]))
begin
Man_tmp = {3'b001,7'b0}; // mant = 0,0010000000
end
else if (Fin[30:23]==8'd109 && (6'b0|Fin[22:17]))
begin
Man_tmp = {4'b0001,Fin[22:17]}; // mant = Fin[22:17]
end
else if (Fin[30:23]==8'd109 && ~(6'b0|Fin[22:17]))
begin
Man_tmp = {4'b0001,6'b0}; // mant = 0,0001000000
end
else if (Fin[30:23]==8'd108 && (5'b0|Fin[22:18]))
begin
Man_tmp = {5'b00001,Fin[22:18]}; // mant = Fin[22:18]
end
else if (Fin[30:23]==8'd108 && ~(5'b0|Fin[22:18]))
begin
Man_tmp = {5'b00001,5'b0}; // mant = 0,0000100000
end
else if (Fin[30:23]==8'd107 && (4'b0|Fin[22:19]))
begin
Man_tmp = {6'b000001,Fin[22:19]}; // mant = Fin[22:19]
end
else if (Fin[30:23]==8'd107 && ~(4'b0|Fin[22:19]))
begin
Man_tmp = {6'b000001,4'b0}; // mant = 0,0000010000
end
else if (Fin[30:23]==8'd106 && (3'b0|Fin[22:20]))
begin
Man_tmp = {7'b0000001,Fin[22:20]}; // mant = Fin[22:20]
end
else if (Fin[30:23]==8'd106 && ~(3'b0|Fin[22:20]))
begin
Man_tmp = {7'b0000001,3'b0}; // mant = 0,0000001000
end
else if (Fin[30:23]==8'd105 && (2'b0|Fin[22:21]))
begin
Man_tmp = {8'b00000001,Fin[22:21]}; // mant = Fin[22:21]
end
else if (Fin[30:23]==8'd105 && ~(2'b0|Fin[22:21]))
begin
Man_tmp = {8'b00000001,2'b0}; // mant = 0,0000000100
end
else if (Fin[30:23]==8'd104 && Fin[22])
begin
Man_tmp = {9'b000000001,Fin[22]}; // mant = Fin[22]
end
else if (Fin[30:23]==8'd104 && ~Fin[22])
begin
Man_tmp = {9'b000000001,1'b0}; // mant = 0,0000000010
end
else
begin
Man_tmp = 10'b0000000001; // mant = 0,0000000001
end
end
// aqui no subnormal - marcar como menor valor em vez de NaN!
else
begin
Exp_tmp = 5'b00000; // exp16 sai 00000
Man_tmp = 10'b0000000001; // mant = 0,0000000001
end
end
assign Fout = {Fin[31], Exp_tmp, Man_tmp};
endmodule
|
|
module hardware_counter (
input clk, resetn,
output reg [31:0] counter
);
always @(posedge clk or negedge resetn) begin
if(resetn == 0) begin
counter <= 32'd0;
end else begin
counter <= counter + 1;
end
end
endmodule
|
|
module det_seq(clk, rst, d, q, num);
input clk, rst;
input d;
output reg q;
output reg [2:0] num;
reg [2:0] cs, ns;
parameter one = 3'd0, two = 3'd1, three = 3'd2;
parameter four = 3'd3, five = 3'd4, six = 3'd5, correct = 3'd6;
// reset
always @(posedge clk or posedge rst)
begin
if(rst)
cs <= one;
else
cs <= ns;
end
// update state
always @(*)
begin
case(cs)
one: begin //1
ns = (d) ? two : one;
end
two: begin //0
ns = (!d) ? three : two;
end
three: begin //1
ns = (d) ? four : one;
end
four: begin //0
ns = (!d) ? five : two;
end
five: begin //1
ns = (d) ? six : one;
end
six: begin //1
ns = (d) ? correct : five;
end
correct: begin
ns = (d) ? two : three;
end
default: ns = one;
endcase
end
// output
always@(*)
begin
if(cs == correct)
q = 1'd1;
else
q = 1'd0;
end
always@(posedge clk or posedge rst)
begin
if(rst)
num <= 3'd0;
else if(cs == correct)
num <= num + 3'd1;
else
num <= num;
end
endmodule
|
|
//------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------
module dpincbar(CIN,CINBAR,IN0,COUT,COUTBAR,Y);
parameter BIT = 0;
parameter COLINST = "0";
parameter GROUP = "dpath1";
parameter
d_CIN_r = 0,
d_CIN_f = 0,
d_CINBAR_r = 0,
d_CINBAR_f = 0,
d_IN0_r = 0,
d_IN0_f = 0,
d_COUT_r = 1,
d_COUT_f = 1,
d_COUTBAR_r = 1,
d_COUTBAR_f = 1,
d_Y_r = 1,
d_Y_f = 1;
input CIN;
input CINBAR;
input IN0;
output COUT;
output COUTBAR;
output Y;
wire CIN_temp;
wire CINBAR_temp;
wire IN0_temp;
reg COUT_temp;
reg COUTBAR_temp;
reg Y_temp;
assign #(d_CIN_r,d_CIN_f) CIN_temp = CIN;
assign #(d_CINBAR_r,d_CINBAR_f) CINBAR_temp = CINBAR;
assign #(d_IN0_r,d_IN0_f) IN0_temp = IN0;
assign #(d_COUT_r,d_COUT_f) COUT = COUT_temp;
assign #(d_COUTBAR_r,d_COUTBAR_f) COUTBAR = COUTBAR_temp;
assign #(d_Y_r,d_Y_f) Y = Y_temp;
always
@(IN0_temp or CIN_temp or CINBAR_temp)
begin
COUT_temp = ( ~ (CINBAR_temp | IN0_temp));
COUTBAR_temp = ( ~ (CIN_temp & ( ~ IN0_temp)));
Y_temp = (CIN_temp ^ IN0_temp);
end
endmodule
|
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter y0=0,y1=1,y2=2,y3=3,y4=4;
reg [2:0] state, next_state;
always @ (posedge clk) begin
if(reset)
state<=y0;
else
state<=next_state;
end
always @ (*) begin
case(state)
y0: next_state = x? y1: y0;
y1: next_state = x? y4: y1;
y2: next_state = x? y1: y2;
y3: next_state = x? y2: y1;
y4: next_state = x? y4: y3;
endcase
end
assign z = (state==y3||state==y4);
endmodule
|
|
`timescale 1ns / 1ps
module decoder(ANODES, X, Y, Z, A, B, C, out);
input [7:0] ANODES;
input [3:0] X;
input [3:0] Y;
input [3:0] Z;
input [3:0] A;
input [3:0] B;
input [3:0] C;
output reg [3:0] out;
always@(*)
begin
out = (ANODES == 8'b11111110) ? X:
(ANODES == 8'b11111101) ? Y:
(ANODES == 8'b11111011) ? Z:
(ANODES == 8'b11110111) ? A:
(ANODES == 8'b11101111) ? B:
(ANODES == 8'b11011111) ? C:
4'b0000;
end
endmodule
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// List of Array Registers Logics used in most of other hardware blocks
//////////////////////////////////////////////////////////////////////////////////
module latch_32bit(
input wire clk, active,
input wire [31:0] in0, in1, in2, in3,
output reg [31:0] out0, out1, out2, out3
);
always @(posedge clk) begin
if (active) begin
out0 <= in0;
out1 <= in1;
out2 <= in2;
out3 <= in3;
end
end
endmodule
module reg_32bit(
input wire clk, rst,
input wire [31:0] in0,
output reg [31:0] out0
);
always@(posedge clk) begin
if (rst) begin
out0 <= 32'h0000_0000;
end else begin
out0 <= in0;
end
end
endmodule
module reg4_32bit(
input wire clk,
input wire [31:0] in0, in1, in2, in3,
output reg [31:0] out0, out1, out2, out3
);
always@(posedge clk) begin
out0 <= in0;
out1 <= in1;
out2 <= in2;
out3 <= in3;
end
endmodule
module reg_16bit(
input wire clk, rst,
input wire [15:0] in0,
output reg [15:0] out0
);
always@(posedge clk) begin
if (rst) begin
out0 <= 16'h0000;
end else begin
out0 <= in0;
end
end
endmodule
module reg_12bit(
input wire clk, rst,
input wire [11:0] in0,
output reg [11:0] out0
);
always@(posedge clk) begin
if (rst) begin
out0 <= 12'h000;
end else begin
out0 <= in0;
end
end
endmodule
module reg_2bit(
input wire clk, rst,
input wire [1:0] in0,
output reg [1:0] out0
);
always@(posedge clk) begin
if (rst) begin
out0 <= 2'b00;
end else begin
out0 <= in0;
end
end
endmodule
module couunter_10(
input wire clk, rst,
output reg [3:0] Q
);
always @(posedge clk) begin
if (rst) begin
Q <= 4'b0;
end else begin
if (Q == 4'd9) begin
Q <= Q;
end else begin
Q <= Q + 1'b1;
end
end
end
endmodule
|
|
//Memeory
module mem(
//Output(s)
ReadData,
//Input(s)
Addr,
WriteData,
MemWrite,
MemRead
);
input wire MemWrite, MemRead;
input wire[15:0] Addr, WriteData;
output reg [15:0] ReadData;
endmodule
|
|
//File12 name : smc_wr_enable_lite12.v
//Title12 :
//Created12 : 1999
//Description12 :
//Notes12 :
//----------------------------------------------------------------------
// Copyright12 1999-2010 Cadence12 Design12 Systems12, Inc12.
// All Rights12 Reserved12 Worldwide12
//
// Licensed12 under the Apache12 License12, Version12 2.0 (the
// "License12"); you may not use this file except12 in
// compliance12 with the License12. You may obtain12 a copy of
// the License12 at
//
// http12://www12.apache12.org12/licenses12/LICENSE12-2.0
//
// Unless12 required12 by applicable12 law12 or agreed12 to in
// writing, software12 distributed12 under the License12 is
// distributed12 on an "AS12 IS12" BASIS12, WITHOUT12 WARRANTIES12 OR12
// CONDITIONS12 OF12 ANY12 KIND12, either12 express12 or implied12. See
// the License12 for the specific12 language12 governing12
// permissions12 and limitations12 under the License12.
//----------------------------------------------------------------------
module smc_wr_enable_lite12 (
//inputs12
n_sys_reset12,
r_full12,
n_r_we12,
n_r_wr12,
//outputs12
smc_n_we12,
smc_n_wr12);
//I12/O12
input n_sys_reset12; //system reset
input r_full12; // Full cycle write strobe12
input [3:0] n_r_we12; //write enable from smc_strobe12
input n_r_wr12; //write strobe12 from smc_strobe12
output [3:0] smc_n_we12; // write enable (active low12)
output smc_n_wr12; // write strobe12 (active low12)
//output reg declaration12.
reg [3:0] smc_n_we12;
reg smc_n_wr12;
//----------------------------------------------------------------------
// negedge strobes12 with clock12.
//----------------------------------------------------------------------
//----------------------------------------------------------------------
//--------------------------------------------------------------------
// Gate12 Write strobes12 with clock12.
//--------------------------------------------------------------------
always @(r_full12 or n_r_we12)
begin
smc_n_we12[0] = ((~r_full12 ) | n_r_we12[0] );
smc_n_we12[1] = ((~r_full12 ) | n_r_we12[1] );
smc_n_we12[2] = ((~r_full12 ) | n_r_we12[2] );
smc_n_we12[3] = ((~r_full12 ) | n_r_we12[3] );
end
//--------------------------------------------------------------------
//write strobe12 generation12
//--------------------------------------------------------------------
always @(n_r_wr12 or r_full12 )
begin
smc_n_wr12 = ((~r_full12 ) | n_r_wr12 );
end
endmodule // smc_wr_enable12
|
|
// megafunction wizard: %MAX II oscillator%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altufm_osc
// ============================================================
// File Name: internal_osc.v
// Megafunction Name(s):
// altufm_osc
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module internal_osc (
oscena,
osc)/* synthesis synthesis_clearbox = 1 */;
input oscena;
output osc;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_PART STRING ""
// Retrieval info: PRIVATE: INTERFACE_CHOICE NUMERIC "4"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL osc
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL oscena
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL internal_osc_bb.v TRUE
// Retrieval info: LIB_FILE: maxii
|
|
// Copyright 2020 Matt Venn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`default_nettype none
module inverter (
input wire in,
output out );
assign out = !in;
endmodule
|
|
module if_else_logicalOR (
input condition1,
input condition2,
input condition3,
output reg result
);
always @(*) begin
if (condition1 || condition2 || condition3) begin
// execute behavior if any condition is met
result <= 1'b1;
end
else begin
// execute default behavior if no condition is met
result <= 1'b0;
end
end
endmodule
|
|
module BTB #(parameter W_PC = 8, W_BTA = 32)
(
input clk,
input reset,
input [W_PC-1:0] pc, // LSB 8 bits
input [31:0] aluBranchAddress,
input [31:0] pcOfAluBranchAddress,
input [0:0] branchTakenE,
input [0:0] branchPredictedE,
output reg [W_BTA-1:0] BTA, // MSB 32 bits
output reg hit,
output reg [39:0] cache0, cache1, cache2
// output reg [2:0] lastUsedID
);
reg [39:0] pcOfAluBranchAddressReg; // First 8 bits are PC, Remaining 32 bits are BTA
reg [2:0] lastUsedID;
reg [39:0] temp0, temp1;
initial
begin
lastUsedID = 0;
cache0 = 40'h0000001108;
cache1 = 40'h0000002212;
cache2 = 40'h0000003316;
end
always @(reset or pc or pcOfAluBranchAddress or aluBranchAddress or branchTakenE or branchPredictedE)
begin
pcOfAluBranchAddressReg = pcOfAluBranchAddress - 4;
if (reset == 1)
begin
lastUsedID = 4; // Reset signal
end
else if ((cache0[7:0] != pcOfAluBranchAddress[7:0]) && (cache1[7:0] != pcOfAluBranchAddress[7:0]) && (cache2[7:0] != pcOfAluBranchAddress[7:0]) && (branchTakenE == 1) && (branchPredictedE == 0))
begin
lastUsedID = 3; // It could not find it in the BTB
end
else if (cache0[7:0] == pc)
begin
hit = 1;
BTA = cache0[39:8];
lastUsedID = 0;
end
else if (cache1[7:0] == pc)
begin
hit = 1;
BTA = cache1[39:8];
lastUsedID = 1;
end
else if (cache2[7:0] == pc)
begin
hit = 1;
BTA = cache2[39:8];
lastUsedID = 2;
end
end
always @(lastUsedID)
begin
if (lastUsedID == 0) // Stay same
begin
cache0 = cache0;
cache1 = cache1;
cache2 = cache2;
end
else if (lastUsedID == 2)
begin
temp0 = cache0;
temp1 = cache1;
cache0 = cache2;
cache1 = temp0;
cache2 = temp1;
end
else if (lastUsedID == 1)
begin
temp0 = cache0;
temp1 = cache1;
cache0 = temp1;
cache1 = temp0;
end
else if (lastUsedID == 4)
begin
cache0 = 0;
cache1 = 0;
cache2 = 0;
end
else if (lastUsedID == 3)
begin
temp0 = cache0;
temp1 = cache1;
cache0 = {aluBranchAddress,pcOfAluBranchAddressReg[7:0]};
cache1 = temp0;
cache2 = temp1;
end
end
endmodule
|
|
module shifter_27 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] c
);
always @* begin
case (alufn[0+5-:6])
6'h20: begin
c = a << b[0+2-:3];
end
6'h21: begin
c = a >> b[0+2-:3];
end
6'h23: begin
c = $signed(a) >>> b[0+2-:3];
end
default: begin
c = a;
end
endcase
end
endmodule
|
|
module sbentsrc #(
parameter RNG_WIDTH = 4,
parameter RESET = 1
)(
input wire i_clk,
input wire i_reset,
input wire i_en,
output reg [RNG_WIDTH-1:0] o_rnd
) /* synthesis syn_preserve = 1 */ ;
wire ff_reset = RESET & i_reset;
function [3:0] sbox_f_hdminmax;
//design criterias:
//- invertible
//- out->in sequence visit all states
//- hamming distance between two consecutive states must be either 1 (the min) or 4 (the max)
input [3:0] in;
begin
case(in)
4'b0000: sbox_f_hdminmax = 4'b1111;//0->F, hd=4
4'b1111: sbox_f_hdminmax = 4'b1110;//F->E, hd=1
4'b1110: sbox_f_hdminmax = 4'b0001;//E->1, hd=4
4'b0001: sbox_f_hdminmax = 4'b0011;//1->3, hd=1
4'b0011: sbox_f_hdminmax = 4'b1100;//3->C, hd=4
4'b1100: sbox_f_hdminmax = 4'b1101;//C->D, hd=1
4'b1101: sbox_f_hdminmax = 4'b0010;//D->2, hd=4
4'b0010: sbox_f_hdminmax = 4'b0110;//2->6, hd=1
4'b0110: sbox_f_hdminmax = 4'b1001;//6->9, hd=4
4'b1001: sbox_f_hdminmax = 4'b1000;//9->8, hd=1
4'b1000: sbox_f_hdminmax = 4'b0111;//8->7, hd=4
4'b0111: sbox_f_hdminmax = 4'b0101;//7->5, hd=1
4'b0101: sbox_f_hdminmax = 4'b1010;//5->A, hd=4
4'b1010: sbox_f_hdminmax = 4'b1011;//A->B, hd=1
4'b1011: sbox_f_hdminmax = 4'b0100;//B->4, hd=4
4'b0100: sbox_f_hdminmax = 4'b0000;//4->0, hd=1
endcase
end
endfunction
function [3:0] inv_sbox_f_hdminmax;
input [3:0] in;
begin
case(in)
4'b1111: inv_sbox_f_hdminmax = 4'b0000;//F->0, hd=4
4'b1110: inv_sbox_f_hdminmax = 4'b1111;//E->F, hd=1
4'b0001: inv_sbox_f_hdminmax = 4'b1110;//1->E, hd=4
4'b0011: inv_sbox_f_hdminmax = 4'b0001;//3->1, hd=1
4'b1100: inv_sbox_f_hdminmax = 4'b0011;//C->3, hd=4
4'b1101: inv_sbox_f_hdminmax = 4'b1100;//D->C, hd=1
4'b0010: inv_sbox_f_hdminmax = 4'b1101;//2->D, hd=4
4'b0110: inv_sbox_f_hdminmax = 4'b0010;//6->2, hd=1
4'b1001: inv_sbox_f_hdminmax = 4'b0110;//9->6, hd=4
4'b1000: inv_sbox_f_hdminmax = 4'b1001;//8->9, hd=1
4'b0111: inv_sbox_f_hdminmax = 4'b1000;//7->8, hd=4
4'b0101: inv_sbox_f_hdminmax = 4'b0111;//5->7, hd=1
4'b1010: inv_sbox_f_hdminmax = 4'b0101;//A->5, hd=4
4'b1011: inv_sbox_f_hdminmax = 4'b1010;//B->A, hd=1
4'b0100: inv_sbox_f_hdminmax = 4'b1011;//4->B, hd=4
4'b0000: inv_sbox_f_hdminmax = 4'b0100;//0->4, hd=1
endcase
end
endfunction
function [3:0] sbox_f_hdvar;
//design criterias:
//- invertible
//- out->in sequence visit all states
//- hamming distance between two consecutive states must be a mixture of 1,2,3,4
input [3:0] in;
begin
case(in)
4'b0000: sbox_f_hdvar = 4'b0011;//0->3, hd=2
4'b0011: sbox_f_hdvar = 4'b1100;//3->C, hd=4
4'b1100: sbox_f_hdvar = 4'b1010;//C->A, hd=2
4'b1010: sbox_f_hdvar = 4'b0001;//A->1, hd=3
4'b0001: sbox_f_hdvar = 4'b0110;//1->6, hd=3
4'b0110: sbox_f_hdvar = 4'b1001;//6->9, hd=4
4'b1001: sbox_f_hdvar = 4'b1000;//9->8, hd=1
4'b1000: sbox_f_hdvar = 4'b0101;//8->5, hd=3
4'b0101: sbox_f_hdvar = 4'b0100;//5->4, hd=1
4'b0100: sbox_f_hdvar = 4'b1101;//4->D, hd=2
4'b1101: sbox_f_hdvar = 4'b0010;//D->2, hd=4
4'b0010: sbox_f_hdvar = 4'b1111;//2->F, hd=3
4'b1111: sbox_f_hdvar = 4'b1110;//F->E, hd=1
4'b1110: sbox_f_hdvar = 4'b0111;//E->7, hd=2
4'b0111: sbox_f_hdvar = 4'b1011;//7->B, hd=2
4'b1011: sbox_f_hdvar = 4'b0000;//B->0, hd=3
endcase
end
endfunction
function [3:0] inv_sbox_f_hdvar;
input [3:0] in;
begin
case(in)
4'b0011: inv_sbox_f_hdvar = 4'b0000;//3->0, hd=2
4'b1100: inv_sbox_f_hdvar = 4'b0011;//C->3, hd=4
4'b1010: inv_sbox_f_hdvar = 4'b1100;//A->C, hd=2
4'b0001: inv_sbox_f_hdvar = 4'b1010;//1->A, hd=3
4'b0110: inv_sbox_f_hdvar = 4'b0001;//6->1, hd=3
4'b1001: inv_sbox_f_hdvar = 4'b0110;//9->6, hd=4
4'b1000: inv_sbox_f_hdvar = 4'b1001;//8->9, hd=1
4'b0101: inv_sbox_f_hdvar = 4'b1000;//5->8, hd=3
4'b0100: inv_sbox_f_hdvar = 4'b0101;//4->5, hd=1
4'b1101: inv_sbox_f_hdvar = 4'b0100;//D->4, hd=2
4'b0010: inv_sbox_f_hdvar = 4'b1101;//2->D, hd=4
4'b1111: inv_sbox_f_hdvar = 4'b0010;//F->2, hd=3
4'b1110: inv_sbox_f_hdvar = 4'b1111;//E->F, hd=1
4'b0111: inv_sbox_f_hdvar = 4'b1110;//7->E, hd=2
4'b1011: inv_sbox_f_hdvar = 4'b0111;//B->7, hd=2
4'b0000: inv_sbox_f_hdvar = 4'b1011;//0->B, hd=3
endcase
end
endfunction
function [3:0] sbox_f_min_hd2;
//design criterias:
//- invertible
//- out->in sequence visit all states
//- hamming distance between two consecutive states >=2
input [3:0] in;
begin
case(in)
4'b0000: sbox_f_min_hd2 = 4'b0011;//0->3, hd=2
4'b0011: sbox_f_min_hd2 = 4'b1100;//3->C, hd=4
4'b1100: sbox_f_min_hd2 = 4'b1010;//C->A, hd=2
4'b1010: sbox_f_min_hd2 = 4'b0001;//A->1, hd=3
4'b0001: sbox_f_min_hd2 = 4'b0110;//1->6, hd=3
4'b0110: sbox_f_min_hd2 = 4'b1111;//6->F, hd=2
4'b1111: sbox_f_min_hd2 = 4'b0101;//F->5, hd=2
4'b0101: sbox_f_min_hd2 = 4'b1000;//5->8, hd=3
4'b1000: sbox_f_min_hd2 = 4'b1011;//8->B, hd=2
4'b1011: sbox_f_min_hd2 = 4'b1101;//B->D, hd=2
4'b1101: sbox_f_min_hd2 = 4'b0111;//D->7, hd=2
4'b0111: sbox_f_min_hd2 = 4'b0010;//7->2, hd=2
4'b0010: sbox_f_min_hd2 = 4'b1001;//2->9, hd=3
4'b1001: sbox_f_min_hd2 = 4'b0100;//9->4, hd=3
4'b0100: sbox_f_min_hd2 = 4'b1110;//4->E, hd=2
4'b1110: sbox_f_min_hd2 = 4'b0000;//E->0, hd=3
endcase
end
endfunction
function [3:0] inv_sbox_f_min_hd2;
input [3:0] in;
begin
case(in)
4'b0011: inv_sbox_f_min_hd2 = 4'b0000;//3->0, hd=2
4'b1100: inv_sbox_f_min_hd2 = 4'b0011;//C->3, hd=4
4'b1010: inv_sbox_f_min_hd2 = 4'b1100;//A->C, hd=2
4'b0001: inv_sbox_f_min_hd2 = 4'b1010;//1->A, hd=3
4'b0110: inv_sbox_f_min_hd2 = 4'b0001;//6->1, hd=3
4'b1111: inv_sbox_f_min_hd2 = 4'b0110;//F->6, hd=2
4'b0101: inv_sbox_f_min_hd2 = 4'b1111;//5->F, hd=2
4'b1000: inv_sbox_f_min_hd2 = 4'b0101;//8->5, hd=3
4'b1011: inv_sbox_f_min_hd2 = 4'b1000;//B->8, hd=2
4'b1101: inv_sbox_f_min_hd2 = 4'b1011;//D->B, hd=2
4'b0111: inv_sbox_f_min_hd2 = 4'b1101;//7->D, hd=2
4'b0010: inv_sbox_f_min_hd2 = 4'b0111;//2->7, hd=2
4'b1001: inv_sbox_f_min_hd2 = 4'b0010;//9->2, hd=3
4'b0100: inv_sbox_f_min_hd2 = 4'b1001;//4->9, hd=3
4'b1110: inv_sbox_f_min_hd2 = 4'b0100;//E->4, hd=2
4'b0000: inv_sbox_f_min_hd2 = 4'b1110;//0->E, hd=3
endcase
end
endfunction
function [3:0] sbox_f_hd3;
//design criterias:
//- invertible
//- out->in sequence visit all states
//- hamming distance between two consecutive states >=3
input [3:0] in;
begin
case(in)
4'b0000: sbox_f_hd3 = 4'b1110;//0->E, hd=3
4'b1110: sbox_f_hd3 = 4'b0011;//E->3, hd=3
4'b0011: sbox_f_hd3 = 4'b1101;//3->D, hd=3
4'b1101: sbox_f_hd3 = 4'b0110;//D->6, hd=3
4'b0110: sbox_f_hd3 = 4'b1000;//6->8, hd=3
4'b1000: sbox_f_hd3 = 4'b0101;//8->5, hd=3
4'b0101: sbox_f_hd3 = 4'b1011;//5->B, hd=3
4'b1011: sbox_f_hd3 = 4'b1100;//B->C, hd=3
4'b1100: sbox_f_hd3 = 4'b0010;//C->2, hd=3
4'b0010: sbox_f_hd3 = 4'b1111;//2->F, hd=3
4'b1111: sbox_f_hd3 = 4'b0001;//F->1, hd=3
4'b0001: sbox_f_hd3 = 4'b1010;//1->A, hd=3
4'b1010: sbox_f_hd3 = 4'b0100;//A->4, hd=3
4'b0100: sbox_f_hd3 = 4'b1001;//4->9, hd=3
4'b1001: sbox_f_hd3 = 4'b0111;//9->7, hd=3
4'b0111: sbox_f_hd3 = 4'b0000;//7->0, hd=3
endcase
end
endfunction
function [3:0] inv_sbox_f_hd3;
input [3:0] in;
begin
case(in)
4'b1110: inv_sbox_f_hd3 = 4'b0000;//E->0, hd=3
4'b0011: inv_sbox_f_hd3 = 4'b1110;//3->E, hd=3
4'b1101: inv_sbox_f_hd3 = 4'b0011;//D->3, hd=3
4'b0110: inv_sbox_f_hd3 = 4'b1101;//6->D, hd=3
4'b1000: inv_sbox_f_hd3 = 4'b0110;//8->6, hd=3
4'b0101: inv_sbox_f_hd3 = 4'b1000;//5->8, hd=3
4'b1011: inv_sbox_f_hd3 = 4'b0101;//B->5, hd=3
4'b1100: inv_sbox_f_hd3 = 4'b1011;//C->B, hd=3
4'b0010: inv_sbox_f_hd3 = 4'b1100;//2->C, hd=3
4'b1111: inv_sbox_f_hd3 = 4'b0010;//F->2, hd=3
4'b0001: inv_sbox_f_hd3 = 4'b1111;//1->F, hd=3
4'b1010: inv_sbox_f_hd3 = 4'b0001;//A->1, hd=3
4'b0100: inv_sbox_f_hd3 = 4'b1010;//4->A, hd=3
4'b1001: inv_sbox_f_hd3 = 4'b0100;//9->4, hd=3
4'b0111: inv_sbox_f_hd3 = 4'b1001;//7->9, hd=3
4'b0000: inv_sbox_f_hd3 = 4'b0111;//0->7, hd=3
endcase
end
endfunction
function [3:0] sbox_f;
input [3:0] in;
begin
sbox_f = sbox_f_hdvar(in);
end
endfunction
function [3:0] inv_sbox_f;
input [3:0] in;
begin
inv_sbox_f = inv_sbox_f_hdvar(in);
end
endfunction
reg [RNG_WIDTH-1:0] in,out,check;
localparam NSBOXES = RNG_WIDTH/4;
reg [NSBOXES-1:0] match;
//wire [NSBOXES-1:0] #250 delayed_match = match;//needed for simulation purposes
always @* begin: MATCH
integer i;
for(i=0;i<NSBOXES;i=i+1) begin
#250 match[i] = (in[i*4+:4]==check[i*4+:4]) & ~match[i] & i_en & ~i_reset;//combinational loop here is intentional, we need it to start the operations
end
end
genvar sbox_index;
generate
for(sbox_index=0;sbox_index<NSBOXES;sbox_index=sbox_index+1) begin: IN
always @(posedge match[sbox_index], posedge ff_reset) begin
if(ff_reset) in[sbox_index*4+:4] <= {4{1'b0}};
else in[sbox_index*4+:4] <= out[sbox_index*4+:4];
end
end
endgenerate
always @* begin: OUT
integer i;
for(i=0;i<NSBOXES;i=i+1) begin
#1000 out[i*4+:4] = sbox_f(in[i*4+:4]);
end
end
always @* begin: CHECK_REG
integer i;
for(i=0;i<NSBOXES;i=i+1) begin
#1000 check[i*4+:4] = inv_sbox_f(out[i*4+:4]);
end
end
always @(posedge i_clk, posedge ff_reset) begin: SAMPLER
if(ff_reset) o_rnd <= {RNG_WIDTH{1'b0}};
else o_rnd <= out ^ check;
end
endmodule
|
|
`default_nettype wire
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
// synopsys translate_off
wire [7:0] B = RegsH[0];
wire [7:0] C = RegsL[0];
wire [7:0] D = RegsH[1];
wire [7:0] E = RegsL[1];
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
wire [15:0] IX = { RegsH[3], RegsL[3] };
wire [15:0] IY = { RegsH[7], RegsL[7] };
// synopsys translate_on
endmodule
|
|
module thermometer_to_bcd(bcd, thermometer);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? 4 :
(thermometer == 16'b11111) ? 5 :
(thermometer == 16'b111111) ? 6 :
(thermometer == 16'b1111111) ? 7 :
(thermometer == 16'b11111111) ? 8 :
(thermometer == 16'b111111111) ? 9 :
(thermometer == 16'b1111111111) ? 9 :
(thermometer == 16'b11111111111) ? {4'd1, 4'd0} :
(thermometer == 16'b111111111111) ? {4'd1, 4'd1} :
(thermometer == 16'b1111111111111) ? {4'd1, 4'd2} :
(thermometer == 16'b11111111111111) ? {4'd1, 4'd3} :
(thermometer == 16'b111111111111111) ? {4'd1, 4'd4} :
(thermometer == 16'b1111111111111111) ? {4'd1, 4'd5} :
{4'd1, 4'd6};
endmodule
|
|
module stack
(
input wire CLK,
input wire RST,
input wire PUSH_STB,
input wire [7:0] PUSH_DAT,
output reg PUSH_ACK,
output reg POP_STB,
output wire [7:0] POP_DAT,
input wire POP_ACK
);
reg [3:0] sp; // stack top pointer
reg [7:0] mem [0:15];
reg [1:0] stack_state;
always@(posedge CLK or posedge RST)
if(RST) begin
PUSH_ACK <= 1'h0;
POP_STB <= 1'h0;
sp <= 4'h0;
stack_state <= 0;
end
else casex(stack_state)
//////// empty
0: begin
// if (PUSH_STB && POP_ACK) begin
// PUSH_ACK <= 1'h1;
// POP_STB <= 1'h0;
// stack_state <= 1;
// sp <= sp ;
// end
if(PUSH_STB) begin
PUSH_ACK <= 1'h1;
POP_STB <= 1'h1;
stack_state <= 1;
sp <= sp + 4'h1;
end
end
//////// not empty
1: begin
if (PUSH_STB && POP_ACK) begin
PUSH_ACK <= 1'h1;
POP_STB <= 1'h1;
stack_state <= 1;
sp <= sp;
end
else if (PUSH_STB) begin
PUSH_ACK <= 1'h1;
POP_STB <= 1'h1;
stack_state <= (sp == 4'hF)? 2 : 1;
//sp <= (sp == 4'hF)? sp : sp + 4'h1;
sp <= sp + 4'h1;
end
else if (POP_ACK) begin
PUSH_ACK <= 1'h0;
POP_STB <= (sp > 4'h1)? 1 : 0;
stack_state <= (sp > 4'h1)? 1 : 0;
//sp <= (sp >= 4'h1)? sp - 4'h1 : sp;
sp <= sp - 4'h1;
end
end
//////// full
2: begin
if (PUSH_STB && POP_ACK) begin
PUSH_ACK <= 1'h1;
POP_STB <= 1'h1;
stack_state <= 2;
sp <= sp;
end
else if (PUSH_STB) begin
PUSH_ACK <= 1'h0;
POP_STB <= 1'h1;
stack_state <= 2;
sp <= sp;
end
else if (POP_ACK) begin
POP_STB <= 1'h1;
stack_state <= 1;
sp <= sp - 4'h1;
end
end
endcase
/////////////
always@(negedge CLK) $display("mem[%d]=%d", sp, mem[sp]);
always@(posedge CLK) begin
if (PUSH_STB && POP_ACK && stack_state != 0) mem[sp - 1] <= PUSH_DAT;
else if (PUSH_STB && stack_state != 2) mem[sp] <= PUSH_DAT;
end
assign POP_DAT = mem [(sp)? sp - 4'h1 : 4'hF];
//assign POP_DAT = mem [sp];
endmodule
|
|
module Adder(A, B, out);
input [7:0] A, B;
output [7:0] out;
assign out = A + B;
endmodule
|
|
`timescale 1ns / 1ps
module rom_mem #(
parameter CELL00 = 16'b0000_0000_0000_0000,
parameter CELL01 = 16'b0000_0000_0000_0000,
parameter CELL02 = 16'b0000_0000_0000_0000,
parameter CELL03 = 16'b0000_0000_0000_0000,
parameter CELL04 = 16'b0000_0000_0000_0000,
parameter CELL05 = 16'b0000_0000_0000_0000,
parameter CELL06 = 16'b0000_0000_0000_0000,
parameter CELL07 = 16'b0000_0000_0000_0000,
parameter CELL08 = 16'b0000_0000_0000_0000,
parameter CELL09 = 16'b0000_0000_0000_0000,
parameter CELL10 = 16'b0000_0000_0000_0000,
parameter CELL11 = 16'b0000_0000_0000_0000,
parameter CELL12 = 16'b0000_0000_0000_0000,
parameter CELL13 = 16'b0000_0000_0000_0000,
parameter CELL14 = 16'b0000_0000_0000_0000,
parameter CELL15 = 16'b0000_0000_0000_0000
) (
input oe,
input [4:0] addr,
output reg [15:0] cell_data
);
always @ (*) begin
if(oe) begin
case(addr)
5'd0: cell_data <= CELL00;
5'd1: cell_data <= CELL01;
5'd2: cell_data <= CELL02;
5'd3: cell_data <= CELL03;
5'd4: cell_data <= CELL04;
5'd5: cell_data <= CELL05;
5'd6: cell_data <= CELL06;
5'd7: cell_data <= CELL07;
5'd8: cell_data <= CELL08;
5'd9: cell_data <= CELL09;
5'd10: cell_data <= CELL10;
5'd11: cell_data <= CELL11;
5'd12: cell_data <= CELL12;
5'd13: cell_data <= CELL13;
5'd14: cell_data <= CELL14;
5'd15: cell_data <= CELL15;
default:cell_data <= 16'd0;
endcase
end
else
cell_data <= 16'd0;
end
endmodule
|
|
//-----------------------
//TP03 - 45142
//-----------------------
module multiplexador(output s, input p, input q, input r);
wire temp1, temp2, temp3;
not(temp3, r);
and(temp1, p, temp3);
and(temp2, q, r);
or ( s,temp1, temp2);
endmodule
module exemplo0033(output s, output s1, input p, input q, input chave);
wire temp1, temp2, temp3, temp4;
and(temp1, p, q);
nand(temp2, p, q);
or (temp3, p, q);
nor(temp4, p, q);
multiplexador MULT(s, temp1, temp2, chave);
multiplexador MULT2(s1, temp3, temp4, chave);
endmodule
module testexemplo0033;
reg a, b, c;
wire s, s1;
exemplo0033 Q03(s, s1, a, b, c);
initial begin
a = 'b0;
b = 'b0;
c = 'b0;
#1$monitor("%3b %3b %3b = %3b %3b", a, b, c, s, s1);
#1a= 'b0;b= 'b0;c= 'b1;
#1a= 'b0;b= 'b1;c= 'b0;
#1a= 'b0;b= 'b1;c= 'b1;
#1a= 'b1;b= 'b0;c= 'b0;
#1a= 'b1;b= 'b0;c= 'b1;
#1a= 'b1;b= 'b1;c= 'b0;
#1a= 'b1;b= 'b1;c= 'b1;
end
endmodule
|
|
module timing_control (
input wire clk,
input wire rst,
// Timing control block inputs and outputs
);
// Timing control block implementation here
endmodule
|
|
module left_shift(
input [31:0] data_in,
input [31:0] shift_amount,
output [31:0] data_out
);
assign data_out = data_in << shift_amount[4:0]; //max shift amount is 5 bits for 32 bit values
endmodule
|
|
module rsc(clk, in, x_out, z_out, rst_N, mode, mode_out, valid_out);
input clk, in, rst_N, mode;
output x_out, z_out, mode_out, valid_out;
wire clk, in, rst_N, mode; // 1-bit wide
reg x_out, z_out, valid_out, mode_out; // 1-bit wide
reg IN, d1, d2, d3;
reg n1, n2, n3, n4;
always @(posedge clk) begin
if(rst_N == 1'b0) begin
d1 <= 1'b0;
d2 <= 1'b0;
d3 <= 1'b0;
IN <= 1'b0;
end
else begin
d3 <= d2;
d2 <= d1;
d1 <= n1;
IN <= in;
end
valid_out <= rst_N;
mode_out <= mode;
end
always @(*) begin
n4 = d2 + d3;
if(mode == 1'b0)
n1 = IN + n4;
else
n1 = n4 + n4;
n2 = d1 + n1;
n3 = d3 + n2;
if(mode == 1'b0)
x_out = IN;
else
x_out = n4;
z_out = n3;
end
endmodule
|
|
module etapa2_flops (
input [7:0] data_in0,
input valid_in0,
output reg [7:0] data_out0,
output reg valid_out0,
input clk_2f,
input reset
);
always @ (posedge clk_2f) begin
if (!reset) begin
data_out0 <= 0;
valid_out0 <= 0;
end else begin
data_out0 <= data_in0;
valid_out0 <= valid_in0;
end
end
endmodule
|
|
`timescale 1ns / 1ps
// fpga4student.com
// FPGA projects, VHDL projects, Verilog projects
// Verilog code for RISC Processor
// Verilog code for Control Unit
module Control_Unit(
input[3:0] opcode,
output reg[1:0] alu_op,
output reg beq,mem_read,mem_write,reg_dst,mem_to_reg,reg_write,load
);
always @(*)
begin
case(opcode)
4'b0000: // LW
begin
reg_dst <= 1'b0;
mem_to_reg <= 1'b1;
reg_write <= 1'b1;
mem_read <= 1'b1;
mem_write <= 1'b0;
beq <= 1'b0;
alu_op <= 2'b10;
load <= 0;
end
4'b0001: // SW
begin
reg_dst <= 1'b0;
mem_to_reg <= 1'b0;
reg_write <= 1'b0;
mem_read <= 1'b0;
mem_write <= 1'b1;
beq <= 1'b0;
alu_op <= 2'b10;
load <= 0;
end
4'b0010: // add
begin
reg_dst <= 1'b1;
mem_to_reg <= 1'b0;
reg_write <= 1'b1;
mem_read <= 1'b0;
mem_write <= 1'b0;
beq <= 1'b0;
alu_op <= 2'b00;
load <= 0;
end
4'b0011: // subtract
begin
reg_dst <= 1'b1;
mem_to_reg <= 1'b0;
reg_write <= 1'b1;
mem_read <= 1'b0;
mem_write <= 1'b0;
beq <= 1'b0;
alu_op <= 2'b01;
load <= 0;
end
4'b0100: // load const
begin
reg_dst <= 1'b0;
mem_to_reg <= 1'b0;
reg_write <= 1'b1;
mem_read <= 1'b0;
mem_write <= 1'b0;
beq <= 1'b0;
alu_op <= 2'b00;
load <= 1;
end
4'b0101: // BEQ
begin
reg_dst <= 1'b0;
mem_to_reg <= 1'b0;
reg_write <= 1'b0;
mem_read <= 1'b0;
mem_write <= 1'b0;
beq <= 1'b1;
alu_op <= 2'b00;
load <= 0;
end
default: begin
reg_dst <= 1'b1;
mem_to_reg <= 1'b0;
reg_write <= 1'b1;
mem_read <= 1'b0;
mem_write <= 1'b0;
beq <= 1'b0;
alu_op <= 2'b00;
end
endcase
end
endmodule
|
|
//Modulo Decodificador do simbolo de adubacao/limpeza
module decode_simb(Limp, M, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_P);
input Limp, M; // Entradas para o decodificador
output SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_P;
// Entradas negadas
wire notL, notM, wire1, wire2, wire3, wire4;
not Not0(notM, M);
not Not1(notL, Limp);
//SEGMENTO A
or Or0(wire1, notM, Limp);
and And0(SEG_A, wire1, wire1);
//SEGMENTO B
and And1(SEG_B, wire1, wire1);
//SEGMENTO C
and And2(SEG_C, wire1, wire1);
//SEGMENTO D
or Or1(SEG_D, M, notL);
//SEGMENTO E
and And3(wire2, notL, notM);
and And4(wire3, notL, notM);
or Or2(wire4, wire2, wire3);
and And5(SEG_E, wire4, wire4);
//SEGMENTO F
and And6(SEG_F, wire4, wire4);
//SEGMENTO G
and And7(SEG_G, wire1, wire1);
//SEGMENTO P
not Not2(SEG_P, 0);
endmodule
|
|
`timescale 1ns / 1ps
`ifndef LIB_STYCZYNSKI_MIN_MAX_V
`define LIB_STYCZYNSKI_MIN_MAX_V
/*
* Piotr Styczyski @styczynski
* Verilog Components Library
*
* Min-max arithmetic module
*
*
* MIT License
*/
module MinMax
#(
parameter INPUT_BIT_WIDTH = 8
)
(
input Clk,
input [INPUT_BIT_WIDTH-1:0] InputA,
input [INPUT_BIT_WIDTH-1:0] InputB,
output reg [INPUT_BIT_WIDTH-1:0] Max,
output reg [INPUT_BIT_WIDTH-1:0] Min
);
always @(posedge Clk)
begin
if(InputA < InputB)
begin
Max <= InputB;
Min <= InputA;
end
else
begin
Max <= InputA;
Min <= InputB;
end
end
endmodule
`endif
|
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// N -bit counter with load, set and 2 increment
module Counter(CLK,
RST_N,
Q_OUT,
DATA_A, ADDA,
DATA_B, ADDB,
DATA_C, SETC,
DATA_F, SETF);
parameter width = 1;
parameter init = 0;
input CLK;
input RST_N;
input [width - 1 : 0] DATA_A;
input ADDA;
input [width - 1 : 0] DATA_B;
input ADDB;
input [width - 1 : 0] DATA_C;
input SETC;
input [width - 1 : 0] DATA_F;
input SETF;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] q_state ;
assign Q_OUT = q_state ;
always@(posedge CLK /*or negedge RST_N*/ ) begin
if (RST_N == 0)
q_state <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if ( SETF )
q_state <= `BSV_ASSIGNMENT_DELAY DATA_F ;
else
q_state <= `BSV_ASSIGNMENT_DELAY (SETC ? DATA_C : q_state ) + (ADDA ? DATA_A : {width {1'b0}}) + (ADDB ? DATA_B : {width {1'b0}} ) ;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
q_state = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
|
module spi_master (
input wire clk,
input wire rst,
input wire enable,
input wire data_in,
output reg data_out,
output reg ready
);
// State machine states
parameter IDLE_STATE = 2'b00;
parameter TRANSMIT_STATE = 2'b01;
parameter RECEIVE_STATE = 2'b10;
// Data registers
reg [7:0] tx_data_reg;
reg [7:0] rx_data_reg;
// Control signals
reg start_transfer;
reg select_slave;
reg spi_clk;
// Shift register
reg [7:0] shift_reg;
// Clock divider
reg [7:0] clk_divider;
// State machine
reg [1:0] state;
always @ (posedge clk or posedge rst) begin
if (rst) begin
state <= IDLE_STATE;
end else begin
case (state)
IDLE_STATE: begin
if (enable) begin
state <= TRANSMIT_STATE;
start_transfer <= 1'b1;
select_slave <= 1'b1;
end
end
TRANSMIT_STATE: begin
if (ready) begin
state <= RECEIVE_STATE;
start_transfer <= 1'b1;
select_slave <= 1'b0;
end
end
RECEIVE_STATE: begin
state <= IDLE_STATE;
end
endcase
end
end
// Data transfer logic
always @ (posedge clk or posedge rst) begin
if (rst) begin
tx_data_reg <= 8'b0;
end else begin
case (state)
IDLE_STATE: begin
// Do nothing
end
TRANSMIT_STATE: begin
// Transmit data to slave device
shift_reg <= tx_data_reg;
spi_clk <= ~spi_clk;
if (clk_divider == 8'd0) begin
ready <= 1'b1;
end
end
RECEIVE_STATE: begin
// Receive data from slave device
rx_data_reg <= shift_reg;
spi_clk <= ~spi_clk;
if (clk_divider == 8'd0) begin
ready <= 1'b1;
end
end
endcase
end
end
// Clock divider logic
always @ (posedge clk or posedge rst) begin
if (rst) begin
clk_divider <= 8'd0;
end else begin
if (spi_clk) begin
clk_divider <= clk_divider + 1;
end
end
end
endmodule
|
|
module VerilogAdder(
input wire [31:0]a,
input wire [31:0]b,
input wire Cin,
output wire posOverflow,
output wire negOverflow,
output wire [31:0]S,
output wire Cout
);
assign {Cout,S} = a + b + Cin;
assign negOverflow = (a[31] == b[31]) & (a[31] == 1) & (S[31] == 0);
assign posOverflow = (a[31] == b[31]) & (a[31] == 0) & (S[31] == 1);
endmodule
|
|
module ADC
(
input wire clk_in,
input wire [7:0]data_in,
output wire read,
output reg [7:0]data_ch1,data_ch2,data_ch3,
output [1:0]in
);
reg [3:0]state;
always @ (posedge clk_in)
begin
state <= state + 1'b1;
end
assign read = (state[1]^state[0]) ? 1'b0 : 1'b1;
assign in[1] = state[3];
assign in[0] = state[2];
always @(state)
begin
case(state)
4'b0110:data_ch1 <= data_in<<2;
4'b1010:data_ch2 <= data_in;
4'b1110:data_ch3 <= data_in;
endcase
end
endmodule
|
|
/*
Copyright (c) 2019-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI stream sink DMA client
*/
module dma_client_axis_sink #
(
// RAM address width
parameter RAM_ADDR_WIDTH = 16,
// RAM segment count
parameter SEG_COUNT = 2,
// RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// RAM segment address width
parameter SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(SEG_COUNT*SEG_BE_WIDTH),
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = SEG_DATA_WIDTH*SEG_COUNT/2,
// Use AXI stream tkeep signal
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
// Use AXI stream tlast signal
parameter AXIS_LAST_ENABLE = 1,
// Propagate AXI stream tid signal
parameter AXIS_ID_ENABLE = 0,
// AXI stream tid signal width
parameter AXIS_ID_WIDTH = 8,
// Propagate AXI stream tdest signal
parameter AXIS_DEST_ENABLE = 0,
// AXI stream tdest signal width
parameter AXIS_DEST_WIDTH = 8,
// Propagate AXI stream tuser signal
parameter AXIS_USER_ENABLE = 1,
// AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1,
// Width of length field
parameter LEN_WIDTH = 16,
// Width of tag field
parameter TAG_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI write descriptor input
*/
input wire [RAM_ADDR_WIDTH-1:0] s_axis_write_desc_ram_addr,
input wire [LEN_WIDTH-1:0] s_axis_write_desc_len,
input wire [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input wire s_axis_write_desc_valid,
output wire s_axis_write_desc_ready,
/*
* AXI write descriptor status output
*/
output wire [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
output wire [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
output wire [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
output wire [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
output wire [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
output wire [3:0] m_axis_write_desc_status_error,
output wire m_axis_write_desc_status_valid,
/*
* AXI stream write data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
input wire s_axis_write_data_tvalid,
output wire s_axis_write_data_tready,
input wire s_axis_write_data_tlast,
input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser,
/*
* RAM interface
*/
output wire [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be,
output wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data,
output wire [SEG_COUNT-1:0] ram_wr_cmd_valid,
input wire [SEG_COUNT-1:0] ram_wr_cmd_ready,
input wire [SEG_COUNT-1:0] ram_wr_done,
/*
* Configuration
*/
input wire enable,
input wire abort
);
parameter RAM_WORD_WIDTH = SEG_BE_WIDTH;
parameter RAM_WORD_SIZE = SEG_DATA_WIDTH/RAM_WORD_WIDTH;
parameter AXIS_KEEP_WIDTH_INT = AXIS_KEEP_ENABLE ? AXIS_KEEP_WIDTH : 1;
parameter AXIS_WORD_WIDTH = AXIS_KEEP_WIDTH_INT;
parameter AXIS_WORD_SIZE = AXIS_DATA_WIDTH/AXIS_WORD_WIDTH;
parameter PART_COUNT = SEG_COUNT*SEG_BE_WIDTH / AXIS_KEEP_WIDTH_INT;
parameter PART_COUNT_WIDTH = PART_COUNT > 1 ? $clog2(PART_COUNT) : 1;
parameter PART_OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
parameter PARTS_PER_SEG = (SEG_BE_WIDTH + AXIS_KEEP_WIDTH_INT - 1) / AXIS_KEEP_WIDTH_INT;
parameter SEGS_PER_PART = (AXIS_KEEP_WIDTH_INT + SEG_BE_WIDTH - 1) / SEG_BE_WIDTH;
parameter OFFSET_WIDTH = AXIS_KEEP_WIDTH_INT > 1 ? $clog2(AXIS_KEEP_WIDTH_INT) : 1;
parameter OFFSET_MASK = AXIS_KEEP_WIDTH_INT > 1 ? {OFFSET_WIDTH{1'b1}} : 0;
parameter ADDR_MASK = {RAM_ADDR_WIDTH{1'b1}} << $clog2(AXIS_KEEP_WIDTH_INT);
parameter CYCLE_COUNT_WIDTH = LEN_WIDTH - $clog2(AXIS_KEEP_WIDTH_INT) + 1;
parameter STATUS_FIFO_ADDR_WIDTH = 5;
parameter OUTPUT_FIFO_ADDR_WIDTH = 5;
// bus width assertions
initial begin
if (RAM_WORD_SIZE * SEG_BE_WIDTH != SEG_DATA_WIDTH) begin
$error("Error: RAM data width not evenly divisble (instance %m)");
$finish;
end
if (AXIS_WORD_SIZE * AXIS_KEEP_WIDTH_INT != AXIS_DATA_WIDTH) begin
$error("Error: AXI stream data width not evenly divisble (instance %m)");
$finish;
end
if (RAM_WORD_SIZE != AXIS_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (2**$clog2(RAM_WORD_WIDTH) != RAM_WORD_WIDTH) begin
$error("Error: RAM word width must be even power of two (instance %m)");
$finish;
end
if (RAM_ADDR_WIDTH != SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH)) begin
$error("Error: RAM_ADDR_WIDTH does not match RAM configuration (instance %m)");
$finish;
end
if (AXIS_DATA_WIDTH > SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: AXI stream interface width must not be wider than RAM interface width (instance %m)");
$finish;
end
if (AXIS_DATA_WIDTH*2**$clog2(PART_COUNT) != SEG_COUNT*SEG_DATA_WIDTH) begin
$error("Error: AXI stream interface width must be a power of two fraction of RAM interface width (instance %m)");
$finish;
end
end
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_WRITE = 2'd1,
STATE_DROP_DATA = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
integer i;
reg [OFFSET_WIDTH:0] cycle_size;
reg [RAM_ADDR_WIDTH-1:0] addr_reg = {RAM_ADDR_WIDTH{1'b0}}, addr_next;
reg [AXIS_KEEP_WIDTH_INT-1:0] keep_mask_reg = {AXIS_KEEP_WIDTH_INT{1'b0}}, keep_mask_next;
reg [OFFSET_WIDTH-1:0] last_cycle_offset_reg = {OFFSET_WIDTH{1'b0}}, last_cycle_offset_next;
reg [LEN_WIDTH-1:0] length_reg = {LEN_WIDTH{1'b0}}, length_next;
reg [CYCLE_COUNT_WIDTH-1:0] cycle_count_reg = {CYCLE_COUNT_WIDTH{1'b0}}, cycle_count_next;
reg last_cycle_reg = 1'b0, last_cycle_next;
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}}, tag_next;
reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_wr_ptr_reg = 0;
reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] status_fifo_rd_ptr_reg = 0, status_fifo_rd_ptr_next;
reg [LEN_WIDTH-1:0] status_fifo_len[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [TAG_WIDTH-1:0] status_fifo_tag[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [AXIS_ID_WIDTH-1:0] status_fifo_id[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [AXIS_DEST_WIDTH-1:0] status_fifo_dest[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [AXIS_USER_WIDTH-1:0] status_fifo_user[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [SEG_COUNT-1:0] status_fifo_mask[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg status_fifo_last[(2**STATUS_FIFO_ADDR_WIDTH)-1:0];
reg [LEN_WIDTH-1:0] status_fifo_wr_len;
reg [TAG_WIDTH-1:0] status_fifo_wr_tag;
reg [AXIS_ID_WIDTH-1:0] status_fifo_wr_id;
reg [AXIS_DEST_WIDTH-1:0] status_fifo_wr_dest;
reg [AXIS_USER_WIDTH-1:0] status_fifo_wr_user;
reg [SEG_COUNT-1:0] status_fifo_wr_mask;
reg status_fifo_wr_last;
reg status_fifo_we = 1'b0;
reg status_fifo_half_full_reg = 1'b0;
reg [STATUS_FIFO_ADDR_WIDTH+1-1:0] active_count_reg = 0;
reg active_count_av_reg = 1'b1;
reg inc_active;
reg dec_active;
reg s_axis_write_desc_ready_reg = 1'b0, s_axis_write_desc_ready_next;
reg [LEN_WIDTH-1:0] m_axis_write_desc_status_len_reg = {LEN_WIDTH{1'b0}}, m_axis_write_desc_status_len_next;
reg [TAG_WIDTH-1:0] m_axis_write_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_write_desc_status_tag_next;
reg [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id_reg = {AXIS_ID_WIDTH{1'b0}}, m_axis_write_desc_status_id_next;
reg [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest_reg = {AXIS_DEST_WIDTH{1'b0}}, m_axis_write_desc_status_dest_next;
reg [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user_reg = {AXIS_USER_WIDTH{1'b0}}, m_axis_write_desc_status_user_next;
reg m_axis_write_desc_status_valid_reg = 1'b0, m_axis_write_desc_status_valid_next;
reg s_axis_write_data_tready_reg = 1'b0, s_axis_write_data_tready_next;
// internal datapath
reg [SEG_COUNT*SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
reg [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_int;
reg [SEG_COUNT*SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_int;
reg [SEG_COUNT-1:0] ram_wr_cmd_valid_int;
wire [SEG_COUNT-1:0] ram_wr_cmd_ready_int;
reg [SEG_COUNT-1:0] ram_wr_cmd_mask;
wire [SEG_COUNT-1:0] out_done;
reg [SEG_COUNT-1:0] out_done_ack;
assign s_axis_write_desc_ready = s_axis_write_desc_ready_reg;
assign m_axis_write_desc_status_len = m_axis_write_desc_status_len_reg;
assign m_axis_write_desc_status_tag = m_axis_write_desc_status_tag_reg;
assign m_axis_write_desc_status_id = m_axis_write_desc_status_id_reg;
assign m_axis_write_desc_status_dest = m_axis_write_desc_status_dest_reg;
assign m_axis_write_desc_status_user = m_axis_write_desc_status_user_reg;
assign m_axis_write_desc_status_error = 4'd0;
assign m_axis_write_desc_status_valid = m_axis_write_desc_status_valid_reg;
assign s_axis_write_data_tready = s_axis_write_data_tready_reg;
always @* begin
state_next = STATE_IDLE;
s_axis_write_desc_ready_next = 1'b0;
m_axis_write_desc_status_len_next = m_axis_write_desc_status_len_reg;
m_axis_write_desc_status_tag_next = m_axis_write_desc_status_tag_reg;
m_axis_write_desc_status_id_next = m_axis_write_desc_status_id_reg;
m_axis_write_desc_status_dest_next = m_axis_write_desc_status_dest_reg;
m_axis_write_desc_status_user_next = m_axis_write_desc_status_user_reg;
m_axis_write_desc_status_valid_next = 1'b0;
s_axis_write_data_tready_next = 1'b0;
if (PART_COUNT > 1) begin
ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
end else begin
ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
end
ram_wr_cmd_addr_int = {PART_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
ram_wr_cmd_valid_int = {SEG_COUNT{1'b0}};
for (i = 0; i < SEG_COUNT; i = i + 1) begin
ram_wr_cmd_mask[i] = ram_wr_cmd_be_int[i*SEG_BE_WIDTH +: SEG_BE_WIDTH] != 0;
end
cycle_size = AXIS_KEEP_WIDTH_INT;
addr_next = addr_reg;
keep_mask_next = keep_mask_reg;
last_cycle_offset_next = last_cycle_offset_reg;
length_next = length_reg;
cycle_count_next = cycle_count_reg;
last_cycle_next = last_cycle_reg;
tag_next = tag_reg;
status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg;
status_fifo_wr_len = 0;
status_fifo_wr_tag = tag_reg;
status_fifo_wr_id = s_axis_write_data_tid;
status_fifo_wr_dest = s_axis_write_data_tdest;
status_fifo_wr_user = s_axis_write_data_tuser;
status_fifo_wr_mask = ram_wr_cmd_mask;
status_fifo_wr_last = 1'b0;
status_fifo_we = 1'b0;
inc_active = 1'b0;
dec_active = 1'b0;
out_done_ack = {SEG_COUNT{1'b0}};
case (state_reg)
STATE_IDLE: begin
// idle state - load new descriptor to start operation
s_axis_write_desc_ready_next = enable && active_count_av_reg;
addr_next = s_axis_write_desc_ram_addr & ADDR_MASK;
last_cycle_offset_next = s_axis_write_desc_len & OFFSET_MASK;
tag_next = s_axis_write_desc_tag;
length_next = 0;
cycle_count_next = (s_axis_write_desc_len - 1) >> $clog2(AXIS_KEEP_WIDTH_INT);
last_cycle_next = cycle_count_next == 0;
if (cycle_count_next == 0 && last_cycle_offset_next != 0) begin
keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_next);
end else begin
keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
end
if (s_axis_write_desc_ready && s_axis_write_desc_valid) begin
s_axis_write_desc_ready_next = 1'b0;
s_axis_write_data_tready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
inc_active = 1'b1;
state_next = STATE_WRITE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE: begin
// write state - generate write operations
s_axis_write_data_tready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
// update counters
addr_next = addr_reg + AXIS_KEEP_WIDTH_INT;
length_next = length_reg + AXIS_KEEP_WIDTH_INT;
cycle_count_next = cycle_count_reg - 1;
last_cycle_next = cycle_count_next == 0;
if (cycle_count_next == 0 && last_cycle_offset_reg != 0) begin
keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg);
end else begin
keep_mask_next = {AXIS_KEEP_WIDTH_INT{1'b1}};
end
if (PART_COUNT > 1) begin
ram_wr_cmd_be_int = (s_axis_write_data_tkeep & keep_mask_reg) << (addr_reg & ({PART_COUNT_WIDTH{1'b1}} << PART_OFFSET_WIDTH));
end else begin
ram_wr_cmd_be_int = s_axis_write_data_tkeep & keep_mask_reg;
end
ram_wr_cmd_addr_int = {SEG_COUNT{addr_reg[RAM_ADDR_WIDTH-1:RAM_ADDR_WIDTH-SEG_ADDR_WIDTH]}};
ram_wr_cmd_data_int = {PART_COUNT{s_axis_write_data_tdata}};
ram_wr_cmd_valid_int = ram_wr_cmd_mask;
// enqueue status FIFO entry for write completion
status_fifo_wr_len = length_next;
status_fifo_wr_tag = tag_reg;
status_fifo_wr_id = s_axis_write_data_tid;
status_fifo_wr_dest = s_axis_write_data_tdest;
status_fifo_wr_user = s_axis_write_data_tuser;
status_fifo_wr_mask = ram_wr_cmd_mask;
status_fifo_wr_last = 1'b0;
status_fifo_we = 1'b1;
if (AXIS_LAST_ENABLE && s_axis_write_data_tlast) begin
if (AXIS_KEEP_ENABLE) begin
cycle_size = AXIS_KEEP_WIDTH_INT;
for (i = AXIS_KEEP_WIDTH_INT-1; i >= 0; i = i - 1) begin
if (~(s_axis_write_data_tkeep & keep_mask_reg) & (1 << i)) begin
cycle_size = i;
end
end
end else begin
cycle_size = AXIS_KEEP_WIDTH_INT;
end
// no more data to transfer, finish operation
if (last_cycle_reg && last_cycle_offset_reg > 0) begin
if (AXIS_KEEP_ENABLE && !(s_axis_write_data_tkeep & keep_mask_reg & ~({AXIS_KEEP_WIDTH_INT{1'b1}} >> (AXIS_KEEP_WIDTH_INT - last_cycle_offset_reg)))) begin
length_next = length_reg + cycle_size;
end else begin
length_next = length_reg + last_cycle_offset_reg;
end
end else begin
if (AXIS_KEEP_ENABLE) begin
length_next = length_reg + cycle_size;
end
end
// enqueue status FIFO entry for write completion
status_fifo_wr_len = length_next;
status_fifo_wr_tag = tag_reg;
status_fifo_wr_id = s_axis_write_data_tid;
status_fifo_wr_dest = s_axis_write_data_tdest;
status_fifo_wr_user = s_axis_write_data_tuser;
status_fifo_wr_mask = ram_wr_cmd_mask;
status_fifo_wr_last = 1'b1;
status_fifo_we = 1'b1;
s_axis_write_data_tready_next = 1'b0;
s_axis_write_desc_ready_next = enable && active_count_av_reg;
state_next = STATE_IDLE;
end else if (last_cycle_reg) begin
if (last_cycle_offset_reg > 0) begin
length_next = length_reg + last_cycle_offset_reg;
end
// enqueue status FIFO entry for write completion
status_fifo_wr_len = length_next;
status_fifo_wr_tag = tag_reg;
status_fifo_wr_id = s_axis_write_data_tid;
status_fifo_wr_dest = s_axis_write_data_tdest;
status_fifo_wr_user = s_axis_write_data_tuser;
status_fifo_wr_mask = ram_wr_cmd_mask;
status_fifo_wr_last = 1'b1;
status_fifo_we = 1'b1;
if (AXIS_LAST_ENABLE) begin
s_axis_write_data_tready_next = 1'b1;
state_next = STATE_DROP_DATA;
end else begin
s_axis_write_data_tready_next = 1'b0;
s_axis_write_desc_ready_next = enable && active_count_av_reg;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_WRITE;
end
end else begin
state_next = STATE_WRITE;
end
end
STATE_DROP_DATA: begin
// drop excess AXI stream data
s_axis_write_data_tready_next = 1'b1;
if (s_axis_write_data_tready && s_axis_write_data_tvalid) begin
if (s_axis_write_data_tlast) begin
s_axis_write_data_tready_next = 1'b0;
s_axis_write_desc_ready_next = enable && active_count_av_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_DROP_DATA;
end
end else begin
state_next = STATE_DROP_DATA;
end
end
endcase
m_axis_write_desc_status_len_next = status_fifo_len[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
m_axis_write_desc_status_tag_next = status_fifo_tag[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
m_axis_write_desc_status_id_next = status_fifo_id[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
m_axis_write_desc_status_dest_next = status_fifo_dest[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
m_axis_write_desc_status_user_next = status_fifo_user[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
m_axis_write_desc_status_valid_next = 1'b0;
if (status_fifo_rd_ptr_reg != status_fifo_wr_ptr_reg) begin
// status FIFO not empty
if ((status_fifo_mask[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] & ~out_done) == 0) begin
// got write completion, pop and return status
status_fifo_rd_ptr_next = status_fifo_rd_ptr_reg + 1;
out_done_ack = status_fifo_mask[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]];
if (status_fifo_last[status_fifo_rd_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]]) begin
m_axis_write_desc_status_valid_next = 1'b1;
dec_active = 1'b1;
end
end
end
end
always @(posedge clk) begin
state_reg <= state_next;
s_axis_write_desc_ready_reg <= s_axis_write_desc_ready_next;
m_axis_write_desc_status_len_reg <= m_axis_write_desc_status_len_next;
m_axis_write_desc_status_tag_reg <= m_axis_write_desc_status_tag_next;
m_axis_write_desc_status_id_reg <= m_axis_write_desc_status_id_next;
m_axis_write_desc_status_dest_reg <= m_axis_write_desc_status_dest_next;
m_axis_write_desc_status_user_reg <= m_axis_write_desc_status_user_next;
m_axis_write_desc_status_valid_reg <= m_axis_write_desc_status_valid_next;
s_axis_write_data_tready_reg <= s_axis_write_data_tready_next;
addr_reg <= addr_next;
keep_mask_reg <= keep_mask_next;
last_cycle_offset_reg <= last_cycle_offset_next;
length_reg <= length_next;
cycle_count_reg <= cycle_count_next;
last_cycle_reg <= last_cycle_next;
tag_reg <= tag_next;
if (status_fifo_we) begin
status_fifo_len[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_len;
status_fifo_tag[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_tag;
status_fifo_id[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_id;
status_fifo_dest[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_dest;
status_fifo_user[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_user;
status_fifo_mask[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_mask;
status_fifo_last[status_fifo_wr_ptr_reg[STATUS_FIFO_ADDR_WIDTH-1:0]] <= status_fifo_wr_last;
status_fifo_wr_ptr_reg <= status_fifo_wr_ptr_reg + 1;
end
status_fifo_rd_ptr_reg <= status_fifo_rd_ptr_next;
status_fifo_half_full_reg <= $unsigned(status_fifo_wr_ptr_reg - status_fifo_rd_ptr_reg) >= 2**(STATUS_FIFO_ADDR_WIDTH-1);
if (active_count_reg < 2**STATUS_FIFO_ADDR_WIDTH && inc_active && !dec_active) begin
active_count_reg <= active_count_reg + 1;
active_count_av_reg <= active_count_reg < (2**STATUS_FIFO_ADDR_WIDTH-1);
end else if (active_count_reg > 0 && !inc_active && dec_active) begin
active_count_reg <= active_count_reg - 1;
active_count_av_reg <= 1'b1;
end else begin
active_count_av_reg <= active_count_reg < 2**STATUS_FIFO_ADDR_WIDTH;
end
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_write_desc_ready_reg <= 1'b0;
m_axis_write_desc_status_valid_reg <= 1'b0;
s_axis_write_data_tready_reg <= 1'b0;
status_fifo_wr_ptr_reg <= 0;
status_fifo_rd_ptr_reg <= 0;
active_count_reg <= 0;
active_count_av_reg <= 1'b1;
end
end
// output datapath logic (write data)
generate
genvar n;
for (n = 0; n < SEG_COUNT; n = n + 1) begin
reg [SEG_BE_WIDTH-1:0] ram_wr_cmd_be_reg = {SEG_BE_WIDTH{1'b0}};
reg [SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_reg = {SEG_ADDR_WIDTH{1'b0}};
reg [SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_reg = {SEG_DATA_WIDTH{1'b0}};
reg ram_wr_cmd_valid_reg = 1'b0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_half_full_reg = 1'b0;
wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {OUTPUT_FIFO_ADDR_WIDTH{1'b0}}});
wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [SEG_BE_WIDTH-1:0] out_fifo_wr_cmd_be[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [SEG_ADDR_WIDTH-1:0] out_fifo_wr_cmd_addr[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [SEG_DATA_WIDTH-1:0] out_fifo_wr_cmd_data[2**OUTPUT_FIFO_ADDR_WIDTH-1:0];
reg [OUTPUT_FIFO_ADDR_WIDTH+1-1:0] done_count_reg = 0;
reg done_reg = 1'b0;
assign ram_wr_cmd_ready_int[n +: 1] = !out_fifo_half_full_reg;
assign ram_wr_cmd_be[n*SEG_BE_WIDTH +: SEG_BE_WIDTH] = ram_wr_cmd_be_reg;
assign ram_wr_cmd_addr[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH] = ram_wr_cmd_addr_reg;
assign ram_wr_cmd_data[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH] = ram_wr_cmd_data_reg;
assign ram_wr_cmd_valid[n +: 1] = ram_wr_cmd_valid_reg;
assign out_done[n] = done_reg;
always @(posedge clk) begin
ram_wr_cmd_valid_reg <= ram_wr_cmd_valid_reg && !ram_wr_cmd_ready[n +: 1];
out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(OUTPUT_FIFO_ADDR_WIDTH-1);
if (!out_fifo_full && ram_wr_cmd_valid_int[n +: 1]) begin
out_fifo_wr_cmd_be[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_be_int[n*SEG_BE_WIDTH +: SEG_BE_WIDTH];
out_fifo_wr_cmd_addr[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_addr_int[n*SEG_ADDR_WIDTH +: SEG_ADDR_WIDTH];
out_fifo_wr_cmd_data[out_fifo_wr_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]] <= ram_wr_cmd_data_int[n*SEG_DATA_WIDTH +: SEG_DATA_WIDTH];
out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
end
if (!out_fifo_empty && (!ram_wr_cmd_valid_reg || ram_wr_cmd_ready[n +: 1])) begin
ram_wr_cmd_be_reg <= out_fifo_wr_cmd_be[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
ram_wr_cmd_addr_reg <= out_fifo_wr_cmd_addr[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
ram_wr_cmd_data_reg <= out_fifo_wr_cmd_data[out_fifo_rd_ptr_reg[OUTPUT_FIFO_ADDR_WIDTH-1:0]];
ram_wr_cmd_valid_reg <= 1'b1;
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (done_count_reg < 2**OUTPUT_FIFO_ADDR_WIDTH && ram_wr_done[n] && !out_done_ack[n]) begin
done_count_reg <= done_count_reg + 1;
done_reg <= 1;
end else if (done_count_reg > 0 && !ram_wr_done[n] && out_done_ack[n]) begin
done_count_reg <= done_count_reg - 1;
done_reg <= done_count_reg > 1;
end
if (rst) begin
out_fifo_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
ram_wr_cmd_valid_reg <= 1'b0;
done_count_reg <= 0;
done_reg <= 1'b0;
end
end
end
endgenerate
endmodule
`resetall
|
|
module d_ff_sync_reset_set (
input wire clk,
input wire reset,
input wire set,
input wire D,
output reg Q
);
always @(posedge clk) begin
if (reset) begin
Q <= 1'b0;
end else if (set) begin
Q <= 1'b1;
end else begin
Q <= D;
end
end
endmodule
|
|
/*######################################################################
//# G0B1T: HDL EXAMPLES. 2018.
//######################################################################
//# Copyright (C) 2018. F.E.Segura-Quijano (FES) fsegura@uniandes.edu.co
//#
//# This program is free software: you can redistribute it and/or modify
//# it under the terms of the GNU General Public License as published by
//# the Free Software Foundation, version 3 of the License.
//#
//# This program is distributed in the hope that it will be useful,
//# but WITHOUT ANY WARRANTY; without even the implied warranty of
//# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//# GNU General Public License for more details.
//#
//# You should have received a copy of the GNU General Public License
//# along with this program. If not, see <http://www.gnu.org/licenses/>
//####################################################################*/
//=======================================================
// MODULE Definition
//=======================================================
module CC_ALU #(parameter DATAWIDTH_BUS=32, parameter DATAWIDTH_ALU_SELECTION=4)(
//////////// OUTPUTS //////////
CC_ALU_overflow_OutLow,
CC_ALU_carry_OutLow,
CC_ALU_negative_OutLow,
CC_ALU_zero_OutLow,
CC_ALU_data_OutBUS,
CC_ALU_Set_Flags_Out,
//////////// INPUTS //////////
CC_ALU_dataA_InBUS,
CC_ALU_dataB_InBUS,
CC_ALU_selection_InBUS
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// OUTPUTS //////////
output CC_ALU_overflow_OutLow;
output CC_ALU_carry_OutLow;
output CC_ALU_negative_OutLow;
output CC_ALU_zero_OutLow;
output reg CC_ALU_Set_Flags_Out;
output reg [DATAWIDTH_BUS-1:0] CC_ALU_data_OutBUS;
//////////// INPUTS //////////
input [DATAWIDTH_BUS-1:0] CC_ALU_dataA_InBUS;
input [DATAWIDTH_BUS-1:0] CC_ALU_dataB_InBUS;
input [DATAWIDTH_ALU_SELECTION-1:0] CC_ALU_selection_InBUS;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire caover,cout;
wire [DATAWIDTH_BUS-2:0] addition0; // Variable usada para la operacin suma y para determinar las flags
wire addition1; // Variable usada para la operacin suma y para determinar las flags
//=======================================================
// Structural coding
//=======================================================
//INPUT LOGIC: COMBINATIONAL
always@(*)
begin
case (CC_ALU_selection_InBUS)
4'b0000: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS & CC_ALU_dataB_InBUS; //ANDCC
CC_ALU_Set_Flags_Out = 1'b0;
end
4'b0001: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS | CC_ALU_dataB_InBUS; //ORCC
CC_ALU_Set_Flags_Out = 1'b0;
end
4'b0010: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS | CC_ALU_dataB_InBUS; //NORCC
CC_ALU_Set_Flags_Out = 1'b0;
end
4'b0011: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS + CC_ALU_dataB_InBUS; //ADDCC
CC_ALU_Set_Flags_Out = 1'b0;
end
4'b0100: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS; //SRL
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b0101: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS & CC_ALU_dataB_InBUS; //AND
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b0110: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS | CC_ALU_dataB_InBUS; //OR
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b0111: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS | CC_ALU_dataB_InBUS; //NOR
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1000: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS + CC_ALU_dataB_InBUS; //ADD
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1001: begin
CC_ALU_data_OutBUS = {CC_ALU_dataA_InBUS[29:0], 2'b00}; //LSHIFT2
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1010: begin
CC_ALU_data_OutBUS = {CC_ALU_dataA_InBUS[21:0], 10'b0000000000}; //LSHIFT10
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1011: begin
CC_ALU_data_OutBUS = {19'b0000000000000000000,CC_ALU_dataA_InBUS[DATAWIDTH_BUS-20:0]}; //SIMM13
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1100: begin
if(CC_ALU_dataA_InBUS[12]==1) begin //SEXT13
CC_ALU_data_OutBUS = {19'b1111111111111111111, CC_ALU_dataA_InBUS[12:0]};
CC_ALU_Set_Flags_Out = 1'b1;
end
else
begin
CC_ALU_data_OutBUS = {19'b0000000000000000000, CC_ALU_dataA_InBUS[12:0]};
CC_ALU_Set_Flags_Out = 1'b1;
end
end
4'b1101: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS + 1'b1; //INC
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1110: begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS + 3'b100; //INCPC
CC_ALU_Set_Flags_Out = 1'b1;
end
4'b1111: begin
CC_ALU_data_OutBUS = {CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1],CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1],CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1],CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1],CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1], CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1:5]}; //RSHIFT5
CC_ALU_Set_Flags_Out = 1'b1;
end
default : begin
CC_ALU_data_OutBUS = CC_ALU_dataA_InBUS; // Default
CC_ALU_Set_Flags_Out = 1'b1;
end
endcase
end
//=======================================================
// Outputs
//=======================================================
/*Flags*/
assign {caover,addition0[DATAWIDTH_BUS-2:0]}=CC_ALU_dataA_InBUS[DATAWIDTH_BUS-2:0] + CC_ALU_dataB_InBUS[DATAWIDTH_BUS-2:0]; // Determinacin de carry del bit nmero 7
assign {cout,addition1}= CC_ALU_dataA_InBUS[DATAWIDTH_BUS-1] + CC_ALU_dataB_InBUS[DATAWIDTH_BUS-1] + caover; // Determinacin de la flag Carry y la suma de busA y busB
assign CC_ALU_zero_OutLow=(CC_ALU_data_OutBUS==8'b00000000) ? 1'b0 : 1'b1; // Determinacin de la flag Zero
assign CC_ALU_carry_OutLow = ~cout;
assign CC_ALU_overflow_OutLow = ~ (caover ^ cout); // Determinacin de la flag Ov a partir de la flag Carry y el carry del bit 7
assign CC_ALU_negative_OutLow = ~ (CC_ALU_data_OutBUS[DATAWIDTH_BUS-1]);
endmodule
|
|
// Stochastic to Binary converter
module StochToBin (
input clk,
input reset,
input bit_stream,
output [7:0] bin_number,
output done
);
localparam BITSTR_LENGTH = 256; // 8-bits, max length of LFSR loop
reg [7:0] ones_count = 0;
reg [7:0] clk_count = 0;
// Accumulate 1s in SN for 256 clk cycles, then reset
always @(posedge clk) begin
if (reset) begin
clk_count <= 0;
ones_count <= 0;
end else begin
// 256 clk cycles
if (clk_count < 8'd255) begin
ones_count <= ones_count + bit_stream;
clk_count <= clk_count + 1;
end else begin
// reset counter to 0 and ones_count to incoming bit
clk_count <= 0;
ones_count <= bit_stream;
end
end
end
// Done logic
assign done = (clk_count == 8'd255) ? 1 : 0;
// Output
assign bin_number = ones_count;
endmodule
|
|
`timescale 1ps / 1ps
/*****************************************************************************
Verilog RTL Description
Configured at: 19:27:26 KST (+0900), Tuesday 19 January 2021
Configured on: design1
Configured by: hanji ()
Created by: Stratus DpOpt 2019.1.01
*******************************************************************************/
module feature_write_addr_gen_Add2i1u32_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [31:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 =
+(in1)
+(32'B00000000000000000000000000000001);
assign out1 = asc001;
endmodule
/* CADENCE ubL3TQE= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
|
|
module pid_control(Clk,Rst_n,CurrentAngle,CurrentGyro,ResultOut_l,ResultOut_r);
input Clk,Rst_n;
input signed[12:0]CurrentAngle,CurrentGyro;
output [15:0]ResultOut_l,ResultOut_r;
//reg [8:0]setAngle;
reg signed[12:0]Angle_1,Angle_2,Angle_3,Angle_4,Angle_5;
reg signed[13:0]Angle_Tmp;
reg signed[12:0]Gyro_1,Gyro_2;
reg signed[13:0]Gyro_Tmp;
parameter setAngle=90;
parameter P=10,
I=0,
D=0;
//reg [3:0]cnt;
//reg Clk_12M;
//always@(posedge Clk or negedge Rst_n)begin
// if(!Rst_n)cnt<=0;
// else if(cnt==2)begin Clk_12M<=1;cnt<=cnt+1;end
// else if(cnt==4)begin Clk_12M<=0;cnt<=0;end
// else cnt<=cnt+1;
//end
//
always@(posedge Clk or negedge Rst_n)begin
if(!Rst_n)begin
Angle_1 <= 0;
Angle_2 <= 0;
Angle_3 <= 0;
Angle_4 <= 0;
Angle_5 <= 0;
end
else begin
Angle_1 <= Angle_2;
Angle_2 <= Angle_3;
Angle_3 <= Angle_4;
Angle_4 <= Angle_5;
Angle_5 <= CurrentAngle - setAngle;
Angle_Tmp <= (Angle_1+Angle_2+Angle_3+Angle_4+Angle_5)/5;
end
end
//
always@(posedge Clk or negedge Rst_n)begin
if(!Rst_n)begin
Gyro_1 <= 0;
Gyro_2 <= 0;
end
else begin
Gyro_1 <= Gyro_2;
Gyro_2 <= CurrentGyro;
Gyro_Tmp <= Gyro_1 *7 +Gyro_2*3;
//Gyro_Tmp <=Gyro_Tmp/10;
end
end
//
reg signed[14:0]ResultOutTmp;
reg [15:0]ResultOutTmp_l,ResultOutTmp_r;
always@(posedge Clk)begin
ResultOutTmp <= P*Angle_Tmp*10 + D*Gyro_Tmp;
if(ResultOutTmp>0)
ResultOutTmp_l<=ResultOutTmp;
else
ResultOutTmp_r<=~ResultOutTmp+1;
end
assign ResultOut_l=(ResultOutTmp_l>7500)?7500:ResultOutTmp_l;
assign ResultOut_r=(ResultOutTmp_r>7500)?7500:ResultOutTmp_r;
endmodule
|
|
module BarrelShifter(
input wire [7:0] input_data,
input wire [1:0] shift_amount,
input wire [3:0] shift_type,
output reg [7:0] output_data
);
always @(*)
begin
case(shift_type)
2'b00: // Logical Shift Left
output_data = input_data << shift_amount;
2'b01: // Logical Shift Right
output_data = input_data >> shift_amount;
2'b10: // Arithmetic Shift Right
if(input_data[7] == 1)
output_data = {input_data[7], input_data[7]} >> shift_amount;
else
output_data = input_data >> shift_amount;
2'b11: // Arithmetic Shift Left
if(input_data[7] == 1)
output_data = {input_data[7], input_data[7]} << shift_amount;
else
output_data = input_data << shift_amount;
default: // No shift
output_data = input_data;
endcase
end
endmodule
|
|
module ConvertBinaryToMantissa (
en,
isFloat,
isExponentOdd,
in,
mantissa,
isDone
);
parameter DOUBLE_PRECISION_ODD = 11'd52,
SINGLE_PRECISION_ODD = 8'd23,
DOUBLE_PRECISION_EVEN = 11'd53,
SINGLE_PRECISION_EVEN = 8'd24,
MANTISSA_SIZE = 6'd52,
BINARY_SIZE = 8'd106;
input en, isFloat, isExponentOdd;
output reg isDone;
input [53-1:0] in;
output [MANTISSA_SIZE-1:0] mantissa;
reg [MANTISSA_SIZE-1:0] mantissa;
always @ (*) begin
if (en) begin
if (isFloat) begin
if (isExponentOdd) begin
mantissa = in[22:0];
end
else begin
mantissa = in[22:0];
end
isDone = 1;
end
else begin
if (isExponentOdd) begin
mantissa = in[51:0];
end
else begin
mantissa = in[51:0];
end
isDone = 1;
end
end
else begin
mantissa = 0;
isDone = 0;
end
end
endmodule // ConvertMantissa
|
|
module HA_Dataflow(a,b,sum,cout);
input a,b;
output sum,cout;
assign #5 sum = a^b;
assign #5 cout = a & b;
endmodule
|
|
// This program was cloned from: https://github.com/chipsalliance/aib-phy-hardware
// License: Apache License 2.0
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2019 Intel Corporation.
module io_min_interp_mux (
input [3:0] phy_clk_phs, // half of 8 phase 1.6GHz clock
input svcc, // for soft tie high
output c_out // 1 of the 3 output phases
);
`ifdef TIMESCALE_EN
timeunit 1ps;
timeprecision 1ps;
`endif
parameter INVERTER_DELAY = 15;
parameter FINGER_DELAY = 45;
wire out_vl;
//--------------------------------------------------------------------------------------------------
// Finger Mux delay for phs[0]
//--------------------------------------------------------------------------------------------------
assign #FINGER_DELAY out_vl = phy_clk_phs[1];
assign #(2 * INVERTER_DELAY) c_out = out_vl;
endmodule
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/06/2023 08:39:44 PM
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(
input [2:0] op,
input [7:0] a,
input [7:0] b,
input shift_logical,
input [2:0] shift_imm,
output [7:0] r,
output [3:0] flags
);
wire [8:0] a_plus_b = a + b;
wire [8:0] a_sub_b = a - b;
wire [7:0] shift_right = shift_logical
? a >> shift_imm
: $signed($signed(a) >>> shift_imm);
wire [8:0] shift_left = a << shift_imm;
reg [7:0] result;
always @(*) begin
case (op)
3'b000: result <= a&b;
3'b001: result <= a|b;
3'b010: result <= a^b;
3'b011: result <= a_plus_b[7:0];
3'b100: result <= a_sub_b[7:0];
3'b101: result <= a_sub_b[7:0];
3'b110: result <= shift_right;
3'b111: result <= shift_left[7:0];
endcase
end
// FLAGS
reg c;
wire n = result[7];
reg v;
wire z = result == 0;
always @(*) begin
case (op)
3'b000: begin c <= 0; v <= 0; end
3'b001: begin c <= 0; v <= 0; end
3'b010: begin c <= 0; v <= 0; end
3'b011: begin c <= a_plus_b[8]; v <= a[7] == b[7] && a[7] != result[7]; end
3'b100: begin c <= a_sub_b[8]; v <= a[7] != b[7] && a[7] != result[7]; end
3'b101: begin c <= a_sub_b[8]; v <= a[7] != b[7] && a[7] != result[7]; end
3'b110: begin c <= 0; v <= 0; end
3'b111: begin c <= shift_left[8]; v <= 0; end
endcase
end
// Use the ALU result unless we are doing comparisons
assign r = op != 'b101 ? result : a;
assign flags = ({ c, n, v, z });
endmodule
|
|
`timescale 1ps / 1ps
/*****************************************************************************
Verilog RTL Description
Configured at: 16:16:05 CST (+0800), Tuesday 04 May 2021
Configured on: ws32
Configured by: m109061634 (m109061634)
Created by: Stratus DpOpt 2019.1.01
*******************************************************************************/
module DC_Filter_Mul_8Ux4U_12U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [3:0] in1;
output [11:0] out1;
wire [11:0] asc001;
assign asc001 =
+(in2 * in1);
assign out1 = asc001;
endmodule
/* CADENCE ubD4SwA= : u9/ySgnWtBlWxVPRXgAZ4Og= ** DO NOT EDIT THIS LINE ******/
|
|
module greyscale(
input [7:0] in_R,
input [7:0] in_G,
input [7:0] in_B,
output [7:0] grey
);
// 16 bit due to multiplication overflow
wire [15:0] intermediate;
// luminance formula (NTSC formula): greyscale = 0.299*R + 0.587*G + 0.114*B)
// R: 77/256 = 0.3
// G: 150/256 = 0.5859375
// B: 29/256 = 0.11328125
assign intermediate = (in_R*77) + (in_G*150) + (in_B*29);
// 8 bit value by dividing by 256 = shaving off 8 bits.
// 2^8 = 256
// >> 8 = /256
assign grey = intermediate[15:8];
endmodule
|
|
module uart_out (
input clk,
input [7:0]data,
input flag_start,
output reg out,
output reg flag_busy
);
wire [9:0]res = {1'b1, data, 1'b0};
reg [3:0]bit_num = 4'h0;
always @(posedge clk) begin
out <= res[bit_num];
if((flag_start == 1) && (flag_busy == 0)) begin
bit_num <= 0;
flag_busy <= 1;
end
if((bit_num == 9) && (flag_busy == 1))
flag_busy <= 0;
else if(flag_busy == 1)
bit_num <= bit_num + 1;
end
endmodule
|
|
// SPDX-License-Identifier: Apache-2.0
// Copyright (C) 2019 Intel Corporation.
// Library - aibnd_lib, Cell - aibnd_rambit_buf, View - schematic
// LAST TIME SAVED: Apr 19 23:56:59 2015
// NETLIST TIME: May 12 17:53:11 2015
// `timescale 1ns / 1ns
module aibnd_rambit_buf ( sig_out, sig_in, vccl_aibnd, vssl_aibnd );
output sig_out;
input sig_in, vccl_aibnd, vssl_aibnd;
wire sig_out, sig_in; // Conversion Sript Generated
// specify
// specparam CDS_LIBNAME = "aibnd_lib";
// specparam CDS_CELLNAME = "aibnd_rambit_buf";
// specparam CDS_VIEWNAME = "schematic";
// endspecify
assign sig_out = sig_in;
endmodule
|
|
module mux2(select,a,b,y);
input select;
input[31:0] a,b;
output reg [31:0] y;
always@(select,a,b) begin
case(select)
1'b0:y=a;
1'b1:y=b;
endcase
end
endmodule
module mux2A(select,a,b,y);
input select;
input[4:0] a,b;
output reg [4:0] y;
always@(select,a,b) begin
case(select)
1'b0:y=a;
1'b1:y=b;
endcase
end
endmodule
|
|
module wideexpr_00419(ctrl, u0, u1, u2, u3, u4, u5, u6, u7, s0, s1, s2, s3, s4, s5, s6, s7, y);
input [7:0] ctrl;
input [0:0] u0;
input [1:0] u1;
input [2:0] u2;
input [3:0] u3;
input [4:0] u4;
input [5:0] u5;
input [6:0] u6;
input [7:0] u7;
input signed [0:0] s0;
input signed [1:0] s1;
input signed [2:0] s2;
input signed [3:0] s3;
input signed [4:0] s4;
input signed [5:0] s5;
input signed [6:0] s6;
input signed [7:0] s7;
output [127:0] y;
wire [15:0] y0;
wire [15:0] y1;
wire [15:0] y2;
wire [15:0] y3;
wire [15:0] y4;
wire [15:0] y5;
wire [15:0] y6;
wire [15:0] y7;
assign y = {y0,y1,y2,y3,y4,y5,y6,y7};
assign y0 = {($unsigned($signed({4{(3'sb010)&(4'sb0001)}})))^({2{(ctrl[7]?s6:(ctrl[0]?(ctrl[3]?4'sb0000:6'sb000110):s2))}})};
assign y1 = s4;
assign y2 = 3'b100;
assign y3 = $signed(s6);
assign y4 = ($signed({s7,$signed(2'sb00),{4{($signed(4'b1000))>>((ctrl[1]?2'sb11:s3))}}}))>((+((($unsigned(+($signed(2'sb01))))+({3{{-((ctrl[4]?u2:6'b010000))}}}))>=(s2)))^~($signed($signed((1'sb0)>>>((ctrl[1]?5'sb00111:(3'sb010)^(s4)))))));
assign y5 = ({3{3'sb011}})>>>(3'sb011);
assign y6 = s7;
assign y7 = {1{(s5)<<<($signed(5'sb01011))}};
endmodule
|
|
module EHR_6 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_6;
end
end
endmodule
|
|
// Guia 10 - 01
// Paulo Henrique de Almeida Amorim - 412765
// constant definitions
`define found 1
`define notfound 0
// FSM by Mealy
module exercicio01_seq010_mealy ( y, x, clk, reset );
output y;
input x;
input clk;
input reset;
reg y;
parameter // state identifiers
start = 2'b00,
id0 = 2'b01,
id01 = 2'b10;
reg [1:0] E1; // current state variables
reg [1:0] E2; // next state logic output
// next state logic
always @( x or E1 )
begin
y = `notfound;
case ( E1 )
start:
if ( x )
E2 = id0;
else
E2 = start;
id0:
if ( x )
E2 = id0;
else
E2 = id01;
id01:
if ( x )
begin
E2 = id0;
y = `found;
end
else
begin
E2 = start;
y = `notfound;
end
default: // undefined state
E2 = 2'bxx;
endcase
end // always at signal or state changing
// state variables
always @( posedge clk or negedge reset )
begin
if ( reset )
E1 = E2; // updates current state
else
E1 = 0; // reset
end // always at signal changing
endmodule // exercicio01_seq010_mealy
module Exercicio1;
reg clk, reset, x;
wire m1;
exercicio01_seq010_mealy M1( m1, x, clk, reset );
initial
begin
$display("Guia 10 - Paulo Henrique de Almeida Amorim - 412765");
$display("\\nTime\\tX Seq 010" );
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#10 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 0;
#5 $finish;
end // initial
always
#5 clk = ~clk;
always @( posedge clk )
begin
$display ( "%4d \\t%b\\t%b", $time, x, m1);
end // always at positive edge clocking changing
endmodule
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22.02.2022 17:03:16
// Design Name:
// Module Name: SpiControll
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpiControll(
input clock,
input [7:0] data_in,
input reset,
input load_data,
output reg done_send,
output spi_clk,// 10 MHz max
output reg spi_data
);
reg [1:0] state;
reg [2:0] counter=0;
reg [2:0] data_count;
reg [7:0] shiftreg;
reg clock_10;
reg ce;
assign spi_clk=(ce==1)?clock_10:1'b1;
always@(posedge clock)
begin
if(counter!=4)
begin
counter <= counter+1;
end
else
counter <= 0;
end
initial clock_10<=0;
always@(posedge clock)
begin
if(counter==4)
begin
clock_10<=~clock_10;
end
end
parameter IDLE= 'd0;
parameter SEND= 'd1;
parameter DONE= 'd2;
always@(negedge clock_10)
begin
if(reset)
begin
state<=IDLE;
data_count<=0;
done_send<=1'b0;
ce<=10;
spi_data<=1'b0;
end
else
begin
case(state)
IDLE:begin
if(load_data)
begin
shiftreg<=data_in;
data_count<=0;
state<=SEND;
end
end
SEND:begin
spi_data <= shiftreg[7];
shiftreg <= {shiftreg[6:0],1'b0};
ce<=1;
if(data_count!=7)
begin
data_count<=data_count+1;
end
else
begin
state<=DONE;
end
end
DONE:begin
done_send<=1'b1;
ce<=0;
if(!load_data)
begin
done_send<=1'b0;
state<=IDLE;
end
end
endcase
end
end
endmodule
|
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:33:11 06/01/2013
// Design Name:
// Module Name: mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module boothmul(result1,q);
input [9:0] q;
output [31:0] result1;
parameter N=34;
reg [N-1:0] m = 34'b01_0110_1100_0001_0110_1100_0001_0110_1100;
wire [2*N-1:0] resultb;
wire [2*N-1:0] resultc;
reg [N-1:0] q_reg;
reg [2*N:0] result;
reg q_1 = 1'b0;
reg [N-1:0] a;
integer i;
assign resultb = result[2*N:1];
assign resultc = resultb>>9;
assign result1 = resultc[31:0];
always @ (m or q)
begin
a=34'b0;
q_reg={24'b0,q};
q_1=1'b0;
result={a,q_reg,q_1};
for(i=0;i<N;i=i+1)
begin
case(result[1:0])
2'b01: a=a+m;
2'b10: a=a-m;
default:;
endcase
result={a,q_reg,q_1};
result={result[2*N],result[2*N:1]};
a=result[2*N:N+1];
q_reg=result[N:1];
q_1=result[0];
end
end
endmodule
|
|
module FixedPointAdder (
input signed [15:0] num1, // 16-bit signed fixed-point number 1
input signed [15:0] num2, // 16-bit signed fixed-point number 2
output reg signed [16:0] result // 17-bit signed fixed-point result
);
reg signed [16:0] result_temp;
always @(*) begin
result_temp = num1 + num2;
result = result_temp >> 1; // Shift right by 1 to account for the binary point
end
endmodule
|
|
module unsigned_multiplier (
input [7:0] A,
input [7:0] B,
output reg [15:0] C
);
reg [15:0] temp;
integer i;
always @(*) begin
temp = 16'b0;
for(i = 0; i < 8; i = i + 1) begin
if(B[i] == 1) begin
temp = temp + (A << i);
end
end
C = temp;
end
endmodule
|
|
module comparator (
input [7:0] num1,
input [7:0] num2,
output equal_flag,
output greater_flag,
output less_flag
);
wire [7:0] xor_output;
wire [7:0] and_output;
assign xor_output = num1 ^ num2;
assign and_output = num1 & num2;
assign equal_flag = !| xor_output;
assign greater_flag = & and_output;
assign less_flag = (& ~num1) & ~num2;
endmodule
|
|
module shift2(input [63:0] data1 , output [63:0] data2);
wire [1:0] a = 2'b00;
assign data2 = {data1[63:0] , a};
endmodule
|
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