repo_name
stringlengths 6
79
| path
stringlengths 4
249
| size
int64 1.02k
768k
| content
stringlengths 15
207k
| license
stringclasses 14
values |
|---|---|---|---|---|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/uart_transmitter.v
| 1,700 |
module MODULE1 # (
parameter VAR7 = 100000000,
parameter VAR2 = 115200
) (
input clk,
output VAR1,
input VAR6,
input [7:0] VAR5,
output VAR3
);
localparam [15:0] VAR4 = (VAR7 / VAR2) - 1;
reg [15:0] VAR9 = 16'd0;
reg [9:0] state = 10'd1023, VAR8 = 10'd1023;
assign VAR1 = VAR8[0];
assign VAR3 = state[0] & ~VAR6;
always @ (posedge clk)
begin
VAR9 <= VAR9 + 16'd1;
if (VAR9 >= VAR4)
begin
VAR9 <= 16'd0;
state <= {1'b1, state[9:1]};
VAR8 <= {1'b1, VAR8[9:1]};
end
if (VAR6 && state[0])
begin
VAR9 <= 16'd0;
state <= 10'd0;
VAR8 <= {1'b1, VAR5, 1'b0};
end
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.pp.symbol.v
| 1,258 |
module MODULE1 (
input VAR2 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule
|
apache-2.0
|
versaloon/vsf
|
vsf/old/example/vsfusbh/proj/Keil_v5_CMEM7/fpga/src/pll_v1.v
| 3,995 |
module MODULE1(
VAR25,
VAR44,
VAR23,
VAR30
);
input VAR25;
output VAR44;
output VAR23;
output VAR30;
VAR20 #(
.VAR56 (1'b0),
.VAR49 (4'b0000),
.VAR32 ("VAR41"),
.VAR31 (2'b01),
.VAR7 (2'b00),
.VAR45 (8'b00111011),
.VAR5 (8'b00000000),
.VAR6 (8'b00000101),
.VAR16 (8'b01100011),
.VAR47 (8'b00000111),
.VAR62 (8'b00000010),
.VAR17 (3'b000),
.VAR15 (1'b1),
.VAR50 (1'b1),
.VAR24 (1'b0),
.VAR59 (1'b0),
.VAR26 (1'b0),
.VAR22 (1'b0),
.VAR33 (1'b0),
.VAR42 (1'b0),
.VAR2 (8'b00000000),
.VAR60 (8'b00000000),
.VAR10 (8'b00000000),
.VAR69 (8'b00000000),
.VAR13 (3'b000),
.VAR64 (3'b000),
.VAR21 (3'b000),
.VAR53 (3'b000),
.VAR29 (1'b0),
.VAR55 (1'b0),
.VAR37 (1'b0),
.VAR39 (2'b00),
.VAR70 (2'b01),
.VAR3 (2'b11),
.VAR28 (3'b100),
.VAR46 (2'b11),
.VAR34 (2'b11),
.VAR9 (1'b0),
.VAR66 (1'b0),
.VAR61 (1'b0),
.VAR1 (1'b0),
.VAR63 (1'b0),
.VAR14 (1'b0),
.VAR38 (1'b0),
.VAR67 (1'b0),
.VAR57 (1'b0),
.VAR71 (1'b0),
.VAR36 (1'b0),
.VAR43 (1'b0),
.VAR11 (2'b01),
.VAR35 (2'b00),
.VAR52 (8'b11000111),
.VAR40 (2'b00),
.VAR54 (6'b000000),
.VAR72 (3'b000),
.VAR51 (5'b00000)
)
VAR19 (
.VAR25 (VAR25),
.VAR12 (),
.VAR18 (),
.VAR68 (),
.VAR4 (),
.VAR48 (),
.VAR65 (),
.VAR58 (),
.VAR44 (VAR44),
.VAR23 (VAR23),
.VAR8 (),
.VAR27 (),
.VAR30 (VAR30)
);
endmodule
|
gpl-3.0
|
LSaldyt/qnp
|
output/vs/var21_multi.v
| 1,618 |
module MODULE1 (VAR5, VAR9, VAR21, VAR1, VAR20, VAR11, VAR25, VAR27, VAR13, VAR17, VAR8, VAR12, VAR23, VAR14, VAR26, VAR24, VAR3, VAR6, VAR4, VAR15, VAR22, valid);
input VAR5, VAR9, VAR21, VAR1, VAR20, VAR11, VAR25, VAR27, VAR13, VAR17, VAR8, VAR12, VAR23, VAR14, VAR26, VAR24, VAR3, VAR6, VAR4, VAR15, VAR22;
output valid;
wire [8:0] VAR19 = 9'd120;
wire [8:0] VAR2 = 9'd60;
wire [8:0] VAR10 = 9'd60;
wire [8:0] VAR18 =
VAR5 * 9'd4
+ VAR9 * 9'd8
+ VAR21 * 9'd0
+ VAR1 * 9'd20
+ VAR20 * 9'd10
+ VAR11 * 9'd12
+ VAR25 * 9'd18
+ VAR27 * 9'd14
+ VAR13 * 9'd6
+ VAR17 * 9'd15
+ VAR8 * 9'd30
+ VAR12 * 9'd8
+ VAR23 * 9'd16
+ VAR14 * 9'd18
+ VAR26 * 9'd18
+ VAR24 * 9'd14
+ VAR3 * 9'd7
+ VAR6 * 9'd7
+ VAR4 * 9'd29
+ VAR15 * 9'd23
+ VAR22 * 9'd24;
wire [8:0] VAR16 =
VAR5 * 9'd28
+ VAR9 * 9'd8
+ VAR21 * 9'd27
+ VAR1 * 9'd18
+ VAR20 * 9'd27
+ VAR11 * 9'd28
+ VAR25 * 9'd6
+ VAR27 * 9'd1
+ VAR13 * 9'd20
+ VAR17 * 9'd0
+ VAR8 * 9'd5
+ VAR12 * 9'd13
+ VAR23 * 9'd8
+ VAR14 * 9'd14
+ VAR26 * 9'd22
+ VAR24 * 9'd12
+ VAR3 * 9'd23
+ VAR6 * 9'd26
+ VAR4 * 9'd1
+ VAR15 * 9'd22
+ VAR22 * 9'd26;
wire [8:0] VAR7 =
VAR5 * 9'd27
+ VAR9 * 9'd27
+ VAR21 * 9'd4
+ VAR1 * 9'd4
+ VAR20 * 9'd0
+ VAR11 * 9'd24
+ VAR25 * 9'd4
+ VAR27 * 9'd20
+ VAR13 * 9'd12
+ VAR17 * 9'd15
+ VAR8 * 9'd5
+ VAR12 * 9'd2
+ VAR23 * 9'd9
+ VAR14 * 9'd28
+ VAR26 * 9'd19
+ VAR24 * 9'd18
+ VAR3 * 9'd30
+ VAR6 * 9'd12
+ VAR4 * 9'd28
+ VAR15 * 9'd13
+ VAR22 * 9'd18;
assign valid = ((VAR18 >= VAR19) && (VAR16 <= VAR2) && (VAR7 <= VAR10));
endmodule
|
mit
|
scalable-networks/ext
|
uhd/fpga/usrp2/sdr_lib/hb/mac.v
| 2,497 |
module MODULE1 (input VAR7, input reset, input enable, input VAR4,
input signed [15:0] VAR1, input signed [15:0] VAR2,
input [7:0] VAR8, output [15:0] VAR5 );
reg signed [30:0] VAR9;
reg signed [39:0] VAR10;
reg signed [15:0] VAR3;
reg VAR6;
always @(posedge VAR7)
VAR6 <= enable;
always @(posedge VAR7)
if(reset | VAR4)
VAR10 <= 40'd0;
else if(VAR6)
VAR10 <= VAR10 + {{9{VAR9[30]}},VAR9};
always @(posedge VAR7)
VAR9 <= VAR1*VAR2;
always @* case(VAR8)
8'd6 : VAR3 <= VAR10[33:18];
8'd7 : VAR3 <= VAR10[32:17];
8'd8 : VAR3 <= VAR10[31:16];
8'd9 : VAR3 <= VAR10[30:15];
8'd10 : VAR3 <= VAR10[29:14];
8'd11 : VAR3 <= VAR10[28:13];
default : VAR3 <= VAR10[15:0];
endcase
assign VAR5 = VAR10[15:0];
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlrtn/sky130_fd_sc_ls__dlrtn.symbol.v
| 1,416 |
module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR8,
input VAR3
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
lneuhaus/pyrpl
|
pyrpl/fpga/rtl/red_pitaya_compressor_block.v
| 4,769 |
module MODULE1
parameter VAR7 = 4, parameter VAR14 = 14, parameter VAR4 = 10 )
(
input VAR16,
input VAR25 ,
input [VAR7:0] VAR27,
input VAR5,
input VAR17,
input signed [VAR14-1:0] VAR19,
input signed [VAR14-1:0] VAR6,
output signed [VAR14-1:0] VAR15
);
reg signed [VAR14+VAR18-1:0] VAR26;
reg signed [VAR14+VAR18-1:0] VAR22; wire signed [VAR14+VAR18-1:0] VAR28;
wire signed [VAR14-1:0] VAR21;
wire VAR11;
assign VAR21 = VAR26[VAR18+VAR14-1:VAR18];
assign VAR28 = VAR22<<VAR27;
always @(posedge VAR16) begin
if (VAR25 == 1'b0) begin
VAR26 <= {VAR18+VAR14{1'b0}};
VAR22 <= {VAR18+VAR14{1'b0}};
end
else begin
VAR22 <= VAR19 - VAR21;
VAR26 <= VAR26 + VAR28;
end
end
assign VAR15 = (VAR5 == 1'b0) ? VAR19 : ( (VAR17==1'b0) ? VAR21 : VAR22);
endmodule
localparam VAR23 = VAR1+16;
reg [15+VAR20-1: 0] VAR3 ;
wire [VAR23 : 0] VAR12 ;
reg [VAR23-1: 0] VAR10 ;
wire [VAR23-VAR1-1: 0] VAR2 ;
always @(posedge VAR16) begin
if (VAR25 == 1'b0) begin
VAR3 <= {15+VAR20{1'b0}};
VAR10 <= {VAR23{1'b0}};
end
else begin
VAR3 <= (VAR9) * (VAR24) ;
if (VAR13)
VAR10 <= { {VAR23-16-VAR1{VAR8[16-1]}},VAR8[16-1:0],{VAR1{1'b0}}};
end
else if (VAR12[VAR23+1-1:VAR23+1-2] == 2'b01) VAR10 <= {1'b0,{VAR23-1{1'b1}}};
end
else if (VAR12[VAR23+1-1:VAR23+1-2] == 2'b10) VAR10 <= {1'b1,{VAR23-1{1'b0}}};
else
VAR10 <= VAR12[VAR23-1:0]; end
end
assign VAR12 = (VAR3) + (VAR10) ;
assign VAR2 = (VAR10[VAR23-1:VAR1]) ;
|
mit
|
jotego/jt12
|
hdl/jt12_eg_comb.v
| 4,080 |
module MODULE1(
input VAR10,
input VAR17,
input [2:0] VAR57,
input [9:0] VAR12,
input [4:0] VAR18, input [4:0] VAR37, input [4:0] VAR47, input [3:0] VAR36,
input [3:0] VAR43, input VAR39,
input [2:0] VAR20,
input VAR25,
output VAR19,
output [4:0] VAR23,
output [2:0] VAR35,
output VAR34,
input VAR50,
input [ 4:0] VAR7,
input [ 4:0] VAR29,
input [14:0] VAR8,
input VAR26,
input [ 1:0] VAR55,
output VAR38,
output VAR21,
output [5:0] VAR41,
output VAR54,
input VAR1,
input VAR14,
input [ 5:1] VAR22,
input VAR48,
input [ 9:0] VAR33,
output [9:0] VAR28,
input VAR5,
input [ 6:0] VAR31,
input VAR9,
input [ 1:0] VAR45,
input [ 6:0] VAR27,
input [ 9:0] VAR4,
input VAR16,
output [9:0] VAR44
);
VAR30 VAR3(
.VAR10 ( VAR10 ),
.VAR17 ( VAR17 ),
.VAR57 ( VAR57 ),
.VAR56 ( VAR12 ),
.VAR18 ( VAR18 ), .VAR37 ( VAR37 ), .VAR47 ( VAR47 ), .VAR36 ( VAR36 ),
.VAR43 ( VAR43 ), .VAR39 ( VAR39 ),
.VAR20 ( VAR20 ),
.VAR25 ( VAR25 ),
.VAR19 ( VAR19 ),
.VAR23 ( VAR23 ),
.VAR35 ( VAR35 ),
.VAR34 ( VAR34 )
);
VAR15 VAR2(
.VAR46 ( VAR50 ),
.VAR23 ( VAR7 ),
.VAR29 ( VAR29 ),
.VAR8 ( VAR8 ),
.VAR26 ( VAR26 ),
.VAR55 ( VAR55 ),
.VAR38 ( VAR38 ),
.VAR21 ( VAR21 ),
.VAR49 ( VAR41 ),
.VAR52 ( VAR54 )
);
wire [9:0] VAR12, VAR51;
VAR13 VAR11(
.VAR46 ( VAR1 ),
.VAR21 ( VAR14 ),
.VAR49 ( VAR22 ),
.VAR39 ( VAR48 ),
.VAR12 ( VAR33 ),
.VAR53( VAR28 ),
.VAR52 ( VAR5 )
);
VAR32 VAR6(
.VAR31 ( VAR31 ),
.VAR9 ( VAR9 ),
.VAR45 ( VAR45 ),
.VAR27 ( VAR27 ),
.VAR40 ( VAR16 ),
.VAR24 ( VAR4 ),
.VAR42 ( VAR44 )
);
endmodule MODULE1
|
gpl-3.0
|
hhuang25/uwaterloo_ece224
|
Lab1/pio_period.v
| 2,084 |
module MODULE1 (
address,
VAR1,
clk,
VAR6,
VAR5,
VAR3,
VAR4,
VAR8
)
;
output [ 3: 0] VAR4;
output [ 3: 0] VAR8;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR6;
input VAR5;
input [ 3: 0] VAR3;
wire VAR9;
reg [ 3: 0] VAR2;
wire [ 3: 0] VAR4;
wire [ 3: 0] VAR7;
wire [ 3: 0] VAR8;
assign VAR9 = 1;
assign VAR7 = {4 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR6)
begin
if (VAR6 == 0)
VAR2 <= 0;
end
else if (VAR1 && ~VAR5 && (address == 0))
VAR2 <= VAR3[3 : 0];
end
assign VAR8 = VAR7;
assign VAR4 = VAR2;
endmodule
|
mit
|
ECE492-Team5/Platform
|
soc-platform-quartusii/hps_fpga_system.v
| 14,278 |
module MODULE1(
output VAR154,
output VAR132,
output VAR51,
input VAR66,
inout [15:0] VAR120,
inout VAR80,
input VAR96,
input VAR32,
input VAR29,
inout [35:0] VAR61,
inout [35:0] VAR67,
inout VAR135,
output [14:0] VAR139,
output [2:0] VAR116,
output VAR75,
output VAR99,
output VAR3,
output VAR30,
output VAR118,
output [3:0] VAR78,
inout [31:0] VAR7,
inout [3:0] VAR26,
inout [3:0] VAR9,
output VAR93,
output VAR2,
output VAR21,
input VAR81,
output VAR14,
output VAR40,
inout VAR82,
output VAR143,
inout VAR8,
input VAR76,
input [3:0] VAR72,
input VAR122,
output [3:0] VAR147,
output VAR84,
inout VAR106,
inout VAR158,
inout VAR64,
inout VAR31,
inout VAR102,
inout VAR113,
inout VAR126,
inout VAR145,
output VAR36,
inout VAR19,
inout [3:0] VAR133,
output VAR152,
input VAR117,
output VAR109,
inout VAR144,
input VAR54,
output VAR25,
input VAR124,
inout [7:0] VAR150,
input VAR131,
input VAR13,
output VAR52,
input [1:0] VAR56,
output [7:0] VAR33,
input [3:0] VAR5
);
wire [1:0] VAR24;
wire [7:0] VAR100;
wire VAR68;
wire [2:0] VAR127;
wire VAR65;
wire VAR34;
wire VAR35;
wire [27:0] VAR85;
assign VAR85 = {{13{1'b0}},VAR5, VAR100, VAR24};
VAR91 VAR48 (
.VAR87 (VAR96 ), .VAR46 (1'b1 ), .VAR92 ( VAR139), .VAR57 ( VAR116), .VAR79 ( VAR30), .VAR105 ( VAR3), .VAR10 ( VAR99), .VAR43 ( VAR118), .VAR108 ( VAR2), .VAR134 ( VAR75), .VAR114 ( VAR14), .VAR128 ( VAR21), .VAR28 ( VAR7), .VAR138 ( VAR9), .VAR90 ( VAR26), .VAR45 ( VAR93), .VAR60 ( VAR78), .VAR95 ( VAR81), .VAR146 ( VAR40), .VAR142 ( VAR147[0] ), .VAR104 ( VAR147[1] ), .VAR112 ( VAR147[2] ), .VAR12 ( VAR147[3] ), .VAR101 ( VAR72[0] ), .VAR156 ( VAR8 ), .VAR121 ( VAR143 ), .VAR59 ( VAR122), .VAR107 ( VAR84), .VAR125 ( VAR76), .VAR103 ( VAR72[1] ), .VAR123 ( VAR72[2] ), .VAR20 ( VAR72[3] ), .VAR47 ( VAR19 ), .VAR41 ( VAR133[0] ), .VAR111 ( VAR133[1] ), .VAR6 ( VAR36 ), .VAR149 ( VAR133[2] ), .VAR88 ( VAR133[3] ), .VAR16 ( VAR150[0] ), .VAR37 ( VAR150[1] ), .VAR137 ( VAR150[2] ), .VAR155 ( VAR150[3] ), .VAR42 ( VAR150[4] ), .VAR62 ( VAR150[5] ), .VAR141 ( VAR150[6] ), .VAR160 ( VAR150[7] ), .VAR73 ( VAR124 ), .VAR17 ( VAR52 ), .VAR38 ( VAR131 ), .VAR151 ( VAR13 ), .VAR157 ( VAR152 ), .VAR129 ( VAR109 ), .VAR153 ( VAR117 ), .VAR98 ( VAR144 ), .VAR18 ( VAR54 ), .VAR161 ( VAR25 ), .VAR148 ( VAR64 ), .VAR89 ( VAR158 ), .VAR130 ( VAR102 ), .VAR162 ( VAR31 ), .VAR39 ( VAR135 ), .VAR110 ( VAR82 ), .VAR97 ( VAR145 ), .VAR115 ( VAR126 ), .VAR94 ( VAR113 ), .VAR136 ( VAR106 ),
.VAR1 (VAR85), .VAR71 (VAR68), .VAR50 (~VAR34), .VAR63 (~VAR35), .VAR11 (~VAR65),
.VAR77 (VAR33),
.VAR74 (VAR154), .VAR119 (VAR132), .VAR27 (VAR51), .VAR15 (VAR66) );
VAR44 VAR22 (
.VAR55 (VAR96),
.VAR70 (VAR127)
);
VAR23 VAR140 (
.clk (VAR96),
.VAR83 (VAR68),
.VAR53 (VAR127[0]),
.VAR49 (VAR65)
);
VAR23 VAR69 (
.clk (VAR96),
.VAR83 (VAR68),
.VAR53 (VAR127[1]),
.VAR49 (VAR34)
);
VAR23 VAR58 (
.clk (VAR96),
.VAR83 (VAR68),
.VAR53 (VAR127[2]),
.VAR49 (VAR35)
);
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.symbol.v
| 1,358 |
module MODULE1 (
input VAR4,
output VAR3
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule
|
apache-2.0
|
Raamakrishnan/MyProc
|
MyProc2/ID.v
| 2,386 |
module MODULE1 (
input wire clk, input wire VAR12,
input wire [VAR16 - 1:0] VAR14,
input wire [VAR16 - 3:0] VAR30,
output wire [VAR16 - 1:0] VAR11,
output wire [VAR16 - 3:0] VAR21,
output wire [VAR16 - 1:0] VAR13,
output wire [VAR16 - 1:0] VAR29,
output reg [VAR15 - 1:0] VAR6,
input wire [VAR16 - 1:0] VAR8,
output reg VAR20,
input wire VAR28,
output reg [VAR15 - 1:0] VAR5,
input wire [VAR16 - 1:0] VAR4,
output reg VAR19,
input wire VAR22,
input wire VAR23,
input wire VAR1
);
wire [5:0] VAR25;
wire [4:0] VAR27;
wire [4:0] VAR18;
wire [4:0] VAR7;
wire [4:0] VAR17;
wire [15:0] VAR24;
wire [25:0] VAR9;
reg [VAR16-1:0] VAR10;
reg [VAR16-1:0] VAR2;
assign VAR25 = VAR14[31:26];
assign VAR27 = VAR14[25:21];
assign VAR18 = VAR14[20:16];
assign VAR7 = VAR14[15:11];
assign VAR17 = VAR14[10:6];
assign VAR24 = VAR14[15:0];
assign VAR9 = VAR14[25:0];
assign VAR11 = (VAR23 === 1)?VAR11:((VAR1 === 1)?VAR26:VAR14);
assign VAR21 = (VAR23 === 1)?VAR21:((VAR1 === 1)?VAR26:VAR30);
assign VAR13 = (VAR20 == 1)? VAR8 : VAR9;
assign VAR29 = (VAR19 == 1)? VAR4 : VAR3(VAR24);
always @(VAR11 or VAR21) begin
VAR20 = 0;
VAR19 = 0;
case(VAR25)
VAR6 <= VAR18;
VAR20 <= 1;
VAR5 <= VAR7;
VAR19 <= 1;
end
VAR6 <= VAR18;
VAR20 <= 1;
end
VAR6 <= VAR27;
VAR20 <= 1;
end
VAR6 <= VAR27;
VAR20 <= 1;
VAR5 <= VAR18;
VAR19 <= 1;
end
end
end
end
endcase
end
always @(posedge VAR28) begin
end
always @(posedge VAR22) begin
end
function [VAR16-1:0] VAR3(
input [15:0] din);
begin
VAR3[VAR16-1:0] = {{(VAR16-16){din[15]}}, din};
end
endfunction
endmodule
|
mit
|
KorotkiyEugene/LAG_sv_syn_quartus
|
LAG_fifo.v
| 7,711 |
typedef struct packed
{
logic VAR17, VAR16, VAR31, VAR7;
} VAR30;
module MODULE2 (VAR6, VAR34, VAR13, VAR28, VAR5, clk, VAR33);
parameter VAR8 = 8;
input VAR6, VAR34;
output VAR30 VAR5;
input VAR14 VAR13;
output VAR14 VAR28;
input clk, VAR33;
logic VAR11, VAR4;
VAR14 VAR23, VAR15;
MODULE1 #(.VAR8(VAR8))
VAR27 (VAR6, VAR34, VAR13, VAR15, clk, VAR33);
assign VAR28 = VAR5.VAR16 ? '0 : VAR15;
MODULE3 #(.VAR8(VAR8))
VAR22(VAR6, VAR34, VAR5, clk, VAR33);
endmodule
module MODULE3 (VAR6, VAR34, VAR5, clk, VAR33);
input VAR6, VAR34;
output VAR30 VAR5;
input clk, VAR33;
parameter VAR8 = 8;
reg [VAR8:0] counter;
logic VAR9, VAR29;
VAR30 VAR3;
logic VAR32, VAR19, VAR24;
always@(posedge clk) begin
if (!VAR33) begin
counter<={{VAR8{1'b0}},1'b1};
VAR9<=1'b0;
VAR29<=1'b0;
end else begin
if (VAR32) begin
end
assert (counter!={1'b1,{VAR8{1'b0}}}) else
counter <= {counter[VAR8-1:0], 1'b0};
end else if (VAR19) begin
end
assert (counter!={{VAR8{1'b0}},1'b1}) else
counter <= {1'b0, counter[VAR8:1]};
end
assert (counter!=0) else
VAR9<=VAR6;
VAR29<=VAR34;
end
assert (VAR6!==1'VAR20) else
end
assert (VAR34!==1'VAR20) else
end
end
assign VAR32 = VAR9 && !VAR29;
assign VAR19 = VAR29 && !VAR9;
assign VAR24 = !(VAR32 || VAR19);
assign VAR5.VAR17 = (counter[VAR8] && !VAR19) || (counter[VAR8-1] && VAR32);
assign VAR5.VAR16 = (counter[0] && !VAR32) || (counter[1] && VAR19);
assign VAR5.VAR31 = (counter[VAR8-1:0] && VAR24) || (counter[VAR8] && VAR19) || (counter[VAR8-2] && VAR32);
assign VAR5.VAR7 = (counter[1] && VAR24) || (counter[0] && VAR32) || (counter[2] && VAR19);
endmodule
module MODULE1 (VAR6, VAR34, VAR13, VAR28, clk, VAR33);
parameter int unsigned VAR8 = 4;
input VAR6, VAR34;
input VAR14 VAR13;
output VAR14 VAR28;
input clk, VAR33;
logic unsigned [VAR8-1:0] VAR12, VAR1;
VAR14 VAR2[0:VAR8-1];
logic VAR10;
integer VAR18,VAR21;
always@(posedge clk) begin
end
assert (VAR8>=2) else ();
if (!VAR33) begin
VAR12<={{VAR8-1{1'b0}},1'b1};
VAR1<={{VAR8-1{1'b0}},1'b1};
end else begin
if (VAR6) begin
for (VAR18=0; VAR18<VAR8; VAR18++) begin
if (VAR1[VAR18]==1'b1) begin
VAR2[VAR18] <= VAR13;
end
end
end
if (VAR6) begin
VAR1 <= {VAR1[VAR8-2:0], VAR1[VAR8-1]};
end
if (VAR34) begin
VAR12 <= {VAR12[VAR8-2:0], VAR12[VAR8-1]};
end
end end
VAR25 begin
VAR28 = 'VAR26;
for (VAR21=0; VAR21<VAR8; VAR21++) begin
if (VAR12[VAR21]==1'b1) begin
VAR28 = VAR2[VAR21];
end
end
end
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/fa/sky130_fd_sc_hs__fa_4.v
| 2,151 |
module MODULE2 (
VAR8,
VAR4 ,
VAR2 ,
VAR7 ,
VAR3 ,
VAR6,
VAR9
);
output VAR8;
output VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR6;
input VAR9;
VAR1 VAR5 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8,
VAR4 ,
VAR2 ,
VAR7 ,
VAR3
);
output VAR8;
output VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR3 ;
supply1 VAR6;
supply0 VAR9;
VAR1 VAR5 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/o22ai/sky130_fd_sc_ls__o22ai.behavioral.v
| 1,615 |
module MODULE1 (
VAR10 ,
VAR3,
VAR6,
VAR5,
VAR2
);
output VAR10 ;
input VAR3;
input VAR6;
input VAR5;
input VAR2;
supply1 VAR8;
supply0 VAR16;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR14 ;
wire VAR11 ;
wire VAR4;
nor VAR13 (VAR14 , VAR5, VAR2 );
nor VAR7 (VAR11 , VAR3, VAR6 );
or VAR12 (VAR4, VAR11, VAR14);
buf VAR15 (VAR10 , VAR4 );
endmodule
|
apache-2.0
|
hakehuang/pycpld
|
ips/ip/uart8bit/data_deal.v
| 1,672 |
module MODULE1(
clk,
VAR3,
VAR5,
VAR1,
VAR2,
VAR8,
VAR7,
VAR9
);
input clk;
input VAR3;
input [7:0] VAR5;
input VAR1;
output [7:0] VAR2;
output VAR8;
input VAR7;
output VAR9;
reg [7:0] VAR4;
reg [3:0] VAR6;
reg VAR9;
reg [7:0] VAR2;
reg VAR8;
always @(posedge clk or negedge VAR3)begin
if(!VAR3)begin
VAR4 <= 8'h0;
VAR6 <= 4'h0;
VAR9 <= 1'h0;
end
else if(VAR6 == 4'h8) begin
VAR9 <= ((VAR4 == 8'd28)||(VAR4 == 8'd36)) ? 1'b1 : 1'b0;
end
else if(VAR6 < 4'h8)begin
VAR6 <= VAR1 ? VAR6 + 1'b1 : VAR6;
VAR4 <= VAR1 ? (VAR5 + VAR4) : VAR4;
end
else
VAR6 <= VAR6 ;
end
always @(posedge clk or negedge VAR3)begin
if(!VAR3)begin
VAR8 <= 1'b0;
VAR2 <= 'h0;
end
else begin
if(~VAR8 & VAR7) VAR8 <= 1'b1;
end
else VAR8 <= 1'b0;
VAR2 <= ~VAR8 & VAR7 ? VAR2 + 1'b1 : VAR2;
end
end
endmodule
|
mit
|
Obijuan/open-fpga-verilog-tutorial
|
tutorial/ICESTICK/T15-divisor/divM.v
| 1,281 |
module MODULE1(input wire VAR4, output wire VAR3);
parameter VAR2 = 12000000;
localparam VAR1 = VAR6(VAR2);
reg [VAR1-1:0] VAR5 = 0;
always @(posedge VAR4)
if (VAR5 == VAR2 - 1)
VAR5 <= 0;
else
VAR5 <= VAR5 + 1;
assign VAR3 = VAR5[VAR1-1];
endmodule
|
gpl-2.0
|
lokisz/openzcore
|
pippo-0.9/rtl/verilog/pippo_if.v
| 12,305 |
module MODULE1(
clk, rst,
VAR14, VAR25, VAR3,
VAR15, VAR28, VAR20, VAR18,
VAR10, VAR13, VAR16, VAR12,
VAR33, VAR8, VAR31, VAR35, VAR21,
VAR5, VAR24, VAR27, VAR19,
VAR34
);
input clk;
input rst;
input [31:0] VAR20;
input VAR15;
input VAR28;
input [31:0] VAR18;
input VAR3;
output [31:0] VAR14;
output VAR25;
input [29:0] VAR10;
input VAR16;
input [31:0] VAR13; input VAR12;
input VAR33;
input VAR31;
input VAR35;
input VAR21;
output VAR8;
output VAR27;
output [31:0] VAR5;
output [29:0] VAR24;
output [29:0] VAR19;
output VAR34;
reg VAR27;
reg [31:0] VAR5;
reg [29:0] VAR24;
reg [29:0] VAR19;
reg VAR34;
reg [31:0] VAR30;
reg VAR17;
reg [31:0] VAR26;
reg [29:0] VAR22;
reg VAR1;
reg [31:0] VAR36;
wire VAR32;
wire [32:0] VAR4;
wire VAR23;
assign VAR14 = VAR36;
assign VAR25 = VAR32;
assign VAR8 = ~VAR15;
assign VAR4={(VAR36[31:2]+31'd1), 2'b00};
assign VAR11 = VAR35 & VAR15;
always @(VAR16 or VAR12 or VAR35 or VAR18 or
VAR11 or VAR10 or VAR13 or VAR36 or VAR4) begin
casex ({VAR16, VAR12, VAR35, VAR11}) 4'b0000: begin
VAR30 = VAR4[31:0];
end
4'b0100: begin
VAR30 = VAR13;
end
4'b1000: begin
VAR30 = {VAR10, 2'b00};
end
4'b0010: begin VAR30 = VAR36;
end
4'b0011: begin
VAR30 = VAR18; end
default: begin
VAR30 = VAR36;
end
endcase
end
always @(posedge clk or posedge rst) begin
if (rst)
VAR36 <= VAR9;
end
else if (VAR4[32] & !VAR21) VAR36 <= VAR9;
else if (VAR21 | (!VAR3) | VAR11)
VAR36 <= VAR30;
end
reg VAR37;
always @(posedge clk or posedge rst) begin
if (rst)
VAR37 <= 1'b0;
end
else if (VAR21)
VAR37 <= 1'b0;
else if (VAR4[32] & !VAR3)
VAR37 <= 1'b1;
end
assign VAR32 = !(VAR33 | VAR35 | (VAR4[32] & VAR37));
always @(VAR15 or VAR31 or VAR35 or VAR21 or
VAR17 or VAR26 or VAR22 or
VAR27 or VAR5 or VAR24 or
VAR20 or VAR18 or
VAR23 or VAR34) begin
casex ({VAR15, VAR31, VAR35, VAR21}) 4'b1000: begin VAR17 = 1'b1;
VAR26 = VAR20;
VAR22 = VAR18[31:2];
VAR1 = VAR23;
end
4'VAR29: begin VAR17 = 1'b0;
VAR26 = VAR2;
VAR22 = VAR24;
VAR1 = 1'b0;
end
4'VAR7: begin VAR17 = 1'b0;
VAR26 = VAR2;
VAR22 = VAR24;
VAR1 = 1'b0;
end
4'VAR6: begin VAR17 = VAR27;
VAR26 = VAR5;
VAR22 = VAR24;
VAR1 = VAR34;
end
default: begin VAR17 = 1'b0;
VAR26 = VAR2;
VAR22 = VAR24;
VAR1 = VAR23;
end
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
VAR27 <= 1'b0;
VAR5 <= VAR2;
VAR24 <= 30'd0;
VAR19 <= 30'd0;
VAR34 = 1'b0;
end
else begin
VAR27 <= VAR17;
VAR5 <= VAR26;
VAR24 <= VAR22;
VAR19 <= VAR4[31:2];
VAR34 = VAR1;
end
end
assign VAR23 = VAR28 & VAR15;
endmodule
|
gpl-2.0
|
toyoshim/mc6502
|
rtl/MC6502ExecutionController.v
| 11,992 |
module MODULE1(
clk,
VAR124,
VAR56,
VAR123,
VAR138,
VAR135,
VAR28,
VAR6,
VAR17,
VAR36,
VAR103,
VAR9,
VAR76,
VAR82,
VAR85,
VAR22,
VAR43,
VAR46,
VAR113,
VAR70,
VAR35,
VAR75,
VAR105,
VAR5,
VAR32,
VAR121,
VAR125,
VAR119,
VAR118,
VAR31,
VAR107,
VAR1,
VAR106,
VAR4,
VAR134,
VAR115,
VAR139,
VAR2,
VAR89,
VAR88,
VAR104,
VAR128,
VAR142,
VAR7,
VAR137,
VAR79,
VAR87);
input clk;
input VAR124;
input VAR56;
input VAR123;
input VAR138;
input VAR135;
input VAR28;
input VAR6;
input VAR17;
input VAR36;
input VAR103;
input VAR9;
input [4:0] VAR76;
input [7:0] VAR82;
input [1:0] VAR85;
output VAR22;
input [7:0] VAR43;
input [7:0] VAR46;
input [7:0] VAR113;
input [7:0] VAR70;
input [7:0] VAR35;
input VAR75;
input VAR105;
input VAR5;
input VAR32;
input VAR121;
output VAR125;
output VAR119;
output VAR118;
output VAR31;
output VAR107;
output VAR1;
output VAR106;
output VAR4;
output VAR134;
output VAR115;
output VAR139;
output VAR2;
output [7:0] VAR89;
output VAR88;
output VAR104;
output VAR128;
output VAR142;
output VAR7;
output VAR137;
output [7:0] VAR79;
output VAR87;
reg VAR97;
reg VAR41;
reg VAR90;
reg VAR69;
reg [7:0] VAR24;
reg [1:0] VAR45;
wire VAR62;
wire [2:0] VAR68;
wire VAR65;
wire VAR44;
wire VAR59;
wire VAR99;
wire [7:0] VAR91;
wire [7:0] wand;
wire [7:0] VAR11;
wire VAR39;
wire VAR58;
wire VAR60;
wire VAR114;
wire VAR8;
wire VAR14;
wire VAR116;
wire VAR81;
wire VAR102;
wire VAR57;
wire VAR10;
wire VAR120;
wire VAR38;
wire VAR30;
wire VAR72;
wire VAR136;
wire [7:0] VAR109;
wire [7:0] VAR54;
wire [7:0] VAR47;
wire VAR42;
wire VAR110;
wire VAR143;
wire VAR67;
wire VAR25;
wire VAR86;
wire [7:0] VAR95;
wire [7:0] VAR51;
wire VAR73;
wire VAR77;
wire VAR53;
wire [7:0] VAR74;
wire VAR29;
wire VAR34;
wire VAR132;
wire VAR78;
wire VAR71;
wire VAR140;
wire VAR130;
wire VAR84;
assign VAR22 = VAR97 | VAR41 | VAR36 | VAR136 |
(VAR103 & !VAR65) |
(VAR9 & !VAR140);
assign VAR125 = VAR72 ? VAR82[0] :
VAR39 ? VAR25 :
VAR60 ? VAR53 : VAR123;
assign VAR119 = VAR72 | VAR39 | VAR60 |
VAR123 | VAR56;
assign VAR118 = VAR72 ? VAR82[2] : VAR135;
assign VAR31 = VAR72 | VAR135 | VAR138;
assign VAR107 = VAR72 ? VAR82[6] :
VAR39 ? VAR86 :
VAR78 ? VAR132 : 1'b0;
assign VAR1 = VAR72 | VAR28 | VAR78 |
(VAR39 & (VAR68 != VAR37));
assign VAR106 = VAR72 ? VAR82[3] : VAR17;
assign VAR4 = VAR72 | VAR17 | VAR6;
assign VAR134 = VAR72 ? VAR82[7] :
VAR60 ? VAR73 :
VAR78 ? VAR29 :
(VAR39 | VAR136) ? VAR143 : VAR89[7];
assign VAR115 = VAR72 | VAR39 | VAR136 | VAR58;
assign VAR139 = VAR72 ? VAR82[1] :
VAR60 ? VAR77 :
VAR78 ? VAR34 :
(VAR39 | VAR136) ? VAR67 :
(VAR89 == 8'h00);
assign VAR2 = VAR72 | VAR39 | VAR136 | VAR58;
assign VAR89 = (VAR39 | VAR71 | VAR41) ? VAR47 :
((VAR14 | VAR116) & VAR36) ? VAR47 :
VAR57 ? VAR51 :
(VAR103 & VAR65) ? VAR82 :
!VAR103 ? VAR82 :
(VAR68 == VAR3) ? VAR91 :
(VAR68 == VAR127) ? wand :
(VAR68 == VAR108) ? VAR11 :
(VAR68 == VAR49) ? VAR82 : 8'VAR48;
assign VAR88 = (VAR36 & (VAR85 == VAR21)) |
(VAR103 & VAR59 & ((VAR68 == VAR3) |
(VAR68 == VAR127) |
(VAR68 == VAR108) |
(VAR68 == VAR55) |
(VAR68 == VAR13)));
assign VAR104 = VAR36 & (VAR85 == VAR93);
assign VAR128 = VAR36 & (VAR85 == VAR98);
assign VAR142 = VAR36 & (VAR85 == VAR126);
assign VAR7 = VAR71;
assign VAR137 = VAR41;
assign VAR79 = VAR90 ? VAR51 : VAR47;
assign VAR87 = VAR136;
assign VAR62 = VAR56 | VAR123 | VAR138 |
VAR135 | VAR28 | VAR6 |
VAR17;
assign VAR68 = VAR76[2:0];
assign VAR65 = VAR76[4:3] == 2'b10;
assign VAR44 = VAR76[4:3] == 2'b11;
assign VAR59 = VAR76[4:3] == 2'b01;
assign VAR99 = VAR76[4:3] == 2'b00;
assign VAR91 = VAR113 | VAR82;
assign wand = VAR113 & VAR82;
assign VAR11 = VAR113 ^ VAR82;
assign VAR39 = VAR103 & VAR59 & ((VAR68 == VAR55) |
(VAR68 == VAR13) |
(VAR68 == VAR37));
assign VAR58 = (VAR103 & VAR59 & (VAR68 != VAR83)) |
VAR78 | VAR38;
assign VAR60 = VAR57 | (VAR90 & VAR136);
assign VAR114 = VAR103 & VAR59 & (VAR68 == VAR37);
assign VAR8 = VAR103 & VAR59 & (VAR68 == VAR13);
assign VAR14 = VAR103 & VAR65 & (VAR68 == VAR101);
assign VAR116 = VAR103 & VAR65 & (VAR68 == VAR122);
assign VAR81 = (VAR68 == VAR61) | (VAR68 == VAR27);
assign VAR102 = (VAR68 == VAR23) | (VAR68 == VAR27);
assign VAR57 = VAR10 & VAR36;
assign VAR10 = VAR103 & VAR65 & ((VAR68 == VAR20) |
(VAR68 == VAR61) |
(VAR68 == VAR23) |
(VAR68 == VAR27));
assign VAR120 = VAR116 & VAR36 & (VAR85 != VAR21);
assign VAR38 = (VAR14 | VAR116) & VAR36 & (VAR85 != VAR21);
assign VAR30 = VAR99 & (VAR68 == VAR112);
assign VAR72 = VAR103 & VAR44 & (VAR68 == VAR141);
assign VAR136 = VAR45 == 2'b01;
assign VAR109 = VAR9 ? VAR43 :
VAR41 ? VAR46 :
VAR38 ? VAR82 :
VAR45[0] ? VAR24 :
(VAR85 == VAR93) ? VAR70 :
(VAR85 == VAR98) ? VAR35 : VAR113;
assign VAR54 = VAR41 ? 8'h00 :
VAR45[0] ? 8'h00 :
VAR38 ? 8'h00 : VAR82;
assign VAR42 = VAR41 ? VAR69 :
VAR45[0] ? VAR69 :
(VAR75 | VAR114 | VAR9 | VAR14);
assign VAR110 = ((VAR41 | (VAR45 != 2'b00)) & !VAR69) |
(VAR116 & VAR36) | VAR8 | VAR114;
assign VAR95 = VAR45[0] ? VAR24 : VAR82;
assign VAR71 = !VAR9 ? 1'b0 :
(VAR68 == VAR80) ? !VAR5 :
(VAR68 == VAR33) ? VAR5 :
(VAR68 == VAR92) ? !VAR32 :
(VAR68 == VAR66) ? VAR32 :
(VAR68 == VAR50) ? !VAR75 :
(VAR68 == VAR12) ? VAR75 :
(VAR68 == VAR94) ? !VAR121 : VAR121;
assign VAR130 = !VAR82[7] & VAR25;
assign VAR84 = VAR82[7] & !VAR25;
assign VAR140 = VAR71 & VAR9 & (VAR130 | VAR84);
assign VAR74 = VAR82 & VAR113;
assign VAR78 = VAR103 & VAR30;
assign VAR34 = VAR74 == 8'h00;
assign VAR29 = VAR74[7];
assign VAR132 = VAR74[0];
always @ (posedge clk or negedge VAR124) begin
if (!VAR124) begin
VAR97 <= 1'b0;
VAR41 <= 1'b0;
VAR90 <= 1'b0;
VAR69 <= 1'b0;
VAR24 <= 1'b0;
VAR45 <= 2'b00;
end else begin
VAR97 <= VAR62;
VAR41 <= VAR140;
if (VAR103) begin
VAR90 <= VAR10;
end
if (VAR45 == 2'b00) begin
VAR69 <= VAR130 | VAR14;
end
if ((VAR14 | VAR116 | VAR10) & !VAR36) begin
VAR24 <= VAR82;
VAR45 <= 2'b11;
end else if (VAR45 != 2'b00) begin
VAR45 <= { 1'b0, VAR45[1] };
end
end
end
VAR52 alu(
.VAR19 (VAR109 ),
.VAR111 (VAR54 ),
.VAR100 (VAR42 ),
.VAR133 (VAR105 ),
.VAR96 (VAR110 ),
.VAR16 (VAR47 ),
.VAR117 (VAR143 ),
.VAR40 (VAR67 ),
.VAR18 (VAR25 ),
.VAR129 (VAR86 ));
VAR131 VAR64(
.VAR63 (VAR95 ),
.VAR15(VAR81),
.VAR26 (VAR102 ),
.VAR100 (VAR75 ),
.VAR144 (VAR51 ),
.VAR117 (VAR73 ),
.VAR40 (VAR77 ),
.VAR18 (VAR53 ));
endmodule
|
bsd-3-clause
|
cr88192/bgbtech_bjx1core
|
bjx1c32b1/DecOp4.v
| 43,554 |
module MODULE1(
clk,
VAR136,
VAR81,
VAR121,
VAR8,
VAR344,
VAR328,
VAR107,
VAR197,
VAR51
);
parameter VAR282 = 0; parameter VAR53 = 0; parameter VAR220 = 1;
input clk; input[47:0] VAR136; input[15:0] VAR81;
output[6:0] VAR121;
output[6:0] VAR8;
output[6:0] VAR344;
output[31:0] VAR328;
output[3:0] VAR107;
output[3:0] VAR197;
output[7:0] VAR51;
reg VAR52; reg VAR11; reg VAR140; reg VAR48;
reg VAR176;
reg VAR280;
reg VAR239;
reg VAR340;
reg VAR61;
reg[15:0] VAR336;
reg[6:0] VAR151;
reg[6:0] VAR43;
reg[6:0] VAR178; reg[31:0] VAR187; reg[7:0] VAR250;
reg[3:0] VAR82;
reg[3:0] VAR289;
reg[3:0] VAR330;
reg[3:0] VAR155;
assign VAR121 = VAR151;
assign VAR8 = VAR43;
assign VAR344 = VAR178;
assign VAR328 = VAR187;
assign VAR51 = VAR250;
assign VAR107 = VAR82;
assign VAR197 = VAR289;
reg[4:0] VAR270;
reg[2:0] VAR76;
reg[6:0] VAR290;
reg[6:0] VAR130;
reg[6:0] VAR15;
reg[6:0] VAR153;
reg[6:0] VAR110;
reg[6:0] VAR348;
reg[6:0] VAR189;
reg[6:0] VAR80;
reg[6:0] VAR20;
reg[6:0] VAR133;
reg[6:0] VAR146;
reg[6:0] VAR157;
reg[31:0] VAR7;
reg[31:0] VAR173;
reg[31:0] VAR88;
reg[31:0] VAR211;
reg VAR281;
reg VAR28;
wire[6:0] VAR129;
wire[6:0] VAR141;
wire[6:0] VAR223;
wire[31:0] VAR174;
wire[7:0] VAR185;
VAR183 VAR343(VAR136[31:0],
VAR129, VAR141, VAR223,
VAR174, VAR185);
always @*
begin
VAR82 = 2;
VAR336=0;
VAR250=VAR103;
VAR187=0;
VAR52=0;
VAR11=0; VAR140=0; VAR48=0;
VAR61=1;
VAR151=VAR100;
VAR43=VAR100;
VAR178=VAR100;
VAR270=VAR148;
VAR76=VAR261;
if(VAR282 && VAR81[5])
begin
VAR340=1; VAR176=VAR81[6];
VAR280=VAR176; VAR239=0;
end else begin
VAR340=0; VAR176=0;
VAR280=0; VAR239=0;
end
VAR336=VAR136[15:0];
VAR289 = 2;
VAR330=2;
VAR155=2;
if(VAR220)
begin
if(VAR136[47:43]==5'h10001)
begin
if( (VAR136[42:40]==3'b010) ||
(VAR136[42:40]==3'b100) ||
(VAR136[42:40]==3'b110))
VAR330=4;
end
if(VAR136[31:27]==5'b10001)
begin
if( (VAR136[26:24]==3'b010) ||
(VAR136[26:24]==3'b100) ||
(VAR136[26:24]==3'b110))
VAR155=4;
end
end
casez(VAR336[15:0])
16'VAR309: begin VAR250=VAR337; VAR270=VAR10;
VAR76=VAR172;
end
16'VAR74: begin VAR250=VAR303; VAR270=VAR135;
end
16'VAR216: begin VAR250 = VAR280 ? VAR297 : VAR334;
VAR270=VAR135;
end
16'VAR22: begin VAR250 = VAR239 ? VAR297 : VAR92;
VAR270=VAR135;
end
16'VAR126: begin VAR250=VAR31; VAR270=VAR139;
end
16'VAR263: begin VAR250=VAR3;
VAR187[7:0]=VAR26;
VAR270=VAR24;
end
16'VAR23: begin VAR250=VAR3;
VAR187[7:0]=VAR293;
VAR270=VAR24;
end
16'VAR123: begin VAR250=VAR3;
VAR187[7:0]=VAR33;
VAR270=VAR24;
end
16'VAR240: begin VAR250=VAR3;
VAR187[7:0]=VAR87;
VAR270=VAR24;
end
16'VAR50: begin VAR250=VAR3;
VAR187[7:0]=VAR204;
VAR270=VAR24;
end
16'VAR257: begin VAR250=VAR3;
VAR187[7:0]=VAR160;
VAR270=VAR24;
end
16'VAR295: begin VAR250=VAR3;
VAR187[7:0]=VAR83;
VAR270=VAR24;
end
16'VAR246: begin VAR250=VAR235; VAR270=VAR294;
end
16'VAR238: begin VAR250=VAR3;
VAR187[7:0]=VAR168;
VAR270=VAR24;
end
16'VAR269: begin VAR250=VAR292; VAR270=VAR338;
end
16'VAR249: begin VAR250=VAR65; VAR270=VAR338;
end
16'VAR277: begin VAR250=VAR337; VAR270=VAR10;
VAR76=VAR167;
end
16'VAR145: begin VAR250=VAR152; VAR270=VAR294;
end
16'VAR67: begin VAR250=VAR3;
VAR187[7:0]=VAR191;
VAR270=VAR24;
end
16'VAR212: begin VAR250=VAR89; VAR270=VAR294;
end
16'VAR199: begin VAR250=VAR103; VAR270=VAR294;
VAR187=1;
end
16'VAR175: begin VAR250=VAR312; VAR270=VAR294;
end
16'VAR233: begin VAR250=VAR321; VAR270=VAR135;
end
16'VAR327: begin VAR250 = VAR280 ? VAR37 : VAR131;
VAR270=VAR135;
end
16'VAR132: begin VAR250 = VAR9;
VAR270=VAR135;
end
16'VAR55: begin VAR250 = VAR239 ? VAR297 : VAR92;
VAR270=VAR144;
end
16'VAR32: begin VAR250=VAR303; VAR270=VAR138;
end
16'VAR231: begin VAR250 = VAR280 ? VAR297 : VAR334;
VAR270=VAR138;
end
16'VAR59: begin VAR250 = VAR239 ? VAR297 : VAR92;
VAR270=VAR138;
end
16'VAR350: begin VAR250=VAR278; VAR270=VAR135;
end
16'VAR77: begin VAR250=VAR303; VAR270=VAR38;
VAR76=VAR102;
end
16'VAR179: begin VAR250 = VAR280 ? VAR297 : VAR334;
VAR270=VAR38;
VAR76=VAR102;
end
16'VAR36: begin VAR250 = VAR239 ? VAR297 : VAR92;
VAR270=VAR38;
VAR76=VAR102;
end
16'VAR329: begin VAR250=VAR190; VAR270=VAR139;
end
16'VAR272: begin VAR250=VAR143; VAR270=VAR320;
VAR76=VAR201;
end
16'VAR35: begin VAR250=VAR259; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR98: begin VAR250=VAR345; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR6: begin VAR250=VAR156; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR57: begin VAR250=VAR308; VAR270=VAR181;
end
16'VAR165: begin VAR250=VAR137; VAR270=VAR181;
end
16'VAR5: begin VAR250=VAR150; VAR270=VAR139;
end
16'VAR54: begin VAR250=VAR109; VAR270=VAR139;
end
16'VAR124: begin VAR250=VAR176 ? VAR27 : VAR163;
VAR270=VAR320;
end
16'VAR78: begin VAR250=VAR176 ? VAR342 : VAR58;
VAR270=VAR320;
end
16'VAR208: begin VAR250=VAR176 ? VAR21 : VAR86;
VAR270=VAR320;
end
16'VAR253: begin VAR250=VAR162; VAR270=VAR181;
end
16'VAR99: begin VAR250=VAR268; VAR270=VAR139;
end
16'VAR346: begin VAR250=VAR176 ? VAR117 : VAR84;
VAR270=VAR320;
end
16'VAR149: begin VAR250=VAR176 ? VAR287 : VAR202;
VAR270=VAR320;
end
16'VAR159: begin VAR250=VAR205; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR234: begin VAR250=VAR331; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR221: begin VAR250=VAR108; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR122: begin VAR250=VAR18; VAR270=VAR181;
VAR76=VAR201;
end
16'VAR274: begin VAR250=VAR31; VAR270=VAR139;
end
16'VAR62: begin VAR250=VAR154; VAR270=VAR181;
end
16'VAR265: begin VAR250=VAR104; VAR270=VAR181;
end
16'VAR13: begin VAR250=VAR316; VAR270=VAR338;
end
16'VAR2: begin VAR250=VAR251; VAR270=VAR338;
end
16'VAR91: begin VAR250=VAR127; VAR270=VAR338;
end
16'VAR286: begin VAR250=VAR219; VAR270=VAR338;
end
16'VAR332: begin VAR250=VAR176 ? VAR21 : VAR86;
VAR270=VAR142;
end
16'VAR73: begin VAR250=VAR49; VAR270=VAR338;
end
16'VAR147: begin VAR250 = VAR340 ? VAR297 : VAR92;
VAR270=VAR38;
VAR76=VAR167;
end
16'VAR4: begin VAR250 = VAR340 ? VAR297 : VAR92;
VAR270=VAR38;
VAR76=VAR172;
end
16'VAR90: begin VAR250=VAR39; VAR270=VAR338;
end
16'VAR170: begin VAR250=VAR70; VAR270=VAR338;
end
16'VAR193: begin VAR250=VAR184; VAR270=VAR338;
end
16'VAR283: begin VAR250=VAR176 ? VAR287 : VAR202;
VAR270=VAR142;
end
16'VAR311: begin VAR250=VAR200; VAR270=VAR338;
end
16'VAR213: begin VAR250 = VAR340 ? VAR37 : VAR9;
VAR270=VAR38;
VAR76=VAR279;
end
16'VAR206: begin VAR250 = VAR340 ? VAR297 : VAR9;
VAR270=VAR38;
VAR76=VAR227;
end
16'VAR19: begin VAR250=VAR96; VAR270=VAR225;
VAR187=2;
end
16'VAR254: begin VAR250=VAR96; VAR270=VAR225;
VAR187=8;
end
16'VAR164: begin VAR250=VAR96; VAR270=VAR225;
VAR187=16;
end
16'VAR247: begin VAR250=VAR96; VAR270=VAR225;
VAR187=-2;
end
16'VAR75: begin VAR250=VAR96; VAR270=VAR225;
VAR187=-8;
end
16'VAR46: begin VAR250=VAR96; VAR270=VAR225;
VAR187=-16;
end
16'VAR79: begin VAR250=VAR337; VAR270=VAR10;
VAR76=VAR279;
end
16'VAR29: begin
VAR250=VAR66; VAR270=VAR142;
end
16'VAR262: begin
VAR250=VAR120; VAR270=VAR142;
end
16'VAR224: begin
end
16'VAR119: begin
VAR250=VAR111; VAR270=VAR142;
end
16'VAR326: begin VAR250=VAR176 ? VAR241 : VAR113;
VAR270=VAR181;
VAR76=VAR261;
end
16'VAR307: begin VAR250=VAR176 ? VAR12 : VAR96;
VAR270=VAR181;
VAR76=VAR261;
end
16'VAR252: begin VAR250=VAR337; VAR270=VAR10;
VAR76=VAR227;
end
16'VAR318: begin VAR250 = VAR9;
VAR270=VAR144;
end
16'VAR40: begin VAR250=VAR321; VAR270=VAR138;
end
16'VAR237: begin VAR250 = VAR280 ? VAR37 : VAR131;
VAR270=VAR138;
end
16'VAR264: begin VAR250 = VAR9;
VAR270=VAR138;
end
16'VAR125: begin VAR250=VAR337; VAR270=VAR10;
end
16'VAR195: begin VAR250=VAR321; VAR270=VAR38;
VAR76=VAR64;
end
16'VAR60: begin VAR250 = VAR280 ? VAR37 : VAR131;
VAR270=VAR38;
VAR76=VAR64;
end
16'VAR230: begin VAR250 = VAR9;
VAR270=VAR38;
VAR76=VAR64;
end
16'VAR310: begin
VAR250=VAR226; VAR270=VAR10;
end
16'VAR101: begin
VAR250=VAR69; VAR270=VAR10;
end
16'VAR243: begin
VAR250=VAR194; VAR270=VAR10;
end
16'VAR41: begin
VAR250=VAR93; VAR270=VAR10;
end
16'VAR16: begin
VAR250=VAR14; VAR270=VAR10;
end
16'VAR248: begin
VAR250=VAR215; VAR270=VAR10;
end
16'VAR182: begin
VAR250=VAR44; VAR270=VAR10;
end
16'VAR315: begin
VAR250=VAR229; VAR270=VAR10;
end
16'VAR45: begin
VAR250=VAR161; VAR270=VAR10;
end
16'VAR207: begin VAR250=VAR18; VAR270=VAR258;
end
16'VAR236: begin VAR250=VAR303;
VAR270=VAR72;
VAR76=VAR256;
end
16'VAR300: begin VAR250=VAR334;
VAR270=VAR72;
VAR76=VAR256;
end
16'VAR305: begin VAR250=VAR218; VAR270=VAR276;
end
16'VAR47: begin if(VAR220)
begin
VAR270=VAR72;
if(VAR336[7])
begin
VAR250=VAR9;
VAR76=VAR296;
end else begin
VAR250=VAR92;
VAR76=VAR317;
end
end
end
16'VAR210: begin VAR250=VAR321;
VAR270=VAR72;
VAR76=VAR291;
end
16'VAR115: begin VAR250=VAR131;
VAR270=VAR72;
VAR76=VAR291;
end
16'VAR105: begin if(VAR220)
begin
VAR270=VAR72;
if(VAR336[7])
begin
VAR250=VAR9;
VAR76=VAR306;
end else begin
VAR250=VAR92;
VAR76=VAR85;
end
end
end
16'VAR169: begin VAR250=VAR163;
VAR270=VAR302;
end
16'VAR314: begin VAR250=VAR196; VAR270=VAR276;
end
16'VAR192: begin if(VAR220)
begin
VAR151=VAR260;
VAR250=VAR134;
VAR187={VAR136[7] ? 8'hFF : 8'h00,
VAR136[7:0], VAR136[31:16]};
VAR270=VAR24;
end
end
16'VAR339: begin VAR250=VAR222; VAR270=VAR276;
end
16'VAR180: begin
end
16'VAR118: begin VAR250=VAR335; VAR270=VAR276;
end
16'VAR324: begin
if(VAR220)
begin
VAR48 = 1;
VAR82 = 4;
end
end
16'VAR347: begin VAR250=VAR95; VAR270=VAR276;
end
16'VAR128: begin VAR151[3:0]=VAR336[11:8];
VAR43=VAR284;
VAR178=VAR100;
VAR187[7:0]=VAR336[ 7:0];
VAR250=VAR131;
VAR270=VAR24;
end
16'VAR198: begin VAR250=VAR17; VAR270=VAR114;
end
16'VAR203: begin VAR250=VAR30; VAR270=VAR114;
end
16'VAR266: begin
if(VAR340)
begin
VAR250=VAR297;
VAR270=VAR72;
VAR76=VAR351;
end else begin
VAR250=VAR303;
VAR270=VAR298;
end
end
16'VAR271: begin
if(VAR340)
begin
end else begin
VAR250=VAR334;
VAR270=VAR298;
end
end
16'VAR313: begin
if(VAR340)
begin
end else begin
VAR250=VAR92;
VAR270=VAR298;
end
end
16'VAR68: begin
if(VAR340)
begin
VAR250=VAR37;
VAR270=VAR72;
VAR76=VAR275;
end else begin
VAR250=VAR321;
VAR270=VAR288;
end
end
16'VAR285: begin
if(VAR340)
begin
end else begin
VAR250=VAR131;
VAR270=VAR288;
end
end
16'VAR322: begin
if(VAR340)
begin
end else begin
VAR250=VAR9;
VAR270=VAR288;
end
end
16'VAR255: begin VAR250=VAR176 ? VAR325 : VAR143;
VAR270=VAR188;
end
16'VAR56: begin VAR250=VAR259; VAR270=VAR302;
end
16'VAR228: begin VAR250=VAR345; VAR270=VAR302;
end
16'VAR319: begin VAR250=VAR156; VAR270=VAR302;
end
16'VAR323: begin VAR151[3:0]=VAR336[11:8];
VAR43=VAR25;
VAR178=VAR100;
VAR187[7:0]=VAR336[ 7:0];
VAR250=VAR9;
VAR270=VAR24;
end
16'VAR245: begin VAR250=VAR134;
VAR270=VAR258;
end
16'VAR341: begin
VAR250=VAR177;
VAR270=VAR244;
end
16'VAR71: begin
VAR250=VAR333;
VAR270=VAR244;
end
16'VAR304: begin
VAR250=VAR217;
VAR270=VAR244;
end
16'VAR42: begin
VAR250=VAR267;
VAR270=VAR244;
end
16'VAR209: begin
VAR250=VAR186;
VAR270=VAR244;
end
16'VAR116: begin
VAR250=VAR9; VAR270=VAR135;
VAR76=VAR106;
end
16'VAR1: begin
VAR250=VAR92; VAR270=VAR135;
VAR76=VAR299;
end
16'VAR301: begin
VAR250=VAR9; VAR270=VAR138;
VAR76=VAR106;
end
16'VAR273: begin
VAR250=VAR9; VAR270=VAR38;
VAR76=VAR94;
end
16'VAR349: begin
VAR250=VAR92; VAR270=VAR138;
VAR76=VAR299;
end
default: begin end
endcase
VAR290 = {3'b000, VAR336[11:8]};
VAR130 = {3'b000, VAR336[ 7:4]};
VAR15 = {3'b000, VAR336[ 3:0]};
VAR153={3'h2, VAR336[7:4]};
VAR110={3'h6, VAR336[7:4]};
VAR348 = {3'h4, VAR336[11:8]};
VAR189 = {3'h4, VAR336[ 7:4]};
VAR146 = {3'h0, 1'b1, VAR336[6:4]};
VAR157 = {3'h0, 1'b1, VAR336[2:0]};
VAR7 = {28'h0, VAR336[ 3:0]};
VAR173 = {24'h0, VAR336[ 7:0]};
VAR88 = {VAR336[ 7] ? 24'hFFFFFF : 24'h000000, VAR336 [ 7:0]};
VAR211 = {VAR336[11] ? 20'hFFFFF : 20'h00000 , VAR336 [11:0]};
case(VAR270)
VAR24: begin
end
VAR338: begin
VAR151=VAR290;
VAR43=VAR290;
end
VAR138: begin
VAR151=VAR290; VAR43=VAR130;
end
VAR135: begin
VAR151=VAR290; VAR43=VAR130;
VAR178=VAR260; VAR187=0;
end
VAR144: begin
VAR151=VAR290; VAR43=VAR130;
VAR187 = VAR7;
end
VAR38: begin
case(VAR76)
VAR102: begin
VAR151=VAR290; VAR43=VAR130;
VAR178=VAR214;
end
VAR64: begin
VAR151=VAR290; VAR43=VAR130;
VAR178=VAR97;
end
VAR232: begin
VAR151=VAR290; VAR43=VAR189;
VAR178=VAR214;
end
VAR94: begin
VAR151=VAR348; VAR43=VAR130;
VAR178=VAR97;
end
default: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
endcase
end
VAR244: begin
VAR151=VAR348;
VAR43=VAR189;
end
VAR10: begin
VAR151=VAR290; VAR43=VAR130;
end
VAR34: begin
case(VAR76)
VAR279: begin
VAR151=VAR110; VAR43=VAR290;
VAR178=VAR97;
end
VAR227: begin
VAR151=VAR153; VAR43=VAR290;
VAR178=VAR97;
end
VAR167: begin
VAR151=VAR290; VAR43=VAR110;
VAR178=VAR214;
end
VAR172: begin
VAR151=VAR290; VAR43=VAR153;
VAR178=VAR214;
end
default: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
endcase
end
VAR166: begin
case(VAR76)
VAR279: begin
VAR151=VAR110; VAR43=VAR290;
end
VAR227: begin
VAR151=VAR153; VAR43=VAR290;
end
VAR167: begin
VAR151=VAR290; VAR43=VAR110;
end
VAR172: begin
VAR151=VAR290; VAR43=VAR153;
end
default: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
endcase
end
VAR181: begin
VAR151=VAR290; VAR43=VAR290; VAR178=VAR130;
end
VAR320: begin
VAR43=VAR290; VAR178=VAR130;
end
VAR139: begin
VAR151=VAR290; VAR43=VAR130;
end
VAR258: begin
VAR151=VAR290; VAR43=VAR290;
VAR178=VAR63; VAR187=VAR88;
end
VAR276: begin
VAR187 = VAR88;
end
VAR114: begin
VAR187 = VAR211;
end
VAR302: begin
VAR151=VAR260; VAR43=VAR260;
VAR178=VAR63; VAR187=VAR173;
end
VAR225: begin
VAR151=VAR290; VAR43=VAR290;
VAR178=VAR63;
end
VAR298: begin
VAR151=VAR112; VAR43=VAR260;
VAR178=VAR63; VAR187=VAR173;
end
VAR288: begin
VAR151=VAR260; VAR43=VAR112;
VAR178=VAR63; VAR187=VAR173;
end
VAR72: begin
case(VAR76)
VAR351: begin
VAR151=VAR158; VAR43=VAR130;
VAR178=VAR63; VAR187=VAR7;
end
VAR275: begin
VAR151=VAR130; VAR43=VAR158;
VAR178=VAR63; VAR187=VAR7;
end
VAR317: begin
VAR151=VAR158; VAR43=VAR146;
VAR178=VAR63;
VAR187[3:0]=VAR336[3:0];
VAR187[31:4]=1;
end
VAR296: begin
VAR151=VAR146; VAR43=VAR158;
VAR178=VAR63;
VAR187[3:0]=VAR336[3:0];
VAR187[31:4]=1;
end
VAR85: begin
VAR151=VAR158;
VAR43={3'h4, 1'b1, VAR336[6:4]};
VAR178=VAR63; VAR187=VAR7;
end
VAR306: begin
VAR151={3'h4, 1'b1, VAR336[6:4]};
VAR43=VAR158;
VAR178=VAR63; VAR187=VAR7;
end
VAR256: begin
VAR151=VAR130; VAR43=VAR260;
VAR178=VAR63; VAR187=VAR7;
end
VAR291: begin
VAR151=VAR260; VAR43=VAR130;
VAR178=VAR63; VAR187=VAR7;
end
default: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
endcase
end
VAR148: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
default: begin
VAR151=VAR171; VAR43=VAR171;
VAR178=VAR171; VAR187=32'VAR242;
end
endcase
if(VAR48)
begin
VAR151=VAR129; VAR43=VAR141;
VAR178=VAR223; VAR187=VAR174;
VAR250=VAR185;
VAR289=VAR330;
end
else
begin
VAR289=VAR155;
end
end
endmodule
|
mit
|
sabertazimi/hust-lab
|
verilog/labs/lab2/src/decoder_74138_dataflow.v
| 1,077 |
module MODULE1(
input [0:2] VAR3,
input VAR1,
input VAR4,
input VAR5,
output [7:0] VAR2
);
assign VAR2[0] = VAR4|VAR5|(~VAR1)|VAR3[0]|VAR3[1]|VAR3[2];
assign VAR2[1] = VAR4|VAR5|(~VAR1)|VAR3[0]|VAR3[1]|(~VAR3[2]);
assign VAR2[2] = VAR4|VAR5|(~VAR1)|VAR3[0]|(~VAR3[1])|VAR3[2];
assign VAR2[3] = VAR4|VAR5|(~VAR1)|VAR3[0]|(~VAR3[1])|(~VAR3[2]);
assign VAR2[4] = VAR4|VAR5|(~VAR1)|(~VAR3[0])|VAR3[1]|VAR3[2];
assign VAR2[5] = VAR4|VAR5|(~VAR1)|(~VAR3[0])|VAR3[1]|(~VAR3[2]);
assign VAR2[6] = VAR4|VAR5|(~VAR1)|(~VAR3[0])|(~VAR3[1])|VAR3[2];
assign VAR2[7] = VAR4|VAR5|(~VAR1)|(~VAR3[0])|(~VAR3[1])|(~VAR3[2]);
endmodule
|
mit
|
Cosmos-OpenSSD/Cosmos-OpenSSD-plus
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_1/c727b95e/src/d_KES_CS_buffer.v
| 14,090 |
module MODULE1
parameter VAR4 = 2,
parameter VAR26 = 12,
parameter VAR22 = 9,
parameter VAR46 = 15
)
(
VAR3 ,
VAR42 ,
VAR9 ,
VAR29 ,
VAR1 ,
VAR18 ,
VAR24 ,
VAR16 ,
VAR48 ,
VAR7 ,
VAR13 ,
VAR36 ,
VAR45 ,
VAR47 ,
VAR40 ,
VAR17 ,
VAR25 ,
VAR19 ,
VAR2 ,
VAR60 ,
VAR20 ,
VAR30 ,
VAR52 ,
VAR11 ,
VAR5 ,
VAR44 ,
VAR33 ,
VAR31 ,
VAR8 ,
VAR14
);
input VAR3 ;
input VAR42 ;
input VAR9 ;
input VAR29 ;
input VAR1 ;
input VAR18 ;
input VAR24 ;
input [3:0] VAR16 ;
input [VAR26 - 1:0] VAR48 ;
input [VAR26 - 1:0] VAR7 ;
input [VAR26 - 1:0] VAR13 ;
input [VAR26 - 1:0] VAR36 ;
input [VAR26 - 1:0] VAR45 ;
input [VAR26 - 1:0] VAR47 ;
input [VAR26 - 1:0] VAR40 ;
input [VAR26 - 1:0] VAR17 ;
input [VAR26 - 1:0] VAR25 ;
input [VAR26 - 1:0] VAR19 ;
input [VAR26 - 1:0] VAR2 ;
input [VAR26 - 1:0] VAR60 ;
input [VAR26 - 1:0] VAR20 ;
input [VAR26 - 1:0] VAR30 ;
input [VAR26 - 1:0] VAR52 ;
input VAR11 ;
output VAR5 ;
output reg VAR44 ;
output reg [VAR4 - 1:0] VAR33 ;
output reg [VAR4 - 1:0] VAR31 ;
output reg [VAR4*VAR22 - 1:0] VAR8 ;
output reg [VAR4*VAR26*VAR46 - 1:0] VAR14 ;
reg VAR54;
reg [3:0] VAR12;
reg [3:0] VAR34;
reg [VAR4 - 1:0] VAR50;
reg [VAR4 - 1:0] VAR55;
reg [VAR4*VAR22 - 1:0] VAR53;
reg [VAR4*VAR26 - 1:0] VAR35;
reg [VAR4*VAR26 - 1:0] VAR27;
reg [VAR4*VAR26 - 1:0] VAR59;
reg [VAR4*VAR26 - 1:0] VAR15;
reg [VAR4*VAR26 - 1:0] VAR43;
reg [VAR4*VAR26 - 1:0] VAR49;
reg [VAR4*VAR26 - 1:0] VAR41;
reg [VAR4*VAR26 - 1:0] VAR23;
reg [VAR4*VAR26 - 1:0] VAR6;
reg [VAR4*VAR26 - 1:0] VAR21;
reg [VAR4*VAR26 - 1:0] VAR28;
reg [VAR4*VAR26 - 1:0] VAR10;
reg [VAR4*VAR26 - 1:0] VAR57;
reg [VAR4*VAR26 - 1:0] VAR39;
reg [VAR4*VAR26 - 1:0] VAR51;
localparam VAR58 = 4'b0000;
localparam VAR37 = 4'b0001;
localparam VAR32 = 4'b0010;
localparam VAR56 = 4'b0100;
localparam VAR38 = 4'b1000;
assign VAR5 = !((VAR12 == VAR56) || (VAR12 == VAR38));
always @ (posedge VAR3) begin
if (VAR42 || VAR9)
VAR12 <= VAR58;
end
else
VAR12 <= VAR34;
end
always @ (*) begin
if(VAR42 || VAR9)
VAR34 <= VAR58;
end
else begin
case (VAR12)
VAR58:
VAR34 <= (VAR29) ? VAR37 : VAR58;
VAR37:
VAR34 <= VAR32;
VAR32:
VAR34 <= (VAR29) ? VAR37 : ( (VAR54) ? VAR56 : VAR32 );
VAR56:
VAR34 <= (VAR11) ? VAR38 : VAR56;
VAR38:
VAR34 <= VAR58;
default:
VAR34 <= VAR58;
endcase
end
end
always @ (posedge VAR3) begin
if (VAR42 || VAR9)
VAR54 <= 0;
end
else
case (VAR34)
VAR58:
VAR54 <= 0;
VAR37:
VAR54 <= VAR18;
default:
VAR54 <= VAR54;
endcase
end
always @ (posedge VAR3) begin
if (VAR42 || VAR9)
begin
VAR44 <= 0;
VAR33 <= 0;
VAR31 <= 0;
VAR8 <= 0;
VAR14 <= 0;
end
else begin
case (VAR34)
VAR38: begin
VAR44 <= 1'b1;
VAR33 <= VAR50;
VAR31 <= VAR55;
VAR8 <= VAR53;
VAR14 <= { VAR35,
VAR27,
VAR59,
VAR15,
VAR43,
VAR49,
VAR41,
VAR23,
VAR6,
VAR21,
VAR28,
VAR10,
VAR57,
VAR39,
VAR51 };
end
default: begin
VAR44 <= 0;
VAR33 <= 0;
VAR31 <= 0;
VAR8 <= 0;
VAR14 <= 0;
end
endcase
end
end
always @ (posedge VAR3) begin
if (VAR42 || VAR9)
begin
VAR50 <= 0;
VAR55 <= 0;
VAR53 <= 0;
VAR35 <= 0;
VAR27 <= 0;
VAR59 <= 0;
VAR15 <= 0;
VAR43 <= 0;
VAR49 <= 0;
VAR41 <= 0;
VAR23 <= 0;
VAR6 <= 0;
VAR21 <= 0;
VAR28 <= 0;
VAR10 <= 0;
VAR57 <= 0;
VAR39 <= 0;
VAR51 <= 0;
end
else begin
case (VAR34)
VAR58: begin
VAR50 <= 0;
VAR55 <= 0;
VAR53 <= 0;
VAR35 <= 0;
VAR27 <= 0;
VAR59 <= 0;
VAR15 <= 0;
VAR43 <= 0;
VAR49 <= 0;
VAR41 <= 0;
VAR23 <= 0;
VAR6 <= 0;
VAR21 <= 0;
VAR28 <= 0;
VAR10 <= 0;
VAR57 <= 0;
VAR39 <= 0;
VAR51 <= 0;
end
VAR37: begin
if (VAR1) begin
case (VAR24)
1'b0: begin
VAR55[0] <= 1'b1;
VAR50[0] <= 1'b1;
end
1'b1: begin
VAR55[1] <= 1'b1;
VAR50[1] <= 1'b1;
end
endcase
VAR53 <= VAR53;
VAR35 <= VAR35;
VAR27 <= VAR27;
VAR59 <= VAR59;
VAR15 <= VAR15;
VAR43 <= VAR43;
VAR49 <= VAR49;
VAR41 <= VAR41;
VAR23 <= VAR23;
VAR6 <= VAR6;
VAR21 <= VAR21;
VAR28 <= VAR28;
VAR10 <= VAR10;
VAR57 <= VAR57;
VAR39 <= VAR39;
VAR51 <= VAR51;
end
else begin
VAR55 <= VAR55;
case (VAR24)
1'b0: begin
VAR50[0] <= (|VAR16) ? 1'b1 : 1'b0;
VAR53[VAR22*1 - 1:VAR22*(1 - 1)] <= VAR16;
VAR35[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR48;
VAR27[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR7;
VAR59[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR13;
VAR15[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR36;
VAR43[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR45;
VAR49[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR47;
VAR41[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR40;
VAR23[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR17;
VAR6[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR25;
VAR21[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR19;
VAR28[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR2;
VAR10[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR60;
VAR57[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR20;
VAR39[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR30;
VAR51[VAR26*1 - 1:VAR26*(1 - 1)] <= VAR52;
end
1'b1: begin
VAR50[1] <= (|VAR16) ? 1'b1 : 1'b0;
VAR53[VAR22*2 - 1:VAR22*(2 - 1)] <= VAR16;
VAR35[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR48;
VAR27[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR7;
VAR59[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR13;
VAR15[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR36;
VAR43[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR45;
VAR49[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR47;
VAR41[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR40;
VAR23[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR17;
VAR6[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR25;
VAR21[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR19;
VAR28[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR2;
VAR10[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR60;
VAR57[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR20;
VAR39[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR30;
VAR51[VAR26*2 - 1:VAR26*(2 - 1)] <= VAR52;
end
default: begin
VAR50 <= VAR50;
VAR53 <= VAR53;
VAR35 <= VAR35;
VAR27 <= VAR27;
VAR59 <= VAR59;
VAR15 <= VAR15;
VAR43 <= VAR43;
VAR49 <= VAR49;
VAR41 <= VAR41;
VAR23 <= VAR23;
VAR6 <= VAR6;
VAR21 <= VAR21;
VAR28 <= VAR28;
VAR10 <= VAR10;
VAR57 <= VAR57;
VAR39 <= VAR39;
VAR51 <= VAR51;
end
endcase
end
end
default: begin
VAR55 <= VAR55;
VAR50 <= VAR50;
VAR53 <= VAR53;
VAR35 <= VAR35;
VAR27 <= VAR27;
VAR59 <= VAR59;
VAR15 <= VAR15;
VAR43 <= VAR43;
VAR49 <= VAR49;
VAR41 <= VAR41;
VAR23 <= VAR23;
VAR6 <= VAR6;
VAR21 <= VAR21;
VAR28 <= VAR28;
VAR10 <= VAR10;
VAR57 <= VAR57;
VAR39 <= VAR39;
VAR51 <= VAR51;
end
endcase
end
end
endmodule
|
gpl-3.0
|
ncos/Xilinx-Verilog
|
GYRACC/src/GYRO/spi_interface.v
| 5,167 |
module MODULE1(
VAR7,
VAR19,
VAR18,
VAR21,
clk,
rst,
VAR2,
VAR3,
VAR5,
VAR15
);
input [7:0] VAR7;
input VAR19;
input VAR18;
input VAR21;
input clk;
input rst;
output [7:0] VAR2;
output VAR3;
output VAR5;
output VAR15;
reg [7:0] VAR2;
reg VAR3;
reg VAR5;
parameter [11:0] VAR20 = 12'hFFF;
reg [11:0] VAR14;
reg VAR4;
reg VAR9;
parameter [3:0] VAR1 = 4'h8;
reg [3:0] VAR6;
reg [7:0] VAR17;
parameter [1:0] VAR11 = 0,
VAR13 = 1,
VAR12 = 2;
reg [1:0] VAR16;
always @(posedge clk)
begin: VAR10
begin
if (rst == 1'b1)
begin
VAR5 <= 1'b1;
VAR16 <= VAR11;
VAR2 <= {8{1'b0}};
VAR17 <= {8{1'b0}};
end
else
case (VAR16)
VAR11 :
begin
VAR3 <= 1'b0;
if (VAR19 == 1'b1)
begin
VAR16 <= VAR13;
VAR6 <= {4{1'b0}};
VAR17 <= VAR7;
end
end
VAR13 :
if (VAR6 < VAR1)
begin
if (VAR9 == 1'b1 & VAR4 == 1'b0)
VAR5 <= VAR17[7];
end
else if (VAR9 == 1'b0 & VAR4 == 1'b1)
begin
VAR17[7:1] <= VAR17[6:0];
VAR17[0] <= VAR21;
VAR6 <= VAR6 + 1'b1;
end
end
else
begin
VAR16 <= VAR12;
VAR3 <= 1'b1;
VAR2 <= VAR17;
end
VAR12 :
begin
VAR3 <= 1'b0;
if (VAR18 == 1'b1)
begin
VAR5 <= 1'b1;
VAR16 <= VAR11;
end
else if (VAR19 == 1'b1)
begin
VAR16 <= VAR13;
VAR6 <= {4{1'b0}};
VAR17 <= VAR7;
end
end
endcase
end
end
always @(posedge clk)
begin: VAR8
begin
if (rst == 1'b1)
begin
VAR9 <= 1'b1;
VAR4 <= 1'b1;
VAR14 <= {12{1'b0}};
end
else if (VAR16 == VAR13)
begin
if (VAR14 == VAR20)
begin
VAR4 <= (~VAR4);
VAR14 <= {12{1'b0}};
end
else
begin
VAR9 <= VAR4;
VAR14 <= VAR14 + 1'b1;
end
end
else
VAR9 <= 1'b1;
end
end
assign VAR15 = VAR9;
endmodule
|
mit
|
ankitshah009/High-Radix-Adaptive-CORDIC
|
HCORDIC_Verilog/HCORDIC_Pipeline.v
| 3,318 |
module MODULE1(
input [15:0] VAR55,
input VAR7,
output [31:0] VAR79,
output [31:0] VAR66,
output [31:0] VAR9,
output VAR47
);
wire VAR72,VAR70,VAR18,VAR15;
wire VAR8,VAR41,VAR51,VAR24;
wire [1:0] VAR1,VAR28,VAR37,VAR69;
wire [31:0] VAR40, VAR60, VAR62, VAR53, VAR78;
wire [31:0] VAR64, VAR36, VAR13, VAR23, VAR11;
wire [31:0] VAR26, VAR58, VAR73, VAR34, VAR33;
wire [31:0] VAR57, VAR77, VAR29, VAR63;
wire [31:0] VAR43;
wire [31:0] VAR50;
wire [31:0] VAR31;
VAR22 VAR75 (
.VAR55(VAR55),
.VAR7(VAR7),
.VAR72(VAR72),
.VAR40(VAR40),
.VAR64(VAR64),
.VAR26(VAR26),
.VAR14(VAR1),
.VAR49(VAR8),
.VAR70(VAR70)
);
VAR48 VAR32 (
.VAR59(VAR40),
.VAR46(VAR64),
.VAR35(VAR26),
.VAR60(VAR60),
.VAR36(VAR36),
.VAR58(VAR58),
.VAR57(VAR57),
.VAR70(VAR70),
.VAR18(VAR18),
.VAR7(VAR7),
.VAR56(VAR1),
.VAR42(VAR8),
.VAR28(VAR28),
.VAR41(VAR41),
.VAR79(VAR62),
.VAR66(VAR13),
.VAR9(VAR73),
.VAR39(VAR77),
.VAR53(VAR53),
.VAR23(VAR23),
.VAR34(VAR34),
.VAR29(VAR29),
.VAR21(VAR37),
.VAR54(VAR51),
.VAR15(VAR15),
.VAR72(VAR72)
);
VAR17 VAR10 (
.VAR61(VAR62),
.VAR80(VAR13),
.VAR52(VAR73),
.VAR67(VAR77),
.VAR7(VAR7),
.VAR37(VAR37),
.VAR51(VAR51),
.VAR3(VAR69),
.VAR6(VAR24),
.VAR78(VAR78),
.VAR11(VAR11),
.VAR33(VAR33),
.VAR63(VAR63),
.VAR43(VAR43),
.VAR50(VAR50),
.VAR31(VAR31)
);
VAR19 VAR27 (
.VAR65(VAR78),
.VAR45(VAR11),
.VAR74(VAR33),
.VAR5(VAR63),
.VAR25(VAR31),
.VAR68(VAR43),
.VAR71(VAR50),
.VAR7(VAR7),
.VAR49(VAR24),
.VAR14(VAR69),
.VAR4(VAR60),
.VAR44(VAR36),
.VAR30(VAR58),
.VAR38(VAR57),
.VAR20(VAR28),
.VAR16(VAR41),
.VAR18(VAR18)
);
VAR12 VAR76 (
.VAR53(VAR53),
.VAR23(VAR23),
.VAR34(VAR34),
.VAR2(VAR29),
.VAR7(VAR7),
.VAR79(VAR79),
.VAR66(VAR66),
.VAR9(VAR9),
.VAR47(VAR47)
);
endmodule
|
apache-2.0
|
VCTLabs/DE1_SOC_Linux_FB
|
soc_system/submodules/altera_avalon_st_bytes_to_packets.v
| 8,093 |
module MODULE1
parameter VAR3 = 0 )
(
input clk,
input VAR10,
input VAR6,
output reg VAR20,
output reg [7: 0] VAR17,
output reg [VAR8-1: 0] VAR21,
output reg VAR5,
output reg VAR12,
output reg VAR16,
input VAR9,
input [7: 0] VAR11
);
reg VAR19, VAR4, VAR2;
wire VAR18, VAR13, VAR15, VAR14, VAR7;
wire [7:0] VAR1;
assign VAR13 = (VAR11 == 8'h7a);
assign VAR15 = (VAR11 == 8'h7b);
assign VAR14 = (VAR11 == 8'h7c);
assign VAR18 = (VAR11 == 8'h7d);
assign VAR1 = VAR19 ? (VAR11 ^ 8'h20) : VAR11;
generate
if (VAR8 == 0) begin
always @(posedge clk or negedge VAR10) begin
if (!VAR10) begin
VAR19 <= 0;
VAR5 <= 0;
VAR12 <= 0;
end else begin
if (VAR9 & VAR16) begin
if (VAR19) begin
if (VAR6) VAR19 <= 0;
end else begin
if (VAR18) VAR19 <= 1;
if (VAR13) VAR5 <= 1;
if (VAR15) VAR12 <= 1;
end
if (VAR6 & VAR20) begin
VAR5 <= 0;
VAR12 <= 0;
end
end
end
end
always @* begin
VAR16 = VAR6;
VAR20 = 0;
if ((VAR6 | ~VAR20) && VAR9) begin
VAR20 = 1;
if (VAR13 | VAR15 | VAR18 | VAR14) VAR20 = 0;
end
VAR17 = VAR1;
end
end else begin
assign VAR7 = VAR11[7];
always @(posedge clk or negedge VAR10) begin
if (!VAR10) begin
VAR19 <= 0;
VAR4 <= 0;
VAR2 <= 0;
VAR5 <= 0;
VAR12 <= 0;
end else begin
if (VAR9 & VAR16) begin
if (VAR19) begin
if (VAR6 | VAR4 | VAR2) VAR19 <= 0;
end else begin
if (VAR18) VAR19 <= 1;
if (VAR13) VAR5 <= 1;
if (VAR15) VAR12 <= 1;
if (VAR14 & VAR3 ) VAR2 <= 1;
if (VAR14 & ~VAR3) VAR4 <= 1;
end
if (VAR4 & (VAR19 | (~VAR13 & ~VAR15 & ~VAR18 & ~VAR14 ))) begin
VAR4 <= 0;
end
if (VAR2 & ~VAR7 & (VAR19 | (~VAR13 & ~VAR15 & ~VAR18 & ~VAR14))) begin
VAR2 <= 0;
end
if (VAR6 & VAR20) begin
VAR5 <= 0;
VAR12 <= 0;
end
end
end
end
always @* begin
VAR16 = VAR6;
VAR20 = 0;
if ((VAR6 | ~VAR20) && VAR9) begin
VAR20 = 1;
if (VAR19) begin
if (VAR4 | VAR2) VAR20 = 0;
end else begin
if (VAR13 | VAR15 | VAR18 | VAR14 | VAR4 | VAR2) VAR20 = 0;
end
end
VAR17 = VAR1;
end
end
endgenerate
generate
if (VAR8 == 0) begin
always @(posedge clk) begin
VAR21 <= 'h0;
end
end else if (VAR8 < 8) begin
always @(posedge clk or negedge VAR10) begin
if (!VAR10) begin
VAR21 <= 'h0;
end else begin
if (VAR16 & VAR9) begin
if ((VAR14 & VAR3) & (~VAR19 & ~VAR13 & ~VAR15 & ~VAR18 )) begin
VAR21 <= 'h0;
end else if (VAR2 & (VAR19 | (~VAR13 & ~VAR15 & ~VAR18 & ~VAR14 & ~VAR4))) begin
VAR21[VAR8-1:0] <= VAR1[VAR8-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge VAR10) begin
if (!VAR10) begin
VAR21 <= 'h0;
end else begin
if (VAR16 & VAR9) begin
if (VAR4 & (VAR19 | (~VAR13 & ~VAR15 & ~VAR18 & ~VAR14))) begin
VAR21 <= VAR1;
end else if ((VAR14 & VAR3) & (~VAR19 & ~VAR13 & ~VAR15 & ~VAR18 )) begin
VAR21 <= 'h0;
end else if (VAR2 & (VAR19 | (~VAR13 & ~VAR15 & ~VAR18 & ~VAR14 & ~VAR4))) begin
VAR21 <= VAR21 <<7;
VAR21[6:0] <= VAR1[6:0];
end
end
end
end
end
endgenerate
endmodule
|
epl-1.0
|
Cosmos-OpenSSD/Cosmos-OpenSSD-plus
|
project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_eq.v
| 35,634 |
module MODULE1 #
(
parameter VAR83 = "VAR34",
parameter VAR42 = "VAR29",
parameter VAR50 = 1
)
(
input VAR108,
input VAR91,
input VAR125,
input [ 1:0] VAR86,
input [ 3:0] VAR71,
input [ 3:0] VAR23,
input [ 5:0] VAR117,
input [ 1:0] VAR98,
input [ 2:0] VAR54,
input [ 5:0] VAR32,
input [ 3:0] VAR123,
input VAR69,
input [17:0] VAR1,
input VAR115,
output VAR25,
output [ 4:0] VAR124,
output [ 6:0] VAR30,
output [ 4:0] VAR46,
output [17:0] VAR74,
output VAR12,
output [ 5:0] VAR135,
output [17:0] VAR58,
output VAR63,
output VAR61,
output VAR110,
output [ 5:0] VAR131
);
reg VAR139;
reg VAR102;
reg [ 1:0] VAR121;
reg [ 3:0] VAR84;
reg [ 5:0] VAR21;
reg [ 1:0] VAR14;
reg [ 3:0] VAR4;
reg [ 5:0] VAR93;
reg [ 1:0] VAR31;
reg [ 2:0] VAR109;
reg [ 5:0] VAR55;
reg [ 3:0] VAR76;
reg VAR49;
reg [17:0] VAR103;
reg VAR51;
reg [ 1:0] VAR129;
reg [ 2:0] VAR112;
reg [ 5:0] VAR106;
reg [ 3:0] VAR82;
reg VAR60;
reg [17:0] VAR78;
reg VAR136;
reg [18:0] VAR97 = 19'd0;
reg VAR75 = 1'd0;
reg [ 1:0] VAR17 = 2'd0;
reg [ 2:0] VAR6 = 3'd0;
reg VAR24 = 1'd0;
reg [ 3:0] VAR7 = 4'd0;
reg [17:0] VAR113 = 18'd0;
reg [ 2:0] VAR122 = 3'd0;
reg [ 5:0] VAR20 = 6'd0;
reg [ 5:0] VAR40 = 6'd0;
reg VAR70 = 1'd0;
reg [18:0] VAR39 = 19'd0;
reg VAR13 = 1'd0;
reg [ 5:0] VAR18 = 6'd0;
reg [17:0] VAR44 = 18'd0;
reg VAR65 = 1'd0;
reg VAR89 = 1'd0;
reg VAR33 = 1'd0;
reg VAR120 = 1'd0;
reg [ 5:0] VAR22 = 6'd0;
wire VAR92;
wire VAR57;
wire [17:0] VAR8;
wire VAR56;
wire VAR73;
localparam VAR114 = 6'b000001;
localparam VAR62 = 6'b000010;
localparam VAR2 = 6'b000100;
localparam VAR140 = 6'b001000;
localparam VAR19 = 6'b010000;
localparam VAR26 = 6'b100000;
localparam VAR88 = 6'b000001;
localparam VAR134 = 6'b000010;
localparam VAR95 = 6'b000100;
localparam VAR5 = 6'b001000;
localparam VAR105 = 6'b010000;
localparam VAR111 = 6'b100000;
localparam VAR45 = 6'd0; localparam VAR128 = 7'd60;
localparam VAR35 = 6'd20;
localparam VAR28 = 6'd0; localparam VAR132 = 7'd68; localparam VAR41 = 6'd13;
localparam VAR80 = 6'd0; localparam VAR126 = 7'd64;
localparam VAR9 = 6'd16;
localparam VAR79 = 6'd0; localparam VAR107 = 7'd70;
localparam VAR52 = 6'd10;
localparam VAR68 = 6'd0; localparam VAR64 = 7'd80;
localparam VAR137 = 6'd0;
localparam VAR53 = 6'd8; localparam VAR130 = 7'd72;
localparam VAR116 = 6'd0;
localparam VAR15 = 6'd10; localparam VAR100 = 7'd70;
localparam VAR3 = 6'd0;
localparam VAR87 = 6'd8; localparam VAR66 = 7'd56;
localparam VAR85 = 6'd16;
localparam VAR72 = 6'd10; localparam VAR127 = 7'd60;
localparam VAR77 = 6'd10;
localparam VAR67 = 6'd13; localparam VAR81 = 7'd68; localparam VAR16 = 6'd0;
localparam VAR37 = 6'd0; localparam VAR118 = 7'd56; localparam VAR138 = 6'd25;
always @ (posedge VAR108)
begin
if (!VAR91)
begin
VAR139 <= 1'd0;
VAR121 <= 2'd0;
VAR84 <= 4'd0;
VAR21 <= 6'd1;
VAR31 <= 2'd0;
VAR109 <= 3'd0;
VAR55 <= 6'd0;
VAR76 <= 4'd0;
VAR49 <= 1'd0;
VAR103 <= 18'd0;
VAR51 <= 1'd0;
VAR102 <= 1'd0;
VAR14 <= 2'd0;
VAR4 <= 4'd0;
VAR93 <= 6'd1;
VAR129 <= 2'd0;
VAR112 <= 3'd0;
VAR106 <= 6'd0;
VAR82 <= 4'd0;
VAR60 <= 1'd0;
VAR78 <= 18'd0;
VAR136 <= 1'd0;
end
else
begin
VAR139 <= VAR125;
VAR121 <= VAR86;
VAR84 <= VAR71;
VAR21 <= VAR117;
VAR31 <= VAR98;
VAR109 <= VAR54;
VAR55 <= VAR32;
VAR76 <= VAR123;
VAR49 <= VAR69;
VAR103 <= VAR1;
VAR51 <= VAR115;
VAR102 <= VAR139;
VAR14 <= VAR121;
VAR4 <= VAR84;
VAR93 <= VAR21;
VAR129 <= VAR31;
VAR112 <= VAR109;
VAR106 <= VAR55;
VAR82 <= VAR76;
VAR60 <= VAR49;
VAR78 <= VAR103;
VAR136 <= VAR51;
end
end
always @ (posedge VAR108)
begin
if (!VAR91)
begin
case (VAR23)
4'd0 : VAR97 <= {VAR35, VAR128, VAR45};
4'd1 : VAR97 <= {VAR41, VAR132, VAR28};
4'd2 : VAR97 <= {VAR9, VAR126, VAR80};
4'd3 : VAR97 <= {VAR52, VAR107, VAR79};
4'd4 : VAR97 <= {VAR137, VAR64, VAR68};
4'd5 : VAR97 <= {VAR116, VAR130, VAR53};
4'd6 : VAR97 <= {VAR3, VAR100, VAR15};
4'd7 : VAR97 <= {VAR85, VAR66, VAR87};
4'd8 : VAR97 <= {VAR77, VAR127, VAR72};
4'd9 : VAR97 <= {VAR16, VAR81, VAR67};
4'd10 : VAR97 <= {VAR138, VAR118, VAR37};
default : VAR97 <= 19'd4;
endcase
VAR75 <= 1'd0;
end
else
begin
if (VAR18 == VAR62)
begin
case (VAR4)
4'd0 : VAR97 <= {VAR35, VAR128, VAR45};
4'd1 : VAR97 <= {VAR41, VAR132, VAR28};
4'd2 : VAR97 <= {VAR9, VAR126, VAR80};
4'd3 : VAR97 <= {VAR52, VAR107, VAR79};
4'd4 : VAR97 <= {VAR137, VAR64, VAR68};
4'd5 : VAR97 <= {VAR116, VAR130, VAR53};
4'd6 : VAR97 <= {VAR3, VAR100, VAR15};
4'd7 : VAR97 <= {VAR85, VAR66, VAR87};
4'd8 : VAR97 <= {VAR77, VAR127, VAR72};
4'd9 : VAR97 <= {VAR16, VAR81, VAR67};
4'd10 : VAR97 <= {VAR138, VAR118, VAR37};
default : VAR97 <= 19'd4;
endcase
VAR75 <= 1'd1;
end
else
begin
VAR97 <= VAR97;
VAR75 <= 1'd0;
end
end
end
always @ (posedge VAR108)
begin
if (!VAR91)
begin
VAR18 <= VAR114;
VAR39 <= 19'd0;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
else
begin
case (VAR18)
VAR114 :
begin
case (VAR14)
2'd0 :
begin
VAR18 <= VAR114;
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
2'd1 :
begin
VAR18 <= VAR62;
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
2'd2 :
begin
VAR18 <= VAR2;
VAR39 <= {VAR93, VAR39[18:6]};
VAR17 <= 2'd1;
VAR13 <= 1'd0;
end
2'd3 :
begin
VAR18 <= VAR19;
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
default :
begin
VAR18 <= VAR114;
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
endcase
end
VAR62 :
begin
VAR18 <= (VAR75 ? VAR26 : VAR62);
VAR39 <= VAR97;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
VAR2 :
begin
VAR18 <= ((VAR17 == 2'd2) ? VAR140 : VAR2);
if (VAR17 == 2'd1)
VAR39 <= {1'd0, VAR93, VAR39[18:7]};
end
else
VAR39 <= {VAR93, VAR39[18:6]};
VAR17 <= VAR17 + 2'd1;
VAR13 <= 1'd0;
end
VAR140 :
begin
VAR18 <= VAR26;
VAR39 <= VAR39 << 1; VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
VAR19:
begin
VAR18 <= VAR26;
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
VAR26 :
begin
VAR18 <= ((VAR14 == 2'd0) ? VAR114 : VAR26);
VAR39 <= VAR39;
VAR17 <= 2'd0;
VAR13 <= 1'd1;
end
default :
begin
VAR18 <= VAR114;
VAR39 <= 19'd0;
VAR17 <= 2'd0;
VAR13 <= 1'd0;
end
endcase
end
end
always @ (posedge VAR108)
begin
if (!VAR91)
begin
VAR22 <= VAR88;
VAR6 <= 3'd0;
VAR24 <= 1'd0;
VAR7 <= 4'd0;
VAR113 <= 18'd0;
VAR122 <= 3'd0;
VAR20 <= 6'd0;
VAR40 <= 6'd0;
VAR70 <= 1'd0;
VAR44 <= 18'd0;
VAR65 <= 1'd0;
VAR89 <= 1'd0;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
else
begin
case (VAR22)
VAR88 :
begin
case (VAR129)
2'd1 :
begin
VAR22 <= VAR134;
VAR6 <= VAR112;
VAR24 <= 1'd0;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= 3'd0;
VAR20 <= VAR20;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= 1'd0;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
2'd2 :
begin
VAR22 <= VAR95;
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR82;
VAR113 <= {VAR93, VAR113[17:6]};
VAR122 <= 3'd1;
VAR20 <= VAR106;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
2'd3 :
begin
VAR22 <= VAR95;
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR82;
VAR113 <= {VAR93, VAR113[17:6]};
VAR122 <= 3'd1;
VAR20 <= VAR106;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
default :
begin
VAR22 <= VAR88;
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= 3'd0;
VAR20 <= VAR20;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
endcase
end
VAR134 :
begin
VAR22 <= (VAR57 ? VAR111 : VAR134);
VAR6 <= VAR112;
VAR24 <= 1'd1;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= 3'd0;
VAR20 <= VAR20;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
VAR95 :
begin
VAR22 <= ((VAR122 == 3'd2) ? VAR5 : VAR95);
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR82;
VAR113 <= {VAR93, VAR113[17:6]};
VAR122 <= VAR122 + 2'd1;
VAR20 <= VAR20;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd1;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
VAR5 :
begin
VAR22 <= ((VAR122 == 3'd7) ? VAR105 : VAR5);
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= VAR122 + 2'd1;
VAR20 <= VAR20;
VAR40 <= ((VAR122 == 3'd7) ? VAR106 : VAR40);
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= 1'd1;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
VAR105 :
begin
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= 3'd0;
VAR20 <= VAR20;
VAR40 <= VAR40;
if (VAR56)
begin
VAR22 <= VAR111;
VAR70 <= 1'd0;
VAR44 <= VAR92 ? {14'd0, VAR8[3:0]} : VAR8;
VAR65 <= VAR92;
VAR89 <= VAR73 || VAR89;
VAR33 <= VAR73 || VAR89;
VAR120 <= 1'd1;
end
else
begin
VAR22 <= VAR105;
VAR70 <= 1'd1;
VAR44 <= VAR44;
VAR65 <= 1'd0;
VAR89 <= VAR89;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
end
VAR111 :
begin
VAR22 <= ((VAR129 == 2'd0) ? VAR88 : VAR111);
VAR6 <= VAR6;
VAR24 <= 1'd0;
VAR7 <= VAR7;
VAR113 <= VAR113;
VAR122 <= 3'd0;
VAR20 <= VAR20;
VAR40 <= VAR40;
VAR70 <= 1'd0;
VAR44 <= VAR44;
VAR65 <= VAR65;
VAR89 <= VAR89;
VAR33 <= VAR33;
VAR120 <= 1'd1;
end
default :
begin
VAR22 <= VAR88;
VAR6 <= 3'd0;
VAR24 <= 1'd0;
VAR7 <= 4'd0;
VAR113 <= 18'd0;
VAR122 <= 3'd0;
VAR20 <= 6'd0;
VAR40 <= 6'd0;
VAR70 <= 1'd0;
VAR44 <= 18'd0;
VAR65 <= 1'd0;
VAR89 <= 1'd0;
VAR33 <= 1'd0;
VAR120 <= 1'd0;
end
endcase
end
end
VAR101 #
(
.VAR83 (VAR83),
.VAR42 (VAR42),
.VAR50 (VAR50)
)
VAR96
(
.VAR119 (VAR108),
.VAR10 (VAR91),
.VAR94 (VAR129),
.VAR11 (VAR20),
.VAR43 (VAR40),
.VAR133 (VAR6),
.VAR36 (VAR24),
.VAR47 (VAR7),
.VAR27 (VAR113),
.VAR59 (VAR70),
.VAR104 (VAR57),
.VAR38 (VAR8),
.VAR99 (VAR56),
.VAR48 (VAR92),
.VAR90 (VAR73)
);
assign VAR25 = VAR39[0];
assign VAR124 = VAR102 ? VAR39[ 4: 0] : 5'h00;
assign VAR30 = VAR102 ? VAR39[12: 6] : 7'h00;
assign VAR46 = VAR102 ? VAR39[17:13] : 5'h00;
assign VAR74 = {1'd0, VAR39[18:14], VAR39[12:7], 1'd0, VAR39[5:1]}; assign VAR12 = VAR13;
assign VAR135 = VAR18;
assign VAR58 = VAR60 ? VAR78 : VAR44;
assign VAR63 = VAR60 ? VAR136 : VAR65;
assign VAR61 = VAR33;
assign VAR110 = VAR120;
assign VAR131 = VAR22;
endmodule
|
gpl-3.0
|
impedimentToProgress/ProbableCause
|
ddr2/cores/ram_wb/ram_wb_b3.v
| 7,673 |
module MODULE1(
VAR22, VAR31, VAR33, VAR3, VAR29, VAR26,
VAR7, VAR27,
VAR28, VAR37, VAR9, VAR30,
VAR2, VAR8);
parameter VAR16 = 32;
parameter VAR14 = 32;
input [VAR14-1:0] VAR22;
input [1:0] VAR31;
input [2:0] VAR33;
input VAR3;
input [VAR16-1:0] VAR29;
input [3:0] VAR26;
input VAR7;
input VAR27;
output VAR28;
output VAR37;
output VAR9;
output [VAR16-1:0] VAR30;
input VAR2;
input VAR8;
parameter VAR38 = 32'h00020000; parameter VAR5 = 17;
parameter VAR6 = (VAR16/8);
parameter VAR15 = 2; parameter VAR10 = (VAR38/VAR6);
reg [VAR16-1:0] VAR20 [0:VAR10-1] ;
reg [(VAR5-VAR15)-1:0] VAR4;
wire [31:0] VAR32;
reg VAR21;
wire VAR11, VAR25;
reg [VAR5-VAR15-1:0] VAR1;
reg [2:0] VAR17;
reg [1:0] VAR24;
wire VAR36;
wire VAR18;
wire VAR34;
assign VAR11 = ((VAR33 == 3'b001)|(VAR33 == 3'b010)) &
VAR7 & !VAR21;
assign VAR25 = ((VAR33 == 3'b111) &
VAR7 & VAR21 & VAR28) | VAR37;
always @(posedge VAR2)
if (VAR8)
VAR21 <= 0;
else if (VAR11)
VAR21 <= 1;
else if (VAR25)
VAR21 <= 0;
always @(VAR28 or VAR21 or VAR11
or VAR24 or VAR17 or VAR22 or VAR4)
if (VAR11)
VAR1 = VAR22[VAR5-1:2];
else if ((VAR17 == 3'b010) & VAR28 & VAR21)
begin
if (VAR24 == 2'b00) VAR1 = VAR4 + 1;
if (VAR24 == 2'b01) VAR1[1:0] = VAR4[1:0] + 1;
if (VAR24 == 2'b10) VAR1[2:0] = VAR4[2:0] + 1;
if (VAR24 == 2'b11) VAR1[3:0] = VAR4[3:0] + 1;
end
always @(posedge VAR2)
VAR24 <= VAR31;
always @(posedge VAR2)
VAR17 <= VAR33;
assign VAR36 = VAR21;
assign VAR18 = (VAR36 &
(VAR4 != VAR22[VAR5-1:2]));
always@(posedge VAR2)
if(VAR8)
VAR4 <= 0;
else if (VAR36)
VAR4 <= VAR1;
else if (VAR3 & VAR7)
VAR4 <= VAR22[VAR5-1:2];
reg [(VAR5-VAR15)-1:0] VAR35;
always@(*)
if(VAR8)
VAR35 = 0;
else if (VAR36)
VAR35 = VAR1;
else if (VAR3 & VAR7)
VAR35 = VAR22[VAR5-1:2];
parameter VAR13 = "VAR23.VAR19";
integer VAR12;
begin
begin
begin
begin
begin
end
begin
end
begin
end
begin
|
mit
|
stanford-ppl/spatial-lang
|
spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_controller.v
| 12,012 |
module MODULE1
parameter VAR42 = 6,
parameter VAR34 = 0,
parameter VAR45 = 0,
parameter VAR76 = 0,
parameter VAR68 = 0,
parameter VAR21 = 0,
parameter VAR70 = 0,
parameter VAR46 = 0,
parameter VAR77 = 0,
parameter VAR64 = 0,
parameter VAR44 = 0,
parameter VAR40 = 0,
parameter VAR20 = 0,
parameter VAR31 = 0,
parameter VAR32 = 0,
parameter VAR61 = 0,
parameter VAR14 = 0,
parameter VAR47 = "VAR75",
parameter VAR56 = 2,
parameter VAR50 = 0,
parameter VAR72 = 3,
parameter VAR71 = 11,
parameter VAR38 = 4,
parameter VAR9 = 0
)
(
input VAR67,
input VAR27,
input VAR30,
input VAR55,
input VAR25,
input VAR79,
input VAR26,
input VAR66,
input VAR62,
input VAR12,
input VAR51,
input VAR48,
input VAR16,
input VAR28,
input VAR22,
input VAR65,
input VAR36,
input VAR63,
input VAR4,
input VAR17,
input VAR2,
input VAR74,
input VAR5,
input VAR43,
input VAR24,
input VAR41,
input VAR60,
input VAR19,
input VAR78,
input VAR29,
input VAR8,
input VAR10,
input clk,
output reg VAR53,
output reg VAR18
);
localparam VAR33 = (VAR47 == "VAR75");
localparam VAR3 = 3;
localparam VAR11 = VAR3 + VAR72;
localparam VAR6 = VAR72 > VAR38 ? VAR72 : VAR38;
localparam VAR54 = (VAR3 > VAR6) ?
VAR71 + 1 :
(
(VAR71 > VAR6)?
VAR71 + (VAR6 - VAR3 + 1) + 1 :
VAR71 + VAR38 + VAR72 - VAR3 + 2
);
localparam VAR52 = VAR38 + 1;
wire VAR49;
wire VAR69;
wire VAR1;
wire VAR39;
reg [VAR11: 0] VAR23;
reg [VAR54-1: 0] VAR59;
reg VAR80;
reg VAR57;
assign VAR49 = (
VAR67 |
VAR27 |
VAR30 |
VAR55 |
VAR25 |
VAR79 |
VAR26 |
VAR66 |
VAR62 |
VAR12 |
VAR51 |
VAR48 |
VAR16 |
VAR28 |
VAR22 |
VAR65
);
assign VAR69 = (
( (VAR34 == 1) ? VAR36 : 1'b0) |
( (VAR45 == 1) ? VAR63 : 1'b0) |
( (VAR76 == 1) ? VAR4 : 1'b0) |
( (VAR68 == 1) ? VAR17 : 1'b0) |
( (VAR21 == 1) ? VAR2 : 1'b0) |
( (VAR70 == 1) ? VAR74 : 1'b0) |
( (VAR46 == 1) ? VAR5 : 1'b0) |
( (VAR77 == 1) ? VAR43 : 1'b0) |
( (VAR64 == 1) ? VAR24 : 1'b0) |
( (VAR44 == 1) ? VAR41 : 1'b0) |
( (VAR40 == 1) ? VAR60 : 1'b0) |
( (VAR20 == 1) ? VAR19 : 1'b0) |
( (VAR31 == 1) ? VAR78 : 1'b0) |
( (VAR32 == 1) ? VAR29 : 1'b0) |
( (VAR61 == 1) ? VAR8 : 1'b0) |
( (VAR14 == 1) ? VAR10 : 1'b0)
);
generate if (VAR47 == "none" && (VAR50==0)) begin
assign VAR1 = VAR49;
assign VAR39 = VAR69;
end else begin
VAR7
.VAR73 (VAR56),
.VAR33(VAR50? 1'b1 : VAR33)
)
VAR13
(
.clk (clk),
.VAR15 (VAR49),
.VAR53 (VAR1)
);
VAR7
.VAR73 (VAR56),
.VAR33(0)
)
VAR37
(
.clk (clk),
.VAR15 (VAR69),
.VAR53 (VAR39)
);
end
endgenerate
generate if ( ( (VAR50 == 0) && (VAR9==0) )|
( (VAR9 == 1) && (VAR47 != "VAR75") ) ) begin
always @* begin
VAR53 = VAR1;
VAR18 = VAR39;
end
end else if ( (VAR50 == 0) && (VAR9==1) ) begin
wire VAR58;
VAR7
.VAR73 (VAR56+1),
.VAR33(0)
)
VAR35
(
.clk (clk),
.VAR15 (VAR1),
.VAR53 (VAR58)
);
always @* begin
VAR53 = VAR58;
VAR18 = VAR39;
end
end
else begin
begin
begin
begin
begin
begin
end
begin
begin
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_term_up.v
| 1,120 |
module MODULE1 (
VAR1, out
);
inout out;
input VAR1;
endmodule
|
gpl-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/xnor2/sky130_fd_sc_hvl__xnor2.symbol.v
| 1,305 |
module MODULE1 (
input VAR7,
input VAR6,
output VAR3
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.blackbox.v
| 1,323 |
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule
|
apache-2.0
|
ShepardSiegel/ocpi
|
coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_blk_ll_credit.v
| 36,978 |
module MODULE1
parameter VAR109 = 0,
parameter VAR37 = 4,
parameter VAR201 = 9,
parameter VAR89 = 12,
parameter VAR148 = 72'h6808682C6808680CFF, parameter VAR179 = 96'h406044644C6C2024282C3034,
parameter VAR144 = 3'b101,
parameter VAR122 = 0,
parameter VAR13 = 0,
parameter VAR90 = 0,
parameter VAR196 = 0,
parameter VAR52 = 0,
parameter VAR77 = 0,
parameter VAR189 = 0
)
(
input wire clk,
input wire VAR59,
output reg [6:0] VAR41,
input wire [11:0] VAR192,
output reg [7:0] VAR25 = 0,
output reg [7:0] VAR15 = 0,
output reg [7:0] VAR173 = 0,
output reg VAR114 = 0,
output reg [11:0] VAR199 = 0,
output reg [11:0] VAR26 = 0,
output reg [11:0] VAR205 = 0,
input VAR44,
output reg [7:0] VAR116 = 0,
output reg [11:0] VAR50 = 0,
output reg [7:0] VAR164 = 0,
output wire [11:0] VAR103,
output wire [7:0] VAR54,
output wire [11:0] VAR121,
input wire VAR146,
output reg [7:0] VAR202 = 0,
output reg VAR92 = 0,
output reg [7:0] VAR149 = 0,
output reg [11:0] VAR31 = 0,
output reg [11:0] VAR66 = 0,
output reg [11:0] VAR22 = 0,
output reg [11:0] VAR131 = 0,
output reg [11:0] VAR190 = 0,
output wire [11:0] VAR105,
input wire VAR206,
output reg VAR115 = 1,
output reg VAR64 = 1,
output reg VAR81 = 1,
input wire VAR38
);
reg [11:0] VAR75 = 0;
reg [11:0] VAR29 = 0;
reg [11:0] VAR145 = 0;
reg [11:0] VAR111 = 0;
reg [6:0] VAR39 = 0;
wire VAR62;
reg VAR94 = 0;
wire VAR71;
reg VAR176 = 0;
reg VAR141 = 0;
reg VAR104 = 0;
reg VAR150 = 0;
reg VAR107 = 0;
reg VAR182 = 0;
reg VAR99 = 0;
reg VAR154 = 0;
reg VAR65 = 0;
reg VAR187 = 0;
reg VAR127 = 0;
reg VAR30 = 0;
reg VAR134 = 0;
reg VAR58 = 0;
reg VAR63 = 0;
reg VAR143 = 0;
reg VAR1 = 0;
reg VAR3 = 0;
reg VAR124 = 0;
reg VAR53 = 0;
reg VAR169 = 0;
reg VAR125 = 0;
reg VAR69 = 0;
reg VAR61 = 0;
reg VAR76 = 0;
reg VAR194 = 0;
reg VAR181 = 0;
reg VAR98 = 0;
reg VAR113 = 0;
reg VAR73 = 0;
reg VAR151 = 0;
reg VAR139 = 0;
reg VAR11 = 0;
reg VAR97 = 0;
reg VAR185 = 0;
reg VAR19 = 0;
reg VAR156 = 0;
reg VAR172 = 0;
reg VAR161 = 0;
reg VAR68 = 0;
reg VAR46 = 0;
reg VAR106 = 0;
reg [11:0] VAR126 = 0;
reg [11:0] VAR130 = 0;
reg [11:0] VAR36 = 0;
reg [11:0] VAR23 = 0;
reg [11:0] VAR20 = 0;
reg [11:0] VAR174 = 0;
wire [7:0] VAR60;
wire [1:0] VAR142;
wire [6:0] VAR133;
wire [6:0] VAR84;
wire [7:0] VAR157;
wire [1:0] VAR27;
wire [6:0] VAR102;
reg [3:0] VAR167 = (VAR201 - 1)%16;
wire VAR42;
reg [4:0] VAR184 = 0;
reg VAR9 = 1;
integer VAR180,VAR87;
assign VAR103 = 0;
assign VAR54 = 0;
assign VAR121 = 0;
localparam VAR155 = 2'b00;
localparam VAR74 = 3'b000;
localparam VAR14 = 3'b001;
localparam VAR137 = 3'b010;
localparam VAR168 = 3'b011;
localparam VAR24 = 3'b100;
localparam VAR91 = 3'b101;
localparam VAR129 = 2'b00;
localparam VAR34 = 2'b01;
localparam VAR112 = 2'b10;
localparam VAR147 = 2'b11;
function integer VAR162 (input integer VAR186);
begin
if (VAR186%16 == 0) VAR162 = VAR186/16;
end
else VAR162 = (VAR186[31:4]+1);
end
endfunction
function integer VAR28 (input integer VAR170, input reg [127:0] VAR110,
input integer VAR10, input integer VAR162);
integer VAR160;
begin
for (VAR160=0; VAR160<VAR162*16; VAR160=VAR160+1)
if (VAR160>=VAR10)
VAR28[VAR160] = 0;
end
else
VAR28[VAR160] = VAR110[VAR170 + VAR160*8];
end
endfunction
function integer VAR21 (input integer VAR170, input reg [127:0] VAR110,
input integer VAR10, input integer VAR162);
integer VAR160;
reg [5:0] VAR119;
begin
for (VAR160=0; VAR160<VAR162*16; VAR160=VAR160+1) begin
VAR119[5] = VAR110[VAR160*8+7];
VAR119[4] = VAR110[VAR160*8+6];
VAR119[3] = VAR110[VAR160*8+5];
VAR119[2] = VAR110[VAR160*8+4];
VAR119[1] = VAR110[VAR160*8+3];
VAR119[0] = VAR110[VAR160*8+2];
if (VAR160>=VAR10)
VAR21[VAR160] = 0;
end
else if ((VAR119[5:0] == { VAR129 , VAR168 }) ||
(VAR119[5:0] == { VAR34 , VAR168 }))
end
VAR21[VAR160] = 1; else if ((VAR119[5:0] == { VAR129 , VAR24 }) ||
(VAR119[5:0] == { VAR34 , VAR24 }))
VAR21[VAR160] = VAR170; else if ((VAR119[5:0] == { VAR129 , VAR91 }) ||
(VAR119[5:0] == { VAR34 , VAR91 }))
VAR21[VAR160] = !VAR170; else
VAR21[VAR160] = 0; end
end
endfunction
parameter VAR57 = VAR162(VAR201);
parameter VAR135 = VAR162(VAR89);
parameter [VAR57*16-1:0] VAR6 = VAR21(1, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR128 = VAR21(0, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR163 = VAR28(7, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR93 = VAR28(6, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR177 = VAR28(5, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR70 = VAR28(4, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR153 = VAR28(3, VAR148,VAR201,VAR57);
parameter [VAR57*16-1:0] VAR83 = VAR28(2, VAR148,VAR201,VAR57);
parameter [VAR135*16-1:0] VAR7 = VAR28(6, VAR179,VAR89,VAR135);
parameter [VAR135*16-1:0] VAR120 = VAR28(5, VAR179,VAR89,VAR135);
parameter [VAR135*16-1:0] VAR198 = VAR28(4, VAR179,VAR89,VAR135);
parameter [VAR135*16-1:0] VAR33 = VAR28(3, VAR179,VAR89,VAR135);
parameter [VAR135*16-1:0] VAR8 = VAR28(2, VAR179,VAR89,VAR135);
parameter VAR158 = (VAR89 - 1)%16;
always @(posedge clk) begin
if (~VAR59) begin
VAR167 <= #VAR82 (VAR201 - 1)%16;
end else if (!VAR42) begin
VAR167 <= #VAR82 VAR167 - 1;
end
end
always @(posedge clk) begin
if (~VAR59) begin
VAR9 <= #VAR82 1;
VAR184 <= #VAR82 'h0;
end else begin
if (VAR184 < 'd16) begin
VAR184 <= #VAR82 VAR184 + 1;
VAR9 <= #VAR82 1;
end else begin
VAR9 <= #VAR82 0;
end
end
end
assign VAR42 = !((!VAR115 && (VAR142[1:0]==2'b11)) ||
(!VAR64 && (VAR142[1:0]==2'b10) && VAR122) ||
(!VAR81 && (VAR142[1:0]==2'b01)));
assign VAR60[1:0] = 2'b00;
assign VAR133[1:0] = 2'b00;
assign VAR157[1:0] = 2'b00;
assign VAR102[1:0] = 2'b00;
genvar VAR197;
generate for (VAR197=0; VAR197<VAR57; VAR197=VAR197+1) begin: VAR101
VAR43 #(.VAR12(VAR6[15:0])) VAR152
(.VAR85(VAR27[1]),.VAR123(VAR27[1]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR128[15:0])) VAR88
(.VAR85(VAR27[0]),.VAR123(VAR27[0]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR163[15:0])) VAR2
(.VAR85(VAR157[7]),.VAR123(VAR157[7]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR93[15:0])) VAR51
(.VAR85(VAR157[6]),.VAR123(VAR157[6]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR177[15:0])) VAR55
(.VAR85(VAR157[5]),.VAR123(VAR157[5]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR70[15:0])) VAR16
(.VAR85(VAR157[4]),.VAR123(VAR157[4]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR153[15:0])) VAR117
(.VAR85(VAR157[3]),.VAR123(VAR157[3]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
VAR43 #(.VAR12(VAR83[15:0])) VAR140
(.VAR85(VAR157[2]),.VAR123(VAR157[2]),.VAR67(clk),.VAR100(VAR42),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]));
end
endgenerate
genvar VAR79;
generate for (VAR79=0; VAR79<VAR57; VAR79=VAR79+1) begin: VAR49
MODULE2 #(.VAR12(VAR6[15:0])) VAR152
(.VAR85(VAR142[1]),.VAR123(VAR142[1]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR128[15:0])) VAR88
(.VAR85(VAR142[0]),.VAR123(VAR142[0]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR163[15:0])) VAR2
(.VAR85(VAR60[7]),.VAR123(VAR60[7]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR93[15:0])) VAR51
(.VAR85(VAR60[6]),.VAR123(VAR60[6]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR177[15:0])) VAR55
(.VAR85(VAR60[5]),.VAR123(VAR60[5]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR70[15:0])) VAR16
(.VAR85(VAR60[4]),.VAR123(VAR60[4]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR153[15:0])) VAR117
(.VAR85(VAR60[3]),.VAR123(VAR60[3]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
MODULE2 #(.VAR12(VAR83[15:0])) VAR140
(.VAR85(VAR60[2]),.VAR123(VAR60[2]),.VAR67(clk),.VAR100(VAR42 & VAR59),
.VAR200(VAR167[3]),.VAR95(VAR167[2]),.VAR171(VAR167[1]),.VAR45(VAR167[0]),
.VAR78(VAR59));
end
endgenerate
assign VAR84[6] = 0;
MODULE2 #(.VAR12(16'b1111110111111011)) VAR188
(.VAR85(VAR84[5]),.VAR123(VAR84[5]),.VAR67(clk),.VAR100(1'b1),
.VAR200(1'b1),.VAR95(1'b1),.VAR171(1'b1),.VAR45(1'b1), .VAR78(VAR59));
MODULE2 #(.VAR12(16'b0000111000011100)) VAR86
(.VAR85(VAR84[4]),.VAR123(VAR84[4]),.VAR67(clk),.VAR100(1'b1),
.VAR200(1'b1),.VAR95(1'b1),.VAR171(1'b1),.VAR45(1'b1), .VAR78(VAR59));
MODULE2 #(.VAR12(16'b0011000001100000)) VAR4
(.VAR85(VAR84[3]),.VAR123(VAR84[3]),.VAR67(clk),.VAR100(1'b1),
.VAR200(1'b1),.VAR95(1'b1),.VAR171(1'b1),.VAR45(1'b1), .VAR78(VAR59));
MODULE2 #(.VAR12(16'b0101011010101101)) VAR40
(.VAR85(VAR84[2]),.VAR123(VAR84[2]),.VAR67(clk),.VAR100(1'b1),
.VAR200(1'b1),.VAR95(1'b1),.VAR171(1'b1),.VAR45(1'b1), .VAR78(VAR59));
assign VAR84[1] = 0;
assign VAR84[0] = 0;
genvar VAR159;
generate for (VAR159=0; VAR159<VAR135; VAR159=VAR159+1) begin: VAR96
VAR43 #(.VAR12(VAR7[15:0])) VAR138
(.VAR85(VAR102[6]),.VAR123(VAR102[6]),.VAR67(clk),.VAR100(VAR60[7]),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]));
VAR43 #(.VAR12(VAR120[15:0])) VAR203
(.VAR85(VAR102[5]),.VAR123(VAR102[5]),.VAR67(clk),.VAR100(VAR60[7]),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]));
VAR43 #(.VAR12(VAR198[15:0])) VAR80
(.VAR85(VAR102[4]),.VAR123(VAR102[4]),.VAR67(clk),.VAR100(VAR60[7]),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]));
VAR43 #(.VAR12(VAR33[15:0])) VAR18
(.VAR85(VAR102[3]),.VAR123(VAR102[3]),.VAR67(clk),.VAR100(VAR60[7]),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]));
VAR43 #(.VAR12(VAR8[15:0])) VAR204
(.VAR85(VAR102[2]),.VAR123(VAR102[2]),.VAR67(clk),.VAR100(VAR60[7]),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]));
end
endgenerate
genvar VAR165;
generate for (VAR165=0; VAR165<VAR135; VAR165=VAR165+1) begin: VAR47
MODULE2 #(.VAR12(VAR7[15:0])) VAR138
(.VAR85(VAR133[6]),.VAR123(VAR133[6]),.VAR67(clk),.VAR100(VAR60[7] & VAR59),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]), .VAR78(VAR59));
MODULE2 #(.VAR12(VAR120[15:0])) VAR203
(.VAR85(VAR133[5]),.VAR123(VAR133[5]),.VAR67(clk),.VAR100(VAR60[7] & VAR59),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]), .VAR78(VAR59));
MODULE2 #(.VAR12(VAR198[15:0])) VAR80
(.VAR85(VAR133[4]),.VAR123(VAR133[4]),.VAR67(clk),.VAR100(VAR60[7] & VAR59),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]), .VAR78(VAR59));
MODULE2 #(.VAR12(VAR33[15:0])) VAR18
(.VAR85(VAR133[3]),.VAR123(VAR133[3]),.VAR67(clk),.VAR100(VAR60[7] & VAR59),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]), .VAR78(VAR59));
MODULE2 #(.VAR12(VAR8[15:0])) VAR204
(.VAR85(VAR133[2]),.VAR123(VAR133[2]),.VAR67(clk),.VAR100(VAR60[7] & VAR59),
.VAR200(VAR158[3]),.VAR95(VAR158[2]),.VAR171(VAR158[1]),.VAR45(VAR158[0]), .VAR78(VAR59));
end
endgenerate
always @(posedge clk) begin
if (~VAR59 || VAR44) begin
VAR41 <= #VAR82 'h0;
VAR39 <= #VAR82 'h0;
VAR53 <= #VAR82 1'b0;
VAR125 <= #VAR82 1'b0;
VAR61 <= #VAR82 1'b0;
VAR169 <= #VAR82 1'b0;
VAR69 <= #VAR82 1'b0;
VAR94 <= #VAR82 1'b0;
VAR76 <= #VAR82 1'b0;
VAR150 <= #VAR82 1'b0;
VAR176 <= #VAR82 1'b0;
VAR141 <= #VAR82 1'b0;
VAR104 <= #VAR82 1'b0;
VAR154 <= #VAR82 1'b0;
VAR65 <= #VAR82 1'b0;
VAR187 <= #VAR82 1'b0;
VAR127 <= #VAR82 1'b0;
VAR30 <= #VAR82 1'b0;
VAR134 <= #VAR82 1'b0;
end else begin
VAR41 <= #VAR82 {VAR9 ? VAR84[6:2] : VAR60[7] ? VAR133[6:2] : VAR60[6:2], VAR155};
VAR39 <= #VAR82 VAR41;
VAR53 <= #VAR82 VAR39[6:2] == {VAR112,VAR74}; VAR125 <= #VAR82 VAR39[6:2] == {VAR112,VAR14}; VAR61 <= #VAR82 VAR39[6:2] == {VAR112,VAR168}; VAR169 <= #VAR82 VAR39[6:2] == {VAR147,VAR74}; VAR69 <= #VAR82 VAR39[6:2] == {VAR147,VAR14}; VAR94 <= #VAR82 VAR39[6:2] == {VAR147,VAR137}; VAR76 <= #VAR82 VAR39[6:2] == {VAR147,VAR168}; VAR150 <= #VAR82 VAR39[6:2] == {VAR129,VAR137}; VAR176 <= #VAR82 VAR39[6:2] == {VAR129,VAR168}; VAR141 <= #VAR82 VAR39[6:2] == {VAR129,VAR24}; VAR104 <= #VAR82 VAR39[6:2] == {VAR129,VAR91}; VAR154 <= #VAR82 VAR39[6:2] == {VAR34, VAR74}; VAR65 <= #VAR82 VAR39[6:2] == {VAR34, VAR14}; VAR187 <= #VAR82 VAR39[6:2] == {VAR34, VAR137}; VAR127 <= #VAR82 VAR39[6:2] == {VAR34, VAR168}; VAR30 <= #VAR82 VAR39[6:2] == {VAR34, VAR24}; VAR134 <= #VAR82 VAR39[6:2] == {VAR34, VAR91}; end
end
assign VAR62 = VAR94;
assign VAR71 = VAR150;
always @(posedge clk) begin
if (~VAR59) begin
VAR202 <= #VAR82 0;
VAR92 <= #VAR82 0;
end else if (VAR62) begin
VAR202 <= #VAR82 VAR192[7:0];
VAR92 <= #VAR82 (VAR192[7:0] != VAR202);
end else begin
VAR92 <= #VAR82 0;
end
end
always @(posedge clk) begin
if (~VAR59) begin
VAR149 <= #VAR82 0;
end else if (VAR71) begin
VAR149 <= #VAR82 VAR192[7:0];
end
end
always @(posedge clk) begin
if (~VAR59) begin
VAR107 <= #VAR82 0;
VAR182 <= #VAR82 0;
VAR99 <= #VAR82 0;
VAR66 <= #VAR82 0;
VAR31 <= #VAR82 0;
VAR131 <= #VAR82 0;
VAR22 <= #VAR82 0;
VAR130 <= #VAR82 0;
VAR36 <= #VAR82 0;
VAR126 <= #VAR82 0;
VAR23 <= #VAR82 'h0;
VAR190 <= #VAR82 0;
VAR20 <= #VAR82 'h0;
end else begin
VAR107 <= #VAR82 VAR176;
VAR182 <= #VAR82 VAR141;
VAR99 <= #VAR82 VAR104;
if (VAR107) begin
VAR66 <= #VAR82 VAR174[11:0];
VAR31 <= #VAR82 VAR199 - VAR174[11:0];
end
if (VAR122 && VAR182) begin
VAR131 <= #VAR82 VAR174[11:0];
VAR22 <= #VAR82 VAR26 - VAR174[11:0];
end
if (VAR99) begin
VAR126 <= #VAR82 VAR174[11:0];
VAR23<= #VAR82 VAR174[11:0] - VAR126;
VAR190 <= #VAR82 VAR205 - VAR174[11:0];
end else begin
VAR23<= #VAR82 'h0;
end
VAR130 <= #VAR82 VAR130 + VAR23;
VAR36 <= #VAR82 VAR130 - VAR20;
if (VAR206)
VAR20 <= #VAR82 0;
end
else
VAR20 <= #VAR82 VAR20 + VAR38;
end
end
assign VAR105 = VAR130;
always @(posedge clk) begin
if (~VAR59) begin
VAR194 <= #VAR82 0;
VAR181 <= #VAR82 0;
VAR98 <= #VAR82 0;
VAR113 <= #VAR82 0;
VAR73 <= #VAR82 0;
VAR151 <= #VAR82 0;
VAR139 <= #VAR82 0;
VAR11<= #VAR82 0;
VAR97 <= #VAR82 0;
VAR75 <= #VAR82 0;
VAR29 <= #VAR82 0;
VAR145 <= #VAR82 0;
VAR111 <= #VAR82 0;
VAR116 <= #VAR82 0;
VAR164 <= #VAR82 0;
VAR50 <= #VAR82 0;
end else begin
VAR194 <= #VAR82 VAR53;
VAR181 <= #VAR82 VAR125;
VAR98 <= #VAR82 VAR61;
VAR113 <= #VAR82 VAR169;
VAR73 <= #VAR82 VAR69;
VAR151 <= #VAR82 VAR76;
VAR139 <= #VAR82 VAR113;
VAR11<= #VAR82 VAR73;
VAR97 <= #VAR82 VAR151;
if (VAR194)
VAR75 <= #VAR82 VAR174;
if (VAR181)
VAR29 <= #VAR82 VAR174;
if (VAR98)
VAR145 <= #VAR82 VAR174;
if (VAR113 || VAR73 || VAR151)
VAR111 <= #VAR82 VAR174;
if (VAR139)
VAR116 <= #VAR82 VAR75 - VAR111;
if (VAR11)
VAR164 <= #VAR82 VAR29 - VAR111;
if (VAR97)
VAR50 <= #VAR82 VAR145 - VAR111;
end
end
always @(posedge clk) begin
if (~VAR59) begin
VAR174 <= #VAR82 'h0;
VAR58 <= #VAR82 1'b0;
VAR63 <= #VAR82 1'b0;
VAR143 <= #VAR82 1'b0;
VAR1 <= #VAR82 1'b0;
VAR3 <= #VAR82 1'b0;
VAR124 <= #VAR82 1'b0;
VAR25 <= #VAR82 'h0;
VAR15 <= #VAR82 'h0;
VAR173 <= #VAR82 'h0;
VAR199 <= #VAR82 'h0;
VAR26 <= #VAR82 'h0;
VAR205 <= #VAR82 'h0;
VAR185 <= #VAR82 1'b0;
VAR19 <= #VAR82 1'b0;
VAR114 <= #VAR82 1'b0;
VAR156 <= #VAR82 1'b0;
VAR172 <= #VAR82 1'b0;
VAR161 <= #VAR82 1'b0;
end else begin
VAR174 <= #VAR82 VAR192;
VAR58 <= #VAR82 VAR154;
VAR63 <= #VAR82 VAR65;
VAR143 <= #VAR82 VAR187;
VAR1 <= #VAR82 VAR127;
VAR3 <= #VAR82 VAR30;
VAR124 <= #VAR82 VAR134;
if (VAR58) begin
VAR25 <= #VAR82 VAR174[7:0];
VAR185 <= #VAR82 1'b1;
end
if (VAR63) begin
VAR15 <= #VAR82 VAR174[7:0];
VAR19 <= #VAR82 1'b1;
end
if (VAR143) begin
VAR173 <= #VAR82 VAR174[7:0];
VAR114 <= #VAR82 1'b1;
end
if (VAR1) begin
VAR199 <= #VAR82 (VAR174[11:0] == 0) ? 12'hfff :
VAR174[11:0];
VAR156 <= #VAR82 1'b1;
end
if (VAR3) begin
VAR26 <= #VAR82 (VAR174[11:0] == 0) ? 12'hfff :
VAR174[11:0];
VAR172 <= #VAR82 1'b1;
end
if (VAR124) begin
VAR205 <= #VAR82 VAR174[11:0];
VAR161 <= #VAR82 1'b1;
end
end
end
always @(posedge clk) begin
if (~VAR59) begin
VAR115 <= #VAR82 1'b1; VAR64 <= #VAR82 1'b1; VAR81 <= #VAR82 1'b1; VAR68 <= #VAR82 1'b0;
VAR46 <= #VAR82 1'b0;
VAR106 <= #VAR82 1'b0;
end else begin
if (!VAR68 && VAR185 && VAR156) begin
VAR115 <= #VAR82 VAR199 < (VAR25*8*(2**VAR144));
VAR68 <= #VAR82 1'b1;
end
if (!VAR46 && VAR19 && VAR172) begin
VAR64 <= #VAR82 (VAR26 < VAR15) && VAR122;
VAR46 <= #VAR82 1'b1;
end
if (!VAR106 && VAR114 && VAR161) begin
VAR81 <= #VAR82 VAR205 < (VAR173*8*(2**VAR144));
VAR106 <= #VAR82 1'b1;
end
end
end
VAR35: assert property (@(posedge clk)
VAR59[*256] | (VAR13<VAR90*8*(VAR144+1)) ? VAR115 : ~VAR115
end
) else
VAR17: assert property (@(posedge clk)
VAR59[*256] | ((VAR196<VAR52)&&VAR122) ? VAR64 : ~VAR64
end
) else
VAR175: assert property (@(posedge clk)
VAR59[*256] | (VAR77<VAR189*8*(VAR144+1)) ? VAR81 : ~VAR81
end
) else
VAR5: assert property (@(posedge clk)
VAR59[*256] #VAR115 | ##[1:16] (VAR41 == 7'h2C)
end
) else
VAR191: assert property (@(posedge clk)
VAR59[*256] #VAR115 | ##[1:16] (VAR41 == 7'h0C)
end
) else
VAR56: assert property (@(posedge clk)
VAR59[*256] #((VAR60[6:0]==7'h2C) || (VAR60[6:0]==7'h0C))| VAR115
end
) else
VAR178: assert property (@(posedge clk)
VAR59[*256] #VAR64 | ##[1:16] (VAR41 == 7'h30)
end
) else
VAR118: assert property (@(posedge clk)
VAR59[*256] #VAR64 | ##[1:16] (VAR41 == 7'h10)
end
) else
VAR193:assert property (@(posedge clk)
VAR59[*256] #((VAR60[6:0]==7'h30) || (VAR60[6:0]==7'h10))| VAR64
end
) else
VAR72: assert property (@(posedge clk)
VAR59[*256] #VAR81 | ##[1:16] (VAR41 == 7'h34)
end
) else
VAR136: assert property (@(posedge clk)
VAR59[*256] #VAR81 | ##[1:16] (VAR41 == 7'h14)
end
) else
VAR32:assert property (@(posedge clk)
VAR59[*256] #((VAR60[6:0]==7'h34) || (VAR60[6:0]==7'h14))| VAR81
) else
VAR48: assert property (@(posedge clk) VAR59 | #(VAR41 != 7'h00)
) else
VAR166: assert property (@(posedge clk)
VAR59 | ((^VAR41) == 1'b0) || ((^VAR41) == 1'b1)
) else
VAR132 : assert property (@(posedge clk)
VAR59 | #(VAR27 == VAR142)) else
VAR108 : assert property (@(posedge clk)
VAR59 | #(VAR157 == VAR60)) else
VAR195 : assert property (@(posedge clk)
VAR59 | #(VAR102 == VAR133)) else
endmodule
module MODULE2 #(
parameter VAR12 = 16'h0000
)(
output VAR123,
input VAR45,
input VAR171,
input VAR95,
input VAR200,
input VAR100,
input VAR67,
input VAR78,
input VAR85
);
reg [15:0] VAR183 = VAR12;
assign VAR123 = VAR183[{VAR200, VAR95, VAR171, VAR45}];
always @(posedge VAR67)
begin
if (VAR78 == 1'b0)
{VAR183[15:0]} <= VAR12;
end
else
if (VAR100 == 1'b1) begin
{VAR183[15:0]} <= {VAR183[14:0], VAR85};
end
end
endmodule
|
lgpl-3.0
|
osrf/wandrr
|
firmware/motor_controller/fpga/foc_consts_32x32.v
| 1,433 |
module MODULE1
(input VAR1,
input [ 4:0] addr,
output reg [31:0] VAR2);
VAR3 VAR2 = 32'h0;
always @(posedge VAR1) begin
case (addr)
5'h00: VAR2 = 32'hc6800000; 5'h01: VAR2 = 32'h3bd55555; 5'h02: VAR2 = 32'h3f2aaaab; 5'h03: VAR2 = 32'hbeaaaaab; 5'h04: VAR2 = 32'h3f13cd36; 5'h05: VAR2 = 32'hbf13cd36; 5'h06: VAR2 = 32'hbf800000; 5'h07: VAR2 = 32'hbf000000; 5'h08: VAR2 = 32'h3f5dddde; 5'h09: VAR2 = 32'h451ff000; 5'h0a: VAR2 = 32'h424cb852; 5'h0b: VAR2 = 32'h459ff800; 5'h0c: VAR2 = 32'h3856bf95; 5'h0d: VAR2 = 32'h3f000000; 5'h0e: VAR2 = 32'h46800000; 5'h0f: VAR2 = 32'h40c90fdb; 5'h10: VAR2 = 32'h3fc90fdb; 5'h11: VAR2 = 32'h39c90fdb; 5'h12: VAR2 = 32'h0;
5'h13: VAR2 = 32'h0;
5'h14: VAR2 = 32'h0;
5'h15: VAR2 = 32'h0;
5'h16: VAR2 = 32'h0;
5'h17: VAR2 = 32'h0;
5'h18: VAR2 = 32'h0;
5'h19: VAR2 = 32'h0;
5'h1a: VAR2 = 32'h0;
5'h1b: VAR2 = 32'h0;
5'h1c: VAR2 = 32'h0;
5'h1d: VAR2 = 32'h0;
5'h1e: VAR2 = 32'h0;
5'h1f: VAR2 = 32'h0; endcase
end
endmodule
|
apache-2.0
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/digital/rtl/bus/bus.v
| 13,926 |
module MODULE1(
input wire clk , input wire reset , input wire VAR41 , output wire VAR29 , input wire [VAR6] VAR2 , input wire VAR14 , input wire VAR50 , input wire [VAR25] VAR59 , input wire VAR10 , output wire VAR9 , input wire [VAR6] VAR43 , input wire VAR19 , input wire VAR46 , input wire [VAR25] VAR28 , input wire VAR38 , output wire VAR27 , input wire [VAR6] VAR20 , input wire VAR33 , input wire VAR32 , input wire [VAR25] VAR12 , input wire VAR26 , output wire VAR47 , input wire [VAR6] VAR57 , input wire VAR31 , input wire VAR39 , input wire [VAR25] VAR13 , output wire [VAR6] VAR44 , output wire VAR48 , output wire VAR42 , output wire [VAR25] VAR1 , output wire VAR51 , input wire [VAR25] VAR56 , input wire VAR8 , output wire VAR53 , input wire [VAR25] VAR7 , input wire VAR52 , output wire VAR17 , input wire [VAR25] VAR15 , input wire VAR60 , output wire VAR30 , input wire [VAR25] VAR18 , input wire VAR11 , output wire VAR22 , input wire [VAR25] VAR34 , input wire VAR3 , output wire VAR36 , input wire [VAR25] VAR4 , input wire VAR16 , output wire VAR40 , input wire [VAR25] VAR49 , input wire VAR58 , output wire VAR23 , input wire [VAR25] VAR5 , input wire VAR55 , output wire [VAR25] VAR21 , output wire VAR35 );
VAR24 VAR24(
.clk (clk ), .reset (reset ), .VAR41 (VAR41 ), .VAR29 (VAR29 ), .VAR10 (VAR10 ), .VAR9 (VAR9 ), .VAR38 (VAR38 ), .VAR27 (VAR27 ), .VAR26 (VAR26 ), .VAR47 (VAR47 ) );
VAR37 VAR37(
.VAR2 (VAR2 ), .VAR14 (VAR14 ), .VAR50 (VAR50 ), .VAR59 (VAR59 ), .VAR29 (VAR29 ), .VAR43 (VAR43 ), .VAR19 (VAR19 ), .VAR46 (VAR46 ), .VAR28 (VAR28 ), .VAR9 (VAR9 ), .VAR20 (VAR20 ), .VAR33 (VAR33 ), .VAR32 (VAR32 ), .VAR12 (VAR12 ), .VAR27 (VAR27 ), .VAR57 (VAR57 ), .VAR31 (VAR31 ), .VAR39 (VAR39 ), .VAR13 (VAR13 ), .VAR47 (VAR47 ), .VAR44 (VAR44 ), .VAR48 (VAR48 ), .VAR42 (VAR42 ), .VAR1 (VAR1 ) );
VAR54 VAR54(
.VAR44 (VAR44 ), .VAR51 (VAR51 ), .VAR53 (VAR53 ), .VAR17 (VAR17 ), .VAR30 (VAR30 ), .VAR22 (VAR22 ), .VAR36 (VAR36 ), .VAR40 (VAR40 ), .VAR23 (VAR23 ) );
VAR45 VAR45(
.VAR51 (VAR51 ), .VAR56 (VAR56 ), .VAR8 (VAR8 ), .VAR53 (VAR53 ), .VAR7 (VAR7 ), .VAR52 (VAR52 ), .VAR17 (VAR17 ), .VAR15 (VAR15 ), .VAR60 (VAR60 ), .VAR30 (VAR30 ), .VAR18 (VAR18 ), .VAR11 (VAR11 ), .VAR22 (VAR22 ), .VAR34 (VAR34 ), .VAR3 (VAR3 ), .VAR36 (VAR36 ), .VAR4 (VAR4 ), .VAR16 (VAR16 ), .VAR40 (VAR40 ), .VAR49 (VAR49 ), .VAR58 (VAR58 ), .VAR23 (VAR23 ), .VAR5 (VAR5 ), .VAR55 (VAR55 ), .VAR21 (VAR21 ), .VAR35 (VAR35 ) );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/edfxtp/sky130_fd_sc_hs__edfxtp.functional.v
| 1,632 |
module MODULE1 (
VAR11 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR2,
VAR9
);
output VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR2;
input VAR9;
wire VAR6;
VAR7 VAR10 VAR1 (VAR6 , VAR5, VAR3, VAR4, VAR2, VAR9);
buf VAR8 (VAR11 , VAR6 );
endmodule
|
apache-2.0
|
thucoldwind/ucore_mips
|
CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/pc.v
| 1,025 |
module MODULE1(
input wire clk,
input wire rst,
input wire VAR11,
input wire[31:0] VAR5,
input wire VAR8,
input wire VAR9,
input wire VAR6,
input wire[31:0] VAR4,
output reg[31:0] VAR2
);
wire[31:0] VAR10 = VAR2 + 32'h4;
wire[31:0] VAR3 = VAR2;
always @(posedge clk) begin
if (rst == VAR7) begin
VAR2 <= 32'h80000000 - 4;
end else if (VAR9 == VAR1) begin
VAR2 <= VAR3;
end else if (VAR6 == VAR7) begin
VAR2 <= VAR4;
end else if (VAR8 == VAR7) begin
VAR2 <= VAR3;
end else if (VAR11 == VAR7) begin
VAR2 <= VAR5;
end else begin
VAR2 <= VAR10;
end
end
endmodule
|
unlicense
|
SiLab-Bonn/basil
|
basil/firmware/modules/bram_fifo/bram_fifo.v
| 2,876 |
module MODULE1 #(
parameter VAR24 = 32'h0000,
parameter VAR2 = 32'h0000,
parameter VAR23 = 32,
parameter VAR38 = 32'h0000,
parameter VAR32 = 32'h0000,
parameter VAR31 = 32'h8000*8,
parameter VAR18 = 95, parameter VAR15 = 5 ) (
input wire VAR16,
input wire VAR14,
input wire [VAR23-1:0] VAR42,
inout wire [31:0] VAR37,
input wire VAR17,
input wire VAR21,
output wire VAR5,
input wire VAR25,
input wire [31:0] VAR7,
output wire VAR10,
output wire VAR40,
output wire VAR27,
output wire VAR4
);
wire VAR22, VAR41;
wire [VAR23-1:0] VAR20;
wire [7:0] VAR39;
wire [7:0] VAR11;
VAR1 #(
.VAR24(VAR24),
.VAR2(VAR2),
.VAR23(VAR23)
) VAR8 (
.VAR17(VAR17),
.VAR21(VAR21),
.VAR42(VAR42),
.VAR37(VAR37[7:0]),
.VAR22(VAR22),
.VAR41(VAR41),
.VAR20(VAR20),
.VAR39(VAR39),
.VAR11(VAR11)
);
wire VAR29, VAR12;
wire [31:0] VAR3, VAR33;
VAR1 #(
.VAR24(VAR38),
.VAR2(VAR32) ,
.VAR23(VAR23),
.VAR36(32)
) VAR26 (
.VAR17(VAR17),
.VAR21(VAR21),
.VAR42(VAR42),
.VAR37(VAR37),
.VAR22(VAR29),
.VAR41(VAR12),
.VAR20(),
.VAR39(VAR33),
.VAR11(VAR3)
);
VAR9 #(
.VAR31(VAR31),
.VAR18(VAR18),
.VAR15(VAR15),
.VAR23(VAR23)
) VAR28 (
.VAR16(VAR16),
.VAR14(VAR14),
.VAR42(VAR20),
.VAR13(VAR39),
.VAR17(VAR22),
.VAR21(VAR41),
.VAR19(VAR11),
.VAR35(VAR29),
.VAR34(VAR12),
.VAR6(VAR33),
.VAR30(VAR3),
.VAR5(VAR5),
.VAR25(VAR25),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR40(VAR40),
.VAR27(VAR27),
.VAR4(VAR4)
);
endmodule
|
bsd-3-clause
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/a32oi/sky130_fd_sc_ms__a32oi_2.v
| 2,483 |
module MODULE1 (
VAR8 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR3,
VAR4,
VAR10 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR3;
input VAR4;
input VAR10 ;
input VAR1 ;
VAR9 VAR12 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8 ,
VAR2,
VAR7,
VAR5,
VAR6,
VAR11
);
output VAR8 ;
input VAR2;
input VAR7;
input VAR5;
input VAR6;
input VAR11;
supply1 VAR3;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR1 ;
VAR9 VAR12 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11)
);
endmodule
|
apache-2.0
|
UGent-HES/ConnectionRouter
|
vtr_flow/benchmarks/fpu/hardlogic/syn2.v
| 2,483 |
module MODULE1(VAR26,
reset,
VAR38,
VAR5,
VAR36,
VAR19,
VAR45,
VAR24,
VAR10,
VAR25,
VAR12
);
input VAR26;
input reset;
input [VAR9-1:0] VAR38;
input [VAR9-1:0] VAR5;
input [VAR9-1:0] VAR36;
input [VAR9-1:0] VAR19;
input [VAR9-1:0] VAR45;
output [VAR9-1:0] VAR24;
output [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR25;
output [VAR9-1:0] VAR12;
wire [VAR9-1:0] VAR39;
wire [VAR9-1:0] VAR15;
wire [VAR9-1:0] VAR28;
wire [VAR9-1:0] VAR11;
wire [VAR9-1:0] VAR49;
wire [VAR9-1:0] VAR4;
wire [VAR9-1:0] VAR48;
wire [VAR9-1:0] VAR34;
wire [VAR9-1:0] VAR18;
reg [VAR9-1:0] VAR14;
reg [VAR9-1:0] VAR29;
reg [VAR9-1:0] VAR41;
reg [VAR9-1:0] VAR40;
reg [VAR9-1:0] VAR31;
reg [VAR9-1:0] VAR21;
wire [VAR9-1:0] VAR24;
wire [VAR9-1:0] VAR10;
wire [VAR9-1:0] VAR25;
wire [VAR9-1:0] VAR12;
wire [7:0] VAR42;
VAR44 VAR33
(
.clk(VAR26),
.VAR43(VAR21),
.VAR22(VAR19),
.out(VAR49),
.VAR46(VAR42)
);
wire [7:0] VAR2;
VAR1 VAR35
(
.clk(VAR26),
.VAR43(VAR28),
.VAR22(VAR38),
.out(VAR39),
.VAR46(VAR2)
);
wire [7:0] VAR8;
VAR44 VAR30
(
.clk(VAR26),
.VAR43(VAR18),
.VAR22(VAR49),
.out(VAR4),
.VAR46(VAR8)
);
wire [7:0] VAR7;
VAR1 VAR32
(
.clk(VAR26),
.VAR43(VAR39),
.VAR22(VAR4),
.out(VAR15),
.VAR46(VAR7)
);
wire [7:0] VAR27;
VAR44 VAR16
(
.clk(VAR26),
.VAR43(VAR38),
.VAR22(VAR21),
.out(VAR48),
.VAR46(VAR27)
);
wire [7:0] VAR37;
VAR1 VAR17
(
.clk(VAR26),
.VAR43(VAR36),
.VAR22(VAR38),
.out(VAR28),
.VAR46(VAR37)
);
wire [7:0] VAR3;
VAR44 VAR6
(
.clk(VAR26),
.VAR43(VAR45),
.VAR22(VAR36),
.out(VAR34),
.VAR46(VAR3)
);
wire [7:0] VAR13;
VAR1 VAR23
(
.clk(VAR26),
.VAR43(VAR45),
.VAR22(VAR19),
.out(VAR11),
.VAR46(VAR13)
);
wire [7:0] VAR47;
VAR44 VAR20
(
.clk(VAR26),
.VAR43(VAR45),
.VAR22(VAR19),
.out(VAR18),
.VAR46(VAR47)
);
assign VAR24 = VAR15;
assign VAR10 = VAR48;
assign VAR25 = VAR34;
assign VAR12 = VAR11;
always @(posedge VAR26)
begin
VAR14 <= VAR5;
VAR29 <= VAR14;
VAR41 <= VAR29;
VAR40 <= VAR41;
VAR31 <= VAR40;
VAR21 <= VAR31;
end
endmodule
|
mit
|
C-L-G/azpr_soc
|
azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/alu.v
| 2,590 |
module MODULE1 (
input wire [VAR5] VAR2, input wire [VAR5] VAR7, input wire [VAR1] VAR8, output reg [VAR5] out, output reg VAR11 );
wire signed [VAR5] VAR9 = (VAR2); wire signed [VAR5] VAR4 = (VAR7); wire signed [VAR5] VAR10 = (out);
always @ begin
case (VAR8)
((VAR9 < 0) && (VAR4 < 0) && (VAR10 > 0))) begin
VAR11 = VAR6;
end else begin
VAR11 = VAR3;
end
end
((VAR9 > 0) && (VAR4 < 0) && (VAR10 < 0))) begin
VAR11 = VAR6;
end else begin
VAR11 = VAR3;
end
end
default : begin VAR11 = VAR3;
end
endcase
end
endmodule
|
apache-2.0
|
htuNCSU/MmcCommunicationVerilog
|
MAX10_SLAVE/phyIniCommand0.v
| 1,139 |
module MODULE1
(
input [(VAR1-1):0] VAR2,
input [(VAR5-1):0] addr,
input VAR7, clk,
output [(VAR1-1):0] VAR4
);
reg [VAR1-1:0] VAR3[2**VAR5-1:0];
reg [VAR5-1:0] VAR6;
begin
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.v
| 2,325 |
module MODULE2 (
VAR9 ,
VAR6 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR7,
VAR2,
VAR1 ,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR10 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6 ,
VAR8 ,
VAR5,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR8 ;
input VAR5;
input VAR4;
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR10 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
BilkentCompGen/GateKeeper
|
FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/one_hot_mux.v
| 4,781 |
module MODULE1
parameter VAR3 = 2,
parameter VAR4 = VAR3*VAR5
)
(
input [VAR3-1:0] VAR8,
input [VAR4-1:0] VAR2,
output [VAR5-1:0] VAR9);
genvar VAR6;
wire [VAR5-1:0] VAR10[(1<<VAR3):1];
reg [VAR5-1:0] VAR7;
assign VAR9 = VAR7;
generate
for( VAR6 = 0 ; VAR6 < VAR3; VAR6 = VAR6 + 1 ) begin : VAR1
assign VAR10[(1<<VAR6)] = VAR2[VAR5*VAR6 +: VAR5];
end
if(VAR3 == 1) begin
always @ begin
case(VAR8)
2'b01: VAR7 = VAR10[1];
2'b10: VAR7 = VAR10[2];
default:VAR7 = VAR10[1];
endcase end
end else if( VAR3 == 4) begin
always @ begin
case(VAR8)
8'b00000001: VAR7 = VAR10[1];
8'b00000010: VAR7 = VAR10[2];
8'b00000100: VAR7 = VAR10[4];
8'b00001000: VAR7 = VAR10[8];
8'b00010000: VAR7 = VAR10[16];
8'b00100000: VAR7 = VAR10[32];
8'b01000000: VAR7 = VAR10[64];
8'b10000000: VAR7 = VAR10[128];
default:VAR7 = VAR10[1];
endcase end
end
endgenerate
endmodule
|
gpl-3.0
|
EliasVansteenkiste/ConnectionRouter
|
vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_004.v
| 1,561 |
module MODULE1 (
VAR15,
VAR6
);
input [31:0] VAR15;
output [31:0]
VAR6;
wire [31:0]
VAR12,
VAR9,
VAR2,
VAR1,
VAR10,
VAR8,
VAR13,
VAR4,
VAR5,
VAR11;
assign VAR12 = VAR15;
assign VAR9 = VAR12 << 7;
assign VAR2 = VAR12 + VAR9;
assign VAR1 = VAR2 << 4;
assign VAR11 = VAR5 << 3;
assign VAR10 = VAR2 + VAR1;
assign VAR5 = VAR13 - VAR4;
assign VAR13 = VAR10 + VAR8;
assign VAR8 = VAR2 << 2;
assign VAR4 = VAR12 << 3;
assign VAR6 = VAR11;
endmodule
module MODULE2(
VAR15,
VAR6,
clk
);
input [31:0] VAR15;
output [31:0] VAR6;
reg [31:0] VAR6;
input clk;
reg [31:0] VAR3;
wire [30:0] VAR7;
always @(posedge clk) begin
VAR3 <= VAR15;
VAR6 <= VAR7;
end
MODULE1 MODULE1(
.VAR15(VAR3),
.VAR6(VAR7)
);
endmodule
|
mit
|
ludisu13/Estructuras2
|
Tarea_final_Decodificador/decodificador.v
| 6,239 |
module MODULE1(
input wire VAR14,
input wire[15:0] VAR1,
input wire VAR2, VAR7, VAR5, VAR12, VAR8, VAR9,
output reg VAR6,
output reg VAR11;
output reg[9:0] VAR4,
output reg[7:0] VAR3,
output reg VAR13,
output reg VAR10
);
always @(posedge VAR14)
begin
case(VAR1[15:0])
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=1;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=1;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=1;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=1;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=1;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=1;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=1;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=1;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=1;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR11<=0;
VAR13<=1;
VAR10<=0;
VAR6<=0;
VAR4<=10'b0;
VAR3=VAR1[7:0];
end
begin
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR11<=1;
VAR4<=VAR1[9:0];
VAR3<=8'b0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR2==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR2==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR5==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR5==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR8==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR8==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR7==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR7==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR12==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR12==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR9==1)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR3<=8'b0;
if(VAR9==0)
begin
VAR6<=1;
VAR4<=VAR1[6:0];
end
else
VAR6<=0;
end
default:
begin
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR11<=0;
VAR4<=10'b0;
VAR3=8'b0;
end
endcase
end
endmodule
|
gpl-3.0
|
zhangly/azpr_cpu
|
rtl/top/lib/altera_dpram_bb.v
| 8,727 |
module MODULE1 (
VAR4,
VAR8,
VAR5,
VAR10,
VAR7,
VAR2,
VAR6,
VAR1,
VAR3,
VAR9);
input [11:0] VAR4;
input [11:0] VAR8;
input VAR5;
input VAR10;
input [31:0] VAR7;
input [31:0] VAR2;
input VAR6;
input VAR1;
output [31:0] VAR3;
output [31:0] VAR9;
tri1 VAR5;
tri0 VAR6;
tri0 VAR1;
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/altera_ddr3/alt_ddrx_bank_tracking.v
| 52,084 |
module MODULE1 #
( parameter
VAR38 = 2,
VAR106 = 2,
VAR124 = 16, VAR18 = 3,
VAR33 = 6, VAR85 = 8
)
(
VAR6,
VAR77,
VAR73,
VAR8,
VAR70,
VAR36,
VAR92,
VAR148,
VAR58,
VAR39,
VAR108,
VAR164,
VAR67,
VAR40,
VAR127,
VAR176,
VAR49,
VAR21,
VAR42,
VAR41,
VAR20,
VAR154,
VAR134,
VAR24,
VAR177,
VAR7,
VAR153,
VAR53,
VAR1,
VAR75,
VAR2,
VAR122,
VAR96,
VAR74,
VAR23,
VAR65,
VAR60,
VAR98,
VAR27,
VAR45,
VAR167,
VAR81,
VAR169,
VAR109,
VAR102,
VAR149,
VAR29,
VAR139,
VAR48,
VAR143,
VAR59,
VAR47,
VAR103,
VAR44,
VAR5,
VAR135,
VAR90,
VAR146,
VAR114,
VAR120,
VAR78,
VAR54,
VAR138,
VAR131,
VAR162,
VAR89,
VAR19,
VAR155,
VAR145,
VAR159,
VAR160,
VAR136,
VAR30,
VAR46,
VAR71,
VAR116,
VAR66,
VAR113,
VAR61,
VAR179,
VAR63,
VAR126,
VAR140,
VAR123,
VAR171
);
input VAR6;
input VAR77;
output [VAR106 - 1 : 0] VAR73;
input VAR8;
input VAR148;
input VAR58;
input VAR39;
input [VAR38 - 1 : 0] VAR70;
input [VAR124 - 1 : 0] VAR36;
input [VAR18 - 1 : 0] VAR92;
input VAR108;
input VAR127;
input VAR176;
input VAR49;
input [VAR38 - 1 : 0] VAR164;
input [VAR124 - 1 : 0] VAR67;
input [VAR18 - 1 : 0] VAR40;
input VAR21;
input VAR154;
input VAR134;
input VAR24;
input [VAR38 - 1 : 0] VAR42;
input [VAR124 - 1 : 0] VAR41;
input [VAR18 - 1 : 0] VAR20;
input VAR177;
input VAR1;
input VAR75;
input VAR2;
input [VAR38 - 1 : 0] VAR7;
input [VAR124 - 1 : 0] VAR153;
input [VAR18 - 1 : 0] VAR53;
input VAR122;
input VAR65;
input VAR60;
input VAR98;
input [VAR38 - 1 : 0] VAR96;
input [VAR124 - 1 : 0] VAR74;
input [VAR18 - 1 : 0] VAR23;
input VAR27;
input VAR169;
input VAR109;
input VAR102;
input [VAR38 - 1 : 0] VAR45;
input [VAR124 - 1 : 0] VAR167;
input [VAR18 - 1 : 0] VAR81;
input VAR149;
input VAR143;
input VAR59;
input VAR47;
input [VAR38 - 1 : 0] VAR29;
input [VAR124 - 1 : 0] VAR139;
input [VAR18 - 1 : 0] VAR48;
input VAR103;
input VAR90;
input VAR146;
input VAR114;
input [VAR38 - 1 : 0] VAR44;
input [VAR124 - 1 : 0] VAR5;
input [VAR18 - 1 : 0] VAR135;
output [VAR33 - 1 : 0] VAR120;
output [VAR33 - 1 : 0] VAR78;
output [VAR33 - 1 : 0] VAR54;
input VAR89;
input VAR19;
input VAR155;
input [VAR38 - 1 : 0] VAR138;
input [VAR124 - 1 : 0] VAR131;
input [VAR18 - 1 : 0] VAR162;
output VAR145;
output VAR159;
output VAR160;
input VAR136;
input VAR30;
input VAR46;
input VAR71;
input VAR116;
input VAR66;
input VAR113;
input VAR61;
input VAR179;
input [VAR106 - 1 : 0] VAR63;
input [VAR124 - 1 : 0] VAR126;
input [VAR18 - 1 : 0] VAR140;
output [VAR106 * (2**VAR18) * VAR124 - 1 : 0] VAR123 ;
output [VAR106 * (2**VAR18) - 1 : 0] VAR171 ;
reg [VAR106 - 1 : 0] VAR73;
integer VAR172;
integer VAR14;
integer VAR28;
reg [(2 ** VAR18) - 1 : 0] VAR79 [VAR106 - 1 : 0];
reg VAR158;
reg VAR80;
reg VAR150;
reg VAR170;
reg VAR91;
reg VAR130;
reg VAR12;
reg [1 : 0] VAR22;
reg VAR68;
reg VAR121;
reg VAR141;
reg VAR99;
reg [VAR38 - 1 : 0] VAR9;
reg [VAR18 - 1 : 0] VAR142;
reg [VAR124 - 1 : 0] VAR16;
reg [VAR18 - 1 : 0] VAR161;
reg [VAR124 - 1 : 0] VAR26;
reg VAR117;
reg VAR118;
reg [VAR85 : 0] VAR174;
reg [VAR85 : 0] VAR97;
reg [VAR33 : 0] VAR62;
reg [VAR33 : 0] VAR168;
reg [VAR33 : 0] VAR133;
reg [VAR33 : 0] VAR129;
reg [VAR33 : 0] VAR43;
reg [VAR33 : 0] VAR93;
reg [VAR85 : 0] VAR17;
reg [VAR85 : 0] VAR72;
wire [(VAR85 + 1) * (VAR38 + VAR18 + VAR124) - 1 : 0] VAR51;
wire [(VAR85 + 1) * VAR38 - 1 : 0] VAR31;
wire [(VAR85 + 1) * VAR18 - 1 : 0] VAR156;
wire [(VAR85 + 1) * VAR124 - 1 : 0] VAR37;
wire [VAR85 : 0] VAR166;
wire [VAR85 : 0] VAR64;
wire [VAR85 : 0] VAR144;
wire [VAR85 : 0] VAR52;
wire [VAR85 : 0] VAR137;
wire [VAR85 : 0] VAR100;
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR104 = {VAR138, VAR162, VAR131};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR165 = {VAR70, VAR92, VAR36};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR110 = {VAR164, VAR40, VAR67};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR25 = {VAR42, VAR20, VAR41};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR56 = {VAR7, VAR53, VAR153};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR4 = {VAR96, VAR23, VAR74};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR105 = {VAR45, VAR81, VAR167};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR125 = {VAR29, VAR48, VAR139};
wire [(VAR38 + VAR18 + VAR124) - 1 : 0] VAR111 = {VAR44, VAR135, VAR5};
wire [VAR33 - 1 : 0] VAR120;
wire [VAR33 - 1 : 0] VAR78;
wire [VAR33 - 1 : 0] VAR54;
reg [VAR85 - 1 : 0] VAR35;
reg [VAR85 - 1 : 0] VAR11;
reg [VAR85 - 1 : 0] VAR87;
reg VAR159;
reg VAR145;
reg VAR160;
assign VAR51 = {VAR111, VAR125, VAR105, VAR4, VAR56, VAR25, VAR110, VAR165, VAR104};
assign VAR31 = {VAR44, VAR29, VAR45, VAR96, VAR7, VAR42, VAR164, VAR70, VAR138};
assign VAR156 = {VAR135, VAR48, VAR81, VAR23, VAR53, VAR20, VAR40, VAR92, VAR162};
assign VAR37 = {VAR5, VAR139, VAR167, VAR74, VAR153, VAR41, VAR67, VAR36, VAR131};
assign VAR166 = {VAR103, VAR149, VAR27, VAR122, VAR177, VAR21, VAR108, VAR8, 1'b0}; assign VAR64 [0] = VAR68;
assign VAR137 = {VAR114, VAR47, VAR102, VAR98, VAR2, VAR24, VAR49, VAR39, VAR155};
assign VAR144 = {VAR90, VAR143, VAR169, VAR65, VAR1, VAR154, VAR127, VAR148, VAR89};
assign VAR52 = {VAR146, VAR59, VAR109, VAR60, VAR75, VAR134, VAR176, VAR58, VAR19};
assign VAR100 = VAR137 & VAR144;
assign VAR120 = VAR35 [VAR33 - 1 : 0];
assign VAR78 = VAR11 [VAR33 - 1 : 0];
assign VAR54 = VAR87 [VAR33 - 1 : 0];
always @
begin
begin
if (VAR30 || VAR150 || VAR46 || VAR71 || VAR116 || VAR91 || VAR130 || VAR12)
VAR141 = 1'b1;
end
else
VAR141 = 1'b0;
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR159 <= 0;
VAR11 <= 0;
VAR145 <= 0;
VAR35 <= 0;
VAR160 <= 0;
VAR87 <= 0;
end
else if (VAR141)
begin
if (VAR22 == 2'b01)
begin
VAR159 <= VAR174 [2];
VAR11 [0] <= VAR174 [3];
VAR11 [1] <= VAR174 [4];
VAR11 [2] <= (VAR33 <= 4) ? 1'b0 : VAR174 [5];
VAR11 [3] <= (VAR33 <= 4) ? 1'b0 : VAR174 [6];
VAR11 [4] <= (VAR33 <= 6) ? 1'b0 : VAR174 [7];
VAR11 [5] <= (VAR33 <= 6) ? 1'b0 : VAR174 [8];
VAR11 [6] <= 1'b0;
VAR11 [7] <= 1'b0;
VAR145 <= VAR97 [2];
VAR35 [0] <= VAR97 [3];
VAR35 [1] <= VAR97 [4];
VAR35 [2] <= (VAR33 <= 4) ? 1'b0 : VAR97 [5];
VAR35 [3] <= (VAR33 <= 4) ? 1'b0 : VAR97 [6];
VAR35 [4] <= (VAR33 <= 6) ? 1'b0 : VAR97 [7];
VAR35 [5] <= (VAR33 <= 6) ? 1'b0 : VAR97 [8];
VAR35 [6] <= 1'b0;
VAR35 [7] <= 1'b0;
VAR160 <= VAR64[2];
VAR87 [0] <= VAR64[3];
VAR87 [1] <= VAR64[4];
VAR87 [2] <= (VAR33 <= 4) ? 1'b0 : VAR64 [5];
VAR87 [3] <= (VAR33 <= 4) ? 1'b0 : VAR64 [6];
VAR87 [4] <= (VAR33 <= 6) ? 1'b0 : VAR64 [7];
VAR87 [5] <= (VAR33 <= 6) ? 1'b0 : VAR64 [8];
VAR87 [6] <= 1'b0;
VAR87 [7] <= 1'b0;
end
else if (VAR22 == 2'b10)
begin
VAR159 <= VAR174 [3];
VAR11 [0] <= VAR174 [4];
VAR11 [1] <= (VAR33 <= 4) ? 1'b0 : VAR174 [5];
VAR11 [2] <= (VAR33 <= 4) ? 1'b0 : VAR174 [6];
VAR11 [3] <= (VAR33 <= 6) ? 1'b0 : VAR174 [7];
VAR11 [4] <= (VAR33 <= 6) ? 1'b0 : VAR174 [8];
VAR11 [5] <= 1'b0;
VAR11 [6] <= 1'b0;
VAR11 [7] <= 1'b0;
VAR145 <= VAR97 [3];
VAR35 [0] <= VAR97 [4];
VAR35 [1] <= (VAR33 <= 4) ? 1'b0 : VAR97 [5];
VAR35 [2] <= (VAR33 <= 4) ? 1'b0 : VAR97 [6];
VAR35 [3] <= (VAR33 <= 6) ? 1'b0 : VAR97 [7];
VAR35 [4] <= (VAR33 <= 6) ? 1'b0 : VAR97 [8];
VAR35 [5] <= 1'b0;
VAR35 [6] <= 1'b0;
VAR35 [7] <= 1'b0;
VAR160 <= VAR64[3];
VAR87 [0] <= VAR64[4];
VAR87 [1] <= (VAR33 <= 4) ? 1'b0 : VAR64 [5];
VAR87 [2] <= (VAR33 <= 4) ? 1'b0 : VAR64 [6];
VAR87 [3] <= (VAR33 <= 6) ? 1'b0 : VAR64 [7];
VAR87 [4] <= (VAR33 <= 6) ? 1'b0 : VAR64 [8];
VAR87 [5] <= 1'b0;
VAR87 [6] <= 1'b0;
VAR87 [7] <= 1'b0;
end
else if (VAR22 == 2'b11)
begin
VAR159 <= VAR174 [4];
VAR11 [0] <= (VAR33 <= 4) ? 1'b0 : VAR174 [5];
VAR11 [1] <= (VAR33 <= 4) ? 1'b0 : VAR174 [6];
VAR11 [2] <= (VAR33 <= 6) ? 1'b0 : VAR174 [7];
VAR11 [3] <= (VAR33 <= 6) ? 1'b0 : VAR174 [8];
VAR11 [4] <= 1'b0;
VAR11 [5] <= 1'b0;
VAR11 [6] <= 1'b0;
VAR11 [7] <= 1'b0;
VAR145 <= VAR97 [4];
VAR35 [0] <= (VAR33 <= 4) ? 1'b0 : VAR97 [5];
VAR35 [1] <= (VAR33 <= 4) ? 1'b0 : VAR97 [6];
VAR35 [2] <= (VAR33 <= 6) ? 1'b0 : VAR97 [7];
VAR35 [3] <= (VAR33 <= 6) ? 1'b0 : VAR97 [8];
VAR35 [4] <= 1'b0;
VAR35 [5] <= 1'b0;
VAR35 [6] <= 1'b0;
VAR35 [7] <= 1'b0;
VAR160 <= VAR64[4];
VAR87 [0] <= (VAR33 <= 4) ? 1'b0 : VAR64 [5];
VAR87 [1] <= (VAR33 <= 4) ? 1'b0 : VAR64 [6];
VAR87 [2] <= (VAR33 <= 6) ? 1'b0 : VAR64 [7];
VAR87 [3] <= (VAR33 <= 6) ? 1'b0 : VAR64 [8];
VAR87 [4] <= 1'b0;
VAR87 [5] <= 1'b0;
VAR87 [6] <= 1'b0;
VAR87 [7] <= 1'b0;
end
else
begin
VAR159 <= VAR174 [1];
VAR11 [0] <= VAR174 [2];
VAR11 [1] <= VAR174 [3];
VAR11 [2] <= VAR174 [4];
VAR11 [3] <= (VAR33 <= 4) ? 1'b0 : VAR174 [5];
VAR11 [4] <= (VAR33 <= 4) ? 1'b0 : VAR174 [6];
VAR11 [5] <= (VAR33 <= 6) ? 1'b0 : VAR174 [7];
VAR11 [6] <= (VAR33 <= 6) ? 1'b0 : VAR174 [8];
VAR11 [7] <= 1'b0;
VAR145 <= VAR97 [1];
VAR35 [0] <= VAR97 [2];
VAR35 [1] <= VAR97 [3];
VAR35 [2] <= VAR97 [4];
VAR35 [3] <= (VAR33 <= 4) ? 1'b0 : VAR97 [5];
VAR35 [4] <= (VAR33 <= 4) ? 1'b0 : VAR97 [6];
VAR35 [5] <= (VAR33 <= 6) ? 1'b0 : VAR97 [7];
VAR35 [6] <= (VAR33 <= 6) ? 1'b0 : VAR97 [8];
VAR35 [7] <= 1'b0;
VAR160 <= VAR64 [1];
VAR87 [0] <= VAR64 [2];
VAR87 [1] <= VAR64 [3];
VAR87 [2] <= VAR64 [4];
VAR87 [3] <= (VAR33 <= 4) ? 1'b0 : VAR64 [5];
VAR87 [4] <= (VAR33 <= 4) ? 1'b0 : VAR64 [6];
VAR87 [5] <= (VAR33 <= 6) ? 1'b0 : VAR64 [7];
VAR87 [6] <= (VAR33 <= 6) ? 1'b0 : VAR64 [8];
VAR87 [7] <= 1'b0;
end
end
else
begin
if (VAR117)
VAR160 <= 1'b0;
end
else
VAR160 <= VAR64 [0];
if (VAR118)
VAR145 <= 1'b0;
end
else
VAR145 <= VAR97 [0];
VAR159 <= VAR174 [0];
VAR11 [0] <= VAR174 [1];
VAR11 [1] <= VAR174 [2];
VAR11 [2] <= VAR174 [3];
VAR11 [3] <= VAR174 [4];
VAR11 [4] <= (VAR33 <= 4) ? 1'b0 : VAR174 [5];
VAR11 [5] <= (VAR33 <= 4) ? 1'b0 : VAR174 [6];
VAR11 [6] <= (VAR33 <= 6) ? 1'b0 : VAR174 [7];
VAR11 [7] <= (VAR33 <= 6) ? 1'b0 : VAR174 [8];
VAR35 [0] <= VAR97 [1];
VAR35 [1] <= VAR97 [2];
VAR35 [2] <= VAR97 [3];
VAR35 [3] <= VAR97 [4];
VAR35 [4] <= (VAR33 <= 4) ? 1'b0 : VAR97 [5];
VAR35 [5] <= (VAR33 <= 4) ? 1'b0 : VAR97 [6];
VAR35 [6] <= (VAR33 <= 6) ? 1'b0 : VAR97 [7];
VAR35 [7] <= (VAR33 <= 6) ? 1'b0 : VAR97 [8];
VAR87 [0] <= VAR64 [1];
VAR87 [1] <= VAR64 [2];
VAR87 [2] <= VAR64 [3];
VAR87 [3] <= VAR64 [4];
VAR87 [4] <= (VAR33 <= 4) ? 1'b0 : VAR64 [5];
VAR87 [5] <= (VAR33 <= 4) ? 1'b0 : VAR64 [6];
VAR87 [6] <= (VAR33 <= 6) ? 1'b0 : VAR64 [7];
VAR87 [7] <= (VAR33 <= 6) ? 1'b0 : VAR64 [8];
end
end
always @
begin
begin
if (VAR162 != VAR161)
VAR117 <= 1'b1;
end
else
VAR117 <= 1'b0;
if (VAR131 != VAR26)
VAR118 <= 1'b1;
end
else
VAR118 <= 1'b0;
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR99 <= 1'b0;
end
else
begin
VAR99 <= VAR66;
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR9 <= 0;
VAR142 <= 0;
VAR16 <= 0;
end
else
begin
VAR9 <= VAR63;
VAR142 <= VAR140;
VAR16 <= VAR126;
end
end
generate
begin
genvar VAR3;
for (VAR3 = 0;VAR3 < VAR33 + 1;VAR3 = VAR3 + 1)
begin : VAR178
wire [VAR38 - 1 : 0] VAR107 = VAR31 [(VAR3 + 1) * VAR38 - 1 : VAR3 * VAR38];
wire [VAR18 - 1 : 0] VAR119 = VAR156 [(VAR3 + 1) * VAR18 - 1 : VAR3 * VAR18];
wire [VAR124 - 1 : 0] VAR55 = VAR37 [(VAR3 + 1) * VAR124 - 1 : VAR3 * VAR124];
always @
begin
VAR43 [VAR3] <= VAR62 [VAR3];
end
always @
begin
VAR32 = 0;
VAR32 [VAR147] = 1'b1;
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR115 <= 0;
end
else
begin
VAR115 <= VAR112;
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR180 <= 0;
end
else
begin
VAR180 <= VAR32;
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR86 <= 1'b0;
end
else
begin
VAR86 <= VAR152;
end
end
always @
begin
if (VAR17 [VAR94])
VAR97 [VAR94] = 1'b1;
end
else if (VAR133 [VAR94])
VAR97 [VAR94] = 1'b1;
end
else
begin
if (VAR86)
VAR97 [VAR94] = &VAR163;
end
else
VAR97 [VAR94] = VAR163 [VAR10];
end
end
for (VAR84 = 0;VAR84 < VAR106;VAR84 = VAR84 + 1)
begin : VAR128
wire [VAR124 - 1 : 0] VAR82 = VAR15 [VAR84][VAR175];
wire VAR83 = VAR79 [VAR84][VAR175];
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
VAR13 [VAR84] <= 1'b0;
end
else
VAR13 [VAR84] <= VAR83;
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
VAR163 [VAR84] <= 1'b0;
end
else
begin
if (VAR82 == VAR69)
VAR163 [VAR84] <= 1'b1 & VAR83;
end
else
VAR163 [VAR84] <= 1'b0;
end
end
end
end
endgenerate
generate
genvar VAR95;
for (VAR95 = 1; VAR95 < VAR33 + 1;VAR95 = VAR95 + 1)
begin : VAR34
reg VAR50;
wire VAR88;
reg VAR151;
reg VAR57;
wire VAR181;
assign VAR181 = VAR166 [VAR95];
assign VAR88 = VAR50;
assign VAR64 [VAR95] = VAR88;
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR50 <= 1'b0;
end
else
begin
VAR50 <= VAR181;
end
end
end
endgenerate
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
VAR121 <= 1'b0;
end
else
VAR121 <= VAR68;
end
always @ (*)
begin
begin
if (VAR30)
VAR68 <= 1'b0;
end
else if (VAR170)
VAR68 <= 1'b1;
end
else if (VAR136)
VAR68 <= 1'b0;
else if (VAR80)
VAR68 <= 1'b1;
else
VAR68 <= VAR121;
end
end
integer VAR101;
integer VAR173;
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
for (VAR101 = 0;VAR101 < VAR106;VAR101 = VAR101 + 1'b1)
begin : VAR157
VAR79 [VAR101] <= 0;
end
end
else
begin
VAR101 <= 0;
for (VAR28 = 0;VAR28 < VAR106;VAR28 = VAR28 + 1'b1)
begin : VAR132
if (VAR63 [VAR28])
begin
if (VAR61)
VAR79 [VAR28][(2 ** VAR18) - 1 : 0] <= 0;
end
else if (VAR113 || VAR179)
VAR79 [VAR28][VAR140] <= 1'b0;
end
else if (VAR66)
VAR79 [VAR28][VAR140] <= 1'b1;
end
end
end
end
always @ (posedge VAR6 or negedge VAR77)
begin
if (!VAR77)
begin
VAR73 <= 0;
end
else
begin
for (VAR14 = 0;VAR14 < VAR106;VAR14 = VAR14 + 1'b1)
begin : VAR76
if (VAR66 && VAR63[VAR14]) VAR73 [VAR14] <= 1'b0;
end
else if (!(|VAR79 [VAR14][(2 ** VAR18) - 1 : 0]))
VAR73 [VAR14] <= 1'b1;
end
else
VAR73 [VAR14] <= 1'b0;
end
end
end
endmodule
|
gpl-3.0
|
mrehkopf/sd2snes
|
verilog/sd2snes_sa1/sa1_iram.v
| 10,701 |
module MODULE1 (
VAR18,
VAR17,
VAR23,
VAR47,
VAR27,
VAR2,
VAR33,
VAR13,
VAR34);
input [10:0] VAR18;
input [10:0] VAR17;
input VAR23;
input [7:0] VAR47;
input [7:0] VAR27;
input VAR2;
input VAR33;
output [7:0] VAR13;
output [7:0] VAR34;
tri1 VAR23;
tri0 VAR2;
tri0 VAR33;
wire [7:0] VAR35;
wire [7:0] VAR19;
wire [7:0] VAR13 = VAR35[7:0];
wire [7:0] VAR34 = VAR19[7:0];
VAR30 VAR40 (
.VAR18 (VAR18),
.VAR17 (VAR17),
.VAR45 (VAR23),
.VAR47 (VAR47),
.VAR27 (VAR27),
.VAR2 (VAR2),
.VAR33 (VAR33),
.VAR13 (VAR35),
.VAR34 (VAR19),
.VAR61 (1'b0),
.VAR59 (1'b0),
.VAR39 (1'b0),
.VAR1 (1'b0),
.VAR48 (1'b1),
.VAR29 (1'b1),
.VAR21 (1'b1),
.VAR26 (1'b1),
.VAR22 (1'b1),
.VAR16 (1'b1),
.VAR56 (1'b1),
.VAR64 (),
.VAR63 (1'b1),
.VAR10 (1'b1));
VAR40.VAR54 = "VAR20",
VAR40.VAR6 = "VAR55",
VAR40.VAR28 = "VAR55",
VAR40.VAR65 = "VAR55",
VAR40.VAR52 = "VAR55",
VAR40.VAR50 = "VAR20",
VAR40.VAR32 = "VAR31 VAR14 VAR25",
VAR40.VAR46 = "VAR30",
VAR40.VAR9 = 2048,
VAR40.VAR43 = 2048,
VAR40.VAR51 = "VAR36",
VAR40.VAR7 = "VAR57",
VAR40.VAR37 = "VAR57",
VAR40.VAR60 = "VAR4",
VAR40.VAR3 = "VAR4",
VAR40.VAR41 = "VAR5",
VAR40.VAR24 = "VAR8",
VAR40.VAR38 = "VAR12",
VAR40.VAR44 = "VAR12",
VAR40.VAR58 = 11,
VAR40.VAR62 = 11,
VAR40.VAR42 = 8,
VAR40.VAR53 = 8,
VAR40.VAR11 = 1,
VAR40.VAR49 = 1,
VAR40.VAR15 = "VAR20";
endmodule
|
gpl-2.0
|
kyzhai/NUNY
|
src/hardware/letterf.v
| 6,374 |
module MODULE1 (
address,
VAR5,
VAR22);
input [11:0] address;
input VAR5;
output [11:0] VAR22;
tri1 VAR5;
wire [11:0] VAR11;
wire [11:0] VAR22 = VAR11[11:0];
VAR52 VAR38 (
.VAR17 (address),
.VAR3 (VAR5),
.VAR23 (VAR11),
.VAR46 (1'b0),
.VAR12 (1'b0),
.VAR31 (1'b1),
.VAR39 (1'b0),
.VAR33 (1'b0),
.VAR28 (1'b1),
.VAR43 (1'b1),
.VAR27 (1'b1),
.VAR51 (1'b1),
.VAR37 (1'b1),
.VAR42 (1'b1),
.VAR50 (1'b1),
.VAR1 ({12{1'b1}}),
.VAR44 (1'b1),
.VAR47 (),
.VAR35 (),
.VAR30 (1'b1),
.VAR25 (1'b1),
.VAR10 (1'b0),
.VAR21 (1'b0));
VAR38.VAR29 = "VAR18",
VAR38.VAR14 = "VAR20",
VAR38.VAR34 = "VAR20",
VAR38.VAR41 = "./VAR49/MODULE1.VAR9",
VAR38.VAR19 = "VAR15 VAR45",
VAR38.VAR32 = "VAR7=VAR4",
VAR38.VAR24 = "VAR52",
VAR38.VAR36 = 4096,
VAR38.VAR26 = "VAR16",
VAR38.VAR2 = "VAR18",
VAR38.VAR40 = "VAR8",
VAR38.VAR6 = 12,
VAR38.VAR48 = 12,
VAR38.VAR13 = 1;
endmodule
|
gpl-2.0
|
rohit91/HDMI2USB
|
hdl/UART/TX_module.v
| 4,287 |
module MODULE1
parameter VAR15 = 8, VAR6 = 16 )
(
input wire clk, reset,
input wire VAR7, VAR2,
input wire [7:0] din,
output reg VAR4,
output wire VAR12
);
localparam [1:0]VAR17 = 2'b00,VAR14 = 2'b01,VAR13 = 2'b10,VAR16 = 2'b11;
reg [1:0] state, VAR11;
reg [3:0] VAR19, VAR9;
reg [2:0] VAR18, VAR5;
reg [7:0] VAR10, VAR1;
reg VAR8, VAR3;
always @(posedge clk)
if (reset)
begin
state <= VAR17;
VAR19 <= 0;
VAR18 <= 0;
VAR10 <= 0;
VAR8 <= 1'b1;
end
else
begin
state <= VAR11;
VAR19 <= VAR9;
VAR18 <= VAR5;
VAR10 <= VAR1;
VAR8 <= VAR3;
end
always @*
begin
VAR11 = state;
VAR4 = 1'b0;
VAR9 = VAR19;
VAR5 = VAR18;
VAR1 = VAR10;
VAR3 = VAR8 ;
if(state==VAR17)
begin
VAR3 = 1'b1;
if (VAR7)
begin
VAR11 = VAR14;
VAR9 = 0;
VAR1 = din;
end
end
else if(state==VAR14)
begin
VAR3 = 1'b0;
if (VAR2)
if (VAR19==15)
begin
VAR11 = VAR13;
VAR9 = 0;
VAR5 = 0;
end
else
VAR9 = VAR19 + 1;
end
else if(state==VAR13)
begin
VAR3 = VAR10[0];
if (VAR2)
if (VAR19==15)
begin
VAR9 = 0;
VAR1 = VAR10 >> 1;
if (VAR18==(VAR15-1))
VAR11 = VAR16 ;
end
else
VAR5 = VAR18 + 1;
end
else
VAR9 = VAR19 + 1;
end
else if(state==VAR16)
begin
VAR3 = 1'b1;
if (VAR2)
if (VAR19==(VAR6-1))
begin
VAR11 = VAR17;
VAR4 = 1'b1;
end
else
VAR9 = VAR19 + 1;
end
end
assign VAR12 = VAR8;
endmodule
|
bsd-2-clause
|
sabertazimi/hust-lab
|
digitalLogic/design/clock_design/src/timing_clock.v
| 3,862 |
module MODULE1
(
input VAR10,
input [(VAR16-1):0] VAR19,
input VAR2,
input VAR3,
input VAR5,
input enable,
input reset,
input [2:0] VAR1,
input [2:0] VAR20,
input [(VAR16-1):0] VAR23,
input [(VAR16-1):0] VAR12,
input [(VAR16-1):0] VAR17,
output [7:0] VAR15,
output [7:0] VAR14,
output [(VAR4-1):0] VAR18
);
wire [(VAR16-1):0] VAR11, VAR9, VAR21;
wire VAR6, VAR22, VAR7;
reg [(VAR16-1):0] VAR13;
reg VAR8;
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/o211a/sky130_fd_sc_hs__o211a.pp.blackbox.v
| 1,336 |
module MODULE1 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR5,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR4;
endmodule
|
apache-2.0
|
r2t2sdr/r2t2
|
fpga/modules/adi_hdl/library/util_adc_pack/util_adc_pack.v
| 17,218 |
module MODULE1 (
clk,
VAR46,
VAR26,
VAR44,
VAR38,
VAR2,
VAR30,
VAR50,
VAR37,
VAR15,
VAR6,
VAR21,
VAR32,
VAR13,
VAR19,
VAR3,
VAR52,
VAR20,
VAR34,
VAR23,
VAR39,
VAR56,
VAR17,
VAR40,
VAR22,
VAR11,
VAR57,
VAR48
);
parameter VAR42 = 8 ; parameter VAR41 = 16;
input clk;
input VAR46;
input VAR26;
input [(VAR41-1):0] VAR44;
input VAR38;
input VAR2;
input [(VAR41-1):0] VAR30;
input VAR50;
input VAR37;
input [(VAR41-1):0] VAR15;
input VAR6;
input VAR21;
input [(VAR41-1):0] VAR32;
input VAR13;
input VAR19;
input [(VAR41-1):0] VAR3;
input VAR52;
input VAR20;
input [(VAR41-1):0] VAR34;
input VAR23;
input VAR39;
input [(VAR41-1):0] VAR56;
input VAR40;
input VAR17;
input [(VAR41-1):0] VAR22;
output [(VAR41*VAR42-1):0] VAR11;
output VAR57;
output VAR48;
reg [(VAR41*VAR42-1):0] VAR1 = 0;
reg [(VAR41*VAR42-1):0] VAR24 = 0;
reg [(VAR41*VAR42-1):0] VAR27 = 0;
reg [3:0] VAR53;
reg [2:0] VAR5;
reg [2:0] VAR35;
reg [7:0] VAR33 = 0;
reg [7:0] VAR7 = 0;
reg [6:0] VAR29 = 0;
reg [7:0] VAR9 = 0;
reg [7:0] VAR51 = 0;
reg [7:0] VAR49 = 0;
reg VAR57 = 0;
reg [(VAR41*VAR42-1):0] VAR11 = 0;
reg [(VAR41-1):0] VAR10;
reg [(VAR41-1):0] VAR45;
reg [(VAR41-1):0] VAR18;
reg [(VAR41-1):0] VAR16;
reg [(VAR41-1):0] VAR8;
reg [(VAR41-1):0] VAR47;
reg [(VAR41-1):0] VAR43;
reg [(VAR41-1):0] VAR31;
wire VAR54;
assign VAR48 = VAR57;
assign VAR54 = VAR26 | VAR2 | VAR37 | VAR21 | VAR19 | VAR20 | VAR39 | VAR40 ;
always @(posedge clk)
begin
VAR53 = VAR5 + VAR35;
VAR5 = VAR46 + VAR38 + VAR50 + VAR6;
if (VAR42 == 8)
begin
VAR35 = VAR13 + VAR52 + VAR23 + VAR17;
end
else
begin
VAR35 = 0;
end
end
always @(posedge clk)
begin
if(VAR54 == 1'b1)
begin
VAR10 <= VAR44;
VAR45 <= VAR30;
VAR18 <= VAR15;
VAR16 <= VAR32;
VAR8 <= VAR3;
VAR47 <= VAR34;
VAR43 <= VAR56;
VAR31 <= VAR22;
end
end
always @(VAR10, VAR45, VAR18, VAR16, VAR46, VAR38, VAR50, VAR6 )
begin
casex ({VAR6,VAR50,VAR38,VAR46})
4'VAR12: VAR24[(VAR41-1):0] = VAR10;
4'VAR55: VAR24[(VAR41-1):0] = VAR45;
4'VAR14: VAR24[(VAR41-1):0] = VAR18;
4'b1000: VAR24[(VAR41-1):0] = VAR16;
default: VAR24 [(VAR41-1):0] = 0;
endcase
casex ({VAR6,VAR50,VAR38,VAR46})
4'VAR36: VAR24[2*VAR41-1:VAR41] = VAR45;
4'VAR25: VAR24[2*VAR41-1:VAR41] = VAR18;
4'VAR4: VAR24[2*VAR41-1:VAR41] = VAR18;
4'b1001: VAR24[2*VAR41-1:VAR41] = VAR16;
4'b1010: VAR24[2*VAR41-1:VAR41] = VAR16;
4'b1100: VAR24[2*VAR41-1:VAR41] = VAR16;
default: VAR24[2*VAR41-1:VAR41] = 0;
endcase
casex ({VAR6,VAR50,VAR38,VAR46})
4'VAR28: VAR24[3*VAR41-1:2*VAR41] = VAR18;
4'b1011: VAR24[3*VAR41-1:2*VAR41] = VAR16;
4'b1101: VAR24[3*VAR41-1:2*VAR41] = VAR16;
4'b1110: VAR24[3*VAR41-1:2*VAR41] = VAR16;
default: VAR24[3*VAR41-1:2*VAR41] = 0;
endcase
case ({VAR6,VAR50,VAR38,VAR46})
4'b1111: VAR24[4*VAR41-1:3*VAR41] = VAR16;
default: VAR24[4*VAR41-1:3*VAR41] = 0;
endcase
end
always @(VAR8, VAR47, VAR43, VAR31, VAR13, VAR52, VAR23, VAR17)
begin
casex ({VAR17,VAR23,VAR52,VAR13})
4'VAR12: VAR27[(VAR41-1):0] = VAR8;
4'VAR55: VAR27[(VAR41-1):0] = VAR47;
4'VAR14: VAR27[(VAR41-1):0] = VAR43;
4'b1000: VAR27[(VAR41-1):0] = VAR31;
default: VAR27[(VAR41-1):0] = 0;
endcase
casex ({VAR17,VAR23,VAR52,VAR13})
4'VAR36: VAR27[2*VAR41-1:VAR41] = VAR47;
4'VAR25: VAR27[2*VAR41-1:VAR41] = VAR43;
4'VAR4: VAR27[2*VAR41-1:VAR41] = VAR43;
4'b1001: VAR27[2*VAR41-1:VAR41] = VAR31;
4'b1010: VAR27[2*VAR41-1:VAR41] = VAR31;
4'b1100: VAR27[2*VAR41-1:VAR41] = VAR31;
default: VAR27[2*VAR41-1:VAR41] = 0;
endcase
casex ({VAR17,VAR23,VAR52,VAR13})
4'VAR28: VAR27[3*VAR41-1:2*VAR41] = VAR43;
4'b1011: VAR27[3*VAR41-1:2*VAR41] = VAR31;
4'b1101: VAR27[3*VAR41-1:2*VAR41] = VAR31;
4'b1110: VAR27[3*VAR41-1:2*VAR41] = VAR31;
default: VAR27[3*VAR41-1:2*VAR41] = 0;
endcase
case ({VAR17,VAR23,VAR52,VAR13})
4'b1111: VAR27[4*VAR41-1:3*VAR41] = VAR31;
default: VAR27[4*VAR41-1:3*VAR41] = 0;
endcase
end
always @(VAR53)
begin
case(VAR53)
4'h1: VAR33 = 8'h01;
4'h2: VAR33 = 8'h02;
4'h4: VAR33 = 8'h08;
4'h8: VAR33 = 8'h80;
default: VAR33 = 8'h0;
endcase
end
always @(VAR24, VAR27, VAR5)
begin
VAR1 = VAR24 | VAR27 << (VAR5 * VAR41);
end
always @(VAR29, VAR33)
begin
case (VAR29)
0:
begin
VAR9 = VAR33[0];
VAR51 = {2{VAR33[1]}};
VAR49 = {4{VAR33[3]}};
end
1:
begin
VAR9 = VAR33[0] << 1;
VAR51 = {2{VAR33[1]}} << 0;
VAR49 = {4{VAR33[3]}} << 0;
end
2:
begin
VAR9 = VAR33[0] << 2;
VAR51 = {2{VAR33[1]}} << 2;
VAR49 = {4{VAR33[3]}} << 0;
end
3:
begin
VAR9 = VAR33[0] << 3;
VAR51 = {2{VAR33[1]}} << 2;
VAR49 = {4{VAR33[3]}} << 0;
end
4:
begin
if (VAR42 == 8)
begin
VAR9 = VAR33[0] << 4;
VAR51 = {2{VAR33[1]}} << 4;
VAR49 = {4{VAR33[3]}} << 4;
end
else
begin
VAR9 = VAR33[0];
VAR51 = {2{VAR33[1]}};
VAR49 = {4{VAR33[3]}};
end
end
5:
begin
VAR9 = VAR33[0] << 5;
VAR51 = {2{VAR33[1]}} << 4;
VAR49 = {4{VAR33[3]}} << 4;
end
6:
begin
VAR9 = VAR33[0] << 6;
VAR51 = {2{VAR33[1]}} << 6;
VAR49 = {4{VAR33[3]}} << 4;
end
7:
begin
VAR9 = VAR33[0] << 7;
VAR51 = {2{VAR33[1]}} << 6;
VAR49 = {4{VAR33[3]}} << 4;
end
8:
begin
VAR9 = VAR33[0] << 0;
VAR51 = {2{VAR33[1]}} << 0;
VAR49 = {4{VAR33[3]}} << 0;
end
default:
begin
VAR9 = 8'h0;
VAR51 = 8'h0;
VAR49 = 8'h0;
end
endcase
end
always @(posedge clk)
begin
VAR7 <= VAR33;
if (VAR33 == 8'h0 || VAR7 != VAR33 )
begin
VAR29 <= 7'h0;
end
else
begin
if( VAR54 == 1'b1)
begin
if (VAR29 > (VAR42 - 1) )
begin
VAR29 <= VAR29 - VAR42 + VAR53;
end
else
begin
VAR29 <= VAR29 + VAR53;
end
if ((VAR29 == (VAR42 - VAR53)) || (VAR33 == (8'h1 << (VAR42 - 1)) ))
begin
VAR57 <= 1'b1;
end
else
begin
VAR57 <= 1'b0;
end
end
else
begin
VAR57 <= 1'b0;
end
end
end
generate
if ( VAR42 == 8 )
begin
always @(posedge clk)
begin
if ((VAR9[0] | VAR51[0] | VAR49[0] | VAR33[VAR42-1]) == 1'b1)
begin
VAR11[(VAR41-1):0] <= VAR1[(VAR41-1):0];
end
if( VAR9[1] == 1'b1)
begin
VAR11[2*VAR41-1:VAR41] <= VAR1[(VAR41-1):0];
end
if ( (VAR51[1] | VAR49[1] | VAR33[VAR42-1]) == 1'b1)
begin
VAR11[2*VAR41-1:VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if ((VAR9[2] | VAR51[2]) == 1'b1)
begin
VAR11[3*VAR41-1:2*VAR41] <= VAR1[(VAR41-1):0];
end
if ((VAR49[2] | VAR33[VAR42-1]) == 1'b1)
begin
VAR11[3*VAR41-1:2*VAR41] <= VAR1[3*VAR41-1:2*VAR41];
end
if (VAR9[3] == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[(VAR41-1):0];
end
if (VAR51[3] == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if ((VAR49[3] | VAR33[VAR42-1]) == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[4*VAR41-1:3*VAR41];
end
if ((VAR9[4] | VAR51[4] | VAR49[4]) == 1'b1)
begin
VAR11[5*VAR41-1:4*VAR41] <= VAR1[(VAR41-1):0];
end
if (VAR33[VAR42-1] == 1'b1)
begin
VAR11[5*VAR41-1:4*VAR41] <= VAR1[5*VAR41-1:4*VAR41];
end
if (VAR9[5] == 1'b1)
begin
VAR11[6*VAR41-1:5*VAR41] <= VAR1[(VAR41-1):0];
end
if ((VAR51[5] | VAR49[5]) == 1'b1)
begin
VAR11[6*VAR41-1:5*VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if (VAR33[VAR42-1] == 1'b1)
begin
VAR11[6*VAR41-1:5*VAR41] <= VAR1[6*VAR41-1:5*VAR41];
end
if ((VAR9[6] | VAR51[6]) == 1'b1)
begin
VAR11[7*VAR41-1:6*VAR41] <= VAR1[(VAR41-1):0];
end
if (VAR49[6] == 1'b1)
begin
VAR11[7*VAR41-1:6*VAR41] <= VAR1[3*VAR41-1:2*VAR41];
end
if (VAR33[VAR42-1] == 1'b1)
begin
VAR11[7*VAR41-1:6*VAR41] <= VAR1[7*VAR41-1:6*VAR41];
end
if (VAR9[7] == 1'b1)
begin
VAR11[8*VAR41-1:7*VAR41] <= VAR1[(VAR41-1):0];
end
if (VAR51[7] == 1'b1)
begin
VAR11[8*VAR41-1:7*VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if (VAR49[7] == 1'b1)
begin
VAR11[8*VAR41-1:7*VAR41] <= VAR1[4*VAR41-1:3*VAR41];
end
if (VAR33[VAR42-1] == 1'b1)
begin
VAR11[8*VAR41-1:7*VAR41] <= VAR1[8*VAR41-1:7*VAR41];
end
end
end
else
begin
always @(posedge clk)
begin
if ((VAR9[0] | VAR51[0] | VAR33[3] ) == 1'b1)
begin
VAR11[(VAR41-1):0] <= VAR1[(VAR41-1):0];
end
if( VAR9[1] == 1'b1)
begin
VAR11[2*VAR41-1:VAR41] <= VAR1[(VAR41-1):0];
end
if ( (VAR51[1] | | VAR33[3] )== 1'b1)
begin
VAR11[2*VAR41-1:VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if ((VAR9[2] | VAR51[2]) == 1'b1)
begin
VAR11[3*VAR41-1:2*VAR41] <= VAR1[(VAR41-1):0];
end
if (( VAR33[3]) == 1'b1)
begin
VAR11[3*VAR41-1:2*VAR41] <= VAR1[3*VAR41-1:2*VAR41];
end
if (VAR9[3] == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[(VAR41-1):0];
end
if (VAR51[3] == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[2*VAR41-1:VAR41];
end
if (VAR33[3] == 1'b1)
begin
VAR11[4*VAR41-1:3*VAR41] <= VAR1[4*VAR41-1:3*VAR41];
end
end
end
endgenerate
endmodule
|
gpl-3.0
|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD
|
project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_tx_pipeline.v
| 22,439 |
module MODULE1 #(
parameter VAR49 = 128, parameter VAR50 = "VAR26", parameter VAR40 = 1,
parameter VAR38 = (VAR49 == 128) ? 2 : 1, parameter VAR39 = VAR49 / 8 ) (
input [VAR49-1:0] VAR62, input VAR31, output VAR44, input [VAR39-1:0] VAR19, input VAR12, input [3:0] VAR6,
output [VAR49-1:0] VAR33, output VAR13, output VAR55, output VAR47, input VAR30, output VAR11, output [VAR38-1:0] VAR59, output VAR17, output VAR18, output VAR2, input VAR23,
input VAR25, input VAR28, input VAR32 );
reg [VAR49-1:0] VAR4;
reg VAR16;
reg [VAR39-1:0] VAR58;
reg [3:0] VAR41;
reg VAR3;
reg VAR45;
reg VAR24;
reg VAR10;
reg VAR5;
wire VAR52;
reg VAR56;
wire VAR48 = VAR31 && VAR44;
wire VAR51 = VAR48 && VAR12;
generate
if(VAR49 == 128) begin : VAR53
assign VAR33 = {VAR4[31:0],
VAR4[63:32],
VAR4[95:64],
VAR4[127:96]};
end
else if(VAR49 == 64) begin : VAR36
assign VAR33 = {VAR4[31:0], VAR4[63:32]};
end
else begin : VAR43
assign VAR33 = VAR4;
end
endgenerate
assign VAR13 = VAR16 && !VAR24;
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(VAR13 && VAR47 && VAR30 && !VAR55) begin
end
else if((VAR24 && VAR55 && VAR47) || !VAR23) begin
end
end
end
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(VAR48 && !VAR12) begin
end
else if(VAR48) begin
end
end
end
generate
if(VAR50 == "VAR27") begin : VAR20
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(!VAR23)
begin
end
else if(!VAR5 && VAR44) begin
end
end
end
assign VAR52 = VAR56;
end
else begin : VAR14
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(VAR10 && !VAR23 && !VAR51)
begin
end
else if(VAR51) begin
end
end
end
assign VAR52 = VAR56 || !VAR23;
end
endgenerate
generate
if(VAR49 == 128) begin : VAR21
wire VAR34 = VAR58[7];
wire VAR1 = VAR58[11];
wire VAR15 = VAR58[15];
assign VAR59[1] = VAR1;
assign VAR59[0] = VAR15 || (VAR34 && !VAR1);
end
else if(VAR49 == 64) begin : VAR60
assign VAR59 = VAR58[7];
end
else begin : VAR9
assign VAR59 = 1'b0;
end
endgenerate
assign VAR55 = VAR3;
assign VAR2 = VAR41[0];
assign VAR17 = VAR41[1];
assign VAR18 = VAR41[2];
assign VAR11 = VAR41[3];
generate
reg VAR42;
if(VAR50 == "VAR26") begin : VAR37
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
end
end
assign VAR47 = VAR42;
assign VAR44 = VAR25;
end
else begin : VAR7
reg [VAR49-1:0] VAR29;
reg VAR54;
reg [VAR39-1:0] VAR8;
reg VAR35;
reg [3:0] VAR22;
reg VAR61;
wire VAR46;
reg VAR57;
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(!VAR44) begin
end
else begin
end
end
end
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(!VAR46) begin
if(VAR57) begin
end
else begin
end
end
end
end
assign VAR46 = VAR47 && !VAR30;
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
end
end
assign VAR47 = VAR16 && !VAR52;
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(VAR5 && !VAR51) begin
end
else if(VAR23) begin
end
else begin
end
end
end
assign VAR44 = VAR45;
end
always @(posedge VAR28) begin
if(VAR32) begin
end
else begin
if(VAR10 && !VAR23 && !VAR51) begin
end
else if(VAR51) begin
end
end
end
endgenerate
endmodule
|
gpl-3.0
|
ptracton/pmodacl2
|
soc/tasks/uart_tasks.v
| 2,827 |
module MODULE1;
task VAR3;
begin
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
end
endtask
task VAR1;
input [7:0] VAR2;
begin
@(posedge VAR5);
end
endtask
task VAR4;
input [7:0] VAR6;
begin
begin
end
end
endtask
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/fa/sky130_fd_sc_lp__fa_2.v
| 2,278 |
module MODULE2 (
VAR8,
VAR2 ,
VAR1 ,
VAR11 ,
VAR4 ,
VAR5,
VAR9,
VAR3 ,
VAR10
);
output VAR8;
output VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR10 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR8,
VAR2 ,
VAR1 ,
VAR11 ,
VAR4
);
output VAR8;
output VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR4 ;
supply1 VAR5;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR10 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR4(VAR4)
);
endmodule
|
apache-2.0
|
DeanoC/ice40k-zpu
|
zpu_rom.v
| 1,076 |
module MODULE1(
input clk,
input [VAR7-1:0] addr,
output [7:0] dout);
parameter VAR7 = 8;
reg [7:0] dout;
reg [7:0] VAR11;
VAR19 #(
.VAR6(256'h80DA0B80C0A8808C0C0B0B0B0BA00881),
.VAR24(256'h050B0B0B0BA00C0B0B0B0B8004000000),
.VAR5(256'h00000001000000000000000000000000),
.VAR13(256'h00000000000000900000000000000090),
.VAR16(256'h0300D080C27F0000B012D080C27F0000),
.VAR4(256'h2813D080C27F00001013D080C27F0300),
.VAR15(256'h1005EF020100000065000D28FC0700C0),
.VAR14(256'h5004EF0201000000700AD080C27F0000),
.VAR8(256'h00FFEE0201000000700AD080C27F0000),
.VAR25(256'h10FEEE0201000000D008D080C27F0000),
.VAR21(256'h9009D080C27F00009405D080C27F0000),
.VAR20(256'h5004EF0201000000A009D080C27F0000),
.VAR22(256'h30FDEE02010000000006D080C27F0000),
.VAR23(256'hE000EF0201000000F00AD080C27F0000),
.VAR12(256'h2E006F757466696C653E2029207C2028),
.VAR3(256'h1005EF02010000000000000000000090)
) VAR2 (
.VAR9(VAR11),
.VAR10(addr[8:0]),
.VAR18(clk), .VAR1(1'b1), .VAR17(1'b1)
);
always @(posedge clk) begin
dout <= VAR11;
end
endmodule
|
mit
|
glennchid/font5-firmware
|
src/verilog/synthesis/MuxModule_old (1).v
| 2,022 |
module MODULE1(
input VAR10,
input [1:0] sel,
input signed[12:0] VAR17,
input signed [12:0] VAR20,
input signed [12:0] VAR16,
input signed [12:0] VAR9,
input signed [12:0] VAR8,
input signed [12:0] VAR15,
output reg signed [14:0] VAR6,
output reg signed [14:0] VAR14,
output reg signed [14:0] VAR18,
output reg signed [14:0] VAR13,
input clk,
input VAR11
);
wire signed [12:0] VAR1, VAR4, VAR12, VAR2;
reg signed [14:0] VAR5,VAR3,VAR19,VAR7;
|
gpl-3.0
|
freecores/orsoc_graphics_accelerator
|
bench/verilog/gfx/interp_bench.v
| 3,012 |
module MODULE1();
parameter VAR15 = 16;
parameter VAR4 = 5;
parameter VAR2 = 3;
reg VAR6; reg VAR13; reg VAR17;
wire VAR11;
reg VAR14;
reg [2*VAR15 -1:0] VAR3; reg [2*VAR15 -1:0] VAR10; reg [2*VAR15 -1:0] VAR8;
reg [VAR15 -1:0] VAR16;
reg [VAR15 -1:0] VAR1;
wire [VAR15 -1:0] VAR12;
wire [VAR15 -1:0] VAR5;
wire [VAR15 -1:0] VAR18; wire [VAR15 -1:0] VAR7;
wire VAR9;
|
gpl-3.0
|
Canaan-Creative/MM
|
verilog/superkdf9/components/spi/wb_spi.v
| 24,050 |
module MODULE1 #(
parameter VAR45 = 0,
parameter VAR47 = 0,
parameter VAR23 = 0,
parameter VAR32 = 7,
parameter VAR7 = 1,
parameter VAR6 = 1,
parameter VAR69 = 32,
parameter VAR11 = 2,
parameter VAR13 = 5,
parameter VAR64 = 2)
(
VAR74, VAR61, VAR31,
VAR44,
VAR4,
VAR8,
VAR1,
VAR60,
VAR58,
VAR71, VAR26,
VAR35,
VAR62,
VAR42,
VAR33,
VAR72,
VAR15,
VAR55,
VAR67,
VAR36,
VAR30,
VAR78,
VAR53,
VAR39
);
input [31:0] VAR74;
input [31:0] VAR61;
input VAR31;
input VAR4;
input VAR44;
input [3:0] VAR8;
input [2:0] VAR1;
input [1:0] VAR60;
input VAR58;
output [31:0] VAR71;
output VAR26;
output VAR35;
output VAR62;
output VAR42;
input VAR33;
output VAR72;
output [VAR6-1:0] VAR15;
output VAR55;
output VAR67;
input VAR36;
input VAR30;
input VAR78;
input VAR53;
input VAR39;
parameter VAR37 = 1;
parameter VAR50 = 3'b000;
parameter VAR27 = 3'b001;
parameter VAR40 = 3'b010;
parameter VAR59 = 3'b011;
parameter VAR76 = 3'b100;
parameter VAR57 = 3'b101;
wire VAR35;
reg VAR26;
reg [31:0] VAR71;
reg [VAR6-1:0] VAR15;
reg VAR55;
reg VAR72;
reg VAR67;
reg VAR17;
reg VAR9;
reg VAR19;
reg VAR70;
reg VAR14;
reg VAR52;
reg VAR51;
reg VAR41;
reg [31:0] VAR29;
reg [VAR69-1:0] VAR54;
reg [VAR69-1:0] VAR66;
reg [VAR69-1:0] VAR75;
reg [VAR69-1:0] VAR20;
reg VAR38;
wire [10:0] VAR46;
reg VAR68;
reg VAR56;
reg VAR5;
reg VAR65;
reg VAR25;
reg VAR24;
wire [8:0] VAR16;
reg VAR63;
reg VAR73;
reg VAR3;
reg VAR77;
reg VAR12;
wire VAR48;
assign VAR62 = 1'b0;
assign VAR42 = 1'b0;
always @(posedge VAR53 or posedge VAR39)
if(VAR39) begin
VAR17 <= #VAR37 1'b0;
VAR9 <= #VAR37 1'b0;
VAR19 <= #VAR37 1'b0;
VAR70 <= #VAR37 1'b0;
VAR14 <= #VAR37 1'b0;
end else begin
VAR17 <= #VAR37 (VAR74[7:0] == 8'h00);
VAR9 <= #VAR37 (VAR74[7:0] == 8'h04);
VAR19 <= #VAR37 (VAR74[7:0] == 8'h08);
VAR70 <= #VAR37 (VAR74[7:0] == 8'h0C);
VAR14 <= #VAR37 (VAR74[7:0] == 8'h10);
end
always @(posedge VAR53 or posedge VAR39)
if(VAR39) begin
VAR52 <= #VAR37 1'b0;
VAR51 <= #VAR37 1'b0;
end else begin
VAR52 <= #VAR37 VAR31 && VAR4 && VAR44;
VAR51 <= #VAR37 !VAR31 && VAR4 && VAR44;
end
always @(posedge VAR53 or posedge VAR39)
if(VAR39)
VAR29 <= #VAR37 32'h0;
end
else
VAR29 <= #VAR37 VAR61;
always @(posedge VAR53 or posedge VAR39)
if(VAR39)
VAR54 <= #VAR37 'h0;
end
else if (VAR38)
VAR54 <= #VAR37 VAR75;
always @(posedge VAR53 or posedge VAR39)
if(VAR39)
VAR66 <= #VAR37 'h0;
else if (VAR52 && VAR9 && VAR3)
VAR66 <= #VAR37 VAR29;
assign VAR48 = VAR63 | VAR73;
assign VAR16 = {VAR48,VAR77,VAR3,VAR12,VAR63,VAR73,3'b000};
always @(posedge VAR53 or posedge VAR39)
if (VAR39) begin
VAR68 <= #VAR37 1'b0;
VAR56 <= #VAR37 1'b0;
VAR5 <= #VAR37 1'b0;
VAR65 <= #VAR37 1'b0;
VAR25 <= #VAR37 1'b0;
VAR24 <= #VAR37 1'b0; end
else if(VAR52 && VAR70) begin
VAR68 <= #VAR37 VAR29[3];
VAR56 <= #VAR37 VAR29[4];
VAR5 <= #VAR37 VAR29[6];
VAR65 <= #VAR37 VAR29[7];
VAR25 <= #VAR37 VAR29[8];
VAR24 <= #VAR37 VAR29[10]; end
assign VAR35 = (VAR25 & (VAR68 & VAR73 | VAR56 & VAR63)) |
(VAR5 & VAR3) |
(VAR65 & VAR77);
always @(posedge VAR53 or posedge VAR39) begin
if (VAR39)
VAR26 <= 1'b0;
end
else if (VAR26)
VAR26 <= 1'b0;
else if (VAR4 && VAR44 && (VAR31 || VAR41))
VAR26 <= 1'b1;
end
always @(posedge VAR53 or posedge VAR39) begin
if (VAR39)
VAR41 <= 1'b0;
end
else if (VAR26)
VAR41 <= 1'b0;
else if (VAR4 && VAR44 && ~VAR31)
VAR41 <= 1'b1;
end
generate
if (VAR7 == 1) begin
reg [VAR6-1:0] VAR49;
reg [VAR13-1:0] VAR34;
reg [5:0] VAR21;
reg VAR10;
reg [2:0] VAR28;
reg [2:0] VAR22;
assign VAR46 = {VAR24,1'b0,VAR25,VAR65,VAR5,1'b0,VAR56,VAR68,3'h0};
always @(posedge VAR53 or posedge VAR39)
if(VAR39)
VAR10 <= #VAR37 1'b0;
end
else if (VAR52 && VAR9)
VAR10 <= #VAR37 1'b1;
else if (VAR28 == VAR27)
VAR10 <= #VAR37 1'b0;
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR71 <= #VAR37 32'h0;
else if (VAR51)
VAR71 <= #VAR37 VAR17 ? VAR54 :
VAR9 ? VAR66 :
VAR19 ? VAR16 :
VAR70 ? VAR46:
VAR14 ? VAR49 :
32'h0;
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR49 <= #VAR37 'h0;
else if (VAR52 && VAR14)
VAR49 <= #VAR37 VAR29;
always @(posedge VAR53 or posedge VAR39) begin
if (VAR39)
VAR15 <= {VAR6{1'b1}};
end
else if (VAR24)
VAR15 <= (~VAR49);
else if ((VAR28 == VAR59) || (VAR28 == VAR40) || (VAR28 == VAR76))
VAR15 <= (~VAR49);
else
VAR15 <= {VAR6{1'b1}};
end
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR55 <= #VAR37 VAR23;
else if ((VAR28 == VAR59) && (VAR34 == VAR32))
VAR55 <= #VAR37 ~VAR55;
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR75 <= #VAR37 'h0;
else if ((VAR34 == VAR32) && (VAR47 == VAR55) && (VAR28 == VAR59)) begin
if (VAR45)
VAR75 <= #VAR37 {VAR33,VAR75[VAR69-1:1]};
end
else
VAR75 <= #VAR37 {VAR75,VAR33};
end
always @(posedge VAR53 or posedge VAR39) begin
if (VAR39)
VAR38 <= 1'b0;
end
else if ((VAR28 == VAR59) && (VAR22 !== VAR59))
VAR38 <= 1'b1;
else if (VAR38)
VAR38 <= 1'b0;
end
always @(posedge VAR53 or posedge VAR39)
if (VAR39 || (VAR28 == VAR50))
VAR34 <= 0;
else if (VAR34 == VAR32)
VAR34 <= 0;
else
VAR34 <= VAR34 + 1;
always @(posedge VAR53 or posedge VAR39) begin
if (VAR39)
VAR28 <= VAR50;
end
else
VAR28 <= VAR22;
end
wire [5:0] VAR43 = (VAR23 == VAR47) ?
VAR69 - 1 :
VAR69;
always @
VAR67 <= #VAR37 VAR45 ? VAR66[VAR18] :
VAR66[VAR69-VAR18-1];
end
always @(negedge VAR78 or posedge VAR39)
if (VAR39)
VAR18 <= #VAR37 'h0;
else if (VAR18 == VAR69 - 1)
VAR18 <= #VAR37 'h0;
else if (!VAR30)
VAR18 <= #VAR37 VAR18 + 1;
always @(negedge VAR78 or posedge VAR39)
if (VAR39)
VAR2 <= #VAR37 1'b0;
else if (VAR18 == VAR69 - 1)
VAR2 <= #VAR37 1'b1;
else
VAR2 <= #VAR37 1'b0;
end else begin
if (VAR23 == 1) begin
always @(*)
VAR67 <= #VAR37 VAR45 ? VAR66[VAR18] :
VAR66[VAR69-VAR18-1];
end
else begin
always @(posedge VAR78 or posedge VAR39)
if (VAR39)
VAR67 <= #VAR37 1'b0;
end
else
VAR67 <= #VAR37 VAR45 ? VAR66[VAR18] :
VAR66[VAR69-VAR18-1];
end
always @(posedge VAR78 or posedge VAR39)
if (VAR39)
VAR18 <= #VAR37 'h0;
else if (VAR18 == VAR69 - 1)
VAR18 <= #VAR37 'h0;
else if (!VAR30)
VAR18 <= #VAR37 VAR18 + 1;
always @(posedge VAR78 or posedge VAR39)
if (VAR39)
VAR2 <= #VAR37 1'b0;
else if (VAR18 == VAR69 - 1)
VAR2 <= #VAR37 1'b1;
else
VAR2 <= #VAR37 1'b0;
end
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR3 <= #VAR37 1'b1;
else if (VAR52 && VAR9 && VAR26)
VAR3 <= #VAR37 1'b0;
else if (VAR2)
VAR3 <= #VAR37 1'b1;
always @(posedge VAR53 or posedge VAR39)
if (VAR39)
VAR12 <= #VAR37 1'b1;
else if (VAR52 && VAR9 && VAR26)
VAR12 <= #VAR37 1'b0;
else if (VAR2)
VAR12 <= #VAR37 1'b1;
always @(posedge VAR53 or posedge VAR39)
if(VAR39)
VAR63 <= #VAR37 1'b0;
else if(!VAR3 && VAR52 && VAR9 && VAR26)
VAR63 <= #VAR37 1'b1;
else if(VAR52 && VAR19 && VAR26)
VAR63 <= #VAR37 1'b0;
end
endgenerate
endmodule
|
unlicense
|
ludisu13/Estructuras2
|
Tarea_final_Memoria/generator.v
| 1,703 |
module MODULE2(clk, VAR4, VAR3, VAR1, VAR6, VAR7, VAR2);
output clk, VAR3, VAR1, VAR6;
output [7:0] VAR4;
output [9:0] VAR7;
output [9:0] VAR2;
MODULE1 MODULE1(clk);
VAR8 VAR5(VAR4, VAR3, VAR1, VAR6, VAR7, VAR2);
endmodule
module MODULE1(clk);
output reg clk;
begin
begin
begin
|
gpl-3.0
|
sabertazimi/hust-lab
|
verilog/labs/lab5/src/_4bit_binary_multiplier.v
| 2,997 |
module MODULE1(
module 4bitbinarymultiplier
(
input VAR20,
input clk,
input [VAR6:0] VAR16,
input [VAR6:0] VAR22,
output [((VAR6*2)-1):0] VAR2,
output VAR3
);
reg [(VAR6-1):0] VAR9 [0: (2*(2**VAR6)-1)];
wire VAR5, VAR14, VAR19, VAR23, VAR15;
wire VAR18;
wire [(VAR6-1):0] VAR4, VAR10;
wire VAR7;
wire VAR8, VAR12, VAR1;
wire [(VAR6-1):0] VAR13, VAR11, VAR21;
wire [(VAR6-1):0] VAR24, VAR17;
assign VAR4 = VAR21 & {(VAR6){VAR11[0]}};
assign VAR2 = {VAR13, VAR11};
assign VAR18 = clk;
assign VAR24 = VAR9[VAR16];
assign VAR17 = VAR9[VAR22];
|
mit
|
TalentlessAlpaca/Automated_Vacuum_Cleaner
|
Ultrasonico/ultrasonic_ctrl.v
| 1,914 |
module MODULE1 (
input clk ,
input enable ,
input VAR5 ,
output [15:0] VAR2 ,
output reg VAR11
) ;
reg [2:0] state ;
reg VAR6 ;
reg VAR18 ;
reg VAR7 ;
reg VAR13 ;
wire [31:0] VAR19 ;
wire VAR14 ;
wire VAR12 ;
localparam VAR4 = 3'b000 ; localparam VAR8 = 3'b001 ; localparam VAR16 = 3'b010 ;
always @ ( negedge clk )
if ( enable )
case ( state )
VAR4:
state <= VAR8 ;
VAR8:
if ( !VAR11 )
state <= VAR16 ;
else
state <= VAR8 ;
VAR16:
state <= state ;
default:
state <= VAR4 ;
endcase
else
state <= VAR4 ;
always @ ( posedge clk)
case ( state )
VAR4: begin
VAR6 <= 0 ;
VAR18 <= 0 ;
VAR7 <= 0 ;
VAR13 <= 0 ;
end VAR8: begin
VAR6 <= 1 ;
VAR18 <= 1 ;
VAR7 <= 1 ;
VAR13 <= 1 ;
VAR11 <= 1 ;
end VAR16: begin
VAR6 <= 1 ;
VAR18 <= 1 ;
VAR7 <= 1 ;
VAR13 <= 0 ;
VAR11 <= 0 ;
end default: begin
VAR6 <= 0 ;
VAR18 <= 0 ;
VAR7 <= 0 ;
VAR13 <= 0 ;
VAR11 <= 0 ;
end
endcase
VAR15 VAR10 (
.clk (clk) ,
.enable (VAR7) ,
.VAR9 (VAR6) ,
.VAR19(VAR19)
) ;
VAR17 VAR1 (
.clk (clk) ,
.VAR5 (VAR5) ,
.VAR9 (VAR18) ,
.VAR2 (VAR2) ,
.VAR3 (VAR12)
);
VAR20 VAR20 (
.clk(clk),
.enable(VAR13) ,
.VAR19(VAR19) ,
.VAR14(VAR14)
);
endmodule
|
mit
|
CospanDesign/nysa-verilog
|
verilog/generic/uart_controller.v
| 6,880 |
module MODULE1 #(
parameter VAR59 = 115200
)(
input clk,
input rst,
input VAR40,
output VAR35,
output reg VAR58,
input VAR53,
input VAR57,
input VAR12,
output [31:0] VAR3,
input VAR28,
input [31:0] VAR8,
output [31:0] VAR5,
input VAR16,
input [7:0] VAR38,
output VAR27,
output [31:0] VAR32,
output [31:0] VAR52,
output VAR4,
output [7:0] VAR2,
input VAR9,
output VAR39,
output [31:0] VAR31,
output [31:0] VAR18,
output VAR55
);
wire [31:0] VAR1;
reg VAR11;
wire [7:0] VAR51;
wire VAR34;
wire VAR10;
wire VAR17;
wire [31:0] VAR56;
wire VAR47;
wire VAR33;
reg VAR23;
reg [7:0] VAR37;
wire VAR36;
wire [7:0] VAR20;
wire VAR21;
wire VAR45;
wire VAR19;
reg VAR50;
wire VAR12;
reg [3:0] state;
VAR54 VAR7 (
.clk (clk ),
.rst (rst || VAR57 ),
.VAR44 (VAR52 ),
.VAR16 (VAR16 ),
.VAR32 (VAR32 ),
.VAR38 (VAR38 ),
.VAR9 (VAR11 ),
.VAR31 (VAR1 ),
.VAR2 (VAR51 ),
.VAR48 (VAR4 ),
.VAR22 (VAR34 ),
.VAR42 (VAR10 ),
.VAR30 (VAR17 )
);
VAR54 VAR6 (
.clk (clk ),
.rst (rst || VAR57 ),
.VAR44 (VAR18 ),
.VAR16 (VAR36 ),
.VAR32 (VAR56 ),
.VAR38 (VAR20 ),
.VAR9 (VAR9 ),
.VAR31 (VAR31 ),
.VAR2 (VAR2 ),
.VAR48 (VAR55 ),
.VAR22 (VAR47 ),
.VAR42 (VAR33 ),
.VAR30 (VAR39 )
);
VAR29 #(
.VAR59 (VAR59 )
) VAR43(
.clk (clk ),
.rst (rst || VAR57 ),
.VAR40 (VAR40 ),
.VAR35 (VAR35 ),
.VAR23 (VAR23 ),
.VAR37 (VAR37 ),
.VAR36 (VAR36 ),
.VAR20 (VAR20 ),
.VAR21 (VAR21 ),
.VAR45 (VAR45 ),
.VAR19 (VAR19 ),
.VAR28 (VAR28 ),
.VAR14 (VAR8 ),
.VAR5 (VAR5 ),
.VAR3 (VAR3 )
);
parameter VAR15 = 3'h0;
parameter VAR25 = 3'h1;
parameter VAR24 = 3'h2;
assign VAR27 = VAR10;
always @ (posedge clk) begin
if (rst) begin
VAR58 <= 0;
state <= VAR15;
VAR50 <= 0;
VAR11 <= 0;
VAR37 <= 0;
end
else begin
VAR23 <= 0;
VAR11 <= 0;
VAR50 <= 0;
VAR58 <= 0;
if (VAR11) begin
VAR37 <= VAR51;
VAR23 <= 1;
end
if (!VAR17 && !VAR45 && !VAR23 && !VAR11 && !VAR16) begin
if (VAR12) begin
if (~VAR53) begin
: VAR46 VAR26 VAR49", );
VAR11 <= 1;
end
end
else begin
VAR11 <= 1;
end
end
if (VAR33 && VAR12) begin
: VAR13 VAR41", );
VAR58 <= 1;
end
end
end
endmodule
|
mit
|
SymbiFlow/yosys
|
techlibs/xilinx/lut_map.v
| 3,501 |
module MODULE1 (VAR2, VAR19);
parameter VAR35 = 0;
parameter VAR21 = 0;
input [VAR35-1:0] VAR2;
output VAR19;
generate
if (VAR35 == 1) begin
if (VAR21 == 2'b01) begin
VAR20 VAR15 (.VAR36(VAR19), .VAR5(VAR2[0]));
end else begin
VAR30 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]));
end
end else
if (VAR35 == 2) begin
VAR10 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]), .VAR33(VAR2[1]));
end else
if (VAR35 == 3) begin
VAR24 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]), .VAR33(VAR2[1]), .VAR18(VAR2[2]));
end else
if (VAR35 == 4) begin
VAR6 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]), .VAR33(VAR2[1]), .VAR18(VAR2[2]),
.VAR23(VAR2[3]));
end else
if (VAR35 == 5 && VAR35 <= VAR34) begin
VAR9 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]), .VAR33(VAR2[1]), .VAR18(VAR2[2]),
.VAR23(VAR2[3]), .VAR12(VAR2[4]));
end else
if (VAR35 == 6 && VAR35 <= VAR34) begin
VAR28 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]), .VAR33(VAR2[1]), .VAR18(VAR2[2]),
.VAR23(VAR2[3]), .VAR12(VAR2[4]), .VAR1(VAR2[5]));
end else
if (VAR35 == 5 && VAR35 > VAR34) begin
wire VAR13, VAR4;
MODULE1 #(.VAR21(VAR21[15: 0]), .VAR35(4)) VAR3 (.VAR2(VAR2[3:0]), .VAR19(VAR13));
MODULE1 #(.VAR21(VAR21[31:16]), .VAR35(4)) VAR8 (.VAR2(VAR2[3:0]), .VAR19(VAR4));
VAR14 VAR16(.VAR17(VAR13), .VAR33(VAR4), .VAR37(VAR2[4]), .VAR36(VAR19));
end else
if (VAR35 == 6 && VAR35 > VAR34) begin
wire VAR13, VAR4;
MODULE1 #(.VAR21(VAR21[31: 0]), .VAR35(5)) VAR3 (.VAR2(VAR2[4:0]), .VAR19(VAR13));
MODULE1 #(.VAR21(VAR21[63:32]), .VAR35(5)) VAR8 (.VAR2(VAR2[4:0]), .VAR19(VAR4));
VAR26 VAR32(.VAR17(VAR13), .VAR33(VAR4), .VAR37(VAR2[5]), .VAR36(VAR19));
end else
if (VAR35 == 7) begin
wire VAR13, VAR4;
MODULE1 #(.VAR21(VAR21[ 63: 0]), .VAR35(6)) VAR3 (.VAR2(VAR2[5:0]), .VAR19(VAR13));
MODULE1 #(.VAR21(VAR21[127:64]), .VAR35(6)) VAR8 (.VAR2(VAR2[5:0]), .VAR19(VAR4));
VAR25 VAR7(.VAR17(VAR13), .VAR33(VAR4), .VAR37(VAR2[6]), .VAR36(VAR19));
end else
if (VAR35 == 8) begin
wire VAR13, VAR4;
MODULE1 #(.VAR21(VAR21[127: 0]), .VAR35(7)) VAR3 (.VAR2(VAR2[6:0]), .VAR19(VAR13));
MODULE1 #(.VAR21(VAR21[255:128]), .VAR35(7)) VAR8 (.VAR2(VAR2[6:0]), .VAR19(VAR4));
VAR31 VAR29(.VAR17(VAR13), .VAR33(VAR4), .VAR37(VAR2[7]), .VAR36(VAR19));
end else
if (VAR35 == 9) begin
wire VAR13, VAR4;
MODULE1 #(.VAR21(VAR21[255: 0]), .VAR35(8)) VAR3 (.VAR2(VAR2[7:0]), .VAR19(VAR13));
MODULE1 #(.VAR21(VAR21[511:256]), .VAR35(8)) VAR8 (.VAR2(VAR2[7:0]), .VAR19(VAR4));
VAR22 VAR27(.VAR17(VAR13), .VAR33(VAR4), .VAR37(VAR2[8]), .VAR36(VAR19));
end else begin
wire VAR11 = 1;
end
endgenerate
endmodule
|
isc
|
olajep/oh
|
src/emesh/hdl/packet2emesh.v
| 2,814 |
module MODULE1 #(parameter VAR4 = 32, parameter VAR2 = 104) (
input [VAR2-1:0] VAR1,
output VAR13, output [1:0] VAR8, output [4:0] VAR5, output [VAR4-1:0] VAR9, output [VAR4-1:0] VAR12, output [VAR4-1:0] VAR11 );
generate
if(VAR2==104)
begin : VAR7
assign VAR13 = VAR1[0];
assign VAR8[1:0] = VAR1[2:1];
assign VAR5[4:0] = {1'b0,VAR1[6:3]};
assign VAR9[31:0] = VAR1[39:8];
assign VAR12[31:0] = VAR1[103:72];
assign VAR11[31:0] = VAR1[71:40];
end
else if(VAR2==136)
begin : VAR14
assign VAR13 = VAR1[0];
assign VAR8[1:0] = VAR1[2:1];
assign VAR5[4:0] = VAR1[7:3];
assign VAR9[63:0] = {VAR1[135:104],VAR1[39:8]};
assign VAR12[63:0] = {VAR1[71:40],VAR1[135:72]};
assign VAR11[63:0] = VAR1[103:40];
end
else if(VAR2==72)
begin : VAR6
assign VAR13 = VAR1[0];
assign VAR8[1:0] = VAR1[2:1];
assign VAR5[4:0] = VAR1[7:3];
assign VAR9[31:0] = VAR1[39:8];
assign VAR11[31:0] = VAR1[71:40];
end
else if(VAR2==40)
begin : VAR10
assign VAR13 = VAR1[0];
assign VAR8[1:0] = VAR1[2:1];
assign VAR5[4:0] = VAR1[7:3];
assign VAR9[15:0] = VAR1[23:8];
assign VAR11[15:0] = VAR1[39:24];
end
else
begin : VAR3
|
mit
|
alexforencich/verilog-lfsr
|
rtl/lfsr.v
| 15,991 |
module MODULE1 #
(
parameter VAR2 = 31,
parameter VAR20 = 31'h10000001,
parameter VAR16 = "VAR19",
parameter VAR17 = 0,
parameter VAR9 = 0,
parameter VAR18 = 8,
parameter VAR12 = "VAR13"
)
(
input wire [VAR18-1:0] VAR8,
input wire [VAR2-1:0] VAR3,
output wire [VAR18-1:0] VAR6,
output wire [VAR2-1:0] VAR15
);
reg [VAR2-1:0] VAR21[VAR2-1:0];
reg [VAR18-1:0] VAR4[VAR2-1:0];
reg [VAR2-1:0] VAR1[VAR18-1:0];
reg [VAR18-1:0] VAR5[VAR18-1:0];
reg [VAR2-1:0] VAR7 = 0;
reg [VAR18-1:0] VAR14 = 0;
integer VAR10, VAR11, VAR22;
|
mit
|
sstallion/apple-mini
|
cpld/cpld.v
| 2,276 |
module MODULE1(input reset,
input VAR3,
input [3:0] addr,
output VAR13, VAR28, VAR17, VAR20, VAR23, VAR2,
input VAR25,
output VAR24,
input VAR18,
output VAR11, VAR6,
input VAR12, VAR8,
output [6:0] VAR27,
input [6:0] VAR7,
output VAR21,
input VAR26, VAR14,
output VAR22, VAR5,
inout [7:0] VAR9);
VAR15 VAR10(
.addr(addr),
.VAR13(VAR13),
.VAR28(VAR28),
.VAR17(VAR17),
.VAR20(VAR20),
.VAR23(VAR23),
.VAR2(VAR2)
);
VAR16 VAR19(
.reset(reset),
.VAR25(VAR25),
.VAR24(VAR24)
);
VAR4 VAR1(
.reset(reset),
.VAR3(VAR3),
.clk(VAR25),
.VAR18(VAR18),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR27(VAR27),
.VAR7(VAR7),
.VAR21(VAR21),
.VAR26(VAR26),
.VAR14(VAR14),
.VAR22(VAR22),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/a21o/sky130_fd_sc_hdll__a21o.blackbox.v
| 1,334 |
module MODULE1 (
VAR7 ,
VAR3,
VAR6,
VAR1
);
output VAR7 ;
input VAR3;
input VAR6;
input VAR1;
supply1 VAR5;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule
|
apache-2.0
|
kDaniu/miaow
|
src/verilog/rtl/dispatcher/global_resource_table.v
| 26,303 |
module MODULE1
(
VAR15, VAR100, VAR142,
VAR93, VAR46, VAR110,
VAR64, VAR163, VAR33,
VAR169, VAR160, VAR149,
VAR129, VAR32, VAR67,
VAR189, VAR6,
clk, rst, VAR139, VAR61,
VAR102, VAR114,
VAR130, VAR97, VAR190,
VAR26, VAR98,
VAR49, VAR44,
VAR19, VAR181,
VAR18, VAR85
);
parameter VAR121 = 64;
parameter VAR79 = 6;
parameter VAR104 = 3;
parameter VAR89 = 10;
parameter VAR184 = 1024;
parameter VAR52 = 10;
parameter VAR20 = 1024;
parameter VAR108 = 10;
parameter VAR140 = 1024;
parameter VAR145 = 10;
parameter VAR124 = 4;
parameter VAR141 = 6;
parameter VAR135 = 40;
parameter VAR42 = 10;
parameter VAR73 = 1024;
localparam VAR29 = 2**VAR104;
localparam VAR8 = VAR121/VAR29;
input clk, rst;
input [VAR79-1:0] VAR139;
input [VAR145-1:0] VAR61;
input VAR102;
input VAR114;
input [VAR145-1:0] VAR130;
input [VAR124-1:0] VAR97;
input [VAR79-1 :0] VAR190;
input [VAR89-1 :0] VAR26;
input [VAR52-1 :0] VAR98;
input [VAR108-1 :0] VAR49;
input [VAR42-1 :0] VAR44;
input [VAR89 :0] VAR19;
input [VAR52 :0] VAR181;
input [VAR108 :0] VAR18;
input [VAR42 :0] VAR85;
output VAR15;
output [VAR141:0] VAR100;
output [VAR79-1 :0] VAR142;
output [VAR89-1 :0] VAR93;
output [VAR89 :0] VAR46;
output [VAR52-1 :0] VAR110;
output [VAR52 :0] VAR64;
output [VAR108-1 :0] VAR163;
output [VAR108 :0] VAR33;
output [VAR42-1 :0] VAR169;
output [VAR42 :0] VAR160;
output VAR149;
output [VAR145-1:0] VAR129;
output [VAR79-1 :0] VAR32;
output VAR67;
output [VAR145-1:0] VAR189;
output [VAR79-1 :0] VAR6;
reg [VAR79-1:0] VAR134;
reg [VAR145-1:0] VAR22;
reg VAR151;
reg VAR112;
reg [VAR124-1:0] VAR74;
reg [VAR145-1:0] VAR58;
reg [VAR79-1 :0] VAR178;
reg [VAR89-1 :0] VAR127;
reg [VAR52-1 :0] VAR173;
reg [VAR108-1 :0] VAR62;
reg [VAR42-1 :0] VAR136;
reg [VAR89 :0] VAR183;
reg [VAR52 :0] VAR99;
reg [VAR108 :0] VAR92;
reg [VAR42 :0] VAR172;
reg VAR51;
reg VAR72;
reg [VAR79-VAR104-1:0] VAR103,
VAR96;
reg [VAR145-1:0] VAR25,
VAR69;
reg [VAR124-1:0] VAR137;
reg [VAR89-1 :0] VAR91;
reg [VAR52-1 :0] VAR132;
reg [VAR108-1 :0] VAR194;
reg [VAR42-1 :0] VAR36;
reg [VAR89 :0] VAR50;
reg [VAR52 :0] VAR2;
reg [VAR108 :0] VAR143;
reg [VAR42 :0] VAR150;
reg [VAR104-1:0] VAR159,
VAR193;
reg [VAR29-1:0] VAR117;
reg [VAR29-1:0] VAR195;
reg VAR38, VAR125;
reg [VAR29-1:0] VAR101,
VAR162;
reg [VAR104-1:0] VAR196;
reg [VAR79-VAR104-1:0] VAR126;
wire [VAR141-1:0] VAR4;
reg [VAR89-1 :0] VAR180;
reg [VAR52-1 :0] VAR34;
reg [VAR108-1 :0] VAR182;
reg [VAR89 :0] VAR152;
reg [VAR52 :0] VAR113;
reg [VAR108 :0] VAR63;
reg [VAR42 :0] VAR192;
wire [VAR29-1:0] VAR156,
VAR68;
wire [(VAR89+1)*VAR29-1:0] VAR144;
wire [VAR89*VAR29-1:0] VAR90;
wire [VAR29-1:0] VAR148,
VAR131;
wire [(VAR52+1)*VAR29-1:0] VAR12;
wire [VAR52*VAR29-1:0] VAR87;
wire [VAR29-1:0] VAR76,
VAR75;
wire [(VAR108+1)*VAR29-1:0] VAR82;
wire [VAR108*VAR29-1:0] VAR48;
reg [VAR29-1:0] VAR35,
VAR77,
VAR71;
reg VAR118,
VAR185,
VAR45;
reg [VAR104-1:0] VAR188,
VAR54;
wire [VAR141-1:0] VAR11;
wire [VAR141:0] VAR164;
wire [VAR89:0] VAR157;
wire [VAR89-1:0] VAR7;
wire [VAR52:0] VAR176;
wire [VAR52-1:0] VAR60;
wire [VAR108:0] VAR1;
wire [VAR108-1:0] VAR21;
wire [VAR42:0] VAR174;
reg [VAR104-1:0] VAR41;
localparam VAR57 = VAR79-VAR104+VAR145+2;
wire VAR28, VAR3;
wire [VAR79-VAR104-1:0] VAR120;
wire [VAR145-1:0] VAR154;
assign VAR15 = (VAR28 | VAR3) &
VAR45;
assign VAR100 = VAR164;
assign VAR142 = {VAR41,VAR120};
assign VAR93 = VAR7;
assign VAR46 = VAR157;
assign VAR110 = VAR60;
assign VAR64 = VAR176;
assign VAR163 = VAR21;
assign VAR33 = VAR1;
assign VAR160 = VAR174;
assign VAR149 = VAR28 & VAR45;
assign VAR129 = VAR154;
assign VAR32 = {VAR41,VAR120};
assign VAR67 = VAR3 & VAR45 ;
assign VAR189 = VAR154;
assign VAR6 = {VAR41,VAR120};
VAR165
.VAR30 (VAR57),
.VAR175 (VAR104),
.VAR14 (VAR29))
VAR161
(
.VAR133 ({VAR120,VAR154,
VAR28,VAR3}),
.rst (rst),
.clk (clk),
.VAR177 (VAR51 |
VAR72),
.VAR147 (VAR159),
.VAR170 ({VAR103,VAR25,
VAR51,
VAR72} ),
.VAR23 (1'b1),
.VAR16 (VAR188));
VAR111
.VAR121 (VAR121),
.VAR79 (VAR79),
.VAR145 (VAR145),
.VAR141 (VAR141),
.VAR135 (VAR135),
.VAR104 (VAR104))
VAR138
(
.VAR191 (VAR4),
.VAR128 (VAR164),
.rst (rst),
.clk (clk),
.VAR27 (VAR51),
.VAR47 (VAR72),
.VAR171 ({VAR159,
VAR103}),
.VAR31 (VAR25),
.VAR146 (VAR137),
.VAR24 (VAR188));
VAR167
.VAR121 (VAR121),
.VAR79 (VAR79),
.VAR104 (VAR104),
.VAR141 (VAR141),
.VAR135 (VAR135),
.VAR42 (VAR42),
.VAR73 (VAR73))
VAR105
(
.VAR86 (VAR174),
.rst (rst),
.clk (clk),
.VAR80 (|VAR101),
.VAR55 (|VAR162),
.VAR53 ({VAR196,VAR126}),
.VAR43 (VAR4),
.VAR17 (VAR192),
.VAR84 (VAR188));
VAR166
.VAR79 (VAR79-VAR104),
.VAR121 (VAR8),
.VAR141 (VAR141),
.VAR9 (VAR135),
.VAR37 (VAR89),
.VAR5 (VAR184))
VAR109 [VAR29-1:0]
(
.VAR39 (VAR156),
.VAR95 (VAR144),
.VAR10 (VAR90),
.clk (clk),
.rst (rst),
.VAR186 (VAR101),
.VAR65 (VAR162),
.VAR83 (VAR126),
.VAR122 (VAR126),
.VAR155 (VAR4),
.VAR78 (VAR4),
.VAR88 (VAR152),
.VAR116 (VAR180));
VAR56
.VAR37 (VAR89),
.VAR104 (VAR104),
.VAR29 (VAR29))
VAR81
(
.VAR66 (VAR68),
.VAR107 (VAR157),
.VAR115 (VAR7),
.clk (clk),
.rst (rst),
.VAR39 (VAR156),
.VAR153 (VAR144),
.VAR119 (VAR90),
.VAR40 (VAR71));
VAR166
.VAR79 (VAR79-VAR104),
.VAR121 (VAR8),
.VAR141 (VAR141),
.VAR9 (VAR135),
.VAR37 (VAR52),
.VAR5 (VAR20))
VAR187 [VAR29-1:0]
(
.VAR39 (VAR148),
.VAR95 (VAR12),
.VAR10 (VAR87),
.clk (clk),
.rst (rst),
.VAR186 (VAR101),
.VAR65 (VAR162),
.VAR83 (VAR126),
.VAR122 (VAR126),
.VAR155 (VAR4),
.VAR78 (VAR4),
.VAR88 (VAR113),
.VAR116 (VAR34));
VAR56
.VAR37 (VAR52),
.VAR104 (VAR104),
.VAR29 (VAR29))
VAR59
(
.VAR66 (VAR131),
.VAR107 (VAR176),
.VAR115 (VAR60),
.clk (clk),
.rst (rst),
.VAR39 (VAR148),
.VAR153 (VAR12),
.VAR119 (VAR87),
.VAR40 (VAR71));
VAR166
.VAR79 (VAR79-VAR104),
.VAR121 (VAR8),
.VAR141 (VAR141),
.VAR9 (VAR135),
.VAR37 (VAR108),
.VAR5 (VAR140))
VAR70 [VAR29-1:0]
(
.VAR39 (VAR76),
.VAR95 (VAR82),
.VAR10 (VAR48),
.clk (clk),
.rst (rst),
.VAR186 (VAR101),
.VAR65 (VAR162),
.VAR83 (VAR126),
.VAR122 (VAR126),
.VAR155 (VAR4),
.VAR78 (VAR4),
.VAR88 (VAR63),
.VAR116 (VAR182));
VAR56
.VAR37 (VAR108),
.VAR104 (VAR104),
.VAR29 (VAR29))
VAR168
(
.VAR66 (VAR75),
.VAR107 (VAR1),
.VAR115 (VAR21),
.clk (clk),
.rst (rst),
.VAR39 (VAR76),
.VAR153 (VAR82),
.VAR119 (VAR48),
.VAR40 (VAR71));
always @( posedge clk or posedge rst ) begin
if (rst) begin
VAR35 <= {VAR29{1'b0}};
VAR51 <= 1'h0;
VAR178 <= {VAR79{1'b0}};
VAR150 <= {(1+(VAR42)){1'b0}};
VAR172 <= {(1+(VAR42)){1'b0}};
VAR36 <= {VAR42{1'b0}};
VAR136 <= {VAR42{1'b0}};
VAR143 <= {(1+(VAR108)){1'b0}};
VAR92 <= {(1+(VAR108)){1'b0}};
VAR194 <= {VAR108{1'b0}};
VAR62 <= {VAR108{1'b0}};
VAR2 <= {(1+(VAR52)){1'b0}};
VAR99 <= {(1+(VAR52)){1'b0}};
VAR132 <= {VAR52{1'b0}};
VAR173 <= {VAR52{1'b0}};
VAR50 <= {(1+(VAR89)){1'b0}};
VAR183 <= {(1+(VAR89)){1'b0}};
VAR91 <= {VAR89{1'b0}};
VAR127 <= {VAR89{1'b0}};
VAR137 <= {(1+(VAR141)){1'b0}};
VAR74 <= {(1+(VAR141)){1'b0}};
VAR58 <= {VAR145{1'b0}};
VAR103 <= {(1+(VAR79-VAR104-1)){1'b0}};
VAR72 <= 1'h0;
VAR151 <= 1'h0;
VAR112 <= 1'h0;
VAR134 <= {VAR79{1'b0}};
VAR22 <= {VAR145{1'b0}};
VAR41 <= {VAR104{1'b0}};
VAR71 <= {VAR29{1'b0}};
VAR188 <= {VAR104{1'b0}};
VAR118 <= 1'h0;
VAR45 <= 1'h0;
VAR101 <= {VAR29{1'b0}};
VAR126 <= {(1+(VAR79-VAR104-1)){1'b0}};
VAR162 <= {VAR29{1'b0}};
VAR192 <= {(1+(VAR42)){1'b0}};
VAR63 <= {(1+(VAR108)){1'b0}};
VAR182 <= {VAR108{1'b0}};
VAR113 <= {(1+(VAR52)){1'b0}};
VAR34 <= {VAR52{1'b0}};
VAR196 <= {VAR104{1'b0}};
VAR152 <= {(1+(VAR89)){1'b0}};
VAR180 <= {VAR89{1'b0}};
VAR159 <= {VAR104{1'b0}};
VAR117 <= {VAR29{1'b0}};
VAR25 <= {VAR145{1'b0}};
end
else begin
VAR134 <= VAR139;
VAR22 <= VAR61;
VAR151 <= VAR102;
VAR112 <= VAR114;
VAR58 <= VAR130;
VAR178 <= VAR190;
VAR74 <= VAR97;
VAR127 <= VAR26;
VAR173 <= VAR98;
VAR62 <= VAR49;
VAR136 <= VAR44;
VAR183 <= VAR19;
VAR99 <= VAR181;
VAR92 <= VAR18;
VAR172 <= VAR85;
VAR51 <= VAR151;
VAR72 <= VAR112;
VAR103 <= VAR96;
VAR25 <= VAR69;
VAR137 <= VAR74;
VAR91 <= VAR127;
VAR132 <= VAR173;
VAR194 <= VAR62;
VAR36 <= VAR136;
VAR50 <= VAR183;
VAR2 <= VAR99;
VAR143 <= VAR92;
VAR150 <= VAR172;
VAR117 <= VAR195;
VAR159 <= VAR193;
VAR101 <= {VAR29{VAR51}} & VAR117;
VAR162 <= {VAR29{VAR72}} & VAR117;
VAR126 <= VAR103;
VAR196 <= VAR159;
VAR180 <= VAR91;
VAR34 <= VAR132;
VAR182 <= VAR194;
VAR152 <= VAR50;
VAR113 <= VAR2;
VAR63 <= VAR143;
VAR192 <= VAR150;
VAR35 <= VAR68 & VAR131 &
VAR75 & (~VAR71);
VAR188 <= VAR54;
VAR71 <= VAR77;
VAR118 <= VAR185;
VAR45 <= VAR118;
VAR41 <= VAR188;
end
end
always @ ( VAR178
or VAR58
or VAR151
or VAR112
or VAR134 or VAR22) begin : VAR94
reg [VAR104-1:0] VAR13;
VAR13 = 0;
VAR96 = 0;
VAR69 = 0;
VAR195 = 0;
if(VAR151) begin
VAR96 = VAR178[VAR79-
VAR104-1:0];
VAR13 = VAR178[VAR79-1:
VAR79-VAR104];
VAR69 = VAR58;
VAR195[VAR13] = 1'b1;
VAR193 = VAR13;
end
else if(VAR112) begin
VAR96 = VAR134[VAR79-
VAR104-1:0];
VAR13 = VAR134[VAR79-1:
VAR79-VAR104];
VAR69 = VAR22;
VAR195[VAR13] = 1'b1;
VAR193 = VAR13;
end
else begin
VAR96 = 0;
VAR69 = 0;
VAR195 = 0;
VAR193 = 0;
end
end
always @ ( VAR35 or VAR71) begin : VAR123
integer VAR106;
reg [VAR104-1:0] VAR158;
reg VAR179;
VAR77 = 0;
VAR54 = 0;
VAR185 = 1'b0;
VAR179 = 1'b0;
VAR158 = 0;
for (VAR106=0; VAR106<VAR29;
VAR106 = VAR106 + 1) begin
if(VAR35[VAR106] &
!VAR71[VAR106]) begin
if(!VAR179) begin
VAR158 = VAR106;
VAR179 = 1'b1;
end
end
end
VAR185 = VAR179;
if( VAR179 ) begin
VAR54 = VAR158;
VAR77[VAR158] = 1'b1;
end
end
endmodule
|
bsd-3-clause
|
alexforencich/xfcp
|
lib/eth/rtl/rgmii_phy_if.v
| 7,377 |
module MODULE1 #
(
parameter VAR52 = "VAR54",
parameter VAR13 = "VAR32",
parameter VAR3 = "VAR25",
parameter VAR36 = "VAR15"
)
(
input wire clk,
input wire VAR59,
input wire rst,
output wire VAR58,
output wire VAR37,
output wire [7:0] VAR57,
output wire VAR46,
output wire VAR10,
output wire VAR26,
output wire VAR56,
output wire VAR33,
input wire [7:0] VAR12,
input wire VAR31,
input wire VAR34,
input wire VAR41,
input wire [3:0] VAR39,
input wire VAR38,
output wire VAR27,
output wire [3:0] VAR5,
output wire VAR35,
input wire [1:0] VAR14
);
wire VAR22;
wire VAR9;
VAR43 #
(
.VAR52(VAR52),
.VAR3(VAR3),
.VAR13(VAR13),
.VAR6(5)
)
VAR2 (
.VAR49(VAR41),
.VAR44({VAR39, VAR38}),
.VAR28(VAR58),
.VAR4({VAR57[3:0], VAR22}),
.VAR21({VAR57[7:4], VAR9})
);
assign VAR46 = VAR22;
assign VAR10 = VAR22 ^ VAR9;
reg VAR1 = 1'b1;
reg VAR29 = 1'b0;
reg VAR19 = 1'b1;
reg VAR18 = 1'b1;
reg [5:0] VAR48 = 6'd0, VAR11;
always @(posedge clk) begin
if (rst) begin
VAR1 <= 1'b1;
VAR29 <= 1'b0;
VAR19 <= 1'b1;
VAR18 <= 1'b1;
VAR48 <= 0;
end else begin
VAR1 <= VAR29;
if (VAR14 == 2'b00) begin
VAR48 <= VAR48 + 1;
VAR19 <= 1'b0;
VAR18 <= 1'b0;
if (VAR48 == 24) begin
VAR1 <= 1'b1;
VAR29 <= 1'b1;
VAR19 <= 1'b1;
end else if (VAR48 >= 49) begin
VAR1 <= 1'b0;
VAR29 <= 1'b0;
VAR18 <= 1'b1;
VAR48 <= 0;
end
end else if (VAR14 == 2'b01) begin
VAR48 <= VAR48 + 1;
VAR19 <= 1'b0;
VAR18 <= 1'b0;
if (VAR48 == 2) begin
VAR1 <= 1'b1;
VAR29 <= 1'b1;
VAR19 <= 1'b1;
end else if (VAR48 >= 4) begin
VAR29 <= 1'b0;
VAR18 <= 1'b1;
VAR48 <= 0;
end
end else begin
VAR1 <= 1'b1;
VAR29 <= 1'b0;
VAR19 <= 1'b1;
VAR18 <= 1'b1;
end
end
end
reg [3:0] VAR16 = 0;
reg [3:0] VAR24 = 0;
reg VAR55 = 1'b0;
reg VAR42 = 1'b0;
reg VAR40 = 1'b1;
always @* begin
if (VAR14 == 2'b00) begin
VAR16 = VAR12[3:0];
VAR24 = VAR12[3:0];
if (VAR29) begin
VAR55 = VAR31;
VAR42 = VAR31;
end else begin
VAR55 = VAR31 ^ VAR34;
VAR42 = VAR31 ^ VAR34;
end
VAR40 = VAR18;
end else if (VAR14 == 2'b01) begin
VAR16 = VAR12[3:0];
VAR24 = VAR12[3:0];
if (VAR29) begin
VAR55 = VAR31;
VAR42 = VAR31;
end else begin
VAR55 = VAR31 ^ VAR34;
VAR42 = VAR31 ^ VAR34;
end
VAR40 = VAR18;
end else begin
VAR16 = VAR12[3:0];
VAR24 = VAR12[7:4];
VAR55 = VAR31;
VAR42 = VAR31 ^ VAR34;
VAR40 = 1;
end
end
wire VAR50;
wire [3:0] VAR8;
wire VAR20;
VAR51 #(
.VAR52(VAR52),
.VAR13(VAR13),
.VAR6(1)
)
VAR53 (
.clk(VAR36 == "VAR15" ? VAR59 : clk),
.VAR23(VAR1),
.VAR47(VAR29),
.VAR30(VAR27)
);
VAR51 #(
.VAR52(VAR52),
.VAR13(VAR13),
.VAR6(5)
)
VAR45 (
.clk(clk),
.VAR23({VAR16, VAR55}),
.VAR47({VAR24, VAR42}),
.VAR30({VAR5, VAR35})
);
assign VAR26 = clk;
assign VAR33 = VAR40;
reg [3:0] VAR7 = 4'hf;
assign VAR56 = VAR7[0];
always @(posedge VAR26 or posedge rst) begin
if (rst) begin
VAR7 <= 4'hf;
end else begin
VAR7 <= {1'b0, VAR7[3:1]};
end
end
reg [3:0] VAR17 = 4'hf;
assign VAR37 = VAR17[0];
always @(posedge VAR58 or posedge rst) begin
if (rst) begin
VAR17 <= 4'hf;
end else begin
VAR17 <= {1'b0, VAR17[3:1]};
end
end
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a21oi/sky130_fd_sc_ls__a21oi_1.v
| 2,261 |
module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR3 ,
VAR8,
VAR5,
VAR4 ,
VAR7
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR8;
input VAR5;
input VAR4 ;
input VAR7 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR9 ,
VAR1,
VAR6,
VAR3
);
output VAR9 ;
input VAR1;
input VAR6;
input VAR3;
supply1 VAR8;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR7 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hdll
|
cells/nor3/sky130_fd_sc_hdll__nor3.functional.pp.v
| 1,862 |
module MODULE1 (
VAR7 ,
VAR10 ,
VAR11 ,
VAR12 ,
VAR4,
VAR14,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR12 ;
input VAR4;
input VAR14;
input VAR9 ;
input VAR5 ;
wire VAR3 ;
wire VAR2;
nor VAR13 (VAR3 , VAR12, VAR10, VAR11 );
VAR8 VAR6 (VAR2, VAR3, VAR4, VAR14);
buf VAR1 (VAR7 , VAR2 );
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.behavioral.v
| 1,336 |
module MODULE1( VAR6, VAR4, VAR5, VAR1, VAR7 );
input VAR7, VAR1, VAR6, VAR5;
output VAR4;
VAR3 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7));
VAR3 VAR8(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7));
|
apache-2.0
|
YoelRP/PROYECTO
|
bin/enpoint/CRC5_D5.v
| 1,421 |
module MODULE1(
VAR3,
VAR6,
VAR4
);
output [4:0] VAR3;
input [4:0] VAR6;
input [4:0] VAR4;
reg [4:0] VAR5;
reg [4:0] VAR2;
reg [4:0] VAR1;
begin
VAR5 = VAR6;
VAR2 = VAR4;
VAR1[0] = VAR5[3] ^ VAR5[0] ^ VAR2[0] ^ VAR2[3];
VAR1[1] = VAR5[4] ^ VAR5[1] ^ VAR2[1] ^ VAR2[4];
VAR1[2] = VAR5[3] ^ VAR5[2] ^ VAR5[0] ^ VAR2[0] ^ VAR2[2] ^ VAR2[3];
VAR1[3] = VAR5[4] ^ VAR5[3] ^ VAR5[1] ^ VAR2[1] ^ VAR2[3] ^ VAR2[4];
VAR1[4] = VAR5[4] ^ VAR5[2] ^ VAR2[2] ^ VAR2[4];
VAR3 = VAR1;
end
endfunction
endmodule
|
gpl-3.0
|
Jafet95/proy_3_grupo_2_sem_1_2016
|
decodificador_cs_registros.v
| 1,962 |
module MODULE1(
input [1:0]VAR10,
output reg VAR4,
output reg VAR3,
output reg VAR1,
output reg VAR6,
output reg VAR9,
output reg VAR2,
output reg VAR5,
output reg VAR7,
output reg VAR8
);
always@*
begin
case(VAR10)
2'b00: begin
VAR4 = 1'b0;
VAR3= 1'b0;
VAR1= 1'b0;
VAR6= 1'b0;
VAR9= 1'b0;
VAR2= 1'b0;
VAR5= 1'b0;
VAR7= 1'b0;
VAR8= 1'b0;
end
2'b01: begin
VAR4 = 1'b1;
VAR3= 1'b1;
VAR1= 1'b1;
VAR6= 1'b0;
VAR9= 1'b0;
VAR2= 1'b0;
VAR5= 1'b0;
VAR7= 1'b0;
VAR8= 1'b0;
end
2'b10: begin
VAR4 = 1'b0;
VAR3= 1'b0;
VAR1= 1'b0;
VAR6= 1'b1;
VAR9= 1'b1;
VAR2= 1'b1;
VAR5= 1'b0;
VAR7= 1'b0;
VAR8= 1'b0;
end
2'b11:
begin
VAR4 = 1'b0;
VAR3= 1'b0;
VAR1= 1'b0;
VAR6= 1'b0;
VAR9= 1'b0;
VAR2= 1'b0;
VAR5= 1'b1;
VAR7= 1'b1;
VAR8= 1'b1;
end
default: begin
VAR4 = 1'b0;
VAR3= 1'b0;
VAR1= 1'b0;
VAR6= 1'b0;
VAR9= 1'b0;
VAR2= 1'b0;
VAR5= 1'b0;
VAR7= 1'b0;
VAR8= 1'b0;
end
endcase
end
endmodule
|
mit
|
trivoldus28/pulsarch-verilog
|
design/sys/iop/ccx/rtl/io_cpx_reqdata_ff.v
| 2,469 |
module MODULE1(
VAR12, VAR10, VAR1,
VAR9, VAR8, VAR11, VAR2, VAR13
);
output [VAR3-1:0] VAR12;
output [7:0] VAR10;
output VAR1;
input [VAR3-1:0] VAR9;
input [7:0] VAR8;
input VAR11;
input VAR2;
input VAR13;
VAR4 #(VAR3) VAR14(
.din (VAR9[VAR3-1:0]),
.VAR6 (VAR12[VAR3-1:0]),
.clk (VAR11),
.VAR13 (VAR13),
.VAR7 (VAR3'd0),
.VAR15 ());
VAR4 #(8) VAR5(
.din (VAR8[7:0]),
.VAR6 (VAR10[7:0]),
.clk (VAR11),
.VAR13 (VAR13),
.VAR7 (8'd0),
.VAR15 ());
endmodule
|
gpl-2.0
|
bettse/proxmark3
|
fpga/lo_read.v
| 2,881 |
module MODULE1(
input VAR17, input [7:0] VAR7, input VAR10,
output VAR5, output VAR3,
output VAR9, output VAR8, output VAR16, output VAR11,
input [7:0] VAR2, output VAR1,
output VAR15, output VAR13, output VAR6,
output VAR4,
input VAR14
);
reg [7:0] VAR12;
always @(posedge VAR17)
begin
if((VAR7 == 8'd7) && !VAR10)
VAR12 <= VAR2;
end
else begin
VAR12[7:1] <= VAR12[6:0];
VAR12[0] <= 1'b0;
end
end
assign VAR13 = VAR12[7] && !VAR10;
assign VAR6 = VAR17;
assign VAR15 = (VAR7[7:3] == 5'd1) && !VAR10;
assign VAR3 = 1'b0;
assign VAR9 = 1'b0;
assign VAR8 = 1'b0;
assign VAR16 = 1'b0;
assign VAR11 = 1'b0;
assign VAR5 = VAR14 & VAR10;
assign VAR1 = ~VAR10;
assign VAR4 = VAR1;
endmodule
|
gpl-2.0
|
aap/pdp6
|
verilog/core256k_x.v
| 10,213 |
module MODULE1(
input wire clk,
input wire reset,
input wire VAR155,
input wire VAR56,
input wire VAR97,
input wire VAR82,
input wire VAR45,
input wire VAR1,
input wire VAR96,
input wire [21:35] VAR62,
input wire [18:21] VAR125,
input wire VAR123,
input wire [0:35] VAR4,
output wire VAR54,
output wire VAR12,
output wire [0:35] VAR128,
input wire VAR159,
input wire VAR42,
input wire VAR27,
input wire VAR65,
input wire [21:35] VAR71,
input wire [18:21] VAR130,
input wire VAR66,
input wire [0:35] VAR78,
output wire VAR24,
output wire VAR107,
output wire [0:35] VAR169,
input wire VAR113,
input wire VAR36,
input wire VAR50,
input wire VAR76,
input wire [21:35] VAR129,
input wire [18:21] VAR88,
input wire VAR162,
input wire [0:35] VAR61,
output wire VAR134,
output wire VAR6,
output wire [0:35] VAR37,
input wire VAR135,
input wire VAR79,
input wire VAR106,
input wire VAR40,
input wire [21:35] VAR2,
input wire [18:21] VAR63,
input wire VAR109,
input wire [0:35] VAR137,
output wire VAR69,
output wire VAR132,
output wire [0:35] VAR23,
output wire [17:0] VAR122,
output reg VAR117,
output reg VAR167,
output wire [35:0] VAR49,
input wire [35:0] VAR29,
input wire VAR157
);
wire VAR25 = 0;
reg [18:35] VAR67;
reg VAR105, VAR164;
reg [0:35] VAR5;
wire VAR98 =
~VAR123 &
VAR45 &
VAR83;
wire VAR116 =
~VAR66 &
VAR42 &
VAR83;
wire VAR17 =
~VAR162 &
VAR36 &
VAR83;
wire VAR89 =
~VAR109 &
VAR79 &
VAR83;
wire [18:35] VAR139 = { VAR125[18:21], VAR62[22:35] };
wire [18:35] VAR55 = { VAR130[18:21], VAR71[22:35] };
wire [18:35] VAR20 = { VAR88[18:21], VAR129[22:35] };
wire [18:35] VAR38 = { VAR63[18:21], VAR2[22:35] };
wire [18:35] VAR118 =
{18{VAR70}}&VAR139 |
{18{VAR87}}&VAR55 |
{18{VAR16}}&VAR20 |
{18{VAR53}}&VAR38;
wire VAR136 =
VAR70&VAR1 |
VAR87&VAR27 |
VAR16&VAR50 |
VAR53&VAR106;
wire VAR114 =
VAR70&VAR96 |
VAR87&VAR65 |
VAR16&VAR76 |
VAR53&VAR40;
wire [0:35] VAR68 =
{36{VAR70}}&VAR4 |
{36{VAR87}}&VAR78 |
{36{VAR16}}&VAR61 |
{36{VAR53}}&VAR137;
VAR28 VAR102(clk, reset, VAR153&VAR70, VAR54);
VAR28 VAR60(clk, reset, VAR153&VAR87, VAR24);
VAR28 VAR173(clk, reset, VAR153&VAR16, VAR134);
VAR28 VAR140(clk, reset, VAR153&VAR53, VAR69);
assign VAR12 = VAR99&VAR70;
assign VAR107 = VAR99&VAR87;
assign VAR6 = VAR99&VAR16;
assign VAR132 = VAR99&VAR53;
assign VAR128 = VAR163 & {36{VAR3 & VAR70}};
assign VAR169 = VAR163 & {36{VAR3 & VAR87}};
assign VAR37 = VAR163 & {36{VAR3 & VAR16}};
assign VAR23 = VAR163 & {36{VAR3 & VAR53}};
wire VAR120 = VAR82 & VAR70 |
VAR159 & VAR87 |
VAR113 & VAR16 |
VAR135 & VAR53;
wire VAR133, VAR166, VAR103;
wire VAR43, VAR101, VAR160;
VAR31 VAR44(clk, reset, VAR155, VAR133);
VAR151 VAR52(clk, reset, VAR133, VAR166, VAR43);
VAR151 VAR9(clk, reset, VAR166, VAR103, VAR101);
VAR28 VAR73(clk, reset, VAR103, VAR160);
reg VAR58, VAR30, VAR149;
reg VAR51, VAR111;
reg VAR83, VAR32, VAR142, VAR144;
reg VAR48, VAR92, VAR34, VAR100;
reg VAR104;
wire VAR70 = VAR48;
wire VAR87 = VAR92;
wire VAR16 = VAR34;
wire VAR53 = VAR100;
wire VAR152, VAR153, VAR138, VAR91, VAR93;
wire VAR64, VAR13, VAR11, VAR85;
wire VAR74, VAR77;
wire VAR176, VAR57;
wire VAR80;
wire VAR35;
wire VAR143;
wire VAR21 = VAR48 | VAR92 | VAR34 | VAR100;
wire VAR110 = VAR74 & ~VAR21;
wire VAR90 = VAR74 & ~VAR25 & VAR21;
wire VAR115 = VAR153;
wire VAR59;
wire VAR14;
wire VAR171;
wire VAR174;
wire VAR99;
wire VAR22;
wire VAR81;
VAR28 VAR72(clk, reset,
(VAR98 | VAR116 | VAR17 | VAR89),
VAR152);
VAR28 VAR15(clk, reset, VAR80 | VAR160, VAR35);
VAR28 VAR10(clk, reset, VAR35 | VAR176, VAR13);
VAR28 VAR94(clk, reset, VAR35 | VAR57, VAR85);
VAR28 VAR175(clk, reset,
VAR35 | VAR93 & ~VAR164 | VAR81,
VAR143);
VAR28 VAR161(clk, reset, VAR51&VAR111, VAR153);
VAR28 VAR41(clk, reset, VAR153, VAR138);
VAR28 VAR124(clk, reset,
VAR153 | VAR171&VAR105&VAR164,
VAR59);
VAR28 VAR108(clk, reset, VAR77&VAR105, VAR174);
VAR28 VAR172(clk, reset, VAR3, VAR99);
VAR28 VAR19(clk, reset, VAR32&(VAR142 | ~VAR164), VAR93);
VAR28 VAR46(clk, reset, VAR142, VAR81);
VAR28 VAR84(clk, reset, VAR97, VAR80);
VAR146 VAR170(clk, reset, VAR85, VAR11);
VAR121 VAR126(clk, reset, VAR152, VAR74);
VAR146 VAR119(clk, reset, VAR138, VAR91);
VAR147 VAR148(clk, reset, VAR91, VAR14);
VAR121 VAR145(clk, reset, VAR156, VAR171);
VAR112 VAR127(clk, reset, VAR91, VAR77);
VAR95 VAR75(clk, reset, VAR93, VAR64);
VAR8 VAR168(clk, reset, VAR64, VAR176);
VAR147 VAR26(clk, reset, VAR176, VAR57);
VAR95 VAR165(clk, reset, VAR120, VAR22);
reg [0:35] VAR163; wire [17:0] VAR7 = VAR67[18:35];
assign VAR122 = VAR7;
assign VAR49 = VAR5;
reg VAR47, VAR150;
wire VAR3;
VAR28 VAR33(clk, reset, VAR47&VAR150, VAR3);
reg VAR39, VAR18;
wire VAR156;
VAR28 VAR154(clk, reset, VAR39&VAR18, VAR156);
reg VAR141, VAR131;
wire VAR86;
VAR28 VAR158(clk, reset, VAR141&VAR131, VAR86);
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR167 <= 0;
VAR117 <= 0;
VAR163 <= 0;
VAR47 <= 0;
VAR150 <= 0;
VAR39 <= 0;
VAR18 <= 0;
VAR141 <= 0;
VAR131 <= 0;
VAR104 <= 0;
VAR142 <= 0;
VAR32 <= 0;
end else begin
if(VAR117 & ~VAR157) begin
VAR117 <= 0;
VAR131 <= 1;
end
if(VAR167 & ~VAR157) begin
VAR167 <= 0;
VAR163 <= VAR29;
VAR150 <= 1;
end
if(VAR35)
VAR131 <= 1;
if(VAR143) begin
VAR48 <= 0;
VAR92 <= 0;
VAR34 <= 0;
VAR100 <= 0;
end
if(VAR98 | VAR116 | VAR17 | VAR89) begin
if(VAR98) begin
VAR48 <= 1;
VAR92 <= 0;
VAR34 <= 0;
VAR100 <= 0;
end else if(VAR116) begin
VAR48 <= 0;
VAR92 <= 1;
VAR34 <= 0;
VAR100 <= 0;
end else if(VAR17 & VAR89) begin
VAR48 <= 0;
VAR92 <= 0;
VAR34 <= VAR104;
VAR100 <= ~VAR104;
VAR104 <= ~VAR104;
end else if(VAR17) begin
VAR48 <= 0;
VAR92 <= 0;
VAR34 <= 1;
VAR100 <= 0;
end else if(VAR89) begin
VAR48 <= 0;
VAR92 <= 0;
VAR34 <= 0;
VAR100 <= 1;
end
end
if(VAR91) begin
if(VAR34)
VAR104 <= 0;
if(VAR100)
VAR104 <= 1;
end
if(VAR152 | VAR43)
VAR83 <= 0;
if(VAR13 | VAR110)
VAR83 <= 1;
if(VAR35 | VAR101)
VAR51 <= 0;
if(VAR90 | VAR152 & VAR25)
VAR51 <= 1;
if(VAR101)
VAR111 <= 0;
if(VAR86 & ~VAR144)
VAR111 <= 1;
if(VAR11)
VAR141 <= 1;
if(VAR153) begin
VAR32 <= 0;
VAR142 <= 0;
VAR144 <= 0;
end
if(VAR171)
VAR32 <= 1;
if(VAR22)
VAR142 <= 1;
if(VAR35)
VAR144 <= 0;
if(VAR91 & VAR56)
VAR144 <= 1;
if(VAR91) begin
VAR51 <= 0;
VAR111 <= 0;
end
if(VAR115) begin
VAR67 <= VAR118;
VAR105 <= VAR136;
VAR164 <= VAR114;
end
VAR5 <= VAR5 | VAR68;
if(VAR59)
VAR5 <= 0;
if(VAR174)
VAR47 <= 1;
if(VAR3) begin
VAR47 <= 0;
VAR150 <= 0;
VAR18 <= 1;
VAR5 <= VAR5 | VAR163;
end
if(VAR101 | VAR13) begin
VAR58 <= 0;
VAR30 <= 0;
VAR149 <= 0;
end
if(VAR138) begin
VAR58 <= 1;
VAR167 <= VAR105;
VAR150 <= 0;
VAR18 <= ~VAR105;
VAR30 <= 0;
end
if(VAR14) begin
VAR58 <= 0;
VAR39 <= 1;
end
if(VAR156) begin
VAR39 <= 0;
VAR18 <= 0;
end
if(VAR93) begin
VAR149 <= 1;
VAR117 <= VAR164;
VAR131 <= ~VAR164;
end
if(VAR64) begin
VAR30 <= 1;
VAR58 <= 0;
end
if(VAR86) begin
VAR141 <= 0;
VAR131 <= 0;
end
end
end
endmodule
|
mit
|
asicguy/gplgpu
|
hdl/math/real_log2_table.v
| 18,767 |
module MODULE1
(
input clk,
input VAR3,
input [8:0] VAR1,
output reg [8:0] VAR2
);
always @(posedge clk, negedge VAR3) begin
if(!VAR3) VAR2 <= 9'h0;
end
else begin
case(VAR1)
0: VAR2 <= 9'd0; 1: VAR2 <= 9'd0; 2: VAR2 <= 9'd32; 3: VAR2 <= 9'd50; 4: VAR2 <= 9'd64; 5: VAR2 <= 9'd74; 6: VAR2 <= 9'd82; 7: VAR2 <= 9'd89; 8: VAR2 <= 9'd96; 9: VAR2 <= 9'd101; 10: VAR2 <= 9'd106; 11: VAR2 <= 9'd110; 12: VAR2 <= 9'd114; 13: VAR2 <= 9'd118; 14: VAR2 <= 9'd121; 15: VAR2 <= 9'd125; 16: VAR2 <= 9'd128; 17: VAR2 <= 9'd130; 18: VAR2 <= 9'd133; 19: VAR2 <= 9'd135; 20: VAR2 <= 9'd138; 21: VAR2 <= 9'd140; 22: VAR2 <= 9'd142; 23: VAR2 <= 9'd144; 24: VAR2 <= 9'd146; 25: VAR2 <= 9'd148; 26: VAR2 <= 9'd150; 27: VAR2 <= 9'd152; 28: VAR2 <= 9'd153; 29: VAR2 <= 9'd155; 30: VAR2 <= 9'd157; 31: VAR2 <= 9'd158; 32: VAR2 <= 9'd160; 33: VAR2 <= 9'd161; 34: VAR2 <= 9'd162; 35: VAR2 <= 9'd164; 36: VAR2 <= 9'd165; 37: VAR2 <= 9'd166; 38: VAR2 <= 9'd167; 39: VAR2 <= 9'd169; 40: VAR2 <= 9'd170; 41: VAR2 <= 9'd171; 42: VAR2 <= 9'd172; 43: VAR2 <= 9'd173; 44: VAR2 <= 9'd174; 45: VAR2 <= 9'd175; 46: VAR2 <= 9'd176; 47: VAR2 <= 9'd177; 48: VAR2 <= 9'd178; 49: VAR2 <= 9'd179; 50: VAR2 <= 9'd180; 51: VAR2 <= 9'd181; 52: VAR2 <= 9'd182; 53: VAR2 <= 9'd183; 54: VAR2 <= 9'd184; 55: VAR2 <= 9'd185; 56: VAR2 <= 9'd185; 57: VAR2 <= 9'd186; 58: VAR2 <= 9'd187; 59: VAR2 <= 9'd188; 60: VAR2 <= 9'd189; 61: VAR2 <= 9'd189; 62: VAR2 <= 9'd190; 63: VAR2 <= 9'd191; 64: VAR2 <= 9'd192; 65: VAR2 <= 9'd192; 66: VAR2 <= 9'd193; 67: VAR2 <= 9'd194; 68: VAR2 <= 9'd194; 69: VAR2 <= 9'd195; 70: VAR2 <= 9'd196; 71: VAR2 <= 9'd196; 72: VAR2 <= 9'd197; 73: VAR2 <= 9'd198; 74: VAR2 <= 9'd198; 75: VAR2 <= 9'd199; 76: VAR2 <= 9'd199; 77: VAR2 <= 9'd200; 78: VAR2 <= 9'd201; 79: VAR2 <= 9'd201; 80: VAR2 <= 9'd202; 81: VAR2 <= 9'd202; 82: VAR2 <= 9'd203; 83: VAR2 <= 9'd204; 84: VAR2 <= 9'd204; 85: VAR2 <= 9'd205; 86: VAR2 <= 9'd205; 87: VAR2 <= 9'd206; 88: VAR2 <= 9'd206; 89: VAR2 <= 9'd207; 90: VAR2 <= 9'd207; 91: VAR2 <= 9'd208; 92: VAR2 <= 9'd208; 93: VAR2 <= 9'd209; 94: VAR2 <= 9'd209; 95: VAR2 <= 9'd210; 96: VAR2 <= 9'd210; 97: VAR2 <= 9'd211; 98: VAR2 <= 9'd211; 99: VAR2 <= 9'd212; 100: VAR2 <= 9'd212; 101: VAR2 <= 9'd213; 102: VAR2 <= 9'd213; 103: VAR2 <= 9'd213; 104: VAR2 <= 9'd214; 105: VAR2 <= 9'd214; 106: VAR2 <= 9'd215; 107: VAR2 <= 9'd215; 108: VAR2 <= 9'd216; 109: VAR2 <= 9'd216; 110: VAR2 <= 9'd217; 111: VAR2 <= 9'd217; 112: VAR2 <= 9'd217; 113: VAR2 <= 9'd218; 114: VAR2 <= 9'd218; 115: VAR2 <= 9'd219; 116: VAR2 <= 9'd219; 117: VAR2 <= 9'd219; 118: VAR2 <= 9'd220; 119: VAR2 <= 9'd220; 120: VAR2 <= 9'd221; 121: VAR2 <= 9'd221; 122: VAR2 <= 9'd221; 123: VAR2 <= 9'd222; 124: VAR2 <= 9'd222; 125: VAR2 <= 9'd222; 126: VAR2 <= 9'd223; 127: VAR2 <= 9'd223; 128: VAR2 <= 9'd224; 129: VAR2 <= 9'd224; 130: VAR2 <= 9'd224; 131: VAR2 <= 9'd225; 132: VAR2 <= 9'd225; 133: VAR2 <= 9'd225; 134: VAR2 <= 9'd226; 135: VAR2 <= 9'd226; 136: VAR2 <= 9'd226; 137: VAR2 <= 9'd227; 138: VAR2 <= 9'd227; 139: VAR2 <= 9'd227; 140: VAR2 <= 9'd228; 141: VAR2 <= 9'd228; 142: VAR2 <= 9'd228; 143: VAR2 <= 9'd229; 144: VAR2 <= 9'd229; 145: VAR2 <= 9'd229; 146: VAR2 <= 9'd230; 147: VAR2 <= 9'd230; 148: VAR2 <= 9'd230; 149: VAR2 <= 9'd231; 150: VAR2 <= 9'd231; 151: VAR2 <= 9'd231; 152: VAR2 <= 9'd231; 153: VAR2 <= 9'd232; 154: VAR2 <= 9'd232; 155: VAR2 <= 9'd232; 156: VAR2 <= 9'd233; 157: VAR2 <= 9'd233; 158: VAR2 <= 9'd233; 159: VAR2 <= 9'd234; 160: VAR2 <= 9'd234; 161: VAR2 <= 9'd234; 162: VAR2 <= 9'd234; 163: VAR2 <= 9'd235; 164: VAR2 <= 9'd235; 165: VAR2 <= 9'd235; 166: VAR2 <= 9'd236; 167: VAR2 <= 9'd236; 168: VAR2 <= 9'd236; 169: VAR2 <= 9'd236; 170: VAR2 <= 9'd237; 171: VAR2 <= 9'd237; 172: VAR2 <= 9'd237; 173: VAR2 <= 9'd237; 174: VAR2 <= 9'd238; 175: VAR2 <= 9'd238; 176: VAR2 <= 9'd238; 177: VAR2 <= 9'd238; 178: VAR2 <= 9'd239; 179: VAR2 <= 9'd239; 180: VAR2 <= 9'd239; 181: VAR2 <= 9'd239; 182: VAR2 <= 9'd240; 183: VAR2 <= 9'd240; 184: VAR2 <= 9'd240; 185: VAR2 <= 9'd241; 186: VAR2 <= 9'd241; 187: VAR2 <= 9'd241; 188: VAR2 <= 9'd241; 189: VAR2 <= 9'd241; 190: VAR2 <= 9'd242; 191: VAR2 <= 9'd242; 192: VAR2 <= 9'd242; 193: VAR2 <= 9'd242; 194: VAR2 <= 9'd243; 195: VAR2 <= 9'd243; 196: VAR2 <= 9'd243; 197: VAR2 <= 9'd243; 198: VAR2 <= 9'd244; 199: VAR2 <= 9'd244; 200: VAR2 <= 9'd244; 201: VAR2 <= 9'd244; 202: VAR2 <= 9'd245; 203: VAR2 <= 9'd245; 204: VAR2 <= 9'd245; 205: VAR2 <= 9'd245; 206: VAR2 <= 9'd245; 207: VAR2 <= 9'd246; 208: VAR2 <= 9'd246; 209: VAR2 <= 9'd246; 210: VAR2 <= 9'd246; 211: VAR2 <= 9'd247; 212: VAR2 <= 9'd247; 213: VAR2 <= 9'd247; 214: VAR2 <= 9'd247; 215: VAR2 <= 9'd247; 216: VAR2 <= 9'd248; 217: VAR2 <= 9'd248; 218: VAR2 <= 9'd248; 219: VAR2 <= 9'd248; 220: VAR2 <= 9'd249; 221: VAR2 <= 9'd249; 222: VAR2 <= 9'd249; 223: VAR2 <= 9'd249; 224: VAR2 <= 9'd249; 225: VAR2 <= 9'd250; 226: VAR2 <= 9'd250; 227: VAR2 <= 9'd250; 228: VAR2 <= 9'd250; 229: VAR2 <= 9'd250; 230: VAR2 <= 9'd251; 231: VAR2 <= 9'd251; 232: VAR2 <= 9'd251; 233: VAR2 <= 9'd251; 234: VAR2 <= 9'd251; 235: VAR2 <= 9'd252; 236: VAR2 <= 9'd252; 237: VAR2 <= 9'd252; 238: VAR2 <= 9'd252; 239: VAR2 <= 9'd252; 240: VAR2 <= 9'd253; 241: VAR2 <= 9'd253; 242: VAR2 <= 9'd253; 243: VAR2 <= 9'd253; 244: VAR2 <= 9'd253; 245: VAR2 <= 9'd253; 246: VAR2 <= 9'd254; 247: VAR2 <= 9'd254; 248: VAR2 <= 9'd254; 249: VAR2 <= 9'd254; 250: VAR2 <= 9'd254; 251: VAR2 <= 9'd255; 252: VAR2 <= 9'd255; 253: VAR2 <= 9'd255; 254: VAR2 <= 9'd255; 255: VAR2 <= 9'd255; 256: VAR2 <= 9'd256; 257: VAR2 <= 9'd256; 258: VAR2 <= 9'd256; 259: VAR2 <= 9'd256; 260: VAR2 <= 9'd256; 261: VAR2 <= 9'd256; 262: VAR2 <= 9'd257; 263: VAR2 <= 9'd257; 264: VAR2 <= 9'd257; 265: VAR2 <= 9'd257; 266: VAR2 <= 9'd257; 267: VAR2 <= 9'd257; 268: VAR2 <= 9'd258; 269: VAR2 <= 9'd258; 270: VAR2 <= 9'd258; 271: VAR2 <= 9'd258; 272: VAR2 <= 9'd258; 273: VAR2 <= 9'd258; 274: VAR2 <= 9'd259; 275: VAR2 <= 9'd259; 276: VAR2 <= 9'd259; 277: VAR2 <= 9'd259; 278: VAR2 <= 9'd259; 279: VAR2 <= 9'd259; 280: VAR2 <= 9'd260; 281: VAR2 <= 9'd260; 282: VAR2 <= 9'd260; 283: VAR2 <= 9'd260; 284: VAR2 <= 9'd260; 285: VAR2 <= 9'd260; 286: VAR2 <= 9'd261; 287: VAR2 <= 9'd261; 288: VAR2 <= 9'd261; 289: VAR2 <= 9'd261; 290: VAR2 <= 9'd261; 291: VAR2 <= 9'd261; 292: VAR2 <= 9'd262; 293: VAR2 <= 9'd262; 294: VAR2 <= 9'd262; 295: VAR2 <= 9'd262; 296: VAR2 <= 9'd262; 297: VAR2 <= 9'd262; 298: VAR2 <= 9'd263; 299: VAR2 <= 9'd263; 300: VAR2 <= 9'd263; 301: VAR2 <= 9'd263; 302: VAR2 <= 9'd263; 303: VAR2 <= 9'd263; 304: VAR2 <= 9'd263; 305: VAR2 <= 9'd264; 306: VAR2 <= 9'd264; 307: VAR2 <= 9'd264; 308: VAR2 <= 9'd264; 309: VAR2 <= 9'd264; 310: VAR2 <= 9'd264; 311: VAR2 <= 9'd264; 312: VAR2 <= 9'd265; 313: VAR2 <= 9'd265; 314: VAR2 <= 9'd265; 315: VAR2 <= 9'd265; 316: VAR2 <= 9'd265; 317: VAR2 <= 9'd265; 318: VAR2 <= 9'd266; 319: VAR2 <= 9'd266; 320: VAR2 <= 9'd266; 321: VAR2 <= 9'd266; 322: VAR2 <= 9'd266; 323: VAR2 <= 9'd266; 324: VAR2 <= 9'd266; 325: VAR2 <= 9'd267; 326: VAR2 <= 9'd267; 327: VAR2 <= 9'd267; 328: VAR2 <= 9'd267; 329: VAR2 <= 9'd267; 330: VAR2 <= 9'd267; 331: VAR2 <= 9'd267; 332: VAR2 <= 9'd268; 333: VAR2 <= 9'd268; 334: VAR2 <= 9'd268; 335: VAR2 <= 9'd268; 336: VAR2 <= 9'd268; 337: VAR2 <= 9'd268; 338: VAR2 <= 9'd268; 339: VAR2 <= 9'd268; 340: VAR2 <= 9'd269; 341: VAR2 <= 9'd269; 342: VAR2 <= 9'd269; 343: VAR2 <= 9'd269; 344: VAR2 <= 9'd269; 345: VAR2 <= 9'd269; 346: VAR2 <= 9'd269; 347: VAR2 <= 9'd270; 348: VAR2 <= 9'd270; 349: VAR2 <= 9'd270; 350: VAR2 <= 9'd270; 351: VAR2 <= 9'd270; 352: VAR2 <= 9'd270; 353: VAR2 <= 9'd270; 354: VAR2 <= 9'd270; 355: VAR2 <= 9'd271; 356: VAR2 <= 9'd271; 357: VAR2 <= 9'd271; 358: VAR2 <= 9'd271; 359: VAR2 <= 9'd271; 360: VAR2 <= 9'd271; 361: VAR2 <= 9'd271; 362: VAR2 <= 9'd271; 363: VAR2 <= 9'd272; 364: VAR2 <= 9'd272; 365: VAR2 <= 9'd272; 366: VAR2 <= 9'd272; 367: VAR2 <= 9'd272; 368: VAR2 <= 9'd272; 369: VAR2 <= 9'd272; 370: VAR2 <= 9'd273; 371: VAR2 <= 9'd273; 372: VAR2 <= 9'd273; 373: VAR2 <= 9'd273; 374: VAR2 <= 9'd273; 375: VAR2 <= 9'd273; 376: VAR2 <= 9'd273; 377: VAR2 <= 9'd273; 378: VAR2 <= 9'd273; 379: VAR2 <= 9'd274; 380: VAR2 <= 9'd274; 381: VAR2 <= 9'd274; 382: VAR2 <= 9'd274; 383: VAR2 <= 9'd274; 384: VAR2 <= 9'd274; 385: VAR2 <= 9'd274; 386: VAR2 <= 9'd274; 387: VAR2 <= 9'd275; 388: VAR2 <= 9'd275; 389: VAR2 <= 9'd275; 390: VAR2 <= 9'd275; 391: VAR2 <= 9'd275; 392: VAR2 <= 9'd275; 393: VAR2 <= 9'd275; 394: VAR2 <= 9'd275; 395: VAR2 <= 9'd276; 396: VAR2 <= 9'd276; 397: VAR2 <= 9'd276; 398: VAR2 <= 9'd276; 399: VAR2 <= 9'd276; 400: VAR2 <= 9'd276; 401: VAR2 <= 9'd276; 402: VAR2 <= 9'd276; 403: VAR2 <= 9'd276; 404: VAR2 <= 9'd277; 405: VAR2 <= 9'd277; 406: VAR2 <= 9'd277; 407: VAR2 <= 9'd277; 408: VAR2 <= 9'd277; 409: VAR2 <= 9'd277; 410: VAR2 <= 9'd277; 411: VAR2 <= 9'd277; 412: VAR2 <= 9'd277; 413: VAR2 <= 9'd278; 414: VAR2 <= 9'd278; 415: VAR2 <= 9'd278; 416: VAR2 <= 9'd278; 417: VAR2 <= 9'd278; 418: VAR2 <= 9'd278; 419: VAR2 <= 9'd278; 420: VAR2 <= 9'd278; 421: VAR2 <= 9'd278; 422: VAR2 <= 9'd279; 423: VAR2 <= 9'd279; 424: VAR2 <= 9'd279; 425: VAR2 <= 9'd279; 426: VAR2 <= 9'd279; 427: VAR2 <= 9'd279; 428: VAR2 <= 9'd279; 429: VAR2 <= 9'd279; 430: VAR2 <= 9'd279; 431: VAR2 <= 9'd280; 432: VAR2 <= 9'd280; 433: VAR2 <= 9'd280; 434: VAR2 <= 9'd280; 435: VAR2 <= 9'd280; 436: VAR2 <= 9'd280; 437: VAR2 <= 9'd280; 438: VAR2 <= 9'd280; 439: VAR2 <= 9'd280; 440: VAR2 <= 9'd281; 441: VAR2 <= 9'd281; 442: VAR2 <= 9'd281; 443: VAR2 <= 9'd281; 444: VAR2 <= 9'd281; 445: VAR2 <= 9'd281; 446: VAR2 <= 9'd281; 447: VAR2 <= 9'd281; 448: VAR2 <= 9'd281; 449: VAR2 <= 9'd281; 450: VAR2 <= 9'd282; 451: VAR2 <= 9'd282; 452: VAR2 <= 9'd282; 453: VAR2 <= 9'd282; 454: VAR2 <= 9'd282; 455: VAR2 <= 9'd282; 456: VAR2 <= 9'd282; 457: VAR2 <= 9'd282; 458: VAR2 <= 9'd282; 459: VAR2 <= 9'd282; 460: VAR2 <= 9'd283; 461: VAR2 <= 9'd283; 462: VAR2 <= 9'd283; 463: VAR2 <= 9'd283; 464: VAR2 <= 9'd283; 465: VAR2 <= 9'd283; 466: VAR2 <= 9'd283; 467: VAR2 <= 9'd283; 468: VAR2 <= 9'd283; 469: VAR2 <= 9'd283; 470: VAR2 <= 9'd284; 471: VAR2 <= 9'd284; 472: VAR2 <= 9'd284; 473: VAR2 <= 9'd284; 474: VAR2 <= 9'd284; 475: VAR2 <= 9'd284; 476: VAR2 <= 9'd284; 477: VAR2 <= 9'd284; 478: VAR2 <= 9'd284; 479: VAR2 <= 9'd284; 480: VAR2 <= 9'd285; 481: VAR2 <= 9'd285; 482: VAR2 <= 9'd285; 483: VAR2 <= 9'd285; 484: VAR2 <= 9'd285; 485: VAR2 <= 9'd285; 486: VAR2 <= 9'd285; 487: VAR2 <= 9'd285; 488: VAR2 <= 9'd285; 489: VAR2 <= 9'd285; 490: VAR2 <= 9'd285; 491: VAR2 <= 9'd286; 492: VAR2 <= 9'd286; 493: VAR2 <= 9'd286; 494: VAR2 <= 9'd286; 495: VAR2 <= 9'd286; 496: VAR2 <= 9'd286; 497: VAR2 <= 9'd286; 498: VAR2 <= 9'd286; 499: VAR2 <= 9'd286; 500: VAR2 <= 9'd286; 501: VAR2 <= 9'd286; 502: VAR2 <= 9'd287; 503: VAR2 <= 9'd287; 504: VAR2 <= 9'd287; 505: VAR2 <= 9'd287; 506: VAR2 <= 9'd287; 507: VAR2 <= 9'd287; 508: VAR2 <= 9'd287; 509: VAR2 <= 9'd287; 510: VAR2 <= 9'd287; 511: VAR2 <= 9'd287; endcase
end
end
endmodule
|
gpl-3.0
|
timtian090/Playground
|
UVM/UVMPlayground/Lab3/Lab3-Project/CLS_PWM_Interval_Timer.v
| 1,849 |
module MODULE1
parameter VAR2 = 50000000, parameter VAR4 = 1000 )
(
output reg VAR1,
input VAR3
);
begin
begin
begin
end
begin
|
mit
|
FAST-Switch/fast
|
projects/SDTS/example/hw-src/ddr2/alt_ddrx_encoder.v
| 2,057 |
module MODULE1 #
( parameter
VAR1 = 64,
VAR11 = 72
)
(
VAR12,
VAR6,
VAR9
);
input VAR12;
input [VAR1 - 1 : 0] VAR6;
output [VAR11 - 1 : 0] VAR9;
wire [VAR11 - 1 : 0] VAR9;
generate
if (VAR11 == 40)
begin
VAR8 VAR4
(
.VAR2 (VAR12),
.VAR7 (VAR6),
.VAR10 (VAR9 [VAR11 - 2 : 0])
);
assign VAR9 [VAR11 - 1] = 1'b0;
end
else if (VAR11 == 72)
begin
VAR3 VAR5
(
.VAR2 (VAR12),
.VAR7 (VAR6),
.VAR10 (VAR9)
);
end
endgenerate
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/o41ai/sky130_fd_sc_ms__o41ai_2.v
| 2,424 |
module MODULE2 (
VAR7 ,
VAR3 ,
VAR12 ,
VAR5 ,
VAR2 ,
VAR8 ,
VAR6,
VAR4,
VAR11 ,
VAR10
);
output VAR7 ;
input VAR3 ;
input VAR12 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR6;
input VAR4;
input VAR11 ;
input VAR10 ;
VAR1 VAR9 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10)
);
endmodule
module MODULE2 (
VAR7 ,
VAR3,
VAR12,
VAR5,
VAR2,
VAR8
);
output VAR7 ;
input VAR3;
input VAR12;
input VAR5;
input VAR2;
input VAR8;
supply1 VAR6;
supply0 VAR4;
supply1 VAR11 ;
supply0 VAR10 ;
VAR1 VAR9 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
|
cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.behavioral.pp.v
| 1,164 |
module MODULE1( VAR5, VAR6, VAR2, VAR1 );
input VAR5;
inout VAR2, VAR1;
output VAR6;
VAR4 VAR3(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1));
VAR4 VAR7(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1));
|
apache-2.0
|
efabless/openlane
|
designs/151/src/riscv_arbiter.v
| 1,414 |
module MODULE1
(
input clk,
input reset,
input VAR8,
output VAR3,
input [VAR5-1:0] VAR10,
output VAR2,
input VAR16,
output VAR18,
input VAR9,
input [VAR5-1:0] VAR4,
output VAR1,
output VAR17,
input VAR14,
output VAR7,
output [VAR5-1:0] VAR13,
output [VAR6-1:0] VAR11,
input VAR15,
input [VAR6-1:0] VAR12
);
assign VAR3 = VAR14;
assign VAR18 = VAR14 & ~VAR8;
assign VAR17 = VAR8 | VAR16;
assign VAR7
= VAR8 ? 1'b0
: VAR9;
assign VAR13
= VAR8 ? VAR10
: VAR4;
assign VAR11
= VAR8 ? 4'd0
: 4'd1;
assign VAR2 = VAR15 & (VAR12 == 4'd0);
assign VAR1 = VAR15 & (VAR12 == 4'd1);
endmodule
|
apache-2.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature_KOA/ecp/sqr.v
| 6,875 |
module MODULE1(VAR1, VAR2);
input wire [232:0] VAR1;
output wire [232:0] VAR2;
assign VAR2[0] = VAR1[0] ^ VAR1[196];
assign VAR2[1] = VAR1[117];
assign VAR2[2] = VAR1[1] ^ VAR1[197];
assign VAR2[3] = VAR1[118];
assign VAR2[4] = VAR1[2] ^ VAR1[198];
assign VAR2[5] = VAR1[119];
assign VAR2[6] = VAR1[3] ^ VAR1[199];
assign VAR2[7] = VAR1[120];
assign VAR2[8] = VAR1[4] ^ VAR1[200];
assign VAR2[9] = VAR1[121];
assign VAR2[10] = VAR1[5] ^ VAR1[201];
assign VAR2[11] = VAR1[122];
assign VAR2[12] = VAR1[6] ^ VAR1[202];
assign VAR2[13] = VAR1[123];
assign VAR2[14] = VAR1[7] ^ VAR1[203];
assign VAR2[15] = VAR1[124];
assign VAR2[16] = VAR1[8] ^ VAR1[204];
assign VAR2[17] = VAR1[125];
assign VAR2[18] = VAR1[9] ^ VAR1[205];
assign VAR2[19] = VAR1[126];
assign VAR2[20] = VAR1[10] ^ VAR1[206];
assign VAR2[21] = VAR1[127];
assign VAR2[22] = VAR1[11] ^ VAR1[207];
assign VAR2[23] = VAR1[128];
assign VAR2[24] = VAR1[12] ^ VAR1[208];
assign VAR2[25] = VAR1[129];
assign VAR2[26] = VAR1[13] ^ VAR1[209];
assign VAR2[27] = VAR1[130];
assign VAR2[28] = VAR1[14] ^ VAR1[210];
assign VAR2[29] = VAR1[131];
assign VAR2[30] = VAR1[15] ^ VAR1[211];
assign VAR2[31] = VAR1[132];
assign VAR2[32] = VAR1[16] ^ VAR1[212];
assign VAR2[33] = VAR1[133];
assign VAR2[34] = VAR1[17] ^ VAR1[213];
assign VAR2[35] = VAR1[134];
assign VAR2[36] = VAR1[18] ^ VAR1[214];
assign VAR2[37] = VAR1[135];
assign VAR2[38] = VAR1[19] ^ VAR1[215];
assign VAR2[39] = VAR1[136];
assign VAR2[40] = VAR1[20] ^ VAR1[216];
assign VAR2[41] = VAR1[137];
assign VAR2[42] = VAR1[21] ^ VAR1[217];
assign VAR2[43] = VAR1[138];
assign VAR2[44] = VAR1[22] ^ VAR1[218];
assign VAR2[45] = VAR1[139];
assign VAR2[46] = VAR1[23] ^ VAR1[219];
assign VAR2[47] = VAR1[140];
assign VAR2[48] = VAR1[24] ^ VAR1[220];
assign VAR2[49] = VAR1[141];
assign VAR2[50] = VAR1[25] ^ VAR1[221];
assign VAR2[51] = VAR1[142];
assign VAR2[52] = VAR1[26] ^ VAR1[222];
assign VAR2[53] = VAR1[143];
assign VAR2[54] = VAR1[27] ^ VAR1[223];
assign VAR2[55] = VAR1[144];
assign VAR2[56] = VAR1[28] ^ VAR1[224];
assign VAR2[57] = VAR1[145];
assign VAR2[58] = VAR1[29] ^ VAR1[225];
assign VAR2[59] = VAR1[146];
assign VAR2[60] = VAR1[30] ^ VAR1[226];
assign VAR2[61] = VAR1[147];
assign VAR2[62] = VAR1[31] ^ VAR1[227];
assign VAR2[63] = VAR1[148];
assign VAR2[64] = VAR1[32] ^ VAR1[228];
assign VAR2[65] = VAR1[149];
assign VAR2[66] = VAR1[33] ^ VAR1[229];
assign VAR2[67] = VAR1[150];
assign VAR2[68] = VAR1[34] ^ VAR1[230];
assign VAR2[69] = VAR1[151];
assign VAR2[70] = VAR1[35] ^ VAR1[231];
assign VAR2[71] = VAR1[152];
assign VAR2[72] = VAR1[36] ^ VAR1[232];
assign VAR2[73] = VAR1[153];
assign VAR2[74] = VAR1[37] ^ VAR1[196];
assign VAR2[75] = VAR1[117] ^ VAR1[154];
assign VAR2[76] = VAR1[38] ^ VAR1[197];
assign VAR2[77] = VAR1[118] ^ VAR1[155];
assign VAR2[78] = VAR1[39] ^ VAR1[198];
assign VAR2[79] = VAR1[119] ^ VAR1[156];
assign VAR2[80] = VAR1[40] ^ VAR1[199];
assign VAR2[81] = VAR1[120] ^ VAR1[157];
assign VAR2[82] = VAR1[41] ^ VAR1[200];
assign VAR2[83] = VAR1[121] ^ VAR1[158];
assign VAR2[84] = VAR1[42] ^ VAR1[201];
assign VAR2[85] = VAR1[122] ^ VAR1[159];
assign VAR2[86] = VAR1[43] ^ VAR1[202];
assign VAR2[87] = VAR1[123] ^ VAR1[160];
assign VAR2[88] = VAR1[44] ^ VAR1[203];
assign VAR2[89] = VAR1[124] ^ VAR1[161];
assign VAR2[90] = VAR1[45] ^ VAR1[204];
assign VAR2[91] = VAR1[125] ^ VAR1[162];
assign VAR2[92] = VAR1[46] ^ VAR1[205];
assign VAR2[93] = VAR1[126] ^ VAR1[163];
assign VAR2[94] = VAR1[47] ^ VAR1[206];
assign VAR2[95] = VAR1[127] ^ VAR1[164];
assign VAR2[96] = VAR1[48] ^ VAR1[207];
assign VAR2[97] = VAR1[128] ^ VAR1[165];
assign VAR2[98] = VAR1[49] ^ VAR1[208];
assign VAR2[99] = VAR1[129] ^ VAR1[166];
assign VAR2[100] = VAR1[50] ^ VAR1[209];
assign VAR2[101] = VAR1[130] ^ VAR1[167];
assign VAR2[102] = VAR1[51] ^ VAR1[210];
assign VAR2[103] = VAR1[131] ^ VAR1[168];
assign VAR2[104] = VAR1[52] ^ VAR1[211];
assign VAR2[105] = VAR1[132] ^ VAR1[169];
assign VAR2[106] = VAR1[53] ^ VAR1[212];
assign VAR2[107] = VAR1[133] ^ VAR1[170];
assign VAR2[108] = VAR1[54] ^ VAR1[213];
assign VAR2[109] = VAR1[134] ^ VAR1[171];
assign VAR2[110] = VAR1[55] ^ VAR1[214];
assign VAR2[111] = VAR1[135] ^ VAR1[172];
assign VAR2[112] = VAR1[56] ^ VAR1[215];
assign VAR2[113] = VAR1[136] ^ VAR1[173];
assign VAR2[114] = VAR1[57] ^ VAR1[216];
assign VAR2[115] = VAR1[137] ^ VAR1[174];
assign VAR2[116] = VAR1[58] ^ VAR1[217];
assign VAR2[117] = VAR1[138] ^ VAR1[175];
assign VAR2[118] = VAR1[59] ^ VAR1[218];
assign VAR2[119] = VAR1[139] ^ VAR1[176];
assign VAR2[120] = VAR1[60] ^ VAR1[219];
assign VAR2[121] = VAR1[140] ^ VAR1[177];
assign VAR2[122] = VAR1[61] ^ VAR1[220];
assign VAR2[123] = VAR1[141] ^ VAR1[178];
assign VAR2[124] = VAR1[62] ^ VAR1[221];
assign VAR2[125] = VAR1[142] ^ VAR1[179];
assign VAR2[126] = VAR1[63] ^ VAR1[222];
assign VAR2[127] = VAR1[143] ^ VAR1[180];
assign VAR2[128] = VAR1[64] ^ VAR1[223];
assign VAR2[129] = VAR1[144] ^ VAR1[181];
assign VAR2[130] = VAR1[65] ^ VAR1[224];
assign VAR2[131] = VAR1[145] ^ VAR1[182];
assign VAR2[132] = VAR1[66] ^ VAR1[225];
assign VAR2[133] = VAR1[146] ^ VAR1[183];
assign VAR2[134] = VAR1[67] ^ VAR1[226];
assign VAR2[135] = VAR1[147] ^ VAR1[184];
assign VAR2[136] = VAR1[68] ^ VAR1[227];
assign VAR2[137] = VAR1[148] ^ VAR1[185];
assign VAR2[138] = VAR1[69] ^ VAR1[228];
assign VAR2[139] = VAR1[149] ^ VAR1[186];
assign VAR2[140] = VAR1[70] ^ VAR1[229];
assign VAR2[141] = VAR1[150] ^ VAR1[187];
assign VAR2[142] = VAR1[71] ^ VAR1[230];
assign VAR2[143] = VAR1[151] ^ VAR1[188];
assign VAR2[144] = VAR1[72] ^ VAR1[231];
assign VAR2[145] = VAR1[152] ^ VAR1[189];
assign VAR2[146] = VAR1[73] ^ VAR1[232];
assign VAR2[147] = VAR1[153] ^ VAR1[190];
assign VAR2[148] = VAR1[74];
assign VAR2[149] = VAR1[154] ^ VAR1[191];
assign VAR2[150] = VAR1[75];
assign VAR2[151] = VAR1[155] ^ VAR1[192];
assign VAR2[152] = VAR1[76];
assign VAR2[153] = VAR1[156] ^ VAR1[193];
assign VAR2[154] = VAR1[77];
assign VAR2[155] = VAR1[157] ^ VAR1[194];
assign VAR2[156] = VAR1[78];
assign VAR2[157] = VAR1[158] ^ VAR1[195];
assign VAR2[158] = VAR1[79];
assign VAR2[159] = VAR1[159] ^ VAR1[196];
assign VAR2[160] = VAR1[80];
assign VAR2[161] = VAR1[160] ^ VAR1[197];
assign VAR2[162] = VAR1[81];
assign VAR2[163] = VAR1[161] ^ VAR1[198];
assign VAR2[164] = VAR1[82];
assign VAR2[165] = VAR1[162] ^ VAR1[199];
assign VAR2[166] = VAR1[83];
assign VAR2[167] = VAR1[163] ^ VAR1[200];
assign VAR2[168] = VAR1[84];
assign VAR2[169] = VAR1[164] ^ VAR1[201];
assign VAR2[170] = VAR1[85];
assign VAR2[171] = VAR1[165] ^ VAR1[202];
assign VAR2[172] = VAR1[86];
assign VAR2[173] = VAR1[166] ^ VAR1[203];
assign VAR2[174] = VAR1[87];
assign VAR2[175] = VAR1[167] ^ VAR1[204];
assign VAR2[176] = VAR1[88];
assign VAR2[177] = VAR1[168] ^ VAR1[205];
assign VAR2[178] = VAR1[89];
assign VAR2[179] = VAR1[169] ^ VAR1[206];
assign VAR2[180] = VAR1[90];
assign VAR2[181] = VAR1[170] ^ VAR1[207];
assign VAR2[182] = VAR1[91];
assign VAR2[183] = VAR1[171] ^ VAR1[208];
assign VAR2[184] = VAR1[92];
assign VAR2[185] = VAR1[172] ^ VAR1[209];
assign VAR2[186] = VAR1[93];
assign VAR2[187] = VAR1[173] ^ VAR1[210];
assign VAR2[188] = VAR1[94];
assign VAR2[189] = VAR1[174] ^ VAR1[211];
assign VAR2[190] = VAR1[95];
assign VAR2[191] = VAR1[175] ^ VAR1[212];
assign VAR2[192] = VAR1[96];
assign VAR2[193] = VAR1[176] ^ VAR1[213];
assign VAR2[194] = VAR1[97];
assign VAR2[195] = VAR1[177] ^ VAR1[214];
assign VAR2[196] = VAR1[98];
assign VAR2[197] = VAR1[178] ^ VAR1[215];
assign VAR2[198] = VAR1[99];
assign VAR2[199] = VAR1[179] ^ VAR1[216];
assign VAR2[200] = VAR1[100];
assign VAR2[201] = VAR1[180] ^ VAR1[217];
assign VAR2[202] = VAR1[101];
assign VAR2[203] = VAR1[181] ^ VAR1[218];
assign VAR2[204] = VAR1[102];
assign VAR2[205] = VAR1[182] ^ VAR1[219];
assign VAR2[206] = VAR1[103];
assign VAR2[207] = VAR1[183] ^ VAR1[220];
assign VAR2[208] = VAR1[104];
assign VAR2[209] = VAR1[184] ^ VAR1[221];
assign VAR2[210] = VAR1[105];
assign VAR2[211] = VAR1[185] ^ VAR1[222];
assign VAR2[212] = VAR1[106];
assign VAR2[213] = VAR1[186] ^ VAR1[223];
assign VAR2[214] = VAR1[107];
assign VAR2[215] = VAR1[187] ^ VAR1[224];
assign VAR2[216] = VAR1[108];
assign VAR2[217] = VAR1[188] ^ VAR1[225];
assign VAR2[218] = VAR1[109];
assign VAR2[219] = VAR1[189] ^ VAR1[226];
assign VAR2[220] = VAR1[110];
assign VAR2[221] = VAR1[190] ^ VAR1[227];
assign VAR2[222] = VAR1[111];
assign VAR2[223] = VAR1[191] ^ VAR1[228];
assign VAR2[224] = VAR1[112];
assign VAR2[225] = VAR1[192] ^ VAR1[229];
assign VAR2[226] = VAR1[113];
assign VAR2[227] = VAR1[193] ^ VAR1[230];
assign VAR2[228] = VAR1[114];
assign VAR2[229] = VAR1[194] ^ VAR1[231];
assign VAR2[230] = VAR1[115];
assign VAR2[231] = VAR1[195] ^ VAR1[232];
assign VAR2[232] = VAR1[116];
endmodule
|
gpl-3.0
|
sukinull/hls_stream
|
Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_OUTPUT_STREAM_if.v
| 11,190 |
module MODULE2 (
input wire VAR11,
input wire VAR38,
output wire VAR31,
input wire VAR57,
output wire [23:0] VAR65,
output wire [2:0] VAR28,
output wire [2:0] VAR15,
output wire [0:0] VAR29,
output wire [0:0] VAR82,
output wire [0:0] VAR18,
output wire [0:0] VAR49,
input wire [23:0] VAR7,
output wire VAR23,
input wire VAR10,
input wire [2:0] VAR76,
output wire VAR13,
input wire VAR46,
input wire [2:0] VAR66,
output wire VAR75,
input wire VAR36,
input wire [0:0] VAR1,
output wire VAR14,
input wire VAR44,
input wire [0:0] VAR53,
output wire VAR24,
input wire VAR51,
input wire [0:0] VAR60,
output wire VAR83,
input wire VAR68,
input wire [0:0] VAR17,
output wire VAR54,
input wire VAR81
);
wire [0:0] VAR22;
wire [0:0] VAR16;
wire [23:0] VAR37;
wire [0:0] VAR62;
wire [2:0] VAR73;
wire [0:0] VAR34;
wire [2:0] VAR4;
wire [0:0] VAR63;
wire [0:0] VAR85;
wire [0:0] VAR80;
wire [0:0] VAR5;
wire [0:0] VAR47;
wire [0:0] VAR19;
wire [0:0] VAR26;
wire [0:0] VAR79;
wire [0:0] VAR55;
wire [0:0] VAR61;
wire [0:0] VAR8;
wire [33:0] VAR25;
wire [0:0] VAR12;
wire [0:0] VAR72;
wire [33:0] VAR78;
MODULE3 #(
.VAR41 ( 34 )
) VAR48 (
.clk ( VAR11 ),
.reset ( VAR38 ),
.VAR25 ( VAR25 ),
.VAR61 ( VAR61 ),
.VAR8 ( VAR8 ),
.VAR78 ( VAR78 ),
.VAR12 ( VAR12 ),
.VAR72 ( VAR72 )
);
MODULE1 #(
.VAR64 ( 24 ),
.VAR84 ( 4 )
) VAR70 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR62 ),
.VAR52 ( VAR23 ),
.read ( VAR22 ),
.write ( VAR10 ),
.dout ( VAR37 ),
.din ( VAR7 )
);
MODULE1 #(
.VAR64 ( 3 ),
.VAR84 ( 4 )
) VAR32 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR34 ),
.VAR52 ( VAR13 ),
.read ( VAR22 ),
.write ( VAR46 ),
.dout ( VAR73 ),
.din ( VAR76 )
);
MODULE1 #(
.VAR64 ( 3 ),
.VAR84 ( 4 )
) VAR45 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR63 ),
.VAR52 ( VAR75 ),
.read ( VAR22 ),
.write ( VAR36 ),
.dout ( VAR4 ),
.din ( VAR66 )
);
MODULE1 #(
.VAR64 ( 1 ),
.VAR84 ( 4 )
) VAR3 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR80 ),
.VAR52 ( VAR14 ),
.read ( VAR22 ),
.write ( VAR44 ),
.dout ( VAR85 ),
.din ( VAR1 )
);
MODULE1 #(
.VAR64 ( 1 ),
.VAR84 ( 4 )
) VAR69 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR47 ),
.VAR52 ( VAR24 ),
.read ( VAR22 ),
.write ( VAR51 ),
.dout ( VAR5 ),
.din ( VAR53 )
);
MODULE1 #(
.VAR64 ( 1 ),
.VAR84 ( 4 )
) VAR71 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR26 ),
.VAR52 ( VAR83 ),
.read ( VAR22 ),
.write ( VAR68 ),
.dout ( VAR19 ),
.din ( VAR60 )
);
MODULE1 #(
.VAR64 ( 1 ),
.VAR84 ( 4 )
) VAR42 (
.clk ( VAR11 ),
.VAR74 ( ~VAR38 ),
.VAR59 ( VAR55 ),
.VAR52 ( VAR54 ),
.read ( VAR22 ),
.write ( VAR81 ),
.dout ( VAR79 ),
.din ( VAR17 )
);
assign VAR31 = VAR12;
assign VAR65 = VAR78[23:0];
assign VAR28 = VAR78[26:24];
assign VAR15 = VAR78[29:27];
assign VAR29 = VAR78[30:30];
assign VAR82 = VAR78[31:31];
assign VAR18 = VAR78[32:32];
assign VAR49 = VAR78[33:33];
assign VAR61 = VAR16;
assign VAR72 = VAR57;
assign VAR25 = {VAR79, VAR19, VAR5, VAR85, VAR4, VAR73, VAR37};
assign VAR22 = VAR16 & VAR8;
assign VAR16 = VAR62 & VAR34 & VAR63 & VAR80 & VAR47 & VAR26 & VAR55;
endmodule
module MODULE1
VAR64 = 8,
VAR84 = 4
)(
input wire clk,
input wire VAR74,
output wire VAR59,
output wire VAR52,
input wire read,
input wire write,
output wire [VAR64-1:0] dout,
input wire [VAR64-1:0] din
);
localparam
VAR21 = 1 << VAR84;
reg VAR43;
reg VAR2;
reg [VAR84-1:0] VAR39;
reg [VAR64-1:0] VAR67[0:VAR21-1];
assign VAR59 = ~VAR43;
assign VAR52 = ~VAR2;
assign dout = VAR67[VAR39];
always @(posedge clk or posedge VAR74) begin
if (VAR74)
VAR43 <= 1'b1;
end
else if (VAR43 & write & ~read)
VAR43 <= 1'b0;
else if (~VAR43 & ~write & read & (VAR39==1'b0))
VAR43 <= 1'b1;
end
always @(posedge clk or posedge VAR74) begin
if (VAR74)
VAR2 <= 1'b0;
end
else if (VAR2 & read & ~write)
VAR2 <= 1'b0;
else if (~VAR2 & ~read & write & (VAR39==VAR21-2'd2))
VAR2 <= 1'b1;
end
always @(posedge clk or posedge VAR74) begin
if (VAR74)
VAR39 <= {VAR84{1'b1}};
end
else if (~VAR43 & ~write & read)
VAR39 <= VAR39 - 1'b1;
else if (~VAR2 & ~read & write)
VAR39 <= VAR39 + 1'b1;
end
always @(posedge clk) begin
if (~VAR2 & write) VAR67[0] <= din;
end
genvar VAR20;
generate
for (VAR20 = 1; VAR20 < VAR21; VAR20 = VAR20 + 1) begin : VAR6
always @(posedge clk) begin
if (~VAR2 & write) VAR67[VAR20] <= VAR67[VAR20-1];
end
end
endgenerate
endmodule
module MODULE3
VAR41 = 8 ) (
input wire clk,
input wire reset,
input wire [VAR41-1:0] VAR25,
input wire VAR61,
output wire VAR8,
output wire [VAR41-1:0] VAR78,
output wire VAR12,
input wire VAR72
);
localparam [1:0]
VAR30 = 2'b10,
VAR50 = 2'b11,
VAR58 = 2'b01;
reg [VAR41-1:0] VAR27;
reg [VAR41-1:0] VAR56;
wire VAR35;
wire VAR77;
wire VAR33;
reg VAR9;
reg [1:0] state;
reg [1:0] VAR40;
assign VAR8 = VAR9;
assign VAR78 = VAR27;
assign VAR12 = state[0];
assign VAR35 = (state == VAR30 && VAR61) ||
(state == VAR50 && VAR61 && VAR72) ||
(state == VAR58 && VAR72);
assign VAR77 = VAR61 & VAR8;
assign VAR33 = (state == VAR58);
always @(posedge clk) begin
if (VAR35) begin
if (VAR33)
VAR27 <= VAR56;
end
else
VAR27 <= VAR25;
end
end
always @(posedge clk) begin
if (VAR77) VAR56 <= VAR25;
end
always @(posedge clk) begin
if (~reset)
VAR9 <= 1'b0;
end
else if (state == VAR30)
VAR9 <= 1'b1;
else if (state == VAR50 && VAR40 == VAR58)
VAR9 <= 1'b0;
else if (state == VAR58 && VAR40 == VAR50)
VAR9 <= 1'b1;
end
always @(posedge clk) begin
if (~reset)
state <= VAR30;
end
else
state <= VAR40;
end
always @(*) begin
case (state)
VAR30:
if (VAR61 & VAR8)
VAR40 = VAR50;
end
else
VAR40 = VAR30;
VAR50:
if (~VAR61 & VAR72)
VAR40 = VAR30;
else if (VAR61 & ~VAR72)
VAR40 = VAR58;
else
VAR40 = VAR50;
VAR58:
if (VAR72)
VAR40 = VAR50;
else
VAR40 = VAR58;
default:
VAR40 = VAR30;
endcase
end
endmodule
|
gpl-2.0
|
Jbag/frequency_divider
|
design/frequency_divider.v
| 1,324 |
module MODULE1(
input clk,
input VAR2,
output VAR1
);
parameter VAR7= 6;
reg VAR3;
reg [9:0] VAR4;
always @(posedge clk or negedge VAR2)
begin
if(!VAR2)
begin
VAR4 <= 10'd0;
VAR3 <= 1'd0;
end
else
begin
if(VAR7==2)
VAR3 <= ~VAR3;
end
else
if(VAR4 <= ((VAR7-1'd1)/2)- 1'd1)
begin
VAR4 <= VAR4 +1'd1;
VAR3 <= 1'd1;
end
else
if(VAR4 <= (VAR7-2'd2))
begin
VAR4 <= VAR4 +1'd1;
VAR3 <= 1'd0;
end
else
begin
VAR4 <= 10'd0;
VAR3 <= 1'd0;
end
end
end
reg VAR6;
reg [9:0] VAR5;
always @(negedge clk or negedge VAR2)
begin
if(!VAR2)
begin
VAR5 <= 10'd0;
VAR6 <= 1'd0;
end
else
begin
if(VAR7==2)
VAR6 <= ~VAR6;
end
else
if(VAR5 <= ((VAR7-1'd1)/2)- 1'd1)
begin
VAR5 <= VAR5 +1'd1;
VAR6 <= 1'd1;
end
else
if(VAR5 <= (VAR7-2'd2))
begin
VAR5 <= VAR5 +1'd1;
VAR6 <= 1'd0;
end
else
begin
VAR5 <= 10'd0;
VAR6 <= 1'd0;
end
end
end
assign VAR1 = VAR3 | VAR6;
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_ms
|
cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.behavioral.pp.v
| 1,237 |
module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule
|
apache-2.0
|
luebbers/reconos
|
support/refdesigns/10.1/xup/eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_c/hdl/verilog/rgb_bram.v
| 8,797 |
module MODULE1(
VAR28, VAR58, VAR33,
VAR31, VAR35,
VAR49, VAR23,
VAR51, VAR6, VAR34, VAR10,
VAR16,VAR46,VAR2,VAR45,VAR26,VAR11, VAR55,VAR24,VAR43,VAR15,VAR39,VAR14, VAR53,VAR44,VAR1,VAR12,VAR8,VAR56 );
input VAR28;
input VAR58;
input VAR33;
input VAR31;
input VAR35;
input VAR49;
input VAR23;
input [0:63] VAR51;
input [0:1] VAR34;
input VAR6;
input VAR10;
output VAR16,VAR46,VAR2,VAR45,VAR26,VAR11;
output VAR55,VAR24,VAR43,VAR15,VAR39,VAR14;
output VAR53,VAR44,VAR1,VAR12,VAR8,VAR56;
wire [0:1] VAR37,VAR54,VAR19,VAR30,VAR42,VAR50;
wire [5:0] VAR17;
wire [5:0] VAR36;
wire [5:0] VAR38;
reg VAR16,VAR46,VAR2,VAR45,VAR26,VAR11;
reg VAR55,VAR24,VAR43,VAR15,VAR39,VAR14;
reg VAR53,VAR44,VAR1,VAR12,VAR8,VAR56;
reg [0:9] VAR40;
reg [0:6] VAR21;
reg VAR59;
always @(posedge VAR58)
begin
if (VAR33 | ~VAR49) begin
VAR40 = 10'b0;
VAR59 = 1'b0;
end
else begin
if (VAR49 & VAR59 == 0) begin
if (VAR40 == 10'd639) begin
VAR40 = 10'b0;
VAR59 = 1'b1;
end
else begin
VAR40 = VAR40 + 1;
VAR59 = 1'b0;
end
end
end
end
always @(posedge VAR31)
begin
if (VAR35) begin
VAR21 = 7'b0;
end
else begin
if (VAR6) begin
if (VAR21 == 7'd79) begin
VAR21 = 7'b0;
end
else begin
VAR21 = VAR21 + 1;
end
end
end
end
VAR61 VAR22 (
.VAR27 (VAR40), .VAR3 (VAR58), .VAR57 (16'b0), .VAR25 (2'b0), .VAR7 ({VAR17, VAR36, VAR38[5:2]}), .VAR4 (VAR38[1:0]), .VAR29 (VAR49), .VAR5 (~VAR28 | VAR33 | ~VAR49), .VAR13 (1'b0), .VAR9 ({VAR21,VAR34}), .VAR18 (VAR31), .VAR41 ({VAR51[40:45], VAR51[48:53], VAR51[56:59],
VAR51[8:13], VAR51[16:21], VAR51[24:27]}), .VAR60 ({VAR51[60:61], VAR51[28:29]}), .VAR32 (), .VAR52 (), .VAR20 (VAR10), .VAR48 (1'b0), .VAR47 (VAR10) );
always @(posedge VAR58)
if (!VAR23)
begin
VAR16 = 1'b0;
VAR46 = 1'b0;
VAR2 = 1'b0;
VAR45 = 1'b0;
VAR26 = 1'b0;
VAR11 = 1'b0;
VAR55 = 1'b0;
VAR24 = 1'b0;
VAR43 = 1'b0;
VAR15 = 1'b0;
VAR39 = 1'b0;
VAR14 = 1'b0;
VAR53 = 1'b0;
VAR44 = 1'b0;
VAR1 = 1'b0;
VAR12 = 1'b0;
VAR8 = 1'b0;
VAR56 = 1'b0;
end
else
begin
VAR16 = VAR17[0];
VAR46 = VAR17[1];
VAR2 = VAR17[2];
VAR45 = VAR17[3];
VAR26 = VAR17[4];
VAR11 = VAR17[5];
VAR55 = VAR36[0];
VAR24 = VAR36[1];
VAR43 = VAR36[2];
VAR15 = VAR36[3];
VAR39 = VAR36[4];
VAR14 = VAR36[5];
VAR53 = VAR38[0];
VAR44 = VAR38[1];
VAR1 = VAR38[2];
VAR12 = VAR38[3];
VAR8 = VAR38[4];
VAR56 = VAR38[5];
end
endmodule
|
gpl-3.0
|
google/skywater-pdk-libs-sky130_fd_sc_lp
|
cells/clkbuf/sky130_fd_sc_lp__clkbuf.pp.blackbox.v
| 1,249 |
module MODULE1 (
VAR4 ,
VAR3 ,
VAR5,
VAR2,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR1 ;
endmodule
|
apache-2.0
|
cpulabs/mist1032isa
|
src/memory_pipe_arbiter.v
| 7,771 |
module MODULE1(
input wire VAR27,
input wire VAR65,
input wire VAR54,
output wire VAR11,
input wire [1:0] VAR46,
input wire [3:0] VAR66,
input wire VAR49,
input wire [13:0] VAR6,
input wire [1:0] VAR63,
input wire [2:0] VAR81,
input wire [31:0] VAR75,
input wire [31:0] VAR64,
input wire [31:0] VAR20,
output wire VAR31,
input wire VAR82,
output wire [63:0] VAR2,
output wire [23:0] VAR35,
input wire VAR3,
output wire VAR15,
input wire [1:0] VAR62,
input wire [2:0] VAR33,
input wire [31:0] VAR8,
input wire [13:0] VAR50,
input wire [31:0] VAR77,
output wire VAR21,
input wire VAR48,
output wire [63:0] VAR44,
output wire [23:0] VAR70,
output wire VAR34,
input wire VAR4,
output wire VAR29, output wire [1:0] VAR36,
output wire [2:0] VAR80,
output wire [31:0] VAR67,
output wire [13:0] VAR42,
output wire [1:0] VAR71,
output wire [3:0] VAR7,
output wire VAR22,
output wire [31:0] VAR13,
output wire [31:0] VAR32,
input wire VAR69,
output wire VAR23,
input wire VAR72,
input wire [63:0] VAR9,
input wire [23:0] VAR60
);
wire VAR1;
wire VAR79;
wire VAR38;
wire VAR43;
wire VAR68;
wire VAR41;
wire VAR76;
wire VAR45 = 1'b0;
reg VAR19;
reg VAR26;
reg [1:0] VAR16;
reg [3:0] VAR58;
reg VAR57;
reg [1:0] VAR56;
reg [2:0] VAR5;
reg [31:0] VAR55;
reg [13:0] VAR10;
reg [31:0] VAR12;
reg [31:0] VAR17;
reg VAR18;
reg [63:0] VAR83;
reg [23:0] VAR37;
reg VAR53;
reg [63:0] VAR25;
reg [23:0] VAR51;
wire VAR39 = VAR1 || VAR4;
wire VAR14 = VAR49 && VAR76;
wire VAR28 = (!VAR49 && VAR76) || VAR41;
VAR47 #(16, 4, 1) VAR73( .VAR27(VAR27),
.VAR65(VAR65),
.VAR61(1'b0),
.VAR30(!VAR39 && VAR28),
.VAR78(VAR76), .VAR24(VAR1),
.VAR52(VAR69 && (VAR38 && !VAR45 || !VAR38 && !VAR48) && !VAR72),
.VAR40(VAR79),
.VAR74(VAR38), .VAR59()
);
assign VAR43 = VAR39 || VAR76;
assign VAR68 = VAR39 || VAR41;
assign VAR41 = !VAR54 && VAR3;
assign VAR76 = VAR54;
always@(posedge VAR27 or negedge VAR65)begin
if(!VAR65)begin
VAR19 <= 1'b0;
VAR16 <= 2'h0;
VAR58 <= 4'h0;
VAR57 <= 1'b0;
VAR26 <= 1'b0;
VAR56 <= 2'h0;
VAR5 <= 3'h0;
VAR55 <= {32{1'b0}};
VAR10 <= 14'h0;
VAR12 <= {32{1'b0}};
VAR17 <= {32{1'b0}};
end
else begin
if(!VAR39)begin
if(VAR76)begin
VAR19 <= 1'b1;
VAR16 <= VAR46;
VAR58 <= VAR66;
VAR57 <= VAR49;
VAR26 <= VAR14;
VAR56 <= VAR63;
VAR5 <= VAR81;
VAR55 <= VAR75;
VAR10 <= VAR6;
VAR12 <= VAR64;
VAR17 <= VAR20;
end
else if(VAR41)begin
VAR19 <= 1'b1;
VAR16 <= 2'h2;
VAR58 <= 4'hf;
VAR57 <= 1'b0;
VAR26 <= 1'b0;
VAR56 <= VAR62;
VAR5 <= VAR33;
VAR55 <= VAR8;
VAR10 <= VAR50;
VAR12 <= VAR77;
VAR17 <= {32{1'b0}};
end
else begin
VAR19 <= 1'b0;
end
end
end
end
always@(posedge VAR27 or negedge VAR65)begin
if(!VAR65)begin
VAR18 <= 1'b0;
VAR83 <= {63{1'b0}};
VAR37 <= 24'h0;
end
else begin
if(!VAR48)begin
VAR18 <= !VAR38 && VAR79 && !VAR72 && VAR69;
VAR83 <= VAR9;
VAR37 <= VAR60;
end
end
end
assign VAR45 = 1'b0;
always@(posedge VAR27 or negedge VAR65)begin
if(!VAR65)begin
VAR53 <= 1'b0;
VAR25 <= {63{1'b0}};
VAR51 <= 24'h0;
end
else begin
if(!VAR45)begin
VAR53 <= ((VAR38 && VAR79) || VAR72) && VAR69;
VAR25 <= VAR9;
VAR51 <= VAR60;
end
end
end
assign VAR11 = VAR68;
assign VAR15 = VAR43;
assign VAR34 = VAR19;
assign VAR29 = VAR26;
assign VAR36 = VAR56;
assign VAR80 = VAR5;
assign VAR67 = VAR55;
assign VAR42 = VAR10;
assign VAR71 = VAR16;
assign VAR7 = VAR58;
assign VAR22 = VAR57;
assign VAR13 = VAR12;
assign VAR32 = VAR17;
assign VAR23 = VAR82 || VAR48;
assign VAR31 = VAR53 && !VAR45;
assign VAR2 = VAR25;
assign VAR35 = VAR51;
assign VAR21 = VAR18 && !VAR48;
assign VAR44 = VAR83;
assign VAR70 = VAR37;
endmodule
|
bsd-2-clause
|
google/skywater-pdk-libs-sky130_fd_sc_hs
|
cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v
| 2,177 |
module MODULE2 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR3,
VAR1 ,
VAR5
);
output VAR7 ;
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR1 ;
input VAR5 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR3
);
output VAR7 ;
output VAR4 ;
input VAR6 ;
input VAR3;
supply1 VAR1;
supply0 VAR5;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
|
apache-2.0
|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
|
cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.behavioral.v
| 1,116 |
module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1));
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hvl
|
cells/nor2/sky130_fd_sc_hvl__nor2.behavioral.pp.v
| 1,792 |
module MODULE1 (
VAR3 ,
VAR5 ,
VAR11 ,
VAR7,
VAR10,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR7;
input VAR10;
input VAR8 ;
input VAR6 ;
wire VAR1 ;
wire VAR9;
nor VAR4 (VAR1 , VAR5, VAR11 );
VAR12 VAR2 (VAR9, VAR1, VAR7, VAR10);
buf VAR13 (VAR3 , VAR9 );
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.v
| 2,262 |
module MODULE1 (
VAR2 ,
VAR4 ,
VAR10 ,
VAR8,
VAR6,
VAR9,
VAR5 ,
VAR3
);
output VAR2 ;
output VAR4 ;
input VAR10 ;
input VAR8;
input VAR6;
input VAR9;
input VAR5 ;
input VAR3 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR2 ,
VAR4 ,
VAR10 ,
VAR8
);
output VAR2 ;
output VAR4 ;
input VAR10 ;
input VAR8;
supply1 VAR6;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
|
apache-2.0
|
google/skywater-pdk-libs-sky130_fd_sc_hd
|
cells/a311oi/sky130_fd_sc_hd__a311oi.symbol.v
| 1,395 |
module MODULE1 (
input VAR10,
input VAR8,
input VAR5,
input VAR6,
input VAR4,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule
|
apache-2.0
|
Miltonhill/WaterbearCPU
|
waterbear.v
| 6,728 |
module MODULE1(
input clk,
input rst,
output[7:0] VAR5);
parameter VAR26=2'b00;
parameter VAR25=2'b01;
parameter VAR22=2'b10;
parameter VAR1=2'b11;
integer VAR6;
reg[1:0] VAR14;
reg[1:0] VAR15;
parameter VAR21 = 4'b001; parameter VAR24 = 4'b010; parameter VAR16 = 4'b011; parameter VAR19 = 4'b100; parameter VAR2 = 4'b101; parameter VAR20 = 4'b110; parameter VAR23 = 4'b111;
reg[15:0] VAR8[0:255]; reg[5:0] VAR9[0:127]; reg[5:0] VAR3[0:127]; reg[5:0] VAR18; reg[7:0] VAR5;
reg[7:0] VAR17; reg[15:0] VAR11; reg[15:0] VAR13;
reg[4:0] VAR7 = 5'b00000;
reg[3:0] VAR10 = 0;
reg VAR4 = 0;
reg[5:0] VAR12 = 0;
begin
begin
|
mit
|
EPiCS/soundgates
|
hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/cf_adc_wr.v
| 5,202 |
module MODULE1 (
VAR12,
VAR8,
VAR3,
VAR24,
VAR14,
VAR16,
VAR13,
VAR18,
VAR2,
VAR7,
VAR15,
VAR17,
VAR26,
VAR10,
VAR5,
VAR27,
VAR19,
VAR25,
VAR21,
VAR6);
parameter VAR23 = 0;
input VAR12;
input [13:0] VAR8;
input VAR3;
output VAR24;
output VAR14;
output [63:0] VAR16;
output VAR13;
output VAR18;
output VAR2;
input VAR7;
input VAR15;
input VAR17;
input [ 3:0] VAR26;
input [ 4:0] VAR10;
input VAR5;
output VAR27;
output [ 4:0] VAR19;
output VAR25;
output VAR21;
output [15:0] VAR6;
reg [ 1:0] VAR4 = 'd0;
reg VAR14 = 'd0;
reg [63:0] VAR16 = 'd0;
wire [13:0] VAR20;
assign VAR21 = 1'b1;
assign VAR6 = {2'd0, VAR20};
always @(posedge VAR24) begin
VAR4 <= VAR4 + 1'b1;
VAR14 <= VAR4[0] & VAR4[1];
VAR16 <= {2'd0, VAR20, VAR16[63:16]};
end
VAR22 VAR1 (
.VAR24 (VAR24),
.VAR16 (VAR20),
.VAR18 (VAR18),
.VAR2 (VAR2),
.VAR7 (VAR7));
VAR11 #(.VAR23 (VAR23)) VAR9 (
.VAR12 (VAR12),
.VAR8 (VAR8),
.VAR3 (VAR3),
.VAR24 (VAR24),
.VAR16 (VAR20),
.VAR13 (VAR13),
.VAR15 (VAR15),
.VAR17 (VAR17),
.VAR26 (VAR26),
.VAR10 (VAR10),
.VAR5 (VAR5),
.VAR27 (VAR27),
.VAR19 (VAR19),
.VAR25 (VAR25));
endmodule
|
mit
|
google/skywater-pdk-libs-sky130_fd_sc_ls
|
cells/a32o/sky130_fd_sc_ls__a32o.functional.v
| 1,580 |
module MODULE1 (
VAR8 ,
VAR7,
VAR2,
VAR13,
VAR11,
VAR3
);
output VAR8 ;
input VAR7;
input VAR2;
input VAR13;
input VAR11;
input VAR3;
wire VAR10 ;
wire VAR5 ;
wire VAR4;
and VAR9 (VAR10 , VAR13, VAR7, VAR2 );
and VAR1 (VAR5 , VAR11, VAR3 );
or VAR6 (VAR4, VAR5, VAR10);
buf VAR12 (VAR8 , VAR4 );
endmodule
|
apache-2.0
|
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