rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-pymtl-chisel-truncate Text Generation • 8B • Updated May 29 • 8
rtl-llm/qwen2.5coder-7b-origen-vhdl-pymtl-chisel-truncate-interleave Text Generation • 8B • Updated May 29 • 5
rtl-llm/qwen2.5coder-7b-origen-chisel-vhdl-verilog-truncate-interleave Text Generation • 8B • Updated May 29 • 6
rtl-llm/qwen2.5coder-7b-translate-vhdl-pymtl-chisel-truncate-interleave Text Generation • 8B • Updated May 29 • 6
rtl-llm/qwen2.5coder-7b-origen-chisel-pymtl-vhdl-verilog-truncate-interleave Text Generation • 8B • Updated May 29 • 6
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-constantlr Text Generation • 8B • Updated May 29 • 5
rtl-llm/qwen2.5coder-7b-translate-vhdl-pymtl-chisel-cleaned Text Generation • 8B • Updated May 29 • 5