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#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int b) { long long int res = 1; while (b) { if (b % 2 == 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b /= 2; } return res; } bool comp(long long int a, long long int b) { return a < b; } long long int binary(long long int *a, long long int l, long long int r, long long int key) { long long int mid; while (l <= r) { mid = (l + r) / 2; if (a[mid] == key) { return mid; } else if (a[mid] < key) { l = mid + 1; } else { r = mid - 1; } } return -1; } bool isprime(long long int n) { if (n <= 1) { return false; } int i; for (i = 2; i <= ceil(sqrt((double)n)); i++) { if (n % i == 0) { return false; } } return true; } bool isPalindrome(long long int n) { long long int rev = 0, temp = n, rem; while (temp) { rem = temp % 10; rev = rev * 10 + rem; temp /= 10; } if (n == rev) return true; return false; } long long int mulmod(long long int a, long long int b, long long int m) { long long int res = 0; a = a % m; while (b > 0) { if (b % 2 == 1) { res = (res + a) % m; } a = (a * 2) % m; b /= 2; } return (res % m); } bool isLeapYear(int year) { if (year % 400 == 0) return true; if (year % 100 == 0) return false; if (year % 4 == 0) return true; return false; } int ones(long long int n) { int ans = 0; while (n) { ans++; n &= (n - 1); } return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t, pro = 1, n, m, temp, k, i, l, r, mid, j, x, y, z, ind, mx = LONG_LONG_MIN, mn = LONG_LONG_MAX, ans = 0, cnt = 0, curr = 0, prev, sum = 0, flag = 0, i1 = -1, i2 = -1; cin >> n; long long int a[n]; for (i = 0; i <= n - 1; i++) { cin >> a[i]; mn = min(mn, a[i]); } vector<long long int> v; for (i = 0; i <= n - 1; i++) { if (a[i] == mn) { v.push_back(i); } } ans = LONG_LONG_MAX; for (i = 0; i <= v.size() - 2; i++) { ans = min(ans, v[i + 1] - v[i]); } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; const int N = 2020; struct trie { trie *c[26]; int cnt; } * root, *nil; string s1, s2, s3; int n, l, r, f[N][N], ans; trie *new_node() { trie *node = new (trie); for (int i = 0; i < 26; i++) node->c[i] = nil; node->cnt = 0; return node; } void deleteTree(trie *root) { for (int i = 0; i < 26; i++) if (root->c[i] != nil) { deleteTree(root->c[i]); delete (root->c[i]); } } int main() { getline(cin, s1); scanf( %d n , &n); nil = new (trie); root = new_node(); for (int i = 1; i <= n; i++) { deleteTree(root); for (int t = 0; t < 26; t++) root->c[t] = nil; cin >> s2 >> l >> r; for (int u = 0; u < s2.size(); u++) { trie *path = root; for (int v = u; v < s2.size(); v++) { int q = s2[v] - a ; if (path->c[q] == nil) { trie *nw = new_node(); path->c[q] = nw; } path = path->c[q]; path->cnt++; } } for (int u = 0; u < s1.size(); u++) { trie *path = root; for (int v = u; v < s1.size(); v++) { int q = s1[v] - a ; if (path->c[q] == nil) { if (l == 0) for (int t = v; t < s1.size(); t++) f[u][t]++; break; } path = path->c[q]; if (path->cnt >= l && path->cnt <= r) f[u][v]++; } } } deleteTree(root); for (int t = 0; t < 26; t++) root->c[t] = nil; for (int i = 0; i < s1.size(); i++) { trie *path = root; for (int j = i; j < s1.size(); j++) { int q = s1[j] - a ; if (path->c[q] == nil) { trie *nw = new_node(); path->c[q] = nw; } path = path->c[q]; if (f[i][j] == n && path->cnt == 0) ans++; path->cnt++; } } cout << ans << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_8_V
`define SKY130_FD_SC_HDLL__CLKBUF_8_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_8_V
|
module convolution_core (
input clk,
input reset,
input [31:0] value0,
input [31:0] value1,
input [31:0] value2,
input [31:0] value3,
input [31:0] value4,
input [31:0] value5,
input [31:0] value6,
input [31:0] value7,
input [31:0] value8,
input caculating_start,
output caculating_done,
input res_done,
output [31:0] ret
);
parameter kernel0 = 8'd1;
parameter kernel1 = 8'd2;
parameter kernel2 = 8'd3;
parameter kernel3 = 8'd4;
parameter kernel4 = 8'd5;
parameter kernel5 = 8'd6;
parameter kernel6 = 8'd7;
parameter kernel7 = 8'd8;
parameter kernel8 = 8'd9;
reg [31:0] Add0,Add1,Add2,Add3,Add4,Add5,Add6,Add7,Add8;
reg status;
reg [31:0] Dout;
assign ret = Dout;
reg reg_caculating_done;
assign caculating_done = reg_caculating_done;
always @(posedge clk) begin
if (reset) begin
status <= 1'b0;
end else if (status == 1'b0 && caculating_start) begin
Add0 <= value0 * kernel0;
Add1 <= value1 * kernel1;
Add2 <= value2 * kernel2;
Add3 <= value3 * kernel3;
Add4 <= value4 * kernel4;
Add5 <= value5 * kernel5;
Add6 <= value6 * kernel6;
Add7 <= value7 * kernel7;
Add8 <= value8 * kernel8;
status <= 1'b1;
end else if (status == 1'b1 && caculating_start) begin
Dout <= Add0+Add1+Add2+Add3+Add4+Add5+Add6+Add7+Add8;
status <= 1'b0;
reg_caculating_done <= 1'b1;
end else if (res_done) begin
reg_caculating_done <= 1'b0;
end
end
endmodule
|
module BarrelShifterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Rs,Rm,IR;
reg SR29_IN;
wire SR29_OUT;
wire [31:0] Out;
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SR29_IN,SR29_OUT,Out);
initial fork
Rs=0;Rm=0;IR=0;SR29_IN=0;
#1 Rs=1;#1 Rm=2;#1 IR[4]=1;#1 SR29_IN=0;
#2 Rs=1;#2 Rm=4; #2 SR29_IN=0;
#3 Rs=1;#3 Rm=8; #3 SR29_IN=0;
#4 Rs=8;#4 Rm=1; #4 SR29_IN=0;
#10 Rs=1;#10 Rm=2;#10 IR[6:5]=1;#10 SR29_IN=0;
#11 Rs=1;#11 Rm=4; #11 SR29_IN=0;
#12 Rs=1;#12 Rm=8; #12 SR29_IN=0;
#13 Rs=8;#13 Rm=1; #13 SR29_IN=0;
#20 Rs=1;#20 Rm=2;#20 IR[6:5]=2;#20 SR29_IN=0;
#21 Rs=1;#21 Rm=4; #21 SR29_IN=0;
#22 Rs=1;#22 Rm=8; #22 SR29_IN=0;
#23 Rs=8;#23 Rm=1; #23 SR29_IN=0;
#24 Rs=8;#24 Rm=32'hF0000001; #24 SR29_IN=0;
#30 Rs=1;#30 Rm=2;#30 IR[6:5]=3;#30 SR29_IN=0;
#31 Rs=1;#31 Rm=4; #31 SR29_IN=0;
#32 Rs=1;#32 Rm=8; #32 SR29_IN=0;
#33 Rs=8;#33 Rm=1; #33 SR29_IN=0;
#34 Rs=8;#34 Rm=32'hF0000001; #34 SR29_IN=0;
#40 IR[11:8]=0;#40 IR[7:0]=0;#40 IR[27:25]=1;#40 IR[4]=0;#40 SR29_IN=0;
#41 IR[11:8]=8;#41 IR[7:0] =1 ; #41 SR29_IN=0;
#50 Rs=0;#50 Rm=0;#50 IR[27:25]=3'b101;#50 SR29_IN=0;
join
initial #sim_time $finish;
initial begin
$dumpfile("BarrelShifterTestBench.vcd");
$dumpvars(0,BarrelShifterTestBench);
$display(" Test Results" );
$monitor("Rs=%8h,Rm=%8h,IR=%8h,Out=%8h,SR29_IN=%1b,SR29_OUT=%1b",Rs,Rm,IR,Out,SR29_IN,SR29_OUT);
end
endmodule
//iverilog BarrelShifter.v BarrelShifterTestBench.v
//reference 1 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CIHDDCIF.html
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 17:17:23 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/fir_lp_54kHz/fir_lp_54kHz_stub.v
// Design : fir_lp_54kHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_lp_54kHz(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[95:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [31:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [95:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> int c[100]; int main() { int n, s, max = 0, i, j; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &s); c[s] += 1; if (s > max) max = s; } for (i = 0; i <= max; i++) for (j = 0; j < c[i]; j++) printf( %d , i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = (int)1e9; const double PI = 2 * acos(0.0); const double eps = 1e-9; int main() { int a, b, c, d; cin >> a >> b >> c >> d; int foo = max(3 * a / 10, a - a / 250 * c); int bar = max(3 * b / 10, b - b / 250 * d); if (foo == bar) cout << Tie << endl; else if (foo > bar) cout << Misha << endl; else cout << Vasya << endl; return 0; }
|
// Full Adder rtl
module full_adder (a0, b0, c0, a1, b1, c_out, s_out, s2, s3);
// Inputs_top
input a0;
input b0;
input c0;
// End of inputs_top
// Outputs_top
output s1;
output c_out;
output s_out;
// End of outputs_top
// Wires
wire c1;
wire c2;
wire s1;
wire d1;
wire c3;
// Some assignments
assign carry_out = c1 | c2;
assign s_out = s1;
//assign d_out = d1;
// Instantiating two half-adders to make the circuit.
// Module instantiation
half_adder u1_half_adder (
// Inputs
.in_x(a0),
.in_y(b0),
// End of inputs
// Outputs
.out_sum(s0),
.out_carry(c1)
// End of outputs
);
// Module instantiation
half_adder u2_half_adder (
// Inputs
.in_x(s0),
.in_y(c0),
// End of inputs
// Outputs
.out_sum(s1),
.out_carry(c2)
// End of outputs
);
// Module instantiation
// Module instantiation
test2 test2 (
// Inputs
.in_1(d1),
.in_2(c3),
.in_3(b1),
// End of inputs
// Outputs
.out_1(s3)
// End of outputs
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char c; int n, b = 0, a = 0; cin >> n; while (n > 0) { cin >> c; if (c == A ) a++; else b++; n--; } if (a > b) cout << Anton ; else if (a < b) cout << Danik ; else cout << Friendship ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int ans[6]; cout << ? 1 2 << n ; cout.flush(); double a; cin >> a; cout << ? 2 3 << n ; cout.flush(); double b; cin >> b; map<double, bool> have; have[4] = 1; have[8] = 1; have[15] = 1; have[16] = 1; have[23] = 1; have[42] = 1; double arr[6] = {4, 8, 15, 16, 23, 42}; for (int i = 0; i < 6; i++) { if ((have[a / arr[i]] && a / arr[i] != arr[i]) && (have[b / arr[i]] && b / arr[i] != arr[i])) { ans[1] = arr[i]; ans[0] = a / arr[i]; ans[2] = b / arr[i]; break; } } cout << ? 4 5 << n ; cout.flush(); double c; cin >> c; cout << ? 5 6 << n ; cout.flush(); double d; cin >> d; for (int i = 0; i < 6; i++) { if ((have[c / arr[i]] && c / arr[i] != arr[i]) && (have[d / arr[i]] && d / arr[i] != arr[i])) { ans[4] = arr[i]; ans[3] = c / arr[i]; ans[5] = d / arr[i]; break; } } cout << ! ; for (int i = 0; i < 6; i++) { cout << ans[i] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; string s; int main() { long long n, x, y, br = 0, k = 0; cin >> n >> x >> y; cin >> s; for (long i = 0; i < n; i++) { if (s[i] == 0 ) { if (i == 0) { br++; } else if (s[i - 1] != 0 ) { br++; } } } long long sol = min(br * y, (br - 1) * x + y); if (sol < 0) { sol = br * y; } cout << sol << endl; }
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#include <bits/stdc++.h> using namespace std; char str[100010]; int f[100010][26 + 2], pre[100010][26], suf[100010][26], g[100010], n; int ans[26 + 2]; int dfs(int l, int r, int c, int fl) { if (l > r) return 0; if (ans[c] != -1) return ans[c]; int u = 0; for (int i = 0; i < 26; i++) { int L = suf[l][i], R = pre[r][i]; if (R < l) continue; int s = g[L] ^ g[R]; if (!fl) s ^= f[L - 1][c] ^ dfs(R + 1, r, i, 0); else s ^= dfs(l, L - 1, i, 1) ^ f[r][i]; u |= 1 << s; } return ans[c] = __builtin_ctz(~u); } int main() { scanf( %s , str + 1); n = strlen(str + 1); for (int i = 1; i <= n; i++) { for (int j = 0; j < 26; j++) pre[i][j] = pre[i - 1][j]; pre[i][str[i] - a ] = i; } for (int i = 0; i < 26; i++) suf[n + 1][i] = n + 1; for (int i = n; i >= 1; i--) { for (int j = 0; j < 26; j++) suf[i][j] = suf[i + 1][j]; suf[i][str[i] - a ] = i; } for (int i = 1; i <= n; i++) { int c = str[i] - a ; g[i] = f[i - 1][c] ^ g[pre[i - 1][c]]; memset(ans, -1, sizeof(ans)); for (int j = 0; j < 26; j++) f[i][j] = dfs(pre[i][j] + 1, i, j, 0); } int m; scanf( %d , &m); while (m-- > 0) { int l, r; scanf( %d%d , &l, &r); memset(ans, -1, sizeof(ans)); if (dfs(l, r, 26, 1)) puts( Alice ); else puts( Bob ); } }
|
// ----------------------------
// This module contains the evenzeroes design
// that will output a 1 when the design receives an
// even number of 0 input bits. Otherwise, a 0 is
// outputted from the design.
//
// Note:
// - Syntax works and compiles with Verilog2LPN compiler
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module evenzeroes_imp(bit0, bit1, parity0, parity1);
input bit0, bit1;
output reg parity0, parity1;
reg state;
initial begin
parity0 = 1'b0;
parity1 = 1'b0;
state = 1'b0;
end
always begin
wait (bit0 == 1'b1 || bit1 == 1'b1) #5;
if ((state != 1'b1 && bit1 == 1'b1) || (state == 1'b1 && bit0 == 1'b1)) begin
#5 parity1 = 1'b1;
end else begin //state is 1
#5 parity0 = 1'b1;
end
if (parity1 == 1'b1) begin
state = 1'b0;
end else begin
state = 1'b1;
end
wait ((parity0 == 1'b1 && state == 1'b1) || (parity1 == 1'b1 && state != 1'b1)) #5;
wait (bit0 != 1'b1 && bit1 != 1'b1) #5; //reset
if (parity0 == 1'b1) begin
#5 parity0 = 1'b0;
end else begin
#5 parity1 = 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct LCT { int ch[555555][2], f[555555], tag[555555], key[555555], sum[555555], st[555555], ls[555555], rs[555555]; LCT() { for (int i = 1; i <= 550000; i++) { sum[i] = ch[i][0] = ch[i][1] = f[i] = tag[i] = key[i] = 0; } } bool isrt(int x) { if (!f[x]) return 1; return (ch[f[x]][0] != x && ch[f[x]][1] != x); } int get(int x) { return (ch[f[x]][1] == x); } void pushup(int x) { sum[x] = key[x]; sum[x] += sum[ch[x][0]]; sum[x] += sum[ch[x][1]]; } void push(int x) { tag[x] ^= 1; swap(ch[x][0], ch[x][1]); } void pushdown(int x) { if (tag[x]) { push(ch[x][0]); push(ch[x][1]); tag[x] = 0; } } void rotate(int x) { int fa = f[x], gfa = f[fa]; int wh = get(x); ch[fa][wh] = ch[x][wh ^ 1]; f[ch[x][wh ^ 1]] = fa; ch[x][wh ^ 1] = fa; if (!isrt(fa)) ch[gfa][ch[gfa][1] == fa] = x; f[fa] = x; f[x] = gfa; pushup(fa); } void splay(int x) { int y = x, z = 0; st[++z] = y; while (!isrt(y)) { y = f[y]; st[++z] = y; } while (z) pushdown(st[z--]); for (int fa; (fa = f[x]) && !isrt(x); rotate(x)) { if (!isrt(fa)) { if (get(fa) == get(x)) rotate(fa); else rotate(x); } } pushup(x); } void access(int x) { for (int y = 0; x; y = x, x = f[x]) { splay(x); ch[x][1] = y; pushup(x); } } void makeroot(int x) { access(x); splay(x); push(x); } int findroot(int x) { access(x); splay(x); int pos = x; while (ch[pos][0]) { pushdown(pos); pos = ch[pos][0]; } splay(pos); return pos; } void split(int x, int y) { makeroot(x); access(y); splay(x); } void link(int x, int y) { makeroot(x); if (findroot(y) != x) f[x] = y; } void cut(int x, int y) { makeroot(x); if (findroot(y) != x || f[y] != x || ch[y][0]) return; ch[x][1] = 0; f[y] = 0; pushup(x); } } lct; int n, pa[333333], x, y, deg[333333]; vector<int> g[333333]; queue<int> q; void dfs(int i, int fa) { pa[i] = fa; for (int j = 0; j < g[i].size(); j++) { int to = g[i][j]; if (to == fa) continue; dfs(to, i); } } int find(int x) { int pos = x; while (pos) { lct.pushdown(pos); if (!lct.ch[pos][0] || !lct.sum[lct.ch[pos][0]]) { if (lct.key[pos]) return pos; pos = lct.ch[pos][1]; } else pos = lct.ch[pos][0]; } return pos; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); lct.key[n + i] = 1; lct.ls[n + i] = x; lct.rs[n + i] = y; lct.link(x, n + i); lct.link(y, n + i); } printf( %d n , n - 1); dfs(1, 0); for (int i = 2; i <= n; i++) deg[pa[i]]++; for (int i = 1; i <= n; i++) { if (!deg[i]) q.push(i); } for (int i = 1; i < n; i++) { x = q.front(); q.pop(); lct.split(x, pa[x]); y = find(x); printf( %d %d %d %d n , x, pa[x], lct.ls[y], lct.rs[y]); lct.cut(y, lct.ls[y]); lct.cut(y, lct.rs[y]); lct.ls[y] = x; lct.rs[y] = pa[x]; lct.link(y, lct.ls[y]); lct.link(y, lct.rs[y]); lct.splay(y); lct.key[y] = 0; lct.pushup(y); if (!--deg[pa[x]]) q.push(pa[x]); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire buf0_out_Q ;
wire not1_out_qn;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q , buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
not not1 (not1_out_qn, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (Q_N , not1_out_qn, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_FUNCTIONAL_PP_V
|
module peripheral_pwm (
input clk,
input rst,
input [15:0] d_in,
input cs,
input [3:0]addr, // 4 LSB from j1_io_addr
input rd,
input wr,
output [2:0] pwm ,
output reg [2:0] d_out
);
//------------------------------------ regs and wires-------------------------------
reg [5:0] s; //selector mux_4 and write registers
reg rst_n = 0;
reg [9:0] number_1;
reg [9:0] number_2;
reg [9:0] number_3; //mult_32 output Regs
//------------------------------------ regs and wires-------------------------------
always @(*) begin//------address_decoder------------------------------
case (addr)
4'h0: begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end //rst_n
4'h2: begin s = (cs && wr) ? 5'b00010 : 5'b00000 ;end //number_1
4'h4: begin s = (cs && wr) ? 5'b00100 : 5'b00000 ;end //number_2
4'h6: begin s = (cs && wr) ? 5'b01000 : 5'b00000 ;end //number_3
4'h8: begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end //pwm
default:begin s = 5'b00000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin // escritura de registros
rst_n <= ~s[0] ; // (s[2]) ? d_in : init; // Write Registers
number_1 <= (s[1]) ? d_in [9:0] : number_1 ; // Write Registers
number_2 <= (s[2]) ? d_in [9:0] : number_2 ; // Write Registers
number_3 <= (s[3]) ? d_in [9:0] : number_3 ; // Write Registers
end // escritura de registros
always @(negedge clk) begin // mux_4 : multiplexa salidas del periferico
if ( s[4] )
d_out <= pwm ;
end // mux_4
pwm pwm1 ( .clk(clk), .rst_n(rst_n), .number(number_1), pwm(pwm [0]) );
pwm pwm2 ( .clk(clk), .rst_n(rst_n), .number(number_2), pwm(pwm [1]) );
pwm pwm3 ( .clk(clk), .rst_n(rst_n), .number(number_3), pwm(pwm [2]) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 405; double f[maxn], g[maxn], ans; int n, m, dis[maxn][maxn], q[maxn]; int main() { scanf( %d%d , &n, &m); memset(dis, 127 / 3, sizeof(dis)); for (int i = 1; i <= n; i++) { dis[i][i] = 0; } for (int i = 1; i <= m; i++) { int u, v; scanf( %d%d , &u, &v); dis[u][v] = dis[v][u] = 1; } for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dis[i][j] = min(dis[i][j], dis[i][k] + dis[k][j]); } } } for (int i = 1; i <= n; i++) { double temp = 0; for (int j = 0; j < n; j++) { int u = 0; memset(f, 0, sizeof(f)); for (int k = 1; k <= n; k++) { if (dis[i][k] == j) { u++; int x = 0; for (int kk = 1; kk <= n; kk++) { if (dis[k][kk] == 1) { x++; } } for (int kk = 1; kk <= n; kk++) { if (dis[k][kk] == 1) { f[kk] += 1.0 / x; } } } } int v = 0; for (int k = 1; k <= n; k++) { if (abs(dis[i][k] - j) <= 1) { q[++v] = k; } } double res = 0; for (int k = 1; k <= n; k++) { for (int kk = 1; kk <= v; kk++) { if (f[q[kk]] > g[dis[k][q[kk]]]) { g[dis[k][q[kk]]] = f[q[kk]]; } } double w = 0; for (int kk = 1; kk <= v; kk++) { w += g[dis[k][q[kk]]]; g[dis[k][q[kk]]] = 0; } res = max(res, w); } if (u) { res = max(res, 1.0); } temp += res / n; } ans = max(ans, temp); } printf( %.12lf n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( O3 ) using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n, x; cin >> n >> x; string s; cin >> s; int a[100001] = {0}; int b[100001] = {0}; int f = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == 0 ) { a[i + 1] = a[i] + 1; b[i + 1] = b[i]; } else { a[i + 1] = a[i]; b[i + 1] = b[i] + 1; } } long long ans = 0; int c0 = 1; for (int i = 1; i <= n; i++) { if (a[i] - b[i] == 0) { c0++; } int g = a[i] - b[i]; long double h; h = (x - g); h *= 1.0; if (a[n] - b[n] == 0) { if (g == x) ans++; continue; } h /= (long double)(a[n] - b[n]); if (h < 0) continue; if (ceil(h) == floor(h)) { ans++; } } if (a[n] - b[n] == 0) { for (int i = 1; i <= n; i++) if (a[i] - b[i] == x) { cout << -1 << n ; f = 1; break; } } if (x == 0) ans++; if (f) continue; cout << ans << n ; } }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : pcie_soft_int.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
//--
//-- Description: PCIe Interrupt Module Wrapper for Softcore CMM32 Interrupt
//-- module
//--
//--
//--
//------------------------------------------------------------------------------
`timescale 1ns/1ns
`ifndef Tcq
`define Tcq 1
`endif
module pcie_soft_cf_int
(
// Clock and reset
input wire clk,
input wire rst_n,
input wire cs_is_intr,
input wire grant,
input wire [31:0] cfg_msguaddr,
// PCIe Block Interrupt Ports
input wire msi_enable,
output [3:0] msi_request,
output wire legacy_int_request,
// LocalLink Interrupt Ports
input wire cfg_interrupt_n,
output wire cfg_interrupt_rdy_n,
// NEWINTERRUPT signals
input wire msi_8bit_en,
input wire cfg_interrupt_assert_n,
input wire [7:0] cfg_interrupt_di,
output [2:0] cfg_interrupt_mmenable,
output [7:0] cfg_interrupt_do,
output cfg_interrupt_msienable,
input wire [31:0] msi_laddr,
input wire [31:0] msi_haddr,
input wire [15:0] cfg_command,
input wire [15:0] cfg_msgctrl,
input wire [15:0] cfg_msgdata,
// To Arb
output wire signaledint,
output wire intr_req_valid,
output wire [1:0] intr_req_type,
output wire [7:0] intr_vector
);
wire intr_rdy;
assign cfg_interrupt_rdy_n = ~intr_rdy;
assign cfg_interrupt_msienable = cfg_msgctrl[0]; // adr 0x48
assign legacy_int_request = 0; // tied low to disable in block
// legacy will be generated manually
assign msi_request = 4'd0; // tied low per ug197
assign cfg_interrupt_mmenable = cfg_msgctrl[6:4]; // MSI Cap Structure
assign cfg_interrupt_do = cfg_msgdata[7:0]; // MSI Message Data
// Interrupt controller from softcore
cmm_intr u_cmm_intr (
.clk (clk)
,.rst (~rst_n)
,.signaledint (signaledint) // O
,.intr_req_valid (intr_req_valid) // O
,.intr_req_type (intr_req_type) // O [1:0]
,.intr_rdy (intr_rdy) // O
,.cfg_interrupt_n (cfg_interrupt_n) // I [7:0]
,.cfg_interrupt_assert_n (cfg_interrupt_assert_n) // I
,.cfg_interrupt_di (cfg_interrupt_di) // I [7:0]
,.cfg_interrupt_mmenable (cfg_interrupt_mmenable) // I [2:0]
//,.cfg_interrupt_mmenable (3'b0) // I [2:0]
,.msi_data (cfg_msgdata) // I[15:0]
,.intr_vector (intr_vector) // O [7:0]
,.cfg ( {556'd0, msi_8bit_en ,467'd0} ) // I[1023:0]
,.command (cfg_command) // I [15:0]
,.msi_control (cfg_msgctrl) // I [15:0]
,.msi_laddr (msi_laddr) // I [31:0]
,.msi_haddr (msi_haddr) // I [31:0]
//,.intr_grant (grant) // I
,.intr_grant (grant & cs_is_intr) // I
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)3e3 + 5; const int INF = (int)1e9; const string T = aeiou ; int dp[MAXN], par[MAXN]; bool space[MAXN]; bool vowel[256]; string s; int n; bool bad(char a, char b, char c) { if (a == b && b == c) { return 0; } if (!vowel[a] && !vowel[b] && !vowel[c]) { return 1; } return 0; } void solve() { cin >> s; n = s.size(); s = # + s; for (char c : T) { vowel[c] = 1; } for (int i = 1; i <= n; ++i) { dp[i] = INF; } for (int l = 1; l <= n; ++l) { bool good = 1; for (int r = l; r <= n; ++r) { if (r - 2 >= l && bad(s[r - 2], s[r - 1], s[r])) { good = 0; break; } if (dp[l - 1] + 1 < dp[r]) { dp[r] = dp[l - 1] + 1; par[r] = l - 1; } } } for (int v = n; v > 0; v = par[v]) { space[v] = 1; } for (int i = 1; i <= n; ++i) { printf( %c , s[i]); if (space[i]) { printf( ); } } } int main() { int tt = 1; while (tt--) { solve(); } return 0; }
|
// date:2016/3/15
//engineer: zhaishaomin
// module function: output inst_word according to coming pc ,
// if missed , it will stall the pipeline and gen a msg to find the requested cache block
// including the origal inst_word
module inst_cache (//input
clk,
rst,
// from pc
v_pc,
pc,
//from ic_download
inst_4word,
v_inst_4word,
//output
// to local mem or OUT_req upload
v_ic_req,
local_or_OUT, //1:local ,0:OUT_req
req_msg,
v_inst,
inst
);
//input
input clk;
input rst;
// from pc
input v_pc;
input [31:0] pc;
//from ic_download
input [127:0] inst_4word;
input v_inst_4word;
//output
// to local mem or OUT_req upload
output v_ic_req;
output local_or_OUT; //1:local ,0:OUT_req
output [47:0] req_msg;
output v_inst;
output [31:0] inst;
/////////////////////////////////////////////////////////////////////
////////////////inst cache data and tag//////////////////////////////
reg tag_we;
reg tag_re;
reg data_we;
reg data_re;
reg [5:0] state_tag_in;
wire [5:0] state_tag_out;
reg [31:0] seled_addr;
reg [127:0]data_write;
wire [127:0]data_read;
reg [31:0] inst1;
reg [31:0] inst2;
reg v_inst;
reg local_or_OUT;
reg [47:0] req_msg;
reg inst1_inst2;
reg v_ic_req;
SP_BRAM_SRd #(32,6,5) tag_ram(.clk(clk), .we(tag_we), .re(tag_re), .a(seled_addr[8:4]), .di(state_tag_in), .dout(state_tag_out));
SP_BRAM_SRd #(32,128,5) data_ram(.clk(clk), .we(data_we), .re(data_re), .a(seled_addr[8:4]), .di(data_write), .dout(data_read));
/////////////////////////////////////////////////////////////////////
/////////////////inst cache fsm//////////////////////////////////////
//paramter
parameter inst_idle=2'b00;
parameter inst_comp_tag=2'b01;
parameter inst_gen_req=2'b10;
parameter inst_wait_rep=2'b11;
parameter local_id=2'b00;
parameter instreq_cmd=5'b00110;
reg [1:0] inst_cstate;
reg [1:0] inst_nstate;
always@(posedge clk)
begin
if(rst)
inst_cstate<=2'b00;
else
inst_cstate<=inst_nstate;
end
//fsm always block
always@(*)
begin
//default values
v_inst=1'b0;
v_ic_req=1'b0;
tag_we=1'b0;
tag_re=1'b0;
data_we=1'b0;
data_re=1'b0;
state_tag_in=5'b00000;
seled_addr=32'h0000;
data_write=128'h0000;
local_or_OUT=1'b0;
req_msg=48'h0000;
inst_nstate=inst_cstate;
inst1 = data_read[31:0];
inst2 = inst_4word[31:0];
inst1_inst2=1'b0;
/////////////////////////////////////////////////
/*read out correct word(32-bit) from cache (to if_id)*/
case(pc[3:2])
2'b00:inst1 = data_read[31:0];
2'b01:inst1 = data_read[63:32];
2'b10:inst1 = data_read[95:64];
2'b11:inst1 = data_read[127:96];
endcase
/////////////////////////////////////////////////
/* read inst_word directly from inst_4word (to if_id) */
case(pc[3:2])
2'b00:inst2 = inst_4word[31:0];
2'b01:inst2 = inst_4word[63:32];
2'b10:inst2 = inst_4word[95:64];
2'b11:inst2 = inst_4word[127:96];
endcase
case(inst_cstate)
inst_idle:
begin
if(v_pc)
inst_nstate=inst_comp_tag;
end
inst_comp_tag:
begin
tag_re=1'b1;
data_re=1'b1;
if(pc[12:9]==state_tag_out[3:0])
// tag equals
begin // [5:4] 00 inv, 01 wait inst rep , 10 valid
if(state_tag_out[5:4]==2'b10)//read hit
begin
//gen read hit ctrl signals
v_inst=1'b1;
inst1_inst2=1'b0;
inst_nstate=inst_idle;
end
/* else if(state_tag_out[5:4]==2'b01) // state is inv ,so read miss
// NOTE:the core only allow one outstanding cache access,
// so there won't be a case that cpu aceesses see apending state!
begin
if(pc[12:11]==local_id)
begin
req_local_remote=1'b0;
end // local 0 ;remote 1; default :remote ?
nstate=inst_gen_req;
// oneORmore=1'b0;
end */
end
else// tag miss
begin
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b01,pc[12:9]};
inst_nstate=inst_gen_req;
end
end
inst_gen_req:
begin
if(pc[12:11]==local_id)
begin
local_or_OUT=1'b0;
end // local 0 ;remote 1; default :remote ?
req_msg={pc[12:11],1'b1,local_id,1'b0,instreq_cmd,5'b00000,pc};
v_ic_req=1'b1;
inst_nstate=inst_wait_rep;
end
inst_wait_rep:
begin
if(v_inst_4word)
begin
tag_re=1'b1;
data_write=inst_4word;
data_we=1'b1;
inst1_inst2=1'b1;
v_inst=1'b1;
// gen new tag to tag ram
tag_we=1'b1;
/*new tag*/
state_tag_in = {2'b10,pc[12:9]}; // 10 means valid
end
end
endcase
end
assign inst=inst1_inst2?inst2:inst1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200009; const int MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false), cout.tie(0), cin.tie(0); int n, k, tot; cin >> n >> k; tot = n; vector<int> sta, vis(n + 2); vis[n + 1] = 1; int cur = 1; vector<int> ans; for (int i = 0; i < k; ++i) { int t; cin >> t; ans.push_back(t); sta.push_back(t); vis[t] = 1; tot--; while (((int)(sta).size()) && sta.back() == cur) { cur++; sta.pop_back(); } } for (int i = 1; i < ((int)(sta).size()); ++i) { if (sta[i] > sta[i - 1]) { cout << -1 n ; return 0; } } while (tot) { while (((int)(sta).size()) && sta.back() == cur) { cur++; sta.pop_back(); } int top; if (((int)(sta).size()) == 0) top = n + 1; else top = sta.back(); for (int i = top; i >= cur; --i) { if (!vis[i]) sta.push_back(i), tot--, ans.push_back(i); vis[i] = 1; } } for (int i : ans) cout << i << ; cout << n ; return 0; }
|
module tb_fpga();
// Test ports
reg A, B;
wire out;
// Configuration ports
reg [899:0] brbselect;
reg [29:0] leftioselect;
/*reg [29:0] rightioselect;
reg [29:0] topioselect;*/
reg [29:0] bottomioselect;
wire [4:0] left, right, top, bottom;
wire [2:0] ibl1w, ibr1w;
wire [14:0] ibbw, r_1;
// assign ibbw[0] = A;
assign bottom[0] = A;
// assign out = ibl1w[0];
assign out = left[0];
io_block ibl1(leftioselect[5:0], ibl1w, left[0]);
io_block ibb1(bottomioselect[5:0], ibbw[2:0], bottom[0]);
last_row_routing lrr1(brbselect[179:0], ibl1w, ibr1w, r_1, ibbw);
integer k = 5;
integer j;
initial begin
brbselect = 900'b0;
leftioselect = 30'b0;
/*rightioselect = 30'b0;
topioselect = 30'b0;*/
bottomioselect = 30'b0;
$display("initialized memory");
// brbselect[4] = 1'b1;
// brbselect[5] = 1'b0;
leftioselect[0] = 1'b1;
bottomioselect[1] = 1'b1;
// A = 1'b0;
$monitor("A = %b, out = %b", A, out);
// for (k = 0; k < 12; k = k + 1) begin
$display ("Current value of k is %d", k);
#10 brbselect = 900'b0; brbselect[k] = 1'b1; A = 1'b0;
#10 A = 1'b1;
// end
end
endmodule
|
#include <bits/stdc++.h> using ll = long long; using namespace std; int n, m; int const N = 3e5 + 2; int const M = (1 << 21); struct Triple { int fi; int se; int th; Triple(int f, int s, int t) : fi(f), se(s), th(t) {} }; struct Compare { bool operator()(const Triple& f, const Triple& g) { if (f.th != g.th) return (f.th < g.th); else return pair<int, int>{f.fi, f.se} < pair<int, int>{g.fi, g.se}; } }; vector<Triple> seg; int t[M]; int lazy[M]; int const INF = 1e9; void push(int v) { t[v * 2] += lazy[v]; lazy[v * 2] += lazy[v]; t[v * 2 + 1] += lazy[v]; lazy[v * 2 + 1] += lazy[v]; lazy[v] = 0; } int query(int v, int l, int r, int tl, int tr) { if (r < l) return INF; if (l == tl && r == tr) return t[v]; else { push(v); int mid = (tl + tr) / 2; int qw1 = query(v * 2, l, min(mid, r), tl, mid); int qw2 = query(v * 2 + 1, max(mid + 1, l), r, mid + 1, tr); return min(qw1, qw2); } } void update(int v, int l, int r, int tl, int tr, int val) { if (r < l) return; if (l == tl && r == tr) { t[v] += val; lazy[v] += val; } else { push(v); int mid = (tl + tr) >> 1; update(v << 1, l, min(mid, r), tl, mid, val); update((v << 1) + 1, max(mid + 1, l), r, mid + 1, tr, val); t[v] = min(t[v << 1], t[(v << 1) + 1]); } } int main() { scanf( %d %d , &n, &m); for (int i = (1); i <= (n); i++) { int l, r, w; scanf( %d %d %d , &l, &r, &w); seg.push_back(Triple({l, r, w})); } sort(seg.begin(), seg.end(), Compare()); int mu = 0; int lb = seg[0].th; int rb = seg[0].th; int ans = INF; for (int i = (1); i <= (n); i++) { update(1, seg[i - 1].fi, seg[i - 1].se - 1, 1, m - 1, 1); rb = seg[i - 1].th; while (query(1, 1, m - 1, 1, m - 1) > 0) { ans = min(ans, rb - lb); update(1, seg[mu].fi, seg[mu].se - 1, 1, m - 1, -1); mu++; if (mu != n) lb = seg[mu].th; } } printf( %d , ans); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: TEC
// Engineer: Jorge Carvajal Araya - Kenneth Morales Madriz
//
// Create Date: 09:22:59 08/13/2013
// Design Name:
// Module Name: PruebaSeleccion
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PruebaSeleccion(out, in, clk, btn0, btn1, btn2, btn3, led0, led1, led2, led3);
//out: Conectan las secciones de los siete segmentos
output reg [6:0] out;
//in: conectan los switch para definir en codigo binario en numero deseado
input wire [3:0] in;
//clk: reloj que permite la lectura de acciones
input wire clk;
//btn[0-3]: botones que determinan cual siete segmentos accionar
input wire btn0;
input wire btn1;
input wire btn2;
input wire btn3;
//led[0-3]: encienden o apagan los siete segmentos segun el boton presionado
output reg led0;
output reg led1;
output reg led2;
output reg led3;
//ledAux[0-3]: almacenan el valor que debe tomar cada led, de esta manera se evitan
//problemas por rebotes mecánicos en los siete segmentos
reg ledAux0;
reg ledAux1;
reg ledAux2;
reg ledAux3;
always @(posedge clk)
begin
//Boton 0 presionado
if(btn0 == 1)
begin
//Se enciende el primer led y se apagan los demás
ledAux0 = 0;
ledAux1 = 1;
ledAux2 = 1;
ledAux3 = 1;
end
//Boton 1 presionado
else if (btn1 == 1)
begin
//Se almacena un 0 en el segundo registro para y se apagan los demás
ledAux0 = 1;
ledAux1 = 0;
ledAux2 = 1;
ledAux3 = 1;
end
//Boton 2 presionado
else if (btn2 == 1)
begin
//Se enciende el tercer led y se apagan los demás
ledAux0 = 1;
ledAux1 = 1;
ledAux2 = 0;
ledAux3 = 1;
end
//Boton 3 presionado
else if (btn3 == 1)
begin
//Se enciende el cuarto led y se apagan los demás
ledAux0 = 1;
ledAux1 = 1;
ledAux2 = 1;
ledAux3 = 0;
end
//Se enciende el led correspondiente
led0 = ledAux0;
led1 = ledAux1;
led2 = ledAux2;
led3 = ledAux3;
//Se define una salida segun la entrada en código binario definida por los switch
case (in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'hA: out = 7'b0001000;
4'hB: out = 7'b0000011;
4'hC: out = 7'b1000110;
4'hD: out = 7'b0100001;
4'hE: out = 7'b0000110;
4'hF: out = 7'b0001110;
default: out = 7'b100000;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200100; int t, n; int MOD; vector<pair<long long int, long long int> > v[N]; long long int kol[N]; long long int gotov[N], sad, a, b; long long int c; long long int sol; vector<long long int> p; long long int FI; long long int inv[N], inv1[N]; long long int powmod(long long int a, long long int x) { long long int rez = 1; while (x) { if (x % 2) { rez = ((rez % MOD) * (a % MOD)) % MOD; } a = ((a % MOD) * (a % MOD)) % MOD; x /= 2; } return rez % MOD; } long long int divide(long long int a, long long int dub) { return a * inv[dub] % MOD; } int djeca(int node, int par) { kol[node] = 0; for (int i = 0; i < v[node].size(); i++) { if (v[node][i].first != par && !gotov[v[node][i].first]) kol[node] += djeca(v[node][i].first, node); } kol[node]++; return kol[node]; } int centr(int node, int par, int sz) { for (int i = 0; i < v[node].size(); i++) { if (v[node][i].first != par && !gotov[v[node][i].first] && kol[v[node][i].first] > sz / 2) { return centr(v[node][i].first, node, sz); } } return node; } map<long long int, long long int> m; map<long long int, long long int> pom[N]; void dfs(int node, int par, long long int x, long long int y, int d, int turn) { int di = ((-y) % MOD + MOD) % MOD; di = divide(di, d) % MOD; if (par != -1) sol += (m[di] - pom[turn][di]); if (!x && par != -1) sol++; if (!y && par != -1) sol++; for (int i = 0; i < v[node].size(); i++) { if (v[node][i].first != par && !gotov[v[node][i].first]) { int kamo; if (par == -1) kamo = i; else kamo = turn; long long int novix = ((v[node][i].second * inv1[d]) % MOD + x) % MOD; long long int noviy = ((y * 10) % MOD + v[node][i].second) % MOD; dfs(v[node][i].first, node, novix, noviy, d + 1, kamo); if (par == -1) pom[i].clear(); } } return; } void broji(int node, int par, long long int x, int d, int turn) { if (par != -1) { m[x % MOD]++; pom[turn][x % MOD]++; } for (int i = 0; i < v[node].size(); i++) { if (v[node][i].first != par && !gotov[v[node][i].first]) { int kamo; if (par == -1) kamo = i; else kamo = turn; long long int novix = ((v[node][i].second * inv1[d]) % MOD + x) % MOD; broji(v[node][i].first, node, novix, d + 1, kamo); } } return; } void decomp(int node, int par) { kol[node] = djeca(node, par); int sad = centr(node, par, kol[node]); broji(sad, -1, 0, 0, 0); dfs(sad, -1, 0, 0, 0, 0); m.clear(); gotov[sad] = 1; for (int i = 0; i < v[sad].size(); i++) { if (!gotov[v[sad][i].first]) decomp(v[sad][i].first, node); } return; } void solve() { cin >> n >> MOD; for (int i = 0; i < n - 1; i++) { cin >> a >> b >> c; v[a].push_back(make_pair(b, c)); v[b].push_back(make_pair(a, c)); } long long int k = MOD; long long int result = MOD; for (int p = 2; p * p <= k; ++p) { if (k % p == 0) { while (k % p == 0) k /= p; result -= result / p; } } if (k > 1) result -= result / k; FI = result; for (int i = 0; i <= n; i++) { inv1[i] = powmod(10, i); } for (int i = 0; i <= n; i++) { inv[i] = powmod(inv1[i], FI - 1); } decomp(0, -1); cout << sol << endl; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
|
//======================================================================
//
// cmac.v
// ------
// Top level wrapper for the CMAC core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module cmac(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam CTRL_FINAL_BIT = 2;
localparam ADDR_CONFIG = 8'h09;
localparam CONFIG_KEYLEN_BIT = 0;
localparam ADDR_STATUS = 8'h0a;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_FINAL_SIZE = 8'h0b;
localparam ADDR_KEY0 = 8'h10;
localparam ADDR_KEY7 = 8'h17;
localparam ADDR_BLOCK0 = 8'h20;
localparam ADDR_BLOCK1 = 8'h21;
localparam ADDR_BLOCK2 = 8'h22;
localparam ADDR_BLOCK3 = 8'h23;
localparam ADDR_RESULT0 = 8'h30;
localparam ADDR_RESULT1 = 8'h31;
localparam ADDR_RESULT2 = 8'h32;
localparam ADDR_RESULT3 = 8'h33;
localparam CORE_NAME0 = 32'h636d6163; // "cmac"
localparam CORE_NAME1 = 32'h2d616573; // "-aes"
localparam CORE_VERSION = 32'h302e3032; // "0.02"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg keylen_reg;
reg config_we;
reg [7 : 0] final_size_reg;
reg final_size_we;
reg [31 : 0] block_reg [0 : 3];
reg block_we;
reg [31 : 0] key_reg [0 : 7];
reg key_we;
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg finalize_reg;
reg finalize_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
wire core_ready;
wire core_valid;
wire [255 : 0] core_key;
wire [127 : 0] core_block;
wire [127 : 0] core_result;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign core_key = {key_reg[0], key_reg[1], key_reg[2], key_reg[3],
key_reg[4], key_reg[5], key_reg[6], key_reg[7]};
assign core_block = {block_reg[0], block_reg[1],
block_reg[2], block_reg[3]};
//----------------------------------------------------------------
// CMAC core instantiation.
//----------------------------------------------------------------
cmac_core cmac_inst(
.clk(clk),
.reset_n(reset_n),
.key(core_key),
.keylen(keylen_reg),
.final_size(final_size_reg),
.init(init_reg),
.next(next_reg),
.finalize(finalize_reg),
.block(core_block),
.result(core_result),
.ready(core_ready),
.valid(core_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0; i < 4; i = i + 1)
block_reg[i] <= 32'h0;
for (i = 0; i < 8; i = i + 1)
key_reg[i] <= 32'h0;
keylen_reg <= 1'h0;
final_size_reg <= 8'h0;
init_reg <= 1'h0;
next_reg <= 1'h0;
finalize_reg <= 1'h0;
end
else
begin
init_reg <= init_new;
next_reg <= next_new;
finalize_reg <= finalize_new;
if (config_we)
begin
keylen_reg <= write_data[CONFIG_KEYLEN_BIT];
end
if (final_size_we)
final_size_reg <= write_data[7 : 0];
if (key_we)
key_reg[address[2 : 0]] <= write_data;
if (block_we)
block_reg[address[1 : 0]] <= write_data;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'h0;
next_new = 1'h0;
finalize_new = 1'h0;
final_size_we = 1'h0;
config_we = 1'h0;
key_we = 1'h0;
block_we = 1'h0;
tmp_read_data = 32'h0;
if (cs)
begin
if (we)
begin
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1'h1;
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK3))
block_we = 1'h1;
case (address)
ADDR_CTRL:
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
finalize_new = write_data[CTRL_FINAL_BIT];
end
ADDR_CONFIG: config_we = 1'h1;
ADDR_FINAL_SIZE: final_size_we = 1'h1;
default:
begin
end
endcase // case (address)
end // if (we)
else
begin
case (address)
ADDR_NAME0: tmp_read_data = CORE_NAME0;
ADDR_NAME1: tmp_read_data = CORE_NAME1;
ADDR_VERSION: tmp_read_data = CORE_VERSION;
ADDR_CTRL: tmp_read_data = {31'h0, keylen_reg};
ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready};
ADDR_FINAL_SIZE: tmp_read_data = {24'h0, final_size_reg};
ADDR_RESULT0: tmp_read_data = core_result[127 : 96];
ADDR_RESULT1: tmp_read_data = core_result[95 : 64];
ADDR_RESULT2: tmp_read_data = core_result[63 : 32];
ADDR_RESULT3: tmp_read_data = core_result[31 : 0];
default:
begin
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // cmac
//======================================================================
// EOF cmac.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; pair<long long, long long> a[n]; for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a, a + n); queue<long long> q; set<long long> s; bool turn = true; long long ans[n]; for (long long i = n - 1; i >= 0; i--) { q.push(a[i].second); s.insert(i); } while (!q.empty()) { long long top = q.front(); q.pop(); if (s.find(top) == s.end()) continue; vector<long long> v; long long count = 0; for (auto itr = prev(s.find(top)); count < k && itr != prev(s.begin()); itr--) { v.push_back(*itr); count++; } count = 0; for (auto itr = s.find(top); count <= k && itr != s.end(); itr++) { v.push_back(*itr); count++; } for (long long i = 0; i < v.size(); i++) { s.erase(v[i]); ans[v[i]] = turn; } turn = !turn; } for (long long i = 0; i < n; i++) { if (ans[i]) cout << 1; else cout << 2; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A21BO_PP_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> a1, a2; vector<int> b1, b2; int subsolve(vector<int>& box, vector<int>& spec) { int N = (int) box.size(); int M = (int) spec.size(); vector<int> good (M+5, 0); int cumulate = 0; for (int i=M-1; i>=0; i--) { int& sp = spec[i]; if (binary_search(box.begin(), box.end(), sp)) cumulate++; good[i] = cumulate; } int ans=good[0]; for (int i=0; i<M; i++) { int boxcnt = (int)(upper_bound(box.begin(), box.end(), spec[i]) - box.begin()); // _ * _ _ _ * _ _ * // # # # # # # # # // [spec[i] - boxcnt + 1, spec[i] + 1) int left_spec = (int)(lower_bound(spec.begin(), spec.end(), spec[i] - boxcnt + 1) - spec.begin()); ans = max(ans, (i-left_spec+1) + good[i+1]); } return ans; } void solve() { a1.clear(); a2.clear(); b1.clear(); b2.clear(); cin >> n >> m; for (int i=0; i<n; i++) { int tmp; scanf( %d , &tmp); if (tmp > 0) a1.push_back(tmp); else a2.push_back(-tmp); } for (int i=0; i<m; i++) { int tmp; scanf( %d , &tmp); if (tmp > 0) b1.push_back(tmp); else b2.push_back(-tmp); } sort(a1.begin(), a1.end()); sort(a2.begin(), a2.end()); sort(b1.begin(), b1.end()); sort(b2.begin(), b2.end()); printf( %d n , subsolve(a1, b1) + subsolve(a2, b2)); } int main() { int t; cin >> t; while (t--) solve(); }
|
//deps: register_unit.v
`timescale 1ns/1ps
module register_unit_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] rD_data_out; // From ru of register_unit.v
wire [15:0] rS_data_out; // From ru of register_unit.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To ru of register_unit.v
reg en; // To ru of register_unit.v
reg [15:0] rD_data_in; // To ru of register_unit.v
reg [2:0] rD_sel; // To ru of register_unit.v
reg [15:0] rS_data_in; // To ru of register_unit.v
reg [2:0] rS_sel; // To ru of register_unit.v
reg rS_wr_en; // To ru of register_unit.v
reg wr_en; // To ru of register_unit.v
// End of automatics
register_unit ru (/*AUTOINST*/
// Outputs
.rD_data_out (rD_data_out[15:0]),
.rS_data_out (rS_data_out[15:0]),
// Inputs
.clk (clk),
.en (en),
.wr_en (wr_en),
.rS_wr_en (rS_wr_en),
.rD_sel (rD_sel[2:0]),
.rS_sel (rS_sel[2:0]),
.rD_data_in (rD_data_in[15:0]),
.rS_data_in (rS_data_in[15:0]));
initial begin
clk <= 0;
rD_sel <= 0;
en <= 0;
rS_sel <= 0;
wr_en <= 0;
rS_wr_en <= 0;
rD_data_in <= 0;
rS_data_in <= 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#20
en <= 1;
rD_sel <= 1;
rD_data_in <= 16'hfeed;
wr_en <= 1;
#10
rD_sel <= 0;
rD_data_in <= 16'hbeef;
wr_en <= 1;
#10
rD_sel <= 0;
rS_sel <= 1;
wr_en <= 0;
#10
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; const int mod = 1000000007; const int inf = 2012345678; const long long infl = 9012345678901234567; const double pi = 3.1415926535897932384626433832795; const int N = 20; const int M = 100010; char buf[M]; int a[M]; int dp[1 << N][N + 1]; int main() { freopen( input.txt , r , stdin); int n, m; scanf( %d%d , &(n), &(m)); for (int i = 0; i < (n); i++) { scanf( %s , buf); for (int j = 0; j < (m); j++) a[j] = 2 * a[j] + buf[j] - 0 ; } for (int i = 0; i < (m); i++) dp[a[i]][0]++; for (int i = 0; i < (m); i++) for (int j = 0; j < (n); j++) dp[a[i] ^ (1 << j)][1]++; for (int k = 2; k <= n; k++) { for (int i = 0; i < ((1 << n)); i++) { int sum = 0; for (int j = 0; j < (n); j++) { sum += dp[i ^ (1 << j)][k - 1]; } sum -= (n - k + 2) * dp[i][k - 2]; dp[i][k] = sum / k; } } int ans = inf; for (int i = 0; i < ((1 << n)); i++) { int s = 0; for (int k = 0; k <= (n); k++) { s += min(k, n - k) * dp[i][k]; } ans = min(ans, s); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> #define mset(arr, val) memset(arr, val, sizeof(arr)) #define all(v) v.begin(), v.end() #define F first #define S second #define endl n using namespace std; // const double PI = acos(-1.0); // const double E = exp(1.0); // const double EPS = 1e-9; const int MOD = (int)1e9 + 7; const int N = (int)2e5; int main() { #ifdef MY_LOCAL freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); #endif ios_base::sync_with_stdio(false); cin.tie(0); int T; cin >> T; for (int tc = 1; tc <= T; tc++) { int n; cin >> n; vector<int> a(n); map<int, int> mp; cin >> a[0]; mp[a[0]] = 0; for (int i = 1; i < n; i++) { cin >> a[i]; if (a[i] != a[i - 1]) { mp[a[i]]++; } } int ans = INT32_MAX; for (auto x : mp) { if (x.first != a[n - 1]) { x.second++; } ans = min(ans, x.second); } if (ans == INT32_MAX) { ans = 0; } cout << ans << endl; } return 0; }
|
`timescale 1 ns / 1 ps
module sfa_5to1_mux
(
output reg s1_tready ,
input wire s1_tvalid ,
input wire [31 : 0] s1_tdata ,
output reg s2_tready ,
input wire s2_tvalid ,
input wire [31 : 0] s2_tdata ,
output reg s3_tready ,
input wire s3_tvalid ,
input wire [31 : 0] s3_tdata ,
output reg s4_tready ,
input wire s4_tvalid ,
input wire [31 : 0] s4_tdata ,
output reg s5_tready ,
input wire s5_tvalid ,
input wire [31 : 0] s5_tdata ,
input wire mO_tready ,
output reg mO_tvalid ,
output reg [31 : 0] mO_tdata ,
input wire [ 3 : 0] CONF
);
always @(*)
begin
case (CONF)
4'd0: begin
mO_tvalid = 1'b0 ;
mO_tdata = 32'd0 ;
s1_tready = 1'b0 ;
s2_tready = 1'b0 ;
s3_tready = 1'b0 ;
s4_tready = 1'b0 ;
s5_tready = 1'b0 ;
end
4'd1: begin
mO_tvalid = s1_tvalid ;
mO_tdata = s1_tdata ;
s1_tready = mO_tready ;
s2_tready = 1'b0 ;
s3_tready = 1'b0 ;
s4_tready = 1'b0 ;
s5_tready = 1'b0 ;
end
4'd2: begin
mO_tvalid = s2_tvalid ;
mO_tdata = s2_tdata ;
s1_tready = 1'b0 ;
s2_tready = mO_tready ;
s3_tready = 1'b0 ;
s4_tready = 1'b0 ;
s5_tready = 1'b0 ;
end
4'd3: begin
mO_tvalid = s3_tvalid ;
mO_tdata = s3_tdata ;
s1_tready = 1'b0 ;
s2_tready = 1'b0 ;
s3_tready = mO_tready ;
s4_tready = 1'b0 ;
s5_tready = 1'b0 ;
end
4'd4: begin
mO_tvalid = s4_tvalid ;
mO_tdata = s4_tdata ;
s1_tready = 1'b0 ;
s2_tready = 1'b0 ;
s3_tready = 1'b0 ;
s4_tready = mO_tready ;
s5_tready = 1'b0 ;
end
4'd5: begin
mO_tvalid = s5_tvalid ;
mO_tdata = s5_tdata ;
s1_tready = 1'b0 ;
s2_tready = 1'b0 ;
s3_tready = 1'b0 ;
s4_tready = 1'b0 ;
s5_tready = mO_tready ;
end
default: begin
mO_tvalid = 1'b0 ;
mO_tdata = 32'd0 ;
s1_tready = 1'b0 ;
s2_tready = 1'b0 ;
s3_tready = 1'b0 ;
s4_tready = 1'b0 ;
s5_tready = 1'b0 ;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> int main() { const int maxN = 3002; bool tests[maxN] = {0}; int n(0); scanf( %d , &n); for (int k = 0; k < n; k++) { int temp; scanf( %d , &temp); tests[temp] = 1; } for (int index = 1; index < maxN; index++) { if (!tests[index]) { printf( %d n , index); break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; priority_queue<pair<long long, long long>, vector<pair<long long, long long>>, less<pair<long long, long long>>> q; priority_queue<long long, vector<long long>, greater<long long>> p; long long n, k, t, b, temp, res; int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> t >> b; q.push({b, t}); } for (int i = 0; i < n; i++) { pair<long long, long long> tt = q.top(); if (p.size() < k) { p.push(tt.second); temp += tt.second; } else { if (tt.second > p.top()) { temp += (tt.second - p.top()); p.pop(); p.push(tt.second); } } q.pop(); res = max(res, tt.first * temp); } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, m; cin >> n; vector<string> a(n); for (int i = 0; i < n; i++) cin >> a[i]; cin >> m; vector<vector<string>> b(m); bool new_problem = 1; for (int i = 0; i < m; i++) { int k; cin >> k; b[i].resize(k); for (int j = 0; j < k; j++) cin >> b[i][j]; int cnt = 0; for (int j = 0; j < n; j++) { for (int p = 0; p < k; p++) { if (a[j] == b[i][p]) { cnt++; break; } } } new_problem &= cnt != n; } if (new_problem) { cout << Brand new problem! n ; return 0; } vector<int> p(n); iota(p.begin(), p.end(), 0); const int INF = 1e9; pair<int, int> best = {INF, INF}; do { int cost = 0; for (int i = 1; i < n; i++) { for (int j = i - 1; j >= 0; j--) cost += p[i] < p[j]; } int take = -1; for (int i = 0; i < m; i++) { int ptr = 0; for (int j = 0; j < (int)b[i].size(); j++) { if (a[p[ptr]] == b[i][j]) ptr++; if (ptr == n) { break; } } if (ptr == n) { take = i; break; } } if (take != -1) { if (cost < best.first || (cost == best.first && take < best.second)) best = {cost, take}; } } while (next_permutation(p.begin(), p.end())); int x = (n * (n - 1) / 2 - best.first + 1); cout << best.second + 1 << n ; cout << [: ; while (x) { cout << | ; x--; } cout << :] n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_FUNCTIONAL_V
|
/*
* File: demo_top.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* top module for FPGA demo on XUP board
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module demo_top(
FPGA_SYSTEMACE_CLOCK,
SW_0, SW_1, SW_2, SW_3,
PB_ENTER, PB_UP, PB_DOWN, PB_LEFT, PB_RIGHT,
LED_0, LED_1, LED_2, LED_3,
RS232_TX_DATA, RS232_RX_DATA
);
//
// I/O
//
// clock to DCM
input FPGA_SYSTEMACE_CLOCK; // 32MHz
// swith on board
input SW_0;
input SW_1;
input SW_2;
input SW_3;
// pushbotton on board
input PB_ENTER;
input PB_UP;
input PB_DOWN;
input PB_LEFT;
input PB_RIGHT;
// led on board
output LED_0;
output LED_1;
output LED_2;
output LED_3;
// uart on board
input RS232_RX_DATA;
output RS232_TX_DATA;
//
// interconnections
//
wire dsu_sram_we;
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [31:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [31:0] dimx_dat_o;
wire [31:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
//
// clock and reset
//
demo_clk demo_clk (
.CLK_IN(FPGA_SYSTEMACE_CLOCK),
.RST(1'b0),
.CLK1X(clk32M),
.CLK2X(clk),
.LOCK(dcm_lock)
);
// [TBD] BUFG
wire rst_tmp;
assign rst_tmp = !PB_ENTER;
reg rst_tmp1, rst_tmp2, rst_tmp3;
always @(posedge clk) begin
rst_tmp1 <= rst_tmp;
rst_tmp2 <= rst_tmp1;
rst_tmp3 <= rst_tmp2;
end
assign rst = rst_tmp1 & rst_tmp2 & rst_tmp3;
//
// heartbreak logic: clock is running
//
// Note: frequency of clk is 64MHz. 1s = 15.5ns * 64 * 10e6 (0x3D0_9000, 0011_1101_0000_1001_0000_0000_0000)
reg [26:0] clk_counter;
always @(posedge clk or posedge rst) begin
if(rst)
clk_counter <= 27'd0;
else
clk_counter <= clk_counter + 27'd1;
end
//
// reserved logic: just to keep core un-optimized by synthesis tool
//
wire iimx_rqt_status;
wire iimx_rsp_status;
wire dimx_rqt_status;
wire dimx_rsp_status;
assign iimx_rqt_status = (|iimx_adr_o) & iimx_rqt_o;
assign dimx_rqt_status = (|dimx_adr_o) & dimx_rqt_o;
assign iimx_rsp_status = (|iimx_dat_i) & iimx_ack_i;
assign dimx_rsp_status = ((|dimx_dat_i) | dimx_we_o) & dimx_ack_i;
//
// xup-v2p board source
// Note: When the FPGA drives a logic 0, the corresponding LED turns on. A single four-position DIP
// switch and five push buttons are provided for user input. If the DIP switch is up, closed, or on,
// or the push button is pressed, a logic 0 is seen by the FPGA, otherwise a logic 1 is indicated.
// signal pushed assert when push push-buttons
wire pushed_tmp;
assign pushed_tmp = !(PB_UP & PB_DOWN & PB_LEFT & PB_RIGHT);
reg pushed_tmp1, pushed_tmp2, pushed_tmp3;
always @(posedge clk) begin
pushed_tmp1 <= pushed_tmp;
pushed_tmp2 <= pushed_tmp1;
pushed_tmp3 <= pushed_tmp2;
end
assign pushed = pushed_tmp1 & pushed_tmp2 & pushed_tmp3;
//
//
//
reg [9:0] num_burn_word;
always @(posedge clk or posedge rst) begin
if(rst)
num_burn_word <= 10'd0;
else if (dsu_sram_we)
num_burn_word <= num_burn_word + 10'd1;
end
//
// LED & SW
//
// SW_0: enable heartbreak flashing
// SW_1: enable imx rqt status flashing
// SW_2: enable imx rsp status flashing
// SW_3: enable for dsu burning mode
//
// LED0: status of clk
// LED1: status of imx request
// LED2: status of imx response
// LED3: status of on-chip ram burning process
assign dsu_rst = pushed;
assign dsu_burn_enable = SW_3;
assign LED0_light = clk_counter[26] & !rst & SW_0;
assign LED1_light = iimx_rqt_status | dimx_rqt_status & SW_1;
assign LED2_light = iimx_rsp_status | dimx_rsp_status & SW_2;
assign LED3_light = |num_burn_word;
assign LED_0 = ! LED0_light;
assign LED_1 = ! LED1_light;
assign LED_2 = ! LED2_light;
assign LED_3 = ! LED3_light;
//
// sys_top
//
top_pss sys_top_pss(
.clk(clk),
.rst(rst),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_we(dsu_sram_we),
.txd(RS232_TX_DATA),
.rxd(RS232_RX_DATA),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { long long n, x; cin >> n; string s = ; if (n % 2 == 0) { s += 1 ; } else s += 7 ; x = n / 2 - 1; for (long long i = 0; i < (x); ++i) s += 1 ; cout << s << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; int n, nn, m; int a[N], b[N], c[N]; int f[N]; inline void add(int i, int v) { for (; i <= n; i += i & -i) f[i] += v; } inline int find(int v) { int i = 0; for (int k = 20; k >= 0; k--) { if (i + (1 << k) <= n && f[i + (1 << k)] < v) { i += 1 << k; v -= f[i]; } } return i + 1; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) { scanf( %d , c + i); if (c[i] != -1) b[++nn] = c[i]; } for (int i = 1; i <= nn; i++) add(i, 1); nn = 0; for (int i = 1; i <= n; i++) { if (c[i] != -1) nn++; else { int k; for (k = 1; k <= m && a[k] <= nn; k++) add(find(a[k] - k + 1), -1); nn -= k - 1; } } if (nn == 0) { printf( Poor stack! n ); return 0; } for (int i = 1; i <= nn; i++) printf( %d , b[find(i)]); }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxfifo_8kx9_to_36.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rxfifo_8kx9_to_36 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [8:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output wrfull;
output [12:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [35:0] sub_wire1;
wire sub_wire2;
wire [12:0] sub_wire3;
wire wrfull = sub_wire0;
wire [35:0] q = sub_wire1[35:0];
wire rdempty = sub_wire2;
wire [12:0] wrusedw = sub_wire3[12:0];
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 8192,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 9,
dcfifo_mixed_widths_component.lpm_widthu = 13,
dcfifo_mixed_widths_component.lpm_widthu_r = 11,
dcfifo_mixed_widths_component.lpm_width_r = 36,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "8192"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "9"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "36"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "11"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "36"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 9 0 INPUT NODEFVAL "data[8..0]"
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL "q[35..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 13 0 OUTPUT NODEFVAL "wrusedw[12..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 9 0 data 0 0 9 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 13 0 @wrusedw 0 0 13 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxfifo_8kx9_to_36_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_scan_mux.v
//
// *Module Description:
// Generic mux for scan mode
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_scan_mux (
// OUTPUTs
data_out, // Scan mux data output
// INPUTs
data_in_scan, // Selected data input for scan mode
data_in_func, // Selected data input for functional mode
scan_mode // Scan mode
);
// OUTPUTs
//=========
output data_out; // Scan mux data output
// INPUTs
//=========
input data_in_scan; // Selected data input for scan mode
input data_in_func; // Selected data input for functional mode
input scan_mode; // Scan mode
//=============================================================================
// 1) SCAN MUX
//=============================================================================
assign data_out = scan_mode ? data_in_scan : data_in_func;
endmodule // omsp_scan_mux
|
#include <bits/stdc++.h> using namespace std; int where[26][26]; int n, dp[(1 << 23) + 5], d[35]; bool fdp[(1 << 23) + 5]; int rec(int mask) { if (fdp[mask]) return dp[mask]; int next = 0; for (int i = n - 1; i >= 0; --i) { if (mask & (1 << i)) { next = i; break; } } next++; fdp[mask] = 1; if (next == n) return dp[mask] = __builtin_popcount(mask); int make = d[next + 1]; dp[mask] = 30; int valid = 0; for (int i = 0; i < n; ++i) { if (mask & (1 << i)) { int j = where[next + 1][i + 1]; if (d[i + 1] < make and j) { j--; if (mask & (1 << j)) valid = 1; } } } if (valid) { dp[mask] = rec(mask | (1 << next)); for (int i = 0; i < next; ++i) { if (mask & (1 << i)) dp[mask] = min(dp[mask], rec((mask ^ (1 << i)) | (1 << next))); } } return dp[mask]; } int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> d[i]; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { int f = d[i] - d[j]; for (int k = 1; k <= n; ++k) { if (d[k] == f) { where[i][j] = k; } } } } int ans = rec(1); if (ans == 30) ans = -1; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int n, m; struct edge { int from; int to; int next; long long flow; } E[10005 << 1]; int sz = 1; int head[10005]; void add_edge(int u, int v, long long w) { sz++; E[sz].from = u; E[sz].to = v; E[sz].next = head[u]; E[sz].flow = w; head[u] = sz; sz++; E[sz].from = v; E[sz].to = u; E[sz].next = head[v]; E[sz].flow = 0; head[v] = sz; } int deep[10005]; bool bfs(int s, int t) { queue<int> q; memset(deep, 0, sizeof(deep)); q.push(s); deep[s] = 1; while (!q.empty()) { int x = q.front(); q.pop(); for (int i = head[x]; i; i = E[i].next) { int y = E[i].to; if (E[i].flow && !deep[y]) { deep[y] = deep[x] + 1; if (y == t) return 1; q.push(y); } } } return 0; } long long dfs(int x, int t, long long minf) { if (x == t) return minf; long long k, rest = minf; for (int i = head[x]; i; i = E[i].next) { int y = E[i].to; if (E[i].flow && deep[y] == deep[x] + 1) { k = dfs(y, t, min(rest, E[i].flow)); if (k == 0) deep[y] = 0; E[i].flow -= k; E[i ^ 1].flow += k; rest -= k; if (rest == 0) break; } } return minf - rest; } long long dinic(int s, int t) { long long maxflow = 0, nowflow = 0; while (bfs(s, t)) { while (nowflow = dfs(s, t, 0x3f3f3f3f3f3f3f3f)) maxflow += nowflow; } return maxflow; } int a[10005]; int main() { int u, v, w; scanf( %d %d , &n, &m); int s = 0, t = n + m + 1; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); add_edge(i, t, a[i]); } long long sum = 0; for (int i = 1; i <= m; i++) { scanf( %d %d %d , &u, &v, &w); sum += w; add_edge(s, i + n, w); add_edge(i + n, u, 0x3f3f3f3f3f3f3f3f); add_edge(i + n, v, 0x3f3f3f3f3f3f3f3f); } printf( %I64d n , sum - dinic(s, t)); }
|
#include <bits/stdc++.h> using namespace std; int n, m, qu; int a[100011]; int st[100011], en[100011]; int pos[100011]; int rt[100011], nxt[100011]; int step[100011]; bool vis[100011]; vector<int> v[100011], vv; queue<int> q; void bunhae_interval() { int r = n % m, mm = n / m; st[0] = 1; for (int i = 0; i < m; i++) { if (i) st[i] = en[i - 1] + 1; en[i] = st[i] + mm - 1; if (i < r) en[i]++; for (int j = st[i]; j <= en[i]; j++) pos[j] = i; } } void update(int x) { int p = pos[x]; for (int i = st[p]; i <= x; i++) vis[i] = 0; vis[x] = 1; q.push(x); while (!q.empty()) { int y = q.front(); q.pop(); for (int i = 0; i < v[y].size(); i++) { int z = v[y][i]; if (vis[z]) continue; vis[z] = 1; step[z] = step[y] + 1; rt[z] = rt[x]; q.push(z); } } } int main() { scanf( %d %d , &n, &qu); m = sqrt(n); bunhae_interval(); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = n; i >= 1; i--) { int j = i + a[i]; if (j > n || pos[j] != pos[i]) nxt[i] = j, rt[i] = i, step[i] = 0; else rt[i] = rt[j], step[i] = step[j] + 1, v[j].push_back(i); } while (qu--) { int tp, x, y; scanf( %d %d , &tp, &x); if (tp == 1) { int cnt = 1, en = x; while (1) { if (rt[en] == en) { if (nxt[en] > n) break; else cnt++, en = nxt[en]; } else { cnt += step[en], en = rt[en]; } } printf( %d %d n , en, cnt); } else { int xx = x + a[x]; if (xx > n) goto la; vv.clear(); for (int i = 0; i < v[xx].size(); i++) if (v[xx][i] != x) vv.push_back(v[xx][i]); v[xx].clear(); for (int i = 0; i < vv.size(); i++) v[xx].push_back(vv[i]); la:; scanf( %d , &y); int z = x + y; if (z > n || pos[z] != pos[x]) nxt[x] = z, rt[x] = x, step[x] = 0; else rt[x] = rt[z], step[x] = step[z] + 1, v[z].push_back(x); a[x] = y; update(x); } } }
|
// DATA derived from module add1 !!!!!!!!!!!!!!!!
// code used to capture inputs change to ref_dut
// converting them to vcd format fed to turbosim in_fifo
reg null_bit;
always @(ref_dut.a[0])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[0]), 14'd0, dt});
end
always @(ref_dut.a[10])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[10]), 14'd1, dt});
end
always @(ref_dut.a[11])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[11]), 14'd2, dt});
end
always @(ref_dut.a[12])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[12]), 14'd3, dt});
end
always @(ref_dut.a[13])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[13]), 14'd4, dt});
end
always @(ref_dut.a[14])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[14]), 14'd5, dt});
end
always @(ref_dut.a[15])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[15]), 14'd6, dt});
end
always @(ref_dut.a[1])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[1]), 14'd7, dt});
end
always @(ref_dut.a[2])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[2]), 14'd8, dt});
end
always @(ref_dut.a[3])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[3]), 14'd9, dt});
end
always @(ref_dut.a[4])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[4]), 14'd10, dt});
end
always @(ref_dut.a[5])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[5]), 14'd11, dt});
end
always @(ref_dut.a[6])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[6]), 14'd12, dt});
end
always @(ref_dut.a[7])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[7]), 14'd13, dt});
end
always @(ref_dut.a[8])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[8]), 14'd14, dt});
end
always @(ref_dut.a[9])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.a[9]), 14'd15, dt});
end
always @(ref_dut.b[0])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[0]), 14'd16, dt});
end
always @(ref_dut.b[10])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[10]), 14'd17, dt});
end
always @(ref_dut.b[11])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[11]), 14'd18, dt});
end
always @(ref_dut.b[12])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[12]), 14'd19, dt});
end
always @(ref_dut.b[13])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[13]), 14'd20, dt});
end
always @(ref_dut.b[14])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[14]), 14'd21, dt});
end
always @(ref_dut.b[15])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[15]), 14'd22, dt});
end
always @(ref_dut.b[1])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[1]), 14'd23, dt});
end
always @(ref_dut.b[2])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[2]), 14'd24, dt});
end
always @(ref_dut.b[3])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[3]), 14'd25, dt});
end
always @(ref_dut.b[4])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[4]), 14'd26, dt});
end
always @(ref_dut.b[5])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[5]), 14'd27, dt});
end
always @(ref_dut.b[6])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[6]), 14'd28, dt});
end
always @(ref_dut.b[7])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[7]), 14'd29, dt});
end
always @(ref_dut.b[8])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[8]), 14'd30, dt});
end
always @(ref_dut.b[9])
begin
dt = $time - start_time;
null_bit = push_input({encode_bit_value(ref_dut.b[9]), 14'd31, dt});
end
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:linescanner_image_capture_unit:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_linescanner_image_capture_unit_1_1 (
enable,
data,
rst_cvc,
rst_cds,
sample,
end_adc,
lval,
pixel_clock,
main_clock_source,
main_clock,
n_reset,
load_pulse,
pixel_data,
pixel_captured
);
input wire enable;
input wire [7 : 0] data;
output wire rst_cvc;
output wire rst_cds;
output wire sample;
input wire end_adc;
input wire lval;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire main_clock_source;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 main_clock CLK" *)
output wire main_clock;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 n_reset RST" *)
input wire n_reset;
output wire load_pulse;
output wire [7 : 0] pixel_data;
output wire pixel_captured;
linescanner_image_capture_unit inst (
.enable(enable),
.data(data),
.rst_cvc(rst_cvc),
.rst_cds(rst_cds),
.sample(sample),
.end_adc(end_adc),
.lval(lval),
.pixel_clock(pixel_clock),
.main_clock_source(main_clock_source),
.main_clock(main_clock),
.n_reset(n_reset),
.load_pulse(load_pulse),
.pixel_data(pixel_data),
.pixel_captured(pixel_captured)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { double a, b, c; while (cin >> a >> b >> c) { double m = a * c; cout << ceil(m / b) - c << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int MX = 300000; const long long mod = 1e9 + 7; const long long inf = 1e18; long long a[MX + 5]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long tc, cs = 1, i, j, k, x, y, z, n, m; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); for (i = 1; i <= n; i++) a[i] += a[i - 1]; cin >> m; for (i = 1; i <= m; i++) { cin >> x; y = a[n] - (a[n - x + 1] - a[n - x]); cout << y << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using Long = long long; vector<vector<int>> G(100010); int D[100010]; int dist[100010]; int P[100010]; int ep1 = -1, ep1lvl = -1, ep2 = -1, ep2lvl = -1; void dfs(int u, int p, int lvl) { if (lvl > ep1lvl) { ep1lvl = lvl; ep1 = u; } for (auto v : G[u]) { if (v != p) dfs(v, u, lvl + 1); } } void dfs1(int u, int p, int lvl) { P[u] = p; if (lvl > ep2lvl) { ep2lvl = lvl; ep2 = u; } for (auto v : G[u]) { if (v != p) dfs1(v, u, lvl + 1); } } int md; vector<int> path; void getMid(int u) { while (P[u] != -1) { path.push_back(u); u = P[u]; } path.push_back(u); reverse(path.begin(), path.end()); } bool ok = true; int n, k; int main() { cin >> n >> k; memset(D, 0, sizeof(D)); for (int i = 0; i < 100000; i++) P[i] = -1, dist[i] = 1 << 30; int first = 0; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; u--, v--; if (!i) first = u; G[u].push_back(v); G[v].push_back(u); D[u]++, D[v]++; } dfs(first, -1, 1); dfs1(ep1, -1, 1); if (ep2lvl <= k) { puts( No ); return 0; } getMid(ep2); md = path[k]; queue<int> Q; Q.push(md); dist[md] = 0; while (!Q.empty()) { int u = Q.front(); Q.pop(); if (u == md) { if (D[u] < 3) ok = false; } else { if (dist[u] != k && (D[u] - 1) < 3) ok = false; if (dist[u] == k && D[u] > 1) ok = false; } for (int v : G[u]) { if (dist[v] == 1 << 30) { dist[v] = dist[u] + 1; Q.push(v); } } } (ok) ? puts( Yes ) : puts( No ); return 0; }
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/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1, PC);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = 200;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[212345], sumi, wow, i; int main() { std::ios::sync_with_stdio(false); int n; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; sumi += a[i]; } wow = 0; for (i = 0; i < n; i++) { wow += a[i]; if (2 * wow >= sumi) break; } cout << i + 1 << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Weak Keeper
// /___/ /\ Filename : KEEPER.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module KEEPER (O);
inout O;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
reg in;
always @(O)
if (O)
in <= 1;
else
in <= 0;
buf (pull1, pull0) B1 (O, in);
endmodule
`endcelldefine
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
// ============================================================================
// CMT
// PLLE2_ADV_VPR
(* blackbox *)
module PLLE2_ADV_VPR (
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input PWRDWN,
input RST,
output LOCKED,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter [0:0] INV_CLKINSEL = 1'd0;
parameter [0:0] ZINV_PWRDWN = 1'd0;
parameter [0:0] ZINV_RST = 1'd1;
parameter [0:0] STARTUP_WAIT = 1'd0;
// Tables
parameter [9:0] TABLE = 10'd0;
parameter [39:0] LKTABLE = 40'd0;
parameter [15:0] POWER_REG = 16'd0;
parameter [11:0] FILTREG1_RESERVED = 12'd0;
parameter [9:0] FILTREG2_RESERVED = 10'd0;
parameter [5:0] LOCKREG1_RESERVED = 6'd0;
parameter [0:0] LOCKREG2_RESERVED = 1'b0;
parameter [0:0] LOCKREG3_RESERVED = 1'b0;
// DIVCLK
parameter [5:0] DIVCLK_DIVCLK_HIGH_TIME = 6'd0;
parameter [5:0] DIVCLK_DIVCLK_LOW_TIME = 6'd0;
parameter [0:0] DIVCLK_DIVCLK_NO_COUNT = 1'b1;
parameter [0:0] DIVCLK_DIVCLK_EDGE = 1'b0;
// CLKFBOUT
parameter [5:0] CLKFBOUT_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKFBOUT_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKFBOUT_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKFBOUT_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKFBOUT_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKFBOUT_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKFBOUT_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKFBOUT_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKFBOUT_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT0
parameter [5:0] CLKOUT0_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT0_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT0_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT0_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT0_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT0_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT0_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT0_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT0_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT0_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT1
parameter [5:0] CLKOUT1_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT1_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT1_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT1_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT1_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT1_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT1_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT1_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT1_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT1_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT2
parameter [5:0] CLKOUT2_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT2_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT2_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT2_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT2_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT2_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT2_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT2_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT2_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT2_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT3
parameter [5:0] CLKOUT3_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT3_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT3_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT3_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT3_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT3_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT3_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT3_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT3_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT3_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT4
parameter [5:0] CLKOUT4_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT4_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT4_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT4_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT4_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT4_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT4_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT4_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT4_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT4_CLKOUT2_NO_COUNT = 1'b1;
// CLKOUT5
parameter [5:0] CLKOUT5_CLKOUT1_HIGH_TIME = 6'd0;
parameter [5:0] CLKOUT5_CLKOUT1_LOW_TIME = 6'd0;
parameter [0:0] CLKOUT5_CLKOUT1_OUTPUT_ENABLE = 1'b0;
parameter [2:0] CLKOUT5_CLKOUT1_PHASE_MUX = 3'd0;
parameter [5:0] CLKOUT5_CLKOUT2_DELAY_TIME = 6'd0;
parameter [0:0] CLKOUT5_CLKOUT2_EDGE = 1'b0;
parameter [2:0] CLKOUT5_CLKOUT2_FRAC = 3'd0;
parameter [0:0] CLKOUT5_CLKOUT2_FRAC_EN = 1'b0;
parameter [0:0] CLKOUT5_CLKOUT2_FRAC_WF_R = 1'b0;
parameter [0:0] CLKOUT5_CLKOUT2_NO_COUNT = 1'b1;
// TODO: Compensation parameters
// TODO: How to simulate a PLL in verilog (i.e. the VCO) ???
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:29:57 03/24/2014
// Design Name:
// Module Name: gpr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gpr(clk, regwrite, data_in, reg_addr1, reg_addr2, write_addr, reg_out1, reg_out2
);
input clk;
input regwrite;
input [31:0] data_in;
input [4:0] reg_addr1, reg_addr2;
input [4:0] write_addr;
output [31:0] reg_out1, reg_out2;
reg [31:0] gpr_reg [31:0];
always @(posedge clk) begin
if(regwrite && write_addr != 5'h00)
gpr_reg[write_addr] <= data_in;
end
assign reg_out1 = (reg_addr1 == 5'b00) ? 32'b0 : gpr_reg[reg_addr1];
assign reg_out2 = (reg_addr2 == 5'b00) ? 32'b0 : gpr_reg[reg_addr2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_LP_V
`define SKY130_FD_SC_LP__DFRBP_LP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrbp_lp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrbp_lp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_LP_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Compound ifdef test with else, exterior define
//
`define DOUBLE
module ifdef1;
reg error ;
`ifdef DOUBLE
`ifdef NOCODE
initial
begin
#20;
error = 1;
#20;
end
`else
initial
begin
#20;
error = 0;
#20;
end
`endif
`endif
initial
begin
#1;
error = 1;
#40;
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; struct Poi { int x, y; Poi() { x = y = 0; } Poi(int _x, int _y) : x(_x), y(_y) {} } q[200000], po[500]; int n, vX, vY, sX, sY, cX, cY, minX, minY, maxX, maxY, up, dw, lf, rt; int pre[500][500], li[200000], len, qi[200000]; bool tree[500][500]; int dx[] = {0, 0, -1, 1}; int dy[] = {-1, 1, 0, 0}; char dirc[] = DULR ; inline int sgn(int x) { return x > 0 ? 1 : x < 0 ? -1 : 0; } inline bool existTree(int x, int y) { if (x < minX || y < minY || x > maxX || y > maxY) return false; return tree[x][y]; } void bfs() { int head = 1, tail = 1; q[1] = Poi(vX, vY), pre[vX][vY] = -1; while (head <= tail) { Poi u = q[head++]; for (int d = 0; d < 4; d++) { int _x = u.x + dx[d], _y = u.y + dy[d]; if (!existTree(_x, _y) && !pre[_x][_y] && 0 <= _x && _x <= 400 && 0 <= _y && _y <= 400) q[++tail] = Poi(_x, _y), pre[_x][_y] = d + 1; } } } inline int area(int x, int y) { return (x < minX ? -3 : x > maxX ? 3 : 0) + (y < minY ? -1 : y > maxY ? 1 : 0); } inline int dLf() { vY--, sY--, putchar(dirc[0]); } inline int dRt() { vY++, sY++, putchar(dirc[1]); } inline int dUp() { vX--, sX--, putchar(dirc[2]); } inline int dDw() { vX++, sX++, putchar(dirc[3]); } void towardsX(int Sj, int Tj) { while ((area(sX, sY) + 4) / 3 != Tj || (area(vX, vY) + 4) / 3 != Tj) Sj < Tj ? dDw() : dUp(); } void towardsY(int Si, int Ti) { while ((area(sX, sY) + 4) % 3 != Ti || (area(vX, vY) + 4) % 3 != Ti) Si < Ti ? dRt() : dLf(); } void moveTo(int S, int T) { if (S == T) return; if (S * T == -1) { while (area(sX, sY) > -2 || area(vX, vY) > -2) dUp(); if (S == -1) while (area(sX, sY) != -2 || area(vX, vY) != -2) dRt(); else while (area(sX, sY) != -4 || area(vX, vY) != -4) dLf(); } else if (S * T == -9) { while ((area(sX, sY) + 1) % 3 || (area(vX, vY) + 1) % 3) dLf(); if (S == -3) while (area(sX, sY) != 2 || area(vX, vY) != 2) dDw(); else while (area(sX, sY) != -4 || area(vX, vY) != -4) dUp(); } else { int Si = (S + 4) % 3, Sj = (S + 4) / 3, Ti = (T + 4) % 3, Tj = (T + 4) / 3; bool bS = S % 3 == 0 || abs(S) < 2, bT = T % 3 == 0 || abs(T) < 2, ord = 0; if (!bS && !bT) ord = 0; else if (!bS) ord = T % 3 != 0; else ord = S % 3 == 0; ord ? (towardsY(Si, Ti), towardsX(Sj, Tj)) : (towardsX(Sj, Tj), towardsY(Si, Ti)); } } void move() { if (!pre[sX][sY]) { puts( -1 ); if (n == 184) printf( T_T ); return; } for (int x = sX, y = sY; pre[x][y] != -1;) li[++len] = pre[x][y] - 1, x -= dx[li[len]], y -= dy[li[len]]; int hi = 1, ti = 0; vX = sX, vY = sY; for (int i = 1; i <= len; i++) { if (i < len - i + 1) swap(li[i], li[len - i + 1]); int _x = sX + dx[li[i]], _y = sY + dy[li[i]]; if (!existTree(_x, _y)) sX = _x, sY = _y, qi[++ti] = li[i]; } while ((vX != sX || vY != sY) && (area(sX, sY) != area(vX, vY) || area(sX, sY) == 0) && hi <= ti) { int d = qi[hi++], _x = sX + dx[d], _y = sY + dy[d]; vX += dx[d], vY += dy[d]; if (!existTree(_x, _y)) sX = _x, sY = _y, qi[++ti] = d; } if (hi > ti) { if (sX != vX || sY != vY) puts( -1 ); else { for (int i = 1; i <= len; i++) printf( %c , dirc[li[i]]); for (int i = 1; i <= hi - 1; i++) printf( %c , dirc[qi[i]]); } return; } for (int i = 1; i <= len; i++) printf( %c , dirc[li[i]]); for (int i = 1; i <= hi - 1; i++) printf( %c , dirc[qi[i]]); moveTo(area(sX, sY), sgn(vX - sX) * 3 + sgn(vY - sY)); if (vX != sX) { int t = vX < sX ? up : dw; while (sY < po[t].y) dRt(); while (sY > po[t].y) dLf(); if (vX < sX) { while (sX + 1 < po[t].x) dDw(); while (vX < sX) putchar(dirc[3]), vX++; } else { while (sX - 1 > po[t].x) dUp(); while (vX > sX) putchar(dirc[2]), vX--; } } if (vY != sY) { int t = vY < sY ? lf : rt; while (sY < po[t].y) dRt(); while (sY > po[t].y) dLf(); vY < sY ? dLf() : dRt(); while (sX < po[t].x) dDw(); while (sX > po[t].x) dUp(); if (vY < sY) while (vY < sY) putchar(dirc[1]), vY++; else while (vY > sY) putchar(dirc[0]), vY--; } } inline void proc(int &x, int &y) { x -= cX, y -= cY; } int main() { scanf( %d%d%d%d%d , &vX, &vY, &sX, &sY, &n); if (!n) { if (vX != sX || vY != sY) puts( -1 ); return 0; } up = dw = lf = rt = -1, minX = minY = 200, maxX = maxY = -200; for (int i = 1; i <= n; i++) { scanf( %d%d , &po[i].x, &po[i].y); minX = min(minX, po[i].x), minY = min(minY, po[i].y); maxX = max(maxX, po[i].x), maxY = max(maxY, po[i].y); if (up == -1 || po[up].x > po[i].x) up = i; if (dw == -1 || po[dw].x < po[i].x) dw = i; if (lf == -1 || po[lf].y > po[i].y) lf = i; if (rt == -1 || po[rt].y < po[i].y) rt = i; } cX = min(minX, min(sX, vX)) - 10, cY = min(minY, min(sY, vY)) - 10; for (int i = 1; i <= n; i++) proc(po[i].x, po[i].y), tree[po[i].x][po[i].y] = true; proc(vX, vY), proc(sX, sY), proc(minX, minY), proc(maxX, maxY); bfs(); move(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; int n, m; int popCount(int x) { int count = 0; while (x) { ++count; x &= x - 1; } return count; } inline bool Okay(int x) { return (((1 << m) - 1) & x) == ((1 << m) - 1); } int main() { ios::sync_with_stdio(false); cin >> n >> m; if (n < m) swap(n, m); int*** Arr = new int**[n + 1]; for (int i = 0; i <= n; ++i) { Arr[i] = new int*[1 << m]; for (int j = 0; j < (1 << m); ++j) { Arr[i][j] = new int[1 << m]; for (int k = 0; k < (1 << m); ++k) { Arr[i][j][k] = 100000000; } } } Arr[0][(1 << m) - 1][0] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < (1 << m); ++j) { for (int k = 0; k < (1 << m); ++k) { for (int t = 0; t < (1 << m); ++t) { if (Okay(j | k | t | (k >> 1) | (k << 1))) Arr[i + 1][k][t] = min(Arr[i + 1][k][t], Arr[i][j][k] + popCount(t)); } } } } int _ans = 100000; for (int k = 0; k < (1 << m); ++k) { for (int t = 0; t < (1 << m); ++t) { if (Okay(k | t | (t << 1) | (t >> 1))) _ans = min(_ans, Arr[n][k][t]); } } cout << n * m - _ans; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:21:12 05/09/2015
// Design Name:
// Module Name: interrupt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module interrupt(
input clock,
input IEN_d,
input IOF_d,
input RTI_d,
input branch_d,
input IRQ,
input [11:0] PC,
output reg branch_ISR,
output reg [11:0] ISR_adr
);
reg [11:0] return_adr;
reg IEN_reg;
reg IRQ_reg;
reg I;
initial begin
IEN_reg = 0;
return_adr = 0;
end
always @(posedge clock) begin
if (IEN_d == 1)
IEN_reg = 1;
if (IOF_d == 1)
IEN_reg = 0;
if (I == 1) begin
IEN_reg = 0;
return_adr = PC;
end
IRQ_reg = IRQ;
end
always @(*) begin
I <= IEN_reg & IRQ_reg & ~branch_d;
if (I == 1) begin
branch_ISR <= 1;
ISR_adr <= 12'h1;
end
else if (RTI_d == 1) begin
branch_ISR <= 1;
ISR_adr <= return_adr;
end
else begin
branch_ISR <= 0;
ISR_adr <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10; int gi() { int x = 0, o = 1; char ch = getchar(); while (!isdigit(ch) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } int n, m, f[N], id[N], dfn[N], tim, fa[N], fe[N], u[N], v[N], w[N]; bool in[N]; vector<pair<int, int> > E[N]; void dfs(int u) { dfn[u] = ++tim; for (auto e : E[u]) { int v = e.first; if (v != fa[u]) { if (!dfn[v]) fa[v] = u, fe[v] = e.second, dfs(v); else if (dfn[v] > dfn[u]) { int x = v; vector<int> vec = {e.second}; do vec.push_back(fe[x]), x = fa[x]; while (x != u); rotate(vec.begin(), min_element(vec.begin(), vec.end()), vec.end()); int p = max_element(vec.begin(), vec.end()) - vec.begin(); bool fl = 1; for (int i = 0; i < p && fl; i++) if (vec[i] > vec[i + 1]) fl = 0; for (int i = p; i < int(vec.size()) - 1 && fl; i++) if (vec[i] < vec[i + 1]) fl = 0; if (fl) id[vec[0]] = vec[p]; } } } } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) u[i] = gi(), v[i] = gi(), E[u[i]].push_back(make_pair(v[i], i)), E[v[i]].push_back(make_pair(u[i], i)); dfs(1); for (int i = 1; i <= n; i++) f[i] = 1; for (int i = m; i; i--) { w[i] = f[u[i]] + f[v[i]]; f[u[i]] = f[v[i]] = w[i] - w[id[i]]; } for (int i = 1; i <= n; i++) cout << f[i] - 1 << ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long int M = 1e9 + 7; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; vector<long long int> v; for (long long int i = 1; i <= 100000; ++i) { long long int x = (i * (3 * i + 1)) / 2; if (x <= 2e9) { v.push_back(x); } } while (t--) { long long int n; cin >> n; long long int ans = 0; while (n >= 2) { long long int x = lower_bound(v.begin(), v.end(), n) - v.begin(); if (v[x] != n) x--; n -= v[x]; ans++; } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } const int INF = 1 << 29; inline int two(int n) { return 1 << n; } inline int test(int n, int b) { return n & two(b); } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } inline int ones(int n) { int res = 0; while (n && ++res) n -= n & (-n); return res; } template <class T> void chmax(T& a, const T& b) { a = max(a, b); } template <class T> void chmin(T& a, const T& b) { a = min(a, b); } long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long nsn(long long a, long long b) { return a / gcd(a, b) * b; } int main() { long long a, b; cin >> a >> b; long long N = nsn(a, b); long long sum1 = N / a - 1, sum2 = N / b - 1; if (a < b) sum2++; else sum1++; if (sum1 > sum2) cout << Dasha << endl; else if (sum1 < sum2) cout << Masha << endl; else cout << Equal << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int w, h; char g[100][100], d[100][100]; bool use[100][100]; int dx[] = {-1, 0, 1, 0}; int dy[] = {0, -1, 0, 1}; bool is_valid(int y, int x) { return 0 <= y && y < h && 0 <= x && x < w; } bool check() { for (int i = 0; i < h; i++) { for (int j = 0; j < w; j++) { if (g[i][j] == B && !use[i][j]) return true; } } return false; } void dfs(int y, int x, int dir, bool can) { if (!is_valid(y, x)) return; if (g[y][x] == W ) return; use[y][x] = true; if (!can) dfs(y + dy[dir], x + dx[dir], dir, can); else { dfs(y + dy[dir], x + dx[dir], dir, can); for (int i = 0; i < 4; i++) { if (i == dir) continue; dfs(y + dy[i], x + dx[i], i, false); } } return; } int main() { cin >> h >> w; for (int i = 0; i < h; i++) { for (int j = 0; j < w; j++) { cin >> g[i][j]; d[i][j] = g[i][j]; } } for (int i = 0; i < h; i++) { for (int j = 0; j < w; j++) { memset(use, 0, sizeof(use)); if (g[i][j] == W ) continue; for (int k = 0; k < 4; k++) { dfs(i, j, k, true); } if (check()) { cout << NO << endl; return 0; } } } cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct guy { int x; int y; int t; }; int r, n; vector<guy> arr; vector<int> dp; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> r >> n; arr = vector<guy>(n); dp = vector<int>(n, 0); for (int i = 0; i < n; i++) { cin >> arr[i].t >> arr[i].x >> arr[i].y; } for (int i = n - 1; i >= 0; i--) { for (int j = i + 1; j < min(n, i + 4 * r); j++) { if (abs(arr[j].y - arr[i].y) + abs(arr[j].x - arr[i].x) <= arr[j].t - arr[i].t) dp[i] = max(dp[i], 1 + dp[j]); } } int ans = 0; for (int i = 0; i < n; i++) { if (abs(1 - arr[i].y) + abs(1 - arr[i].x) <= arr[i].t) { ans = max(ans, 1 + dp[i]); } } cout << ans << n ; return 0; }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_led (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`include "../network_params.h"module window_selector(
input clock,
input reset,
input [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_vector,
input [`X_COORD_BITWIDTH:0] x,
input [`Y_COORD_BITWIDTH:0] y,
output reg[`CAMERA_PIXEL_BITWIDTH:0] value_out
);
// wire declarations
wire [`CAMERA_PIXEL_BITWIDTH:0] buffer_wire [`BUFFER_BW:0][`BUFFER_BH:0];
// reg declarations
reg[`CAMERA_PIXEL_BITWIDTH:0] width_selector_wire [`BUFFER_BH:0];
genvar j;
genvar i;
generate
for (j=0; j<`BUFFER_H; j=j+1) begin : buffer_height_loop
for(i=0; i<`BUFFER_W; i=i+1) begin : buffer_width_loop
assign buffer_wire[i][j] = buffer_vector[
(`CAMERA_PIXEL_WIDTH*i)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*j) +`CAMERA_PIXEL_BITWIDTH:
(`CAMERA_PIXEL_WIDTH*i)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*j)
];
end // for i
end // for j
endgenerate
// width selector
genvar m;
generate
for (m=0; m<`BUFFER_H; m=m+1) begin : width_selector
always@(*) begin
case(x)
`X_COORD_WIDTH'd0: width_selector_wire[m] = buffer_wire[0][m];
`X_COORD_WIDTH'd1: width_selector_wire[m] = buffer_wire[1][m];
`X_COORD_WIDTH'd2: width_selector_wire[m] = buffer_wire[2][m];
`X_COORD_WIDTH'd3: width_selector_wire[m] = buffer_wire[3][m];
`X_COORD_WIDTH'd4: width_selector_wire[m] = buffer_wire[4][m];
`X_COORD_WIDTH'd5: width_selector_wire[m] = buffer_wire[5][m];
`X_COORD_WIDTH'd6: width_selector_wire[m] = buffer_wire[6][m];
`X_COORD_WIDTH'd7: width_selector_wire[m] = buffer_wire[7][m];
`X_COORD_WIDTH'd8: width_selector_wire[m] = buffer_wire[8][m];
`X_COORD_WIDTH'd9: width_selector_wire[m] = buffer_wire[9][m];
`X_COORD_WIDTH'd10: width_selector_wire[m] = buffer_wire[10][m];
`X_COORD_WIDTH'd11: width_selector_wire[m] = buffer_wire[11][m];
`X_COORD_WIDTH'd12: width_selector_wire[m] = buffer_wire[12][m];
`X_COORD_WIDTH'd13: width_selector_wire[m] = buffer_wire[13][m];
`X_COORD_WIDTH'd14: width_selector_wire[m] = buffer_wire[14][m];
`X_COORD_WIDTH'd15: width_selector_wire[m] = buffer_wire[15][m];
`X_COORD_WIDTH'd16: width_selector_wire[m] = buffer_wire[16][m];
`X_COORD_WIDTH'd17: width_selector_wire[m] = buffer_wire[17][m];
`X_COORD_WIDTH'd18: width_selector_wire[m] = buffer_wire[18][m];
`X_COORD_WIDTH'd19: width_selector_wire[m] = buffer_wire[19][m];
`X_COORD_WIDTH'd20: width_selector_wire[m] = buffer_wire[20][m];
`X_COORD_WIDTH'd21: width_selector_wire[m] = buffer_wire[21][m];
`X_COORD_WIDTH'd22: width_selector_wire[m] = buffer_wire[22][m];
`X_COORD_WIDTH'd23: width_selector_wire[m] = buffer_wire[23][m];
`X_COORD_WIDTH'd24: width_selector_wire[m] = buffer_wire[24][m];
`X_COORD_WIDTH'd25: width_selector_wire[m] = buffer_wire[25][m];
`X_COORD_WIDTH'd26: width_selector_wire[m] = buffer_wire[26][m];
`X_COORD_WIDTH'd27: width_selector_wire[m] = buffer_wire[27][m];
default: width_selector_wire[m] = `CAMERA_PIXEL_WIDTH'd0; endcase
end //always
end //for
endgenerate
always@(*) begin
case(y)
`Y_COORD_WIDTH'd0: value_out = width_selector_wire[0];
`Y_COORD_WIDTH'd1: value_out = width_selector_wire[1];
`Y_COORD_WIDTH'd2: value_out = width_selector_wire[2];
`Y_COORD_WIDTH'd3: value_out = width_selector_wire[3];
`Y_COORD_WIDTH'd4: value_out = width_selector_wire[4];
`Y_COORD_WIDTH'd5: value_out = width_selector_wire[5];
`Y_COORD_WIDTH'd6: value_out = width_selector_wire[6];
`Y_COORD_WIDTH'd7: value_out = width_selector_wire[7];
`Y_COORD_WIDTH'd8: value_out = width_selector_wire[8];
`Y_COORD_WIDTH'd9: value_out = width_selector_wire[9];
`Y_COORD_WIDTH'd10: value_out = width_selector_wire[10];
`Y_COORD_WIDTH'd11: value_out = width_selector_wire[11];
`Y_COORD_WIDTH'd12: value_out = width_selector_wire[12];
`Y_COORD_WIDTH'd13: value_out = width_selector_wire[13];
`Y_COORD_WIDTH'd14: value_out = width_selector_wire[14];
`Y_COORD_WIDTH'd15: value_out = width_selector_wire[15];
`Y_COORD_WIDTH'd16: value_out = width_selector_wire[16];
`Y_COORD_WIDTH'd17: value_out = width_selector_wire[17];
`Y_COORD_WIDTH'd18: value_out = width_selector_wire[18];
`Y_COORD_WIDTH'd19: value_out = width_selector_wire[19];
`Y_COORD_WIDTH'd20: value_out = width_selector_wire[20];
`Y_COORD_WIDTH'd21: value_out = width_selector_wire[21];
`Y_COORD_WIDTH'd22: value_out = width_selector_wire[22];
`Y_COORD_WIDTH'd23: value_out = width_selector_wire[23];
`Y_COORD_WIDTH'd24: value_out = width_selector_wire[24];
`Y_COORD_WIDTH'd25: value_out = width_selector_wire[25];
`Y_COORD_WIDTH'd26: value_out = width_selector_wire[26];
`Y_COORD_WIDTH'd27: value_out = width_selector_wire[27];
default: value_out = `CAMERA_PIXEL_WIDTH'd0;
endcase
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int MOD2 = (int)1e8 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return val < a ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } inline long long isqrt(long long k) { long long r = sqrt(k) + 1; while (r * r > k) r--; return r; } inline long long icbrt(long long k) { long long r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } inline int sign(long double x) { return x < -EPS ? -1 : x > +EPS; } inline int sign(long double x, long double y) { return sign(x - y); } template <class TF, class TC, TF Foo, TC Coo> struct MinCostMaximumFlow { static const int MAXV = 1e5 + 5; static const int MAXE = 1e6 + 5; int n, s, t, E; int adj[MAXE], nxt[MAXE], lst[MAXV], frm[MAXV], vis[MAXV]; TF cap[MAXE], flw[MAXE], totalFlow; TC cst[MAXE], dst[MAXV], totalCost; void init(int n, int s, int t) { this->n = n, this->s = s, this->t = t; fill_n(lst, n, -1), E = 0; } void add(int u, int v, TF ca, TC co) { adj[E] = v, cap[E] = ca, flw[E] = 0, cst[E] = +co, nxt[E] = lst[u], lst[u] = E++; adj[E] = u, cap[E] = 0, flw[E] = 0, cst[E] = -co, nxt[E] = lst[v], lst[v] = E++; } int spfa() { fill_n(dst, n, Coo), dst[s] = 0; queue<int> que; que.push(s); while (que.size()) { int u = que.front(); que.pop(); for (int e = lst[u]; e != -1; e = nxt[e]) if (flw[e] < cap[e]) { int v = adj[e]; if (dst[v] > dst[u] + cst[e]) { dst[v] = dst[u] + cst[e]; frm[v] = e; if (!vis[v]) { vis[v] = 1; que.push(v); } } } vis[u] = 0; } return dst[t] < Coo; } TC mincost() { totalCost = 0, totalFlow = 0; while (1) { if (!spfa()) break; TF mn = Foo; for (int v = t, e = frm[v]; v != s; v = adj[e ^ 1], e = frm[v]) mn = min(mn, cap[e] - flw[e]); for (int v = t, e = frm[v]; v != s; v = adj[e ^ 1], e = frm[v]) { flw[e] += mn; flw[e ^ 1] -= mn; } totalFlow += mn; totalCost += mn * dst[t]; } return totalCost; } }; MinCostMaximumFlow<int, int, (int)1e9, (int)1e9> mcmf; const int maxn = 5e3 + 5; int n; int a[maxn]; int num[100005]; void solve() { cin >> n; for (int i = (0); i < (n); i++) cin >> a[i]; int tot = n + n, s = tot++, t = tot++, ss = tot++; mcmf.init(tot, ss, t); mcmf.add(ss, s, 2, 0); for (int i = (0); i < (n); i++) { mcmf.add(s, i, 1, 0); mcmf.add(i + n, t, 1, 0); mcmf.add(i, i + n, 1, -1); static int* his[maxn]; int nhis = 0; for (int j = (i + 1); j < (n); j++) if (abs(a[i] - a[j]) == 1) { his[nhis++] = &num[a[j]]; if (num[a[j]]++ <= 4) { mcmf.add(i + n, j, 1, 0); } } for (int j = (0); j < (nhis); j++) (*his[j])--; } vector<int> lst[7]; for (int i = (n)-1; i >= (0); i--) { int r = a[i] % 7; for (int j = (0); j < (int((lst[r]).size())); j++) { mcmf.add(i + n, lst[r][j], 1, 0); } while (int((lst[r]).size()) > 4) lst[r].erase(lst[r].begin()); lst[r].push_back(i); } cout << -mcmf.mincost() << n ; } int main() { int JUDGE_ONLINE = 1; if (fopen( in.txt , r )) { JUDGE_ONLINE = 0; assert(freopen( in.txt , r , stdin)); } else { ios_base::sync_with_stdio(0), cin.tie(0); } solve(); if (!JUDGE_ONLINE) { } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_N_BLACKBOX_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ()
* Description: Phy layer SD host controller for 1 bit SD mode
* When the i_data_en signal goes high the core will read in the
* i_write_flag.
* Writing:
* If high then it will read in the i_data_h2s data until
* it reads i_data_count bytes from the host, each i_data_stb will tell
* the above phy to present a new byte to on the i_data_h2s register.
*
* Reading:
* read the number of bytes on i_data_count. when a new byte is finished
* the new byte will be on o_data_s2h.
*
* To activate a transaction set i_en along with i_write_flag to 1 for write
* or 0 for read, the core will strobe in/out data on it's own, it's
* up to the above layer to make sure there is enough data or space
* available, the maximum space should be 2048 bytes. when a transaction is
* finished the o_finished flag will go high, the controlling core must
* de-assert i_en in order to reset the core to get ready for new
* transactions. This signal will go high for one clock cycle if the host
* de-asserts i_en before a transaction is finished.
*
* clk: sdio_clk
* rst: reset core
* i_en: Enable a data transaction
* o_finished: transaction is finished (de-assert i_en to reset)
* i_write_flag: 1 = Write, 0 = Read
* i_data_h2s: Data from host to SD card
* o_data_h2s: Data from SD card to host
* i_data_count: Number of bytes to read/write
* o_data_stb: request or strobe in a byte
* o_crc_err: CRC error occured during read
* io_sd_data: raw sdio data bits
*
* Changes:
* 2015.08.24: Initial commit
*/
module sd_sd1_phy (
input clk,
input rst,
input i_en,
output reg o_finished,
input i_write_flag,
output reg o_crc_err, //Detected a CRC error during read
output reg o_data_stb,
input [11:0] i_data_count,
input [7:0] i_data_h2s,
output reg [7:0] o_data_s2h,
inout [7:0] io_sd_data
);
//local parameters
localparam IDLE = 4'h0;
localparam WRITE_START = 4'h1;
localparam WRITE = 4'h2;
localparam WRITE_CRC = 4'h3;
localparam WRITE_FINISHED= 4'h4;
localparam READ_START = 4'h5;
localparam READ = 4'h6;
localparam READ_CRC = 4'h7;
localparam FINISHED = 4'h8;
//registes/wires
reg [3:0] state;
reg [7:0] sd_data;
wire sd_data_bit;
wire [15:0] gen_crc;
reg [15:0] crc;
reg crc_rst;
reg [3:0] bit_count; //Need 4 bits to cound the CRC value
wire sd_bit;
reg r_sd_bit;
//submodules
sd_crc_16 (
.clk (clk ),
.rst (crc_rst ),
.en (crc_en ),
//.bitval (r_sd_bit ), //Shoud this be registered?
.bitval (sd_bit ),
.crc (gen_crc )
);
//asynchronous logic
assign sd_data_bit = (state == WRITE_START) ? 1'b0 :
(state == WRITE_CRC) ? crc[15] :
(state == WRITE_FINISHED) ? 1'b1 :
sd_data[7];
assign io_sd_data = (i_write_flag) ? {7'b0, sd_data_bit}, 8'hZZ;
assign sd_bit = io_sd_data[0];
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_data_stb <= 0;
if (rst) begin
sd_data <= 0;
state <= IDLE;
crc_rst <= 1;
crc_en <= 0;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
end
else begin
case (state)
IDLE: begin
crc_en <= 0;
crc_rst <= 1;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
if (i_en) begin
crc_rst <= 0;
if(i_write_flag) begin
state <= WRITE_START;
end
else begin
state <= READ_START;
end
end
end
WRITE_START: begin
//Set the data bit low to initiate a transaction
//The assignment statement above will take care of setting data bit to 0
state <= WRITE;
crc_en <= 1;
sd_data <= i_data_h2s;
end
WRITE: begin
sd_data <= {sd_data[6:0], 0};
bit_count <= bit_count + 1;
if (bit_count >= 7) begin
if (data_count < i_data_count) begin
o_data_stb <= 1;
bit_count <= 0;
data_count <= data_count + 1;
sd_data <= i_data_h2s;
end
else begin
state <= WRITE_CRC;
crc_en <= 0;
crc <= gen_crc;
end
end
end
WRITE_CRC: begin
crc <= {crc[14:0], sd_bit};
bit_count <= bit_count + 1;
if (bit_count >= 15) begin
state <= WRITE_FINISHED;
end
end
WRITE_FINISHED: begin
//Pass through, assign statement will set the value to 1
state <= FINISHED;
end
READ_START: begin
//Wait for data bit to go low
if (!sd_bit) begin
crc_en <= 1;
state <= READ;
end
end
READ: begin
//Shift the bits in
o_data_s2h <= {o_data_sh[6:0], sd_bit};
bit_count <= bit_count + bit_count + 8'h1;
if (bit_count >= 7) begin
//Finished reading a byte
o_data_stb <= 1; //Will this give me enough time for the new data to get clocked in?
bit_count <= 0;
if (data_count < i_data_count) begin
data_count <= data_count + 1;
end
else begin
//Finished reading all bytes
state <= READ_CRC;
end
end
end
READ_CRC: begin
crc_en <= 0; //XXX: should this be in the previous state??
crc <= {crc[14:0], sd_bit};
if (bit_count >= 15) begin
state <= FINISHED;
end
end
FINISHED: begin
o_finished <= 1;
if (crc != gen_crc) begin
o_crc_err <= 1;
end
if (!i_en) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
end
endcase
r_sd_bt <= sd_bit;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void prin(int n) { printf( %d n , n); } int main() { int n; cin >> n; long long cur = 3, mi = 7; for (int i = 1; i < 3 * n; i++) { cur *= 3; cur %= (int)1e9 + 7; } for (int i = 1; i < n; i++) { mi *= 7; mi %= (int)1e9 + 7; } cout << (((cur - mi) % ((int)1e9 + 7)) + ((int)1e9 + 7)) % ((int)1e9 + 7); }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_jumplogic(
ck,
reset_n,
cntr_value,
cntr_load,
reg_select,
reg_load_select,
jump_value,
jump_load,
jump_check,
jump_taken,
jump_address,
cntr_3
);
parameter DATA_WIDTH = 8;
input ck;
input reset_n;
input [DATA_WIDTH-1:0] cntr_value;
input cntr_load;
input [1:0] reg_select;
input [1:0] reg_load_select;
input [DATA_WIDTH-1:0] jump_value;
input jump_load;
input jump_check;
output jump_taken;
output [DATA_WIDTH-1:0] jump_address;
output [DATA_WIDTH-1:0] cntr_3;
reg [7:0] cntr [0:3];
reg [7:0] cntr_shadow [0:3];
reg [7:0] jump_pointers [0:3];
wire [3:0] comparisons;
assign jump_address = jump_pointers[reg_select];
assign jump_taken = (jump_check & ~comparisons[reg_select]);
assign cntr_3 = cntr[3];
genvar c;
generate
for(c = 0; c < 4; c = c + 1)
begin : jumpcounter
assign comparisons[c] = (cntr[c] == 8'b00000000);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
cntr[c] <= {DATA_WIDTH{1'b0}};
end
else if (cntr_load && reg_load_select == c) begin
cntr[c] <= cntr_value;
end
else if (jump_check && reg_select == c) begin
cntr[c] <= (comparisons[c]) ? cntr_shadow[c] : cntr[c] - 1'b1;
end
end
end
endgenerate
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
jump_pointers[0] <= {DATA_WIDTH{1'b0}};
jump_pointers[1] <= {DATA_WIDTH{1'b0}};
jump_pointers[2] <= {DATA_WIDTH{1'b0}};
jump_pointers[3] <= {DATA_WIDTH{1'b0}};
cntr_shadow[0] <= {DATA_WIDTH{1'b0}};
cntr_shadow[1] <= {DATA_WIDTH{1'b0}};
cntr_shadow[2] <= {DATA_WIDTH{1'b0}};
cntr_shadow[3] <= {DATA_WIDTH{1'b0}};
end
else begin
if(jump_load) begin
jump_pointers[0] <= (reg_load_select == 2'b00)? jump_value : jump_pointers[0];
jump_pointers[1] <= (reg_load_select == 2'b01)? jump_value : jump_pointers[1];
jump_pointers[2] <= (reg_load_select == 2'b10)? jump_value : jump_pointers[2];
jump_pointers[3] <= (reg_load_select == 2'b11)? jump_value : jump_pointers[3];
end
if(cntr_load) begin
cntr_shadow[0] <= (reg_load_select == 2'b00)? cntr_value : cntr_shadow[0];
cntr_shadow[1] <= (reg_load_select == 2'b01)? cntr_value : cntr_shadow[1];
cntr_shadow[2] <= (reg_load_select == 2'b10)? cntr_value : cntr_shadow[2];
cntr_shadow[3] <= (reg_load_select == 2'b11)? cntr_value : cntr_shadow[3];
end
end
end
endmodule
|
module mera400f(
input clk_ext,
// iobus
input rxd,
output txd,
// ram
output ram_ce, ram_oe, ram_we,
output [17:0] ram_a,
inout [15:0] ram_d,
// display
output [0:15] w,
output [10:0] rotary_bus,
output [0:9] indicators
);
parameter CLK_EXT_HZ;
// -----------------------------------------------------------------------
// --- Clocks ------------------------------------------------------------
// -----------------------------------------------------------------------
localparam CLK_SYS_HZ = CLK_EXT_HZ;
localparam CLK_UART_HZ = CLK_EXT_HZ;
wire clk_sys = clk_ext;
wire clk_uart = clk_ext;
wire clk_ram = clk_ext;
// -----------------------------------------------------------------------
// --- INTERFACE ---------------------------------------------------------
// -----------------------------------------------------------------------
// signal positions on the system bus
`define pa 0
`define cl 1
`define w 2
`define r 3
`define s 4
`define f 5
`define in 6
`define ok 7
`define en 8
`define pe 9
`define qb 10
`define pn 11
`define nb 12:15
`define ad 16:31
`define dt 32:47
`define BUS_MAX 47
// bus drivers for CPUs and memory (receivers on CPU and memory side)
wire [0:`BUS_MAX] cpu0r;
wire [0:`BUS_MAX] cpu1r;
wire [0:`BUS_MAX] memr;
wire [0:`BUS_MAX] iobr;
// interface reservation signals
wire [1:4] zg;
wire [1:4] zw;
wire [1:4] zz;
isk ISK(
.clk_sys(clk_sys),
.cpu0d(cpu0d),
.cpu0r(cpu0r),
.cpu1d(48'd0),
.cpu1r(cpu1r),
.iobd(iobd),
.iobr(iobr),
.memd(memd),
.memr(memr),
.zg(zg),
.zw(zw),
.zz(zz)
);
// -----------------------------------------------------------------------
// --- CPU ---------------------------------------------------------------
// -----------------------------------------------------------------------
// to system bus
wire [0:`BUS_MAX] cpu0d;
wire dmcl;
assign cpu0d[`cl] = dcl | dmcl;
// to control panel
wire p0;
wire hlt_n, p, run, _wait, irq, q, mc_0, awaria;
cpu #(
.CPU_NUMBER(1'b0),
.AWP_PRESENT(1'b1),
.INOU_USER_ILLEGAL(1'b1),
.STOP_ON_NOMEM(1'b1),
.LOW_MEM_WRITE_DENY(1'b0),
.ALARM_DLY_TICKS(23'd5_000_000),
.ALARM_TICKS(8'd3)
) CPU0(
.clk_sys(clk_sys),
// power supply
.off(off),
.pon(pon),
.pout(pout),
.clm(clm),
.clo(clo),
// control panel
.kl(kl),
.panel_store(panel_store),
.panel_fetch(panel_fetch),
.panel_load(panel_load),
.panel_bin(panel_bin),
.oprq(oprq),
.stop(stop),
.start(start),
.work(work),
.mode(mode),
.step(step),
.stop_n(stop_n),
.cycle(cycle),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.zegar(zegar),
.p0(p0),
.w(w),
.hlt_n(hlt_n),
.p(p),
.run(run),
._wait(_wait),
.irq(irq),
.q(q),
.mc_0(mc_0),
.awaria(awaria),
// system bus - drivers
.dmcl(dmcl),
.dw(cpu0d[`w]),
.dr(cpu0d[`r]),
.ds(cpu0d[`s]),
.df(cpu0d[`f]),
.din(cpu0d[`in]),
.dok(cpu0d[`ok]),
.dqb(cpu0d[`qb]),
.dpn(cpu0d[`pn]),
.dnb(cpu0d[`nb]),
.dad(cpu0d[`ad]),
.ddt(cpu0d[`dt]),
// system bus - receivers
.rpa(cpu0r[`pa]),
.rin(cpu0r[`in]),
.rok(cpu0r[`ok]),
.ren(cpu0r[`en]),
.rpe(cpu0r[`pe]),
.rpn(cpu0r[`pn]),
.rdt(cpu0r[`dt]),
// system bus reservation
.zg(zg[1]),
.zw(zw[1]),
.zz(zz[1])
);
// -----------------------------------------------------------------------
// --- P-K ---------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:15] kl;
wire zegar;
wire wre, rsa, rsb, rsc;
wire wic, wac, war, wir, wrs, wrz, wkb;
wire panel_store, panel_fetch, panel_load, panel_bin;
wire oprq, stop, start, work, mode, step, stop_n, cycle;
wire dcl;
// outputs to IOBUS
wire [0:3] rotary_pos;
assign rotary_bus = {wre, rsc, rsb, rsa, wic, wac, war, wir, wrs, wrz, wkb};
pk #(
.TIMER_CYCLE_MS(8'd10),
.CLK_SYS_HZ(CLK_SYS_HZ)
) PK(
.clk_sys(clk_sys),
.hlt_n(hlt_n),
.off(off),
.work(work),
.stop(stop),
.start(start),
.mode(mode),
.stop_n(stop_n),
.p0(p0),
.kl(kl),
.dcl(dcl),
.step(step),
.fetch(panel_fetch),
.store(panel_store),
.cycle(cycle),
.load(panel_load),
.bin(panel_bin),
.oprq(oprq),
.zegar(zegar),
.p(p),
.mc_0(mc_0),
.alarm(awaria),
._wait(_wait),
.irq(irq),
.q(q),
.run(run),
.wre(wre),
.rsa(rsa),
.rsb(rsb),
.rsc(rsc),
.wic(wic),
.wac(wac),
.war(war),
.wir(wir),
.wrs(wrs),
.wrz(wrz),
.wkb(wkb),
.indicators(indicators),
.rotary_pos(rotary_pos),
.rotary_in(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
// -----------------------------------------------------------------------
// --- IO BUS ------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:`BUS_MAX] iobd;
// outputs to CP
wire [0:3] rotary_out;
wire rotary_trig;
wire [0:15] keys;
wire keys_trig;
wire [0:3] fn;
wire fn_v;
wire fn_trig;
iobus #(
.CLK_UART_HZ(CLK_UART_HZ),
.UART_BAUD(1_000_000)
) IOBUS(
.clk_sys(clk_sys),
.clk_uart(clk_uart),
.rxd(rxd),
.txd(txd),
.zg(zg[4]),
.zw(zw[4]),
.dpa(iobd[`pa]),
.rcl(iobr[`cl]),
.dw(iobd[`w]),
.dr(iobd[`r]),
.rs(iobr[`s]),
.rf(iobr[`f]),
.din(iobd[`in]),
.rok(iobr[`ok]),
.dok(iobd[`ok]),
.den(iobd[`en]),
.dpe(iobd[`pe]),
.rpe(iobr[`pe]),
.rqb(iobr[`qb]),
.rpn(iobr[`pn]),
.dpn(iobd[`pn]),
.rnb(iobr[`nb]),
.dnb(iobd[`nb]),
.rad(iobr[`ad]),
.dad(iobd[`ad]),
.rdt(iobr[`dt]),
.ddt(iobd[`dt]),
.w(w),
.rotary_pos(rotary_pos),
.indicators(indicators),
.rotary_out(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
// -----------------------------------------------------------------------
// --- MEMORY ------------------------------------------------------------
// -----------------------------------------------------------------------
wire [0:`BUS_MAX] memd;
mem_elwro_sram MEM(
.clk(clk_ram),
.ram_ce(ram_ce),
.ram_oe(ram_oe),
.ram_we(ram_we),
.ram_a(ram_a),
.ram_d(ram_d),
.reset(memr[`cl]),
.reset_hold(memd[`cl]),
.nb(memr[`nb]),
.ad(memr[`ad]),
.rdt(memr[`dt]),
.ddt(memd[`dt]),
.w(memr[`w]),
.r(memr[`r]),
.s(memr[`s]),
.ok(memd[`ok])
);
// -----------------------------------------------------------------------
// --- POWER SUPPLY ------------------------------------------------------
// -----------------------------------------------------------------------
wire off, pout, pon, clo, clm;
puks PUKS(
.clk_sys(clk_sys),
.rcl(cpu0r[`cl]),
.dcl(dcl),
.off(off),
.pout(pout),
.pon(pon),
.clo(clo),
.clm(clm)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; int n; int main() { scanf( %d , &n); if (n % 5 == 0) { cout << n / 5; } else cout << n / 5 + 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, val; int arr[3] = {0}, count = 0; cin >> n; for (int i = 0; i < n; ++i) { cin >> val; arr[val]++; } if (arr[2] <= arr[1]) { count += arr[2]; arr[1] -= arr[2]; count += (arr[1] / 3); } else { count += arr[1]; } cout << count; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, ans; int main() { cin >> a >> b >> c; long long pom = min(a, b); a -= pom; b -= pom; ans = c + pom; ans <<= 1; if (a or b) ans++; cout << ans; }
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.ne1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.ne1_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module uut_1_bytep
(
output wire [31:0] data_o,
output wire sof_o,
input wire [7:0] data_i,
input wire sof_i,
input wire pclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg [7:0] data_z1;
reg sof_z1;
reg [7:0] data_z2;
reg sof_z2;
reg [7:0] data_z3;
reg sof_z3;
reg [7:0] data_z4;
reg sof_z4;
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge pclk_i) begin
data_z1[7:0] <= data_i[7:0];
sof_z1 <= sof_i;
data_z2[7:0] <= data_z1[7:0];
sof_z2 <= sof_z1;
data_z3[7:0] <= data_z2[7:0];
sof_z3 <= sof_z2;
data_z4[7:0] <= data_z3[7:0];
sof_z4 <= sof_z3;
end
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*)
begin
data_o[31:0] = {data_z4[7:0], data_z3[7:0], data_z2[7:0], data_z1[7:0]};
sof_o = sof_z4;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 28.04.2016 02:45:18
// Design Name:
// Module Name: pll_lock_lookup
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pll_lock_lookup(
input clk,
input [6:0] divider,
output reg [39:0] value
);
(*rom_style = "block" *) reg [39:0] lookup [0:64];
wire [5:0] addr;
initial
begin
lookup[00]=40'b00110_00110_1111101000_1111101001_0000000001;
lookup[01]=40'b00110_00110_1111101000_1111101001_0000000001;
lookup[02]=40'b01000_01000_1111101000_1111101001_0000000001;
lookup[03]=40'b01011_01011_1111101000_1111101001_0000000001;
lookup[04]=40'b01110_01110_1111101000_1111101001_0000000001;
lookup[05]=40'b10001_10001_1111101000_1111101001_0000000001;
lookup[06]=40'b10011_10011_1111101000_1111101001_0000000001;
lookup[07]=40'b10110_10110_1111101000_1111101001_0000000001;
lookup[08]=40'b11001_11001_1111101000_1111101001_0000000001;
lookup[09]=40'b11100_11100_1111101000_1111101001_0000000001;
lookup[10]=40'b11111_11111_1110000100_1111101001_0000000001;
lookup[11]=40'b11111_11111_1100111001_1111101001_0000000001;
lookup[12]=40'b11111_11111_1011101110_1111101001_0000000001;
lookup[13]=40'b11111_11111_1010111100_1111101001_0000000001;
lookup[14]=40'b11111_11111_1010001010_1111101001_0000000001;
lookup[15]=40'b11111_11111_1001110001_1111101001_0000000001;
lookup[16]=40'b11111_11111_1000111111_1111101001_0000000001;
lookup[17]=40'b11111_11111_1000100110_1111101001_0000000001;
lookup[18]=40'b11111_11111_1000001101_1111101001_0000000001;
lookup[19]=40'b11111_11111_0111110100_1111101001_0000000001;
lookup[20]=40'b11111_11111_0111011011_1111101001_0000000001;
lookup[21]=40'b11111_11111_0111000010_1111101001_0000000001;
lookup[22]=40'b11111_11111_0110101001_1111101001_0000000001;
lookup[23]=40'b11111_11111_0110010000_1111101001_0000000001;
lookup[24]=40'b11111_11111_0110010000_1111101001_0000000001;
lookup[25]=40'b11111_11111_0101110111_1111101001_0000000001;
lookup[26]=40'b11111_11111_0101011110_1111101001_0000000001;
lookup[27]=40'b11111_11111_0101011110_1111101001_0000000001;
lookup[28]=40'b11111_11111_0101000101_1111101001_0000000001;
lookup[29]=40'b11111_11111_0101000101_1111101001_0000000001;
lookup[30]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[31]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[32]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[33]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[34]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[35]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[36]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[37]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[38]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[39]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[40]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[41]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[42]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[43]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[44]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[45]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[46]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[47]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[48]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[49]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[50]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[51]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[52]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[53]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[54]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[55]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[56]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[57]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[58]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[59]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[60]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[6]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[00]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[00]=40'b11111_11111_0011111010_1111101001_0000000001;
end
assign addr = divider - 1;
always @(posedge clk)
begin
value = lookup[addr];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_TB_V
`define SKY130_FD_SC_MS__DLRBN_TB_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrbn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_ms__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; int n, m; int a[105][105]; int ans, row[105], col[105]; void caluRow() { for (int i = 1; i <= n; i++) { int mi = 501; for (int j = 1; j <= m; j++) mi = min(mi, a[i][j]); if (mi > 0) { ans += mi; row[i] += mi; for (int j = 1; j <= m; j++) a[i][j] -= mi; } } } void caluCol() { for (int i = 1; i <= m; i++) { int mi = 501; for (int j = 1; j <= n; j++) mi = min(mi, a[j][i]); if (mi > 0) { ans += mi; col[i] += mi; for (int j = 1; j <= n; j++) a[j][i] -= mi; } } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &a[i][j]); if (m > n) { caluRow(); caluCol(); } else { caluCol(); caluRow(); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j]) { printf( -1 ); return 0; } printf( %d n , ans); for (int i = 1; i <= n; i++) while (row[i]--) printf( row %d n , i); for (int i = 1; i <= m; i++) while (col[i]--) printf( col %d n , i); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; int fa[maxn][20], d[maxn], n, p, q, ans, b, c; int dist(int x, int y) { int res = d[x] + d[y]; if (d[x] < d[y]) swap(x, y); for (int j = 18; j >= 0; j--) if (d[fa[x][j]] >= d[y]) x = fa[x][j]; if (x == y) return res - 2 * d[x]; for (int j = 18; j >= 0; j--) if (fa[x][j] != fa[y][j]) x = fa[x][j], y = fa[y][j]; return res - 2 * d[fa[x][0]]; } int main() { scanf( %d , &n); d[0] = -1; p = q = 1; for (int i = 2; i <= n; i++) { scanf( %d , &fa[i][0]); d[i] = d[fa[i][0]] + 1; for (int j = 1; j <= 18; j++) fa[i][j] = fa[fa[i][j - 1]][j - 1]; b = dist(i, p); c = dist(i, q); if (b >= c && b >= ans) ans = b, q = i; else if (c >= b && c >= ans) ans = c, p = i; printf( %d , ans); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR2_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << --n / 2 << endl; return 0; }
|
#include <bits/stdc++.h> int n, m; char a[10000]; char b[10000]; int main() { scanf( %s %s , a, b); n = strlen(a); m = strlen(b); int minn = 10000000; for (int i = -m + 1; i < n; i++) { int count = 0; for (int j = 0; j < m; j++) { if (i + j < 0 || i + j >= n) { count++; } else if (a[i + j] != b[j]) count++; } if (count < minn) minn = count; } printf( %d n , minn); }
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
//
`define bsg_mem_1rw_sync_macro(bits,words) \
if (els_p == words && width_p == bits) \
begin: macro \
saed90_``bits``x``words``_1P mem \
(.CE1 (clk_lo) \
,.WEB1 (~w_i) \
,.OEB1 (1'b0) \
,.CSB1 (~v_i) \
,.A1 (addr_i) \
,.I1 (data_i) \
,.O1 (data_o) \
); \
end
module bsg_mem_1rw_sync #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(els_p)
,parameter addr_width_lp=$clog2(els_p)
// whether to substitute a 1r1w
,parameter substitute_1r1w_p=1
,parameter enable_clock_gating_p=1'b0
,parameter latch_last_read_p=0
)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,input [addr_width_lp-1:0] addr_i
,input v_i
,input w_i
,output logic [width_p-1:0] data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
// TODO: ADD ANY NEW RAM CONFIGURATIONS HERE
`bsg_mem_1rw_sync_macro (512,512) else
begin: z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(0)
) mem
(.w_clk_i (clk_lo )
,.w_reset_i (reset_i )
,.w_v_i (v_i & w_i )
,.w_addr_i (addr_i )
,.w_data_i (data_i )
,.r_addr_i (addr_i )
,.r_v_i (v_i & ~w_i)
,.r_data_o (data_lo )
);
// register output data to convert sync to async
always_ff @(posedge clk_lo)
data_o <= data_lo;
end // block: s1r1w
else
begin: notmacro
// Instantiate a synthesizable 1rw sync ram
bsg_mem_1rw_sync_synth #(.width_p(width_p), .els_p(els_p), .latch_last_read_p(latch_last_read_p)) synth
(.clk_i( clk_lo )
,.reset_i
,.data_i
,.addr_i
,.v_i
,.w_i
,.data_o
);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)
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#include <bits/stdc++.h> using namespace std; long long a, b, i, c, x, y, z, k, h; int main() { cin >> x >> y; for (a = 0; a <= 1000; a++) { for (b = 0; b <= 1000; b++) if (a * a + b == x && a + b * b == y) h++; } cout << h; }
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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(long long a) { write(a); puts( ); } inline void wri(long long a) { write(a); putchar( ); } inline unsigned long long rnd() { return ((unsigned long long)rand() << 30 ^ rand()) << 4 | rand() % 4; } const int N = 100005, ZT = 500, K = 5, mod = 1e9 + 7; struct data { int a[K]; bool ins(int x) { for (int i = (int)(K - 1); i >= (int)(0); i--) if (x >> i & 1) { if (a[i]) { x ^= a[i]; } else { for (int j = (int)(0); j <= (int)(i - 1); j++) if (x >> j & 1) x ^= a[j]; a[i] = x; for (int j = (int)(i + 1); j <= (int)(K - 1); j++) if (a[j] >> i & 1) a[j] ^= x; return 1; } } return 0; } int& operator[](int x) { return a[x]; } } A[ZT], ffff, qj; bool operator<(data a, data b) { for (int i = (int)(0); i <= (int)(K - 1); i++) if (a[i] != b[i]) return a[i] < b[i]; return 0; } map<data, int> M; vector<pair<int, int> > v[N]; bool vis[N], bj[N]; int dis[N], alb[N], fa[N], Q, QJ, QQ; void dfs(int p) { vis[p] = 1; for (auto i : v[p]) if (i.first != 1) { if (!vis[i.first]) { dis[i.first] = dis[p] ^ i.second; fa[i.first] = p; dfs(i.first); } else { if (bj[p] && bj[i.first]) { Q = 1; QQ = alb[p] ^ alb[i.first] ^ i.second; } else if (i.first != fa[p] && i.first < p) { QJ *= qj.ins(i.second ^ dis[p] ^ dis[i.first]); } } } } int dq, gg[ZT][ZT], zy[ZT][ZT]; long long ans, f[ZT], g[ZT]; inline void add(long long& a, long long b) { a = (a + b) % mod; } void dfs(data a) { if (!M.count(a)) { M[a] = ++dq; A[dq] = a; } else return; for (int j = (int)(0); j <= (int)((1 << K) - 1); j++) { data b = a; b.ins(j); dfs(b); } } int main() { dfs(ffff); for (int i = (int)(1); i <= (int)(dq); i++) for (int j = (int)(1); j <= (int)(dq); j++) { data a = A[i]; gg[i][j] = 1; for (int o = (int)(0); o <= (int)(K - 1); o++) if (A[j][o]) gg[i][j] &= a.ins(A[j][o]); zy[i][j] = M[a]; } int n = read(), m = read(); for (int i = (int)(1); i <= (int)(m); i++) { int a = read(), b = read(), w = read(); v[a].push_back(make_pair(b, w)); v[b].push_back(make_pair(a, w)); } for (auto i : v[1]) { bj[i.first] = 1; alb[i.first] = i.second; } vis[1] = 1; f[1] = 1; for (auto i : v[1]) if (!vis[i.first]) { Q = 0; QJ = 1; memset((qj.a), 0, sizeof(qj.a)); dfs(i.first); if (!QJ) continue; memcpy(g, f, sizeof(f)); if (Q) { int x = M[qj]; QJ *= qj.ins(QQ); int y = M[qj]; for (int j = (int)(1); j <= (int)(dq); j++) { if (gg[j][x]) add(g[zy[j][x]], f[j] * 2); if (gg[j][y]) add(g[zy[j][y]], f[j] * QJ); } } else { int x = M[qj]; for (int j = (int)(1); j <= (int)(dq); j++) if (gg[j][x]) add(g[zy[j][x]], f[j]); } swap(f, g); } for (int i = (int)(1); i <= (int)(dq); i++) add(ans, f[i]); cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; int a[n + 2]; int pos[n + 2]; for (int i = 1; i <= n; i++) { cin >> a[i]; pos[a[i]] = i; } int swap = 0; for (int i = 1; i <= n; i++) { int p = pos[i]; if (p == i) continue; int prev = a[i]; a[i] = i; pos[prev] = p; a[p] = prev; pos[i] = i; swap++; } if (n % 2) { if (swap % 2) { cout << Petr n ; } else { cout << Um_nik n ; } } else { if (swap % 2) { cout << Um_nik n ; } else { cout << Petr n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 100005; char buf[100000]; vector<pair<int, string> > vp; int b[maxn], n, m; pair<int, string> me; int getL() { int tx = 0, ret = 1; if (m == n) { me.first -= b[0]; tx = 1; } for (int i = 0; i < (int)vp.size(); i++) { if (vp[i] < me) { ret++; continue; } while (tx < m) { pair<int, string> tmp = vp[i]; tmp.first -= b[tx]; tx++; if (tmp < me) { ret++; break; } } } if (m == n) me.first += b[0]; return ret; } int getH() { me.first -= b[m - 1]; int tx = m - 2, ret = 1; vector<pair<int, string> > vp2; for (int i = 0; i < (int)vp.size(); i++) { if (vp[i] < me) { if (tx >= 0) tx--; ret++; } else vp2.push_back(vp[i]); } for (int i = (int)vp2.size() - 1; i >= 0; i--) { while (tx >= 0) { pair<int, string> tmp = vp2[i]; tmp.first -= b[tx]; tx--; if (tmp < me) { ret++; } else break; } } while (tx >= 0) { ret++; tx--; } me.first += b[m - 1]; return ret; } int main() { while (scanf( %d , &n) != EOF) { vp.clear(); for (int i = 0; i < n; i++) { int tmp; scanf( %s%d , buf, &tmp); vp.push_back(make_pair(-tmp, string(buf))); } scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &b[i]); } sort(b, b + m); scanf( %s , buf); string s(buf); for (int i = 0; i < (int)vp.size(); i++) { if (vp[i].second == s) { me = vp[i]; swap(vp[i], vp[vp.size() - 1]); vp.pop_back(); break; } } sort(vp.begin(), vp.end()); printf( %d %d n , getH(), getL()); } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_FUNCTIONAL_PP_V
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//decoder module
module decoder(instruction, nsel, opcode, readnum, writenum, ALUop, op, shift, sximm5, sximm8);
//inputs and outputs
input[15:0] instruction;
input [1:0] nsel;
output [2:0] opcode, readnum, writenum;
output [1:0] ALUop, op, shift;
output [15:0] sximm5, sximm8;
reg [2:0] tempReg;
wire [2:0] Rd, Rn, Rm;
//assignments based off of instruction
assign opcode = instruction[15:13];
assign op = instruction[12:11];
assign ALUop = instruction[12:11];
assign sximm5 = instruction[4]? {10'b1111111111,instruction[4:0]} : {10'b0000000000, instruction[4:0]};
assign sximm8 = instruction[7]? {7'b1111111,instruction[7:0]} : {7'b0000000, instruction[7:0]};
assign shift = instruction[4:3];
assign Rn = instruction[10:8];
assign Rd = instruction[7:5];
assign Rm = instruction[2:0];
always@(*) begin
case(nsel)
2'b00: tempReg = Rn; //nsel 00 = Rn
2'b01: tempReg = Rd; //nsel 01 = Rd
2'b10: tempReg = Rm; //nsel 10 = Rm
default: tempReg = 3'bxxx;
endcase
end
assign readnum = tempReg;
assign writenum = tempReg;
endmodule
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int maxN = 80; long long f[maxN]; int d[maxN]; const int maxD = 1000; const int K = 13; int dp[maxD][maxD]; bool filled = false; pair<int, int> get(int order, long long x) { if (order == K && filled) { return make_pair(dp[x][1], dp[x][f[K]]); } if (order == 0) { return make_pair(0, 0); } if (order == 1) { return make_pair(x != 1, x != 2); } if (x > f[order - 1]) { int add = 0; while (order > 1 && x > f[order - 1]) { x -= f[order - 1]; order -= 2; ++add; } pair<int, int> current = get(order, x); return make_pair(current.first + add, current.second); } pair<int, int> current = get(order - 1, x); int toOne = min(current.first, current.second + 2); int toN = min(current.first, current.second) + 1 + d[order - 2]; return make_pair(toOne, toN); } int calc(int order, long long x, long long y) { if (order == K && filled) { return dp[x][y]; } if (x == y) { return 0; } if (x > y) { swap(x, y); } if (order == 1) { return x != y; } if (order == 0) { return 0; } if (f[order - 1] >= y) { pair<int, int> a = get(order - 1, x); pair<int, int> b = get(order - 1, y); int score = min(a.first + b.second, a.second + b.first) + 2; return min(score, calc(order - 1, x, y)); } if (x > f[order - 1]) { while (order > 1 && x > f[order - 1]) { x -= f[order - 1]; y -= f[order - 1]; order -= 2; } return calc(order, x, y); } pair<int, int> a = get(order - 2, y - f[order - 1]); pair<int, int> b = get(order - 1, x); return min(b.first, b.second) + 1 + a.first; } void gen() { int t = 100000; int n = 1000; cout << t << << n << endl; for (int i = 0; i < t; ++i) { long long x = 1LL * rand() * rand() * rand() + 1LL; long long y = 1LL * rand() * rand() * rand() + 1LL; cout << x << << y << endl; } } int main() { f[0] = 1; f[1] = 2; for (int i = 2; i < maxN; ++i) { f[i] = f[i - 1] + f[i - 2]; } d[0] = 0; d[1] = 1; for (int i = 2; i < maxN; ++i) { d[i] = d[i - 2] + 1; } for (int i = 1; i <= f[K]; ++i) { for (int j = i; j <= f[K]; ++j) { dp[i][j] = dp[j][i] = calc(K, i, j); } } cerr << clock() << endl; filled = true; int t, n; scanf( %d%d , &t, &n); if (n >= maxN) { n = maxN - 1; } for (int i = 1; i <= t; ++i) { long long u, v; scanf( %I64d%I64d , &u, &v); if (u > v) { swap(u, v); } int m = n; while (m > 20 && f[m - 5] >= v) { --m; } printf( %d n , calc(m, u, v)); } cerr << clock() << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 7; const int mxn = 3e5 + 9; inline long long in() { long long _; scanf( %lld , &_); return _; } int n, m, k; struct node { int len; int link; int firstpos; map<char, int> nxt; void clr() { len = link = firstpos = 0; nxt.clear(); } void print() { cerr << __FUNCTION__ << << 50 << .. , cerr << len << = << len, cerr << , , cerr << link << = << link, cerr << , , cerr << firstpos << = << firstpos, cerr << endl; for (auto z : nxt) { cerr << z.first << << z.second << endl; } } }; node t[mxn]; int sz, last; void init() { sz = last = 0; t[0].len = 0; t[0].firstpos = 0; t[0].link = -1; sz++; } long long cnt[mxn]; set<pair<int, int> > nodes; void add_letter(char ch) { int cur = sz++; t[cur].len = t[last].len + 1; t[cur].firstpos = t[cur].len; cnt[cur] = 1; nodes.insert(make_pair(t[cur].len, cur)); int p; for (p = last; p != -1 && !t[p].nxt.count(ch); p = t[p].link) t[p].nxt[ch] = cur; if (p == -1) t[cur].link = 0; else { int q = t[p].nxt[ch]; if (t[p].len + 1 == t[q].len) t[cur].link = q; else { int clone = sz++; t[clone].len = t[p].len + 1; t[clone].nxt = t[q].nxt; t[clone].link = t[q].link; t[clone].firstpos = t[q].firstpos; cnt[clone] = 0; nodes.insert(make_pair(t[clone].len, clone)); for (; p != -1 && t[p].nxt[ch] == q; p = t[p].link) t[p].nxt[ch] = clone; t[q].link = t[cur].link = clone; } } last = cur; } string ans = ; void kth(int cur) { if (k <= 0) return; for (auto x : t[cur].nxt) { k -= cnt[x.second]; kth(x.second); if (k <= 0) { ans += x.first; return; } } } void CLR() { for (int i = 0; i < sz; i++) { t[i].clr(); cnt[i] = 0; } sz = last = 0; nodes.clear(); } char s[mxn]; int main() { int tc = 1; while (tc--) { scanf( %s , s); k = in(); init(); n = strlen(s); if (1LL * n * (n + 1) < k * 2) { printf( No such line. n ); continue; } for (int i = 0; i < n; i++) add_letter(s[i]); for (set<pair<int, int> >::reverse_iterator it = nodes.rbegin(); it != nodes.rend(); it++) { int x = (*it).second; cnt[t[x].link] += cnt[x]; } ans = ; kth(0); reverse(ans.begin(), ans.end()); printf( %s n , ans.c_str()); if (tc) CLR(); } return 0; }
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