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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
`timescale 1ns / 1ps
module vio_0 (
clk,
probe_out0,
probe_out1,
probe_out2,
probe_out3
);
input clk;
output reg [0 : 0] probe_out0 = 'h0 ;
output reg [0 : 0] probe_out1 = 'h0 ;
output reg [0 : 0] probe_out2 = 'h0 ;
output reg [0 : 0] probe_out3 = 'h0 ;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
`include "functions.vh"
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
`timescale 1 ns / 10 ps
module synth_reg_w_init (i, ce, clr, clk, o);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 'b0000;
parameter latency = 1;
input[width - 1:0] i;
input ce, clr, clk;
output[width - 1:0] o;
wire[(latency + 1) * width - 1:0] dly_i;
wire #0.2 dly_clr;
genvar index;
generate
if (latency == 0)
begin:has_0_latency
assign o = i;
end
else
begin:has_latency
assign dly_i[(latency + 1) * width - 1:latency * width] = i ;
assign dly_clr = clr ;
for (index=1; index<=latency; index=index+1)
begin:fd_array
// synopsys translate_off
defparam reg_comp_1.width = width;
defparam reg_comp_1.init_index = init_index;
defparam reg_comp_1.init_value = init_value;
// synopsys translate_on
single_reg_w_init #(width, init_index, init_value)
reg_comp_1(.clk(clk),
.i(dly_i[(index + 1)*width-1:index*width]),
.o(dly_i[index * width - 1:(index - 1) * width]),
.ce(ce),
.clr(dly_clr));
end
assign o = dly_i[width-1:0];
end
endgenerate
endmodule
module single_reg_w_init (i, ce, clr, clk, o);
parameter width = 8;
parameter init_index = 0;
parameter [width-1 : 0] init_value = 8'b00000000;
input[width - 1:0] i;
input ce;
input clr;
input clk;
output[width - 1:0] o;
parameter [0:0] init_index_val = (init_index == 1) ? 1'b1 : 1'b0;
parameter [width-1:0] result = (width > 1) ? { {(width-1){1'b0}}, init_index_val } : init_index_val;
parameter [width-1:0] init_const = (init_index > 1) ? init_value : result;
wire[width - 1:0] o;
genvar index;
generate
for (index=0;index < width; index=index+1) begin:fd_prim_array
if (init_const[index] == 0)
begin:rst_comp
FDRE fdre_comp(.C(clk),
.D(i[index]),
.Q(o[index]),
.CE(ce),
.R(clr));
end
else
begin:set_comp
FDSE fdse_comp(.C(clk),
.D(i[index]),
.Q(o[index]),
.CE(ce),
.S(clr));
end
end
endgenerate
endmodule
|
(** * Rel: Properties of Relations *)
(* $Date: 2012-04-23 14:08:14 -0400 (Mon, 23 Apr 2012) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
#include <bits/stdc++.h> using namespace std; const long long A = 31, mod = 1000000033LL; vector<string> read(int n) { vector<string> ans(n); for (auto &x : ans) cin >> x; return ans; } vector<long long> hsh(vector<string> vec, long long a) { vector<long long> ans; for (auto x : vec) { long long h = 0; for (auto y : x) h = (h * a + (y - a )) % mod; ans.push_back(h); } return ans; } long long hsh(vector<long long> &vec, int beg, int end, long long a) { long long h = 0; for (int i = beg; i < end; i++) h = (h * a + vec[i]) % mod; return h; } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; long long Am = 1; for (int i = 0; i < m; i++) Am = Am * A % mod; auto m1 = read(n), tmp2 = read(m); vector<string> m2(n, string(m, )); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) m2[i][j] = tmp2[j][i]; auto h1 = hsh(m1, A), h2 = hsh(m2, Am); vector<pair<long long, int>> vec; for (int i = 0; i + m <= n; i++) vec.emplace_back(hsh(h1, i, i + m, Am), i); sort(vec.begin(), vec.end()); for (int i = 0; i + m <= n; i++) { auto h = hsh(h2, i, i + m, A); auto p = lower_bound(vec.begin(), vec.end(), make_pair(h, 0)); if (p != vec.end() && p->first == h) { cout << p->second + 1 << << i + 1 << endl; return 0; } } }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> int debugnum = 0; using namespace std; const long long MOD = 998244353; inline long long add(long long a, long long b) { return (a + b) % MOD; } int toint(bitset<10> bs) { int ret = 0; for (int i = 9; i >= 0; i--) { ret = (ret << 1) | bs[i]; } return ret; } long long chpow(long long a, long long b) { long long ret = 1; for (long long i = 1; i <= b; i <<= 1) { if (i & b) ret = ret * a % MOD; a = a * a % MOD; } return ret; } long long DP[20][10][1024]; long long sum[20][10][1024]; void init() { memset(DP, 0, sizeof DP); memset(sum, 0, sizeof sum); for (int i = (0); i < (10); i++) DP[0][i][1 << i] = 1; for (int i = (0); i < (10); i++) sum[0][i][1 << i] = i; for (int i = (1); i < (19); i++) { for (int j = (0); j < (10); j++) { for (int S = (0); S < (1024); S++) { long long &tmp = DP[i][j][S]; long long &tmp2 = sum[i][j][S]; bitset<10> bs = S, bs1; if (bs[j] == 0) continue; bs1 = bs; bs1[j] = 0; for (int j1 = (0); j1 < (10); j1++) { tmp += DP[i - 1][j1][S] + DP[i - 1][j1][toint(bs1)]; tmp2 += sum[i - 1][j1][S] + sum[i - 1][j1][toint(bs1)]; tmp %= MOD; tmp2 %= MOD; } tmp2 += tmp * (j * chpow(10, i) % MOD) % MOD; tmp2 %= MOD; } } } } long long solve(long long N, long long K, bitset<10> S0, long long extra = 0) { long long ret = 0; long long Ai = N, p = 1, i = 0; while (Ai >= 10) Ai /= 10, p *= 10, i++; if (i == 0) { long long cnt = 0; for (int i = (0); i < (Ai + 1); i++) { if ((S0 | bitset<10>(1 << i)).count() <= K) cnt += i + extra; } cnt %= MOD; return cnt; } if (S0.count() == 0) { unsigned long long p = 1; for (int i = (0); i < (19); i++) { for (int j = (1); j < (10); j++) { if ((1LL + j) * p > N) break; for (int S1 = (0); S1 < (1024); S1++) { bitset<10> S = S1; if (S.count() <= K) { ret += sum[i][j][S1]; ret %= MOD; } } } p *= 10; } } else { for (int j = (0); j < (Ai); j++) { for (int S1 = (0); S1 < (1024); S1++) { bitset<10> S = bitset<10>(S1) | S0; if (S.count() <= K) { ret += DP[i][j][S1] * extra % MOD + sum[i][j][S1]; ret %= MOD; } } } } S0[Ai] = 1; if ((N - Ai * p) * 10 < p) S0[0] = 1; if (N >= 10) ret += solve(N - Ai * p, K, S0, (extra + Ai * p % MOD) % MOD); ret %= MOD; return ret; } int main() { init(); long long N, M, K; while (cin >> N >> M >> K) { N--; long long output = (MOD + solve(M, K, 0) - solve(N, K, 0)) % MOD; cout << output << endl; } return 0; }
|
#include <bits/stdc++.h> bool map[21][21]; int i, j, k, n, m, lim, tot, l, t, c[1 << 10]; long long f[1 << 10][1 << 10], ans; int main() { scanf( %d%d%d , &n, &m, &lim); tot = 1 << n; memset(map, 0, sizeof(map)); memset(f, 0, sizeof(f)); for (i = 0; i < tot; i++) for (j = i, c[i] = 0; j; j >>= 1) c[i] += j & 1; for (i = 1; i <= m; i++) { scanf( %d%d , &j, &k); map[j][k] = map[k][j] = 1; f[(1 << (j - 1)) + (1 << (k - 1))][(1 << (j - 1)) + (1 << (k - 1))] = 1; } for (i = 1; i < tot; i++) for (j = 1; j < i; j++) { if (c[i] <= c[j]) continue; for (k = j, l = 1; k; k >>= 1, l++) { if (!(k & 1)) continue; for (t = 1; t <= n; t++) if (map[t][l] && (i >> (t - 1)) % 2 && (j >> (t - 1)) % 2 == 0) f[i][j] += f[i - (1 << (l - 1))][j - (1 << (l - 1))] + f[i - (1 << (l - 1))][j - (1 << (l - 1)) + (1 << (t - 1))]; } f[i][j] /= c[j]; } for (i = 1; i < tot; i++) { if (c[i] == lim) ans += f[tot - 1][i]; } printf( %I64d n , ans); }
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: pc_next.v (tranlate from pc_next.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from pc_next.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Program Counter Next
// AUTHOR: Steve Rhoads ()
// DATE CREATED: 2/8/01
// FILENAME: pc_next.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements the Program Counter logic.
//-------------------------------------------------------------------
`include "yf32_define.v"
module pc_next (clk, reset, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_out, pc_out_plus4);
input clk;
input reset;
input [31:2] pc_new;
input take_branch;
input pause_in;
input [25:0] opcode25_0;
input [ 1:0] pc_source;
output [31:0] pc_out;
output [31:0] pc_out_plus4;
reg[31:2] pc_next;
// type pc_source_type is (from_inc4, from_opcode25_0, from_branch,
// from_lbranch);
reg[31:2] pc_reg;
wire [31:2] pc_inc = pc_reg + 1; //pc_reg+1
wire [31:0] pc_out = {pc_reg, 2'b00} ;
wire [31:0] pc_out_plus4 = {pc_inc, 2'b00} ;
always @(posedge clk or posedge reset)
begin
if (reset)
pc_reg <= `PC_RESET;
else
pc_reg <= pc_next;
end
always @(pc_source or pc_inc or pc_reg or opcode25_0 or
take_branch or pc_new or pause_in)
begin
case (pc_source)
`from_inc4 : pc_next = pc_inc;
`from_opcode25_0 : pc_next = {pc_reg[31:28], opcode25_0};
default : begin
//from_branch | from_lbranch =>
if (take_branch) pc_next = pc_new;
else pc_next = pc_inc;
end
endcase
if (pause_in == 1'b1)
begin
pc_next = pc_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); if (arr[n - 1] < arr[n - 2] + arr[n - 3]) { cout << YES << endl; for (int i = 0; i < n - 2; i++) { cout << arr[i] << ; } cout << arr[n - 1] << << arr[n - 2]; } else { cout << NO ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_1_V
`define SKY130_FD_SC_HVL__A22OI_1_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_1_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; int main() { int A, B; scanf( %d%d , &A, &B); int S = A + B; long long K = 0; while ((K + 1) * (K + 2) / 2 <= S) ++K; vector<int> a, b; for (int i = (K + 1) - 1; i >= (1); --i) { if (i <= A) { a.push_back(i); A -= i; } else { b.push_back(i); B -= i; } } printf( %d n , a.size()); for (auto k : a) printf( %d , k); printf( n ); printf( %d n , b.size()); for (auto k : b) printf( %d , k); printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int n, r[20], b[20]; char ch[20]; long long dp[(1 << 16)][260]; long long dfs(int bit, int discount) { long long& ret = dp[bit][discount]; if (ret != -1) return ret; if (bit == (1 << n) - 1) { return ret = 0; } ret = 0xffffffffffffff; int Rcard = 0, Bcard = 0, cnt = 0; ; long long Rused = 0, Bused = 0; for (int i = 0; i < n; i++) { if (bit & (1 << i)) { ++cnt; Rused += r[i]; Bused += b[i]; if (ch[i] == R ) ++Rcard; else Bcard++; } } int gap = discount - 120; long long remainR = 0, remainB = 0; if (gap > 0) Rused -= gap; else Bused += gap; if (Rused > Bused) { remainB = Rused - Bused; } else { remainR = Bused - Rused; } for (int i = 0; i < n; i++) { if (!(bit & (1 << i))) { long long maxi = max((long long)(r[i] - Rcard - remainR), (long long)(b[i] - Bcard - remainB)); maxi = max(maxi, (long long)0); long long discountR = min(r[i], Rcard); long long discountB = min(b[i], Bcard); long long go = dfs(bit | (1 << i), discount + discountR - discountB); ret = min(ret, go + maxi); } } return ret; } int main() { memset(dp, -1, sizeof(dp)); scanf( %d , &n); for (int i = 0; i < n; i++) { cin >> ch[i]; scanf( %d %d , &r[i], &b[i]); } long long ans = dfs(0, 120); ans += n; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long inf = 0x3f3f3f3f3f3f3f3f; const long long mod = 1e9 + 7; const int N = 2e5 + 10; int T; int n, m; int cnt[1000][2], mz[40][40]; int main() { scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &mz[i][j]); int a = abs(i - 1) + abs(j - 1); int b = abs(i - n) + abs(j - m); cnt[min(a, b)][mz[i][j]]++; } } int ans = 0; for (int i = 0; i <= (n - 1 + m - 1 - 1) / 2; i++) { ans += min(cnt[i][1], cnt[i][0]); } printf( %d n , ans); } return 0; }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_monitor.v
// Title : Debug monitor memory Wishbone interface
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.3
// : Removed port mismatch in instantiation of module
// : lm32_monitor_ram.
// =============================================================================
`include "system_conf.v"
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_monitor (
// ----- Inputs -------
clk_i,
rst_i,
MON_ADR_I,
MON_CYC_I,
MON_DAT_I,
MON_SEL_I,
MON_STB_I,
MON_WE_I,
// ----- Outputs -------
MON_ACK_O,
MON_RTY_O,
MON_DAT_O,
MON_ERR_O
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Wishbone clock
input rst_i; // Wishbone reset
input [10:2] MON_ADR_I; // Wishbone address
input MON_STB_I; // Wishbone strobe
input MON_CYC_I; // Wishbone cycle
input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
input MON_WE_I; // Wishbone write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output MON_ACK_O; // Wishbone acknowlege
reg MON_ACK_O;
output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
reg [`LM32_WORD_RNG] MON_DAT_O;
output MON_RTY_O; // Wishbone retry
wire MON_RTY_O;
output MON_ERR_O; // Wishbone error
wire MON_ERR_O;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [1:0] state; // Current state of FSM
wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
reg write_enable; // RAM write enable
reg [`LM32_WORD_RNG] write_data; // RAM write data
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_monitor_ram ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.ClockEnA (`TRUE),
.ClockEnB (`FALSE),
.AddressA (MON_ADR_I[10:2]),
.AddressB (9'b0),
.DataInA (write_data),
.DataInB (32'b0),
.WrA (write_enable),
.WrB (`FALSE),
// ----- Outputs -------
.QA (data),
.QB (dataB)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
assign MON_RTY_O = `FALSE;
assign MON_ERR_O = `FALSE;
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
write_enable <= #1 `FALSE;
MON_ACK_O <= #1 `FALSE;
MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
state <= #1 2'b00;
end
else
begin
casez (state)
2'b01:
begin
// Output read data to Wishbone
MON_ACK_O <= #1 `TRUE;
MON_DAT_O <= #1 data;
// Sub-word writes are performed using read-modify-write
// as the Lattice EBRs don't support byte enables
if (MON_WE_I == `TRUE)
write_enable <= #1 `TRUE;
write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
state <= #1 2'b10;
end
2'b10:
begin
// Wishbone access occurs in this cycle
write_enable <= #1 `FALSE;
MON_ACK_O <= #1 `FALSE;
MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
state <= #1 2'b00;
end
default:
begin
write_enable <= #1 `FALSE;
MON_ACK_O <= #1 `FALSE;
// Wait for a Wishbone access
if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
state <= #1 2'b01;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_SYMBOL_V
`define SKY130_FD_SC_MS__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 3e+5; bool vis[MAX_N] = {0}; char t = . ; int main() { int n, m, ans = 0, cnt = 0; string str; cin >> n >> m >> str; for (int i = 0; i < n; i++) { if (str[i] == t) { ans++; if (i == 0 || str[i - 1] != t) cnt++; vis[i + 1] = 1; } } while (m--) { int i; char ch; cin >> i >> ch; bool a = vis[i], b = ch == t; if (a != b) { if (a) ans--; else ans++; if (vis[i - 1] && vis[i + 1] && !b) cnt++; else if (vis[i - 1] && vis[i + 1] && b) cnt--; else if (!vis[i - 1] && !vis[i + 1] && !b) cnt--; else if (!vis[i - 1] && !vis[i + 1] && b) cnt++; } vis[i] = b; cout << ans - cnt << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) #pragma GCC optimization( unroll-loops ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); void naive(int x, int y) { if (x == y) { cout << Yes n ; return; } for (int i = 2; i * i <= x; i++) { while (x % i == 0) { if (y % (i * i) == 0) { y /= i * i; x /= i; } else if (x % (i * i) == 0 && y % i == 0) { x /= i * i; y /= i; } else { cout << No n ; return; } } } if (x == y * y || x * x == y) cout << Yes n ; else cout << No n ; } void fast(long long x, long long y) { long long p = x * y; long long l = 1, r = 1e6 + 42; while (r - l > 1) { long long m = ((r + l) >> 1); if (m * m * m > p) r = m; else l = m; } if (l * l * l == p && x % l == 0 && y % l == 0) cout << Yes n ; else if (r * r * r == p && x % r == 0 && y % r == 0) cout << Yes n ; else cout << No n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n = 0; cin >> n; while (n--) { long long a, b; cin >> a >> b; if (a > b) swap(a, b); fast(a, b); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { string s1; cin >> s1; int p1 = 0, p2 = 0, c1, c2; set<pair<pair<int, int>, pair<int, int> > > s; int c = 0; for (int i = 0; i < s1.size(); i++) { if (s1[i] == N ) { c2 = p2 + 1; c1 = p1; } else if (s1[i] == S ) { c2 = p2 - 1; c1 = p1; } else if (s1[i] == E ) { c1 = p1 + 1; c2 = p2; } else if (s1[i] == W ) { c1 = p1 - 1; c2 = p2; } if (s.find(make_pair(make_pair(c1, c2), make_pair(p1, p2))) != s.end() || s.find(make_pair(make_pair(p1, p2), make_pair(c1, c2))) != s.end()) { c = c + 1; } else { c = c + 5; s.insert(make_pair(make_pair(p1, p2), make_pair(c1, c2))); } p1 = c1; p2 = c2; } cout << c << n ; } }
|
`timescale 1ns/1ps
/***************************************************************************
Name:
Date: 7/18/2016
Founction: I2C top module
Note:
****************************************************************************/
module I2C_MASTER(clk,rst_n,sda,scl,RD_EN,WR_EN,receive_status,maddress_sel
);
input clk;
input maddress_sel;
input rst_n;
input RD_EN;
input WR_EN;
reg WR,RD;
output scl;
output receive_status;
inout sda;
reg scl_clk;
reg receive_status;
reg[7:0] clk_div;
reg[7:0] send_count;
wire[7:0] data;
reg[7:0] data_reg;
wire ack;
reg[7:0] send_memory[31:0];
reg[7:0] receive_memory[31:0];
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
scl_clk <= 1'b0;
clk_div <= 'h0;
send_memory[0] <= 8'd0;
send_memory[1] <= 8'd1;
send_memory[2] <= 8'd2;
send_memory[3] <= 8'd3;
send_memory[4] <= 8'd4;
send_memory[5] <= 8'd5;
send_memory[6] <= 8'd6;
send_memory[7] <= 8'd7;
send_memory[8] <= 8'd8;
send_memory[9] <= 8'd9;
send_memory[10] <= 8'd10;
send_memory[11] <= 8'd11;
send_memory[12] <= 8'd12;
send_memory[13] <= 8'd13;
send_memory[14] <= 8'd14;
send_memory[15] <= 8'd15;
send_memory[16] <= 8'd16;
send_memory[17] <= 8'd17;
send_memory[18] <= 8'd18;
send_memory[19] <= 8'd19;
send_memory[20] <= 8'd20;
send_memory[21] <= 8'd21;
send_memory[22] <= 8'd22;
send_memory[23] <= 8'd23;
send_memory[24] <= 8'd24;
send_memory[25] <= 8'd25;
send_memory[26] <= 8'd26;
send_memory[27] <= 8'd27;
send_memory[28] <= 8'd28;
send_memory[29] <= 8'd29;
send_memory[30] <= 8'd30;
send_memory[31] <= 8'd31;
end
else begin
if(clk_div > 'd200)begin
scl_clk <= ~scl_clk;
clk_div <= 'h0;
end
else
clk_div <= clk_div + 1'b1;
end
end
always @(posedge ack or negedge rst_n)begin
if(!rst_n)begin
send_count <= 'h0;
end
else begin
if((send_count < 10'd32) && (ack))begin
send_count <= send_count + 1'b1;
receive_memory[send_count] <= RD_EN ? data : 8'h0;
end
else begin
send_count <= send_count;
end
end
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <=(receive_memory[31]== 31) ? 1'b1 : 1'b0;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
WR <= 1'b0;
RD <= 1'b0;
data_reg <= 'h0;
end
else begin
if(send_count == 8'd32)begin
WR <= 1'b0;
RD <= 1'b0;
end
else begin
if(RD_EN)
RD <= 1'b1;
else if(WR_EN)begin
WR <= 1'b1;
data_reg <= send_memory[send_count];
end
end
end
end
assign data = WR_EN ? data_reg : 8'hz;
I2C_wr I2C_wr_instance(
.sda(sda),
.scl(scl),
.ack(ack),
.rst_n(rst_n),
.clk(scl_clk),
.WR(WR),
.RD(RD),
.data(data),
.maddress_sel(maddress_sel)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ben_mem.v when simulating
// the core, ben_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ben_mem(
clka,
addra,
douta
);
input clka;
input [14 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ben_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_fast_cfg_init_cntr.v
// Version : 1.3
//--
//-- Description: PCIe Fast Configuration Init Counter
//--
//------------------------------------------------------------------------------
module pcie_7x_v1_3_fast_cfg_init_cntr #(
parameter PATTERN_WIDTH = 8,
parameter INIT_PATTERN = 8'hA5,
parameter TCQ = 1
) (
input clk,
input rst,
output reg [PATTERN_WIDTH-1:0] pattern_o
);
always @(posedge clk) begin
if(rst) begin
pattern_o <= #TCQ {PATTERN_WIDTH{1'b0}};
end else begin
if(pattern_o != INIT_PATTERN) begin
pattern_o <= #TCQ pattern_o + 1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4B_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int AND = 0; const int OR = 1; const int NAND = 2; const int NOR = 3; const int N = 111; int n, m, k; string s; int a[N][3]; int b[N][3]; vector<int> g[N]; bool st[N]; int ord[N]; int ordSz; int col[N]; int C; bool used[N]; bool oldUsed[N]; long long G[N]; int readType() { cin >> s; if (s == and ) return AND; if (s == or ) return OR; if (s == nand ) return NAND; if (s == nor ) return NOR; throw; } void read() { cin >> n >> m >> k; for (int i = 0; i < m; i++) { a[i][0] = readType(); cin >> s; int p = 1; for (int j = 0; j < n; j++) { if (s[j] == x ) { a[i][p++] = j; } } } for (int i = 0; i < k; i++) { b[i][0] = readType(); cin >> s; int p = 1; for (int j = 0; j < m; j++) { if (s[j] == x ) { b[i][p++] = j; } } } } void addEdge(int v, int u) { g[v ^ 1].push_back(u); g[u ^ 1].push_back(v); } void addGraph(int v, int tp) { tp = a[v][0] ^ (tp << 1); if (tp == 0) { st[2 * a[v][1] + 1] = 1; st[2 * a[v][2] + 1] = 1; } else if (tp == 1) { addEdge(2 * a[v][1] + 1, 2 * a[v][2] + 1); } else if (tp == 2) { addEdge(2 * a[v][1], 2 * a[v][2]); } else if (tp == 3) { st[2 * a[v][1]] = 1; st[2 * a[v][2]] = 1; } } void dfsMark(int v) { used[v] = 1; for (int u : g[v]) { if (!used[u]) dfsMark(u); } } bool checkUsed() { for (int i = 0; i < n; i++) if (used[2 * i] && used[2 * i + 1]) return false; return true; } bool checkSAT(long long MASK) { for (int i = 0; i < 2 * n; i++) { g[i].clear(); st[i] = 0; used[i] = 0; } for (int i = 0; i < k; i++) { if (((MASK >> i) & 1) == 0) continue; for (int j = 1; j < 3; j++) addGraph(b[i][j], (int)(b[i][0] < 2)); } for (int i = 0; i < 2 * n; i++) if (st[i]) dfsMark(i); if (!checkUsed()) return false; for (int i = 0; i < n; i++) { if (used[2 * i] || used[2 * i + 1]) continue; for (int j = 0; j < 2 * n; j++) oldUsed[j] = used[j]; dfsMark(2 * i); if (checkUsed()) continue; for (int j = 0; j < 2 * n; j++) used[j] = oldUsed[j]; dfsMark(2 * i + 1); if (!checkUsed()) return false; } return checkUsed(); } int intVar[10]; int cntVar; bool oper(int t, bool v1, bool v2) { bool res = 0; if (t >= 2) { t ^= 2; res ^= 1; } if (t == AND) return res ^ (v1 && v2); else return res ^ (v1 || v2); } bool getValConst(int v, int MASK) { for (int i = 0; i < cntVar; i++) { if (intVar[i] == v) { return (MASK >> i) & 1; } } throw; } bool getValA1(int v, int MASK) { return oper(a[v][0], getValConst(a[v][1], MASK), getValConst(a[v][2], MASK)); } bool getValA2(int v, int MASK) { return oper(a[v][0] ^ 2, getValConst(a[v][1], MASK), getValConst(a[v][2], MASK)); } bool getValB1(int v, int MASK) { return oper(b[v][0], getValA1(b[v][1], MASK), getValA1(b[v][2], MASK)); } bool getValB2(int v, int MASK) { return oper(b[v][0] ^ 2, getValA2(b[v][1], MASK), getValA2(b[v][2], MASK)); } bool solve(int id1, int id2) { cntVar = 0; for (int i = 1; i < 3; i++) for (int j = 1; j < 3; j++) { intVar[cntVar++] = a[b[id1][i]][j]; intVar[cntVar++] = a[b[id2][i]][j]; } sort(intVar, intVar + cntVar); cntVar = unique(intVar, intVar + cntVar) - intVar; for (int MASK = 0; MASK < (1 << cntVar); MASK++) { if (getValB1(id1, MASK) && getValB2(id2, MASK)) return true; } return false; } bool isGoodMask(long long MASK) { return !checkSAT(MASK); } void eraseFromG(int v, int u) { if ((G[v] >> u) & 1) G[v] ^= 1LL << u; } int ANS = 0; void brute(int curAns, long long curMask, long long cand, long long already) { if (cand == 0) { if (isGoodMask(curMask)) ANS = max(ANS, curAns); return; } bool ok = true; for (int i = 0; ok && i < k; i++) { if (((already >> i) & 1) == 0) continue; if ((G[i] & cand) == cand) ok = false; } if (!ok) return; for (int v = 0; (1LL << v) <= cand; v++) { if (((cand >> v) & 1) == 0) continue; brute(curAns + 1, curMask | (1LL << v), (cand & G[v]) ^ (1LL << v), already & G[v]); already |= 1LL << v; cand ^= 1LL << v; } } int main() { read(); for (int i = 0; i < k; i++) G[i] = (1LL << k) - 1; for (int i = 0; i < k; i++) for (int j = 0; j < k; j++) { if (solve(i, j)) { eraseFromG(i, j); eraseFromG(j, i); } } long long all = 0; for (int i = 0; i < k; i++) { if (((G[i] >> i) & 1) == 0) continue; all |= 1LL << i; } brute(0, 0, all, 0); if (ANS == 0) cout << -1 << endl; else cout << k - ANS << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_2_V
`define SKY130_FD_SC_HD__O211AI_2_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o211ai_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_2_V
|
#include <bits/stdc++.h> using namespace std; int p, n; char arr[1002], brr[1002]; int main() { scanf( %s , arr); n = strlen(arr); for (int i = 0; i < n; i++) { if (arr[i] == . ) { p = i; } } if (arr[p - 1] == 9 ) { printf( GOTO Vasilisa. n ); } else { if (arr[p + 1] - 0 >= 5) { arr[p - 1]++; } for (int i = 0; i < p; i++) { printf( %c , arr[i]); } printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_GPIO_OVTV2_BLACKBOX_V
`define SKY130_FD_IO__TOP_GPIO_OVTV2_BLACKBOX_V
/**
* top_gpio_ovtv2: General Purpose I/0.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_gpio_ovtv2 (
OUT ,
OE_N ,
HLD_H_N ,
ENABLE_H ,
ENABLE_INP_H ,
ENABLE_VDDA_H ,
ENABLE_VDDIO ,
ENABLE_VSWITCH_H,
INP_DIS ,
VTRIP_SEL ,
HYS_TRIM ,
SLOW ,
SLEW_CTL ,
HLD_OVR ,
ANALOG_EN ,
ANALOG_SEL ,
ANALOG_POL ,
DM ,
IB_MODE_SEL ,
VINREF ,
PAD ,
PAD_A_NOESD_H ,
PAD_A_ESD_0_H ,
PAD_A_ESD_1_H ,
AMUXBUS_A ,
AMUXBUS_B ,
IN ,
IN_H ,
TIE_HI_ESD ,
TIE_LO_ESD
);
input OUT ;
input OE_N ;
input HLD_H_N ;
input ENABLE_H ;
input ENABLE_INP_H ;
input ENABLE_VDDA_H ;
input ENABLE_VDDIO ;
input ENABLE_VSWITCH_H;
input INP_DIS ;
input VTRIP_SEL ;
input HYS_TRIM ;
input SLOW ;
input [1:0] SLEW_CTL ;
input HLD_OVR ;
input ANALOG_EN ;
input ANALOG_SEL ;
input ANALOG_POL ;
input [2:0] DM ;
input [1:0] IB_MODE_SEL ;
input VINREF ;
inout PAD ;
inout PAD_A_NOESD_H ;
inout PAD_A_ESD_0_H ;
inout PAD_A_ESD_1_H ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
output IN ;
output IN_H ;
output TIE_HI_ESD ;
output TIE_LO_ESD ;
// Voltage supply signals
supply1 VDDIO ;
supply1 VDDIO_Q;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_GPIO_OVTV2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; double distance(double v, double a, double t) { return v * t + a * t * t / 2; } double time(double v, double a, double d) { return (-v + sqrt(v * v + 2 * a * d)) / a; } int main(int argc, char* argv[]) { cout.precision(16); double a, v, l, d, w; cin >> a >> v >> l >> d >> w; double t = 0; double p = (w * w + 2 * a * d) / (4 * a); if (p <= d) { if (sqrt(2 * p * a) <= v) t += sqrt(2 * p * a) / a + (sqrt(2 * p * a) - w) / a; else t += v / a + (d - distance(0, a, v / a) - distance(v, -a, max(0.0, (v - w) / a))) / v + max(0.0, (v - w) / a); if (d + distance(w, a, max(0.0, (v - w) / a)) < l) t += max(0.0, (v - w) / a) + (l - d - distance(w, a, max(0.0, (v - w) / a))) / v; else t += time(w, a, l - d); } else { if (distance(0, a, v / a) < l) t += v / a + (l - distance(0, a, v / a)) / v; else t += time(0, a, l); } cout << t << endl; return 0; }
|
#include<bits/stdc++.h> #define ll long long #define all(v) v.begin(),v.end() #define rall(v) v.rbegin(),v.rend() #define sz(x) (int)(x).size() #define PB push_back #define PI 3.1415926535897932384626433832795 #define what(x) cout<<#x<< is <<x<<endl; using namespace std; #ifdef LOCAL//ONLINE_JUDGE #include D: c_c++ template.h #else #define debug(...) 42 #endif ll powmod(ll a,ll b,ll mod) { ll res=1;a%=mod; for(;b;b>>=1){ if(b&1)res=res*a%mod; a=a*a%mod; } return res; } void solve(){ ll n,k; cin>>n>>k; if(k>=n){ cout<<k/n+((k%n)?1:0)<< n ; }else{ ll f = (n/k)*k; if(f<n)f+=k; cout<<f/n+((f%n)?1:0)<< n ; } } int main(){ ios::sync_with_stdio(false); cin.tie(0); // #ifdef LOCAL // freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); // #endif int tc=1; cin>>tc; while(tc--)solve(); }
|
#include <bits/stdc++.h> using namespace std; struct Ratio { long long p; long long q; Ratio(long long p_, long long q_) : p(p_), q(q_) {} bool operator<(const Ratio& o) const { return p * o.q < q * o.p; } bool operator>(const Ratio& o) const { return p * o.q > q * o.p; } bool operator==(const Ratio& o) const { return p * o.q == q * o.p; } }; int main() { ios_base::sync_with_stdio(false); long long x1, x2, y1, y2, n; cin >> n >> x1 >> y1 >> x2 >> y2; vector<pair<long long, long long>> r(n), v(n); for (int i = 0; i < n; ++i) { cin >> r[i].first >> r[i].second >> v[i].first >> v[i].second; } bool has_upper = false; Ratio ans_upper{0, 1}, ans_lower{0, 1}; for (int i = 0; i < n; ++i) { if (v[i].first == 0) { if (r[i].first < x1 || r[i].first > x2) { cout << -1 << n ; return 0; } } else if (v[i].first > 0) { if (x1 > r[i].first) { ans_lower = max(ans_lower, Ratio(x1 - r[i].first, v[i].first)); } if (x2 < r[i].first) { cout << -1 << n ; return 0; } if (has_upper) ans_upper = min(ans_upper, Ratio(x2 - r[i].first, v[i].first)); else ans_upper = Ratio(x2 - r[i].first, v[i].first); has_upper = true; } else { if (r[i].first < x1) { cout << -1 << n ; return 0; } if (has_upper) ans_upper = min(ans_upper, Ratio(r[i].first - x1, -v[i].first)); else ans_upper = Ratio(r[i].first - x1, -v[i].first); has_upper = true; if (r[i].first > x2) { ans_lower = max(ans_lower, Ratio(r[i].first - x2, -v[i].first)); } } if (v[i].second == 0) { if (r[i].second < y1 || r[i].second > y2) { cout << -1 << n ; return 0; } } else if (v[i].second > 0) { if (y1 > r[i].second) { ans_lower = max(ans_lower, Ratio(y1 - r[i].second, v[i].second)); } if (y2 < r[i].second) { cout << -1 << n ; return 0; } if (has_upper) ans_upper = min(ans_upper, Ratio(y2 - r[i].second, v[i].second)); else ans_upper = Ratio(y2 - r[i].second, v[i].second); has_upper = true; } else { if (r[i].second < y1) { cout << -1 << n ; return 0; } if (has_upper) ans_upper = min(ans_upper, Ratio(r[i].second - y1, -v[i].second)); else ans_upper = Ratio(r[i].second - y1, -v[i].second); has_upper = true; if (r[i].second > y2) { ans_lower = max(ans_lower, Ratio(r[i].second - y2, -v[i].second)); } } if (has_upper && !(ans_lower < ans_upper)) { cout << -1 << n ; return 0; } } for (int i = 0; i < n; ++i) { if (v[i].first == 0 && (r[i].first == x1 || r[i].first == x2)) { cout << -1 << n ; return 0; } if (v[i].second == 0 && (r[i].second == y1 || r[i].second == y2)) { cout << -1 << n ; return 0; } } cout << fixed << setprecision(9) << (ans_lower.p + 0.0) / ans_lower.q << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_TB_V
`define SKY130_FD_SC_HDLL__SDFRBP_TB_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfrbp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_TB_V
|
// Simplistic packetizer mod supporting circular buffer
// The mod relies on following RAM writer module address rolling over
// The paketizer lets through data to RAM writer untill trigger signal,
// then lets through cfg_data number of beats and stops
// The start position is recorded
// Requirement: trigger signal transisions once and stays true
// CNTR_WIDTH*AXIS_TDATA_WIDTH must equal writer's ADDR_WIDTH*clogb2((AXI_DATA_WIDTH/8)-1)
`timescale 1 ns / 1 ps
module axis_circular_packetizer #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32,
parameter CONTINUOUS = "FALSE",
parameter NON_BLOCKING = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
output wire [CNTR_WIDTH-1:0] trigger_pos,
input wire trigger,
output wire enabled,
output wire complete,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast
);
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next, int_trigger_pos, int_trigger_pos_next;
reg int_enbl_reg, int_enbl_next;
reg int_complete_reg, int_complete_next;
wire int_comp_wire, int_tvalid_wire, int_tlast_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_trigger_pos <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_complete_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_trigger_pos <= int_trigger_pos_next;
int_enbl_reg <= int_enbl_next;
int_complete_reg <= int_complete_next;
end
end
assign int_comp_wire = int_cntr_reg < cfg_data;
assign int_tvalid_wire = int_enbl_reg & s_axis_tvalid;
assign int_tlast_wire = ~int_comp_wire;
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS_LABEL
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
int_complete_next = int_complete_reg;
int_trigger_pos_next = int_trigger_pos;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
end
end
else
begin : STOP
always @*
begin
int_cntr_next = int_cntr_reg;
int_trigger_pos_next = int_trigger_pos;
int_enbl_next = int_enbl_reg;
int_complete_next = int_complete_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_comp_wire)
begin
if(trigger)
int_cntr_next = int_cntr_reg + 1'b1;
else
int_trigger_pos_next = int_trigger_pos + 1'b1;
end
if(m_axis_tready & int_tvalid_wire & int_tlast_wire)
begin
int_enbl_next = 1'b0;
int_complete_next = 1'b1;
end
end
end
endgenerate
if(NON_BLOCKING == "TRUE")
assign s_axis_tready = ~int_enbl_reg | m_axis_tready;
else
assign s_axis_tready = int_enbl_reg & m_axis_tready;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tvalid = int_tvalid_wire;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
assign trigger_pos = int_trigger_pos;
assign enabled = int_enbl_reg;
assign complete = int_complete_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct yy { int id, val; } f[8000]; int a[8000], p[8000][2], d[8000]; bool b[8000]; bool cmp(yy x, yy y) { return x.val > y.val; } int main() { int i, j, n, m, t, x; bool tm; scanf( %d%d , &n, &m); for (i = 1; i <= 2 * n; ++i) { scanf( %d , &f[i].val); f[i].id = i; a[i] = f[i].val; } sort(f + 1, f + 1 + 2 * n, cmp); for (i = 1; i <= m; ++i) { scanf( %d%d , &p[i][0], &p[i][1]); d[p[i][0]] = p[i][1]; d[p[i][1]] = p[i][0]; } scanf( %d , &t); if (t == 1) { for (i = 1; i <= m; ++i) { if (a[p[i][0]] > a[p[i][1]]) { printf( %d n , p[i][0]); fflush(stdout); b[p[i][0]] = 1; } else { printf( %d n , p[i][1]); fflush(stdout); b[p[i][1]] = 1; } scanf( %d , &x); b[x] = 1; } for (i = 1; i <= 2 * n; ++i) { if (!b[f[i].id]) { printf( %d n , f[i].id); fflush(stdout); b[f[i].id] = 1; scanf( %d , &x); b[x] = 1; } } } else { for (i = 1; i <= n; ++i) { scanf( %d , &x); b[x] = 1; if (d[x] && !b[d[x]]) { printf( %d n , d[x]); fflush(stdout); b[d[x]] = 1; } else { tm = 0; for (j = 1; j <= m; ++j) if (!b[p[j][0]]) { if (a[p[j][0]] > a[p[j][1]]) { printf( %d n , p[j][0]); fflush(stdout); b[p[j][0]] = 1; tm = 1; break; } else { printf( %d n , p[j][1]); fflush(stdout); b[p[j][1]] = 1; tm = 1; break; } } if (!tm) for (j = 1; j <= 2 * n; ++j) if (!b[f[j].id]) { printf( %d n , f[j].id); fflush(stdout); b[f[j].id] = 1; break; } } } } return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
out_port,
readdata
)
;
output irq;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input [ 31: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire [ 31: 0] data_in;
reg [ 31: 0] data_out;
wire irq;
reg [ 31: 0] irq_mask;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
wire wr_strobe;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({32 {(address == 0)}} & data_in) |
({32 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign wr_strobe = chipselect && ~write_n;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (clk_en)
if (wr_strobe)
data_out <= (address == 5)? data_out & ~writedata[31 : 0]: (address == 4)? data_out | writedata[31 : 0]: (address == 0)? writedata[31 : 0]: data_out;
end
assign out_port = data_out;
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[31 : 0];
end
assign irq = |(data_in & irq_mask);
endmodule
|
// UC Berkeley CS250
// Authors: Ryan Thornton ()
// Arya Reais-Parsi ()
///////// BASIC LUT /////////
// Assumptions:
// MEM_SIZE is a multiple of CONFIG_WIDTH
module lut #(
parameter INPUTS=4, MEM_SIZE=1<<INPUTS, CONFIG_WIDTH=8
) (
// IO
input [INPUTS-1:0] addr,
output out,
// Stream Style Configuration
input config_clk,
input config_en,
input [CONFIG_WIDTH-1:0] config_in,
output [CONFIG_WIDTH-1:0] config_out
);
reg [MEM_SIZE-1:0] mem = 0;
assign out = mem[addr];
// Stream Style Configuration Logic
generate
genvar i;
for (i=1; i<(MEM_SIZE/CONFIG_WIDTH); i=i+1) begin
always @(posedge config_clk) begin
if (config_en)
mem[(i+1)*CONFIG_WIDTH-1:i*CONFIG_WIDTH] <= mem[(i)*CONFIG_WIDTH-1:(i-1)*CONFIG_WIDTH];
end
end
always @(posedge config_clk) begin
if (config_en) begin
mem[CONFIG_WIDTH-1:0] <= config_in;
end
end
assign config_out = mem[MEM_SIZE-1:MEM_SIZE-CONFIG_WIDTH];
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_mem.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_mem (/*AUTOARG*/
// Outputs
que_mem_data, listen_out,
// Inputs
que_mem_addr, dram_cpu_wr_addr, dram_cpu_wr_data, dram_clk, clk,
dram_cpu_wr_en, margin, sehold, mem_bypass
);
// DRAM memory compiler interface.
output [255:0] que_mem_data;
output [64:0] listen_out;
// Inputs
input [4:0] que_mem_addr; // read enable(bit[4]) + addr(bit3-bit0)
input [3:0] dram_cpu_wr_addr;
input [63:0] dram_cpu_wr_data;
input dram_clk;
input clk;
input [3:0] dram_cpu_wr_en;
input [4:0] margin;
input sehold;
input mem_bypass;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
wire temp0;
wire temp1;
wire temp2;
wire temp3;
wire si;
wire [64:0] listen_out1;
wire [64:0] listen_out2;
wire [64:0] listen_out3;
// DRAM Write Data queue - using Memory Compiler
// 64 bit word X 32 entries X 4 instances
// Need to run at 700 MHZ SS, 840 MHZ TT
// Dual ported instances
// Port A is the Write port and port B is the Read port Always
/*bw_rf_16x65 AUTO_TEMPLATE(
// OUTPUTS
.do ({temp@, que_mem_data[@"(+ (* (% @ 4) 64) 63)":@"(* (% @ 4) 64)"]}),
// INPUTS
.rd_a (que_mem_addr[3:0]),
.wr_a (dram_cpu_wr_addr[3:0]),
.di ({1'b0, dram_cpu_wr_data[63:0]}),
.rd_clk (dram_clk),
.wr_clk (clk),
.hold (sehold),
.scan_en (1'b0),
.csn_rd (que_mem_addr[4]),
.csn_wr (dram_cpu_wr_en[@"(% @ 4)"]),
.testmux_sel (mem_bypass),
.oen (1'b0));
*/
// Bank0 data buffer
bw_rf_16x65 dramdatawrqent0b01(/*AUTOINST*/
// Outputs
.so (so),
.do ({temp0, que_mem_data[63:0]}), // Templated
.listen_out(listen_out[64:0]),
// Inputs
.rd_clk (dram_clk), // Templated
.wr_clk (clk), // Templated
.csn_rd (que_mem_addr[4]), // Templated
.csn_wr (dram_cpu_wr_en[0]), // Templated
.hold (sehold), // Templated
.testmux_sel(mem_bypass), // Templated
.scan_en (1'b0), // Templated
.margin (margin[4:0]),
.rd_a (que_mem_addr[3:0]), // Templated
.wr_a (dram_cpu_wr_addr[3:0]), // Templated
.di ({1'b0, dram_cpu_wr_data[63:0]}), // Templated
.si (si));
/*bw_rf_16x65 AUTO_TEMPLATE(
// OUTPUTS
.do ({temp@, que_mem_data[@"(+ (* (% @ 4) 64) 63)":@"(* (% @ 4) 64)"]}),
// INPUTS
.rd_a (que_mem_addr[3:0]),
.wr_a (dram_cpu_wr_addr[3:0]),
.di ({1'b0, dram_cpu_wr_data[63:0]}),
.rd_clk (dram_clk),
.wr_clk (clk),
.csn_rd (que_mem_addr[4]),
.hold (sehold),
.scan_en (1'b0),
.csn_wr (dram_cpu_wr_en[@"(% @ 4)"]),
.testmux_sel (mem_bypass),
.oen (1'b0));
*/
bw_rf_16x65 dramdatawrqent1b01(/*AUTOINST*/
// Outputs
.so (so),
.do ({temp1, que_mem_data[127:64]}), // Templated
.listen_out(listen_out1[64:0]),
// Inputs
.rd_clk (dram_clk), // Templated
.wr_clk (clk), // Templated
.csn_rd (que_mem_addr[4]), // Templated
.csn_wr (dram_cpu_wr_en[1]), // Templated
.hold (sehold), // Templated
.testmux_sel(mem_bypass), // Templated
.scan_en (1'b0), // Templated
.margin (margin[4:0]),
.rd_a (que_mem_addr[3:0]), // Templated
.wr_a (dram_cpu_wr_addr[3:0]), // Templated
.di ({1'b0, dram_cpu_wr_data[63:0]}), // Templated
.si (si));
bw_rf_16x65 dramdatawrqent2b01(/*AUTOINST*/
// Outputs
.so (so),
.do ({temp2, que_mem_data[191:128]}), // Templated
.listen_out(listen_out2[64:0]),
// Inputs
.rd_clk (dram_clk), // Templated
.wr_clk (clk), // Templated
.csn_rd (que_mem_addr[4]), // Templated
.csn_wr (dram_cpu_wr_en[2]), // Templated
.hold (sehold), // Templated
.testmux_sel(mem_bypass), // Templated
.scan_en (1'b0), // Templated
.margin (margin[4:0]),
.rd_a (que_mem_addr[3:0]), // Templated
.wr_a (dram_cpu_wr_addr[3:0]), // Templated
.di ({1'b0, dram_cpu_wr_data[63:0]}), // Templated
.si (si));
/*bw_rf_16x65 AUTO_TEMPLATE(
// OUTPUTS
.do ({temp@, que_mem_data[@"(+ (* (% @ 4) 64) 63)":@"(* (% @ 4) 64)"]}),
// INPUTS
.rd_a (que_mem_addr[3:0]),
.wr_a (dram_cpu_wr_addr[3:0]),
.di ({1'b0, dram_cpu_wr_data[63:0]}),
.rd_clk (dram_clk),
.wr_clk (clk),
.hold (sehold),
.scan_en (1'b0),
.csn_rd (que_mem_addr[4]),
.csn_wr (dram_cpu_wr_en[@"(% @ 4)"]),
.testmux_sel (mem_bypass),
.oen (1'b0));
*/
bw_rf_16x65 dramdatawrqent3b01(/*AUTOINST*/
// Outputs
.so (so),
.do ({temp3, que_mem_data[255:192]}), // Templated
.listen_out(listen_out3[64:0]),
// Inputs
.rd_clk (dram_clk), // Templated
.wr_clk (clk), // Templated
.csn_rd (que_mem_addr[4]), // Templated
.csn_wr (dram_cpu_wr_en[3]), // Templated
.hold (sehold), // Templated
.testmux_sel(mem_bypass), // Templated
.scan_en (1'b0), // Templated
.margin (margin[4:0]),
.rd_a (que_mem_addr[3:0]), // Templated
.wr_a (dram_cpu_wr_addr[3:0]), // Templated
.di ({1'b0, dram_cpu_wr_data[63:0]}), // Templated
.si (si));
endmodule // dram_mem
// Local Variables:
// verilog-library-directories:("." "../../srams/rtl")
// End:
|
#include <bits/stdc++.h> using namespace std; long long N = 1e7 + 5; std::vector<long long> v(N, 0); std::vector<long long> p; void sieve() { for (long long i = 2; i < N; i++) { if (v[i] != 0) continue; p.push_back(i); for (long long j = 2 * i; j < N; j += i) v[j] = 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; long long cnt = 0; for (long long i = 2; i <= (long long)sqrt(n); i++) if (n % i == 0) cnt++; v[0] = 1; v[1] = 1; if (cnt == 0) { cout << 1 << n ; cout << n; return 0; } sieve(); long long bal = 0; if (n % 2 == 0) bal = 2; else bal = 3; long long temp = n - bal; if (n == 4) { cout << 2 << n << 2 << << 2; return 0; } for (long long i = 0; i < p.size(); i++) { cnt = 0; for (long long j = 2; temp - p[i] > 0 and j <= (long long)sqrt(temp - p[i]); j++) { if ((temp - p[i]) % j == 0) { cnt = 1; break; } } if (!cnt) { cout << 3 << n << bal << << p[i] << << temp - p[i]; return 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1 >> s2; if (s2.size() > s1.size()) swap(s1, s2); int x = s1.size() - s2.size(); for (int i = 0; i < s1.size() && i < s2.size(); ++i) { if (s1[s1.size() - i - 1] != s2[s2.size() - i - 1]) { x = s1.size() - i + s2.size() - i; break; } } cout << x << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_BLACKBOX_V
/**
* top_power_lvc_wpad: A power pad with an ESD low-voltage clamp.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_lvc_wpad (
P_PAD ,
AMUXBUS_A ,
AMUXBUS_B ,
SRC_BDY_LVC1,
SRC_BDY_LVC2,
OGC_LVC ,
DRN_LVC1 ,
BDY2_B2B ,
DRN_LVC2 ,
P_CORE ,
VDDIO ,
VDDIO_Q ,
VDDA ,
VCCD ,
VSWITCH ,
VCCHIB ,
VSSA ,
VSSD ,
VSSIO_Q ,
VSSIO
);
inout P_PAD ;
inout AMUXBUS_A ;
inout AMUXBUS_B ;
inout SRC_BDY_LVC1;
inout SRC_BDY_LVC2;
inout OGC_LVC ;
inout DRN_LVC1 ;
inout BDY2_B2B ;
inout DRN_LVC2 ;
inout P_CORE ;
inout VDDIO ;
inout VDDIO_Q ;
inout VDDA ;
inout VCCD ;
inout VSWITCH ;
inout VCCHIB ;
inout VSSA ;
inout VSSD ;
inout VSSIO_Q ;
inout VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_LVC_WPAD_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { int a, i, temp; long long int sum = 0, n, fra; cin >> a; for (i = 2; i <= a - 1; i++) { temp = a; while (temp > 0) { sum += temp % i; temp = temp / i; } } temp = a - 2; fra = gcd(sum, temp); while (fra != 1) { sum = sum / fra; temp = temp / fra; fra = gcd(sum, temp); } cout << sum << / << temp << endl; }
|
// mbt 9-7-14
//
// bsg_sbox
//
// The switchbox concentrates working channel signals to reduce
// the complexity of downstream logic.
//
// the one_hot_p option selectively uses one-hot muxes,
// pipelining the mux decode logic at the expensive of
// energy and area.
//
// pipeline_indir_p and pipeline_outdir_p add
// pipelining (two element fifos) in each direction
//
// NB: An implementation based on Benes networks could potentially
// use less area, at the cost of complexity and wire congestion.
//
`include "bsg_defines.v"
module bsg_sbox
#(parameter `BSG_INV_PARAM( num_channels_p )
, parameter `BSG_INV_PARAM(channel_width_p )
, parameter pipeline_indir_p = 0
, parameter pipeline_outdir_p = 0
, parameter one_hot_p = 1
)
(input clk_i
, input reset_i
, input calibration_done_i
// which channels are active
, input [num_channels_p-1:0] channel_active_i
// unconcentrated to concentrated
, input [num_channels_p-1:0 ] in_v_i
, input [channel_width_p-1:0] in_data_i [num_channels_p-1:0]
, output [num_channels_p-1:0 ] in_yumi_o
, output [num_channels_p-1:0 ] in_v_o
, output [channel_width_p-1:0] in_data_o [num_channels_p-1:0]
, input [num_channels_p-1:0 ] in_yumi_i
// concentrated to unconcentrated
, input [num_channels_p-1:0 ] out_me_v_i
, input [channel_width_p-1:0] out_me_data_i [num_channels_p-1:0]
, output [num_channels_p-1:0 ] out_me_ready_o
, output [num_channels_p-1:0 ] out_me_v_o
, output [channel_width_p-1:0] out_me_data_o [num_channels_p-1:0]
, input [num_channels_p-1:0 ] out_me_ready_i
);
logic [`BSG_SAFE_CLOG2(num_channels_p)*num_channels_p-1:0] fwd_sel , fwd_dpath_sel
,fwd_sel_r, fwd_dpath_sel_r;
logic [`BSG_SAFE_CLOG2(num_channels_p)*num_channels_p-1:0] bk_sel , bk_dpath_sel
,bk_sel_r, bk_dpath_sel_r;
genvar i,j;
bsg_scatter_gather #(.vec_size_lp(num_channels_p)) bsg
(.vec_i(channel_active_i)
,.fwd_o (fwd_sel )
,.fwd_datapath_o(fwd_dpath_sel)
,.bk_o (bk_sel )
,.bk_datapath_o (bk_dpath_sel )
);
always @(posedge clk_i)
begin
fwd_sel_r <= fwd_sel;
fwd_dpath_sel_r <= fwd_dpath_sel;
bk_sel_r <= bk_sel;
bk_dpath_sel_r <= bk_dpath_sel;
end
wire [num_channels_p-1:0 ] in_v_o_int;
wire [channel_width_p-1:0] in_data_o_int [num_channels_p-1:0];
wire [num_channels_p-1:0 ] in_yumi_i_int;
wire [num_channels_p-1:0 ] out_me_v_i_int;
wire [channel_width_p-1:0] out_me_data_i_int [num_channels_p-1:0];
wire [num_channels_p-1:0 ] out_me_ready_o_int;
for (i = 0; i < num_channels_p; i = i + 1)
begin : sbox
if (one_hot_p)
begin : fi1hot
logic [num_channels_p-1:0][num_channels_p-1:0] fwd_sel_one_hot_r;
always @(posedge clk_i)
fwd_sel_one_hot_r[i] <= (1 << fwd_sel[i*`BSG_SAFE_CLOG2(num_channels_p)+:`BSG_SAFE_CLOG2(num_channels_p)]);
assign in_v_o_int[i] = |(in_v_i & fwd_sel_one_hot_r[i]);
end
else
assign in_v_o_int[i]
= in_v_i [fwd_sel_r[i*`BSG_SAFE_CLOG2(num_channels_p)+:`BSG_SAFE_CLOG2(num_channels_p)]];
assign in_yumi_o[i]
= in_yumi_i_int[bk_sel_r[i*`BSG_SAFE_CLOG2(num_channels_p)+:`BSG_SAFE_CLOG2(num_channels_p)]];
// shift forward data over to exclude data that cannot be selected
wire [channel_width_p-1:0] forward [num_channels_p-i-1:0];
for (j = 0; j < num_channels_p - i; j++)
begin
assign forward[j] = in_data_i[i+j];
end
assign in_data_o_int[i]
= forward[fwd_dpath_sel_r[(i*`BSG_SAFE_CLOG2(num_channels_p))+:`BSG_SAFE_CLOG2(num_channels_p)]];
assign out_me_v_o[i]
= out_me_v_i_int [bk_sel_r[(i*`BSG_SAFE_CLOG2(num_channels_p))+:`BSG_SAFE_CLOG2(num_channels_p)]];
assign out_me_ready_o_int[i]
= out_me_ready_i[fwd_sel_r[(i*`BSG_SAFE_CLOG2(num_channels_p))+:`BSG_SAFE_CLOG2(num_channels_p)]];
// shift backward data over to exclude data that cannot be selected
wire [channel_width_p-1:0] backward [i+1-1:0];
for (j = 0; j <= i; j++)
begin : rofj
assign backward[j] = out_me_data_i_int[j];
end
assign out_me_data_o[i]
= backward[bk_dpath_sel_r[(i*`BSG_SAFE_CLOG2(num_channels_p))+:`BSG_SAFE_CLOG2(num_channels_p)]];
if (pipeline_indir_p)
begin :pipe_in
wire ready_int;
assign in_yumi_i_int[i] = ready_int & in_v_o_int[i];
bsg_two_fifo #(.width_p(channel_width_p)) infifo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(ready_int)
,.data_i(in_data_o_int[i])
,.v_i (in_v_o_int [i] & calibration_done_i)
,.v_o (in_v_o [i])
,.data_o(in_data_o [i])
,.yumi_i(in_yumi_i [i])
);
end
else
begin : pipe_in
// default: route signals out
assign in_v_o [i] = in_v_o_int [i];
assign in_data_o [i] = in_data_o_int[i];
assign in_yumi_i_int[i] = in_yumi_i [i];
end
if (pipeline_outdir_p)
begin : pipe_out
bsg_two_fifo #(.width_p(channel_width_p)) outfifo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ready_o(out_me_ready_o [i])
,.data_i(out_me_data_i [i])
,.v_i (out_me_v_i [i] & calibration_done_i)
,.v_o (out_me_v_i_int [i])
,.data_o(out_me_data_i_int [i])
,.yumi_i(out_me_ready_o_int [i] & out_me_v_i_int[i])
);
end
else
begin : pipe_out
// default: route signals out
assign out_me_v_i_int [i] = out_me_v_i [i];
assign out_me_data_i_int [i] = out_me_data_i [i];
assign out_me_ready_o [i] = out_me_ready_o_int [i];
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_sbox)
//
// end SBOX
// *********************************************************************
|
#include <bits/stdc++.h> using namespace std; long long int n, a[100] = {}, r = 0, s = 0, m; int main() { ios_base::sync_with_stdio(0); for (long long int i = 1; i <= 5; i++) { cin >> m; a[m]++; s += m; if (a[m] == 2 || a[m] == 3) r = max(r, m * a[m]); } cout << s - r; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int nax = 2e5; int par[nax], dp[nax]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; map<int, int> prev; int ma = -1, mai; for (int i = 0; i < n; i++) { int a; cin >> a; dp[i] = 1; par[i] = -1; if (prev.count(a - 1)) { par[i] = prev[a - 1]; dp[i] = dp[prev[a - 1]] + 1; } if (dp[i] > ma) { ma = dp[i]; mai = i; } prev[a] = i; } cout << ma << endl; int p = mai; vector<int> path; while (p != -1) { path.push_back(p); p = par[p]; } reverse(path.begin(), path.end()); for (int i : path) cout << i + 1 << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll inf = 1e18; const int N = 2 * 1e5 + 10; ll res; ll a[N]; void solve() { ll n, k; cin >> n >> k; if (n == 1) { cout << 0 << n ; return; } if (n == 2) { cout << k << n ; return; } cout << 2 * k << n ; } int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ll t = 1; cin >> t; while (t--) { solve(); } }
|
/*
* Copyright (c) 2014 CERN
* @author Maciej Suminski <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Test for VPI functions handling dynamic arrays
module main();
initial
begin
int int_darray[];
real real_darray[];
bit [63:0] bit_darray[];
string string_darray[];
int_darray = new[4];
int_darray = '{1, 2, 3, 4};
$display_array(int_darray);
$increase_array_vals(int_darray);
real_darray = new[2];
real_darray = '{2.2, 2.3};
$increase_array_vals(real_darray);
$display_array(real_darray);
bit_darray = new[4];
bit_darray = '{64'hdeadbeefcafebabe, 64'h0badc0dec0dec0de,
64'h0123456789abcdef, 64'hfedcba9876543210};
$increase_array_vals(bit_darray);
$display_array(bit_darray);
string_darray = new[4];
string_darray = '{"test string", "another one", "yet one more", "the last one"};
$increase_array_vals(string_darray);
$display_array(string_darray);
end
endmodule
|
//-----------------------------------------------------------------------------
// Title : 10/100/1G Ethernet FIFO for 8-bit client I/F
// Project : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper
// File : eth_fifo_8.v
// Version : 1.8
//-----------------------------------------------------------------------------
//
// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
// The top level wrapper consists of individual fifos on the
// transmitter path and on the receiver path.
//
// Each path consists of an 8 bit local link to 8 bit client
// interface FIFO.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module eth_fifo_8
(
// Transmit FIFO MAC TX Interface
tx_clk, // MAC transmit clock
tx_reset, // Synchronous reset (tx_clk)
tx_enable, // Clock enable for tx_clk
tx_data, // Data to MAC transmitter
tx_data_valid, // Valid signal to MAC transmitter
tx_ack, // Ack signal from MAC transmitter
tx_underrun, // Underrun signal to MAC transmitter
tx_collision, // Collsion signal from MAC transmitter
tx_retransmit, // Retransmit signal from MAC transmitter
// Transmit FIFO Local-link Interface
tx_ll_clock, // Local link write clock
tx_ll_reset, // synchronous reset (tx_ll_clock)
tx_ll_data_in, // Data to Tx FIFO
tx_ll_sof_in_n, // sof indicator to FIFO
tx_ll_eof_in_n, // eof indicator to FIFO
tx_ll_src_rdy_in_n, // src ready indicator to FIFO
tx_ll_dst_rdy_out_n, // dst ready indicator from FIFO
tx_fifo_status, // FIFO memory status
tx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO MAC RX Interface
rx_clk, // MAC receive clock
rx_reset, // Synchronous reset (rx_clk)
rx_enable, // Clock enable for rx_clk
rx_data, // Data from MAC receiver
rx_data_valid, // Valid signal from MAC receiver
rx_good_frame, // Good frame indicator from MAC receiver
rx_bad_frame, // Bad frame indicator from MAC receiver
rx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO Local-link Interface
rx_ll_clock, // Local link read clock
rx_ll_reset, // synchronous reset (rx_ll_clock)
rx_ll_data_out, // Data from Rx FIFO
rx_ll_sof_out_n, // sof indicator from FIFO
rx_ll_eof_out_n, // eof indicator from FIFO
rx_ll_src_rdy_out_n, // src ready indicator from FIFO
rx_ll_dst_rdy_in_n, // dst ready indicator to FIFO
rx_fifo_status // FIFO memory status
);
//---------------------------------------------------------------------------
// Define Interface Signals
//---------------------------------------------------------------------------
parameter FULL_DUPLEX_ONLY = 0;
// Transmit FIFO MAC TX Interface
input tx_clk;
input tx_reset;
input tx_enable;
output [7:0] tx_data;
output tx_data_valid;
input tx_ack;
output tx_underrun;
input tx_collision;
input tx_retransmit;
// Transmit FIFO Local-link Interface
input tx_ll_clock;
input tx_ll_reset;
input [7:0] tx_ll_data_in;
input tx_ll_sof_in_n;
input tx_ll_eof_in_n;
input tx_ll_src_rdy_in_n;
output tx_ll_dst_rdy_out_n;
output [3:0] tx_fifo_status;
output tx_overflow;
// Receive FIFO MAC RX Interface
input rx_clk;
input rx_reset;
input rx_enable;
input [7:0] rx_data;
input rx_data_valid;
input rx_good_frame;
input rx_bad_frame;
output rx_overflow;
// Receive FIFO Local-link Interface
input rx_ll_clock;
input rx_ll_reset;
output [7:0] rx_ll_data_out;
output rx_ll_sof_out_n;
output rx_ll_eof_out_n;
output rx_ll_src_rdy_out_n;
input rx_ll_dst_rdy_in_n;
output [3:0] rx_fifo_status;
assign tx_underrun = 1'b0;
// Transmitter FIFO
defparam tx_fifo_i.FULL_DUPLEX_ONLY = FULL_DUPLEX_ONLY;
tx_client_fifo_8 tx_fifo_i (
.rd_clk (tx_clk),
.rd_sreset (tx_reset),
.rd_enable (tx_enable),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_ack (tx_ack),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit),
.overflow (tx_overflow),
.wr_clk (tx_ll_clock),
.wr_sreset (tx_ll_reset),
.wr_data (tx_ll_data_in),
.wr_sof_n (tx_ll_sof_in_n),
.wr_eof_n (tx_ll_eof_in_n),
.wr_src_rdy_n (tx_ll_src_rdy_in_n),
.wr_dst_rdy_n (tx_ll_dst_rdy_out_n),
.wr_fifo_status (tx_fifo_status)
);
// Receiver FIFO
rx_client_fifo_8 rx_fifo_i (
.wr_clk (rx_clk),
.wr_enable (rx_enable),
.wr_sreset (rx_reset),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_good_frame (rx_good_frame),
.rx_bad_frame (rx_bad_frame),
.overflow (rx_overflow),
.rd_clk (rx_ll_clock),
.rd_sreset (rx_ll_reset),
.rd_data_out (rx_ll_data_out),
.rd_sof_n (rx_ll_sof_out_n),
.rd_eof_n (rx_ll_eof_out_n),
.rd_src_rdy_n (rx_ll_src_rdy_out_n),
.rd_dst_rdy_n (rx_ll_dst_rdy_in_n),
.rx_fifo_status (rx_fifo_status)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt Zdiv_def ZBinary ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see file Zdiv_def.
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Zmod a (Zabs b).
Definition div a b := (Zsgn b) * (Zdiv a (Zabs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod : forall a b, b<>0 ->
a = b*(div a b) + modulo a b.
Proof.
intros a b Hb. unfold div, modulo.
rewrite Zmult_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos : forall a b, b<>0 ->
0 <= modulo a b < Zabs b.
Proof.
intros a b Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos : forall a b, 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros a b _ Hb. rewrite <- (Z.abs_eq b) at 3 by z_order.
apply mod_always_pos. z_order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e9 + 7; map<long long, long long> factorize(long long n) { map<long long, long long> ans; for (long long i = 2; i * i <= n; i++) { while (n % i == 0) { ans[i]++; n /= i; } } if (n > 1) { ans[n]++; n = 1; } return ans; } void FAST() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } long long binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } int main() { FAST(); long long t; cin >> t; while (t--) { long long x; cin >> x; long long y; cin >> y; long long k; cin >> k; long long reqy = y * k; if ((k * (y + 1) - 1) % (x - 1)) { cout << (k * (y + 1) - 1) / (x - 1) + k + 1 << n ; } else cout << (k * (y + 1) - 1) / (x - 1) + k << n ; } }
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_interrupt.v
// Title : Interrupt logic
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_interrupt (
// ----- Inputs -------
clk_i,
rst_i,
// From external devices
interrupt_n,
// From pipeline
stall_x,
`ifdef CFG_DEBUG_ENABLED
non_debug_exception,
debug_exception,
`else
exception,
`endif
eret_q_x,
`ifdef CFG_DEBUG_ENABLED
bret_q_x,
`endif
csr,
csr_write_data,
csr_write_enable,
// ----- Outputs -------
interrupt_exception,
// To pipeline
csr_read_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [interrupts-1:0] interrupt_n; // Interrupt pins, active-low
input stall_x; // Stall X pipeline stage
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception; // Non-debug related exception has been raised
input debug_exception; // Debug-related exception has been raised
`else
input exception; // Exception has been raised
`endif
input eret_q_x; // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x; // Return from breakpoint
`endif
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output interrupt_exception; // Request to raide an interrupt exception
wire interrupt_exception;
output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
reg [`LM32_WORD_RNG] csr_read_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
reg ie; // Interrupt enable
reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
reg [interrupts-1:0] ip; // Interrupt pending
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted (active-low) or are already pending
assign asserted = ip | ~interrupt_n;
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
`LM32_CSR_IM: csr_read_data = im;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
else
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
endgenerate
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= #1 `FALSE;
eie <= #1 `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= #1 `FALSE;
`endif
im <= #1 {interrupts{1'b0}};
ip <= #1 {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= #1 asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= #1 ie;
ie <= #1 `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= #1 ie;
ie <= #1 `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= #1 ie;
ie <= #1 `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= #1 eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= #1 bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= #1 csr_write_data[0];
eie <= #1 csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= #1 csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= #1 csr_write_data[interrupts-1:0];
if (csr == `LM32_CSR_IP)
ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= #1 `FALSE;
eie <= #1 `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= #1 `FALSE;
`endif
ip <= #1 {interrupts{1'b0}};
end
else
begin
// Set IP bit when interrupt line is asserted
ip <= #1 asserted;
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= #1 ie;
ie <= #1 `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= #1 ie;
ie <= #1 `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= #1 ie;
ie <= #1 `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= #1 eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= #1 bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if (csr == `LM32_CSR_IE)
begin
ie <= #1 csr_write_data[0];
eie <= #1 csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= #1 csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IP)
ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
end
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; struct info { long long fs, sm, id; } bd[100001]; int cmp(info a, info b) { return a.fs < b.fs; } int main() { ios_base::sync_with_stdio(0); long long int i, j, x, n, cnt = 0, m, y, k, ans = 0, cf, cm, a, rr1 = 0, l, r, md, r1, r2, xxx, flg; cin >> n >> a >> cf >> cm >> m; long long in[n + 1], bs[n + 1]; for (i = 1; i <= n; i++) { cin >> in[i]; bd[i].fs = a - in[i]; bd[i].id = i; bs[i] = a - in[i]; } sort(bd + 1, bd + 1 + n, cmp); sort(bs + 1, bs + 1 + n); for (i = 2; i <= n; i++) { bd[i].fs += bd[i - 1].fs; } bd[n].sm = 0; for (i = n - 1; i >= 1; i--) { x = abs(in[bd[i + 1].id] - in[bd[i].id]); bd[i].sm = bd[i + 1].sm + x * (n - i); } bd[0].fs = bd[0].id = 0; bd[0].sm = (a - in[bd[1].id]) * n + bd[1].sm; for (i = 1; i <= n; i++) { if (bs[i] > 0) break; cnt++; } ans = cnt * cf + cm * in[bd[n].id]; for (i = n; i >= 0; i--) { x = m; y = cnt * cf; rr1 = cnt; flg = 0; if (x >= bd[i].fs) { flg = 1; y = i * cf; x -= bd[i].fs; rr1 = i; } l = i; r = n; while (r - l > 1) { md = (l + r) / 2; if (bd[md].sm > x) l = md; else r = md; } if (bd[l].sm <= x && i != 0) r = l; x -= bd[r].sm; if (r == i && flg) { if (i == n) { y = a * cm + n * cf; if (ans <= y) { ans = y; r1 = n; r2 = n + 1; } } else { y += cm * (min(a, in[bd[r].id] + x / (n - r))); if (ans <= y) { ans = y; r1 = i; xxx = min(a, in[bd[r].id] + x / (n - r)); r2 = i + 1; } } continue; } if (r - 1 > 0) y += cm * (min(a, min(in[bd[r - 1].id], in[bd[r].id] + x / (n - r + 1)))); else y += cm * (min(a, in[bd[r].id] + x / (n - r + 1))); if (y >= ans) { ans = y; r1 = rr1; r2 = r; if (r - 1 > 0) xxx = min(a, min(in[bd[r - 1].id], in[bd[r].id] + x / (n - r + 1))); else xxx = min(a, in[bd[r].id] + x / (n - r + 1)); } } for (i = 1; i <= r1; i++) { in[bd[i].id] = a; } for (i = r2; i <= n; i++) { in[bd[i].id] = xxx; } cout << ans << endl; for (i = 1; i <= n; i++) cout << in[i] << ; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n, m, s[N], t[N], nxt[N]; int kmp() { for (int i = 1, j = 0; i < n; i++) { while (j && s[i] != s[j]) j = nxt[j]; nxt[i + 1] = s[i] == s[j] ? ++j : 0; } int cnt = 0; for (int i = 0, j = 0; i < m; i++) { while (j && s[j] != t[i]) j = nxt[j]; if (t[i] == s[j] && ++j == n) { j = nxt[j]; cnt++; } } return cnt; } int main() { scanf( %d%d , &m, &n); if (n == 1) return printf( %d n , m), 0; for (int i = 0; i < m; i++) { scanf( %d , &t[i]); if (i) t[i - 1] = t[i] - t[i - 1]; } for (int i = 0; i < n; i++) { scanf( %d , &s[i]); if (i) s[i - 1] = s[i] - s[i - 1]; } n--, m--; printf( %d n , kmp()); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int T; cin>>T; while(T--) { string S; cin>>S; long long int A[100]; long long int x=0; long long int val=0; long long int N=S.length(); long long int first,mid,last; A[0]=0;A[1]=0;A[2]=0; string str= ; for(long long int i=0;i<N;i++) { char c; c=S[i]; if(c== ? ) A[x]++; else { str+=c; x++; } } // cout<<A[0]<< <<A[1]<< <<A[2]<<endl; if(str== () ) { val=1; } else if(str== )( ) { if((A[0]>=1)&&(A[2]>=1)) { val=1; } } if(val==0) cout<< NO <<endl; else if(val==1&&(N%2==0)) cout<< YES <<endl; else cout<< NO <<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int sz = 1e5 + 50; map<int, int> prime, mark; void init() { prime[2] = 1; int limit = sqrt(sz) + 1; for (int i = 3; i <= sz; i += 2) { if (!mark[i]) { prime[i] = 1; if (i <= limit) { for (int j = i * i; j <= sz; j += i * 2) mark[j] = 1; } } } } int main() { init(); int n, a; scanf( %d , &n); int o = 0, t = 0; while (n--) { scanf( %d , &a); a == 1 ? o++ : t++; } int sum = 0; vector<int> v; while (t || o) { if (o > 0 && prime[sum + 1]) { o--; sum += 1; v.push_back(1); } else if (t > 0 && prime[sum + 2]) { t--; sum += 2; v.push_back(2); } else { if (t) sum += 2, t--, v.push_back(2); else sum++, o--, v.push_back(1); } } for (auto i : v) printf( %d , i); printf( n ); }
|
#include <bits/stdc++.h> using namespace std; int n, a[25], d[25][25], f[1 << 25], ans = INT_MAX; int popcnt(int x) { int cnt = 0; while (x > 0) cnt += (x & 1), x >>= 1; return cnt; } int main() { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; for (int j = 0; j < i; ++j) d[i][j] = -1; for (int j = 0; j < i; ++j) for (int k = j; k < i; ++k) if (a[j] + a[k] == a[i]) d[i][j] = k, d[i][k] = j; } f[1] = true; for (int i = 1; i < n; ++i) for (int j = 1 << (i - 1); j < (1 << i); ++j) if (f[j] == true) for (int k = 0; k < i; ++k) if (j & (1 << k) && d[i][k] >= 0 && (j & (1 << d[i][k]))) { for (int l = 0; l <= i; ++l) f[(j & (~(1 << l))) | (1 << i)] = true; break; } for (int i = 1 << (n - 1); i < (1 << n); ++i) if (f[i] == true) ans = min(ans, popcnt(i)); if (ans == INT_MAX) cout << -1; else cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; string str; cin >> str; int overlap = -1; int max = -1; for (int i = 1; i < n; ++i) { if (str[i] == str[0]) { int j = 0; for (j = 0; i + j < n; ++j) { if (str[i + j] == str[j]) continue; break; } if (i + j == n && j > max) { overlap = i; max = j; } } } string firstHalf = ; string secondHalf = str; if (overlap != -1) { firstHalf = str.substr(0, overlap); secondHalf = str.substr(overlap); long long secondLen = secondHalf.length(); firstHalf = str.substr(0, secondLen); secondHalf = str.substr(secondLen); } for (int x = 0; x < k; ++x) { if (x == 0) cout << str; else cout << secondHalf; } cout << endl; return 0; }
|
/*
* This is a post-synthesis test for the blif_shift.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif_shift.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif_shift_tb.v foo.v
* $ vvp foo.vvp
*/
module main;
parameter W=3;
reg [W:0] D;
reg [W:0] S;
parameter WO=5;
wire [WO:0] SHL;
wire [WO:0] SHR;
wire [WO:0] ASHL;
wire [WO:0] ASHR;
reg [WO:0] shl;
reg [WO:0] shr;
reg [WO:0] ashl;
reg [WO:0] ashr;
`ifdef DUMMY
shift ss(.D (D), .S (S), .SHL (SHL), .SHR (SHR), .ASHL (ASHL), .ASHR (ASHR));
`else
shift ss(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
.\S[3] (S[3]), .\S[2] (S[2]), .\S[1] (S[1]), .\S[0] (S[0]),
.\SHL[5] (SHL[5]), .\SHL[4] (SHL[4]), .\SHL[3] (SHL[3]), .\SHL[2] (SHL[2]), .\SHL[1] (SHL[1]), .\SHL[0] (SHL[0]),
.\SHR[5] (SHR[5]), .\SHR[4] (SHR[4]), .\SHR[3] (SHR[3]), .\SHR[2] (SHR[2]), .\SHR[1] (SHR[1]), .\SHR[0] (SHR[0]),
.\ASHL[5] (ASHL[5]), .\ASHL[4] (ASHL[4]), .\ASHL[3] (ASHL[3]), .\ASHL[2] (ASHL[2]), .\ASHL[1] (ASHL[1]), .\ASHL[0] (ASHL[0]),
.\ASHR[5] (ASHR[5]), .\ASHR[4] (ASHR[4]), .\ASHR[3] (ASHR[3]), .\ASHR[2] (ASHR[2]), .\ASHR[1] (ASHR[1]), .\ASHR[0] (ASHR[0]));
`endif
int ddx;
int sdx;
initial begin
for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1)
for (sdx = 0 ; sdx < WO + 2 ; sdx = sdx+1) begin
D = ddx[W:0];
S = sdx[W:0];
shl = D << S;
shr = D >> S;
ashl = $signed(D) <<< S;
ashr = $signed(D) >>> S;
// $display("D = %b, S = %b", D, S);
// $display("shl = %b, shr = %b", shl, shr);
// $display("ashl = %b, ashr = %b", ashl, ashr);
#1;
if (SHL !== shl) begin
$display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, SHL, shl);
$finish;
end
if (SHR !== shr) begin
$display("FAILED -- D=%b, S=%b, SHR=%b (should be %b)", D, S, SHR, shr);
$finish;
end
if (ASHL !== ashl) begin
$display("FAILED -- D=%b, S=%b, ASHL=%b (should be %b)", D, S, ASHL, ashl);
$finish;
end
if (ASHR !== ashr) begin
$display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, ASHR, ashr);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; long double dp[4005][4005]; long double absf(long double a) { if (a < 0) return a * (-1); return a; } long double solve(vector<long double> &a, long long idx, long long left) { if (idx >= a.size()) return left == 0 ? 0 : 100000; if (dp[idx][left] != -100000) { return dp[idx][left]; } long double cur_up = ceil(a[idx]); long double cur_down = floor(a[idx]); if (left > 0) { long double pt1 = a[idx] - cur_down + solve(a, idx + 1, left - 1); long double pt2 = a[idx] - cur_up + solve(a, idx + 1, left); if (absf(pt1) < absf(pt2)) { return dp[idx][left] = pt1; } else { return dp[idx][left] = pt2; } } else { long double pt2 = a[idx] - cur_up + solve(a, idx + 1, left); return dp[idx][left] = pt2; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; vector<long double> a; for (long long i = 0; i < 2 * n; i++) { long double temp; cin >> temp; a.push_back(temp); } for (long long i = 0; i < 4005; i++) { for (long long j = 0; j < 4005; j++) { dp[i][j] = -100000; } } long double res = abs(solve(a, 0, n)); cout << fixed << setprecision(3); cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int cnt[1 << 14]; signed main() { ios_base ::sync_with_stdio(false); cin.tie(0); int n, k, maxn = 0; cin >> n >> k; for (int i = 0; i < n; ++i) { int a; cin >> a; maxn = max(maxn, a); ++cnt[a]; } long long ans = 0; if (k == 0) { for (int i = 0; i <= maxn; ++i) ans += cnt[i] * (cnt[i] - 1LL) / 2; cout << ans << n ; return 0; } int l = 32 - __builtin_clz(max(1, maxn)); for (int i = 0; i < (1 << l); ++i) { if (__builtin_popcount(i) != l - k) continue; for (int j = 0; j <= maxn; ++j) ans += 1LL * cnt[j] * cnt[(j & i) | (~j & ~i & ((1 << l) - 1))]; } cout << ans / 2 << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_2_V
`define SKY130_FD_SC_HDLL__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_2 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_2 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k = 0; cin >> n; vector<int> adj[n]; for (int i = 1, u, v; i < n; i++) { cin >> u >> v; u--; v--; adj[u].push_back(v); adj[v].push_back(u); k = max(k, max((int)adj[u].size(), (int)adj[v].size()) + 1); } cout << k << endl; int nd_clr[n], prnt[n]; queue<int> Q; Q.push(0); nd_clr[0] = 0; prnt[0] = 0; while (!Q.empty()) { int u = Q.front(); Q.pop(); int clr = nd_clr[u]; for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v != prnt[u]) { int c = (clr + 1) % k; if (c == nd_clr[prnt[u]]) c = (c + 1) % k; nd_clr[v] = c; clr = c; prnt[v] = u; Q.push(v); } } } for (int i = 0; i < n; i++) cout << nd_clr[i] + 1 << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int sl = s.length(); pair<int, int> a[26] = {}; for (int i = 0; i < 26; i++) a[i].second = i + a ; for (int i = 0; i < sl; i++) a[s[i] - a ].first++; sort(a, a + 26, greater<pair<int, int> >()); string ans(sl, ? ); bool valid = false; for (int i = 1; i < sl / 2; i++) ans[i] = a[0].second, a[0].first--; for (int i = sl / 2; i < sl; i++) { int sq = sqrt(i + 1); bool ok = false; for (int j = 2; j <= sq; j++) ok |= ((i + 1) % j == 0); if (ok) ans[i] = a[0].second, a[0].first--; } if (a[0].first >= 0) { string rem = ; for (int i = 0; i < 26; i++) while (a[i].first--) rem.push_back(a[i].second); for (int i = 0, j = 0; i < sl; i++) if (ans[i] == ? ) { ans[i] = rem[j]; j++; } valid = true; } if (valid == false) cout << NO n ; else cout << YES n << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void split(string &s, vector<string> &v, string &sep) { int current, previous = 0; current = s.find_first_of(sep); while (current != string::npos) { v.push_back(s.substr(previous, current - previous)); previous = current + 1; current = s.find_first_of(sep, previous); } v.push_back(s.substr(previous, current - previous)); } int main() { int n, flag = 0; cin >> n; for (int i = 0; i < n; i++) { int temp; cin >> temp; if (temp) { flag = 1; } } if (flag) { cout << HARD ; cout << endl; } else { cout << EASY ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int mult(int a, int b, int p = 1000000007) { return ((a % p) * (b % p)) % p; } int multbig(int a, int b, int mod) { if (a == 0 or b == 0) return 0; if (a == 1 or b == 1) return (a * b) % mod; int cur = multbig(a, b / 2, mod); cur = (2 * cur) % mod; if (b % 2) cur = (cur + a) % mod; return cur; } int add(int a, int b, int p = 1000000007) { return (a % p + b % p) % p; } int fpow(int n, int k, int p = 1000000007) { int r = 1; for (; k; k >>= 1LL) { if (k & 1LL) r = mult(r, n, p); n = mult(n, n, p); } return r; } int inv(int a, int p = 1000000007) { return fpow(a, p - 2, p); } int inv_euclid(int a, int m = 1000000007) { int m0 = m; int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { int q = a / m; int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } vector<pair<int, int>> vvv; pair<int, int> aa[200003]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < (int)m; i++) { int p, q; cin >> p >> q; if (p > q) { swap(p, q); } aa[i].first = p; aa[i].second = q; vvv.push_back(make_pair(p, q)); } sort(vvv.begin(), vvv.end()); int f = 0; for (int i = 2; i <= n; i++) { if (n % i == 0) { int lol = n / i; vector<pair<int, int>> vv; for (int i = 0; i < (int)m; i++) { int p = aa[i].first + lol; int q = aa[i].second + lol; if (p > n) { p = p - n; } if (q > n) { q = q - n; } if (p > q) { swap(p, q); } vv.push_back(make_pair(p, q)); } sort(vv.begin(), vv.end()); if (vv == vvv) { f = 1; break; } } } if (f) { cout << Yes n ; } else cout << No n ; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07:56:48 06/02/2013
// Design Name:
// Module Name: rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rom ( input [7:0] addr,output reg [15:0] dout );
always @ (addr)
case (addr)
8'b0000_0000: dout = 16'b0111_0000_0001_0111; ///addi r1,r0,#7;
8'b0000_0001: dout = 16'b1000_0001_0010_0010; //Subi r2,r1,#2
8'b0000_0010: dout = 16'b1010_0000_0010_0000; //store [r0],r2
8'b0000_0011: dout = 16'b1001_0000_0011_0000; //load r3 [r0]
8'b0000_0100: dout = 16'b0001_0001_0010_0100; //add r4,r1,r2
8'b0000_0101: dout = 16'b0010_0100_0010_0101; //Sub r5,r4,r2
8'b0000_0110: dout = 16'b1100_0000_0101_0001; //stori [1],$r5;
8'b0000_0111: dout = 16'b1011_0000_0110_0001; //loadi r6,[1];
8'b0000_1000: dout = 16'b0101_0100_0111_0011; //SHL r7, r4,#3
8'b0000_1001: dout = 16'b0110_0100_1000_0010; //SHR r8,r4,#2
8'b0000_1010: dout = 16'b0011_0100_0001_1001; //AND R9, R4, R1;
8'b0000_1011: dout = 16'b0100_0100_0010_1010; //OR R10, R4, R2;
8'b0000_1100: dout = 16'b1101_0110_0101_0111; //Bre Jump R10, R4, R2;
8'b0000_1101: dout = 16'b0000_0000_0000_0000; //Halt
default: dout = 16'h0000;
endcase
endmodule
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0_M_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
// Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT = 32
)
(
// Users to add ports here
input wire [7:0] FrameSize,
input wire En,
// User ports ends
// Do not modify the ports beyond this line
// Global ports
input wire M_AXIS_ACLK,
//
input wire M_AXIS_ARESETN,
// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
output wire M_AXIS_TVALID,
// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
// TLAST indicates the boundary of a packet.
output wire M_AXIS_TLAST,
// TREADY indicates that the slave can accept a transfer in the current cycle.
input wire M_AXIS_TREADY
);
// sample generator -counter
reg [C_M_AXIS_TDATA_WIDTH-1 : 0] counterR;
assign M_AXIS_TDATA = counterR;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
// counter R circuit
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
counterR<=0;
end
else begin
if( M_AXIS_TVALID && M_AXIS_TREADY)
counterR<= counterR+1;
end
// wait for counter number of clock cycle after reset
reg sampleGeneratorEnR;
reg [7:0] afterResetCycleCounterR;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
sampleGeneratorEnR<= 0;
afterResetCycleCounterR<=0;
end
else begin
afterResetCycleCounterR <= afterResetCycleCounterR + 1;
if(afterResetCycleCounterR == C_M_START_COUNT)
sampleGeneratorEnR <= 1;
end
// M_AXIS_TVALID circuit
reg tValidR;
assign M_AXIS_TVALID = tValidR;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
tValidR<= 0;
end
else begin
if(!En)
tValidR<=0;
else if (sampleGeneratorEnR)
tValidR <= 1;
end
// M_AXIS_TLAST ckt
reg [7:0] packetCounter;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
packetCounter <= 8'hff ;
end
else begin
if(M_AXIS_TVALID && M_AXIS_TREADY ) begin
if(packetCounter== (FrameSize - 1 ))
packetCounter <= 8'hff;
else
packetCounter <= packetCounter + 1;
// end
end
end
assign M_AXIS_TLAST = (packetCounter == (FrameSize -1 )) ?1:0;
//end of custom module now!
endmodule
|
`default_nettype none
module pic(
//System
input wire iCLOCK,
input wire inRESET,
/****************************************
System Infomation
****************************************/
output wire oSYSINFO_IOSR_VALID,
output wire [31:0] oSYSINFO_IOSR, //IO Start Address
/****************************************
IO - CPU Connection
****************************************/
//Req
input wire iIO_REQ,
output wire oIO_BUSY,
input wire [1:0] iIO_ORDER, //if (!iIO_RW && iIO_ORDER!=2'h2) then Alignment Fault
input wire iIO_RW, //0=Write 1=Read
input wire [31:0] iIO_ADDR,
input wire [31:0] iIO_DATA,
//Output
output wire oIO_VALID,
input wire iIO_BUSY,
output wire [31:0] oIO_DATA,
//Interrupt
output wire oIO_INTERRUPT_VALID,
output wire [5:0] oIO_INTERRUPT_NUM,
input wire iIO_INTERRUPT_ACK,
/****************************************
To DPS Connection
****************************************/
//Request
output wire oDPS_REQ, //Input
input wire iDPS_BUSY,
output wire oDPS_RW, //0=Read : 1=Write
output wire [31:0] oDPS_ADDR,
output wire [31:0] oDPS_DATA,
//Return
input wire iDPS_REQ, //Output
output wire oDPS_BUSY,
input wire [31:0] iDPS_DATA,
//Interrupt
input wire iDPS_IRQ_REQ,
input wire [5:0] iDPS_IRQ_NUM,
output wire oDPS_IRQ_ACK,
/****************************************
To GCI Connection
****************************************/
//Request
output wire oGCI_REQ, //Input
input wire iGCI_BUSY,
output wire oGCI_RW, //0=Read : 1=Write
output wire [31:0] oGCI_ADDR,
output wire [31:0] oGCI_DATA,
//Return
input wire iGCI_REQ, //Output
output wire oGCI_BUSY,
input wire [31:0] iGCI_DATA,
//Interrupt
input wire iGCI_IRQ_REQ,
input wire [5:0] iGCI_IRQ_NUM,
output wire oGCI_IRQ_ACK
);
/******************************************************************************************
Assign
******************************************************************************************/
//GCI SIze
//wire [32:0] gci_use_size;
//IRQ Controll
reg b_irq_state;
reg b_irq_gci_ack_mask;
reg b_irq_dps_ack_mask;
//CPU2IO State
reg b_cpu_error; //<- Interrupt Triger
reg b_cpu_req;
reg b_cpu_rw;
reg [31:0] b_cpu_addr;
reg [31:0] b_cpu_data;
//GCI Use Size Controllor
reg [1:0] b_iosize_state;
reg b_iosize_gci_size_valid;
reg [31:0] b_iosize_gci_size;
/******************************************************************************************
IOSR
******************************************************************************************/
//assign gci_use_size = 33'h100000000 - b_iosize_gci_size;
assign oSYSINFO_IOSR_VALID = b_iosize_gci_size_valid;
//assign oSYSINFO_IOSR = (b_iosize_gci_size_valid)? gci_use_size[31:0] + 32'h00000200 : 32'h00000000;
assign oSYSINFO_IOSR = ~(b_iosize_gci_size[31:0] + 32'h00000200) + 32'h1;//(b_iosize_gci_size_valid)? 33'h100000000 - (b_iosize_gci_size[31:0] + 32'h00000200) : 32'h00000000;
/******************************************************************************************
IRQ Controll
******************************************************************************************/
localparam L_PARAM_IRQ_STT_IDLE = 1'b0;
localparam L_PARAM_IRQ_STT_ACK_WAIT = 1'b1;
//Interrupt Controllor
assign oGCI_IRQ_ACK = b_irq_gci_ack_mask && iIO_INTERRUPT_ACK;
assign oDPS_IRQ_ACK = b_irq_dps_ack_mask && iIO_INTERRUPT_ACK;
assign oIO_INTERRUPT_VALID = (b_irq_state == L_PARAM_IRQ_STT_IDLE)? (iGCI_IRQ_REQ || iDPS_IRQ_REQ) : 1'b0;
assign oIO_INTERRUPT_NUM = (iGCI_IRQ_REQ)? iGCI_IRQ_NUM + 6'h4 : iDPS_IRQ_NUM;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
b_irq_gci_ack_mask <= 1'b0;
b_irq_dps_ack_mask <= 1'b0;
end
else begin
case(b_irq_state)
L_PARAM_IRQ_STT_IDLE:
begin
b_irq_gci_ack_mask <= 1'b0;
b_irq_dps_ack_mask <= 1'b0;
if(iGCI_IRQ_REQ)begin
b_irq_state <= L_PARAM_IRQ_STT_ACK_WAIT;
b_irq_gci_ack_mask <= iGCI_IRQ_REQ;
end
else if(iDPS_IRQ_REQ)begin
b_irq_state <= L_PARAM_IRQ_STT_ACK_WAIT;
b_irq_dps_ack_mask <= iDPS_IRQ_REQ;
end
end
L_PARAM_IRQ_STT_ACK_WAIT:
begin
if(iIO_INTERRUPT_ACK)begin
b_irq_state <= L_PARAM_IRQ_STT_IDLE;
end
end
endcase
end
end
/******************************************************************************************
CPU
******************************************************************************************/
//CPU -> IO Buffer & Error Check
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_cpu_error <= 1'b0;
b_cpu_req <= 1'b0;
b_cpu_rw <= 1'b0;
b_cpu_addr <= {32{1'b0}};
b_cpu_data <= {32{1'b0}};
end
else begin
if(!iGCI_BUSY || !iDPS_BUSY)begin
//Error Check
if(iIO_REQ && iIO_ORDER != 2'h2 && !iIO_RW)begin
b_cpu_error <= 1'b1;
b_cpu_req <= 1'b0;
b_cpu_rw <= 1'b0;
b_cpu_addr <= {32{1'b0}};
b_cpu_data <= {32{1'b0}};
end
else begin
b_cpu_error <= 1'b0;
b_cpu_req <= iIO_REQ;
b_cpu_rw <= iIO_RW;
b_cpu_addr <= iIO_ADDR;
b_cpu_data <= iIO_DATA;
end
end
end
end
/******************************************************************************************
GCI
******************************************************************************************/
//GCI Use Size Controllor
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_iosize_state <= 2'h0;
b_iosize_gci_size_valid <= 1'b0;
b_iosize_gci_size <= {32{1'b0}};
end
else begin
case(b_iosize_state)//synthesis parallel_case full_case
2'h0: //IDLE
begin
if(!iGCI_BUSY)begin
b_iosize_state <= 2'h1;
end
end
2'h1: //REQUEST
begin
if(!iGCI_BUSY)begin
b_iosize_state <= 2'h2;
end
end
2'h2: //WAIT
begin
if(iGCI_REQ)begin
b_iosize_state <= 2'h3;
b_iosize_gci_size_valid <= 1'b1;
b_iosize_gci_size <= iGCI_DATA;
end
end
2'h3: //INITIAL_END
begin
b_iosize_gci_size_valid <= b_iosize_gci_size_valid;
b_iosize_gci_size <= b_iosize_gci_size;
end
endcase
end
end
/******************************************************************************************
Assign
******************************************************************************************/
//Connect (This -> CPU)
assign oIO_BUSY = iGCI_BUSY || iDPS_BUSY || !b_iosize_gci_size_valid/*Initial END*/;
assign oIO_VALID = (b_iosize_state == 2'h3)? iGCI_REQ || iDPS_REQ : 1'b0;
assign oIO_DATA = (iGCI_REQ)? iGCI_DATA : iDPS_DATA;
wire device_select = (b_cpu_addr >= 32'h00000200)? 1'b1 : 1'b0;
//DPS
assign oDPS_REQ = b_cpu_req && !device_select;
assign oDPS_RW = (b_iosize_state == 2'h1)? 1'b0 : b_cpu_rw;
assign oDPS_ADDR = (b_iosize_state == 2'h1)? 32'h4 : b_cpu_addr;
assign oDPS_DATA = (b_iosize_state == 2'h1)? 32'h0 : b_cpu_data;
assign oDPS_BUSY = (b_iosize_state == 2'h1)? 1'b0 : iIO_BUSY;
//Connection (This -> GCI)
assign oGCI_REQ = b_iosize_state == 2'h1 || b_cpu_req && device_select;
assign oGCI_RW = (b_iosize_state == 2'h1)? 1'b0 : b_cpu_rw;
assign oGCI_ADDR = (b_iosize_state == 2'h1)? 32'h4 : b_cpu_addr - 32'h00000200;
assign oGCI_DATA = (b_iosize_state == 2'h1)? 32'h0 : b_cpu_data;
assign oGCI_BUSY = (b_iosize_state == 2'h1)? 1'b0 : iIO_BUSY;
//Connection (This -> CPU)
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int d = 0, tot = 0, c; bool flag = false; for (int i = 0; i < n; i++) { cin >> c; tot = tot + c; if (tot >= 8 && flag == false) { k = k - 8; tot = tot - 8; d++; if (k <= 0) flag = true; } else if (tot < 8 && flag == false) { k = k - tot; tot = 0; d++; if (k <= 0) flag = true; } } if (flag == true) { cout << d << endl; } else { cout << -1 << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; char s; int rock[4][2]; int k = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> s; if (s == * ) { rock[k][0] = i; rock[k][1] = j; k++; } } if (rock[0][0] == rock[1][0]) rock[3][0] = rock[2][0]; if (rock[0][0] == rock[2][0]) rock[3][0] = rock[1][0]; if (rock[2][0] == rock[1][0]) rock[3][0] = rock[0][0]; if (rock[0][1] == rock[1][1]) rock[3][1] = rock[2][1]; if (rock[0][1] == rock[2][1]) rock[3][1] = rock[1][1]; if (rock[2][1] == rock[1][1]) rock[3][1] = rock[0][1]; cout << rock[3][0] + 1 << << rock[3][1] + 1; cin >> n; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[20][5000 + 5]; vector<pair<int, int> > e[20][5000 + 5]; int vis[20][5000 + 5]; int n[5000 + 5]; long long sum[20]; vector<pair<int, int> > cycle[5000 * 15 + 5]; int N; vector<int> bit[(1 << 15) + 5]; pair<int, int> sta[5000 * 15 + 5]; int top; int dp[(1 << 15) + 5]; void dfs(int i, int j) { vis[i][j] = 1; sta[++top] = make_pair(i, j); if (e[i][j].size()) { assert(e[i][j].size() == 1); int x = e[i][j][0].first; int y = e[i][j][0].second; if (vis[x][y] == 0) dfs(x, y); else if (vis[x][y] == 1) { int t = top; vector<pair<int, int> > tmp; do { tmp.push_back(sta[t]); } while (sta[t--] != make_pair(x, y)); int f = 1; int b[20] = {}; for (auto it : tmp) if (++b[it.first] > 1) f = 0; if (f) cycle[++N] = tmp; } } top--; vis[i][j] = 2; } int main() { int k; scanf( %d , &k); long long S = 0; for (int i = 1; i <= k; i++) { scanf( %d , &n[i]); for (int j = 1; j <= n[i]; j++) { scanf( %d , &a[i][j]); sum[i] += a[i][j]; S += a[i][j]; } sort(a[i] + 1, a[i] + 1 + n[i]); } if (S % k != 0) { puts( No ); return 0; } S /= k; for (int i = 1; i <= k; i++) { long long diff = S - sum[i]; for (int j = 1; j <= n[i]; j++) { long long f = a[i][j] + diff; for (int c = 1; c <= k; c++) { if (c == i && diff != 0) continue; int id = lower_bound(a[c] + 1, a[c] + n[c] + 1, f) - a[c]; if (a[c][id] == f) { e[i][j].push_back(make_pair(c, id)); } } } } for (int i = 1; i <= k; i++) for (int j = 1; j <= n[i]; j++) if (vis[i][j] == 0) dfs(i, j); for (int i = 1; i <= N; i++) { int b = 0; for (auto it : cycle[i]) b |= 1 << it.first - 1; bit[b].push_back(i); } memset(dp, -1, sizeof dp); dp[0] = 0; for (int s = 0; s <= (1 << k) - 1; s++) { for (int t = s; t; t = (t - 1) & s) if (bit[t].size() && dp[s ^ t] != -1) { dp[s] = t; break; } } if (dp[(1 << k) - 1] != -1) { vector<int> ans; int s = (1 << k) - 1; while (s) { ans.push_back(bit[dp[s]][0]); s = s ^ dp[s]; } int id1[20] = {}, id2[20] = {}; for (auto id : ans) { int L = cycle[id].size(); for (int i = 0; i <= L - 1; i++) { id1[cycle[id][i].first] = cycle[id][i].second; id2[cycle[id][i].first] = cycle[id][(i + 1) % L].first; } } puts( Yes ); for (int i = 1; i <= k; i++) printf( %d %d n , a[i][id1[i]], id2[i]); } else puts( No ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b; cin >> a >> b; long long ans = 0; while (true) { if (!a || !b) { cout << ans; return 0; } if (a == b || (a % b == 0)) { cout << (a / b + ans); return 0; } if (a > b) { long long tmp = a / b; a -= tmp * b; ans += tmp; } else { long long tmp = b / a; b -= tmp * a; ans += tmp; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; string ans = ; int f; if (a > b) { ans += 0 ; a--; f = 0; } else { ans += 1 ; f = 1; b--; } for (int i = 1; i < c; i++) { if (f) { ans += 0 ; a--; f = f ^ 1; } else { ans += 1 ; b--; f = f ^ 1; } } if (!f) { while (a--) { ans += 0 ; } f = f ^ 1; while (b--) { ans += 1 ; } } else { while (b--) { ans += 1 ; } while (a--) { ans += 0 ; } } cout << ans << endl; }
|
/* Top level module for button demo without debouncing
(not a good way of doing things!)
This uses button 1 of the keypad when installed correctly.
*/
module top (
// input hardware clock (12 MHz)
hwclk,
// LED
led1,
// Keypad lines
keypad_r1,
keypad_c1,
);
/* Clock input */
input hwclk;
/* LED outputs */
output led1;
/* Numpad I/O */
output keypad_r1=0;
input keypad_c1;
/* LED register */
reg ledval = 1'b0;
/* Numpad pull-up settings for columns:
PIN_TYPE: <output_type=0>_<input=1>
PULLUP: <enable=1>
PACKAGE_PIN: <user pad name>
D_IN_0: <internal pin wire (data in)>
*/
wire keypad_c1_din;
SB_IO #(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
) keypad_c1_config (
.PACKAGE_PIN(keypad_c1),
.D_IN_0(keypad_c1_din)
);
/* LED Wiring */
assign led1=ledval;
/* Toggle LED when button [1] pressed */
always @ (negedge keypad_c1_din) begin
ledval = ~ledval;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const long long mod = 1e9 + 7; int n, c[505], d[505][505], fa[505], a[505]; long long dp[505][505], comb[505][505]; int Find(int x) { return x == fa[x] ? x : fa[x] = Find(fa[x]); } void Union(int u, int v) { int x = Find(u); int y = Find(v); if (x != y) fa[x] = y; } int is(int i, int j) { long long x = 1LL * a[i] * a[j]; long long y = sqrt(1.0 * x); if (y * y == x) return 1; return 0; } int main() { for (int j = 0; j < 505; j++) comb[0][j] = 0; for (int i = 0; i < 505; i++) comb[i][0] = 1; for (int i = 1; i < 505; i++) for (int j = 1; j < 505; j++) comb[i][j] = (comb[i - 1][j - 1] + comb[i - 1][j]) % mod; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); memset(d, 0, sizeof(d)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) continue; if (is(i, j)) d[i][j] = 1; } } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) if (d[i][k]) for (int j = 1; j <= n; j++) d[i][j] = d[i][j] || d[k][j]; for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i == j) continue; if (d[i][j]) Union(i, j); } } vector<int> g[505]; for (int i = 1; i <= n; i++) g[Find(i)].push_back(i); int cnt = 0; for (int i = 1; i <= n; i++) if (g[i].size() != 0) c[++cnt] = g[i].size(); int N = cnt; dp[0][0] = 1; int all = 1; for (int x = 1; x <= N; x++) { for (int ij = 1; ij <= c[x]; ij++) { for (int y = 0; y <= all; y++) { if (dp[x - 1][y] > 0) { for (int j = 0; j <= min(ij, y); j++) { int i = ij - j; int z = all - y; long long add = dp[x - 1][y] * comb[y][j] % mod; add = add * comb[z][i] % mod; add = add * comb[c[x] - 1][ij - 1] % mod; dp[x][(y - j) + (c[x] - ij)] = (dp[x][(y - j) + (c[x] - ij)] + add) % mod; } } } } all += c[x]; } long long ans = dp[N][0]; for (int i = 1; i <= N; i++) { long long tmp = 1LL; for (int j = 1; j <= c[i]; j++) tmp = tmp * j % mod; ans = ans * tmp % mod; } printf( %I64d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; string rotate(string s) { for (int i = 1; i <= 3; i++) { swap(s[i - 1], s[i]); } return s; } string rotate2(string s) { swap(s[0], s[4]); swap(s[2], s[4]); swap(s[2], s[5]); return s; } string solve(string s) { string ans = s; for (int i = 0; i < 2; i++) { for (int j = 0; j < 4; j++) { for (int k = 0; k < 4; k++) { s = rotate(s); ans = min(ans, s); } s = rotate2(s); } s = rotate(s); } return ans; } int main() { string s; cin >> s; set<string> st; sort(s.begin(), s.end()); do { st.insert(solve(s)); } while (next_permutation(s.begin(), s.end())); cout << st.size() << endl; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:13:25 03/11/2015
// Design Name: counter
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/counter/tb_counter.v
// Project Name: counter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_counter #(
parameter MODULUS = 10,
parameter WIDTH = $clog2(MODULUS)
);
wire clk;
wire[WIDTH - 1:0] data;
counter_gen_test
generator (
.clk(clk)
);
counter #(
.WIDTH(WIDTH),
.MODULUS(MODULUS)
)
uut (
.ce(1'b1),
.clr(1'b0),
.clk(clk),
.out(data)
);
counter_check_test #(
.WIDTH(WIDTH),
.MODULUS(MODULUS)
)
checker (
.in(data)
);
endmodule
|
module note2dds(clk, note, adder);
input wire clk;
input wire [8:0] note; // запас 2 бита. то есть нота не до 127, а до 512!
output [31:0] adder;
reg [31:0] adder_tbl [15:0];
reg [3:0] addr;
reg [3:0] divider;
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator
//; Add input / 64 to accumulator
initial begin
addr <= 4'd0;
divider <= 4'd0;
adder_tbl[ 4'd0] <= 32'd0368205249;
adder_tbl[ 4'd1] <= 32'd0390099873;
adder_tbl[ 4'd2] <= 32'd0413296419;
adder_tbl[ 4'd3] <= 32'd0437872302;
adder_tbl[ 4'd4] <= 32'd0463909545;
adder_tbl[ 4'd5] <= 32'd0491495042;
adder_tbl[ 4'd6] <= 32'd0520720858;
adder_tbl[ 4'd7] <= 32'd0551684531;
adder_tbl[ 4'd8] <= 32'd0584489400;
adder_tbl[ 4'd9] <= 32'd0619244949;
adder_tbl[ 4'd10] <= 32'd0656067170;
adder_tbl[ 4'd11] <= 32'd0695078954;
adder_tbl[4'd12] <= 32'd0;
adder_tbl[4'd13] <= 32'd0;
adder_tbl[4'd14] <= 32'd0;
adder_tbl[4'd15] <= 32'd0;
end
assign adder = adder_tbl[addr] >> divider;
wire [5:0] diap = (note < 12) ? 6'd00 :
(note < 24) ? 6'd01 :
(note < 36) ? 6'd02 :
(note < 48) ? 6'd03 :
(note < 60) ? 6'd04 :
(note < 72) ? 6'd05 :
(note < 84) ? 6'd06 :
(note < 96) ? 6'd07 :
(note < 108) ? 6'd08 :
(note < 120) ? 6'd09 :
(note < 132) ? 6'd10 :
(note < 144) ? 6'd11 :
(note < 156) ? 6'd12 :
(note < 168) ? 6'd13 :
(note < 180) ? 6'd14 :
(note < 192) ? 6'd15 :
(note < 204) ? 6'd16 :
(note < 216) ? 6'd17 :
(note < 228) ? 6'd18 :
(note < 240) ? 6'd19 :
(note < 252) ? 6'd20 :
(note < 264) ? 6'd21 :
(note < 276) ? 6'd22 :
(note < 288) ? 6'd23 :
(note < 300) ? 6'd24 :
(note < 312) ? 6'd25 :
(note < 324) ? 6'd26 :
(note < 336) ? 6'd27 :
(note < 348) ? 6'd28 :
(note < 360) ? 6'd29 :
(note < 372) ? 6'd30 :
(note < 384) ? 6'd31 :
(note < 396) ? 6'd32 :
(note < 408) ? 6'd33 :
(note < 420) ? 6'd34 :
(note < 432) ? 6'd35 :
(note < 444) ? 6'd36 :
(note < 456) ? 6'd37 :
(note < 468) ? 6'd38 :
(note < 480) ? 6'd39 :
(note < 492) ? 6'd40 :
(note < 504) ? 6'd41 : 6'd042 ;
wire [6:0] c_addr = note - (diap * 4'd012);
always @ (posedge clk) begin
addr <= c_addr[3:0];
divider <= 6'd042 - diap;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_TB_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv5sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_TB_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: rep_jbi_sc0_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module rep_jbi_sc0_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_buf, scbuf_jbi_data_buf, jbi_scbuf_ecc_buf,
jbi_sctag_req_vld_buf, scbuf_jbi_ctag_vld_buf,
scbuf_jbi_ue_err_buf, sctag_jbi_iq_dequeue_buf,
sctag_jbi_wib_dequeue_buf, sctag_jbi_por_req_buf,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req
);
output [31:0] jbi_sctag_req_buf;
output [31:0] scbuf_jbi_data_buf;
output [6:0] jbi_scbuf_ecc_buf;
output jbi_sctag_req_vld_buf;
output scbuf_jbi_ctag_vld_buf;
output scbuf_jbi_ue_err_buf;
output sctag_jbi_iq_dequeue_buf;
output sctag_jbi_wib_dequeue_buf;
output sctag_jbi_por_req_buf;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
// This repeater bank is a row of flops
// There are a maximum of 10 flops per row.
assign jbi_sctag_req_buf = jbi_sctag_req ;
assign scbuf_jbi_data_buf = scbuf_jbi_data ;
assign jbi_scbuf_ecc_buf[6:0] = jbi_scbuf_ecc[6:0] ;
assign jbi_sctag_req_vld_buf = jbi_sctag_req_vld ;
assign scbuf_jbi_ctag_vld_buf = scbuf_jbi_ctag_vld ;
assign scbuf_jbi_ue_err_buf = scbuf_jbi_ue_err ;
assign sctag_jbi_iq_dequeue_buf = sctag_jbi_iq_dequeue ;
assign sctag_jbi_wib_dequeue_buf = sctag_jbi_wib_dequeue;
assign sctag_jbi_por_req_buf = sctag_jbi_por_req ;
endmodule
|
//-----------------------------------------------------------------
//
// The original verilog code provided by Clifford E. Cummings,
// Sunburst Design, Inc.
//
//
//----------------------------------------------------------------
module small_async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 3,
parameter ALMOST_FULL_SIZE = 5,
parameter ALMOST_EMPTY_SIZE = 3
)
(
//wr interface
output wfull,
output w_almost_full,
input [DSIZE-1:0] wdata,
input winc, wclk, wrst_n,
//rd interface
output [DSIZE-1:0] rdata,
output rempty,
output r_almost_empty,
input rinc, rclk, rrst_n
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
sync_r2w #(ASIZE) sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst_n(wrst_n));
sync_w2r #(ASIZE) sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst_n(rrst_n));
fifo_mem #(DSIZE, ASIZE) fifo_mem
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(.ADDRSIZE(ASIZE), .ALMOST_EMPTY_SIZE(ALMOST_EMPTY_SIZE))
rptr_empty
(.rempty(rempty),
.r_almost_empty(r_almost_empty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst_n(rrst_n));
wptr_full #(.ADDRSIZE(ASIZE), .ALMOST_FULL_SIZE(ALMOST_FULL_SIZE))
wptr_full
(.wfull(wfull),
.w_almost_full(w_almost_full),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst_n(wrst_n));
endmodule // small_async_fifo
module sync_r2w #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] wq2_rptr,
input [ADDRSIZE:0] rptr,
input wclk, wrst_n);
reg [ADDRSIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
endmodule // sync_r2w
module sync_w2r #(parameter ADDRSIZE = 3)
(output reg [ADDRSIZE:0] rq2_wptr,
input [ADDRSIZE:0] wptr,
input rclk, rrst_n);
reg [ADDRSIZE:0] rq1_wptr;
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;
else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
endmodule // sync_w2r
module rptr_empty
#(parameter ADDRSIZE = 3,
parameter ALMOST_EMPTY_SIZE=3)
(output reg rempty,
output reg r_almost_empty,
output [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input [ADDRSIZE :0] rq2_wptr,
input rinc, rclk, rrst_n);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
reg [ADDRSIZE :0] rq2_wptr_bin;
integer i;
//------------------
// GRAYSTYLE2 pointer
//------------------
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//--------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//--------------------------------------------------------------
wire rempty_val = (rgraynext == rq2_wptr);
// Gray code to Binary code conversion
always @(rq2_wptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
rq2_wptr_bin[i] = ^ (rq2_wptr >> i);
wire [ADDRSIZE:0] subtract = (rbinnext + ALMOST_EMPTY_SIZE)-rq2_wptr_bin;
wire r_almost_empty_val = ~subtract[ADDRSIZE];
always @(posedge rclk or negedge rrst_n)
if (!rrst_n) begin
rempty <= 1'b1;
r_almost_empty <= 1'b 1;
end
else begin
rempty <= rempty_val;
r_almost_empty <= r_almost_empty_val;
end
endmodule // rptr_empty
module wptr_full
#(parameter ADDRSIZE = 3,
parameter ALMOST_FULL_SIZE=5
)
(output reg wfull,
output reg w_almost_full,
output [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input [ADDRSIZE :0] wq2_rptr,
input winc, wclk, wrst_n);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
reg [ADDRSIZE :0] wq2_rptr_bin;
integer i;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//-----------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//-----------------------------------------------------------------
wire wfull_val = (wgraynext ==
{~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
// Gray code to Binary code conversion
always @(wq2_rptr)
for (i=0; i<(ADDRSIZE+1); i=i+1)
wq2_rptr_bin[i] = ^ (wq2_rptr >> i);
wire [ADDRSIZE :0] subtract = wbinnext - wq2_rptr_bin - ALMOST_FULL_SIZE;
wire w_almost_full_val = ~subtract[ADDRSIZE];
always @(posedge wclk or negedge wrst_n)
if (!wrst_n) begin
wfull <= 1'b0;
w_almost_full <= 1'b 0;
end
else begin
wfull <= wfull_val;
w_almost_full <= w_almost_full_val;
end
endmodule // wptr_full
module fifo_mem #(parameter DATASIZE = 8, // Memory data word width
parameter ADDRSIZE = 3) // Number of mem address bits
(output [DATASIZE-1:0] rdata,
input [DATASIZE-1:0] wdata,
input [ADDRSIZE-1:0] waddr, raddr,
input wclken, wfull, wclk);
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] mem [0:DEPTH-1];
assign rdata = mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) mem[waddr] <= wdata;
endmodule // fifo_mem
|
#include <bits/stdc++.h> using namespace std; const int N = 600 + 5; const int M = 2e5 + 5; template <class T> inline void getin(T& num) { char c; bool flag = 0; num = 0; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag = 1; while (c >= 0 && c <= 9 ) { num = num * 10 + c - 48; c = getchar(); } if (flag) num = -num; } int n, m, u, v, In[N]; int tot, x[N], y[N], Out[N]; int cnt, fir[N], tar[M], nxt[M]; long long p, f[N][N], a[N][N]; inline void link(int a, int b) { tar[++cnt] = b, In[b]++, Out[a]++; nxt[cnt] = fir[a], fir[a] = cnt; } template <class T> inline void add(T& a, T b) { a += b; if (a >= p) a -= p; } inline void Dp() { queue<int> q; int c = 0; for (int i = 1; i <= n; i++) { if (!In[i]) x[++tot] = i; if (!Out[i]) y[++c] = i; } for (int i = 1; i <= n; i++) f[i][i] = 1; for (int i = 1; i <= n; i++) if (!In[i]) q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = fir[u]; i; i = nxt[i]) { int v = tar[i]; for (int i = 1; i <= n; i++) add(f[i][v], f[i][u]); In[v]--; if (!In[v]) q.push(v); } } for (int i = 1; i <= tot; i++) for (int j = 1; j <= tot; j++) a[i][j] = f[x[i]][y[j]]; } inline int calc(int n) { int ret = 1; for (int i = 1; i <= n; i++) { if (a[i][i] < 0) { ret = -ret; for (int k = i; k <= n; k++) a[i][k] = -a[i][k]; } for (int j = i + 1; j <= n; j++) { for (int k = i; k <= n; k++) a[i][k] %= p, a[j][k] %= p; while (a[j][i]) { if (a[j][i] < 0) { ret = -ret; for (int k = i; k <= n; k++) a[j][k] = -a[j][k]; } int t = a[i][i] / a[j][i]; for (int k = i; k <= n; k++) a[i][k] = (a[i][k] - t * a[j][k]) % p; for (int k = i; k <= n; k++) swap(a[i][k], a[j][k]); ret = -ret; } } if (a[i][i] == 0) return 0; ret = 1ll * ret * a[i][i] % p; } return (ret + p) % p; } int main() { getin(n), getin(m), getin(p); for (int i = 1; i <= m; i++) getin(u), getin(v), link(u, v); Dp(); cout << calc(tot) << n ; }
|
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_TB_V
`define SKY130_FD_SC_HS__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 TE_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 TE_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 TE_B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 TE_B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_TB_V
|
#include <bits/stdc++.h> using namespace std; double dot(complex<double> a, complex<double> b) { return (conj(a) * b).real(); } double cross(complex<double> a, complex<double> b) { return (conj(a) * b).imag(); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long double x, y, minangle = 600; int n, s, e; cin >> n; vector<pair<long double, int>> v; for (int i = 1; i <= n; i++) { cin >> x >> y; v.push_back({atan2(x, y) * 180.0 / 3.14159265359, i}); while (v.back().first < 0) v.back().first += 360.0; while (v.back().first > 360.0) v.back().first -= 360.0; } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { if (min(abs(v[i].first - v[(i + 1) % n].first), 360.0 - abs(v[i].first - v[(i + 1) % n].first)) - minangle <= -1e-20) { minangle = min(abs(v[i].first - v[(i + 1) % n].first), 360.0 - abs(v[i].first - v[(i + 1) % n].first)); s = v[i].second; e = v[(i + 1) % n].second; } } cout << s << << e; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O41A_BEHAVIORAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; namespace io { template <typename T> inline void read(T &x) { bool flag = false; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); c == - ? flag = true, x = 0 : x = c - 0 ; c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); if (flag) x = -x; } template <typename T> inline void write(T x) { char st[10010]; int cnt = 0; if (x < 0) x = -x, putchar( - ); if (x == 0) putchar( 0 ); while (x) { st[++cnt] = x % 10 + 48; x /= 10; } while (cnt) { putchar(st[cnt--]); } } } // namespace io using namespace io; int main() { int a, ans = 0; read(a); while (a) { ans += (a % 8 == 1); a /= 8; } write(ans); puts( ); return 0; }
|
module marsohod_3(
input CLK100MHZ,
input KEY0,
input KEY1,
output [7:0] LED,
output [12:1] IO
);
// wires & inputs
wire clk;
wire clkIn = CLK100MHZ;
wire rst_n = KEY0;
wire clkEnable = ~KEY1;
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( 4'b1000 ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( 4'b0010 ),
.regData ( regData )
);
//outputs
assign LED[0] = clk;
assign LED[7:1] = regData[6:0];
wire [11:0] seven_segments;
assign IO[12:1] = seven_segments;
sm_hex_display_digit sm_hex_display_digit
(
.digit1 (digit1),
.digit2 (digit2),
.digit3 (digit3),
.clkIn (clkIn),
.seven_segments (seven_segments)
);
wire [6:0] digit3;
wire [6:0] digit2;
wire [6:0] digit1;
sm_hex_display digit_02 (regData [3:0], digit3 [6:0]);
sm_hex_display digit_01 (regData [7:4], digit2 [6:0]);
sm_hex_display digit_00 (regData [11:8], digit1 [6:0]);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninja_life.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ninja_life (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/ninja_life.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/ninja_life.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/ninja_life.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninja_life_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 1000; const long long INF64 = 1e18; const int N = 1001000; const int MOD = 1e9 + 7; const double EPS = 1E-9; long long gcd(long long a, long long b) { return a == 0 ? b : gcd(b % a, a); } int add(int first, int second, int m) { first += second; while (first >= m) first -= m; while (first < 0) first += m; return first; } int sub(int first, int second, int m) { return add(first, -second, m); } int mul(int first, int second, int m) { return (first * 1ll * second) % m; } int binpow(int first, int second, int m) { int z = 1; while (second) { if (second & 1) z = mul(z, first, m); first = mul(first, first, m); second >>= 1; } return z; } int divide(int first, int second, int m) { return mul(first, binpow(second, m - 2, m), m); } const int K = 2; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); bool is_prime(int first) { for (int i = 2; i * 1ll * i <= first; i++) if (first % i == 0) return false; return true; } int gen_prime(int first, int offset) { int z = first + (rnd() % offset); while (!is_prime(z)) z++; return z; } array<int, K> P = {10, 10}; array<int, K> M = {1000000007, 1000000009}; void precalc() { for (int i = 0; i < K; i++) { P[i] = gen_prime(100, 100); M[i] = gen_prime(1000000000, 1000000); } } array<int, K> add(array<int, K> first, array<int, K> second) { array<int, K> res; for (int i = 0; i < K; i++) res[i] = add(first[i], second[i], M[i]); return res; } array<int, K> sub(array<int, K> first, array<int, K> second) { array<int, K> res; for (int i = 0; i < K; i++) res[i] = sub(first[i], second[i], M[i]); return res; } array<int, K> mul(array<int, K> first, array<int, K> second) { array<int, K> res; for (int i = 0; i < K; i++) res[i] = mul(first[i], second[i], M[i]); return res; } array<int, K> binpow(array<int, K> first, int second) { array<int, K> res; for (int i = 0; i < K; i++) res[i] = binpow(first[i], second, M[i]); return res; } array<int, K> divide(array<int, K> first, array<int, K> second) { array<int, K> z; for (int i = 0; i < K; i++) z[i] = divide(first[i], second[i], M[i]); return z; } int code(char c) { return (c - 0 ); } array<int, K> make_hash(int first) { array<int, K> res; for (int i = 0; i < K; i++) res[i] = first; return res; } vector<array<int, K> > get_prefix_hashes(const string& s) { int n = s.size(); vector<array<int, K> > ans(n + 1); array<int, K> curP = make_hash(1); for (int i = 0; i < n; i++) { ans[i + 1] = add(ans[i], mul(make_hash(code(s[i])), curP)); curP = mul(curP, P); } return ans; } array<int, K> DP[N], DQ[N]; array<int, K> substr_hash(const vector<array<int, K> >& p, int l, int r) { return mul(sub(p[r], p[l]), DQ[l]); } array<int, K> concat(array<int, K> a, array<int, K> b, int len) { return add(a, mul(b, DP[len])); } vector<array<int, K> > test; void preprecalc() { DP[0] = make_hash(1); for (int i = 1; i < N; i++) DP[i] = mul(P, DP[i - 1]); for (int i = 0; i < N; i++) DQ[i] = divide(make_hash(1), DP[i]); } int ans = INF; string s; void rec(int l, int r, char c, int cur) { if (r - l == 1) { cur += (s[l] != c); ans = min(ans, cur); return; } int m = (r + l) / 2; int curl = 0, curr = 0; for (int i = l; i < m; ++i) { curl += (s[i] != c); curr += (s[i + m - l] != c); } rec(l, m, c + 1, cur + curr); rec(m, r, c + 1, cur + curl); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; set<int> have; for (int i = 0; i < 2 * n; ++i) { int first; cin >> first; if (!have.count(first)) { cout << first << ; have.insert(first); } } cout << n ; } }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; if (n & 1) cout << n / 2 << n ; else { long long int p = 1; for (long long int i = 1; 2 * p <= n; i++) p = 1 << i; cout << (n - p) / 2 << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { double n, x; cin >> n >> x; vector<double> a(n); for (__typeof(n) i = 0; i < n; i++) { cin >> a[i]; } sort(a.rbegin(), a.rend()); a.push_back(0); double no = 1, am = a[0]; while ((am / no >= x) && (no <= n)) { am += a[no]; no++; } cout << no - 1 << n ; } return 0; }
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// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:45:39 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v
// Design : blk_mem_gen_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *)
module blk_mem_gen_1(clka, wea, addra, dina, clkb, enb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[11:0],dina[7:0],clkb,enb,addrb[9:0],doutb[31:0]" */;
input clka;
input [0:0]wea;
input [11:0]addra;
input [7:0]dina;
input clkb;
input enb;
input [9:0]addrb;
output [31:0]doutb;
endmodule
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#include <bits/stdc++.h> using namespace std; int n; bool vis[400]; set<int> sub[400]; vector<int> ga[400]; vector<int> path; vector<int> ord; int curr; void DFS(int a) { sub[a].insert(a); for (int i = 0; i < ga[a].size(); i++) { int b = ga[a][i]; if (vis[b]) continue; vis[b] = true; DFS(b); for (__typeof(sub[b].begin()) it = sub[b].begin(); it != sub[b].end(); it++) sub[a].insert(*it); } } void SFD(int a) { if (ord[curr] == a) { curr++; return; } while (1) { if (curr == ord.size()) return; bool upd = false; for (int i = 0; i < ga[a].size(); i++) { int b = ga[a][i]; if (vis[b] || sub[b].find(ord[curr]) == sub[b].end()) continue; vis[b] = true; path.push_back(b); SFD(b); path.push_back(a); upd = true; break; } if (!upd) return; } } int main() { cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; ga[a].push_back(b); ga[b].push_back(a); } int x; while (cin >> x) ord.push_back(x); vis[1] = true; DFS(1); memset(vis, false, sizeof(vis)); path.push_back(1); vis[1] = true; SFD(1); if (path.size() != n * 2 - 1) cout << -1; else { for (int i = 0; i < path.size(); i++) cout << path[i] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long MOD = 1e9 + 7; long long MAX = 1e17; bool b[1000]; int main() { ios_base::sync_with_stdio(0); ; int m, t, r, ans = 0; cin >> m >> t >> r; int w[m]; for (int i = 0; i < m; i++) cin >> w[i]; if (r > t) { cout << -1 << endl; return 0; } for (int i = 0; i < m; i++) w[i] += t + 10; for (int i = 0; i < m; i++) { int k = r; for (int j = w[i] - t; j < w[i]; j++) if (b[j]) k--; if (k <= 0) continue; for (int j = w[i] - 1; j > w[i] - t - 1; j--) { if (!b[j]) { b[j] = 1; k--; ans++; } if (k == 0) break; if (j == w[i] - t) { cout << -1 << endl; return 0; } } } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const int maxn5 = 3e5 + 10; const int maxn3 = 1e3 + 10; const long long mod = 1e9 + 7; const long long inf = 2e18; int a[maxn5], righ[24][maxn5], lef[24][maxn5]; int mn[18][maxn5], mx[18][maxn5], n, ans[maxn5], l[maxn5], r[maxn5]; void rmq(int k) { for (int i = 0; i < 3 * n; i++) { mn[0][i] = i - lef[k][i % n]; mx[0][i] = i + righ[k][i % n]; } for (int i = 1; i < 18; i++) { for (int j = 0; j < 3 * n and (j + (1 << i) - 1) < 3 * n; j++) { mn[i][j] = min(mn[i - 1][j], mn[i - 1][j + (1 << (i - 1))]); mx[i][j] = max(mx[i - 1][j], mx[i - 1][j + (1 << (i - 1))]); } } return; } int get_left(int l, int r) { int k = 31 - __builtin_clz(r - l + 1); return min(mn[k][l], mn[k][r - (1 << k) + 1]); } int get_right(int l, int r) { int k = 31 - __builtin_clz(r - l + 1); return max(mx[k][l], mx[k][r - (1 << k) + 1]); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < 3 * n; i++) lef[0][i] = a[i % n], righ[0][i] = a[i % n]; for (int i = 1; i < 18; i++) { rmq(i - 1); for (int j = 0; j < n; j++) { if (lef[i - 1][j] >= n or righ[i - 1][j] >= n) { lef[i][j] = maxn; righ[i][j] = maxn; continue; } lef[i][j] = n + j - get_left(n + j - lef[i - 1][j], n + j + righ[i - 1][j]); righ[i][j] = get_right(n + j - lef[i - 1][j], n + j + righ[i - 1][j]) - j - n; } } for (int i = 0; i < n; i++) l[i] = i + n, r[i] = i + n; for (int i = 17; i >= 0; i--) { rmq(i); for (int j = 0; j < n; j++) if (get_right(l[j], r[j]) - get_left(l[j], r[j]) < n) { int a = get_left(l[j], r[j]); int b = get_right(l[j], r[j]); l[j] = a, r[j] = b; ans[j] += (1 << i); } } for (int i = 0; i < n; i++) cout << ans[i] + (r[i] - l[i] < n - 1 ? 1 : 0) << ; return 0; }
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#include <bits/stdc++.h> using namespace std; int r1, c1, r2, c2; int CB[10][10]; int dr[8] = {1, -1, 1, -1, -2, -2, 2, 2}; int dc[8] = {2, 2, -2, -2, -1, 1, -1, 1}; int main() { char s[10]; scanf( %s , s); r1 = s[0] - a + 1; c1 = s[1] - 0 ; scanf( %s , s); r2 = s[0] - a + 1; c2 = s[1] - 0 ; CB[r1][c1] = 2; CB[r2][c2] = 2; for (int i = r1, j = c1 + 1; j <= 8; j++) CB[i][j] = 1; for (int i = r1, j = c1 - 1; j > 0; j--) CB[i][j] = 1; for (int i = r1 + 1, j = c1; i <= 8; i++) CB[i][j] = 1; for (int i = r1 - 1, j = c1; i > 0; i--) CB[i][j] = 1; for (int i = 0; i < 8; i++) { int p = r2 + dr[i]; int q = c2 + dc[i]; if (p > 0 && q > 0 && p < 9 && q < 9) CB[p][q] = 1; } for (int i = 0; i < 8; i++) { int p = r1 + dr[i]; int q = c1 + dc[i]; if (p > 0 && q > 0 && p < 9 && q < 9) CB[p][q] = 1; } int cnt = 0; for (int i = 1; i <= 8; i++) { for (int j = 1; j <= 8; j++) { if (CB[i][j] == 0) cnt++; } } printf( %d n , cnt); return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> void inc(T& a, const T& b) { if (a < b) a = b; } template <class T> void dec(T& a, const T& b) { if (a > b) a = b; } const int N = 100010; int n; int a[N]; struct node { int lf, len; bool operator<(const node& rhs) const { if (len != rhs.len) return len < rhs.len; return lf < rhs.lf; } } c[N * 10]; int cn; map<int, vector<int> > g; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , a + i); if (g.find(a[i]) == g.end()) g[a[i]] = vector<int>(); g[a[i]].push_back(i); } for (map<int, vector<int> >::iterator it = (g).begin(); it != (g).end(); ++it) { vector<int>& t = it->second; int sz = t.size(); for (int i = 0; i < sz; i++) { for (int j = i + 1; j < sz; j++) { if (t[j] - t[i] + t[j] > n) break; c[cn].lf = t[i]; c[cn].len = t[j] - t[i]; cn++; } } } sort(c, c + cn); int p = 0; for (int i = 0; i < cn; i++) { int& lf = c[i].lf; int rt = lf + c[i].len; if (lf < p) continue; bool flag = true; for (int j = 1; j < c[i].len; j++) { if (a[lf + j] != a[rt + j]) { flag = false; break; } } if (flag) { p = rt; } } printf( %d n , n - p); for (int i = p; i < n; ++i) { printf( %d , a[i]); putchar(i + 1 < n ? 32 : 10); } return 0; }
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`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express BFM Shmem Module
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_bfm_shmem_common.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// Implements the common shared memory array
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcietb_bfm_shmem_common(dummy_out) ;
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
output dummy_out;
reg [7:0] shmem[0:SHMEM_SIZE-1] ;
// Protection Bit for the Shared Memory
// This bit protects critical data in Shared Memory from being overwritten.
// Critical data includes things like the BAR table that maps BAR numbers to addresses.
// Deassert this bit to REMOVE protection of the CRITICAL data.
reg protect_bfm_shmem;
initial
begin
shmem_fill(0,SHMEM_FILL_ZERO,SHMEM_SIZE,{64{1'b0}}) ;
protect_bfm_shmem = 1'b1;
end
endmodule // altpcietb_bfm_shmem_common
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