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// patterngenerator.v
`timescale 1ns / 1ps
module patterngenerator
(
// avalon clock interface
input csi_clock_clk,
input csi_clock_reset,
// avalon mm slave: status/control
input avs_ctrl_address,
input avs_ctrl_read,
output [31:0]avs_ctrl_readdata,
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
// avalon mm slave: command memory
input [7:0]avs_data_address,
input avs_data_write,
input [1:0]avs_data_byteenable,
input [15:0]avs_data_writedata,
// pattern generator interface
input clkena,
input trigger,
output [5:0]pgout
);
/* avalon 16 bit register file
0 w control register
0 r status register
1 w period register
control register:
bit 7: enable pattern generator
bit 2: enable loop
bit 1: enable external trigger
bit 0: start single sequence
*/
// control regisdter bits
reg ctrl_ena;
reg ctrl_ext;
reg ctrl_loop;
reg ctrl_start;
wire start;
wire enable;
wire ena_loop;
wire ena_ext;
wire set_start;
wire running;
reg [15:0]period;
reg [15:0]loopcnt;
wire [7:0]seq_address;
wire [15:0]seq_command;
// --- control register programming ---------------------------------------
always @(posedge csi_clock_clk or posedge csi_clock_reset)
begin
if (csi_clock_reset)
begin
{ ctrl_ena, ctrl_loop, ctrl_ext, ctrl_start } <= 4'b0000;
period <= 0;
end
else if (avs_ctrl_write)
begin
case (avs_ctrl_address)
0: { ctrl_ena, ctrl_loop, ctrl_ext, ctrl_start }
<= { avs_ctrl_writedata[7], avs_ctrl_writedata[2:0] };
1: period <= avs_ctrl_writedata[15:0];
endcase
end
else if (clkena) ctrl_start <= 0;
end
assign avs_ctrl_readdata =
avs_ctrl_address ? { 16'd0, period } : { 31'd0, running };
assign enable = ctrl_ena;
assign ena_ext = ctrl_ext;
assign ena_loop = ctrl_loop;
assign set_start = ctrl_start;
// --- trigger generator --------------------------------------------------
wire trig_loop = loopcnt == 0;
always @(posedge csi_clock_clk or posedge csi_clock_reset)
begin
if (csi_clock_reset) loopcnt <= 0;
else if (clkena)
begin
if (ena_loop)
begin
if (trig_loop) loopcnt <= period; else loopcnt <= loopcnt - 1;
end
else loopcnt <= 0;
end
end
assign start = set_start || (ena_loop && trig_loop) || (ena_ext && trigger);
pg_ram ram
(
// avalon port
.clock (csi_clock_clk),
.wren (avs_data_write),
.wraddress (avs_data_address),
.byteena_a (avs_data_byteenable),
.data (avs_data_writedata),
// pattern generator port
.rdaddress (seq_address),
.q (seq_command)
);
pg_sequencer pg
(
.clk(csi_clock_clk),
.sync(clkena),
.reset(csi_clock_reset),
.enable(enable),
.start(start),
.running(running),
.pgout(pgout),
.ip(seq_address),
.cmd(seq_command)
);
endmodule
|
module processor(
input wire mclk,
// For Physical EPP Memory Interface
/*input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output wire epp_wait,
inout wire[7:0] epp_data,*/
// For Simulated Memory Interface
input wire core_stall,
output wire memory_read,
output wire memory_write,
output wire[31:0] memory_address,
output wire[31:0] memory_din,
input wire[31:0] memory_dout,
input wire[7:0] switch,
input wire[3:0] button,
output wire[7:0] seg,
output wire[3:0] digit,
output wire hsync,
output wire vsync,
output wire[7:0] color
);
// Combinational
assign seg[7] = 1'b1;
// State
wire[3:0] enable = 4'b1111;
// For Physical EPP Memory Interface
/*wire core_stall;
wire memory_read;
wire memory_write;
wire[31:0] memory_address;
wire[31:0] memory_din;
wire[31:0] memory_dout;*/
// Displays
wire[15:0] digit_values;
wire[11:0] vga_write_address;
wire[7:0] vga_write_data;
wire vga_write_enable;
// Modules
core core_inst(
.mclk(mclk),
.stall(core_stall),
.dbg(digit_values),
.mem_address(memory_address),
.mem_din(memory_din),
.mem_dout(memory_dout),
.mem_re(memory_read),
.mem_we(memory_write),
.vga_address(vga_write_address),
.vga_data(vga_write_data),
.vga_we(vga_write_enable)
);
// For Physical EPP Memory Interface
/*memory memory_inst(
.mclk(mclk),
.epp_astb(epp_astb),
.epp_dstb(epp_dstb),
.epp_wr(epp_wr),
.epp_wait(epp_wait),
.epp_data(epp_data),
.core_stall(core_stall),
.read(memory_read),
.write(memory_write),
.address(memory_address),
.din(memory_din),
.dout(memory_dout)
);*/
digits digits_inst(
.seg(seg[6:0]),
.digit(digit),
.mclk(mclk),
.enable(enable),
.values(digit_values)
);
vga vga_inst(
.mclk(mclk),
.hsync(hsync),
.vsync(vsync),
.standard(switch[7:4]),
.emphasized(switch[3:0]),
.background(button),
.write_address(vga_write_address),
.write_data(vga_write_data),
.write_enable(vga_write_enable),
.color(color)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x in[3:0]=%x out=%x,%x\n", $time, cyc, crc, sum, crc[3:0], out1,out2);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
`define EXPECTED_SUM 64'h10204fa5567c8a4b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
case (in[3:0]) inside
default: {out1,out2} = {1'b0,5'h0F}; // Note not last item
4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01};
4'h4: {out1,out2} = {1'b1,5'h04};
[4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match
4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08};
[4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C};
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isprime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } vector<long long int> prime; void sieve(long long int n) { bool bakh[n + 1]; memset(bakh, true, sizeof(bakh)); for (long long int p = 2; p * p <= n; p++) { if (bakh[p] == true) { for (long long int i = p * p; i <= n; i += p) bakh[i] = false; } } for (long long int p = 2; p <= n; p++) if (bakh[p]) prime.push_back(p); } long long int eulertotient(long long int z) { long long int fac = z; for (long long int i = 0; prime[i] * prime[i] <= z; i++) { if (z % prime[i] == 0) { fac -= (fac / prime[i]); while (z % prime[i] == 0) z /= prime[i]; } } if (z > 1) fac -= (fac / z); return fac; } long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int lcm(long long int a, long long int b) { long long int g = gcd(a, b); long long int ans = (a * b) / g; return ans; } long long int modInverse(long long int a, long long int m) { long long int hvf = gcd(a, m); if (hvf == 1) return power(a, m - 2, m); return -1; } void multiply(long long int F[2][2], long long int M[2][2]) { long long int x = F[0][0] * M[0][0] + F[0][1] * M[1][0]; long long int y = F[0][0] * M[0][1] + F[0][1] * M[1][1]; long long int z = F[1][0] * M[0][0] + F[1][1] * M[1][0]; long long int w = F[1][0] * M[0][1] + F[1][1] * M[1][1]; F[0][0] = x; F[0][1] = y; F[1][0] = z; F[1][1] = w; } void powermat(long long int F[2][2], long long int n) { if (n == 0 || n == 1) return; long long int M[2][2] = {{1, 1}, {1, 0}}; powermat(F, n / 2); multiply(F, F); if (n % 2 != 0) multiply(F, M); } long long int fib(long long int n) { long long int F[2][2] = {{1, 1}, {1, 0}}; if (n == 0) return 0; powermat(F, n - 1); return F[0][0]; } vector<long long int> merge(vector<long long int> v1, vector<long long int> v2) { vector<long long int> temp; long long int i = 0, j = 0; while (i < v1.size() && j < v2.size()) { if (v1[i] < v2[j]) temp.push_back(v1[i]), i++; else temp.push_back(v2[j]), j++; } while (i < v1.size()) temp.push_back(v1[i]), i++; while (j < v2.size()) temp.push_back(v2[j]), j++; return temp; } long long int n, m; vector<long long int> mark; vector<long long int> top; vector<pair<long long int, long long int> > adj[100005]; void dfs(long long int u) { mark[u] = 1; for (auto v : adj[u]) { if (!mark[v.first]) dfs(v.first); } top.push_back(u); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int a, b; cin >> n >> m; for (long long int i = 1; i <= m; i++) cin >> a >> b, adj[a].push_back({b, i}); mark.clear(); mark.resize(n + 1, 0); for (long long int i = 1; i <= n; i++) { if (!mark[i]) dfs(i); } bool flag; long long int ans = 0; for (long long int i = n - 1; i > 0; i--) { long long int u = top[i], v = top[i - 1]; flag = 0; for (auto e : adj[u]) { if (e.first == v) { ans = max(ans, e.second); flag = 1; break; } } if (!flag) return cout << -1 << endl, 0; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int a[100000]; int m[100001]; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } m[n] = 1e9 + 1; for (int i = n - 1; i >= 0; i--) { m[i] = min(m[i + 1], a[i]); } for (int i = 0; i < n; i++) { cout << (lower_bound(m + i + 1, m + n, a[i]) - m - i - 2) << n ; } return 0; }
|
`timescale 1 ns/1 ps
module someTwoPortVendorMem_4096_32_0 (QA,
CLKA,
CENA,
WENA,
AA,
DA,
OENA,
QB,
CLKB,
CENB,
WENB,
AB,
DB,
OENB);
output [31:0] QA;
input CLKA;
input CENA;
input WENA;
input [11:0] AA;
input [31:0] DA;
input OENA;
output [31:0] QB;
input CLKB;
input CENB;
input WENB;
input [11:0] AB;
input [31:0] DB;
input OENB;
reg [31:0] mem [4096:0];
reg [31:0] QA,QB;
initial
begin
$display("%m : someTwoPortVendorMem_4096_32_0 instantiated.");
end
always @(posedge CLKA)
begin
if((CENA == 0)&&(WENA==0))
begin
mem[AA] <= DA;
end
else if((CENA == 0)&&(WENA==1))
begin
QA <=mem[AA];
end
end
always @(posedge CLKB)
begin
if((CENB == 0)&&(WENB==0))
begin
mem[AB] <= DB;
end
else if((CENB == 0)&&(WENB==1))
begin
QB <=mem[AB];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND4_PP_BLACKBOX_V
/**
* nand4: 4-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; inline int read(int f = 1, int x = 0, char ch = ) { while (!isdigit(ch = getchar())) if (ch == - ) f = -1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f * x; } const int N = 2e5 + 5; int m, n, T, s[2][N], c[2], f[2], ans, q[N], t[N], type[N], tot; long long a, b; int main() { m = read(); while (m--) { n = read(), T = read(), a = read(), b = read(); c[0] = c[1] = f[0] = f[1] = ans = 0; for (int i = 1; i <= n; ++i) type[i] = read(), s[0][i] = s[1][i] = 0; for (int i = 1; i <= n; ++i) q[i] = t[i] = read(); sort(q + 1, q + 1 + n), tot = unique(q + 1, q + 1 + n) - q - 1; for (int i = 1; i <= n; ++i) { int j = lower_bound(q + 1, q + 1 + tot, t[i]) - q; ++s[type[i]][j], ++c[type[i]]; } q[tot + 1] = max(q[tot] + 1, T + 1); for (int i = 0; i <= tot; ++i) { f[0] += s[0][i], f[1] += s[1][i]; int t = min(q[i + 1] - 1, T), resa = c[0] - f[0], resb = c[1] - f[1]; ; if (f[0] * a + f[1] * b > t) continue; int rest = t - (f[0] * a + f[1] * b); if (resa * a <= rest) ans = max(f[0] + f[1] + resa + min((rest - resa * a) / b, 1ll * resb), 1ll * ans); else ans = max(f[0] + f[1] + rest / a, 1ll * ans); } printf( %d n , ans); } return 0; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:19:11 02/11/2009
// Design Name:
// Module Name: RCB_FRL_RX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////
module RCB_FRL_RX(
input CLKDIV,
input [31:0] DATA_IN,
output [31:0] DATA_OUT,
input RST,
// input RDCLK,
input RDEN,
output ALMOSTEMPTY
// output fifo_WREN
);
wire [7:0] data_channel1;
wire [7:0] data_channel2;
wire [7:0] data_channel3;
wire [7:0] data_channel4;
wire wren_channel1;
wire wren_channel2;
wire wren_channel3;
wire wren_channel4;
wire pempty_channel1;
wire pempty_channel2;
wire pempty_channel3;
wire pempty_channel4;
assign ALMOSTEMPTY = pempty_channel1 | pempty_channel2 | pempty_channel3 | pempty_channel4;
// four data channels, to do byte alignment and Sora-FRL packet decapsulation
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_01_inst (
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[7:0]), .RST(RST), .data_valid(wren_channel1),
.data_out(data_channel1[7:0])
);
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_02_inst (
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[15:8]), .RST(RST), .data_valid(wren_channel2),
.data_out(data_channel2[7:0])
);
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_03_inst (
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[23:16]), .RST(RST), .data_valid(wren_channel3),
.data_out(data_channel3[7:0])
);
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_04_inst (
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[31:24]), .RST(RST), .data_valid(wren_channel4),
.data_out(data_channel4[7:0])
);
// assign fifo_WREN = wren_channel1 & wren_channel2 & wren_channel3 & wren_channel4;
// Four 8-bit data fifos for four data channels
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst1(
.clk (CLKDIV),
.rst (RST),
.din (data_channel1[7:0]), // Bus [7 : 0]
.wr_en (wren_channel1),
.rd_en (RDEN),
.dout (DATA_OUT[7:0]), // Bus [7 : 0]
.full (),
.empty (),
.prog_empty (pempty_channel1)
);
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst2(
.clk (CLKDIV),
.rst (RST),
.din (data_channel2[7:0]), // Bus [7 : 0]
.wr_en (wren_channel2),
.rd_en (RDEN),
.dout (DATA_OUT[15:8]), // Bus [7 : 0]
.full (),
.empty (),
.prog_empty (pempty_channel2)
);
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst3(
.clk (CLKDIV),
.rst (RST),
.din (data_channel3[7:0]), // Bus [7 : 0]
.wr_en (wren_channel3),
.rd_en (RDEN),
.dout (DATA_OUT[23:16]), // Bus [7 : 0]
.full (),
.empty (),
.prog_empty (pempty_channel3)
);
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst4(
.clk (CLKDIV),
.rst (RST),
.din (data_channel4[7:0]), // Bus [7 : 0]
.wr_en (wren_channel4),
.rd_en (RDEN),
.dout (DATA_OUT[31:24]), // Bus [7 : 0]
.full (),
.empty (),
.prog_empty (pempty_channel4)
);
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_01_inst(
// .ALMOSTEMPTY(pempty_channel1), .ALMOSTFULL(), .DO(DATA_OUT [7:0]), .EMPTY(), .FULL(),
// .DI(data_channel1[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel1), .RST(RST)
// );
//
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_02_inst(
// .ALMOSTEMPTY(pempty_channel2), .ALMOSTFULL(), .DO(DATA_OUT [15:8]), .EMPTY(), .FULL(),
// .DI(data_channel2[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel2), .RST(RST)
// );
//
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_03_inst(
// .ALMOSTEMPTY(pempty_channel3), .ALMOSTFULL(), .DO(DATA_OUT [23:16]), .EMPTY(), .FULL(),
// .DI(data_channel3[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel3), .RST(RST)
// );
//
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_04_inst(
// .ALMOSTEMPTY(pempty_channel4), .ALMOSTFULL(), .DO(DATA_OUT [31:24]), .EMPTY(), .FULL(),
// .DI(data_channel4[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel4), .RST(RST)
// );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_TB_V
`define SKY130_FD_SC_HD__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_hd__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_TB_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Sat Jun 4 16:53:15 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_stub.v
// Design : ClockDivider
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ClockDivider(clk, clk_vga, clk_cpu, clk_2cpu)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_vga,clk_cpu,clk_2cpu" */;
input clk;
output clk_vga;
output clk_cpu;
output clk_2cpu;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Max = 1e5 + 10; int fw[Max][26]; int bw[Max][26]; int gs[Max][26]; int ge[Max][26]; int n; int A[Max]; int mex(vector<int> vec); void CalcGS(int i, int c); void CalcGE(int i, int c); int mex(vector<int> vec) { sort(vec.begin(), vec.end()); if (vec[0] > 0) return 0; for (int i = 1; i < vec.size(); i++) if (vec[i] > vec[i - 1] + 1) return vec[i - 1] + 1; return vec.back() + 1; } int G(int l, int r) { if (l >= r) return 0; if ((r - l) == 1 || (r - l) == 2 && A[l + 1] == A[r + 1]) return 1; l++, r--; for (int ch = 0; ch < 26; ch++) { if (A[l] == ch && A[r] == ch) { CalcGS(l + 1, ch); CalcGS(r + 1, ch); } else if (A[r] == ch) { CalcGS(l, ch); CalcGS(r + 1, ch); } else if (A[l] == ch) { int lCh = bw[r][ch]; CalcGS(l + 1, ch); CalcGS(lCh + 1, ch); CalcGE(r, ch); } else { int lCh = bw[r][ch]; if (lCh < l) continue; CalcGS(l, ch); CalcGS(lCh + 1, ch); CalcGE(r, ch); } } vector<int> vec; for (int ch = 0; ch < 26; ch++) { int g = 0; if (A[l] == ch && A[r] == ch) { g = gs[l + 1][ch] ^ gs[r + 1][ch]; } else if (A[r] == ch) { g = gs[l][ch] ^ gs[r + 1][ch]; } else if (A[l] == ch) { int lCh = bw[r][ch]; g = gs[l + 1][ch] ^ gs[lCh + 1][ch] ^ ge[r][ch]; } else { int lCh = bw[r][ch]; if (lCh < l) continue; g = gs[l][ch] ^ gs[lCh + 1][ch] ^ ge[r][ch]; } vec.push_back(g); } return mex(vec); } void CalcGE(int i, int c) { if (ge[i][c] >= 0) return; if (A[i] == c) { ge[i][c] = 0; return; } int l = bw[i][c], r = i + 1; ge[i][c] = G(l, r); } void CalcGS(int i, int c) { if (gs[i][c] >= 0) return; CalcGS(fw[i - 1][c] + 1, c); if (A[i] == c) { gs[i][c] = 0 ^ gs[fw[i - 1][c] + 1][c]; return; } int g = G(i - 1, fw[i - 1][c]) ^ gs[fw[i - 1][c] + 1][c]; gs[i][c] = g; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { string s; cin >> s; n = s.size(); for (int i = 0; i <= n; i++) for (int ch = 0; ch < 26; ch++) gs[i][ch] = ge[i][ch] = -1; for (int ch = 0; ch < 26; ch++) gs[0][ch] = gs[n + 1][ch] = 0; for (int i = 0; i < n; i++) A[i + 1] = s[i] - a ; for (int ch = 0; ch < 26; ch++) { int lastChSeen = n + 1; for (int i = n; i--;) { fw[i + 1][ch] = lastChSeen; if (A[i + 1] == ch) lastChSeen = i + 1; } fw[0][ch] = lastChSeen; lastChSeen = 0; bw[0][ch] = lastChSeen; for (int i = 0; i < n; i++) { bw[i + 1][ch] = lastChSeen; if (A[i + 1] == ch) lastChSeen = i + 1; } } } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; if (l == r) { cout << Alice n ; continue; } int g = G(l - 1, r + 1); if (g == 0) cout << Bob n ; else cout << Alice n ; } }
|
module PressCountFPGA(clock,reset,countu,countd,nr_presses,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock;
input wire reset;
input wire countu;
input wire countd;
output wire [7:0] nr_presses;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire cm_locked;
wire cm_clock0;
wire cm_clock180;
ClockManager
cm (.clock(clock),
.reset(reset),
.locked(cm_locked),
.clock0(cm_clock0),
.clock180(cm_clock180));
PressCount
presscount (.clock0(cm_clock0),
.clock180(cm_clock180),
.reset(reset & cm_locked),
.countu(countu),
.countd(countd),
.nr_presses(nr_presses),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // PressCountFPGA
|
#include <bits/stdc++.h> using namespace std; const long double PI = 3.141592653589793238462643l; void solve(); int main() { solve(); return 0; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } void solve() { long long a, b, x1, y1, x2, y2; cin >> a >> b >> x1 >> y1 >> x2 >> y2; long long ans1, ans2; long long eps11 = 0, eps12 = 0, eps21 = 0, eps22 = 0; if (x1 + y1 < 0) eps11 = -2 * a; if (x2 + y2 < 0) eps12 = -2 * a; if (x1 - y1 < 0) eps21 = -2 * b; if (x2 - y2 < 0) eps22 = -2 * b; ans1 = (x1 + y1 + eps11) / (2 * a) - (eps12 + x2 + y2) / (2 * a); ans2 = (eps21 + x1 - y1) / (2 * b) - (eps22 + x2 - y2) / (2 * b); if (ans1 < 0) ans1 = -ans1; if (ans2 < 0) ans2 = -ans2; cout << max(ans1, ans2); }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 5,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
output wire [31:0] P_mode
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of P_mode
// bit 31~0 - P_mode[31:0] (Read/Write)
// 0x14 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 5'h00,
ADDR_GIE = 5'h04,
ADDR_IER = 5'h08,
ADDR_ISR = 5'h0c,
ADDR_P_MODE_DATA_0 = 5'h10,
ADDR_P_MODE_CTRL = 5'h14,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 5;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
reg [31:0] int_P_mode;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_P_MODE_DATA_0: begin
rdata <= int_P_mode[31:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
assign P_mode = int_P_mode;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_P_mode[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_mode[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_MODE_DATA_0)
int_P_mode[31:0] <= (WDATA[31:0] & wmask) | (int_P_mode[31:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
#include <bits/stdc++.h> char _; using namespace std; int N, C, D; pair<int, int> A[400000]; long long Z, ZO, ZOZ, O, OZ, OZO; inline bool cmp(const pair<int, int>& a, const pair<int, int>& b) { if ((b.second < 0) ^ (a.second < 0)) return 1LL * a.first * b.second > 1LL * b.first * a.second; return 1LL * a.first * b.second < 1LL * b.first * a.second; } inline bool eq(const pair<int, int>& a, const pair<int, int>& b) { return 1LL * a.first * b.second == 1LL * b.first * a.second; } int main() { do { while ((N = getchar()) < 0 ) ; for (N -= 0 ; 0 <= (_ = getchar()); N = (N << 3) + (N << 1) + _ - 0 ) ; } while (0); do { while ((C = getchar()) < 0 ) ; for (C -= 0 ; 0 <= (_ = getchar()); C = (C << 3) + (C << 1) + _ - 0 ) ; } while (0); do { while ((D = getchar()) < 0 ) ; for (D -= 0 ; 0 <= (_ = getchar()); D = (D << 3) + (D << 1) + _ - 0 ) ; } while (0); for (int i = 0; i < N; i++) { do { while ((A[i].first = getchar()) < 0 ) ; for (A[i].first -= 0 ; 0 <= (_ = getchar()); A[i].first = (A[i].first << 3) + (A[i].first << 1) + _ - 0 ) ; } while (0); do { while ((A[i].second = getchar()) < 0 ) ; for (A[i].second -= 0 ; 0 <= (_ = getchar()); A[i].second = (A[i].second << 3) + (A[i].second << 1) + _ - 0 ) ; } while (0); A[i].first -= C, A[i].second -= D; } sort(A, A + N, cmp); for (int i = 0, j; i < N; i = j) { long long NZ = Z, NZO = ZO, NZOZ = ZOZ, NO = O, NOZ = OZ, NOZO = OZO; for (j = i; j < N && eq(A[i], A[j]); j++) { if (A[j].second < 0) { NOZO += OZ; NZO += Z; NO++; } else { NZOZ += ZO; NOZ += O; NZ++; } } Z = NZ, ZO = NZO, ZOZ = NZOZ, O = NO, OZ = NOZ, OZO = NOZO; } int L = 0, R = 0, D = 0; for (int i = 0; i < N; i++) if (A[i].second == 0) { if (A[i].first < 0) L++; else R++; } for (int i = 0; i < N; i++) if (A[i].second < 0) D++; printf( %lld n , OZO + ZOZ - 1LL * L * R * D); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND3_BEHAVIORAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int max1 = 0, max2 = 0, min1 = (1000000000 + 9), min2 = (1000000000 + 9); for (int i = 0; i < n; i++) { long long int x, y; cin >> x >> y; if (y < min1) { min1 = y; } if (x > max1) { max1 = x; } } long long int m; cin >> m; for (int i = 0; i < m; i++) { long long int x, y; cin >> x >> y; if (y < min2) { min2 = y; } if (x > max2) { max2 = x; } } long long int x1 = (max1 - min2); long long int x2 = (max2 - min1); long long int x3 = max(x1, x2); if (x3 < 0) { cout << 0 << endl; } else { cout << x3 << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long in() { long long re = 0, f = 1; char x = getchar(); while (x < 0 || x > 9 ) { if (x == - ) f = -1; x = getchar(); } while (x >= 0 && x <= 9 ) re = re * 10 + x - 48, x = getchar(); return re * f; } void out(long long x) { if (x < 0) putchar( - ), x = -x; if (!x) { putchar( 0 ); return; } char z[21], ct = 0; while (x) { z[++ct] = x % 10 + 48, x /= 10; } while (ct) { putchar(z[ct]); --ct; } } const long long mod1 = 1e9 + 7; const long long mod2 = 998244353; const long long base1 = 3001; const long long base2 = 2333; long long upd(long long a, long long b) { return a < 0 ? a + b : a; } struct ull { long long x, y; ull operator-(const ull &b) const { return (ull){upd(x - b.x, mod1), upd(y - b.y, mod2)}; } ull operator+(const long long &b) const { return (ull){(x + b) % mod1, (y + b) % mod2}; } ull operator+(const ull &b) const { return (ull){(x + b.x) % mod1, (y + b.y) % mod2}; } ull operator*(const ull &b) const { return (ull){(x * b.x) % mod1, (y * b.y) % mod2}; } bool operator==(const ull &b) const { return x == b.x && y == b.y; } bool operator!=(const ull &b) const { return x != b.x || y != b.y; } } base; ull hs[1000010], pw[1000010]; ull geths(int l, int r) { int len = r - l + 1; ull re = hs[r] - hs[l - 1] * pw[len]; return re; } long long ls[200010], lt[200010]; char cs[200010], ct[200010]; long long S[500000], T[500000]; int n, m; int main() { n = in(); m = in(); for (int i = 1; i <= n; ++i) { scanf( %d-%c , &ls[i], &cs[i]); if (cs[i] == cs[i - 1]) { ls[i - 1] += ls[i]; --i; --n; } } for (int i = 1; i <= m; ++i) { scanf( %d-%c , <[i], &ct[i]); if (ct[i] == ct[i - 1]) { lt[i - 1] += lt[i]; --i; --m; } } if (m == 1) { char c = ct[1]; long long ans = 0; for (int i = 1; i <= n; ++i) if (cs[i] == c) ans = ans + max(0ll, ls[i] - lt[1] + 1); cout << ans << n ; return 0; } base = (ull){base1, base2}; int cnt1 = lt[1], cnt2 = lt[m], ch = ct[m]; for (int i = 1; i <= n; ++i) S[i * 2 - 1] = ls[i], S[i * 2] = cs[i]; T[1] = ct[1]; for (int i = 2; i < m; ++i) T[i * 2 - 2] = lt[i], T[i * 2 - 1] = ct[i]; int tlen = m * 2 - 3; ull hT = (ull){0, 0}; for (int i = 1; i <= tlen; ++i) hT = hT * base + (long long)T[i]; pw[0].x = pw[0].y = 1; for (int ed = max(tlen, n * 2), i = 1; i <= ed; ++i) pw[i] = pw[i - 1] * base; for (int i = 1; i <= n * 2; ++i) hs[i] = hs[i - 1] * base + (long long)S[i]; long long ans = 0; for (int i = 2; i + tlen + 1 <= n * 2; i += 2) { int l = i, r = i + tlen - 1; ull hS = geths(l, r); if (hS == hT) { if (S[l - 1] < cnt1) continue; if (S[r + 1] < cnt2) continue; if (S[r + 2] != ch) continue; ++ans; } } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int k[n][n]; for (int j = 0; j < n; j++) for (int i = 0; i < n; i++) k[i][j] = (i)*n + j + 1; for (int i = 0; i < n; i += 2) reverse(k[i], k[i] + n); for (int j = n - 1; j >= 0; j--) { for (int i = 0; i < n; i++) cout << k[i][j] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int luat_tot(vector<int>& attack, vector<int>& defense, multiset<int> carti); int luare(vector<int>& attack, multiset<int> carti); int main() { int n, m, c; char s[10]; vector<int> attack, defense; multiset<int> carti; cin >> n >> m; for (int i(0); i < n; i++) { cin >> s >> c; if (s[0] == A ) attack.push_back(c); else defense.push_back(c); } while (m--) { cin >> c; carti.insert(c); } sort(attack.rbegin(), attack.rend()); int r(luat_tot(attack, defense, carti)); vector<int> attack_part; while (!attack.empty()) { attack_part.push_back(attack.back()); attack.pop_back(); sort(attack_part.rbegin(), attack_part.rend()); r = max(r, luare(attack_part, carti)); } cout << r; return 0; } int luare(vector<int>& attack, multiset<int> carti) { int r(0); for (auto i : attack) { if (carti.empty()) return 0; if (*carti.rbegin() < i) return 0; r += *carti.rbegin() - i; carti.erase(carti.find(*carti.rbegin())); } return r; } int luat_tot(vector<int>& attack, vector<int>& defense, multiset<int> carti) { int r(0); for (auto i : defense) { if (carti.empty()) return 0; if (carti.upper_bound(i) == carti.end()) return 0; carti.erase(carti.upper_bound(i)); } for (auto i : attack) { if (carti.empty() || *carti.rbegin() < i) return 0; r += *carti.rbegin() - i; carti.erase(carti.find(*carti.rbegin())); } for (auto i : carti) r += i; return r; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) using namespace std; constexpr long long mod = 998244353; const long long INF = mod * mod; const long double eps = 1e-12; const long double pi = acosl(-1.0); long long mod_pow(long long x, long long n, long long m = mod) { if (n < 0) { long long res = mod_pow(x, -n, m); return mod_pow(res, m - 2, m); } if (abs(x) >= m) x %= m; if (x < 0) x += m; long long res = 1; while (n) { if (n & 1) res = res * x % m; x = x * x % m; n >>= 1; } return res; } struct modint { long long n; modint() : n(0) { ; } modint(long long m) : n(m) { if (n >= mod) n %= mod; else if (n < 0) n = (n % mod + mod) % mod; } operator int() { return n; } }; bool operator==(modint a, modint b) { return a.n == b.n; } modint operator+=(modint& a, modint b) { a.n += b.n; if (a.n >= mod) a.n -= mod; return a; } modint operator-=(modint& a, modint b) { a.n -= b.n; if (a.n < 0) a.n += mod; return a; } modint operator*=(modint& a, modint b) { a.n = ((long long)a.n * b.n) % mod; return a; } modint operator+(modint a, modint b) { return a += b; } modint operator-(modint a, modint b) { return a -= b; } modint operator*(modint a, modint b) { return a *= b; } modint operator^(modint a, long long n) { if (n == 0) return modint(1); modint res = (a * a) ^ (n / 2); if (n % 2) res = res * a; return res; } long long inv(long long a, long long p) { return (a == 1 ? 1 : (1 - p * inv(p % a, a)) / a + p); } modint operator/(modint a, modint b) { return a * modint(inv(b, mod)); } modint operator/=(modint& a, modint b) { a = a / b; return a; } const int max_n = 1 << 18; modint fact[max_n], factinv[max_n]; void init_f() { fact[0] = modint(1); for (int i = 0; i < max_n - 1; i++) { fact[i + 1] = fact[i] * modint(i + 1); } factinv[max_n - 1] = modint(1) / fact[max_n - 1]; for (int i = max_n - 2; i >= 0; i--) { factinv[i] = factinv[i + 1] * modint(i + 1); } } modint comb(int a, int b) { if (a < 0 || b < 0 || a < b) return 0; return fact[a] * factinv[b] * factinv[a - b]; } modint combP(int a, int b) { if (a < 0 || b < 0 || a < b) return 0; return fact[a] * factinv[a - b]; } struct uf { private: vector<int> par, ran; public: uf(int n) { par.resize(n, 0); ran.resize(n, 0); for (int i = 0; i < n; i++) { par[i] = i; } } int find(int x) { if (par[x] == x) return x; else return par[x] = find(par[x]); } void unite(int x, int y) { x = find(x), y = find(y); if (x == y) return; if (ran[x] < ran[y]) { par[x] = y; } else { par[y] = x; if (ran[x] == ran[y]) ran[x]++; } } bool same(int x, int y) { return find(x) == find(y); } }; const int mn = 1000005; vector<int> ps; vector<int> chp[mn]; bool isp[mn]; void init() { fill(isp + 2, isp + mn, true); for (int i = 2; i < mn; i++) { if (!isp[i]) continue; ps.push_back(i); chp[i].push_back(i); for (int j = 2 * i; j < mn; j += i) { isp[j] = false; chp[j].push_back(i); } } } void solve() { int n, q; cin >> n >> q; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<int> trans(mn); for (int i = 0; i < ps.size(); i++) trans[ps[i]] = i; uf u(ps.size()); for (int i = 0; i < n; i++) { int pre = -1; for (int j = 0; j < chp[a[i]].size(); j++) { int id = trans[chp[a[i]][j]]; if (pre >= 0) { u.unite(id, pre); } pre = id; } } vector<unordered_map<int, int>> mp(ps.size()); for (int i = 0; i < n; i++) { vector<int> ids; ids.push_back(u.find(trans[chp[a[i]][0]])); for (int p : chp[a[i] + 1]) { int id = trans[p]; id = u.find(id); ids.push_back(id); } for (int j = 0; j < ids.size(); j++) for (int k = j + 1; k < ids.size(); k++) { int a = ids[j]; int b = ids[k]; if (a == b) continue; if (a > b) swap(a, b); mp[a][b] = true; } } for (int i = 0; i < q; i++) { int s, t; cin >> s >> t; s--; t--; s = trans[chp[a[s]][0]]; t = trans[chp[a[t]][0]]; s = u.find(s); t = u.find(t); if (s == t) { cout << 0 << n ; } else { if (s > t) swap(s, t); if (mp[s][t]) { cout << 1 << n ; } else { cout << 2 << n ; } } } } signed main() { ios::sync_with_stdio(false); cin.tie(0); init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int SIZE = 500 + 10; int data[SIZE]; map<int, int> all_nums; int n; bool used[SIZE * SIZE]; int gcd(int a, int b) { if (a % b == 0) return b; return gcd(b, a % b); } void make_data() { srand(time(0)); int n = 5; int data[SIZE]; for (int i = 0; i < n; i++) data[i] = (rand() % (10)); FILE* output = fopen( input.txt , w ); fprintf(output, %d n , n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) fprintf(output, %d , gcd(data[i], data[j])); fclose(output); } int main() { cin >> n; int val; for (int i = 0; i < n * n; i++) { cin >> val; all_nums[val]++; } auto iter = all_nums.rbegin(); data[n - 1] = iter->first; iter->second--; int curtop = n - 1; for (int i = 0; i < n - 1; i++) { while (all_nums.rbegin()->second == 0) { all_nums.erase(all_nums.find(all_nums.rbegin()->first)); } data[curtop - 1] = all_nums.rbegin()->first; all_nums.rbegin()->second--; for (int k = curtop; k < n; k++) all_nums[gcd(data[curtop - 1], data[k])] -= 2; curtop--; } for (int i = 0; i < n; i++) cout << data[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<long long> ad[200009]; long long vis[200009]; long long cnt, ans; void dfs(int u) { vis[u] = 1; cnt++; for (auto x : ad[u]) { if (!vis[x]) dfs(x); } } int main() { long long i, j, k, l, m, n, u, v; cin >> n >> k; for (i = 0; i < k; i++) { cin >> u >> v; ad[u].push_back(v); ad[v].push_back(u); } for (i = 1; i <= n; i++) { if (ad[i].size() == 0) continue; if (!vis[i]) { cnt = 0; dfs(i); cnt--; ans += cnt; } } cout << k - ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int n, m, q; int nxt[100001]; char s[100001], t[100001]; int temp[100001]; int l, r; bool check(int u) { for (int i = 0; i < m; ++i) { if (s[u + i] != t[i]) return 0; } return 1; } void pre_do() { for (int i = 1; i <= n - m + 1; i++) { temp[i] += check(i); } } void putin() { cin >> n >> m >> q; scanf( %s%s , s + 1, t); } int main() { putin(); pre_do(); for (int i = 1; i <= n; i++) { temp[i] += temp[i - 1]; } for (int i = 1; i <= q; i++) { cin >> l >> r; if (r - l + 1 < m) cout << 0 << endl; else cout << temp[r - m + 1] - temp[l - 1] << endl; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:12:26 04/22/2016
// Design Name:
// Module Name: alarm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alarm(
output [3:0] alarmHourTens, alarmHourMu, alarmMinTens, alarmMinMu,
input setM, setH, clk10hz
);
wire rcoM__, rcoM_, rcoH__, rcoH_, minClkRate, hourClkRate, nand3, nand5;
parameter dGND = 4'b0000;
parameter h = 1'b1;
assign nand3 = !(alarmMinTens[0] & alarmMinTens[2] & rcoM__);
assign nand5 = !(!setH & alarmHourMu[0] & alarmHourMu[1] & alarmHourTens[1]); //24 reset
// assign clkMinSelected = (minClkRate & setButton) |((!setButton) & clk10hz);
// assign clkHourSelected = (hourClkRate & setButton)|((!setButton) & clk10hz);
c74160 m__(alarmMinMu, rcoM__, dGND, !setM, h, clk10hz, h);
c74160 m_(alarmMinTens, rcoM_, dGND, rcoM__, nand3, clk10hz, h);
c74160 h__(alarmHourMu, rcoH__, dGND, !setH, nand5, clk10hz, h);
c74160 h_(alarmHourTens, rcoH_, dGND, rcoH__, nand5, clk10hz, h);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long sum = 0; vector<long long> a(n); for (long long i = 0; i < n; ++i) { cin >> a[i]; sum += a[i]; } vector<long long> prime; for (long long i = 2; i * i <= sum; ++i) { if (sum % i == 0) { prime.push_back(i); while (sum % i == 0) sum /= i; } } if (sum > 1) prime.push_back(sum); long long ans = LLONG_MAX; for (long long i : prime) { long long now = 0; long long cnt = 0; for (long long j = 0; j < n; ++j) { cnt += a[j]; now += min(cnt % i, i - cnt % i); } ans = min(ans, now); } cout << (ans == LLONG_MAX ? -1 : ans) << endl; return 0; }
|
//************************************************************
// CHECKS
// ______ _ _ _______ ______ _ _ _
// / _____) | | (_______) _____) | / ) | |
// | / | |__ | |_____ | / | | / / \ \
// | | | __)| | ___)| | | |< < \ \
// | \_____| | | | |____| \_____| | \ \ _____) )
// \______)_| |_|_______)______)_| \_|______/
//
//
// Logging.
//
// Allow you to see, in time, when values are transmitted and received.
//
//
// For this test, the number of cycles on the slowest clock should match the
// number of words transmitted plus a small constant.
//
`include "bsg_defines.v"
module test_bsg_comm_link_checker #(parameter `BSG_INV_PARAM(channel_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(ring_bytes_p)
, parameter `BSG_INV_PARAM(check_bytes_p)
, parameter `BSG_INV_PARAM(verbose_p)
, parameter `BSG_INV_PARAM(iterations_p)
, parameter `BSG_INV_PARAM(core_0_period_p)
, parameter `BSG_INV_PARAM(core_1_period_p)
, parameter `BSG_INV_PARAM(io_master_0_period_p)
, parameter `BSG_INV_PARAM(io_master_1_period_p)
, parameter chip_num_p=0
, parameter node_num_p=0
, parameter `BSG_INV_PARAM(cycle_counter_width_p)
, parameter skip_checks_p=0
)
(input clk
, input valid_in
, input ready_in
, input yumi_out
, input [ring_bytes_p*channel_width_p-1:0] data_in
, input [ring_bytes_p*channel_width_p-1:0] data_out
, input async_reset
, input slave_reset_tline
// , input [num_channels_p-1:0] io_clk_tline
, input [num_channels_p-1:0] io_valid_tline
, input [channel_width_p-1:0] io_data_tline [num_channels_p-1:0]
// , input [num_channels_p-1:0] token_clk_tline
, input [cycle_counter_width_p-1:0] core_ctr[1:0]
, input [cycle_counter_width_p-1:0] io_ctr [1:0]
, output done_o
);
localparam channel_verbose_p = 1'b0;
// non-synthesizeable; testing only
logic [5:0] top_bits = 0;
logic [31:0] words_received_r ;
wire [check_bytes_p*channel_width_p-1:0] data_in_check;
genvar j;
always_ff @(negedge clk)
if (async_reset)
words_received_r <= 0;
else
words_received_r <= words_received_r + (valid_in & ready_in);
logic done_r;
assign done_o = done_r;
test_bsg_data_gen #(.channel_width_p(channel_width_p)
,.num_channels_p(check_bytes_p)
) tbdg_receive
(.clk_i(clk )
,.reset_i(async_reset )
,.yumi_i (ready_in & valid_in)
,.o (data_in_check)
);
always_ff @(negedge clk)
begin
if (valid_in & ready_in)
begin
if (verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1]
, " ## chip %1d node %1d recv %-d, %x"
, chip_num_p, node_num_p, words_received_r, data_in);
if (!skip_checks_p)
assert (data_in_check == data_in[check_bytes_p*channel_width_p-1:0])
else
begin
$error("## transmission error %x, %x, difference = %x"
, data_in_check, data_in, data_in_check ^ data_in);
// $finish();
end
// we only terminate when all nodes on core 0 have received all the words
if ((words_received_r
>=
(iterations_p << (channel_width_p-$clog2(num_channels_p)))
) & (chip_num_p == 0) & ~done_r)
begin
done_r <= 1'b1;
$display("## DONE node = %-d words = %-d CHANNEL_BITWIDTH = %-d",node_num_p,words_received_r,channel_width_p
," RING_BYTES = %-d;",ring_bytes_p
," NUM_CHAN = %-d;",num_channels_p
," C0 = %-d;",core_0_period_p
," I0 = %-d; I1 = %-d;",io_master_0_period_p
,io_master_1_period_p
," C1 = %-d;",core_1_period_p,
," (Cycles Per Word) "
, real'(core_ctr[0])
/ real'(words_received_r)
," ", real'(io_ctr [0])
/ real'(words_received_r)
," ", real'(io_ctr [1])
/ real'(words_received_r)
," ", real'(core_ctr[1])
/ real'(words_received_r)
);
end
end
if (yumi_out)
if (verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1]
, " ## chip %1d node %1d sent %x",chip_num_p, node_num_p, data_out);
if (async_reset) done_r <= 1'b0;
end // always_ff @
`ifdef BSG_IP_CORES_UNIT_TEST
`define TEST_BSG_COMM_LINK_CHECKER_PREFIX core[chip_num_p].
`else
`define TEST_BSG_COMM_LINK_CHECKER_PREFIX
`endif
// avoid redundant printing of channel info
if (node_num_p == 0)
for (j = 0; j < num_channels_p; j=j+1)
begin
// in parent
always @(slave_reset_tline or io_valid_tline[j] or io_data_tline[j]
or `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.pos_credit_ctr.r_free_credits_r
or `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.neg_credit_ctr.r_free_credits_r
)
if (verbose_p)
begin
if (channel_verbose_p)
$display("## SR=%1d", slave_reset_tline
, core_ctr[0], io_ctr[0], core_ctr[1], io_ctr[1],
" ## chip %1d channel %1d", chip_num_p, j, " (p,n)=(%2d %2d)"
, `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.pos_credit_ctr.r_free_credits_r
, `TEST_BSG_COMM_LINK_CHECKER_PREFIX guts.comm_link.ch[j].sso.neg_credit_ctr.r_free_credits_r
, " ## io xmit %1d,%x"
, io_valid_tline[j],io_data_tline[j]
);
end
end // for (j = 0; j < num_channels_p; j=j+1)
endmodule
`BSG_ABSTRACT_MODULE(test_bsg_comm_link_checker)
|
#include <bits/stdc++.h> using namespace std; vector<long long> z; const long long N = 5e3 + 7, M1 = 1e9 + 7, M2 = 1e9 + 9, b1 = 127, b2 = 239; long long maxi1[N], maxi2[N], maxx[N]; pair<long long, long long> h1[N], h2[N]; pair<long long, long long> poww[N]; string best; long long mod(long long x, long long m) { x %= m; if (x < 0) x += m; return x; } pair<long long, long long> get_h(long long l, long long r) { long long res1 = mod(h1[r].first - h1[l - 1].first * poww[r - l + 1].first, M1); long long res2 = mod(h1[r].second - h1[l - 1].second * poww[r - l + 1].second, M2); return {res1, res2}; } pair<long long, long long> get_h2(long long l, long long r) { long long res1 = mod(h2[r].first - h2[l - 1].first * poww[r - l + 1].first, M1); long long res2 = mod(h2[r].second - h2[l - 1].second * poww[r - l + 1].second, M2); return {res1, res2}; } void solve(string s) { long long n = s.length(); string t = s; long long ser = (n + 1) / 2; long long len = 0; while (len != n && s[len] == s[n - len - 1]) { len++; } if (len == n) { best = s; return; } if (2 * len > (long long)best.size()) { best = ; for (long long i = 0; i < len; i++) best += s[i]; for (long long i = len - 1; i >= 0; i--) best += s[i]; } for (long long i = 0; i < ser; i++) { maxi1[i] = -1; long long l = i, r = i; while (l >= 0 && r < n && s[l] == s[r]) { l--; r++; maxi1[i] += 2; if (l < len) { long long curlen = maxi1[i] + 2 * (l + 1); if (curlen > (long long)best.size()) { best = ; for (long long j = 0; j < r; j++) { best += s[j]; } for (long long j = l; j >= 0; j--) { best += s[j]; } } } } } if (n % 2 == 1) ser--; for (long long i = 0; i < ser; i++) { maxi2[i] = 0; long long l = i, r = i + 1; while (l >= 0 && r < n && s[l] == s[r]) { l--; r++; maxi2[i] += 2; if (l < len) { long long curlen = maxi2[i] + 2 * (l + 1); if (curlen > (long long)best.size()) { best = ; for (long long j = 0; j < r; j++) { best += s[j]; } for (long long j = l; j >= 0; j--) { best += s[j]; } } } } } } signed main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; for (long long i = 0; i < t; i++) { string s; cin >> s; best = s[0]; solve(s); reverse(s.begin(), s.end()); solve(s); cout << best << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; bool vis[200005]; vector<int> v[200005], ak, d1, dn; vector<int> bfs(int n) { queue<int> q; vector<int> dis(200005); q.push(n); vis[n] = true; dis[n] = 0; while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < v[x].size(); i++) { int u = v[x][i]; if (vis[u] == false) { vis[u] = true; dis[u] = dis[x] + 1; q.push(u); } } } return dis; } bool cmp(int x, int y) { return d1[x] < d1[y]; } int main() { int n, m, k, n1, n2, sp, ans = 0; scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < k; i++) { scanf( %d , &sp); ak.push_back(sp); } for (int i = 0; i < m; i++) { scanf( %d %d , &n1, &n2); v[n1].push_back(n2); v[n2].push_back(n1); } d1 = bfs(1); memset(vis, false, sizeof(vis)); dn = bfs(n); sort(ak.begin(), ak.end(), cmp); for (int i = 1; i < ak.size(); i++) { int x = ak[i - 1]; int y = ak[i]; ans = max(ans, d1[x] + 1 + dn[y]); } ans = min(ans, d1[n]); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, x, y; cin >> n >> x >> y; long long chis = y - n + 1; if (n - 1 + chis * chis >= x && chis > 0) { for (long long i = 0; i < n - 1; i++) cout << 1 << n ; cout << chis; } else cout << -1 ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFSBP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_SYMBOL_V
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lp20khz_1MSa_iir_filter
`include "lp20khz_1MSa_iir_filter.v"
`define FIN "tb_tmp/data.in"
`define FOUT "tb_tmp/data.filtered"
module lp20khz_1MSa_iir_filter_tb;
integer fin, fout, r;
reg clk;
reg [7:0] adc_d;
wire data_rdy;
wire [7:0] adc_filtered;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout = $fopen(`FOUT, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
always @(posedge clk)
if (data_rdy) begin
if ($time > 1)
r = $fputc(adc_filtered, fout);
if (!$feof(fin))
adc_d <= $fgetc(fin);
else begin
$fclose(fin);
$fclose(fout);
$finish;
end
end
// module to test
lp20khz_1MSa_iir_filter filter(clk, adc_d, data_rdy, adc_filtered);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_0_V
`define SKY130_FD_SC_LP__AND4_0_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_0 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4_0 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_0_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vpii = vector<pair<int, int>>; using vc = vector<char>; using vvc = vector<vc>; long long binpow(long long a, long long n) { long long res = 1; while (n) { if (n & 1) res *= a; a *= a; n >>= 1; } return res; } bool prime(long long n) { for (long long i = 2; i <= sqrt(n); i++) { if (n % i == 0) return false; } return true; } int gcd(int a, int b) { while (b) { a %= b; swap(a, b); } return a; } long long lcm(int a, int b) { return a / gcd(a, b) * b; } template <class T1, class T2> void Cin_vector(vector<T1>& a, T2 n) { for (auto& val : a) { std::cin >> val; } } template <class T1, class T2> void Cout_vector(vector<T1>& a, T2 n) { for (auto& val : a) { std::cout << val << ; } } template <class T1, class T2, class T3> void Cin_matrix(vector<vector<T1>>& a, T2 n, T3 m) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { std::cin >> a[i][j]; } } } template <class T1, class T2, class T3> void Cout_matrix(vector<vector<T1>>& a, T2 n, T3 m) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { std::cout << a[i][j] << ; } std::cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); vector<string> otvet = { F , M , S }; vector<string> strs; map<string, int> counts; for (int i = 0; i < 3; i++) { string s; std::cin >> s; strs.push_back(s); counts[s]++; } int maxs = 0; string temp; for (auto& [strings, cnt] : counts) { if (cnt > maxs) { maxs = cnt; temp = strings; } } if (maxs == 1 || maxs == 3) { std::cout << ? ; } else { string c; for (auto& [strings, cnt] : counts) { if (strings != temp) { c = strings; } } if (temp == rock && c == paper || temp == paper && c == scissors || temp == scissors && c == rock ) { for (int i = 0; i < 3; i++) { if (c == strs[i]) { std::cout << otvet[i]; break; } } } else { std::cout << ? ; } } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlybuf4s18kapwr (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 21:28:51 04/04/2016
// Design Name:
// Module Name: contador_AD_HH_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_HH_2dig
(
input wire clk,
input wire reset,
input wire [3:0]en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_HH//Dígitos BCD ya concatenados hacia los registros(8 bits)
);
localparam N = 5; // Para definir el número de bits del contador (hasta 23->5 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 5'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 3)
begin
if (enUP)
begin
if (q_act >= 5'd23) q_next = 5'd0;
else q_next = q_act + 5'd1;
end
else if (enDOWN)
begin
if (q_act == 5'd0) q_next = 5'd23;
else q_next = q_act - 5'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_HH = {digit1,digit0};
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
// pn interface
adc_pnseq_sel,
adc_pn_err,
adc_pn_oos);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_err;
output adc_pn_oos;
// internal registers
reg [47:0] adc_pn_data_pn = 'd0;
// internal signals
wire [47:0] adc_pn_data_pn_s;
wire [47:0] adc_data_inv_s;
// prbs pn9 function
function [47:0] pn9;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[8] ^ din[4];
dout[46] = din[7] ^ din[3];
dout[45] = din[6] ^ din[2];
dout[44] = din[5] ^ din[1];
dout[43] = din[4] ^ din[0];
dout[42] = din[3] ^ din[8] ^ din[4];
dout[41] = din[2] ^ din[7] ^ din[3];
dout[40] = din[1] ^ din[6] ^ din[2];
dout[39] = din[0] ^ din[5] ^ din[1];
dout[38] = din[8] ^ din[0];
dout[37] = din[7] ^ din[8] ^ din[4];
dout[36] = din[6] ^ din[7] ^ din[3];
dout[35] = din[5] ^ din[6] ^ din[2];
dout[34] = din[4] ^ din[5] ^ din[1];
dout[33] = din[3] ^ din[4] ^ din[0];
dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4];
dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3];
dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2];
dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1];
dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0];
dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4];
dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3];
dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2];
dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1];
dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0];
dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4];
dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3];
dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2];
dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1];
dout[18] = din[6] ^ din[8] ^ din[0];
dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3];
dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2];
dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1];
dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0];
dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4];
dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3];
dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2];
dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1];
dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0];
dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8];
dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7];
dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6];
dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5];
dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1];
dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0];
dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4];
dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// prbs pn23 function
function [47:0] pn23;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[22] ^ din[17];
dout[46] = din[21] ^ din[16];
dout[45] = din[20] ^ din[15];
dout[44] = din[19] ^ din[14];
dout[43] = din[18] ^ din[13];
dout[42] = din[17] ^ din[12];
dout[41] = din[16] ^ din[11];
dout[40] = din[15] ^ din[10];
dout[39] = din[14] ^ din[9];
dout[38] = din[13] ^ din[8];
dout[37] = din[12] ^ din[7];
dout[36] = din[11] ^ din[6];
dout[35] = din[10] ^ din[5];
dout[34] = din[9] ^ din[4];
dout[33] = din[8] ^ din[3];
dout[32] = din[7] ^ din[2];
dout[31] = din[6] ^ din[1];
dout[30] = din[5] ^ din[0];
dout[29] = din[4] ^ din[22] ^ din[17];
dout[28] = din[3] ^ din[21] ^ din[16];
dout[27] = din[2] ^ din[20] ^ din[15];
dout[26] = din[1] ^ din[19] ^ din[14];
dout[25] = din[0] ^ din[18] ^ din[13];
dout[24] = din[22] ^ din[12];
dout[23] = din[21] ^ din[11];
dout[22] = din[20] ^ din[10];
dout[21] = din[19] ^ din[9];
dout[20] = din[18] ^ din[8];
dout[19] = din[17] ^ din[7];
dout[18] = din[16] ^ din[6];
dout[17] = din[15] ^ din[5];
dout[16] = din[14] ^ din[4];
dout[15] = din[13] ^ din[3];
dout[14] = din[12] ^ din[2];
dout[13] = din[11] ^ din[1];
dout[12] = din[10] ^ din[0];
dout[11] = din[9] ^ din[22] ^ din[17];
dout[10] = din[8] ^ din[21] ^ din[16];
dout[9] = din[7] ^ din[20] ^ din[15];
dout[8] = din[6] ^ din[19] ^ din[14];
dout[7] = din[5] ^ din[18] ^ din[13];
dout[6] = din[4] ^ din[17] ^ din[12];
dout[5] = din[3] ^ din[16] ^ din[11];
dout[4] = din[2] ^ din[15] ^ din[10];
dout[3] = din[1] ^ din[14] ^ din[9];
dout[2] = din[0] ^ din[13] ^ din[8];
dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7];
dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6];
pn23 = dout;
end
endfunction
// pn sequence selection
assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]};
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn;
always @(posedge adc_clk) begin
if(adc_pnseq_sel == 4'b0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_data_inv_s),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 20 * 1000 + 200; const int INF = 1000 * 1000 * 1000; int d[N]; int n, m; inline void read() { scanf( %d %d , &n, &m); } inline void solve() { for (int i = 0; i < N; i++) d[i] = INF; queue<int> q; q.push(n); d[n] = 0; while (!q.empty()) { int v = q.front(); q.pop(); if (v * 2 <= 20 * 1000 && d[v * 2] == INF) { q.push(v * 2); d[v * 2] = d[v] + 1; } if (v - 1 > 0 && d[v - 1] == INF) { q.push(v - 1); d[v - 1] = d[v] + 1; } } cout << d[m]; } int main() { read(); solve(); return 0; }
|
module top(CLCK, SCL, SDA, CNT1A, CNT1B, CNT2A,CNT2B, CNT3A, CNT3B, CNT4A, CNT4B);
input CLCK;
input SCL;
inout SDA;
input CNT1A;
input CNT1B;
input CNT2A;
input CNT2B;
input CNT3A;
input CNT3B;
input CNT4A;
input CNT4B;
wire[15:0] CNTR1;
wire[15:0] CNTR2;
wire[15:0] CNTR3;
wire[15:0] CNTR4;
wire[7:0] CMD;
wire[1:0] TEND;
quad counter1(.clk (CLCK),
.quadA (CNT1A),
.quadB (CNT1B),
.count (CNTR1),
.CMD (CMD),
.TEND (TEND));
quad counter2(.clk (CLCK),
.quadA (CNT2A),
.quadB (CNT2B),
.count (CNTR2),
.CMD (CMD),
.TEND (TEND));
quad counter3(.clk (CLCK),
.quadA (CNT3A),
.quadB (CNT3B),
.count (CNTR3),
.CMD (CMD),
.TEND (TEND));
quad counter4(.clk (CLCK),
.quadA (CNT4A),
.quadB (CNT4B),
.count (CNTR4),
.CMD (CMD),
.TEND (TEND));
I2CSlave(.CLCK (CLCK),
.SCL (SCL),
.SDA (SDA),
.CNTR1 (CNTR1),
.CNTR2 (CNTR2),
.CNTR3 (CNTR3),
.CNTR4 (CNTR4),
.CMD (CMD),
.TEND (TEND));
endmodule
|
#include <bits/stdc++.h> using namespace std; struct second { int l, r, x, id; bool operator<(const second a) const { if (r < a.r) return 1; if (r > a.r) return 0; return id < a.id; } } s[10005]; int cmp(const second a, const second b) { if (a.l != b.l) return a.l < b.l; return a.r < b.r; } set<second> st; int a[10005]; int dp1[10005], dp2[10005]; bool ans[10005]; int main(void) { int n, q; scanf( %d%d , &n, &q); int i; for (i = 0; i < q; i++) { scanf( %d%d%d , &s[i].l, &s[i].r, &s[i].x); s[i].id = i; } sort(s, s + q, cmp); int j = 0; dp1[0] = dp2[0] = 1; for (i = 1; i <= n; i++) { bool modi = false; while (j < q && s[j].l <= i) { st.insert(s[j]); int x = s[j].x; for (int l = n; l >= x; l--) { dp1[l] += dp1[l - x]; dp1[l] %= 19950527; dp2[l] += dp2[l - x]; } modi = true; j++; } while (!st.empty()) { auto it = st.begin(); if (it->r < i) { int x = it->x; for (int l = x; l <= n; l++) { dp1[l] -= dp1[l - x]; dp1[l] %= 19950527; dp2[l] -= dp2[l - x]; } st.erase(it); modi = true; } else { break; } } if (!modi) continue; for (int l = 1; l <= n; l++) if (dp1[l] || dp2[l]) ans[l] = true; } int cnt = 0; for (i = 1; i <= n; i++) if (ans[i]) cnt++; printf( %d n , cnt); for (i = 1; i <= n; i++) if (ans[i]) printf( %d , i); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/RAT_ScratchRam_0_0_sim_netlist.v
// Design : RAT_ScratchRam_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_ScratchRam_0_0,ScratchRam,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ScratchRam,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_ScratchRam_0_0
(DATA_IN,
DATA_OUT,
ADDR,
WE,
CLK);
input [9:0]DATA_IN;
output [9:0]DATA_OUT;
input [7:0]ADDR;
input WE;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
wire [7:0]ADDR;
wire CLK;
wire [9:0]DATA_IN;
wire [9:0]DATA_OUT;
wire WE;
RAT_ScratchRam_0_0_ScratchRam U0
(.ADDR(ADDR),
.CLK(CLK),
.DATA_IN(DATA_IN),
.DATA_OUT(DATA_OUT),
.WE(WE));
endmodule
(* ORIG_REF_NAME = "ScratchRam" *)
module RAT_ScratchRam_0_0_ScratchRam
(DATA_OUT,
CLK,
DATA_IN,
WE,
ADDR);
output [9:0]DATA_OUT;
input CLK;
input [9:0]DATA_IN;
input WE;
input [7:0]ADDR;
wire [7:0]ADDR;
wire CLK;
wire [9:0]DATA_IN;
wire [9:0]DATA_OUT;
wire WE;
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_0_0
(.A(ADDR),
.D(DATA_IN[0]),
.O(DATA_OUT[0]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_1_1
(.A(ADDR),
.D(DATA_IN[1]),
.O(DATA_OUT[1]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_2_2
(.A(ADDR),
.D(DATA_IN[2]),
.O(DATA_OUT[2]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_3_3
(.A(ADDR),
.D(DATA_IN[3]),
.O(DATA_OUT[3]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_4_4
(.A(ADDR),
.D(DATA_IN[4]),
.O(DATA_OUT[4]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_5_5
(.A(ADDR),
.D(DATA_IN[5]),
.O(DATA_OUT[5]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_6_6
(.A(ADDR),
.D(DATA_IN[6]),
.O(DATA_OUT[6]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_7_7
(.A(ADDR),
.D(DATA_IN[7]),
.O(DATA_OUT[7]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_8_8
(.A(ADDR),
.D(DATA_IN[8]),
.O(DATA_OUT[8]),
.WCLK(CLK),
.WE(WE));
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
RAM_reg_0_255_9_9
(.A(ADDR),
.D(DATA_IN[9]),
.O(DATA_OUT[9]),
.WCLK(CLK),
.WE(WE));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int n, k; long long m, f[1005][105][2]; long long dfs(int Index, int y, int now, int flag) { if (Index > n) return (flag == 0); if (f[Index][y][flag] != -1) return f[Index][y][flag]; int st = Index == n ? 1 : 0, y1; long long res = 0; for (int i = st; i <= 9; i++) { y1 = (y + now * i % k) % k; res = (res + dfs(Index + 1, y1, now * 10 % k, (flag && (y1 != 0 || !i)))) % m; } f[Index][y][flag] = res; return res; } int main() { scanf( %d %d %lld , &n, &k, &m); memset(f, -1, sizeof f); printf( %lld n , dfs(1, 0, 1, 1)); return 0; }
|
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 15.0.2 Build 153 07/15/2015 SJ Web Edition"
// CREATED "Tue Nov 17 20:37:33 2015"
module text2_export(
RESET,
CLOCK_50,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HSYNC,
VGA_VSYNC
);
input wire RESET;
input wire CLOCK_50;
output wire VGA_RED;
output wire VGA_GREEN;
output wire VGA_BLUE;
output wire VGA_HSYNC;
output wire VGA_VSYNC;
wire [10:0] SYNTHESIZED_WIRE_0;
wire [10:0] SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire [2:0] SYNTHESIZED_WIRE_4;
assign SYNTHESIZED_WIRE_2 = ~RESET;
demo2_text b2v_text(
.clk(CLOCK_50),
.PIXEL_H(SYNTHESIZED_WIRE_0),
.PIXEL_V(SYNTHESIZED_WIRE_1),
.PIXEL(SYNTHESIZED_WIRE_4));
vga_driver b2v_vga(
.RESET(SYNTHESIZED_WIRE_2),
.VGA_CLOCK(SYNTHESIZED_WIRE_3),
.PIXEL(SYNTHESIZED_WIRE_4),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HS(VGA_HSYNC),
.VGA_VS(VGA_VSYNC),
.PIXEL_H(SYNTHESIZED_WIRE_0),
.PIXEL_V(SYNTHESIZED_WIRE_1));
vga_clock b2v_vga_clock(
.CLOCK_50(CLOCK_50),
.CLOCK_25(SYNTHESIZED_WIRE_3));
endmodule
|
#include <bits/stdc++.h> using namespace std; using dd = long double; struct Tree { struct Node { dd mul; dd add; dd sum; Node() : mul(1), add(0), sum(0) {} }; int S; vector<Node> drz; void update(int v) { drz[v].sum = drz[2 * v].sum + drz[2 * v + 1].sum; } Tree(const vector<int>& tab) { int n = tab.size(); S = 1; while (S < n) { S *= 2; } drz.resize(2 * S); for (int i = 0; i < n; i++) { drz[i + S].sum = tab[i]; } for (int v = S - 1; v; v--) { update(v); } } void receive(int v, int len, dd mul, dd add) { drz[v].sum = drz[v].sum * mul + add * len; drz[v].mul *= mul; drz[v].add = drz[v].add * mul + add; } void push(int v, int len) { dd mul = drz[v].mul; dd add = drz[v].add; receive(2 * v, len / 2, mul, add); receive(2 * v + 1, len / 2, mul, add); drz[v].mul = 1; drz[v].add = 0; } void mul_add_rec(int v, int vl, int vr, int l, int r, dd mul, dd add) { if (vl > r || l > vr) { return; } if (l <= vl && vr <= r) { receive(v, vr - vl + 1, mul, add); return; } push(v, vr - vl + 1); int vc = (vl + vr) / 2; mul_add_rec(2 * v, vl, vc, l, r, mul, add); mul_add_rec(2 * v + 1, vc + 1, vr, l, r, mul, add); update(v); } void mul_add(int l, int r, dd mul, dd add) { mul_add_rec(1, 0, S - 1, l, r, mul, add); } dd sum_rec(int v, int vl, int vr, int l, int r) { if (vl > r || l > vr) { return 0; } if (l <= vl && vr <= r) { return drz[v].sum; } push(v, vr - vl + 1); int vc = (vl + vr) / 2; return sum_rec(2 * v, vl, vc, l, r) + sum_rec(2 * v + 1, vc + 1, vr, l, r); } dd sum(int l, int r) { return sum_rec(1, 0, S - 1, l, r); } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, q; cin >> n >> q; vector<int> tab(n + 1); for (int i = 1; i <= n; i++) { cin >> tab[i]; } Tree tree(tab); while (q--) { int t; cin >> t; if (t == 1) { int l1, r1, l2, r2; cin >> l1 >> r1 >> l2 >> r2; auto sum1 = tree.sum(l1, r1); auto sum2 = tree.sum(l2, r2); int len1 = r1 - l1 + 1; int len2 = r2 - l2 + 1; tree.mul_add(l1, r1, 1.0 * (len1 - 1) / len1, 1.0 * sum2 / len1 / len2); tree.mul_add(l2, r2, 1.0 * (len2 - 1) / len2, 1.0 * sum1 / len1 / len2); } else { int l, r; cin >> l >> r; cout << setprecision(10) << fixed << tree.sum(l, r) << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> pairs[2 * 100000 + 10]; vector<int> adj[100000 + 10]; bool done[100000 + 10]; int result[100000 + 10]; void check(int N) { bool adj[N + 2][N + 2]; memset(adj, false, sizeof(adj)); for (int i = 1; i <= 2 * N; i++) { scanf( %d %d , &pairs[i].first, &pairs[i].second); adj[pairs[i].first][pairs[i].second] = true; adj[pairs[i].second][pairs[i].first] = true; } int A[N]; for (int i = 0; i < N; i++) A[i] = i + 1; do { bool found = true; for (int i = 0; i < N; i++) if (!(adj[A[i]][A[(i + 1) % N]] && adj[A[i]][A[(i + 2) % N]])) found = false; if (found) { for (int i = 0; i < N; i++) printf( %d , A[i]); printf( n ); return; } } while (next_permutation(A, A + N)); printf( -1 n ); } bool contains(int a, int b) { for (int i = 0; i < adj[a].size(); i++) if (adj[a][i] == b) return true; return false; } int main() { int N; scanf( %d , &N); if (N == 5 || N == 6) { check(N); return 0; } for (int i = 1; i <= 2 * N; i++) { scanf( %d %d , &pairs[i].first, &pairs[i].second); adj[pairs[i].first].push_back(pairs[i].second); adj[pairs[i].second].push_back(pairs[i].first); } int prev = 1; done[1] = true; result[0] = 1; int candidate[4 + 1], counts[4 + 1], num; for (int i = 1; i <= N; i++) if (adj[i].size() != 4) { printf( -1 n ); return 0; } for (int i = 1; i < N; i++) { int num = 0; for (int j = 0; j < adj[prev].size(); j++) candidate[num++] = adj[prev][j]; memset(counts, 0, sizeof(counts)); for (int j = 0; j < num; j++) for (int k = 0; k < adj[candidate[j]].size(); k++) for (int l = 0; l < num; l++) if (adj[candidate[j]][k] == candidate[l]) counts[l]++; for (int j = 0; j < num; j++) if (!done[candidate[j]] && counts[j] >= 2) { prev = candidate[j]; done[prev] = true; result[i] = prev; break; } } for (int i = 1; i <= N; i++) if (!done[i]) { printf( -1 n ); return 0; } bool found = true; for (int i = 0; i < N; i++) if (!(contains(result[i], result[(i + 1) % N]) && contains(result[i], result[(i + 2) % N]))) found = false; if (!found) { printf( -1 n ); return 0; } for (int i = 0; i < N; i++) printf( %d , result[i]); printf( n ); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_p_dst_data_stream_2_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_p_dst_data_stream_2_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_p_dst_data_stream_2_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_p_dst_data_stream_2_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, mod = 1e9 + 7; int head[N], nxt[N << 1], to[N << 1], num = 0, n, b[N], fa[N], q[N], DFN = 0, k[N], in[N]; inline void link(int x, int y) { nxt[++num] = head[x]; to[num] = y; head[x] = num; } inline int qm(int x, int k) { int sum = 1; while (k) { if (k & 1) sum = 1ll * sum * x % mod; x = 1ll * x * x % mod; k >>= 1; } return sum; } inline int inv(int x) { return qm(x, mod - 2); } inline void dfs(int x, int last) { q[++DFN] = x; for (int i = head[x]; i; i = nxt[i]) if (to[i] != last) fa[to[i]] = x, dfs(to[i], x); } int main() { int x, y, z; scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d%d , &x, &y, &z); x++; y++; link(x, y); link(y, x); k[x]++; k[y]++; b[x] += z; b[y] += z; } for (int i = 1; i <= n; i++) in[i] = k[i]; dfs(1, 1); for (int i = n; i >= 1; i--) { int x = q[i]; if (in[x] == 1) continue; k[fa[x]] = (k[fa[x]] - inv(k[x])) % mod; b[fa[x]] = (b[fa[x]] + 1ll * inv(k[x]) * b[x]) % mod; } b[1] = 1ll * b[1] * inv(k[1]) % mod; if (b[1] < 0) b[1] += mod; printf( %d n , b[1]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_PP_SYMBOL_V
|
/**
NOTE: Code borrowed heavily from Pranav Kaundinya, et. al. (2012).
*/
module ntsc_to_bram(clk, vclk, fvh, dv, din, ntsc_addr, ntsc_data, ntsc_we, sw);
input clk; // system clock
input vclk; // video clock from camera
input [2:0] fvh;
input dv;
input [29:0] din;
input sw;
output reg [16:0] ntsc_addr;
output reg [11:0] ntsc_data;
output ntsc_we; // write enable for NTSC data
parameter COL_START = 10'd0;
parameter ROW_START = 10'd0;
reg [9:0] col = 0;
reg [9:0] row = 0;
reg [29:0] vdata = 0;
reg vwe;
reg old_dv;
reg old_frame; // frames are even / odd interlaced
reg even_odd; // decode interlaced frame to this wire
wire frame = fvh[2];
wire frame_edge = frame & ~old_frame;
always @ (posedge vclk) begin//LLC1 is reference
old_dv <= dv;
vwe <= dv && !fvh[2] & ~old_dv; // if data valid, write it
old_frame <= frame;
even_odd = frame_edge ? ~even_odd : even_odd;
if (!fvh[2]) begin
col <= fvh[0] ? COL_START :
(!fvh[2] && !fvh[1] && dv && (col < 1024)) ? col + 1 : col;
row <= fvh[1] ? ROW_START :
(!fvh[2] && fvh[0] && (row < 768)) ? row + 1 : row;
vdata <= (dv && !fvh[2]) ? din : vdata;
end
end
// synchronize with system clock
reg [9:0] x[1:0],y[1:0];
reg [29:0] data[1:0];
reg we[1:0];
reg eo[1:0];
always @(posedge clk)begin
{x[1],x[0]} <= {x[0],col};
{y[1],y[0]} <= {y[0],row};
{data[1],data[0]} <= {data[0],vdata};
{we[1],we[0]} <= {we[0],vwe};
{eo[1],eo[0]} <= {eo[0],even_odd};
end
// edge detection on write enable signal
reg old_we;
wire we_edge = we[1] & ~old_we;
always @(posedge clk) old_we <= we[1];
// shift each set of four bytes into a large register for the ZBT
// compute address to store data in
wire [9:0] y_addr = {y[1][8:0], eo[1]};
wire [9:0] x_addr = x[1];
wire [7:0] R, G, B;
ycrcb2rgb conv( R, G, B, clk, 1'b0, data[1][29:20],
data[1][19:10], data[1][9:0] );
wire [16:0] myaddr_o = (y_addr[7:0] << 8) + (y_addr[7:0] << 6) + x_addr[8:0];
wire [16:0] myaddr;
synchronize #(.NSYNC(3), .W(17)) myaddr_sync(clk, myaddr_o, myaddr);
// update the output address and data only when four bytes ready
wire ntsc_we_o = (x_addr < COL_START + 10'd320 && y_addr < ROW_START + 10'd240) && (we_edge);
synchronize #(.NSYNC(3)) we_sync(clk, ntsc_we_o, ntsc_we);
always @(posedge clk)
if ( ntsc_we ) begin
ntsc_addr <= myaddr; // normal and expanded modes
ntsc_data <= ~sw ? {R[7:4], G[7:4], B[7:4]} :
{x_addr[9], 3'b0, x_addr[8], 3'b0, x_addr[7], 3'b0};
end
endmodule // ntsc_to_zbt
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y; } p[8]; int cmp(node a, node b) { if (a.x == b.x) return (a.y < b.y); return a.x < b.x; } int main() { while (scanf( %d %d , &p[0].x, &p[0].y) != EOF) { int cnt1 = 0; int cnt2 = 0; int cnt3 = 0; int cnt4 = 0; for (int i = 1; i < 8; i++) { scanf( %d %d , &p[i].x, &p[i].y); } sort(p, p + 8, cmp); node zuoshang = p[0]; node youxia = p[7]; for (int i = 1; i < 7; i++) { if (p[i].x == zuoshang.x) cnt1++; if (p[i].y == zuoshang.y) cnt2++; if (p[i].x == youxia.x) cnt3++; if (p[i].y == youxia.y) cnt4++; } if (cnt1 == 2 && cnt2 == 2 && cnt3 == 2 && cnt4 == 2 && p[1].y == p[6].y && p[4].x == p[3].x) puts( respectable ); else puts( ugly ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long po(long long x, long long y, long long p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int countP(int n, int k) { if (n == 0 || k == 0 || k > n) return 0; if (k == 1 || k == n) return 1; return k * countP(n - 1, k) + countP(n - 1, k - 1); } void solve() { long long fac = 1; long long n; cin >> n; long long xo = n; if (n == 2) cout << 1 << n ; else { for (long long i = 1; i <= n; i++) { fac = fac * i; } fac *= 2; fac /= n; fac /= n; cout << fac << n ; } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t = 1; while (t--) { solve(); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_FUNCTIONAL_V
`define SKY130_FD_SC_HD__HA_FUNCTIONAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_FUNCTIONAL_V
|
module object_store(
input wire mclk,
input wire stall,
input wire reset,
output reg[31:0] mem_address = 0,
output reg[31:0] mem_din,
input wire[31:0] mem_dout,
output reg mem_re = 0,
output reg mem_we = 0,
input wire [4:0] slot_index,
output wire[31:0] slot_value,
output reg initialized = 0
);
parameter state_reset = 2'b00;
parameter state_load_ptr = 2'b01;
parameter state_load_regs = 2'b10;
parameter state_complete = 2'b11;
reg[1:0] state = state_reset;
parameter last_slot = 5'd26;
reg[4:0] store_index = 0;
reg[31:0] slots[0:26];
wire has_control = !stall && !mem_re && !mem_we;
// Should slots be wired or accessed via bus?
assign slot_value = slots[slot_index];
always @ (posedge mclk) begin
if(reset) begin
state <= state_reset;
end else begin
if(has_control) begin
case(state)
state_reset: begin
// Read memory at address 0
mem_address <= 31'b0;
mem_re <= 1;
state <= state_load_ptr;
store_index <= 0;
initialized <= 0;
end
state_load_ptr: begin
// Read memory at location of first slot;
mem_address <= mem_dout + 2;
mem_re <= 1;
state <= state_load_regs;
end
state_load_regs: begin
// Store slot value & increment memory address;
slots[store_index] <= mem_dout;
if(store_index == last_slot) begin
state <= state_complete;
initialized <= 1;
end else begin
mem_address <= mem_address + 1;
store_index <= store_index + 1;
mem_re <= 1;
end
end
default: begin
// Trap
end
endcase
end else begin
// No pipeline
// Force machine to wait at least a cycle after asserting read/write
// and ensure read/write is asserted for just one cycle.
mem_we <= 0;
mem_re <= 0;
end
end
end
endmodule
|
//==================================================================================================
// Filename : FSM_input_enable.v
// Created On : 2016-10-04 09:10:38
// Last Modified : 2016-10-04 09:45:50
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Added extra state to the mix, pertaining to the
// initialization module (FSM).
//
//==================================================================================================
//==================================================================================================
// Filename : FSM_input_enable.v
// Created On : 2016-09-21 00:26:00
// Last Modified : 2016-10-04 09:08:38
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : FSM controlling the initialization and input of the operands and the
// desired operation
//
//==================================================================================================
`timescale 1ns / 1ps
module FSM_INPUT_ENABLE(
//INPUTS
input wire clk,
input wire rst,
input wire init_OPERATION,
output reg enable_input_internal,
//output enable for the first stage of the pipeline
output wire enable_Pipeline_input,
output reg enable_shift_reg
);
////////States///////////
//Zero Phase
parameter [3:0] State0 = 3'd0,
State1 = 3'd1,
State2 = 3'd2,
State3 = 3'd3,
State4 = 3'd4,
State5= 3'd5,
State6 = 3'd6,
State7 = 3'd7;
//State registers
reg [2:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= State0;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//DEFAULT INITIAL VALUES
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
enable_input_internal=1; //It is internal because its an intermediary value
enable_shift_reg = 0;
case(state_reg)
State0:
begin
//OUTPUT SIGNAL
//NEXT STATE
if(init_OPERATION)
state_next = State1; //JUMP TO NEXT STATE
else begin
state_next = State0; //STAY
end
end
State1:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State6;
end
State6:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State2;
end
State2:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State3;
end
State3:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State4;
end
State4:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State5;
end
State5:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
//state_next = State0;
if (init_OPERATION) begin
state_next = State1;
end else begin
state_next = State0;
end
end
// State6:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=1;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State1;
// end
// State7:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=0;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State0;
// end
default:
begin
state_next =State0;
end
endcase
end
assign enable_Pipeline_input = enable_input_internal & init_OPERATION;
endmodule
|
#include <bits/stdc++.h> using namespace std; int M = 1e9 + 7; int incr(string &s) { int i, n = s.length(); for (i = n - 1; i >= 0; --i) { if (s[i] != 9 ) { s[i]++; return 0; } s[i] = 0 ; } for (i = n - 1; i >= 0; --i) { s[i] = 0 ; } s = 1 + s; return 0; } int incr2(string &s, int t) { while (t > 0) { for (int i = s.length() - 1; i >= 0; --i) { if (s[i] != 9 ) { s[i]++; --t; if (s[i] == 5 ) { if (i == 0) { return 1; } s.pop_back(); break; } else { return 0; } } else { s[i] = 0 ; s.pop_back(); if (i == 0) { return 1; } } } } for (int i = s.length() - 1; i >= 0; --i) { if (s[i] != 9 ) { s[i]++; return 0; } } } int main() { int i, n, t; cin >> n >> t; string s; cin >> s; int di = s.find( . ); string dpart = s.substr(0, di); s = s.substr(di + 1, n - di - 1); if (s[0] >= 5 ) { incr(dpart); cout << dpart; return 0; } for (i = 0; i < s.length(); i++) { if (s[i] >= 5 ) { break; } } if (i == s.length()) { cout << dpart << . << s; return 0; } s = s.substr(0, i); int c4 = 0; for (i = s.length() - 1; i >= 0; --i) { if (s[i] == 4 ) { c4++; } else { break; } } if (c4 == 0) { incr2(s, 0); cout << dpart << . << s; return 0; } if (c4 == s.length() && t > c4) { incr(dpart); cout << dpart; return (0); } cout << dpart << . ; if (t <= c4) { cout << s.substr(0, s.length() - t) << 5 ; return 0; } s[s.length() - c4 - 1]++; cout << s.substr(0, s.length() - c4); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { long long n, k; cin >> n >> k; long long cur = 1, now = 1, ans = 0; while (now <= k && cur < n) { cur += now; now <<= 1; ans++; } if (cur < n) { ans += (n - cur + k - 1) / k; } printf( %lld n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, fre[11], fre1[11]; string tot, no, cm = , cm1 = ; bool belongs(int x) { int tmp = x, len = 0, i; int tmf[11] = {}; while (tmp > 0) { tmf[(tmp % 10)]++; tmp /= 10; len++; } if (n - len == x) { for (i = 0; i < 10; i++) { if (fre1[i] < tmf[i]) return false; } return true; } return false; } int main() { int i, j; cin >> tot; cin >> no; if (tot == 01 || tot == 10 ) { cout << 0 n ; return 0; } n = tot.length(); m = no.length(); for (i = 0; i < n; i++) { fre[tot[i] - 48]++; fre1[tot[i] - 48]++; } for (i = 0; i < m; i++) { fre1[no[i] - 48]--; } for (i = 1; i <= n; i++) { if (belongs(i)) { int tmp = i; while (tmp > 0) { fre1[(tmp % 10)]--; tmp /= 10; } break; } } int tm; for (i = 0; i < 10; i++) { tm = fre1[i]; while (tm > 0) { cm1 += (i + 48); tm--; } } for (i = 1; i < 10; i++) { if (fre1[i] > 0) { cm += (i + 48); fre1[i]--; break; } } for (i = 0; i < 10; i++) { tm = fre1[i]; while (tm > 0) { cm += (i + 48); tm--; } } if (no[0] == 0 ) { i = 1; n = cm.size(); while (i < n && cm[i] < no[0]) { i++; } string ans1 = , ans2 = ; for (j = 0; j < min(i, n); j++) ans1 += cm[j]; ans1 += no; for (j = i; j < n; j++) ans1 += cm[j]; i = 1; while (i < n && cm[i] <= no[0]) { i++; } for (j = 0; j < min(i, n); j++) ans2 += cm[j]; ans2 += no; for (j = i; j < n; j++) ans2 += cm[j]; string ans; if (ans1[0] != 0 ) { ans = ans1; } else if (ans2[0] != 0 ) { ans = ans2; } if (ans1[0] != 0 ) { ans = min(ans, ans1); } if (ans2[0] != 0 ) { ans = min(ans, ans2); } cout << ans << endl; } else { string ans3 = no + cm1; i = 1; n = cm.size(); while (i < n && cm[i] < no[0]) { i++; } string ans1 = , ans2 = ; for (j = 0; j < min(i, n); j++) ans1 += cm[j]; ans1 += no; for (j = i; j < n; j++) ans1 += cm[j]; i = 1; while (i < n && cm[i] <= no[0]) { i++; } for (j = 0; j < min(i, n); j++) ans2 += cm[j]; ans2 += no; for (j = i; j < n; j++) ans2 += cm[j]; string ans; if (ans1[0] != 0 ) { ans = ans1; } else if (ans2[0] != 0 ) { ans = ans2; } else if (ans3[0] != 0 ) { ans = ans3; } if (ans1[0] != 0 ) { ans = min(ans, ans1); } if (ans2[0] != 0 ) { ans = min(ans, ans2); } if (ans3[0] != 0 ) { ans = min(ans, ans3); } cout << ans << endl; } return 0; }
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// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
module Rs232Tx(input clk, output UART_TX, input [7:0] data, input send, output reg uart_ovf, output reg sending);
reg [9:0] sendbuf = 9'b000000001;
//reg sending;
reg [13:0] timeout;
assign UART_TX = sendbuf[0];
always @(posedge clk) begin
if (send && sending)
uart_ovf <= 1;
if (send && !sending) begin
sendbuf <= {1'b1, data, 1'b0};
sending <= 1;
timeout <= 100 - 1; // 115200
end else begin
timeout <= timeout - 1;
end
if (sending && timeout == 0) begin
timeout <= 100 - 1; // 115200
if (sendbuf[8:0] == 9'b000000001)
sending <= 0;
else
sendbuf <= {1'b0, sendbuf[9:1]};
end
end
endmodule
module Rs232Rx(input clk, input UART_RX, output [7:0] data, output send);
reg [8:0] recvbuf;
reg [5:0] timeout = 10/2 - 1;
reg recving;
reg data_valid = 0;
assign data = recvbuf[7:0];
assign send = data_valid;
always @(posedge clk) begin
data_valid <= 0;
timeout <= timeout - 6'd1;
if (timeout == 0) begin
timeout <= 10 - 1;
recvbuf <= (recving ? {UART_RX, recvbuf[8:1]} : 9'b100000000);
recving <= 1;
if (recving && recvbuf[0]) begin
recving <= 0;
data_valid <= UART_RX;
end
end
// Once we see a start bit we want to wait
// another half period for it to become stable.
if (!recving && UART_RX)
timeout <= 10/2 - 1;
end
endmodule
// Decodes incoming UART signals and demuxes them into addr/data lines.
// Packet Format:
// 1 byte checksum | 1 byte address | 1 byte count | (count + 1) data bytes
module UartDemux(input clk, input RESET, input UART_RX, output reg [7:0] data, output reg [7:0] addr, output reg write, output reg checksum_error);
wire [7:0] indata;
wire insend;
Rs232Rx uart(clk, UART_RX, indata, insend);
reg [1:0] state = 0;
reg [7:0] cksum;
reg [7:0] count;
wire [7:0] new_cksum = cksum + indata;
always @(posedge clk) if (RESET) begin
write <= 0;
state <= 0;
count <= 0;
cksum <= 0;
addr <= 0;
data <= 0;
checksum_error <= 0;
end else begin
write <= 0;
if (insend) begin
cksum <= new_cksum;
count <= count - 8'd1;
if (state == 0) begin
state <= 1;
cksum <= indata;
end else if (state == 1) begin
addr <= indata;
state <= 2;
end else if (state == 2) begin
count <= indata;
state <= 3;
end else begin
data <= indata;
write <= 1;
if (count == 1) begin
state <= 0;
if (new_cksum != 0)
checksum_error <= 1;
end
end
end
end
endmodule
|
// Register file modeled off HW6 solutions #3
module reg_file(
input clk,
input regWrite,
//input wire regInit,
input [4:0] readReg1,
input [4:0] readReg2,
input [4:0] writeReg,
input [31:0] writeData,
output reg [31:0] readData1,
output reg [31:0] readData2
);
reg [31:0] regFile [31:0];
integer i;
initial begin
for (i=0; i<32; i=i+1) begin
regFile[i] <=0;
end
end
always@(readReg1 or readReg2 or regFile)
begin
readData1 <= regFile[readReg1];
readData2 <= regFile[readReg2];
end
// Register only updates when regWrite control signal enabled
// When regInit true, initialize all registers to 0 (avoids using for-loop)
always@(posedge clk)
begin
if(regWrite)
regFile[writeReg] <= writeData;
/*if (regInit) begin
regFile[31] <= 32'h00000000;
regFile[30] <= 32'h00000000;
regFile[29] <= 32'h00000000;
regFile[28] <= 32'h00000000;
regFile[27] <= 32'h00000000;
regFile[26] <= 32'h00000000;
regFile[25] <= 32'h00000000;
regFile[24] <= 32'h00000000;
regFile[23] <= 32'h00000000;
regFile[22] <= 32'h00000000;
regFile[21] <= 32'h00000000;
regFile[20] <= 32'h00000000;
regFile[19] <= 32'h00000000;
regFile[18] <= 32'h00000000;
regFile[17] <= 32'h00000000;
regFile[16] <= 32'h00000000;
regFile[15] <= 32'h00000000;
regFile[14] <= 32'h00000000;
regFile[13] <= 32'h00000000;
regFile[12] <= 32'h00000000;
regFile[11] <= 32'h00000000;
regFile[10] <= 32'h00000000;
regFile[9] <= 32'h00000000;
regFile[8] <= 32'h00000000;
regFile[7] <= 32'h00000000;
regFile[6] <= 32'h00000000;
regFile[5] <= 32'h00000000;
regFile[4] <= 32'h00000000;
regFile[3] <= 32'h00000000;
regFile[2] <= 32'h00000000;
regFile[1] <= 32'h00000000;
regFile[0] <= 32'h00000000;
end */
end
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5 + 5; int n, q; ll a[N], tree[N << 2], lz[N << 2]; void push(int node, int s, int e) { tree[node] += lz[node]; if (s != e) { lz[node << 1] += lz[node]; lz[node << 1 | 1] += lz[node]; } lz[node] = 0; } void upd(int node, int s, int e, int l, int r, ll v) { push(node, s, e); if (r < s || e < l || l > r) return; if (l <= s && e <= r) { lz[node] += v; push(node, s, e); return; } int md = (s + e) >> 1; upd(node << 1, s, md, l, r, v); upd(node << 1 | 1, md + 1, e, l, r, v); tree[node] = max(tree[node << 1], tree[node << 1 | 1]); } int get(int node, int s, int e) { push(node, s, e); if (tree[node] < 0) return -1; if (s == e) return tree[node] != 0 ? -1 : s + 1; int md = (s + e) >> 1; int x = get(node << 1, s, md); if (~x) return x; return get(node << 1 | 1, md + 1, e); } int main() { scanf( %d%d , &n, &q); for (int i = 0; i < n; i++) { scanf( %lld , a + i); upd(1, 0, n - 1, i, i, a[i]); upd(1, 0, n - 1, i + 1, n - 1, -a[i]); } while (q--) { int x, v; scanf( %d%d , &x, &v); upd(1, 0, n - 1, x - 1, x - 1, -a[x - 1] + v); upd(1, 0, n - 1, x, n - 1, a[x - 1] - v); a[x - 1] = v; printf( %d n , get(1, 0, n - 1)); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long cnt, n, pre, i, j, k, l, x, y, z, a[310][310]; cin >> n; pre = 0; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { cin >> a[i][j]; pre += a[i][j]; } } cin >> k; while (k--) { cin >> x >> y >> z; if (a[x][y] <= z) cout << pre / 2 << ; else { cnt = 0; a[x][y] = z; a[y][x] = z; for (i = 1; i <= n; i++) { a[x][i] = min(a[x][i], a[x][y] + a[y][i]); a[i][x] = a[x][i]; } for (i = 1; i <= n; i++) { a[y][i] = min(a[y][i], a[y][x] + a[x][i]); a[i][y] = a[y][i]; } for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) a[i][j] = min(min(a[i][j], a[i][x] + a[x][j]), a[i][y] + a[y][j]); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) cnt += a[i][j]; pre = cnt; cout << pre / 2 << ; } } cout << endl; return 0; }
|
`default_nettype none
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1, COUT);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
parameter INJECT1_0 = "YES";
parameter INJECT1_1 = "YES";
// First half
wire LUT4_0, LUT2_0;
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
assign S0 = LUT4_0 ^ gated_cin_0;
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
// Second half
wire LUT4_1, LUT2_1;
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
assign S1 = LUT4_1 ^ gated_cin_1;
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
endmodule
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#include <bits/stdc++.h> using namespace std; struct LINE { int start; int end; }; int ans = 0; vector<int> res; string shift(string s, int p1, int p2) { char t; for (int f = p2; f > p1; f--) { ans++; res.push_back(f); t = s[f]; s[f] = s[f - 1]; s[f - 1] = t; } return s; } int main() { string s, t; int a1[27]; int a2[27]; for (int i = 0; i < 27; i++) { a2[i] = 0; a1[i] = 0; } getline(std::cin, s); getline(std::cin, s); getline(std::cin, t); for (int i = 0; i < s.length(); i++) { a1[((int)s[i]) - 97]++; } for (int i = 0; i < t.length(); i++) { a2[((int)t[i]) - 97]++; } for (int i = 0; i < 27; i++) { if (a1[i] != a2[i]) { cout << -1; return 0; } } for (int i = 0; i < s.length(); i++) { if (s[i] == t[i]) continue; int a = s.find(t[i], i); s = shift(s, i, a); } cout << ans << n ; for (int i = 0; i < res.size(); i++) { cout << res[i] << ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 123456; char buffer[N]; string solve(string s, int k) { const int n = s.size(); sort(s.begin(), s.end()); string res; int ptr = 0; while (ptr < n) { int p = ptr; char mini = ~ ; char maxi = 0 ; assert(mini > z && maxi < a ); for (int i = 0; i < k && ptr < n; i++) { mini = min(mini, s[ptr]); maxi = max(maxi, s[ptr]); ptr++; } if (!res.empty()) { if (mini == s.back()) { res += mini; } else { res += s.substr(p); break; } } else { if (mini == maxi) { res += mini; } else { res += maxi; break; } } } return res; } string brute_force(string s, int k) { assert(k == 2); int n = s.size(); string res = ~~~ ; sort(s.begin(), s.end()); for (int i = 0; i < (1 << n); i++) { string left, right; for (int j = 0; j < n; j++) { if (i & (1 << j)) { left += s[j]; } else { right += s[j]; } } if (left.empty() || right.empty()) { continue; } res = min(res, max(left, right)); } return res; } void test() { assert(solve( ccbbb , 2) == bbcc ); assert(solve( bbabc , 2) == b ); assert(solve( bababc , 2) == abbbc ); assert(solve( babab , 2) == abb ); assert(solve( baba , 2) == ab ); assert(solve( baacb , 2) == abbc ); assert(solve( baacb , 3) == b ); assert(solve( aaaaa , 3) == aa ); assert(solve( aaxxzz , 4) == x ); assert(solve( phoenix , 1) == ehinopx ); assert(solve( phoenix , 2) == h ); for (int i = 0; i < 100; i++) { int n = 10; string s; for (int j = 0; j < n; j++) { s += rand() % 5 + a ; } assert(brute_force(s, 2) == solve(s, 2)); } } int main() { int T; cin >> T; int n, k; while (T--) { scanf( %d%d , &n, &k); scanf( %s , buffer); puts(solve(buffer, k).c_str()); } return 0; }
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#include <bits/stdc++.h> long long srf(int a, int b, int c) { std::cout << 1 << (a + 1) << << (b + 1) << << (c + 1) << std::endl; long long val; std::cin >> val; return val; } bool scl(int a, int b, int c) { std::cout << 2 << (a + 1) << << (b + 1) << << (c + 1) << std::endl; int val; std::cin >> val; return val > 0; } void accept(std::vector<int> ans) { std::cout << 0 ; for (int i : ans) { std::cout << (i + 1) << ; } std::cout << std::endl; return; } signed main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); int n; std::cin >> n; std::vector<int> ans(n); std::iota(ans.begin(), ans.end(), 0); int pos = std::min_element(ans.begin() + 1, ans.end(), [&ans](int f, int s) { return scl(ans[0], f, s); }) - ans.begin(); std::swap(ans[1], ans[pos]); std::map<int, long long> map; for (int i = 2; i < n; i++) { map[ans[i]] = srf(ans[0], ans[1], ans[i]); } pos = std::max_element(ans.begin() + 1, ans.end(), [&map](int f, int s) { return map[f] < map[s]; }) - ans.begin(); std::swap(ans.back(), ans[pos]); std::vector<int> left, right; for (int i = 2; i < (ans.size() - 1); i++) { if (scl(ans[0], ans.back(), ans[i])) { left.push_back(ans[i]); } else { right.push_back(ans[i]); } } std::vector<int> ans2 = {ans[0], ans[1]}; std::sort(right.begin(), right.end(), [&map](int f, int s) { return map[f] < map[s]; }); for (int i : right) { ans2.push_back(i); } ans2.push_back(ans.back()); std::sort(left.begin(), left.end(), [&map](int f, int s) { return map[f] < map[s]; }); std::reverse(left.begin(), left.end()); for (int i : left) { ans2.push_back(i); } accept(ans2); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 3079; int r, c, n, k; vector<int> nx(maxn, -1), pv(maxn, -1), kth(maxn, -1); vector<vector<int> > my(maxn); class point { public: int x, y; }; bool cmp(point& a, point& b) { return (a.y == b.y ? a.x < b.x : a.y < b.y); } vector<point> v(maxn); long long sum(int i) { return (v[i].y - v[pv[i]].y) * (c + 1 - v[kth[i]].y); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> r >> c >> n >> k; long long ans = 0; int m = n + k + 1; for (int i = 1; i <= n; i++) cin >> v[i].x >> v[i].y; v[0] = {r + 1, 0}; for (int i = n + 1; i < m; i++) v[i] = {r + 1, c + 1}; sort(v.begin(), v.begin() + m, cmp); for (int i = n + 1; i < m; i++) kth[i] = m - 1, pv[i] = i - 1, nx[i] = min(m - 1, i + 1); for (int i = m - 1; i >= 0; i--) my[v[i].x].push_back(i); for (int x1 = 1; x1 <= r; x1++) { int p = 0; for (int i = 1; i <= n; i++) { if (v[i].x < x1) continue; nx[p] = i, pv[i] = p; p = i; } nx[p] = n + 1, pv[n + 1] = p; kth[p] = (k == 1 ? p : pv[m - 1]); for (int i = p; i >= 0; i = pv[i]) kth[i] = pv[kth[nx[i]]]; long long cur = 0; for (int i = nx[0]; i <= n; i = nx[i]) cur += sum(i); for (int x2 = r; x2 >= x1; x2--) { ans += cur; for (int i : my[x2]) { cur -= sum(i); for (int j = pv[i], cnt = 0; cnt < k - 1 && j; cnt++, j = pv[j]) { cur -= sum(j); if (j < i) kth[j] = nx[kth[j]]; cur += sum(j); } cur -= sum(nx[i]); nx[pv[i]] = nx[i], pv[nx[i]] = pv[i]; cur += sum(nx[i]); } } } cout << ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; string ls[] = { , one , two , three , four , five , six , seven , eight , nine }; string fr[] = { , , twenty , thirty , forty , fifty , sixty , seventy , eighty , ninety }; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; int first = n / 10, second = n % 10; switch (n) { case 0: cout << zero << endl; break; case 10: cout << ten << endl; break; case 11: cout << eleven << endl; break; case 12: cout << twelve << endl; break; case 13: cout << thirteen << endl; break; case 14: cout << fourteen << endl; break; case 15: cout << fifteen << endl; break; case 16: cout << sixteen << endl; break; case 17: cout << seventeen << endl; break; case 18: cout << eighteen << endl; break; case 19: cout << nineteen << endl; break; default: { if (!first) cout << ls[second] << endl; else if (!second) cout << fr[first] << endl; else cout << fr[first] << - << ls[second] << endl; } } }
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/****************************************
Adder
for MIST32 Processor
Takahiro Ito @cpu_labs
****************************************/
`default_nettype none
`include "core.h"
module execute_adder #(
parameter P_N = 32
)(
//iDATA
input wire [P_N-1:0] iDATA_0,
input wire [P_N-1:0] iDATA_1,
input wire [4:0] iADDER_CMD,
//oDATA
output wire [P_N-1:0] oDATA,
output wire oSF,
output wire oOF,
output wire oCF,
output wire oPF,
output wire oZF
);
/****************************************
This -> Output
****************************************/
assign {oZF, oPF, oOF, oSF, oCF, oDATA} = func_adder_execution(iADDER_CMD, iDATA_0, iDATA_1);
//ZF, PF, OF, SF, CF, Data
function [36:0] func_adder_execution;
input [4:0] func_cmd;
input [31:0] func_data0;
input [31:0] func_data1;
reg [32:0] func_pri_op0;
reg [32:0] func_pri_op1;
reg [32:0] func_pri_out;
begin
case(func_cmd)
`EXE_ADDER_ADD :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_SUB :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = ({1'b0, ~func_data1} + 32'h1);
func_pri_out = func_pri_op0 + func_pri_op1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0],( func_data0[31] != func_data1[31] && func_data0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], func_pri_out[31:0]};
end
`EXE_ADDER_NEG:
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = ~func_data0 + {{P_N-1{1'b0}}, 1'b1};
func_adder_execution = {5'h0, func_pri_out[31:0]};
end
`EXE_ADDER_COUT :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = func_pri_op0 + func_pri_op1;//func_data0 + func_data1;
func_adder_execution = {(func_pri_out[31:0] == {32{1'h0}}), func_pri_out[0], (func_pri_op0[31] == func_pri_op1[31] && func_pri_op0[31] != func_pri_out[31]), func_pri_out[31], func_pri_out[32], 31'h0 , func_pri_out[32]};
end
`EXE_ADDER_SEXT8 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {24{func_data1[7]}}, func_data1[7:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};
end
`EXE_ADDER_SEXT16 :
begin
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {1'b0, {16{func_data1[15]}}, func_data1[15:0]};
func_adder_execution = {5'h0, func_pri_out[31:0]};
end
`EXE_ADDER_MAX :
if(func_data0[31] && func_data1[31])begin
func_adder_execution = (!(func_data0[30:0] > func_data1[30:0]))? {5'h0, func_data0} : {5'h0, func_data0};
end
else if(!func_data0[31] && !func_data1[31])begin
func_adder_execution = (func_data0[30:0] > func_data1[30:0])? {5'h0, func_data0} : {5'h0, func_data0};
end
else if(!func_data0[31] && func_data1[31])begin
func_adder_execution = {5'h0, func_data0};
end
else begin
func_adder_execution = {5'h0, func_data1};
end
`EXE_ADDER_MIN :
if(func_data0[31] && func_data1[31])begin
func_adder_execution = (func_data0[30:0] > func_data1[30:0])? {5'h0, func_data0} : {5'h0, func_data0};
end
else if(!func_data0[31] && !func_data1[31])begin
func_adder_execution = (!(func_data0[30:0] > func_data1[30:0]))? {5'h0, func_data0} : {5'h0, func_data0};
end
else if(!func_data0[31] && func_data1[31])begin
func_adder_execution = {5'h0, func_data1};
end
else begin
func_adder_execution = {5'h0, func_data0};
end
`EXE_ADDER_UMAX :
begin
func_adder_execution = (func_data0 > func_data1)? {5'h0, func_data0} : {5'h0, func_data1};
end
`EXE_ADDER_UMIN :
begin
func_adder_execution = (func_data0 < func_data1)? {5'h0, func_data0} : {5'h0, func_data1};
end
default:
begin/*
//$display("[ERROR] : adder_n.v func_addder_execution Error");
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'b0}};
*/
func_pri_op0 = {1'b0, func_data0};
func_pri_op1 = {1'b0, func_data1};
func_pri_out = {33{1'b0}};
func_adder_execution = {37{1'h0}};
end
endcase
end
endfunction
endmodule
`default_nettype wire
|
//
// Copyright (c) 2015 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define PDP1_SBS_ESM 11'o0055
`define PDP1_SBS_LSM 11'o0054
`define PDP1_SBS_CBS 11'o0056
`define PDP1_SBS_CKS 11'o0033
module pdp1_sbs(i_clk, i_rst,
sb_ireq, sb_dne,
pb_att, pb_op, pb_sqb,
tr_lp, tr_ptr, tr_tyo, tr_tyi, tr_tp, tr_drm);
input i_clk;
input i_rst;
output reg sb_ireq;
input sb_dne;
input pb_att;
input [0:10] pb_op;
output [0:5] pb_sqb;
input tr_lp;
input tr_ptr;
input tr_tyo;
input tr_tyi;
input tr_tp;
input tr_drm;
reg r_en;
wire w_tr_any;
assign pb_sqb = {tr_lp, tr_ptr, tr_tyo, tr_tyi, tr_tp, tr_drm, r_en};
assign w_tr_any = (|pb_sqb[0:4]);
always @(posedge i_clk) begin
if(i_rst) begin
sb_ireq <= 1'b0;
r_en <= 1'b0;
end
else begin
if(pb_att) begin
case(pb_op)
`PDP1_SBS_ESM:
r_en <= 1'b1;
`PDP1_SBS_LSM:
r_en <= 1'b0;
`PDP1_SBS_CBS:
sb_ireq <= 1'b0;
endcase // case (pb_op)
end
else begin
if(w_tr_any & ~sb_dne)
sb_ireq <= 1'b1;
else if(sb_dne & sb_ireq)
sb_ireq <= 1'b0;
end
end
end
endmodule // pdp1_sbs
|
`timescale 1ns / 1ps
`define READ 2'b01
`define WRITE 2'b10
`define DO_NOTHING 2'b00
`define INVALID 2'b11
`define DATA_VALID 1'b1
`define DATA_INVALID 1'b0
`define FIFO_FULL 1'b1
`define FIFO_NOT_FULL 1'b0
`define FIFO_EMPTY 1'b1
`define FIFO_NOT_EMPTY 1'b0
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:56 03/25/2015
// Design Name:
// Module Name: fifo_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo_top(
data_out, empty_flag, full_flag,
vector_in, reset,
clk
);
parameter DATA_WIDTH = 4;
parameter NUM_ENTRIES = 4;
parameter OPCODE_WIDTH = 2;
parameter LINE_WIDTH = DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
parameter INITIAL_VALUE = 'b0;
parameter NUM_ENTRIES_BIT = `LOG2(NUM_ENTRIES);
output reg [DATA_WIDTH-1:0]data_out;
output reg empty_flag;
output reg full_flag;
input [OPCODE_WIDTH+DATA_WIDTH-1:0]vector_in;
input reset;
input clk;
reg [DATA_WIDTH-1:0]fifo_data[NUM_ENTRIES-1:0];
reg [NUM_ENTRIES-1:0]fifo_valid_invalid_bit;
reg [OPCODE_WIDTH-1:0]control_in; // control bits for the module obtained from the input vector
reg [DATA_WIDTH-1:0]data_in; // data bits for the module obtained from the input vector
reg [NUM_ENTRIES_BIT-1:0]fifo_head_pos;
reg [NUM_ENTRIES_BIT-1:0]fifo_tail_pos;
reg [NUM_ENTRIES_BIT-1:0]loop_variable;
always@(posedge clk)
begin
if(reset)
begin
data_out = INITIAL_VALUE;
fifo_head_pos = INITIAL_VALUE;
fifo_tail_pos = INITIAL_VALUE;
loop_variable = INITIAL_VALUE;
control_in = INITIAL_VALUE;
data_in = INITIAL_VALUE;
fifo_valid_invalid_bit = INITIAL_VALUE;
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// if the tail and head are at the same location
if(fifo_tail_pos == fifo_head_pos)begin
// check if the data contained in that location is VALID/INVALID
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_INVALID && fifo_valid_invalid_bit[fifo_head_pos] == `DATA_INVALID)
begin
// if INVALID, fifo empty
// $display("INVALID, EMPTY");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end else
begin
// else, fifo full
// $display("VALID, FULL");
empty_flag = `FIFO_NOT_EMPTY;
full_flag = `FIFO_FULL;
end
end else
begin
// $display("DIFFERENT LOCATIONS");
empty_flag = `FIFO_EMPTY;
full_flag = `FIFO_NOT_FULL;
end
// $display("fifo_head_pos:%d, fifo_tail_pos:%d, empty_flag:%d, full_flag:%d", fifo_head_pos, fifo_tail_pos, empty_flag,full_flag);
control_in = vector_in[LINE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH];
data_in = vector_in[LINE_WIDTH-OPCODE_WIDTH-1:LINE_WIDTH-OPCODE_WIDTH-DATA_WIDTH];
// $display("control: %d,data_in: %d",control_in, data_in);
case(control_in)
`READ:
begin
// $display("FIFO READ");
if(fifo_valid_invalid_bit[fifo_tail_pos] == `DATA_VALID)
begin
data_out = fifo_data[fifo_tail_pos];
fifo_valid_invalid_bit[fifo_tail_pos] = `DATA_INVALID;
fifo_tail_pos = fifo_tail_pos + 1'b1;
end else
begin
data_out = 'bx;
end
end
`WRITE:
begin
// $display("FIFO WRITE");
if(empty_flag == `FIFO_EMPTY && full_flag == `FIFO_NOT_FULL)
begin
fifo_data[fifo_head_pos] = data_in;
fifo_valid_invalid_bit[fifo_head_pos] = `DATA_VALID;
if(fifo_head_pos == NUM_ENTRIES-1)
fifo_head_pos = 0;
else
fifo_head_pos = fifo_head_pos + 1'b1;
end
// else
// $display("CACHE FULL, empty_flag:%d, full_flag:%d",empty_flag,full_flag);
end
// `INVALID: $display("INVLAID");
// `DO_NOTHING:
// begin
// repeat(NUM_ENTRIES)
// begin
// $display("loop_variable:%d, fifo_valid_invalid_bit:%d, fifo_data:%d", loop_variable, fifo_valid_invalid_bit[loop_variable], fifo_data[loop_variable]);
// loop_variable = loop_variable + 1'b1;
// end
// end
default: data_out = 'bx;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T> inline void println(T first) { print(first); putchar( n ); } template <class T, class U> inline void print(T first, U second) { printsp(first); println(second); } template <class T, class U, class V> inline void print(T first, U second, V z) { printsp(first); printsp(second); println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } int V, E, src, tar; int head[60000], work[60000], dis[60000]; int to[2010000], cap[2010000], nxt[2010000]; int q[60000], qf, qb; int n, m, males, females; void init(int n, int s, int t) { V = n; E = 0; src = s; tar = t; memset(head, -1, sizeof(int) * V); } void add_edge(int u, int v, int c) { to[E] = v; cap[E] = c; nxt[E] = head[u]; head[u] = E++; to[E] = u; cap[E] = 0; nxt[E] = head[v]; head[v] = E++; } bool bfs() { memset(dis, -1, sizeof(int) * V); qf = qb = 0; q[qb++] = src; dis[src] = 0; while (qf < qb && dis[tar] == -1) { int u = q[qf++]; for (int i = head[u]; i >= 0; i = nxt[i]) { int v = to[i]; if (dis[v] == -1 && cap[i] > 0) { dis[v] = dis[u] + 1; q[qb++] = v; } } } return dis[tar] >= 0; } int dfs(int u, int &bot) { int v, bot1, delta; if (u == tar) return bot; for (int &i = work[u]; i >= 0; i = nxt[i]) { int v = to[i]; if (dis[v] != dis[u] + 1 || cap[i] == 0) continue; bot1 = min(bot, cap[i]); if (delta = dfs(v, bot1)) { cap[i] -= delta; cap[i ^ 1] += delta; bot = bot1; return delta; } } return 0; } int dinic() { int ans = 0, delta, bot; while (bfs()) { memcpy(work, head, sizeof(int) * V); delta = 0x3f3f3f3f; while (delta = dfs(src, bot = 0x3f3f3f3f)) ans += delta; } return ans; } void NoSolution() { puts( -1 ); exit(0); } char grid[33][33]; int dst[33][33][33][33]; int dx[] = {0, 0, -1, 1}; int dy[] = {-1, 1, 0, 0}; int mx[33 * 33], my[33 * 33], mt[33 * 33]; int fx[33 * 33], fy[33 * 33], ft[33 * 33]; int can(long long mid) { init(males + females + n * m * 2 + 10, 0, males + females + n * m * 2 + 1); for (int i = 0; i < males; i++) { add_edge(src, i + 1, 1); for (int j = 1; j <= n; j++) for (int k = 1; k <= m; k++) { if (dst[mx[i]][my[i]][j][k] == 0x3f3f3f3f) continue; if ((long long)dst[mx[i]][my[i]][j][k] * mt[i] > mid) continue; add_edge(i + 1, males + (j - 1) * m + k, 1); } } for (int i = 0; i < females; i++) { add_edge(males + n * m * 2 + i + 1, tar, 1); for (int j = 1; j <= n; j++) for (int k = 1; k <= m; k++) { if (dst[fx[i]][fy[i]][j][k] == 0x3f3f3f3f) continue; if ((long long)dst[fx[i]][fy[i]][j][k] * ft[i] > mid) continue; add_edge(males + (j - 1) * m + k + n * m, males + n * m * 2 + i + 1, 1); } } for (int j = 1; j <= n; j++) for (int k = 1; k <= m; k++) add_edge(males + (j - 1) * m + k, males + (j - 1) * m + k + n * m, 1); return dinic() == males; } int main() { gn(n, m); gn(males, females); if (abs(males - females) != 1) NoSolution(); for (int i = 1; i <= n; i++) scanf( %s , grid[i] + 1); int r, c, t; gn(r, c, t); memset(dst, 0x3f, sizeof dst); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (grid[i][j] == . ) { dst[i][j][i][j] = 0; qf = qb = 0; q[qb++] = i; q[qb++] = j; while (qf < qb) { int u = q[qf++], v = q[qf++]; for (int k = 0; k < 4; k++) { int uu = u + dx[k], vv = v + dy[k]; if ((uu < 1 || vv < 1 || uu > n || vv > m) || grid[uu][vv] == # ) continue; if (dst[i][j][uu][vv] > dst[i][j][u][v] + 1) { dst[i][j][uu][vv] = dst[i][j][u][v] + 1; q[qb++] = uu; q[qb++] = vv; } } } } } for (int i = 0; i < males; i++) gn(mx[i], my[i], mt[i]); for (int i = 0; i < females; i++) gn(fx[i], fy[i], ft[i]); if (males == females + 1) { fx[females] = r; fy[females] = c; ft[females] = t; females++; } else if (males + 1 == females) { mx[males] = r; my[males] = c; mt[males] = t; males++; } assert(males == females); long long st = -1, ed = (long long)1e16; while (ed - st > 1) { long long mid = st + ed >> 1; if (can(mid)) ed = mid; else st = mid; } if (ed == (long long)1e16) NoSolution(); println(ed); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MSU_DATA
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:45 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`timescale 1ns/10ps
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int dp[4011][4011]; long long int b[2000000]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int a[n]; set<long long int> st; for (int i = 0; i < n; i++) { cin >> a[i]; st.insert(a[i]); } long long int k = 0; for (auto u : st) { b[u] = k; k++; } for (int i = 0; i < n; i++) { a[i] = b[a[i]]; } for (int i = 0; i < n; i++) { long long int f = 0; for (int j = i - 1; j >= 0; j--) { if (a[i] == a[j]) { if (f == 1) continue; f = 1; dp[a[i]][a[j]]++; } else { dp[a[i]][a[j]] = max(dp[a[i]][a[j]], 1 + dp[a[j]][a[i]]); } } } long long int ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) ans = max(ans, dp[i][j]); } cout << ans + 1; }
|
#include <bits/stdc++.h> using namespace std; long long n, k, a[200], m; int main() { cin >> n >> m; k = n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); while (m > 0) m -= a[n--]; if (n < 0) n = 0; cout << k - n << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V
|
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// Provides a FIFO interface for JTAG communication.
module jtag_fifo (
input rx_clk,
input [11:0] rx_data,
input wr_en, rd_en,
output [8:0] tx_data,
output tx_full, tx_empty
);
wire jt_capture, jt_drck, jt_reset, jt_sel, jt_shift, jt_tck, jt_tdi, jt_update;
wire jt_tdo;
BSCAN_SPARTAN6 # (.JTAG_CHAIN(1)) jtag_blk (
.CAPTURE(jt_capture),
.DRCK(jt_drck),
.RESET(jt_reset),
.RUNTEST(),
.SEL(jt_sel),
.SHIFT(jt_shift),
.TCK(jt_tck),
.TDI(jt_tdi),
.TDO(jt_tdo),
.TMS(),
.UPDATE(jt_update)
);
reg captured_data_valid = 1'b0;
reg [12:0] dr;
// FIFO from TCK to rx_clk
wire full;
fifo_generator_v8_2 tck_to_rx_clk_blk (
.wr_clk(jt_tck),
.rd_clk(rx_clk),
.din({7'd0, dr[8:0]}),
.wr_en(jt_update & jt_sel & !full),
.rd_en(rd_en & !tx_empty),
.dout(tx_data),
.full(full),
.empty(tx_empty)
);
// FIFO from rx_clk to TCK
wire [11:0] captured_data;
wire empty;
fifo_generator_v8_2 rx_clk_to_tck_blk (
.wr_clk(rx_clk),
.rd_clk(jt_tck),
.din({4'd0, rx_data}),
.wr_en(wr_en & !tx_full),
.rd_en(jt_capture & ~empty & ~jt_reset),
.dout(captured_data),
.full(tx_full),
.empty(empty)
);
assign jt_tdo = captured_data_valid ? captured_data[0] : dr[0];
always @ (posedge jt_tck or posedge jt_reset)
begin
if (jt_reset == 1'b1)
begin
dr <= 13'd0;
end
else if (jt_capture == 1'b1)
begin
// Capture-DR
captured_data_valid <= !empty;
dr <= 13'd0;
end
else if (jt_shift == 1'b1 & captured_data_valid)
begin
// Shift-DR
captured_data_valid <= 1'b0;
dr <= {jt_tdi, 1'b1, captured_data[11:1]};
end
else if (jt_shift == 1'b1)
begin
dr <= {jt_tdi, dr[12:1]};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e2 + 10; const long long mod = 998244353; const long long inf = (long long)4e17 + 5; const int INF = 1e9 + 7; const double pi = acos(-1.0); long long inv(long long b) { if (b == 1) return 1; return (mod - mod / b) * inv(mod % b) % mod; } inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n; int ans[105]; int more[maxn], les[maxn]; int mmax, mmin; int nex[maxn], pre[maxn]; inline void ask_m(int x) { printf( ? ); fflush(stdout); for (int i = 1; i <= n; i++) { if (i == x) printf( 2 ); else printf( 1 ); } puts( ); fflush(stdout); scanf( %d , more + x); if (more[x] == 0) { ans[x] = n; mmax = x; } } inline void ask_l(int x) { printf( ? ); fflush(stdout); for (int i = 1; i <= n; i++) { if (i == x) printf( 1 ); else printf( 2 ); } puts( ); fflush(stdout); scanf( %d , les + x); if (les[x] == 0) { ans[x] = 1; mmin = x; } } void solve() { for (int i = 1; i <= n; i++) { ask_m(i); } for (int i = 1; i <= n; i++) { ask_l(i); } for (int i = 1; i <= n; i++) { if (more[i] == i || !more[i]) continue; nex[i] = more[i]; pre[more[i]] = i; } for (int i = 1; i <= n; i++) { if (les[i] == i || !les[i]) continue; nex[les[i]] = i; pre[i] = les[i]; } int fr; for (int i = 1; i <= n; i++) { if (!nex[i]) { fr = i; break; } } for (int i = n; i >= 1; i--) { ans[fr] = i; fr = pre[fr]; } printf( ! ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); puts( ); fflush(stdout); } int main() { scanf( %d , &n); solve(); return 0; }
|
module QcmMasterControllerWithFCounterMain(clk, sig, codeSer, codePar, enableSer, enablePar, ioPowerEnable, clkEnable);
/*
This is the master controller module which instantiates the sub-modules responsible for master controller operation:
counter=frequency counter (really, a period counter with inversion) for
determining the RF frequency from the square-wave input on "sig"
lut=look-up-table for mapping from a frequency to a capacitor state.
Currently, the same state number is assigned to both the series and parallel outputs
driver=responsible for mapping from look-up-table output to encoded
signal for decoder boards (in present implementation, no adjustment
needs to be made to lut output), and also determines whether the state
has settled and the cap boards may act on the change.
PIN ASSIGNMENT FOR EPM2210F256C5N (MANY MACROCELL CPLD)
To arrive at this pin assignment,
(1) consult pin assignment for CapBoardDecoder (for tuning code pins) OR "BurkeCPLDBoardConfigurationTemplate.doc" (for signal input)
(2) map to pins on standard 84-pin CPLD
(3) consult Bill Parkin's 84-256-pin adapter schematic to map to 256-pin pin values.
Ok clk Location PIN_83 Yes
Ok sig Location PIN_28 Yes
Ok enableSer Location PIN_52 Yes AC16
Ok enablePar Location PIN_68 Yes AC26
Ok codeSer[0] Location PIN_33 Yes AC4
Ok codeSer[1] Location PIN_34 Yes AC7
Ok codeSer[2] Location PIN_39 Yes AC9
Ok codeSer[3] Location PIN_40 Yes AC11
Ok codeSer[4] Location PIN_48 Yes AC13
Ok codeSer[5] Location PIN_49 Yes AC14
Ok codeSer[6] Location PIN_51 Yes AC15
Ok codePar[0] Location PIN_57 Yes AC17
Ok codePar[1] Location PIN_58 Yes AC18
Ok codePar[2] Location PIN_60 Yes AC19
Ok codePar[3] Location PIN_61 Yes AC20
Ok codePar[4] Location PIN_64 Yes AC21
Ok codePar[5] Location PIN_65 Yes AC23
Ok codePar[6] Location PIN_67 Yes AC25
Ok ioPowerEnable Location PIN_56 Yes
Ok clkEnable Location PIN_73 Yes
Ted Golfinopoulos, pin assignment made on 25 Oct 2011
*/
input clk, sig; //1 bit inputs corresponding to clk and RF signal.
output wire [6:0] codeSer, codePar; //Capacitor state encoded in a number which is interpreted by CapBoardDecoder to determine which caps to turn on.
output enableSer, enablePar; //"Ready" bits indicating codes are ready for decoding.
output ioPowerEnable; //Bit which receives clock-like signal and allows IO circuitry to receive power on LH timing board.
output clkEnable; //Bit which, when high, enables clock.
wire [13:0] f; //Frequency of sig IN HUNDREDS OF Hz, need 4 significant decimal figures.
wire [6:0] state; //Intermediate variable to hold lut output.
reg [1:0] clkCntr; //Divide clock signal down.
initial begin
#0
clkCntr=2'b0; //Initialize clock counter.
end
//Instantiate frequency counter object.
fcounter c(clk, sig, f);
//79 corner frequencies in HUNDREDS OF Hz,
//from about 50 kHz (500 hundred Hz) to 300 kHz (3000 hundred Hz)
//Instantiate look-up table which determines state from frequency.
lutSmall tab(clk,f,state);
//At this point, the look-up table outputs a state in the same format required for the encoded cap states, and
//the cap index for the series board is the same as for the parallel board.
assign codeSer=state;
assign codePar=state;
//Instantiate drivers for serial and parallel states - primarily, this determines when the states are ready for decoding by CapBoardDecoder.
//driver dSer(clk,codeSer, enableSer);
//driver dPar(clk, codePar, enablePar);
assign enablePar=1'b1;
assign enableSer=1'b1;
always @(posedge clk) begin
clkCntr=clkCntr+2'b1; //Increment clock counter.
end
//Give ioPowerEnable bit a divided version of the clock. The rationale behind this is
//that (a) the ioPowerEnable bit needs a clock-like signal and (b) you should do an operation
//on the clock to prove that the CPLD is working (otherwise synthesis can just connect a wire,
//and so passing the clock to the ioPowerEnable bit may not demonstrate functionality). This
//is in accordance with the new version of the LH Timing Board. Pin 56 on the CPLD must receive
//the ioPowerEnable bit.
assign ioPowerEnable=clkCntr[1];
assign clkEnable=1'b1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = LLONG_MAX; const int mxn = 1011; bool DEBUG = 0; string s[mxn]; bool grid[mxn][mxn], chg[mxn][mxn]; long long dist[mxn][mxn]; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, -1, 0, 1}; int n, m; bool check(int x, int y) { if (0 <= x && x < n && 0 <= y && y < m) return 1; return 0; } void init() { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (chg[i][j]) continue; bool f = 0; for (int k = 0; k < 4 && !f; k++) { int x = i + dx[k]; int y = j + dy[k]; if (!check(x, y)) continue; if (grid[x][y] == grid[i][j]) { f = 1; chg[x][y] = 1; } } if (f) chg[i][j] = 1; else chg[i][j] = 0; } } } void bfs(int x, int y) { queue<pair<int, int> > q; q.push(pair<int, int>(x, y)); while (!q.empty()) { pair<int, int> now = q.front(); x = now.first; y = now.second; q.pop(); for (int i = 0; i < 4; i++) { int X = x + dx[i]; int Y = y + dy[i]; if (!check(X, Y)) continue; if (dist[x][y] + 1 < dist[X][Y]) { dist[X][Y] = dist[x][y] + 1; q.push(pair<int, int>(X, Y)); } } } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int q; cin >> n >> m >> q; for (int i = 0; i < n; i++) { cin >> s[i]; for (int j = 0; j < m; j++) { grid[i][j] = s[i][j] == 1 ; } } init(); vector<pair<int, int> > visit; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (chg[i][j]) { dist[i][j] = 0; visit.emplace_back(i, j); } else { dist[i][j] = 1e18 + 1; } } } for (auto cor : visit) { bfs(cor.first, cor.second); } int a, b; long long t; while (q--) { cin >> a >> b >> t; a--; b--; if (t < dist[a][b]) { cout << grid[a][b] << n ; } else { t -= dist[a][b]; if (t % 2) cout << int(grid[a][b] ^ 1) << n ; else cout << grid[a][b] << n ; } } }
|
`timescale 1 ns / 1 ps
module axis_delay #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [CNTR_WIDTH-1:0] axis_data_count,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// Slave side
output wire s_axis_fifo_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_fifo_tdata,
input wire s_axis_fifo_tvalid,
// Master side
input wire m_axis_fifo_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_fifo_tdata,
output wire m_axis_fifo_tvalid
);
reg int_enbl_reg, int_enbl_next;
wire int_comp_wire;
assign int_comp_wire = axis_data_count > cfg_data;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_enbl_reg <= 1'b0;
end
else
begin
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_enbl_next = int_enbl_reg;
if( ~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
end
assign m_axis_fifo_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_fifo_tready;
assign m_axis_tvalid = int_enbl_reg ? s_axis_fifo_tvalid : s_axis_tvalid;
assign s_axis_fifo_tready = int_enbl_reg ? m_axis_tready : 1'b0;
assign m_axis_fifo_tdata=s_axis_tdata;
assign m_axis_tdata=s_axis_fifo_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<string, int> mp; int sum[1111], cnt, po[1111], Sum[1111]; char s[1111][1111], ss[1111][1111]; int a[1111]; int find(char *s) { if (mp[s]) return mp[s]; mp[s] = ++cnt; strcpy(ss[cnt], s); return cnt; } int main() { int n; while (scanf( %d , &n) == 1) { int mx = -1000000000; for (int i = 1; i <= n; i++) { scanf( %s%d , s[i], &a[i]); int id = find(s[i]); sum[id] += a[i]; } for (int i = 1; i <= cnt; i++) mx = max(mx, sum[i]); for (int i = 1; i <= n; i++) { int id = find(s[i]); Sum[id] += a[i]; if (Sum[id] >= mx && sum[id] >= mx) { puts(s[i]); break; } } } }
|
#include <bits/stdc++.h> using namespace std; int m, n; int main() { cin >> n >> m; if (m * n % 2 || ((min(m, n) == 1) && max(m, n) > 2)) { cout << 1 << n ; cout << n << << m << << 1 << << 1 << n ; for (int i = 1; i <= m; ++i) { if (i % 2) { for (int j = 1; j <= n; ++j) cout << j << << i << n ; } else { for (int j = n; j >= 1; --j) cout << j << << i << n ; } } cout << 1 << << 1; } else { cout << 0 << n ; if (n % 2 == 0) { for (int i = 1; i <= m; ++i) cout << 1 << << i << n ; for (int i = 2; i <= n; ++i) { if (i % 2) { for (int j = 2; j <= m; ++j) cout << i << << j << n ; } else { for (int j = m; j >= 2; --j) cout << i << << j << n ; } } for (int i = n; i >= 1; --i) cout << i << << 1 << n ; } else { for (int i = 1; i <= n; ++i) cout << i << << 1 << n ; for (int i = 2; i <= m; ++i) { if (i % 2) { for (int j = 2; j <= n; ++j) cout << j << << i << n ; } else { for (int j = n; j >= 2; --j) cout << j << << i << n ; } } for (int i = m; i >= 1; --i) cout << 1 << << i << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_TB_V
`define SKY130_FD_SC_HD__A21BO_TB_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21bo.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__a21bo dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_TB_V
|
module zeowaa
(
input clk_50,
input [ 5:2] key,
input [ 7:0] sw,
output [11:0] led,
output [ 7:0] hex,
output [ 7:0] digit,
output buzzer
);
// wires & inputs
wire clkCpu;
wire clkIn = clk_50;
wire rst_n = key[4];
wire clkEnable = ~sw[ 7] | ~key[5];
wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
wire [ 4:0 ] regAddr = ~sw[4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign led[0] = ~clkCpu;
assign led[11:1] = ~regData[11:0];
//hex out
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b0 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( hex[6:0] ),
.dot ( hex[7] ),
.anodes ( digit )
);
assign buzzer = 1'b1;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:54:36 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [31:0]probe2;
input [31:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct T { int lz, sz; int v[2], t[2], f1[2], f2[2]; T(int x = 1) { lz = 0, sz = x; for (int i = 0; i < 2; i++) { v[i] = f1[i] = x; t[i] = f2[i] = 0; } } void upd() { for (int i = 0; i < 2; i++) t[i] ^= 1; swap(v[0], v[1]); lz ^= 1; } friend T operator+(T l, T r) { T ret(0); T c[2] = {l, r}; int first = 0, g = 0; for (int i = 0; i < 2; i++) ret.v[i] = 0; for (int i = 0; i < 2; i++) { first += c[i].f1[!i]; g ^= c[i].t[!i]; ret.sz += c[i].sz; ret.t[i] = c[i].t[i]; if (c[i].f1[i] == c[i].sz) { if (c[i].t[i] == c[!i].t[i]) { ret.f1[i] = c[i].f1[i] + c[!i].f1[i]; ret.f2[i] = c[!i].f2[i]; } else { ret.f1[i] = c[i].f1[i]; ret.f2[i] = c[!i].f1[i]; } } else { ret.f1[i] = c[i].f1[i]; ret.f2[i] = c[i].f2[i]; ret.f2[i] += (ret.f1[i] + ret.f2[i] == c[i].sz && c[i].t[i] != c[!i].t[i]) * c[!i].f1[i]; } for (int j = 0; j < 2; j++) ret.v[j] = max({ret.v[j], ret.f1[i], ret.f2[i], c[i].v[j]}); } if (g) { ret.v[c[0].t[1]] = max(ret.v[c[0].t[1]], first); } else { for (int i = 0; i < 2; i++) { int j = !i ^ c[i].t[!i]; ret.v[j] = max(ret.v[j], first + c[i].f2[!i]); } } return ret; } }; struct segTree { int l, r; segTree *c[2]; T val; segTree(int a, int b) { l = a, r = b; val.sz = r - l + 1; if (l != r) { int mid = (l + r) / 2; c[0] = new segTree(l, mid); c[1] = new segTree(mid + 1, r); val = c[0]->val + c[1]->val; } } T add(int a, int b) { if (b < l || r < a) return T(0); if (a <= l && r <= b) { val.upd(); return val; } T ret[2]; for (int i = 0; i < 2; i++) { if (val.lz) c[i]->val.upd(); ret[i] = c[i]->add(a, b); } val = c[0]->val + c[1]->val; return ret[0] + ret[1]; } }; const int mxn = 500000; int n, q; segTree tre(1, mxn); int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> q; for (int i = 1; i <= n; i++) { char c; cin >> c; if (c == < ) tre.add(i, i); } while (q--) { int l, r; cin >> l >> r; cout << tre.add(l, r).v[0] << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_PP_SYMBOL_V
|
`include "datapath/pc.v"
`include "datapath/alu.v"
`include "datapath/dm.v"
`include "datapath/ext.v"
`include "datapath/im.v"
`include "datapath/npc.v"
`include "datapath/rf.v"
`include "datapath/mux.v"
`include "control/ctrl.v"
module mips (clk, rst);
input clk;
input rst;
wire [31:0] pc_next;
wire [31:0] pc_cur;
wire [31:0] ins;
wire [31:0] ext_imm;
wire [31:0] routa;
wire [31:0] routb;
wire [31:0] rin;
wire [31:0] aluSrc_mux_out;
wire [31:0] alu_out;
wire [31:0] dm_out;
wire [4:0] rWin;
wire [3:0] aluCtr;
wire branch;
wire jump;
wire regDst;
wire aluSrc;
wire regWr;
wire memWr;
wire extOp;
wire memtoReg;
wire zero;
pc pc(
.clk(clk),
.rst(rst),
.niaddr(pc_next),
.iaddr(pc_cur)
);
npc npc(
.iaddr(pc_cur),
.branch(branch),
.jump(jump),
.zero(zero),
.imm16(ins[15:0]),
.imm26(ins[25:0]),
.niaddr(pc_next)
);
im_4k im(
.iaddr(pc_cur[11:2]),
.ins(ins)
);
ext extOp_ext(
.imm16(ins[15:0]),
.extOp(extOp),
.dout(ext_imm)
);
mux #(32) aluSrc_mux(
.a(routb),
.b(ext_imm),
.ctrl_s(aluSrc),
.dout(aluSrc_mux_out)
);
mux #(5) regDst_mux(
.a(ins[20:16]),
.b(ins[15:11]),
.ctrl_s(regDst),
.dout(rWin)
);
regFile rf(
.busW(rin),
.clk(clk),
.wE(regWr),
.rW(rWin),
.rA(ins[25:21]),
.rB(ins[20:16]),
.busA(routa),
.busB(routb)
);
alu alu(
.ALUop(aluCtr),
.a(routa),
.b(aluSrc_mux_out),
.result(alu_out),
.zero(zero)
);
dm_4k dm(
.addr(alu_out[11:2]),
.din(routb),
.wEn(memWr),
.clk(clk),
.dout(dm_out)
);
mux memtoReg_mux(
.a(alu_out),
.b(dm_out),
.ctrl_s(memtoReg),
.dout(rin)
);
ctrl ctrl(
.ins(ins),
.branch(branch),
.jump(jump),
.regDst(regDst),
.aluSrc(aluSrc),
.aluCtr(aluCtr),
.regWr(regWr),
.memWr(memWr),
.extOp(extOp),
.memtoReg(memtoReg)
);
endmodule // MIPS main program;
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module spi_dma_ext
(
// General
clk_i,
rst_i,
// SPI Interface
spi_clk_o,
spi_ss_o,
spi_mosi_o,
spi_miso_i,
// Memory interface
mem_address_o,
mem_data_o,
mem_data_i,
mem_rd_o,
mem_wr_o,
// Control
xfer_count_i,
xfer_address_i,
xfer_start_i,
xfer_rx_only_i,
xfer_done_o,
xfer_busy_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter MEM_ADDR_WIDTH = 18;
parameter XFER_COUNT_WIDTH = 32;
parameter SPI_CLK_DIV = 4;
parameter TRANSFER_WIDTH = 8;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
// General
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
// SPI Interface
output spi_clk_o /*verilator public*/;
output spi_ss_o /*verilator public*/;
output spi_mosi_o /*verilator public*/;
input spi_miso_i /*verilator public*/;
// Memory interface
output[MEM_ADDR_WIDTH - 1:0] mem_address_o /*verilator public*/;
output[TRANSFER_WIDTH - 1:0] mem_data_o /*verilator public*/;
input[TRANSFER_WIDTH - 1:0] mem_data_i /*verilator public*/;
output mem_rd_o /*verilator public*/;
output mem_wr_o /*verilator public*/;
// Control
input[XFER_COUNT_WIDTH - 1:0] xfer_count_i /*verilator public*/;
input[MEM_ADDR_WIDTH - 1:0] xfer_address_i /*verilator public*/;
input xfer_start_i /*verilator public*/;
input xfer_rx_only_i /*verilator public*/;
output xfer_done_o /*verilator public*/;
output xfer_busy_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire spim_start;
wire spim_done;
wire spim_busy;
wire [TRANSFER_WIDTH - 1:0] spim_data_tx;
wire [TRANSFER_WIDTH - 1:0] spim_data_rx;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// SPI Master
spi_master
#(
.CLK_DIV(SPI_CLK_DIV),
.TRANSFER_WIDTH(TRANSFER_WIDTH)
)
U1_SPIM
(
// Clocking / Reset
.clk_i(clk_i),
.rst_i(rst_i),
// Control & Status
.start_i(spim_start),
.done_o(spim_done),
.busy_o(spim_busy),
// Data
.data_i(spim_data_tx),
.data_o(spim_data_rx),
// SPI interface
.spi_clk_o(spi_clk_o),
.spi_ss_o(spi_ss_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
// DMA controller
spi_ctrl
#(
.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
.XFER_COUNT_WIDTH(XFER_COUNT_WIDTH),
.TRANSFER_WIDTH(TRANSFER_WIDTH)
)
U2_SPI_DMA
(
// General
.clk_i(clk_i),
.rst_i(rst_i),
// Memory interface
.mem_address_o(mem_address_o),
.mem_data_o(mem_data_o),
.mem_data_i(mem_data_i),
.mem_rd_o(mem_rd_o),
.mem_wr_o(mem_wr_o),
// SPI Access
.spi_start_o(spim_start),
.spi_done_i(spim_done),
.spi_busy_i(spim_busy),
.spi_data_i(spim_data_rx),
.spi_data_o(spim_data_tx),
// Control
.xfer_count_i(xfer_count_i),
.xfer_address_i(xfer_address_i),
.xfer_start_i(xfer_start_i),
.xfer_rx_only_i(xfer_rx_only_i),
.xfer_done_o(xfer_done_o),
.xfer_busy_o(xfer_busy_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n], vis[200005] = {0}; for (int i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] <= n) vis[arr[i]]++; } sort(arr, arr + n); vector<int> v; for (int i = 1; i <= n; i++) { if (!vis[i]) v.push_back(i); } int m = v.size(), l = 0; int ans = 0; for (int i = 0; i < n; i++) { int x = arr[i]; if (x <= n && vis[x] > 1) { int r = vis[x], k = 1; while (r > 1) { if (l < m && (2 * v[l]) < x) { ans++; l++; } else { ans = -1; k = 0; break; } r--; i++; } if (!k) break; } if (x > n) { if (l < m && (2 * v[l]) < x) { ans++; l++; } else { ans = -1; break; } } } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b != 0) return gcd(b, a % b); else return a; } long long int power(long long int a, long long int b) { if (b == 0) return 1; if (b == 1) return a; if (b % 2 == 0) { long long int t = power(a, b / 2); return t * t; } else { long long int t = power(a, b / 2); return a * t * t; } } long long int powin(long long int a, long long int b) { if (b == 0) return 1; else if (b == 1) return a; else if (b % 2 == 0) { long long int t = powin(a, b / 2); return (t * t) % 1000000007; } else { long long int t = powin(a, b / 2); return (((t * t) % 1000000007) * a) % 1000000007; } } long long int n, k; long long int dp[509][10 * 509]; long long int h[20]; void solve() { for (long long int i = 1; i < n + 1; i++) { for (long long int j = 1; j < k * n + 1; j++) { for (long long int p = 1; p < k + 1; p++) { if (j >= p) dp[i][j] = max(dp[i][j], dp[i - 1][j - p] + h[p]); } } } } long long int fr[100000 + 10]; long long int f[100000 + 10]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; memset(dp, 0, sizeof dp); memset(fr, 0, sizeof fr); memset(f, 0, sizeof f); for (long long int i = 0; i < n * k; i++) { long long int t; cin >> t; fr[t]++; } for (long long int i = 0; i < n; i++) { int p; cin >> p; f[p]++; } h[0] = 0; for (long long int i = 1; i < k + 1; i++) { cin >> h[i]; dp[1][i] = h[i]; } solve(); long long int ans = 0; for (long long int i = 1; i < 100000 + 1; i++) { if (f[i] > 0) { long long int temp = 0; for (long long int j = 1; j < f[i] + 1; j++) { temp = max(dp[j][fr[i]], temp); } ans += temp; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 5; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long r; cin >> r; for (long long i = 1; i * i <= r; i++) { long long y = r - i * i - i - 1; if (y > 0 && y % (2 * i) == 0) { cout << i << << y / (2 * i) << n ; return 0; } } cout << NO << n ; return 0; }
|
//==================================================================================================
// Filename : antares_cloz.v
// Created On : Thu Sep 3 16:03:13 2015
// Last Modified : Sat Nov 07 11:49:40 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Count leading ones/zeros unit.
//==================================================================================================
module antares_cloz (
input [31:0] A,
output [5:0] clo_result,
output [5:0] clz_result
);
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [5:0] clo_result;
reg [5:0] clz_result;
// End of automatics
//--------------------------------------------------------------------------
// Count Leading Ones
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd0;
32'b10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd1;
32'b110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd2;
32'b1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd3;
32'b1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd4;
32'b1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd5;
32'b1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd6;
32'b1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd7;
32'b1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd8;
32'b1111_1111_10zz_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd9;
32'b1111_1111_110z_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd10;
32'b1111_1111_1110_zzzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd11;
32'b1111_1111_1111_0zzz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd12;
32'b1111_1111_1111_10zz_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd13;
32'b1111_1111_1111_110z_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd14;
32'b1111_1111_1111_1110_zzzz_zzzz_zzzz_zzzz : clo_result = 6'd15;
32'b1111_1111_1111_1111_0zzz_zzzz_zzzz_zzzz : clo_result = 6'd16;
32'b1111_1111_1111_1111_10zz_zzzz_zzzz_zzzz : clo_result = 6'd17;
32'b1111_1111_1111_1111_110z_zzzz_zzzz_zzzz : clo_result = 6'd18;
32'b1111_1111_1111_1111_1110_zzzz_zzzz_zzzz : clo_result = 6'd19;
32'b1111_1111_1111_1111_1111_0zzz_zzzz_zzzz : clo_result = 6'd20;
32'b1111_1111_1111_1111_1111_10zz_zzzz_zzzz : clo_result = 6'd21;
32'b1111_1111_1111_1111_1111_110z_zzzz_zzzz : clo_result = 6'd22;
32'b1111_1111_1111_1111_1111_1110_zzzz_zzzz : clo_result = 6'd23;
32'b1111_1111_1111_1111_1111_1111_0zzz_zzzz : clo_result = 6'd24;
32'b1111_1111_1111_1111_1111_1111_10zz_zzzz : clo_result = 6'd25;
32'b1111_1111_1111_1111_1111_1111_110z_zzzz : clo_result = 6'd26;
32'b1111_1111_1111_1111_1111_1111_1110_zzzz : clo_result = 6'd27;
32'b1111_1111_1111_1111_1111_1111_1111_0zzz : clo_result = 6'd28;
32'b1111_1111_1111_1111_1111_1111_1111_10zz : clo_result = 6'd29;
32'b1111_1111_1111_1111_1111_1111_1111_110z : clo_result = 6'd30;
32'b1111_1111_1111_1111_1111_1111_1111_1110 : clo_result = 6'd31;
32'b1111_1111_1111_1111_1111_1111_1111_1111 : clo_result = 6'd32;
default : clo_result = 6'd0;
endcase // casez (A)
end // always @ (*)
//--------------------------------------------------------------------------
// Count Leading Zeros
//--------------------------------------------------------------------------
always @(*) begin
casez (A)
32'b1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd0;
32'b01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd1;
32'b001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd2;
32'b0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd3;
32'b0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd4;
32'b0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd5;
32'b0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd6;
32'b0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd7;
32'b0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd8;
32'b0000_0000_01zz_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd9;
32'b0000_0000_001z_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd10;
32'b0000_0000_0001_zzzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd11;
32'b0000_0000_0000_1zzz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd12;
32'b0000_0000_0000_01zz_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd13;
32'b0000_0000_0000_001z_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd14;
32'b0000_0000_0000_0001_zzzz_zzzz_zzzz_zzzz : clz_result = 6'd15;
32'b0000_0000_0000_0000_1zzz_zzzz_zzzz_zzzz : clz_result = 6'd16;
32'b0000_0000_0000_0000_01zz_zzzz_zzzz_zzzz : clz_result = 6'd17;
32'b0000_0000_0000_0000_001z_zzzz_zzzz_zzzz : clz_result = 6'd18;
32'b0000_0000_0000_0000_0001_zzzz_zzzz_zzzz : clz_result = 6'd19;
32'b0000_0000_0000_0000_0000_1zzz_zzzz_zzzz : clz_result = 6'd20;
32'b0000_0000_0000_0000_0000_01zz_zzzz_zzzz : clz_result = 6'd21;
32'b0000_0000_0000_0000_0000_001z_zzzz_zzzz : clz_result = 6'd22;
32'b0000_0000_0000_0000_0000_0001_zzzz_zzzz : clz_result = 6'd23;
32'b0000_0000_0000_0000_0000_0000_1zzz_zzzz : clz_result = 6'd24;
32'b0000_0000_0000_0000_0000_0000_01zz_zzzz : clz_result = 6'd25;
32'b0000_0000_0000_0000_0000_0000_001z_zzzz : clz_result = 6'd26;
32'b0000_0000_0000_0000_0000_0000_0001_zzzz : clz_result = 6'd27;
32'b0000_0000_0000_0000_0000_0000_0000_1zzz : clz_result = 6'd28;
32'b0000_0000_0000_0000_0000_0000_0000_01zz : clz_result = 6'd29;
32'b0000_0000_0000_0000_0000_0000_0000_001z : clz_result = 6'd30;
32'b0000_0000_0000_0000_0000_0000_0000_0001 : clz_result = 6'd31;
32'b0000_0000_0000_0000_0000_0000_0000_0000 : clz_result = 6'd32;
default : clz_result = 6'd0;
endcase // casez (A)
end // always @ (*)
endmodule // antares_cloz
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#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int n, i, j, k, cnt, tot, f[maxn]; char s[maxn]; int main() { scanf( %d%s , &n, s + 1); if (n & 1) return puts( 0 ), 0; tot = n >> 1; f[0] = 1; for (i = 1; i <= n; i++) { if (s[i] == ? ) for (j = i >> 1, k = max(1, tot - (n - i)); j >= k; j--) f[j] = f[j] + f[j - 1]; else cnt++; } if (cnt > tot) return puts( 0 ), 0; int ans = f[tot]; for (i = tot - cnt; i; i--) ans *= 25; printf( %u , ans); return 0; }
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