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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (GATE , GATE_N_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<int> di = {0, 0, 1, -1}; vector<int> dj = {1, -1, 0, 0}; int main() { ios::sync_with_stdio(0), cin.tie(0); vector<vector<int>> dpa(1001, vector<int>(1001, 2140000000)); vector<vector<int>> dpb(1001, vector<int>(1001, 2140000000)); vector<vector<int>> dpc(1001, vector<int>(1001, 2140000000)); vector<vector<pair<int, int>>> pa( 1001, vector<pair<int, int>>(1001, {2140000000, 0})); vector<vector<pair<int, int>>> pb( 1001, vector<pair<int, int>>(1001, {2140000000, 0})); vector<vector<pair<int, int>>> pc( 1001, vector<pair<int, int>>(1001, {2140000000, 0})); int xa, ya; cin >> xa >> ya; dpa[xa][ya] = 0; int xb, yb; cin >> xb >> yb; dpb[xb][yb] = 0; int xc, yc; cin >> xc >> yc; dpc[xc][yc] = 0; queue<pair<int, int>> q; q.push({xa, ya}); while (!q.empty()) { int vx = q.front().first; int vy = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { int tx = vx + di[i]; int ty = vy + dj[i]; if (tx >= 0 && tx <= 1000 && ty >= 0 && ty <= 1000 && dpa[tx][ty] == 2140000000) { q.push({tx, ty}); dpa[tx][ty] = dpa[vx][vy] + 1; pa[tx][ty] = {vx, vy}; } } } q.push({xb, yb}); while (!q.empty()) { int vx = q.front().first; int vy = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { int tx = vx + di[i]; int ty = vy + dj[i]; if (tx >= 0 && tx <= 1000 && ty >= 0 && ty <= 1000 && dpb[tx][ty] == 2140000000) { q.push({tx, ty}); dpb[tx][ty] = dpb[vx][vy] + 1; pb[tx][ty] = {vx, vy}; } } } q.push({xc, yc}); while (!q.empty()) { int vx = q.front().first; int vy = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { int tx = vx + di[i]; int ty = vy + dj[i]; if (tx >= 0 && tx <= 1000 && ty >= 0 && ty <= 1000 && dpc[tx][ty] == 2140000000) { q.push({tx, ty}); dpc[tx][ty] = dpc[vx][vy] + 1; pc[tx][ty] = {vx, vy}; } } } int ans = 2140000000; int ansx; int ansy; for (int i = 0; i <= 1000; i++) { for (int j = 0; j <= 1000; j++) { if (dpa[i][j] + dpb[i][j] + dpc[i][j] + 1 < ans) { ans = dpa[i][j] + dpb[i][j] + dpc[i][j] + 1; ansx = i; ansy = j; } } } cout << ans << endl; int sax = ansx; int say = ansy; int sbx = ansx; int sby = ansy; int scx = ansx; int scy = ansy; vector<vector<int>> used(1001, vector<int>(1001, 0)); while (make_pair(sax, say) != make_pair(2140000000, 0)) { int tx = sax; sax = pa[sax][say].first; say = pa[tx][say].second; if (make_pair(sax, say) != make_pair(2140000000, 0) && !used[sax][say]) { cout << sax << << say << endl; used[sax][say] = 1; } } while (make_pair(sbx, sby) != make_pair(2140000000, 0)) { int tx = sbx; sbx = pb[sbx][sby].first; sby = pb[tx][sby].second; if (make_pair(sbx, sby) != make_pair(2140000000, 0) && !used[sbx][sby]) { cout << sbx << << sby << endl; used[sbx][sby] = 1; } } while (make_pair(scx, scy) != make_pair(2140000000, 0)) { int tx = scx; scx = pc[scx][scy].first; scy = pc[tx][scy].second; if (make_pair(scx, scy) != make_pair(2140000000, 0) && !used[scx][scy]) { cout << scx << << scy << endl; used[scx][scy] = 1; } } cout << ansx << << ansy << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long int MOD = 1e9 + 7; long long int t; string s; long long int n; long long int dp[100][2501]; long long int adp[100][2501]; long long int l, r, sm; void solve() { cin >> s; n = s.length() - 1; sm = 0; for (auto it : s) sm += it - a ; l = adp[n][sm] - 1; if (l < 0) l += MOD; cout << l << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); for (int i = 0; i < 26; i++) adp[0][i] = dp[0][i] = 1; for (int i = 1; i <= 2500; i++) { dp[0][i] += dp[0][i - 1]; dp[0][i] %= MOD; } for (int i = 1; i < 100; i++) { for (int j = 0; j <= 2500; j++) { l = r = 0; if (j - 26 >= 0) l = dp[i - 1][j - 26]; r = dp[i - 1][j]; dp[i][j] = r - l; if (dp[i][j] < 0) dp[i][j] += MOD; dp[i][j] %= MOD; adp[i][j] = dp[i][j]; if (j != 0) { dp[i][j] += dp[i][j - 1]; dp[i][j] %= MOD; } } } t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_op( clock, resetn, left_mantissa, right_mantissa, left_sign, right_sign, common_exponent,
resulting_mantissa, resulting_exponent, resulting_sign,
valid_in, valid_out, stall_in, stall_out, enable);
parameter HIGH_CAPACITY = 1;
// Latency = 1 cycle.
input clock, resetn, left_sign, right_sign;
input [26:0] left_mantissa;
input [26:0] right_mantissa;
input [8:0] common_exponent;
input valid_in, stall_in, enable;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [27:0] resulting_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [8:0] resulting_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg resulting_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg valid_out;
output stall_out;
wire enable_add = (HIGH_CAPACITY==1) ? (~valid_out | ~stall_in) : enable;
wire do_subtraction = right_sign ^ left_sign;
assign stall_out = valid_out & stall_in;
wire [27:0] op_ab = left_mantissa + ({28{do_subtraction}} ^ right_mantissa) + do_subtraction;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
resulting_mantissa <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
resulting_exponent <= 9'bxxxxxxxx;
resulting_sign <= 1'bx;
valid_out <= 1'b0;
end
else if (enable_add)
begin
valid_out <= valid_in;
resulting_mantissa <= op_ab;
resulting_exponent <= common_exponent;
resulting_sign <= left_sign;
end
end
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
Pin 8: Power-on reset flag
Pin 9: Always high
Pin 10: Power-on reset flag
TEST PROCEDURE:
Verify pins 8, 9, and 10 all go high after the device is programmed.
TODO: is there a good way to characterize timing?
*/
module POR(rst_out1, one, rst_out2);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P8" *)
output wire rst_out1;
(* LOC = "P9" *)
output wire one;
(* LOC = "P10" *)
output wire rst_out2;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reset logic
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
assign one = 1'b1;
assign rst_out1 = por_done;
assign rst_out2 = por_done;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model of the noise generator
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "noisegen.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_noise_gen();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the noise generator
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] n; // Output signal noise
// Declare "reg" signals: inputs to the DUT
reg [7:0] err; // Input signal - error
reg [7:0] error_level; // Input signal - err_level
/**
* Instantiate an instance of noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "n_g"
*/
noise_generator n_g (
// instance_name(signal name),
// Signal name can be the same as the instance name
err,n,error_level);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
err = 8'd1;
error_level = 8'd100;
// @t=10,
#10
err = 8'd103;
error_level = 8'd100;
// @t=20,
#10
err = 8'd205;
error_level = 8'd100;
// @t=30,
#10
err = 8'd251;
error_level = 8'd100;
// @t=40,
#10
err = 8'd79;
error_level = 8'd100;
// @t=50,
#10
err = 8'd37;
error_level = 8'd10;
// @t=60,
#10
err = 8'd7;
error_level = 8'd10;
// @t=70,
#10
err = 8'd10;
error_level = 8'd10;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 10; const int MAXN = 1e4 + 10; const int MOD = 1e9 + 7; const int inf = 1e9; const double pi = acos(-1.0); const double eps = 1e-6; int dx[] = {0, -1, 0, 1}; int dy[] = {1, 0, -1, 0}; map<int, int> mymap, mymap1; int n, m; vector<int> Ve, Vo; int save[200100]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; int res = 0; for (int i = 1; i <= n; i++) { int x; cin >> x; if (x % 2) { if (!mymap[x]) { Vo.push_back(x); mymap[x] = 1; mymap1[x] = i; } } else { if (!mymap[x]) { Ve.push_back(x); mymap[x] = 1; mymap1[x] = i; } } } int o = Vo.size(); int e = Ve.size(); int r = -1; if (o >= n / 2 && e <= n / 2) r = min(o - n / 2, n / 2 - e); else if (o <= n / 2 && e >= n / 2) r = min(n / 2 - o, e - n / 2); if (r != -1) { res += r; if (o <= n / 2) { o += r; e -= r; } else { o -= r; e += r; } } res += max(n / 2 - o, 0); res += max(n / 2 - e, 0); for (int i = 1; i <= min(n, m); i++) if (i % 2) { if (!mymap[i]) { mymap[i] = 1; Vo.push_back(i); } } else { if (!mymap[i]) { mymap[i] = 1; Ve.push_back(i); } } o = Vo.size(); e = Ve.size(); if (o >= n / 2 && e >= n / 2) { cout << res << endl; vector<int> K; K.clear(); for (int i = 0; i < n / 2; i++) if (mymap1[Vo[i]]) save[mymap1[Vo[i]]] = Vo[i]; else K.push_back(Vo[i]); for (int i = 0; i < n / 2; i++) if (mymap1[Ve[i]]) save[mymap1[Ve[i]]] = Ve[i]; else K.push_back(Ve[i]); int p = 1; int q = 0; while (p <= n && q < K.size()) if (save[p]) p++; else { save[p] = K[q]; p++; q++; } for (int i = 1; i <= n; i++) cout << save[i] << ; } else cout << -1; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s6s (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; if (n == 1) cout << 1 << endl; else cout << (n / 2) << endl; } return 0; }
|
/*
* Verification test for increment/decrement operators
*
* Author: Prasad Joshi <>
*/
module main;
logic la;
logic lb;
int ia;
int ib;
bit ba;
bit bb;
real ra;
real rb;
real rc;
initial begin
/* logic tests */
la = 0;
#1
lb = ++la;
#1
if (la != lb) begin
$display("FAILED");
$finish;
end
ib = 15;
#1
ia = ++ib;
#1
if (ia != ib) begin
$display("FAILED");
$finish;
end
ia = 15;
#1
ib = ia++;
#1
if (ia != 16 || ib != 15) begin
$display("FAILED");
$finish;
end
ib = --ia;
if (ib != ia) begin
$display("FAILED");
$finish;
end
/* bit test */
ba = 0;
#1
for (ia = 0; ia < 10; ia = ia + 1) begin
bb = --ba;
#1
if (bb != ba && !(bb == 1 || bb == 0)) begin
$display("FAILED");
$finish;
end
end
/* real decrement test */
ia = 15;
ra = --ia;
if (ra != ia) begin
$display("FAILED");
$finish;
end
rb = 19.99;
rc = rb - 2;
ra = --rb;
if (ra != rb) begin
$display("FAILED");
$finish;
end
ra = rb--;
if (ra == rb || rc != rb) begin
$display("FAILED");
$finish;
end
/* real increment test */
ia = 15;
ra = ++ia;
if (ra != ia) begin
$display("FAILED");
$finish;
end
rb = 19.99;
rc = rb + 2;
ra = ++rb;
if (ra != rb) begin
$display("FAILED");
$finish;
end
ra = rb++;
if (ra == rb || rc != rb) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
module tb_fmrv32im_max10;
reg sim_end;
reg RST_N;
reg CLK;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_max10.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_max10.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_max10.u_fmrv32im_core.dbus_wdata;
end
end
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
fmrv32im_max10
#(
.MEM_FILE ("../../../../src/imem.mif")
)
u_fmrv32im_max10
(
.CLK48MHZ (CLK),
.led (led)
);
endmodule // tb_fmrv32im_core
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Ryan
//
// Create Date: 06/07/2017
// Module Name: Main Module
// Project Name: Joystick controller
// Target Devices: ICE40/Icestick
// Tool versions: APIO/Icestorm
// Description: This module uses the Digilent PMOD JSTK2 to play around with and learn
// how to interface with serial communications.
// The positional data of the joystick ranges from 0 to 1023 in
// both the X and Y directions. The center LED will illuminate when a button is pressed.
// SPI mode 0 is used for communication between the PmodJSTK and the FPGA.
//////////////////////////////////////////////////////////////////////////////////
// Top level entitiy
// ==============================================================================
// Define Module
// ==============================================================================
module Main_Control(
clk,
rst,
LED,
JSTK_SS,
JSTK_MOSI,
JSTK_MISO,
JSTK_SCK
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input clk; // 12Mhz onboard clock
input rst; // reset command, not implemented
output [4:0] LED; // On-board LEDs
input JSTK_MISO; // Master In Slave Out
output JSTK_SS; // Slave Select
output JSTK_MOSI; // Master Out Slave In
output JSTK_SCK; // Serial Clock
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Signal to send/receive data to/from PMOD peripherals
wire sndRec;
// Data read from PmodJSTK
wire [39:0] jstkData;
// Signal carrying joystick X data
wire [9:0] XposData;
// Signal carrying joystick Y data
wire [9:0] YposData;
// Holds data to be sent to PmodJSTK
wire [39:0] sndData;
// Currently selected color for system
wire [23:0] RGBcolor;
// ===========================================================================
// Implementation
// ===========================================================================
//-----------------------------------------------
// PmodJSTK Interface
//-----------------------------------------------
PmodJSTK PmodJSTK_Int(
.CLK(clk),
.RST(rst),
.sndRec(sndRec),
.DIN(sndData),
.MISO(JSTK_MISO),
.SS(JSTK_SS),
.SCLK(JSTK_SCK),
.MOSI(JSTK_MOSI),
.DOUT(jstkData)
);
//-----------------------------------------------
// Cycle colors based on joystick button
//-----------------------------------------------
RGB_color_set Select_Color(
.clk(clk),
.button(jstkData[1:0]),
.RGBcolor(RGBcolor)
);
//-----------------------------------------------
// System update timing Generator
//-----------------------------------------------
ClkDiv_20Hz genSndRec(
.CLK(clk),
.RST(rst),
.CLKOUT(sndRec)
);
//-----------------------------------------------
// Report joystick shit on on-board LEDs
//-----------------------------------------------
LED_joystick boardLEDcontroller(
.clk(clk),
.xpos(XposData),
.ypos(YposData),
.button(jstkData[1:0]),
.LED(LED)
);
//-----------------------------------------------
// Assignments
//-----------------------------------------------
// Collect joystick state for position state
assign YposData = {jstkData[25:24], jstkData[39:32]};
assign XposData = {jstkData[9:8], jstkData[23:16]};
// Data to be sent to PmodJSTK, first byte signifies to control RGB on PmodJSTK
assign sndData = {8'b10000100, RGBcolor, 8'b00000000};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; int n, a[7], cnt[7], t[N]; void GetData() { int i; scanf( %d , &n); for (i = 0; i < 3; ++i) scanf( %d , &a[i]); for (i = 0; i < n; ++i) scanf( %d , &t[i]); } void Solve() { int i, j, ans, mn; bool flag = false; sort(a, a + 3); sort(t, t + n); a[3] = a[0] + a[1]; a[4] = a[0] + a[2]; a[5] = a[1] + a[2]; a[6] = a[3] + a[2]; if (t[n - 1] > a[6]) ans = -1, mn = 0; else { if (a[2] > a[3]) { swap(a[2], a[3]); flag = true; } memset(cnt, 0, sizeof(cnt)); for (i = 0; i < n; ++i) { for (j = 0; j < 7; ++j) { if (a[j] >= t[i]) { cnt[j]++; break; } } } ans = cnt[6]; for (; cnt[5] > 0; ++ans) { cnt[5]--; if (cnt[0] > 0) cnt[0]--; } for (; cnt[4] > 0; ++ans) { cnt[4]--; if (cnt[1] > 0) cnt[1]--; else if (cnt[0] > 0) cnt[0]--; } if (flag) { for (; cnt[3] > 0; ++ans) { cnt[3]--; if (cnt[0] > 0 && cnt[1] > 0) { cnt[0]--; cnt[1]--; } else if (cnt[0] > 0) { if (cnt[0] > 1) cnt[0] -= 2; else if (cnt[2] > 0) cnt[2]--; else cnt[0]--; } else if (cnt[1] > 0) { if (cnt[2] > 0) cnt[2]--; else cnt[1]--; } else if (cnt[2] > 0) cnt[2]--; } } else { for (; cnt[3] > 0; ++ans) { cnt[3]--; if (cnt[2] > 0) cnt[2]--; else if (cnt[1] > 0) cnt[1]--; else if (cnt[0] > 0) cnt[0]--; } } mn = n; for (i = 0; i <= cnt[2]; ++i) { int a, b, c, tmp = i; a = cnt[0]; b = cnt[1]; c = cnt[2]; c -= i; if (c >= i) c -= i; else if (b >= i - c) b -= i - c, c = 0; else { if (a >= i - c - b) a -= i - c - b; else a = 0; b = c = 0; } if (c > 0) { if (b < c) a = max(0, a - c - c + b); else a = max(0, a - c); b = max(0, b - c); tmp += c; } if (b >= a * 2) tmp += (b + 1) / 2; else tmp += (a + b + 2) / 3; mn = min(mn, tmp); } } printf( %d n , ans + mn); } int main() { GetData(); Solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_1_V
`define SKY130_FD_SC_HD__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_1_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-12; const int INF = 1 << 30; const long long LINF = 1ll << 61; const int BUFFER_SZ = 1 << 20; const int MOD = 1000 * 1000 * 1000 + 7; char BUFFER[BUFFER_SZ]; int gi() { int x; scanf( %d , &x); return x; } double gd() { double x; scanf( %lf , &x); return x; } long long gll() { long long x; scanf( %lld , &x); return x; } vector<int> gvi(int n) { vector<int> a; while (n-- > 0) a.push_back(gi()); return a; } string gs() { scanf( %s , BUFFER); return string(BUFFER); } template <class T> void print(vector<T> &x, string format) { format += %c ; for (int i = 0; i < x.size(); ++i) printf(format.c_str(), x[i], i + 1 == x.size() ? n : ); } void solve() { int n = gi(); vector<int> a = gvi(n); for (int i = 0; i < a.size(); ++i) { for (int j = i + 1; j < a.size(); ++j) { for (int k = j + 1; k < a.size(); ++k) { if (a[i] == a[j] + a[k]) { printf( %d %d %d n , i + 1, j + 1, k + 1); return; } if (a[j] == a[i] + a[k]) { printf( %d %d %d n , j + 1, i + 1, k + 1); return; } if (a[k] == a[i] + a[j]) { printf( %d %d %d n , k + 1, i + 1, j + 1); return; } } } } printf( -1 n ); } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> add_pair(pair<long long, long long> a, pair<long long, long long> b) { return make_pair(a.first + b.first, a.second + b.second); } long long power(long long a, long long b) { long long res = 1; a = a % ((long long)1e9 + 7); while (b > 0) { if (b & 1) { res = (res * a) % ((long long)1e9 + 7); b--; } a = (a * a) % ((long long)1e9 + 7); b >>= 1; } return res; } long long fermat_inv(long long y) { return power(y, ((long long)1e9 + 7) - 2); } long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } long long mul(long long a, long long b) { return (a * (b % ((long long)1e9 + 7))) % ((long long)1e9 + 7); } long long sub(long long a, long long b) { return ((a - b) % ((long long)1e9 + 7) + ((long long)1e9 + 7)) % ((long long)1e9 + 7); } long long add(long long a, long long b) { return ((a + b) % ((long long)1e9 + 7) + ((long long)1e9 + 7)) % ((long long)1e9 + 7); } vector<vector<int> > G; int n, ans; void bfs(int rt) { int x; queue<int> q; vector<int> d(n), par(n); vector<bool> vis(n, false); d[rt] = 0; par[rt] = rt; q.push(rt); while (!q.empty()) { x = q.front(); vis[x] = true; q.pop(); for (auto it = (G[x]).begin(); it != (G[x]).end(); it++) { if (!vis[*it]) { d[*it] = d[x] + 1; par[*it] = x; vis[*it] = true; q.push(*it); } else { if (*it != par[x] && par[*it] != x) { ans = min(ans, d[x] + d[*it] + 1); if (ans == 3) return; } } } } } void solve() { int i, j; long long x; cin >> n; vector<long long> a; vector<int> cnt(61, 0ll); for (i = (0); i < (n); i += (1)) { cin >> x; if (x == 0) continue; a.push_back(x); for (j = 0; j < 61; j++) { if (x & (1ll << j)) { cnt[j]++; } } } for (i = (0); i < (61); i += (1)) { if (cnt[i] > 2) { cout << 3 << n ; return; } } n = (a).size(); G = vector<vector<int> >(n, vector<int>()); ans = n + 1; for (i = (0); i < (n); i += (1)) { for (j = (0); j < (i); j += (1)) { if (a[i] & a[j]) { G[i].push_back(j); G[j].push_back(i); } } } for (i = (0); i < (n); i += (1)) { bfs(i); if (ans == 3) break; } if (ans == n + 1) cout << -1 << n ; else cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; t = 1; while (t--) { solve(); } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_bscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_bscan(q_dn_mux_l ,rst_val_up ,mode_ctl ,serial_out ,
bsr_so ,bsr_si ,se ,q25_dn_pad_l ,q_up_pad ,update_dr ,out_type ,
q25_dn_mux_l ,bsr_data_to_core ,rcvr_data_to_bsr ,shift_dr ,up_open
,ps_select ,q_dn_pad_l ,sel_data_n ,bypass_enable ,q_up_mux ,
down_25 ,rst_val_dn ,clk ,serial_in ,hiz_l ,rst_io_l ,clock_dr ,
bypass_in );
output q_dn_mux_l ;
output serial_out ;
output bsr_so ;
output q25_dn_mux_l ;
output bsr_data_to_core ;
output sel_data_n ;
output q_up_mux ;
input rst_val_up ;
input mode_ctl ;
input bsr_si ;
input se ;
input q25_dn_pad_l ;
input q_up_pad ;
input update_dr ;
input out_type ;
input rcvr_data_to_bsr ;
input shift_dr ;
input up_open ;
input ps_select ;
input q_dn_pad_l ;
input bypass_enable ;
input down_25 ;
input rst_val_dn ;
input clk ;
input serial_in ;
input hiz_l ;
input rst_io_l ;
input clock_dr ;
input bypass_in ;
wire [1:0] doe ;
wire [1:0] tf ;
wire [2:0] q ;
wire net110 ;
wire net117 ;
wire net119 ;
wire net123 ;
wire bypass ;
wire net127 ;
wire sd_n ;
wire se_n ;
wire net137 ;
wire net140 ;
wire bsr_to_core ;
wire bso_n ;
wire se_in ;
bw_u1_inv_8x so_inv8x (
.z (bsr_so ),
.a (bso_n ) );
bw_io_dtl_flps three_flps (
.d ({rcvr_data_to_bsr ,doe[1:0] } ),
.q ({q } ),
.clk (clock_dr ),
.so (net110 ),
.si (bsr_si ),
.se (net117 ) );
bw_u1_inv_1x ud_inv1x (
.z (net137 ),
.a (update_dr ) );
bw_u1_inv_5x bc_inv5x (
.z (bsr_data_to_core ),
.a (net127 ) );
bw_u1_inv_1x ps_inv1 (
.z (bypass ),
.a (net140 ) );
bw_u1_inv_3x shfdr_inv3x (
.z (net117 ),
.a (sd_n ) );
bw_u1_nand2_1x ps_nand2 (
.z (net140 ),
.a (tf[1] ),
.b (bypass_enable ) );
bw_u1_inv_1x shfdr_inv1x (
.z (sd_n ),
.a (shift_dr ) );
bw_u1_inv_4x so_inv4x (
.z (bso_n ),
.a (net110 ) );
bw_io_dq_pscan pscan (
.serial_in (serial_in ),
.serial_out (serial_out ),
.bypass_in (bypass_in ),
.out_type (out_type ),
.clk (clk ),
.bypass (bypass ),
.ps_select (ps_select ),
.rcv_in (rcvr_data_to_bsr ) );
bw_u1_inv_2x bc_inv2x (
.z (net127 ),
.a (bsr_to_core ) );
bw_io_bs_fsdq_2x three_latches (
.q ({bsr_to_core ,tf[1:0] } ),
.d ({q } ),
.up_dr (net119 ) );
bw_io_dtl_bscl1 comb_lgc_1 (
.intest_oe (doe[0] ),
.intest_d (doe[1] ),
.q_dn_pad (q_dn_pad_l ),
.q25_dn_pad (q25_dn_pad_l ),
.q_up_pad (q_up_pad ) );
bw_io_dtl_bscl2 comb_lgc_2 (
.scan_mode (se_in ),
.mode_ctl (mode_ctl ),
.out_type (out_type ),
.rst_val_dn (rst_val_dn ),
.bscan_oe (tf[0] ),
.sel_data_n (sel_data_n ),
.q25_dn_mux_l (q25_dn_mux_l ),
.down_25 (down_25 ),
.rst_io_l (rst_io_l ),
.ps_select (ps_select ),
.q_dn_mux_l (q_dn_mux_l ),
.up_open (up_open ),
.bscan_d (tf[1] ),
.hiz_l (hiz_l ),
.q_up_mux (q_up_mux ),
.ps_data (serial_out ),
.rst_val_up (rst_val_up ) );
bw_u1_inv_2x se_inv2x (
.z (se_in ),
.a (se_n ) );
bw_u1_inv_3x ud_inv3x (
.z (net119 ),
.a (net123 ) );
bw_u1_inv_1x se_inv1x (
.z (se_n ),
.a (se ) );
bw_u1_inv_2x ud_inv2x (
.z (net123 ),
.a (net137 ) );
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_CS_X.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_BCH_CS_X
// File Name: d_BCH_CS_X.v
//
// Version: v1.0.0-256B_T14
//
// Description:
// - BCH decoder: Chien search (CS) array
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_BCH_CS_X
#
(
parameter Multi = 2,
parameter GF = 12
)
(
i_clk,
i_RESET,
i_exe_cs,
i_data_fowarding,
i_MUX_data_ready,
i_BRAM_read_data,
i_v_000,
i_v_001,
i_v_002,
i_v_003,
i_v_004,
i_v_005,
i_v_006,
i_v_007,
i_v_008,
i_v_009,
i_v_010,
i_v_011,
i_v_012,
i_v_013,
i_v_014,
o_cs_available,
o_cs_cmplt,
o_BRAM_read_enable,
o_BRAM_read_address,
o_c_message_valid,
o_c_message_output_cmplt,
o_c_message
);
input i_clk;
input i_RESET;
input i_exe_cs;
input [Multi - 1:0] i_data_fowarding;
input i_MUX_data_ready;
input [Multi*8 - 1:0] i_BRAM_read_data;
input [GF*Multi - 1:0] i_v_000;
input [GF*Multi - 1:0] i_v_001;
input [GF*Multi - 1:0] i_v_002;
input [GF*Multi - 1:0] i_v_003;
input [GF*Multi - 1:0] i_v_004;
input [GF*Multi - 1:0] i_v_005;
input [GF*Multi - 1:0] i_v_006;
input [GF*Multi - 1:0] i_v_007;
input [GF*Multi - 1:0] i_v_008;
input [GF*Multi - 1:0] i_v_009;
input [GF*Multi - 1:0] i_v_010;
input [GF*Multi - 1:0] i_v_011;
input [GF*Multi - 1:0] i_v_012;
input [GF*Multi - 1:0] i_v_013;
input [GF*Multi - 1:0] i_v_014;
output o_cs_available;
output [Multi - 1:0] o_cs_cmplt;
output [Multi - 1:0] o_BRAM_read_enable;
output [Multi*8 - 1:0] o_BRAM_read_address;
output [Multi - 1:0] o_c_message_valid;
output [Multi - 1:0] o_c_message_output_cmplt;
output [Multi*8 - 1:0] o_c_message;
wire [Multi - 1:0] w_cs_available;
wire [Multi - 1:0] w_cs_start;
wire [Multi - 1:0] w_cs_pause;
wire [Multi - 1:0] w_c_message_output_start;
genvar i;
generate
for (i = 0; i < Multi; i = i + 1)
begin
d_BCH_CS_top
d_clustered_CS
(
.i_clk (i_clk ),
.i_RESET (i_RESET ),
.i_stop_dec (1'b0 ),
.o_cs_available (w_cs_available[i] ),
.i_exe_cs (i_exe_cs ),
.i_data_fowarding (i_data_fowarding[i] ),
.i_MUX_data_ready (i_MUX_data_ready ),
.i_v_000 (i_v_000[GF * (i+1) - 1 : GF * i] ),
.i_v_001 (i_v_001[GF * (i+1) - 1 : GF * i] ),
.i_v_002 (i_v_002[GF * (i+1) - 1 : GF * i] ),
.i_v_003 (i_v_003[GF * (i+1) - 1 : GF * i] ),
.i_v_004 (i_v_004[GF * (i+1) - 1 : GF * i] ),
.i_v_005 (i_v_005[GF * (i+1) - 1 : GF * i] ),
.i_v_006 (i_v_006[GF * (i+1) - 1 : GF * i] ),
.i_v_007 (i_v_007[GF * (i+1) - 1 : GF * i] ),
.i_v_008 (i_v_008[GF * (i+1) - 1 : GF * i] ),
.i_v_009 (i_v_009[GF * (i+1) - 1 : GF * i] ),
.i_v_010 (i_v_010[GF * (i+1) - 1 : GF * i] ),
.i_v_011 (i_v_011[GF * (i+1) - 1 : GF * i] ),
.i_v_012 (i_v_012[GF * (i+1) - 1 : GF * i] ),
.i_v_013 (i_v_013[GF * (i+1) - 1 : GF * i] ),
.i_v_014 (i_v_014[GF * (i+1) - 1 : GF * i] ),
.o_cs_start ( ),
.o_cs_cmplt (o_cs_cmplt[i] ),
.o_cs_pause ( ),
.o_BRAM_read_enable (o_BRAM_read_enable[i] ),
.o_BRAM_read_address (o_BRAM_read_address[(i+1)*8 - 1:i*8] ),
.i_BRAM_read_data (i_BRAM_read_data[(i+1)*8 - 1:i*8] ),
.o_c_message_valid (o_c_message_valid[i] ),
.o_c_message_output_start ( ),
.o_c_message_output_cmplt (o_c_message_output_cmplt[i] ),
.o_c_message (o_c_message[(i+1)*8 - 1:i*8] )
);
end
endgenerate
assign o_cs_available = w_cs_available[0] ;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); const int inf = 0x3f3f3f3f; const long long oo = 1LL << 60; const int N = 10010; const int E = 200010; class Graph { public: int pnt[E], nxt[E], id[E]; int head[N], nv, ne; void init(const int v) { nv = v; ne = 0; memset(head, 255, sizeof(head)); } void add(const int u, const int v, const int i) { pnt[ne] = v, id[ne] = i, nxt[ne] = head[u], head[u] = ne++; pnt[ne] = u, id[ne] = i, nxt[ne] = head[v], head[v] = ne++; } } ga, gb; int n, rt; int dfn[N], low[N], idx; int stk[N], top; int belong[N], bcnt; bool vis[N]; int cnt[N]; void dfs(const Graph &g, int u, int f) { int i, v, e; dfn[u] = low[u] = idx++; stk[++top] = u; vis[u] = 1; for (i = g.head[u]; ~i; i = g.nxt[i]) { v = g.pnt[i], e = g.id[i]; if (dfn[v] < 0) { dfs(g, v, e); low[u] = min(low[u], low[v]); } else if (e != f && vis[v] && low[u] > dfn[v]) low[u] = dfn[v]; } if (dfn[u] == low[u]) { do { v = stk[top--]; vis[v] = 0; belong[v] = bcnt; } while (v != u); bcnt++; } } void bcc(const Graph &g) { top = bcnt = idx = 0; memset(dfn, 255, sizeof(dfn)); memset(vis, 0, sizeof(vis)); for (int i = 0; i < g.nv; i++) if (dfn[i] < 0) dfs(g, i, -1); } void find(const Graph &g) { rt = -1; int mm = -1; memset(cnt, 0, sizeof(cnt)); for (int i = 0; i < g.nv; i++) cnt[belong[i]]++; for (int i = 0; i < bcnt; i++) if (cnt[i] > mm) { mm = cnt[i]; rt = i; } } void shrink(const Graph &ga, Graph &gb) { int v, cnt = 1; gb.init(bcnt); for (int i = 0; i < ga.nv; i++) for (int j = ga.head[i]; ~j; j = ga.nxt[j]) if (belong[i] != belong[v = ga.pnt[j]]) gb.add(belong[i], belong[v], cnt++); } bool in[N]; int Q[N], dist[N]; void spfa(const Graph &g, int src) { int i, u, v, l, r = 0; memset(dist, 63, sizeof(dist)); memset(in, 0, sizeof(in)); dist[Q[r++] = src] = 0; in[src] = 1; for (l = 0; l != r; l = (l + 1) % N) for (i = g.head[u = Q[l]], in[u] = 0; ~i; i = g.nxt[i]) if (dist[v = g.pnt[i]] > dist[u] + 1) { dist[v] = dist[u] + 1; if (!in[v]) in[Q[r++] = v] = 1, r %= N; } } int main(void) { scanf( %d , &n); ga.init(n); for (int i = 1; i <= n; i++) { int u, v; scanf( %d%d , &u, &v); ga.add(u - 1, v - 1, i); } bcc(ga); find(ga); shrink(ga, gb); spfa(gb, rt); for (int i = 0; i < ga.nv; i++) printf( %d%c , dist[belong[i]], i == ga.nv - 1 ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; const ld eps = 1e-8; template <class U, class V> ostream& operator<<(ostream& out, const pair<U, V>& p) { return out << ( << p.first << , << p.second << ) ; } template <size_t i, class T> ostream& print_tuple_utils(ostream& out, const T& tup) { if constexpr (i == tuple_size<T>::value) return out << ) ; else return print_tuple_utils<i + 1, T>(out << (i ? , : ( ) << get<i>(tup), tup); } template <class... U> ostream& operator<<(ostream& out, const tuple<U...>& tup) { return print_tuple_utils<0, tuple<U...>>(out, tup); } template <class Con, class = decltype(begin(declval<Con>()))> typename enable_if<!is_same<Con, string>::value, ostream&>::type operator<<( ostream& out, const Con& container) { out << { ; for (auto it = container.begin(); it != container.end(); ++it) out << (it == container.begin() ? : , ) << *it; return out << } ; } template <int mod_> struct modint { static constexpr int mod = mod_; int x; modint(int xx = 0) : x(xx) {} modint(ll xx) : x((int)(xx % mod)) {} friend inline modint operator+(modint u, const modint& v) { return u += v; } modint& operator+=(const modint& o) { if ((x += o.x) >= mod) x -= mod; return *this; } friend inline modint operator-(modint u, const modint& v) { return u -= v; } modint& operator-=(const modint& o) { if ((x -= o.x) < 0) x += mod; return *this; } friend inline modint operator*(modint u, const modint& v) { return u *= v; } modint& operator*=(const modint& o) { return *this = modint(1ll * x * o.x); } modint pow(ll exp) const { modint base = *this, ans = 1; for (; exp > 0; exp >>= 1, base *= base) if (exp & 1) ans *= base; return ans; } friend inline modint operator/(modint u, const modint& v) { return u /= v; } modint& operator/=(const modint& o) { return *this *= o.pow(mod - 2); } friend bool operator==(const modint& u, const modint& v) { return u.x == v.x; } friend ostream& operator<<(ostream& out, const modint& u) { return out << u.x; } }; using mint = modint<(int)1e9 + 7>; const int maxn = 696; mint comb[maxn][maxn]; mint fac[maxn]; void precal() { for (int i = (int)(0); i < (int)(maxn); ++i) { comb[i][0] = 1; for (int f = (int)(1); f < (int)(i + 1); ++f) { comb[i][f] = comb[i - 1][f] + comb[i - 1][f - 1]; } } fac[0] = 1; for (int i = (int)(1); i < (int)(maxn); ++i) fac[i] = fac[i - 1] * i; } int reduce_factor(int num) { int ans = 1; for (int i = 2; i * i <= num; ++i) { if (num % i) continue; int cnt = 0; while (num % i == 0) { num /= i; cnt ^= 1; } if (cnt) ans *= i; } if (num > 1) ans *= num; return ans; } mint brute(const vector<int>& a) { auto is_perfect_sqr = [&](ll num) { ll x = (ll)round(sqrt(num)); return x * x == num; }; vector<int> pos(((int)a.size())); for (int i = (int)(0); i < (int)(((int)a.size())); ++i) pos[i] = i; mint ans = 0; do { bool ok = true; for (int i = (int)(0); i < (int)(((int)a.size()) - 1); ++i) { if (!is_perfect_sqr(1ll * a[pos[i]] * a[pos[i + 1]])) continue; ok = false; break; } ans += ok; } while (next_permutation((pos).begin(), (pos).end())); return ans; } mint solve(const vector<int>& a) { map<int, int> cnt; for (auto i : a) { int rd = reduce_factor(i); if (0) cerr << [ i = << (i) << ] << [ rd = << (rd) << ] << endl; cnt[rd]++; } vector<mint> dp = {1}; int cnt_have = 0; for (auto [val, cur_cnt] : cnt) { ; if (0) cerr << [ val = << (val) << ] << [ cur_cnt = << (cur_cnt) << ] << endl; vector<mint> new_dp(((int)a.size()) + 2); auto cur_fac = fac[cur_cnt]; for (int prev_same_pos = (int)(0); prev_same_pos < (int)(((int)dp.size())); ++prev_same_pos) { if (dp[prev_same_pos] == 0) continue; int prev_res_pos = cnt_have + 1 - prev_same_pos; for (int cnt_group = (int)(1); cnt_group < (int)(cur_cnt + 1); ++cnt_group) { ; if (0) cerr << [ cnt_group = << (cnt_group) << ] << endl; int add_same_pos = cur_cnt - cnt_group; for (int choose_same_pos = (int)(0); choose_same_pos < (int)(prev_same_pos + 1); ++choose_same_pos) { int choose_res_pos = cnt_group - choose_same_pos; if (choose_res_pos < 0) break; if (choose_res_pos > prev_res_pos) continue; int new_same_pos = prev_same_pos + add_same_pos - choose_same_pos; mint cur_ans = comb[prev_same_pos][choose_same_pos] * comb[prev_res_pos][choose_res_pos] * comb[cur_cnt - 1][cnt_group - 1] * dp[prev_same_pos]; if (0) cerr << [ choose_same_pos = << (choose_same_pos) << ] << [ new_same_pos = << (new_same_pos) << ] << [ cur_ans = << (cur_ans) << ] << endl; new_dp[new_same_pos] += cur_fac * cur_ans; } } } swap(dp, new_dp); while (dp.size() and dp.back() == 0) dp.pop_back(); cnt_have += cur_cnt; if (0) cerr << [ dp = << (dp) << ] << endl; if (0) cerr << [ cnt_have = << (cnt_have) << ] << endl; } return dp[0]; } mt19937 rng; void check() { while (true) { int n = ((int)(rng() >> 1)) % 5 + 1; vector<int> a(n); for (int i = (int)(0); i < (int)(n); ++i) a[i] = ((int)(rng() >> 1)) % 100 + 1; ofstream inp( main.inp ); inp << n << endl; for (int i = (int)(0); i < (int)(n); ++i) inp << a[i] << ; inp << endl; auto ans = solve(a); auto exp = brute(a); inp << [ ans = << (ans) << ] << [ exp = << (exp) << ] << endl; inp.close(); if (ans == exp) { cout << OK << endl; continue; } cout << FAILED << endl; exit(0); } } int main() { precal(); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> a(n); for (int i = (int)(0); i < (int)(n); ++i) cin >> a[i]; cout << solve(a) << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long t; scanf( %lld , &t); while (t--) { long long a, b, c, d, k; scanf( %lld%lld%lld , &a, &b, &c); scanf( %lld %lld , &d, &k); long long x = (a - 1 + c) / c; long long y = (b + d - 1) / d; if (x + y <= k) { printf( %lld %lld n , k - y, y); } else { printf( -1 n ); } } return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_mc_speed
//----------- Ports Declarations -----------------------------------------------
(
// physical interface
input [2:0] position_i,
output [2:0] position_o,
output [31:0] speed_o,
output new_speed_o,
input [1:0] hall_bemf_i,
input ref_clk,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [31:0] speed_data_s;
wire adc_enable_s;
wire adc_status_s;
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire [31:0] pid_s;
wire [ 2:0] position_s;
wire [ 2:0] bemf_s;
wire [ 2:0] bemf_delayed_s;
wire new_speed_s;
wire [ 2:0] bemf_multiplex_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign bemf_s = position_s ;
assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
assign new_speed_o = new_speed_s;
assign speed_o = speed_data_s;
// processor read interface
always @(negedge up_rstn or posedge up_clk)
begin
if(up_rstn == 0)
begin
up_rdata <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
end else
begin
up_rdata <= up_adc_common_rdata_s;
up_wack <= up_adc_common_wack_s;
up_rack <= up_adc_common_rack_s;
end
end
// HALL sensors debouncers
debouncer
#( .DEBOUNCER_LEN(400))
position_0(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[0]),
.sig_o(position_s[0]));
debouncer
#( .DEBOUNCER_LEN(400))
position_1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[1]),
.sig_o(position_s[1]));
debouncer
#( .DEBOUNCER_LEN(400))
position_2(
.clk_i(ref_clk),
.rst_i(adc_rst),
.sig_i(position_i[2]),
.sig_o(position_s[2]));
delay_30_degrees delay_30_degrees_i1(
.clk_i(ref_clk),
.rst_i(adc_rst),
.offset_i(32'h0),
.position_i(bemf_s),
.position_o(bemf_delayed_s));
speed_detector
#( .AVERAGE_WINDOW(1024),
.LOG_2_AW(10),
.SAMPLE_CLK_DECIM(1000))
speed_detector_inst(
.clk_i(ref_clk),
.rst_i(adc_rst),
.position_i(position_o),
.new_speed_o(new_speed_s),
.current_speed_o(),
.speed_o(speed_data_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd2),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone dual port RAM
*/
module wb_dp_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
// port A
input wire a_clk,
input wire [ADDR_WIDTH-1:0] a_adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] a_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] a_dat_o, // DAT_O() data out
input wire a_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] a_sel_i, // SEL_I() select input
input wire a_stb_i, // STB_I strobe input
output wire a_ack_o, // ACK_O acknowledge output
input wire a_cyc_i, // CYC_I cycle input
// port B
input wire b_clk,
input wire [ADDR_WIDTH-1:0] b_adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] b_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] b_dat_o, // DAT_O() data out
input wire b_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] b_sel_i, // SEL_I() select input
input wire b_stb_i, // STB_I strobe input
output wire b_ack_o, // ACK_O acknowledge output
input wire b_cyc_i // CYC_I cycle input
);
// for interfaces that are more than one word wide, disable address lines
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
// width of data port in words (1, 2, 4, or 8)
parameter WORD_WIDTH = SELECT_WIDTH;
// size of words (8, 16, 32, or 64 bits)
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg [DATA_WIDTH-1:0] a_dat_o_reg = {DATA_WIDTH{1'b0}};
reg a_ack_o_reg = 1'b0;
reg [DATA_WIDTH-1:0] b_dat_o_reg = {DATA_WIDTH{1'b0}};
reg b_ack_o_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] a_adr_i_valid = a_adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
wire [VALID_ADDR_WIDTH-1:0] b_adr_i_valid = b_adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign a_dat_o = a_dat_o_reg;
assign a_ack_o = a_ack_o_reg;
assign b_dat_o = b_dat_o_reg;
assign b_ack_o = b_ack_o_reg;
integer i;
initial begin
for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 1) begin
mem[i] = 0;
end
end
// port A
always @(posedge a_clk) begin
a_ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (a_cyc_i & a_stb_i & ~a_ack_o) begin
if (a_we_i & a_sel_i[i]) begin
mem[a_adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= a_dat_i[WORD_SIZE*i +: WORD_SIZE];
end
a_dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[a_adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
a_ack_o_reg <= 1'b1;
end
end
end
// port B
always @(posedge b_clk) begin
b_ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (b_cyc_i & b_stb_i & ~b_ack_o) begin
if (b_we_i & b_sel_i[i]) begin
mem[b_adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= b_dat_i[WORD_SIZE*i +: WORD_SIZE];
end
b_dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[b_adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
b_ack_o_reg <= 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_LP2_V
`define SKY130_FD_SC_LP__DLXTP_LP2_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp2 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtp_lp2 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_LP2_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
// Depth 2 FIFO Data width 0
module FIFO20(CLK,
RST,
ENQ,
FULL_N,
DEQ,
EMPTY_N,
CLR
);
parameter guarded = 1;
input RST;
input CLK;
input ENQ;
input CLR;
input DEQ;
output FULL_N;
output EMPTY_N;
reg empty_reg;
reg full_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0 ;
full_reg = 1'b1 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (ENQ && !DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg;
end // if (ENQ && !DEQ)
else if (!ENQ && DEQ)
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if (!ENQ && DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO20: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO20: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, const char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); int a, b, c, x, y, z; int spa = 0, spb = 0, spc = 0; int req = 0; cin >> a >> b >> c; cin >> x >> y >> z; if (a > x) spa = a - x; else req += x - a; if (b > y) spb = b - y; else req += y - b; if (c > z) spc = c - z; else req += z - c; if (spa > 0) req = req - spa / 2; if (spb > 0) req = req - spb / 2; if (spc > 0) req = req - spc / 2; if (req <= 0) cout << Yes ; else cout << No ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int f = 1, x = 0; char ch; do { ch = getchar(); if (ch == - ) f = -1; } while (ch < 0 || ch > 9 ); do { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); return f * x; } int r, x, y, px, py; int main() { scanf( %d%d%d%d%d , &r, &x, &y, &px, &py); double dis = sqrt(1.0 * (x - px) * (x - px) + 1.0 * (y - py) * (y - py)); printf( %d n , (int)(ceil(1.0 * dis / (2.0 * r)))); }
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int n, m, p; int a[200004], b[200004]; int sol[200004]; int ns = 0; int main() { scanf( %d%d%d , &n, &m, &p); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= m; ++i) scanf( %d , &b[i]); int num = m; for (int i = 1; i <= p && i + (m - 1) * 1ll * p <= n; ++i) { mp.clear(); num = m; for (int j = 1; j <= m; ++j) mp[b[j]]++; for (int j = i, cc = 0; j <= n; j += p) { ++cc; mp[a[j]]--; if (mp[a[j]] == 0) mp.erase(a[j]); if (mp.empty()) sol[ns++] = j - (m - 1) * p; if (cc == m) { --cc; int x = a[j - cc * p]; mp[x]++; if (mp[x] == 0) mp.erase(x); } } } sort(sol, sol + ns); cout << ns << endl; for (int i = 0; i < ns; ++i) printf( %d , sol[i]); }
|
#include <bits/stdc++.h> const int M = 2000; int T, n, x, ans, f0[M + 10], f1[M + 10]; inline int min(int x, int y) { return x < y ? x : y; } inline int max(int x, int y) { return x > y ? x : y; } void work() { for (int i = 0; i <= M; ++i) f0[i] = i; scanf( %d , &n), ans = 114514; while (n--) { scanf( %d , &x), memset(f1, 0x3f, sizeof f1); for (int i = 0; i <= M; ++i) i - x >= 0 && (f1[i] = min(f1[i], max(f0[i - x], i))), i + x <= M && (f1[i] = min(f1[i], f0[i + x])); memcpy(f0, f1, sizeof f0); } for (int i = 0; i <= M; ++i) ans = min(ans, f0[i]); printf( %d n , ans); } int main() { scanf( %d , &T); while (T--) work(); return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "syntheziedviterbi.v"
//`include "viterbi_decoder.sdf"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_viterbi_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the Viterbi decoder
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire data; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] encoded_input; // Input signal - cx
reg clock; // Input signal - clk
reg reset_sig; // Input signal - reset
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
data,encoded_input,clock,reset_sig);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=10,
#10
reset_sig = 1'd1;
encoded_input = 2'd0;
// @t=20,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=30,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=40,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=50,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=60,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=70,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=80,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=90,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=100,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=110,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=120,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=130,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=140,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=150,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=160,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=170,
#10
reset_sig = 1'd0;
encoded_input = 2'd3;
// @t=180,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=190,
#10
reset_sig = 1'd0;
encoded_input = 2'd0;
// @t=200,
#10
reset_sig = 1'd0;
encoded_input = 2'd1;
// @t=210,
#10
reset_sig = 1'd0;
encoded_input = 2'd2;
// @t=220,
#10
reset_sig = 0;
encoded_input = $random;
// @t=230,
#10
reset_sig = 0;
encoded_input = $random;
// @t=240,
#10
reset_sig = 0;
encoded_input = $random;
// @t=250,s
#10
reset_sig = 0;
encoded_input = $random;
// @t=260,
#10
reset_sig = 0;
encoded_input = $random;
// @t=270,
#10
reset_sig = 0;
encoded_input = $random;
// @t=280,
#10
reset_sig = 0;
encoded_input = $random;
// @t=290,
#10
reset_sig = 0;
encoded_input = $random;
// @t=300,
#10
reset_sig = 0;
encoded_input = $random;
// @t=310,
#10
reset_sig = 0;
encoded_input = $random;
// @t=320,
#10
reset_sig = 0;
encoded_input = $random;
// @t=330,
#10
reset_sig = 0;
encoded_input = $random;
// @t=340,
#10
reset_sig = 0;
encoded_input = $random;
// @t=350,
#10
reset_sig = 0;
encoded_input = $random;
// @t=360,
#10
reset_sig = 0;
encoded_input = $random;
// @t=370,
#10
reset_sig = 0;
encoded_input = $random;
// @t=380,
#10
reset_sig = 0;
encoded_input = $random;
// @t=390,
#10
reset_sig = 0;
encoded_input = $random;
// @t=400,
#10
reset_sig = 1;
encoded_input = $random;
// @t=410,
#10
reset_sig = 0;
encoded_input = $random;
// @t=420,
#10
reset_sig = 0;
encoded_input = $random;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, res, t, k, o; long long a[1000100], b[1000100]; priority_queue<int, vector<int>, greater<int> > q; int main() { scanf( %lld %lld , &n, &k); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i]); } scanf( %lld , &m); for (long long i = 1; i <= n; i++) { scanf( %lld , &b[i]); } res = 0; for (int i = 1; i <= n; i++) { q.push(b[i]); while (k < a[i] && !q.empty()) { k = k + m; res += q.top(); q.pop(); } if (k < a[i]) { res = -1; break; } } printf( %lld n , res); }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > g(7); vector<int> vis(7); int cycles = 0; int nds = 0; bool allvis() { for (int i = 1; i <= 5; i++) if (!vis[i]) return false; return true; } bool dfs(int node, int par, int cnt) { if (vis[node]) { cycles++; nds = cnt; return true; } vis[node] = 1; for (int i = 0; i < g[node].size(); i++) { int child = g[node][i]; if (child != par) { if (dfs(child, node, cnt + 1)) return true; } } return false; } int main() { int m; while (cin >> m) { g.clear(); g.resize(7); vis.clear(); vis.resize(7); cycles = 0; nds = 0; int a, b; for (int i = 0; i < m; i++) { cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } int tmp = 0; for (int i = 1; i <= 5; i++) { if (g[i].size() < 2) tmp++; } dfs(1, 0, 0); if (cycles == 1 && nds == 5 && m == 5) cout << FAIL << endl; else cout << WIN << endl; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Tick Timer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// TT according to OR1K architectural specification. ////
//// ////
//// To Do: ////
//// None ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_tt(
// RISC Internal Interface
clk, rst, du_stall,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
intr
);
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input du_stall; // DU stall
input spr_cs; // SPR CS
input spr_write; // SPR Write
input [31:0] spr_addr; // SPR Address
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output intr; // Interrupt output
`ifdef OR1200_TT_IMPLEMENTED
//
// TT Mode Register bits (or no register)
//
`ifdef OR1200_TT_TTMR
reg [31:0] ttmr; // TTMR bits
`else
wire [31:0] ttmr; // No TTMR register
`endif
//
// TT Count Register bits (or no register)
//
`ifdef OR1200_TT_TTCR
reg [31:0] ttcr; // TTCR bits
`else
wire [31:0] ttcr; // No TTCR register
`endif
//
// Internal wires & regs
//
wire ttmr_sel; // TTMR select
wire ttcr_sel; // TTCR select
wire match; // Asserted when TTMR[TP]
// is equal to TTCR[27:0]
wire restart; // Restart counter when asserted
wire stop; // Stop counter when asserted
reg [31:0] spr_dat_o; // SPR data out
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`OR1200_TTOFS_BITS] == `OR1200_TT_OFS_TTCR)) ? 1'b1 : 1'b0;
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef OR1200_TT_TTMR
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ttmr <= 32'b0;
else if (ttmr_sel && spr_write)
ttmr <= spr_dat_i;
else if (ttmr[`OR1200_TT_TTMR_IE])
ttmr[`OR1200_TT_TTMR_IP] <= ttmr[`OR1200_TT_TTMR_IP] | (match & ttmr[`OR1200_TT_TTMR_IE]);
`else
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
`endif
//
// Write to or increment of TTCR
//
`ifdef OR1200_TT_TTCR
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ttcr <= 32'b0;
else if (restart)
ttcr <= 32'b0;
else if (ttcr_sel && spr_write)
ttcr <= spr_dat_i;
else if (!stop)
ttcr <= ttcr + 32'd1;
`else
assign ttcr = 32'b0;
`endif
//
// Read TT registers
//
always @(spr_addr or ttmr or ttcr)
case (spr_addr[`OR1200_TTOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_TT_READREGS
`OR1200_TT_OFS_TTMR: spr_dat_o = ttmr;
`endif
default: spr_dat_o = ttcr;
endcase
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`OR1200_TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
//
// Restart when match and TTMR[M]==0x1
//
assign restart = match && (ttmr[`OR1200_TT_TTMR_M] == 2'b01);
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0 or when RISC is stalled by debug unit
//
assign stop = match & (ttmr[`OR1200_TT_TTMR_M] == 2'b10) | (ttmr[`OR1200_TT_TTMR_M] == 2'b00) | du_stall;
//
// Generate an interrupt request
//
assign intr = ttmr[`OR1200_TT_TTMR_IP];
`else
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign intr = 1'b0;
//
// Read TT registers
//
`ifdef OR1200_TT_READREGS
assign spr_dat_o = 32'b0;
`endif
`endif
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 07/19/06 - Add else to handle x case for o_out (CR 234718).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS (O, I, IB);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
localparam MODULE_NAME = "IBUFDS";
output O;
input I, IB;
wire i_in, ib_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
assign O = o_out;
assign i_in = I;
assign ib_in = IB;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
#1 $finish;
end
endcase
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE);
#1 $finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE);
#1 $finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> const int mod = 1e9 + 7; const int MAXN = 1e5 + 5, MAXSIZ = 3; template <typename _T> void read(_T &x) { x = 0; char s = getchar(); int f = 1; while (s < 0 || 9 < s) { f = 1; if (s == - ) f = -1; s = getchar(); } while ( 0 <= s && s <= 9 ) { x = (x << 3) + (x << 1) + s - 0 , s = getchar(); } x *= f; } template <typename _T> void write(_T x) { if (x < 0) { putchar( - ), x = -x; } if (9 < x) { write(x / 10); } putchar(x % 10 + 0 ); } struct matrix { int mat[MAXSIZ][MAXSIZ], n, m; matrix() { n = m = 0, memset(mat, 0, sizeof mat); } matrix(const int N, const int M) { n = N, m = M, memset(mat, 0, sizeof mat); } int *operator[](const int indx) { return mat[indx]; } matrix operator*(matrix other) const { matrix ret = matrix(n, other.m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (mat[i][j]) for (int k = 1; k <= ret.m; k++) { ret[i][k] += 1ll * mat[i][j] * other[j][k] % mod; if (ret[i][k] > mod) ret[i][k] -= mod; } return ret; } bool operator==(matrix other) const { if (n ^ other.n || m ^ other.m) return false; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (mat[i][j] ^ other[i][j]) return false; return true; } bool operator!=(matrix other) const { return !(*this == other); } void operator*=(matrix other) { *this = *this * other; } }; struct vector { int vec[MAXSIZ], n; vector() { n = 0, memset(vec, 0, sizeof vec); } vector(const int N) { n = N, memset(vec, 0, sizeof vec); } int &operator[](const int indx) { return vec[indx]; } vector operator*(matrix other) const { vector ret = vector(n); for (int i = 1; i <= n; i++) for (int j = 1; j <= ret.n; j++) { ret[i] += 1ll * vec[j] * other[j][i] % mod; if (ret[i] > mod) ret[i] -= mod; } return ret; } vector operator+(vector other) const { vector ret = *this; for (int i = 1; i <= n; i++) { ret[i] += other[i]; if (ret[i] > mod) ret[i] -= mod; } return ret; } void operator*=(matrix other) { *this = *this * other; } void operator+=(vector other) { *this = *this + other; } }; struct segmentTreeNode { vector s; matrix tag; } segTree[MAXN << 2]; matrix I, B; vector A; int a[MAXN]; int N, M; void upt(const int x) { (segTree[x].s) = (segTree[x << 1].s) + (segTree[x << 1 | 1].s); } void prod(const int x, const matrix v) { (segTree[x].s) *= v, (segTree[x].tag) *= v; } void normalize(const int x) { if ((segTree[x].tag) != I) prod(x << 1, (segTree[x].tag)), prod(x << 1 | 1, (segTree[x].tag)), (segTree[x].tag) = I; } void init() { I = matrix(2, 2); for (int i = 1; i <= 2; i++) I[i][i] = 1; B = matrix(2, 2); B[1][1] = B[2][1] = B[1][2] = 1; A = vector(2); A[1] = 1; } matrix qkpow(matrix base, int indx) { if (indx < 0) return I; matrix ret = I; while (indx) { if (indx & 1) ret *= base; base *= base, indx >>= 1; } return ret; } void build(const int u, const int l, const int r) { if (l > r) return; (segTree[u].tag) = I; int mid = l + r >> 1; if (l == r) { (segTree[u].s) = A * qkpow(B, a[l] - 1); return; } build(u << 1, l, mid), build(u << 1 | 1, mid + 1, r); upt(u); } void update(const int x, const int l, const int r, const int segL, const int segR, const matrix v) { int mid = l + r >> 1; if (segL <= l && r <= segR) { prod(x, v); return; } if (l == r) return; normalize(x); if (segL <= mid) update(x << 1, l, mid, segL, segR, v); if (segR > mid) update(x << 1 | 1, mid + 1, r, segL, segR, v); upt(x); } int query(const int x, const int l, const int r, const int segL, const int segR) { int mid = l + r >> 1, ret = 0; if (segL <= l && r <= segR) return (segTree[x].s)[1]; if (l == r) return 0; normalize(x); if (segL <= mid) (ret += query(x << 1, l, mid, segL, segR)) %= mod; if (segR > mid) (ret += query(x << 1 | 1, mid + 1, r, segL, segR)) %= mod; return ret; } int main() { matrix tmp; int opt, optL, optR, optV; init(); read(N), read(M); for (int i = 1; i <= N; i++) read(a[i]); build(1, 1, N); while (M--) { read(opt), read(optL), read(optR); if (opt == 1) { read(optV); tmp = qkpow(B, optV); update(1, 1, N, optL, optR, tmp); } else write(query(1, 1, N, optL, optR)), putchar( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mx = 2e6 + 10; int n, m; bool vis[mx]; int sta[mx], siz, is; int dfn[mx], id[mx]; int be[mx], ty; vector<int> g[mx]; void tarjan(int u) { dfn[u] = id[u] = ++is; sta[++siz] = u; vis[u] = 1; for (int v : g[u]) { if (!dfn[v]) { tarjan(v); id[u] = min(id[u], id[v]); } else if (vis[v]) id[u] = min(id[u], dfn[v]); } if (id[u] == dfn[u]) { ty++; while (sta[siz] != u) { be[sta[siz]] = ty; vis[sta[siz]] = 0; siz--; } be[u] = ty, vis[u] = 0, siz--; } } int cnt_one() { int cnt = 0; for (int i = 1; i <= n; i++) if (be[i] == 1) cnt++; return cnt; } int main() { int t; scanf( %d , &t); while (t--) { scanf( %d%d , &n, &m); for (int i = 1; i <= 2 * n; i++) g[i].clear(); ty = is = siz = 0; for (int i = 1; i <= 2 * n; i++) dfn[i] = vis[i] = 0; for (int i = 0, u, v; i < m; i++) { scanf( %d%d , &u, &v); if (u == v) g[v + n].push_back(u); else g[u].push_back(v + n); } if (n == 1) { puts( No ); continue; } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i); int cnt = cnt_one(); if (cnt == n) puts( No ); else { puts( Yes ); printf( %d %d n , cnt, n - cnt); for (int i = 1; i <= n; i++) if (be[i] == 1) printf( %d , i); puts( ); for (int i = 1; i <= n; i++) if (be[i] != 1) printf( %d , i); puts( ); } } return 0; }
|
module Vga_control(
// Host Side
input [3:0] iRed,
input [3:0] iGreen,
input [3:0] iBlue,
output [9:0] oCurrent_X, // Max horizontal pixels: 1023.
output [9:0] oCurrent_Y, // Max vertical pixels: 1023.
output [21:0] oAddress,
output oRequest,
output reg oTopOfScreen, // 1 when at the very top of (blank) screen.
// VGA Side
output [3:0] oVGA_R,
output [3:0] oVGA_G,
output [3:0] oVGA_B,
output reg oVGA_HS, // Active low.
output reg oVGA_VS, // Active low.
output oVGA_BLANK, // Active low.
output oVGA_CLOCK, // Inverse of iCLK.
// Control Signal
input iCLK,
input iRST_N
);
// LK: There are two internal registers, H_Cont and V_Cont. They are 0-based. The
// H_Cont value has these ranges:
//
// H_Cont oVGA_HS
// [0, H_FRONT) 1 (front porch)
// [H_FRONT, H_FRONT + H_SYNC) 0 (sync pulse)
// [H_FRONT + H_SYNC, H_BLANK) 1 (back porch, V_Cont is incremented)
// [H_BLANK, H_TOTAL) 1 (pixels are visible)
//
// V_Cont value has these ranges:
//
// V_Cont oVGA_VS
// [0, V_FRONT) 1 (front porch)
// [V_FRONT, V_FRONT + V_SYNC) 0 (sync pulse)
// [V_FRONT + V_SYNC, V_BLANK) 1 (back porch)
// [V_BLANK, V_TOTAL) 1 (pixels are visible)
//
// Note that V_Cont is incremented on the positive edge of oVGA_HS, which means
// that its values are offset from the normal 0-639 range of H_Cont.
//
// oTopOfScreen is the first pixel of the second row, since that's where
// both are zero.
//
// The VGA clock is 25.175 MHz. With 800x525 pixels (640x480 visible),
// that's 59.94 FPS.
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 10;
parameter V_SYNC = 2;
parameter V_BACK = 33;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign oVGA_BLANK = ~(H_Cont<H_BLANK || V_Cont<V_BLANK);
assign oVGA_CLOCK = ~iCLK;
//assign oVGA_R = oRequest ? iRed : 4'b0 ;
//assign oVGA_G = oRequest ? iGreen : 4'b0 ;
//assign oVGA_B = oRequest ? iBlue : 4'b0 ;
assign oVGA_R = oRequest ? iRed : 4'b0 ;
assign oVGA_G = oRequest ? iGreen : 4'b0 ;
assign oVGA_B = oRequest ? iBlue : 4'b0 ;
assign oAddress = oCurrent_Y*H_ACT + oCurrent_X;
assign oRequest = H_Cont >= H_BLANK && V_Cont >= V_BLANK;
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0;
wire oTopOfScreenNext = H_Cont == 0 && V_Cont == 0;
always @(posedge iCLK)
begin
oTopOfScreen <= oTopOfScreenNext;
end
// Horizontal Generator: Refer to the pixel clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if(H_Cont<H_TOTAL-1)
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
// Horizontal Sync
if(H_Cont==H_FRONT-1) // Front porch end
oVGA_HS <= 1'b0;
if(H_Cont==H_FRONT+H_SYNC-1) // Sync pulse end
oVGA_HS <= 1'b1;
end
end
// Vertical Generator: Refer to the horizontal sync
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end else if (H_Cont == 0) begin
if(V_Cont<V_TOTAL-1)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
// Vertical Sync
if(V_Cont==V_FRONT-1) // Front porch end
oVGA_VS <= 1'b0;
if(V_Cont==V_FRONT+V_SYNC-1) // Sync pulse end
oVGA_VS <= 1'b1;
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module SyncWire( DIN, DOUT );
parameter width = 1;
input [width - 1 : 0] DIN;
output [width - 1 : 0] DOUT;
assign DOUT = DIN ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__TAP_PP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_PP_SYMBOL_V
|
module BlockFall(clock0,clock180,reset,vga_hsync,vga_vsync,vga_r,vga_g,vga_b);
input wire clock0;
input wire clock180;
input wire reset;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [7:0] alu_result;
wire swc_ready;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0,swc_ready}),
.ireg_2(8'h00),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
BlockFallRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
BlockFallRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
Alu
alu (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result));
Swc
swc (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.ready(swc_ready));
VGA1
vga (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // Auto2
|
#include <bits/stdc++.h> using namespace std; long long ans[100010]; long long ans2[100010]; int main() { int n, p; int l, r; while (cin >> n >> p) { for (int i = 0; i < n; i++) { scanf( %d%d , &l, &r); ans[i] = r / p - l / p; ans2[i] = r - l + 1; if (l % p == 0) ans[i]++; } ans[n] = ans[0]; ans2[n] = ans2[0]; double anss = 0; for (int i = 0; i < n; i++) anss += ((ans[i] * (ans2[i + 1] - ans[i + 1]) + (ans2[i] - ans[i]) * ans[i + 1] + ans[i] * ans[i + 1]) * 1.0) / (ans2[i] * ans2[i + 1] * 1.0) * 2000; printf( %.10llf , anss); } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostSlaveAvalonWrap.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper. Enable connection to Altera Avalon bus
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbHostSlaveAvalonWrap(
clk,
reset,
address,
writedata,
readdata,
write,
read,
waitrequest,
chipselect,
irq,
usbClk,
USBWireVPI,
USBWireVMI,
USBWireDataInTick,
USBWireVPO,
USBWireVMO,
USBWireDataOutTick,
USBWireOutEn_n,
USBFullSpeed
);
input clk;
input reset;
input [7:0] address;
input [7:0] writedata;
output [7:0] readdata;
input write;
input read;
output waitrequest;
input chipselect;
output irq;
input usbClk;
input USBWireVPI /* synthesis useioff=1 */;
input USBWireVMI /* synthesis useioff=1 */;
output USBWireVPO /* synthesis useioff=1 */;
output USBWireVMO /* synthesis useioff=1 */;
output USBWireDataOutTick /* synthesis useioff=1 */;
output USBWireDataInTick /* synthesis useioff=1 */;
output USBWireOutEn_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
wire clk;
wire reset;
wire [7:0] address;
wire [7:0] writedata;
wire [7:0] readdata;
wire write;
wire read;
wire waitrequest;
wire chipselect;
wire irq;
wire usbClk;
wire USBWireVPI;
wire USBWireVMI;
wire USBWireVPO;
wire USBWireVMO;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBWireOutEn_n;
wire USBFullSpeed;
//internal wiring
wire strobe_i;
wire ack_o;
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = hostSOFSentIntOut | hostConnEventIntOut |
hostResumeIntOut | hostTransDoneIntOut |
slaveSOFRxedIntOut | slaveResetEventIntOut |
slaveResumeIntOut | slaveTransDoneIntOut |
slaveNAKSentIntOut;
assign strobe_i = chipselect & ( read | write);
assign waitrequest = ~ack_o;
assign USBWireOutEn_n = ~USBWireCtrlOut;
assign USBWireDataIn = {USBWireVPI, USBWireVMI};
assign {USBWireVPO, USBWireVMO} = USBWireDataOut;
//Parameters declaration:
defparam usbHostSlaveInst.HOST_FIFO_DEPTH = 64;
parameter HOST_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.HOST_FIFO_ADDR_WIDTH = 6;
parameter HOST_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP0_FIFO_DEPTH = 64;
parameter EP0_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP0_FIFO_ADDR_WIDTH = 6;
parameter EP0_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP1_FIFO_DEPTH = 64;
parameter EP1_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP1_FIFO_ADDR_WIDTH = 6;
parameter EP1_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP2_FIFO_DEPTH = 64;
parameter EP2_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP2_FIFO_ADDR_WIDTH = 6;
parameter EP2_FIFO_ADDR_WIDTH = 6;
defparam usbHostSlaveInst.EP3_FIFO_DEPTH = 64;
parameter EP3_FIFO_DEPTH = 64;
defparam usbHostSlaveInst.EP3_FIFO_ADDR_WIDTH = 6;
parameter EP3_FIFO_ADDR_WIDTH = 6;
usbHostSlave usbHostSlaveInst (
.clk_i(clk),
.rst_i(reset),
.address_i(address),
.data_i(writedata),
.data_o(readdata),
.we_i(write),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.hostSOFSentIntOut(hostSOFSentIntOut),
.hostConnEventIntOut(hostConnEventIntOut),
.hostResumeIntOut(hostResumeIntOut),
.hostTransDoneIntOut(hostTransDoneIntOut),
.slaveSOFRxedIntOut(slaveSOFRxedIntOut),
.slaveResetEventIntOut(slaveResetEventIntOut),
.slaveResumeIntOut(slaveResumeIntOut),
.slaveTransDoneIntOut(slaveTransDoneIntOut),
.slaveNAKSentIntOut(slaveNAKSentIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Q> void inin(Q &x) { x = 0; int f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = 1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); x = f ? -x : x; } int n, a[100010], b[100010]; long long sum[100010], ans[100010], tot[100010]; int erfen(int x, int l, int r) { int ll = l, rr = r, mid; while (ll < rr) { mid = (ll + rr) >> 1; if (sum[mid] - sum[l - 1] < x) ll = mid + 1; else rr = mid; } if (ll == n && sum[n] - sum[l - 1] < x) return n + 1; return ll; } int main() { inin(n); for (int i = (1); i <= (n); i++) inin(a[i]); for (int i = (1); i <= (n); i++) inin(b[i]), sum[i] = sum[i - 1] + b[i]; for (int i = (1); i <= (n); i++) { int x = erfen(a[i], i, n); tot[x]--; ans[x] += a[i] - (sum[x - 1] - sum[i - 1]); tot[i] += tot[i - 1] + 1; ans[i] += 1LL * b[i] * tot[i]; } for (int i = (1); i <= (n); i++) printf( %lld , ans[i]); return 0; }
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_INTERMDISABLE_INT.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_INTERMDISABLE_INT (O, I, IB, IBUFDISABLE, INTERMDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_INTERMDISABLE_INT";
output O;
input I;
input IB;
input IBUFDISABLE;
input INTERMDISABLE;
wire i_in, ib_in, ibufdisable_in, intermdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
assign intermdisable_in = INTERMDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int mat[105][105]; int nodes[105]; int n, m; int cycles = 0; void cycle_det(int cur, int parent); int main() { cin >> n >> m; memset(mat, 0, sizeof mat); memset(nodes, 0, sizeof nodes); for (int i = 0; i < m; i++) { int _1, _2; cin >> _1 >> _2; mat[_1 - 1][_2 - 1] = 1; mat[_2 - 1][_1 - 1] = 1; } cycle_det(0, -1); int count = 0; for (int i = 0; i < n; i++) if (nodes[i] == 1) count++; if (cycles != 2 || count != n) cout << NO n ; else cout << FHTAGN! n ; } void cycle_det(int cur, int parent) { if (cycles > 2) return; nodes[cur] = 1; for (int i = 0; i < n; i++) { int tmp = 0; if (mat[cur][i] == 1 && !nodes[i]) { nodes[i] = 1; cycle_det(i, cur); } else if (mat[cur][i] == 1 && i != parent && nodes[i]) { cycles++; } } }
|
#include <bits/stdc++.h> using namespace std; struct SegmentTree { struct Node { Node *lch, *rch; long long sum; Node() { lch = rch = nullptr; sum = 0; } void up() { sum = 0; if (lch != nullptr) sum += lch->sum; if (rch != nullptr) sum += rch->sum; } } * root; SegmentTree() { root = nullptr; } void modify(int l, int r, int pos, int v, Node*& node) { if (node == nullptr) node = new Node(); if (l == r) { node->sum += v; } else { int mid = (l + r) >> 1; if (pos <= mid) modify(l, mid, pos, v, node->lch); else modify(mid + 1, r, pos, v, node->rch); node->up(); } } long long query(int l, int r, int ql, int qr, Node* node) { if (node == nullptr) return 0; if (l == ql && r == qr) return node->sum; int mid = (l + r) >> 1; if (qr <= mid) return query(l, mid, ql, qr, node->lch); else if (ql > mid) return query(mid + 1, r, ql, qr, node->rch); else return query(l, mid, ql, mid, node->lch) + query(mid + 1, r, mid + 1, qr, node->rch); } } bit[100010]; int n; inline int lowbit(int x) { return x & -x; } inline void modify(int x, int y, int v) { for (int i = x; i <= n; i += lowbit(i)) bit[i].modify(0, n, y, v, bit[i].root); } inline long long query(int pos, int ql, int qr) { long long res = 0; for (int i = pos; i > 0; i -= lowbit(i)) res += bit[i].query(0, n, ql, qr, bit[i].root); return res; } inline long long Query(int xl, int xr, int yl, int yr) { return query(xr, yl, yr) - query(xl - 1, yl, yr); } set<int> pos[100010]; int a[100010]; int main() { int m, op, p, x, l, r; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) pos[i].insert(0); for (int i = 1; i <= n; i++) { scanf( %d , a + i); auto it = pos[a[i]].end(); it--; modify(i, *it, i - *it); pos[a[i]].insert(i); } while (m--) { scanf( %d , &op); if (op == 1) { scanf( %d%d , &p, &x); auto it = pos[a[p]].find(p), it2 = it; it2--; it++; modify(p, *it2, -(p - *it2)); if (it != pos[a[p]].end()) { modify(*it, p, -(*it - p)); modify(*it, *it2, *it - *it2); } pos[a[p]].erase(p); a[p] = x; pos[x].insert(p); it = pos[x].find(p), it2 = it; it2--; it++; modify(p, *it2, p - *it2); if (it != pos[x].end()) { modify(*it, *it2, -(*it - *it2)); modify(*it, p, *it - p); } } else { scanf( %d%d , &l, &r); printf( %lld n , Query(l, r, l, r)); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int m; cin >> m; int i; map<int, int> ipattern; for (i = 1; i <= n; i++) { int x; cin >> x; ipattern[i] = x; } int max = 0; for (i = 1; i <= n; i++) { if (ipattern[i] > max) { max = ipattern[i]; } } int r = max % m; int an = max / m; if (r == 0) an = an - 1; else { an = an; } int j; if (an == 0) { cout << n; } else { for (j = 1; j <= an; j++) { for (i = 1; i <= n; i++) { if ((ipattern[i] - m) <= 0) { ipattern.erase(i); } else { ipattern[i] = ipattern[i] - m; } } } int y; for (auto itr = ipattern.begin(); itr != ipattern.end(); ++itr) { y = itr->first; } cout << y << endl; } }
|
#include <bits/stdc++.h> using namespace std; inline int Max(int a, int b) { return (((b - a) >> (32 - 1)) & (a ^ b)) ^ b; } inline int Min(int a, int b) { return (((b - a) >> (32 - 1)) & (a ^ b)) ^ a; } string s; long long num[2][1000005], len[2][1000005]; long long rnum[2][1000005]; int main() { cin.tie(0); ios::sync_with_stdio(false); int n; while (cin >> n) { cin >> s; memset(num, 0, sizeof(num)); memset(rnum, 0, sizeof(rnum)); memset(len, 0, sizeof(len)); for (int i = (1); i <= (n); i++) { for (int j = (0); j <= (1); j++) { num[j][i] = num[j][i - 1]; len[j][i] = len[j][i - 1]; } if (s[i - 1] == U ) { num[0][i]++; len[0][i] += i; rnum[0][num[0][i]] = i; } else { num[1][i]++; len[1][i] += i; rnum[1][num[1][i]] = i; } } for (int i = (1); i <= (n); i++) { long long ret = 0; int a = num[1][n] - num[1][i]; int b = num[0][i - 1]; if (s[i - 1] == U ) { if (a <= b) { int ps = rnum[0][b - a]; ret = 2 * ((len[1][n] - len[1][i]) - (len[0][i - 1] - len[0][ps])) + n - i + 1; } else { int ps = rnum[1][num[1][i] + b + 1]; ret = 2 * ((len[1][ps] - len[1][i]) - len[0][i - 1]) - i; } } else { if (a < b) { int ps = rnum[0][b - a - 1]; ret = 2 * ((len[1][n] - len[1][i]) - (len[0][i - 1] - len[0][ps])) + n + i + 1; } else { int ps = rnum[1][num[1][i] + b]; ret = 2 * ((len[1][ps] - len[1][i]) - len[0][i - 1]) + i; } } cout << ret << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[500], c, i, n, big; int main() { while (~scanf( %d %d , &n, &c)) { for (i = 0; i < n; i++) { scanf( %d , &a[i]); } big = 0; for (i = 0; i < n - 1; i++) { if (a[i] - a[i + 1] - c > big) big = a[i] - a[i + 1] - c; } printf( %d n , big); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_V
|
module I2C_HDMI_Config ( // Host Side
iCLK,
iRST_N,
// I2C Side
I2C_SCLK,
I2C_SDAT,
HDMI_TX_INT,
READY
);
// Host Side
input iCLK;
input iRST_N;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
input HDMI_TX_INT;
output READY ;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
reg READY ;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 31;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
READY<=0;
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
READY<=0;
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'h72,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
else
begin
READY<=1;
if(!HDMI_TX_INT)
begin
LUT_INDEX <= 0;
end
else
LUT_INDEX <= LUT_INDEX;
end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Video Config Data
0 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation
1 : LUT_DATA <= 16'h0100; //Set 'N' value at 6144
2 : LUT_DATA <= 16'h0218; //Set 'N' value at 6144
3 : LUT_DATA <= 16'h0300; //Set 'N' value at 6144
4 : LUT_DATA <= 16'h1470; // Set Ch count in the channel status to 8.
5 : LUT_DATA <= 16'h1520; //Input 444 (RGB or YCrCb) with Separate Syncs, 48kHz fs
6 : LUT_DATA <= 16'h1630; //Output format 444, 24-bit input
7 : LUT_DATA <= 16'h1846; //Disable CSC
8 : LUT_DATA <= 16'h4080; //General control packet enable
9 : LUT_DATA <= 16'h4110; //Power down control
10 : LUT_DATA <= 16'h49A8; //Set dither mode - 12-to-10 bit
11 : LUT_DATA <= 16'h5510; //Set RGB in AVI infoframe
12 : LUT_DATA <= 16'h5608; //Set active format aspect
13 : LUT_DATA <= 16'h96F6; //Set interrup
14 : LUT_DATA <= 16'h7307; //Info frame Ch count to 8
15 : LUT_DATA <= 16'h761f; //Set speaker allocation for 8 channels
16 : LUT_DATA <= 16'h9803; //Must be set to 0x03 for proper operation
17 : LUT_DATA <= 16'h9902; //Must be set to Default Value
18 : LUT_DATA <= 16'h9ae0; //Must be set to 0b1110000
19 : LUT_DATA <= 16'h9c30; //PLL filter R1 value
20 : LUT_DATA <= 16'h9d61; //Set clock divide
21 : LUT_DATA <= 16'ha2a4; //Must be set to 0xA4 for proper operation
22 : LUT_DATA <= 16'ha3a4; //Must be set to 0xA4 for proper operation
23 : LUT_DATA <= 16'ha504; //Must be set to Default Value
24 : LUT_DATA <= 16'hab40; //Must be set to Default Value
25 : LUT_DATA <= 16'haf16; //Select HDMI mode
26 : LUT_DATA <= 16'hba60; //No clock delay
27 : LUT_DATA <= 16'hd1ff; //Must be set to Default Value
28 : LUT_DATA <= 16'hde10; //Must be set to Default for proper operation
29 : LUT_DATA <= 16'he460; //Must be set to Default Value
30 : LUT_DATA <= 16'hfa7d; //Nbr of times to look for good phase
default: LUT_DATA <= 16'h9803;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
/*!
* \file ram_subcell.v
* \brief RAM cell instance, uses feedback signal to perform read-modify-write operations
* \author Luca Maggiani
* \version 1.0
* \date Jan 2014
* \pre It needs ram_module instances
* \see ram_subcell
* \see ram_module
*/
module ram_subcell(
clk,
reset_n,
data_a,
data_b,
data_valid_in,
address_a_valid,
memory_clear,
enable_wire,
q_b,
q_a,
address_a,
address_b
);
parameter HISTOGRAM_WIDTH = 16;
parameter HISTMEM_WORD = 1024;
localparam HISTMEM_ADDR_WIDTH = $clog2(HISTMEM_WORD);
localparam READ_STATE = 2'b01;
localparam WRITE_STATE = 2'b10;
input clk, reset_n;
input [(HISTOGRAM_WIDTH-1):0] data_a, data_b;
input data_valid_in, memory_clear;
input address_a_valid;
input enable_wire;
output [(HISTOGRAM_WIDTH-1):0] q_a, q_b;
input [(HISTMEM_ADDR_WIDTH-1):0] address_a;
input [(HISTMEM_ADDR_WIDTH-1):0] address_b;
reg memory_clear_reg;
wire wren_a;
wire wren_b;
wire [(HISTOGRAM_WIDTH-1):0] ram_data_in;
reg [(HISTMEM_ADDR_WIDTH-1):0] address_a_reg;
reg [1:0] state, state_new;
/* ######################
#
# FSM subcell control
#
######################
*/
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
address_a_reg <= {HISTOGRAM_WIDTH{1'b0}};
else
if (address_a_valid)
address_a_reg <= address_a;
else
address_a_reg <= address_a_reg;
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
state <= READ_STATE;
else
state <= state_new;
always@(*)
case(state)
READ_STATE:
begin
if (data_valid_in)
state_new = WRITE_STATE;
else
state_new = READ_STATE;
end
WRITE_STATE:
begin
state_new = READ_STATE;
end
default:
state_new = READ_STATE;
endcase
altsyncram #(
.address_reg_b("CLOCK0"),
.clock_enable_input_a("NORMAL"),
.clock_enable_input_b("NORMAL"),
.clock_enable_output_a("NORMAL"),
.clock_enable_output_b("NORMAL"),
.indata_reg_b("CLOCK0"),
.intended_device_family("Cyclone IV E"),
.lpm_type("altsyncram"),
.numwords_a(HISTMEM_WORD),
.numwords_b(HISTMEM_WORD),
.operation_mode("BIDIR_DUAL_PORT"),
.outdata_aclr_a("NONE"),
.outdata_aclr_b("NONE"),
.outdata_reg_b("CLOCK0"),
.power_up_uninitialized("FALSE"),
.ram_block_type("M9K"),
.read_during_write_mode_mixed_ports("OLD_DATA"),
.widthad_a(HISTMEM_ADDR_WIDTH),
.widthad_b(HISTMEM_ADDR_WIDTH),
.width_a(HISTOGRAM_WIDTH),
.width_b(HISTOGRAM_WIDTH),
.width_byteena_a(1),
.width_byteena_b(1),
.wrcontrol_wraddress_reg_b("CLOCK0")
)
ram_module_inst (
.clock0 (clk),
.wren_a (wren_a),
.address_b (address_b),
.clocken0 (enable_wire),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a_reg),
.data_a (ram_data_in),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1)
);
assign wren_a = (state == WRITE_STATE)? 1'b1: 1'b0;
assign wren_b = memory_clear;
assign ram_data_in = data_a + q_a;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (auto i : v) os << i << ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& v) { for (auto i : v) os << i << ; return os; } const int N = 41; const int dx[] = {1, 1, 2, 2, -1, -1, -2, -2}; const int dy[] = {2, -2, 1, -1, 2, -2, 1, -1}; using pii = pair<int, int>; int db[N][N]; int dw[N][N]; int ex[N][N]; bool vis[N][N]; int n, m; void init() { pii S = {n / 2, m / 2}; queue<pii> q; q.push(S); memset(dw, 0x3f, sizeof(dw)); dw[n / 2][m / 2] = 0; while (!q.empty()) { pii u = q.front(); q.pop(); if (vis[u.first][u.second]) continue; vis[u.first][u.second] = true; for (int i = 0; i < 8; ++i) { pii v; v.first = u.first + dx[i]; v.second = u.second + dy[i]; if (v.first > 0 && v.first <= n && v.second > 0 && v.second <= m) { q.push(v); dw[v.first][v.second] = min(dw[u.first][u.second] + 1, dw[v.first][v.second]); } } } S = {n / 2 + 1, m / 2}; memset(db, 0x3f, sizeof(db)); memset(vis, 0, sizeof(vis)); db[n / 2 + 1][m / 2] = 0; q.push(S); while (!q.empty()) { pii u = q.front(); q.pop(); if (vis[u.first][u.second]) continue; vis[u.first][u.second] = true; for (int i = 0; i < 8; ++i) { pii v; v.first = u.first + dx[i]; v.second = u.second + dy[i]; if (v.first > 0 && v.first <= n && v.second > 0 && v.second <= m) { q.push(v); db[v.first][v.second] = min(db[u.first][u.second] + 1, db[v.first][v.second]); } } } S = {n / 2, m / 2}; memset(ex, 0x3f, sizeof(ex)); for (int i = 0; i < 8; ++i) { pii v; v = {S.first + dx[i], S.second + dy[i]}; q.push(v); ex[v.first][v.second] = 0; } memset(vis, 0, sizeof(vis)); while (!q.empty()) { pii u = q.front(); q.pop(); if (vis[u.first][u.second]) continue; vis[u.first][u.second] = true; for (int i = 0; i < 8; ++i) { pii v; v.first = u.first + dx[i]; v.second = u.second + dy[i]; if (v.first > 0 && v.first <= n && v.second > 0 && v.second <= m) { q.push(v); ex[v.first][v.second] = min(ex[u.first][u.second] + 1, ex[v.first][v.second]); } } } ex[S.first][S.second] = -1; } bool inside(pii x) { return x.first >= 1 && x.second >= 1 && x.first <= n && x.second <= m; } int main() { scanf( %d%d , &n, &m); init(); pii w, b; scanf( %d%d%d%d , &w.first, &w.second, &b.first, &b.second); pii TW = {n / 2, m / 2}; pii TB = {n / 2 + 1, m / 2}; bool atk, reach; atk = true; reach = false; for (int i = 0; i < 8; ++i) { pii v; v = {w.first + dx[i], w.second + dy[i]}; if (!inside(v)) continue; bool flag = false; for (int j = 0; j < 8; ++j) { pii w; w = {b.first + dx[j], b.second + dy[j]}; if (w == v) flag = true; } if (!flag) atk = false; if (v == TW) { if (flag) atk = true; reach = true; break; } } if (reach && !atk) { printf( WHITE n ); printf( %d %d n , TW.first, TW.second); fflush(stdout); return 0; } int BB = db[b.first][b.second]; int WW = dw[w.first][w.second]; int BW = dw[b.first][b.second]; int WB = db[w.first][w.second]; if (WW + 1 <= BW && WW <= BB) { printf( WHITE n ); fflush(stdout); while (w != TW) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {w.first + dx[i], w.second + dy[i]}; if (!inside(tmp)) continue; if (dw[tmp.first][tmp.second] < dw[w.first][w.second]) { w = tmp; printf( %d %d n , w.first, w.second); fflush(stdout); if (w == b) return 0; if (w != TW) scanf( %d%d , &b.first, &b.second); break; } } } return 0; } if (BB + 2 <= WB && BB + 1 <= WW) { printf( BLACK n ); fflush(stdout); while (b != TB) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {b.first + dx[i], b.second + dy[i]}; if (!inside(tmp)) continue; if (db[tmp.first][tmp.second] < db[b.first][b.second]) { b = tmp; printf( %d %d n , tmp.first, tmp.second); fflush(stdout); if (b == w) return 0; if (b != TB) scanf( %d%d , &w.first, &w.second); break; } } } return 0; } if (((w.first + w.second) & 1) ^ ((b.first + b.second) & 1)) { printf( WHITE n ); fflush(stdout); if (WW <= BB) { while (w != TW) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {w.first + dx[i], w.second + dy[i]}; if (!inside(tmp)) continue; if (dw[tmp.first][tmp.second] < dw[w.first][w.second]) { printf( %d %d n , tmp.first, tmp.second); fflush(stdout); w = tmp; if (w == b) return 0; scanf( %d%d , &b.first, &b.second); break; } } } } else { while (w != TB) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {w.first + dx[i], w.second + dy[i]}; if (!inside(tmp)) continue; if (db[tmp.first][tmp.second] < db[w.first][w.second]) { printf( %d %d n , tmp.first, tmp.second); fflush(stdout); w = tmp; if (w == b) return 0; scanf( %d%d , &b.first, &b.second); break; } } } for (int i = 0; i < 8; ++i) { pii tmp; tmp = {w.first + dx[i], w.second + dy[i]}; if (!inside(tmp)) continue; if (tmp == b) return 0 * printf( %d %d n , tmp.first, tmp.second); } while (w != TW) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {w.first + dx[i], w.second + dy[i]}; if (!inside(tmp)) continue; if (dw[tmp.first][tmp.second] < dw[w.first][w.second]) { printf( %d %d n , tmp.first, tmp.second); fflush(stdout); w = tmp; if (w == b) return 0; scanf( %d%d , &b.first, &b.second); break; } } } } return 0; } else { printf( BLACK n ); fflush(stdout); scanf( %d%d , &w.first, &w.second); if (WW >= BB) { while (b != TB) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {b.first + dx[i], b.second + dy[i]}; if (!inside(tmp)) continue; if (db[tmp.first][tmp.second] < db[b.first][b.second]) { b = tmp; printf( %d %d n , tmp.first, tmp.second); fflush(stdout); if (w == b) return 0; scanf( %d%d , &w.first, &w.second); break; } } } } else { while (b != TW) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {b.first + dx[i], b.second + dy[i]}; if (!inside(tmp)) continue; if (dw[tmp.first][tmp.second] < dw[b.first][b.second]) { b = tmp; printf( %d %d n , tmp.first, tmp.second); fflush(stdout); if (w == b) return 0; scanf( %d%d , &w.first, &w.second); break; } } } for (int i = 0; i < 8; ++i) { pii tmp; tmp = {b.first + dx[i], b.second + dy[i]}; if (!inside(tmp)) continue; if (tmp == w) return 0 * printf( %d %d n , tmp.first, tmp.second); } while (b != TB) { for (int i = 0; i < 8; ++i) { pii tmp; tmp = {b.first + dx[i], b.second + dy[i]}; if (!inside(tmp)) continue; if (db[tmp.first][tmp.second] < db[b.first][b.second]) { b = tmp; printf( %d %d n , tmp.first, tmp.second); fflush(stdout); if (w == b) return 0; scanf( %d%d , &w.first, &w.second); break; } } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long bl_size = 320; int n, m; long long k; long long res; long long a[100005]; unordered_map<long long, long long> cnt; struct Query { int l, r, id; bool operator<(Query other) const { if (l / bl_size != other.l / bl_size) return l < other.l; else return (l / bl_size & 1) ? (r < other.r) : (r > other.r); } }; void add(long long x) { long long y = x ^ k; res += cnt[y]; cnt[x]++; } void rem(long long x) { long long y = x ^ k; if (y != x) res -= (cnt[y]); else res -= (cnt[y] - 1); cnt[x]--; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); scanf( %d%d%d , &n, &m, &k); long long prev[n + 10]; prev[0] = 0; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), prev[i] = prev[i - 1] ^ a[i]; Query q[100005]; for (int i = 1; i <= m; i++) { scanf( %d%d , &q[i].l, &q[i].r); q[i].l--; q[i].id = i; } sort(q + 1, q + n + 1); res = 0; long long ans[m + 10]; int cur_l = 0, cur_r = -1; for (int i = 1; i <= m; i++) { while (cur_l > q[i].l) { cur_l--; add(prev[cur_l]); } while (cur_l < q[i].l) { rem(prev[cur_l]); cur_l++; } while (cur_r > q[i].r) { rem(prev[cur_r]); cur_r--; } while (cur_r < q[i].r) { cur_r++; add(prev[cur_r]); } ans[q[i].id] = res; } for (int i = 1; i <= m; i++) cout << ans[i] << endl; }
|
#include <bits/stdc++.h> using namespace std; int is_prime(long long int n) { for (long long int i = 2; i * i <= n; i++) { if (n % i == 0) return 0; } return 1; } int main() { int t; cin >> t; for (int i = 0; i < t; i++) { int a, b, c, d, k; cin >> a >> b >> c >> d >> k; a = (a + c - 1) / c; b = (b + d - 1) / d; if (a + b <= k) cout << a << << b << endl; else cout << -1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> a[200100]; int cnt[200100]; vector<int> res; int main() { int n; scanf( %d , &n); int q; for (int i = 1; i <= n; i++) { scanf( %d , &q); a[q].push_back(i); } int pos = 0; while (true) { if (cnt[pos] < a[pos].size()) { res.push_back(a[pos][cnt[pos]]); cnt[pos]++; pos++; } else pos -= 3; if (pos < 0) break; } if (res.size() != n) { puts( Impossible ); } else { puts( Possible ); for (int i = 0; i < n; i++) { printf( %d , res[i]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int SIZE = 1000009; char s[SIZE]; long long int dsum[SIZE]; int dtotal; long long int usum[SIZE]; int utotal; int main() { int N; scanf( %d%s , &N, s + 1); for (int i = 1; i <= N; i++) { if (s[i] == U ) { ++utotal; usum[utotal] = i + usum[utotal - 1]; } else { ++dtotal; dsum[dtotal] = i + dsum[dtotal - 1]; } } int meetd = 0; int meetu = 0; for (long long int i = 1; i <= N; i++) { meetd += s[i] == D ; int lu = meetu; int rd = dtotal - meetd; int mn = min(lu, rd); long long int ans = (dsum[meetd + mn] - dsum[meetd] - (usum[meetu] - usum[meetu - mn])) * 2; if (s[i] == U ) { if (lu >= rd) ans += N + 1 - i; else ans += (dsum[meetd + mn + 1] - dsum[meetd + mn] - i) * 2 + i; } else { if (rd >= lu) ans += i; else ans += (i - usum[meetu - mn] + usum[meetu - mn - 1]) * 2 + N + 1 - i; } meetu += s[i] == U ; printf( %lld , ans); } printf( n ); }
|
#include <bits/stdc++.h> using namespace std; const long long maxN = 3e2 + 2, N = 1e5 + 7, MOD = 1e9 + 7, Mod = 1e9 + 6, INF = 1LL << 56; long long n, m, k, x, y, z, dp[maxN][maxN], ans[maxN][maxN]; int main() { cin.tie(0); cout.tie(0); ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) dp[i][j] = INF, ans[i][j] = INF; } for (int i = 1; i <= m; i++) cin >> x >> y >> z, dp[x][y] = min(dp[x][y], z); for (long long i = n; i >= 1; i--) { for (long long j = n; j >= 1; j--) dp[i + 1][j] = min(dp[i + 1][j], dp[i][j]), dp[i][j - 1] = min(dp[i][j], dp[i][j - 1]); } for (int len = 1; len <= n - 1; len++) { for (int i = 1; i <= n - len; i++) { long long j = len - i; for (int u = i; u <= j; u++) dp[i][j] = min(dp[i][u] + dp[u + 1][j], dp[i][j]); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= i; j++) { if (i != 1) ans[i][j] = min(ans[i][j], ans[i - 1][j]); for (int u = 1; u <= j; u++) ans[i][j] = min(ans[i - u][j - u] + dp[i - u + 1][i], ans[i][j]); } } if (ans[n][k] == INF) return cout << -1 n , 0; return cout << ans[n][k] << n , 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long p = 998244353; long long n, ans, a[1000010], c[1000010], cnt[1000010]; long long ksm(long long x, long long y) { long long xlh = 1; while (y) { if (y & 1) xlh = xlh * x % p; x = x * x % p; y /= 2; } return xlh; } int main() { long long i, j, x; scanf( %lld , &n); for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); for (j = 1; j <= a[i]; j++) { scanf( %lld , &x); cnt[x]++; c[x] = (c[x] + ksm(a[i], p - 2) * ksm(n, p - 2) % p) % p; } } for (i = 1; i <= 1000000; i++) if (cnt[i]) { ans = (ans + c[i] * cnt[i] % p * ksm(n, p - 2) % p) % p; } printf( %lld , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.v
// Design : system_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_0_0
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire resetn;
system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.resetn(resetn));
endmodule
(* ORIG_REF_NAME = "system_clk_wiz_0_0_clk_wiz" *)
module system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
(clk_out1,
resetn,
locked,
clk_in1);
output clk_out1;
input resetn;
output locked;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_0_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfbout_system_clk_wiz_0_0;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_0_0),
.O(clkfbout_buf_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_0_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(36.500000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(8.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(36.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_0_0),
.CLKFBOUT(clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_system_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_system_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, flag = 1; char c = getchar(); while ((c > 9 || c < 0 ) && c != - ) c = getchar(); if (c == - ) flag = 0, c = getchar(); while (c <= 9 && c >= 0 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return flag ? x : -x; } const int maxn = 2005; int f[maxn][maxn]; char s[maxn][maxn]; int main() { int n = read(), m = read(); for (int i = (1); i <= (int)(n); i++) scanf( %s , s[i] + 1); for (int i = (1); i <= (int)(2); i++) for (int j = (1); j <= (int)(m); j++) f[i][j] = 1; for (int i = (3); i <= (int)(n); i++) for (int j = (1); j <= (int)(m); j++) { if (j == 1 || j == m) { f[i][j] = 1; continue; } if (s[i][j] != s[i - 1][j - 1] || s[i][j] != s[i - 1][j] || s[i][j] != s[i - 1][j + 1] || s[i][j] != s[i - 2][j]) { f[i][j] = 1; continue; } int x = 100000; x = min(x, f[i - 1][j - 1]); x = min(x, f[i - 1][j]); x = min(x, f[i - 1][j + 1]); x = min(x, f[i - 2][j]); f[i][j] = x + 1; } long long ans = 0; for (int i = (1); i <= (int)(n); i++) for (int j = (1); j <= (int)(m); j++) ans += f[i][j]; cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__ISOBUFSRC_PP_BLACKBOX_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long maxN = 2e5 + 13, mod = 1e9 + 7; long long r, g, odp[maxN], ans; bool can(long long x) { if (x * (x + 1) / 2 <= r + g) return 1; return 0; } int32_t main() { cin >> r >> g; long long lf = 0, rg = max(r, g) + 1; while (rg - lf > 1) { long long mid = lf + rg >> 1; if (can(mid)) lf = mid; else rg = mid; } long long h = lf; odp[0] = 1; for (long long j = 0; j <= h; j++) { for (long long i = r; i >= 0; i--) { if (!(i == 0 && j == 0)) odp[i] = (odp[i] + ((i >= j) ? odp[i - j] : 0)) % mod; } } for (long long i = r; i + g >= h * (h + 1) / 2 && i >= 0; i--) { ans = (ans + odp[i]) % mod; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N =9999999; const double pi=acos(-1); int n,t,ans,a[N],k,s1,s2; int main(){ cin>>t; while(t--){ cin>>n>>k; if(n%2==1)cout<<((k-1)+((k-1))/(n/2))%n+1<<endl; else cout<<(k-1)%n+1<<endl; } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) #pragma GCC ostarimize( O500 ) using namespace std; const bool db = false; set<pair<int, int>> s; int a[200100]; int main() { int n, k, q; scanf( %d %d %d n , &n, &k, &q); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); scanf( n ); int type, num; set<pair<int, int>>::iterator it; while (q--) { scanf( %d %d n , &type, &num); if (type == 1) { s.insert({-a[num], num}); if (s.size() > k) { it = s.end(); it--; s.erase(it); } } else { if (s.count({-a[num], num})) puts( YES ); else puts( NO ); } } return 0; }
|
`timescale 1ns / 1ps
//**********************************************************************
// File: spi_master.v
// Module:spi_master
// by Robin zhang
//**********************************************************************
module spi_master(
clk,rst_n,
spi_miso,spi_mosi,spi_clk,
spi_tx_en,spi_rx_en,spi_over,mode_select,receive_status,
cs
);
input clk;
input rst_n;
input spi_miso;
output spi_mosi;
output spi_clk;
output cs;
input spi_tx_en;
output spi_over;
output receive_status;
input spi_rx_en;
input mode_select;
reg[7:0] data_count;
reg[7:0] recv_detect;
reg[7:0] spi_tx_db;
reg[4:0] cnt8;
reg spi_clkr;
reg spi_mosir;
reg spi_mosir1;
reg receive_status;
reg[7:0] spi_rx_dbr;
reg[7:0] spi_rx_dbr1;
reg frame_delay;
reg start_delay;
reg cs;
reg[7:0] frame_delay_cnt;
reg[7:0] start_delay_cnt;
wire[7:0] spi_rx_db;
wire[4:0] mode_reg;
wire[4:0] start_reg;
/***********************************************************************
*detect spi mode
***********************************************************************/
assign mode_reg = mode_select ? 5'd18 : 5'd17;
assign start_reg = mode_select ? 5'd1 : 5'd0;
/***********************************************************************
*control the spi timimg
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt8 <= 5'd0;
data_count <= 8'h0;
spi_tx_db <= 8'h0;
recv_detect <= 8'h0;
cs <= 1'b1;
end
else if((spi_tx_en || spi_rx_en) && (data_count < 8'd64) && (start_delay == 1'b1)) begin
if(cnt8 < mode_reg)begin
cnt8 <= cnt8+1'b1;
cs <= 1'b0;
end
else begin
if(spi_tx_en && spi_rx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
else begin
if(spi_tx_en && (frame_delay == 1'b0)) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
spi_tx_db <= spi_tx_db + 1'b1;
end
else if(frame_delay == 1'b0) begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count + 1'b1;
recv_detect <= (spi_rx_db == data_count) ? (recv_detect+1'b1) : recv_detect;
end
end
end
end
else begin
cs <= 1'b1;
cnt8 <= 5'd0;
data_count <= data_count;
end
end
/***********************************************************************
*start delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
start_delay <= 1'b0;
start_delay_cnt <= 'h0;
end
else begin
if((spi_tx_en || spi_rx_en) && (start_delay_cnt < 'd250))begin
start_delay_cnt <= start_delay_cnt + 1'b1;
end
else begin
start_delay <= 1'b1;
end
end
end
/***********************************************************************
*frame to frame delay
***********************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
frame_delay <= 1'b1;
frame_delay_cnt <= 'h0;
end
else begin
if((cnt8 >= (mode_reg - 1'b1)) && (frame_delay_cnt < 'd250))begin
frame_delay <= 1'b1;
frame_delay_cnt <= frame_delay_cnt + 1'b1;
end
else begin
frame_delay <= 1'b0;
frame_delay_cnt <= 'h0;
end
end
end
/***********************************************************************
*generate spi clk
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_clkr <= mode_select ? 1'b1 : 1'b0;
else if(cnt8 > start_reg && cnt8 < mode_reg)
spi_clkr <= ~spi_clkr;
else
spi_clkr <= spi_clkr;
end
assign spi_clk = spi_clkr;
/***********************************************************************
*spi master output data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd0: spi_mosir <= spi_tx_db[7];
4'd1: spi_mosir <= spi_tx_db[6];
4'd2: spi_mosir <= spi_tx_db[5];
4'd3: spi_mosir <= spi_tx_db[4];
4'd4: spi_mosir <= spi_tx_db[3];
4'd5: spi_mosir <= spi_tx_db[2];
4'd6: spi_mosir <= spi_tx_db[1];
4'd7: spi_mosir <= spi_tx_db[0];
default: spi_mosir <= 1'b1;
endcase
end
else
spi_mosir <= 1'b1;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_mosir1 <= 1'b1;
else if(spi_tx_en) begin
case(cnt8[4:1])
4'd1: spi_mosir1 <= spi_tx_db[7];
4'd2: spi_mosir1 <= spi_tx_db[6];
4'd3: spi_mosir1 <= spi_tx_db[5];
4'd4: spi_mosir1 <= spi_tx_db[4];
4'd5: spi_mosir1 <= spi_tx_db[3];
4'd6: spi_mosir1 <= spi_tx_db[2];
4'd7: spi_mosir1 <= spi_tx_db[1];
4'd8: spi_mosir1 <= spi_tx_db[0];
default: spi_mosir1 <= 1'b1;
endcase
end
else
spi_mosir1 <= 1'b1;
end
assign spi_mosi = mode_select ? spi_mosir1 : spi_mosir;
/***********************************************************************
*spi master input data
***********************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd1: spi_rx_dbr[7] <= spi_miso;
5'd3: spi_rx_dbr[6] <= spi_miso;
5'd5: spi_rx_dbr[5] <= spi_miso;
5'd7: spi_rx_dbr[4] <= spi_miso;
5'd9: spi_rx_dbr[3] <= spi_miso;
5'd11: spi_rx_dbr[2] <= spi_miso;
5'd13: spi_rx_dbr[1] <= spi_miso;
5'd15: spi_rx_dbr[0] <= spi_miso;
default: spi_rx_dbr <= spi_rx_dbr;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
spi_rx_dbr1 <= 8'hff;
else if(spi_rx_en) begin
case(cnt8)
5'd3: spi_rx_dbr1[7] <= spi_miso;
5'd5: spi_rx_dbr1[6] <= spi_miso;
5'd7: spi_rx_dbr1[5] <= spi_miso;
5'd9: spi_rx_dbr1[4] <= spi_miso;
5'd11: spi_rx_dbr1[3] <= spi_miso;
5'd13: spi_rx_dbr1[2] <= spi_miso;
5'd15: spi_rx_dbr1[1] <= spi_miso;
5'd17: spi_rx_dbr1[0] <= spi_miso;
default: spi_rx_dbr1 <= spi_rx_dbr1;
endcase
end
end
assign spi_rx_db = mode_select ? spi_rx_dbr1 : spi_rx_dbr;
assign spi_over = (data_count == 8'd64) ? 1'b1 :1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
receive_status <= 1'b0;
else
receive_status <= (recv_detect == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// clock divider generating clock and clock enable
module clock_divider #(
parameter DIVISOR = 40000000
) (
input wire CLK,
input wire RESET,
output reg CE, // for sequential logic driven by CLK
output reg CLOCK // only for combinatorial logic, does not waste bufg
);
integer counter_ce;
initial counter_ce = 0;
integer counter_clk;
initial counter_clk = 0;
initial CLOCK = 1'b0;
initial CE = 1'b0;
// clock enable
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
CE <= 1'b0;
end
else
begin
if (counter_ce == 0)
begin
CE <= 1'b1;
end
else
begin
CE <= 1'b0;
end
end
end
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
counter_ce <= 0;
end
else
begin
if (counter_ce == (DIVISOR - 1))
counter_ce <= 0;
else
counter_ce <= counter_ce + 1;
end
end
// clock
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
CLOCK <= 1'b0;
end
else
begin
if (counter_clk == 0)
begin
CLOCK <= ~CLOCK;
end
else
begin
CLOCK <= CLOCK;
end
end
end
always @(posedge CLK or posedge RESET)
begin
if (RESET == 1'b1)
begin
counter_clk <= 0;
end
else
begin
if (counter_clk == ((DIVISOR >> 1) - 1)) // DIVISOR/2
counter_clk <= 0;
else
counter_clk <= counter_clk + 1;
end
end
endmodule
|
`define DROP_SFD
module gmii2fifo9 # (
parameter Gap = 4'h2
) (
input sys_rst,
input gmii_rx_clk,
input gmii_rx_dv,
input [7:0] gmii_rxd,
// FIFO
output [8:0] din,
input full,
output reg wr_en,
output wr_clk
);
assign wr_clk = gmii_rx_clk;
parameter STATE_IDLE = 1'b0;
parameter STATE_DATA = 1'b1;
//-----------------------------------
// logic
//-----------------------------------
`ifndef DROP_SFD
reg [7:0] rxd = 8'h00;
reg rxc = 1'b0;
reg [3:0] gap_count = 4'h0;
always @(posedge gmii_rx_clk) begin
if (sys_rst) begin
gap_count <= 4'h0;
wr_en <= 1'b0;
end else begin
wr_en <= 1'b0;
if (gmii_rx_dv == 1'b1) begin
gap_count <= Gap;
rxd[7:0] <= gmii_rxd[7:0];
rxc <= 1'b1;
wr_en <= 1'b1;
end else begin
if (gap_count != 4'h0) begin
rxd[7:0] <= 8'h0;
rxc <= 1'b0;
wr_en <= 1'b1;
gap_count <= gap_count - 4'h1;
end
end
end
end
`else
reg [7:0] rxd = 8'h00;
reg rxc = 1'b0;
reg [3:0] gap_count = 4'h0;
reg [1:0] state;
always @(posedge gmii_rx_clk) begin
if (sys_rst) begin
state <= STATE_IDLE;
gap_count <= 4'h0;
wr_en <= 1'b0;
end else begin
wr_en <= 1'b0;
if (gmii_rx_dv == 1'b1) begin
case (state)
STATE_IDLE: begin
if (gmii_rxd[7:0] == 8'hd5)
state <= STATE_DATA;
end
STATE_DATA: begin
gap_count <= Gap;
rxd[7:0] <= gmii_rxd[7:0];
rxc <= 1'b1;
wr_en <= 1'b1;
end
endcase
end else begin
state <= STATE_IDLE;
if (gap_count != 4'h0) begin
rxd[7:0] <= 8'h0;
rxc <= 1'b0;
wr_en <= 1'b1;
gap_count <= gap_count - 4'h1;
end
end
end
end
`endif
assign din[8:0] = {rxc, rxd[7:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; struct edge { int v, id; edge *next; } * h[233333], pool[555555]; int top; inline void addedge(int u, int v, int id) { edge *tmp = &pool[top++]; tmp->v = v; tmp->id = id; tmp->next = h[u]; h[u] = tmp; edge *pmt = &pool[top++]; pmt->v = u; pmt->id = -id; pmt->next = h[v]; h[v] = pmt; } int n, m; int s[233333], f[233333], vis[233333], pa[233333]; void dfs(int u) { vis[u] = 1; for (edge *tmp = h[u]; tmp; tmp = tmp->next) { if (tmp->v != pa[u] && !vis[tmp->v]) { pa[tmp->v] = u; dfs(tmp->v); if (s[tmp->v]) { if (tmp->id > 0) f[tmp->id] += s[tmp->v]; else f[-tmp->id] -= s[tmp->v]; s[u] += s[tmp->v]; } } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &s[i]); scanf( %d , &m); int u, v; for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); addedge(u, v, i); } for (int i = 1; i <= n; i++) { if (!vis[i]) { dfs(i); if (s[i] != 0) { printf( Impossible n ); return 0; } } } printf( Possible n ); for (int i = 1; i <= m; i++) printf( %d n , f[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n + 1]; int i, m, k, l, x, y; for (i = 1; i <= n; i++) cin >> a[i]; cin >> m; for (i = 0; i < m; i++) { cin >> x >> y; a[x - 1] += y - 1; a[x + 1] += (a[x] - y); a[x] = 0; } for (i = 1; i <= n; i++) cout << a[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; #define ll int #define vl vector<long long> #define fr(i,a,n) for(ll i=a; i<n; i++) #define all(x) x.begin(), x.end() int32_t main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll t; cin>>t; while(t--){ ll n, x=0, z[4]; cin>>n; for(ll i=0; i<4; i++) cin>>z[i]; for(ll i=0; i<=15; i++){ ll a=0, b=0, c=0, d=0; if(i&1) a++; if(i&2) b++; if(i&4) c++; if(i&8) d++; if(z[0]-a-b<=n-2 && z[0]>=a+b) x++; if(z[1]-c-b<=n-2 && z[1]>=c+b) x++; if(z[2]-c-d<=n-2 && z[2]>=c+d) x++; if(z[3]-a-d<=n-2 && z[3]>=a+d) x++; if(x==4) break; else x=0; } if(x==4) cout<< Yes n ; else cout<< No n ; } }
|
module test_001(clk, a, a_old, b);
// test case taken from:
// http://www.reddit.com/r/yosys/comments/1wvpj6/trouble_with_assertions_and_sat_solver/
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 1;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_002(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 0; // <-- this will fail
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_003(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b; // <-- this will fail
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
module test_004(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 0;
output reg b = 1;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old == b); // <-- this will fail
end
endmodule
module test_005(clk, a, a_old, b);
// copy from test_001 with modifications
input wire clk;
input wire a;
output reg a_old = 1; // <-- inverted, no problem
output reg b = 0;
wire assertion = (a_old != b);
always @(posedge clk) begin
a_old <= a;
b <= !a;
assert(a_old != b);
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int64_t dr8[] = {1, 1, 0, -1, -1, -1, 0, 1}; int64_t dc8[] = {0, 1, 1, 1, 0, -1, -1, -1}; int64_t dr4[] = {1, 0, 0, -1}; int64_t dc4[] = {0, 1, -1, 0}; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int64_t i, n, j, m, k, l, t; int64_t x; cin >> x; while (x--) { cin >> n; vector<int64_t> v(n); for (i = 0; i < n; i++) cin >> v[i]; for (i = 0; i < n / 2; i++) { k = v[i]; v[i] = v[n - 1 - i]; v[n - 1 - i] = k; } for (i = 0; i < n; i++) cout << v[i] << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 2005; string str[max_n]; int dp[max_n][max_n][4]; inline void solve() { register int n, m, i, j, k; long long ans = 0; cin >> n >> m; for (i = 0; i < n; ++i) cin >> str[i]; for (i = 0; i < n; ++i) { dp[i][0][0] = 1; for (j = 1; j < m; ++j) { if (str[i][j] == str[i][j - 1]) dp[i][j][0] = dp[i][j - 1][0] + 1; else dp[i][j][0] = 1; } } for (i = 0; i < n; ++i) { dp[i][m - 1][1] = 1; for (j = m - 2; j >= 0; --j) { if (str[i][j] == str[i][j + 1]) dp[i][j][1] = dp[i][j + 1][1] + 1; else dp[i][j][1] = 1; } } for (j = 0; j < m; ++j) dp[0][j][2] = 1; for (i = 1; i < n; ++i) { for (j = 0; j < m; ++j) { if (str[i][j] == str[i - 1][j]) dp[i][j][2] = min(dp[i][j][0], min(dp[i][j][1], dp[i - 1][j][2] + 1)); else dp[i][j][2] = 1; } } for (j = 0; j < m; ++j) dp[n - 1][j][3] = 1; for (i = n - 2; i >= 0; --i) { for (j = 0; j < m; ++j) { if (str[i][j] == str[i + 1][j]) dp[i][j][3] = min(dp[i][j][2], dp[i + 1][j][3] + 1); else dp[i][j][3] = 1; ans += dp[i][j][3]; } } ans += m; cout << ans << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(long long a) { write(a); puts( ); } inline void wri(long long a) { write(a); putchar( ); } inline unsigned long long rnd() { return ((unsigned long long)rand() << 30 ^ rand()) << 4 | rand() % 4; } const int N = 50005, K = 16; int n; char ch[N], q[N]; struct data { int m, tong[N], SA[N], y[N], x[N], rk[N], h[N], height[N], logn[N]; char ch[N]; int dp[N][K]; inline int ask(int a, int b) { if (a == b) return n - a + 1; a = rk[a]; b = rk[b]; if (a > b) swap(a, b); b--; int zs = logn[b - a + 1]; return min(dp[b][zs], dp[a + (1 << zs) - 1][zs]); } void init() { int m = 150; memset(SA, 0, sizeof(SA)); memset(rk, 0, sizeof(rk)); memset(h, 0, sizeof(h)); memset(height, 0, sizeof(height)); memset(dp, 0, sizeof(dp)); memset(tong, 0, sizeof(tong)); memset(x, 0, sizeof(x)); memset(y, 0, sizeof(y)); for (int i = 1; i <= n; i++) tong[x[i] = ch[i]]++; for (int i = 1; i <= m; i++) tong[i] += tong[i - 1]; for (int i = n; i; i--) SA[tong[x[i]]--] = i; logn[0] = -1; for (int k = 1; k <= n; k <<= 1) { int p = 0; for (int i = n - k + 1; i <= n; i++) y[++p] = i; for (int i = 1; i <= n; i++) if (SA[i] > k) y[++p] = SA[i] - k; memset(tong, 0, sizeof(tong)); for (int i = 1; i <= n; i++) tong[x[y[i]]]++; for (int i = 1; i <= m; i++) tong[i] += tong[i - 1]; for (int i = n; i; i--) SA[tong[x[y[i]]]--] = y[i]; swap(x, y); x[SA[1]] = p = 1; for (int i = 2; i <= n; i++) x[SA[i]] = y[SA[i]] == y[SA[i - 1]] && y[SA[i] + k] == y[SA[i - 1] + k] ? p : ++p; if (p >= n) break; m = p; } for (int i = 1; i <= n; i++) rk[SA[i]] = i; for (int i = 1; i <= n; i++) { int t = SA[rk[i] + 1]; for (h[i] = max(0, h[i - 1] - 1); ch[i + h[i]] == ch[t + h[i]]; h[i]++) ; height[rk[i]] = h[i]; } for (int i = 1; i <= n; i <<= 1) logn[i] = logn[i >> 1] + 1; for (int i = 1; i <= n; i++) { dp[i][0] = height[i]; if (i > 1 && !logn[i]) logn[i] = logn[i - 1]; } for (int j = 1; j < K; j++) for (int i = 1 << j; i <= n; i++) dp[i][j] = min(dp[i][j - 1], dp[i - (1 << (j - 1))][j - 1]); } } S1, S2; bool check(int x) { for (int i = x; i + x <= n; i += x) { if (S1.ask(i, i + x) + S2.ask(n - i + 1, n - i - x + 1) >= x) return 1; } return 0; } void build() { memset(S1.ch, 0, sizeof(S1.ch)); memset(S2.ch, 0, sizeof(S2.ch)); for (int i = 1; i <= n; i++) S1.ch[i] = S2.ch[n - i + 1] = ch[i]; S1.init(); S2.init(); } int main() { scanf( %s , ch + 1); n = strlen(ch + 1); build(); for (int i = 1; i <= n; i++) if (check(i)) { int tot = 0; for (int j = 1; j <= i; j++) q[++tot] = ch[j]; for (int j = i + 1; j <= n; j++) { q[++tot] = ch[j]; if (S1.ask(j - i, j) >= i) { tot -= i; for (int k = j + 1; k < j + i && k <= n; k++) q[++tot] = ch[k]; j = j + i - 1; continue; } } n = tot; for (int j = 1; j <= n; j++) ch[j] = q[j]; build(); } ch[n + 1] = 0; puts(ch + 1); }
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
`define MSU
`ifndef MSU
assign reg_data_out = 0;
assign status_out = 0;
assign volume_out = 0;
assign volume_latch_out = 0;
assign addr_out = 0;
assign track_out = 0;
assign DBG_msu_reg_oe_rising = 0;
assign DBG_msu_reg_oe_falling = 0;
assign DBG_msu_reg_we_rising = 0;
assign DBG_msu_address = 0;
assign DBG_msu_address_ext_write_rising = 0;
`else
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 2147483647; int main() { string st; int i; cin >> st; for (i = 0; i < (int)st.size(); ++i) { if (st[i] == 0 ) { { st.erase(i, 1); break; } } else { if (i == (int)st.size() - 1) { st.erase(i, 1); } } } cout << st << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_4_V
`define SKY130_FD_SC_MS__O211AI_4_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_4_V
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { while (b) { a %= b; swap(a, b); } return a; } int main() { int n, k, i; long double x, y, xant, yant; scanf( %d%d , &n, &k); double sol = 0; for (i = 0; i < n; i++) { cin >> x >> y; if (i) sol += sqrt((x - xant) * (x - xant) + (y - yant) * (y - yant)); xant = x, yant = y; } sol = (sol * (long double)k) / 50.0; printf( %.9lf n , sol); return 0; }
|
`timescale 1 ns / 1 ps
module axi_bram_writer #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH/8-1:0] bram_porta_we
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
reg int_awready_reg, int_awready_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
wire int_wvalid_wire;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b0;
int_wready_reg <= 1'b0;
int_bvalid_reg <= 1'b0;
end
else
begin
int_awready_reg <= int_awready_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
end
end
always @*
begin
int_awready_next = int_awready_reg;
int_wready_next = int_wready_reg;
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire & ~int_awready_reg)
begin
int_awready_next = 1'b1;
int_wready_next = 1'b1;
end
if(int_awready_reg)
begin
int_awready_next = 1'b0;
int_wready_next = 1'b0;
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
assign s_axi_bresp = 2'd0;
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bvalid = int_bvalid_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = s_axi_awaddr[ADDR_LSB+BRAM_ADDR_WIDTH-1:ADDR_LSB];
assign bram_porta_wrdata = s_axi_wdata;
assign bram_porta_we = int_wvalid_wire ? s_axi_wstrb : {(BRAM_DATA_WIDTH/8){1'b0}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFRTP_1_V
`define SKY130_FD_SC_HVL__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; long long r1, r2, r3, d; cin >> n >> r1 >> r2 >> r3 >> d; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<vector<long long>> dp(n, vector<long long>(2, LLONG_MAX)); dp[0][0] = r1 * a[0] + r3; dp[0][1] = min(r1 * (a[0] + 2), r2 + r1); for (int i = 1; i < n; i++) { long long one = r1 * a[i] + r3; long long two = min(r1 * (a[i] + 2), r2 + r1); dp[i][0] = min(dp[i][0], dp[i - 1][0] + one); dp[i][0] = min(dp[i][0], dp[i - 1][1] + min(one, two) + 2 * d); if (i == n - 1) dp[i][0] = min(dp[i][0], dp[i - 1][1] + one + d); dp[i][1] = min(dp[i][1], dp[i - 1][0] + two); } printf( %lld n , min(dp[n - 1][0], dp[n - 1][1] + 2 * d) + (n - 1) * d); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_TB_V
`define SKY130_FD_SC_HS__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 A3 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 A3 = 1'b0;
#320 B1 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B1 = 1'b1;
#440 A3 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B1 = 1'bx;
#560 A3 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_TB_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) s = (s << 1) + (s << 3) + (ch ^ 48), ch = getchar(); return s * w; } int n, q; long long A[300010], B[300010], C[300010], D[300010], E[300010]; multiset<long long> S_Max, S_Min; multiset<long long> S[300010]; int main() { n = read(), q = read(); for (register int i = 1; i <= n; i++) B[i] = read(); for (register int i = 1; i <= n; i++) A[i] = read(), D[i] += 2, D[A[i]]++; for (register int i = 1; i <= n; i++) E[i] = B[i] / D[i]; for (register int i = 1; i <= n; i++) C[A[i]] += E[i]; for (register int i = 1; i <= n; i++) S[A[i]].insert(B[i] - D[i] * E[i] + E[i] + C[i]); for (register int i = 1; i <= n; i++) if (!S[i].empty()) { S_Max.insert(*S[i].rbegin() + E[i]); S_Min.insert(*S[i].begin() + E[i]); } while (q--) { int opt = read(); if (opt == 1) { int x = read(), y = read(), fa = A[x]; S_Max.erase(S_Max.find(*S[fa].rbegin() + E[fa])); S_Min.erase(S_Min.find(*S[fa].begin() + E[fa])); S[fa].erase(S[fa].find(B[x] - D[x] * E[x] + E[x] + C[x])); S_Max.erase(S_Max.find(*S[A[fa]].rbegin() + E[A[fa]])); S_Min.erase(S_Min.find(*S[A[fa]].begin() + E[A[fa]])); S[A[fa]].erase(S[A[fa]].find(B[fa] - D[fa] * E[fa] + E[fa] + C[fa])); S_Max.erase(S_Max.find(*S[A[A[fa]]].rbegin() + E[A[A[fa]]])); S_Min.erase(S_Min.find(*S[A[A[fa]]].begin() + E[A[A[fa]]])); S[A[A[fa]]].erase(S[A[A[fa]]].find(B[A[fa]] - D[A[fa]] * E[A[fa]] + E[A[fa]] + C[A[fa]])); C[A[fa]] -= E[fa]; D[fa]--, E[fa] = B[fa] / D[fa], C[fa] -= E[x]; C[A[fa]] += E[fa]; S[A[A[fa]]].insert(B[A[fa]] - D[A[fa]] * E[A[fa]] + E[A[fa]] + C[A[fa]]); S_Max.insert(*S[A[A[fa]]].rbegin() + E[A[A[fa]]]); S_Min.insert(*S[A[A[fa]]].begin() + E[A[A[fa]]]); S[A[fa]].insert(B[fa] - D[fa] * E[fa] + E[fa] + C[fa]); S_Max.insert(*S[A[fa]].rbegin() + E[A[fa]]); S_Min.insert(*S[A[fa]].begin() + E[A[fa]]); if (!S[fa].empty()) { S_Max.insert(*S[fa].rbegin() + E[fa]); S_Min.insert(*S[fa].begin() + E[fa]); } if (!S[y].empty()) { S_Max.erase(S_Max.find(*S[y].rbegin() + E[y])); S_Min.erase(S_Min.find(*S[y].begin() + E[y])); } S[y].insert(B[x] - D[x] * E[x] + E[x] + C[x]); S_Max.erase(S_Max.find(*S[A[y]].rbegin() + E[A[y]])); S_Min.erase(S_Min.find(*S[A[y]].begin() + E[A[y]])); S[A[y]].erase(S[A[y]].find(B[y] - D[y] * E[y] + E[y] + C[y])); S_Max.erase(S_Max.find(*S[A[A[y]]].rbegin() + E[A[A[y]]])); S_Min.erase(S_Min.find(*S[A[A[y]]].begin() + E[A[A[y]]])); S[A[A[y]]].erase( S[A[A[y]]].find(B[A[y]] - D[A[y]] * E[A[y]] + E[A[y]] + C[A[y]])); C[A[y]] -= E[y]; D[y]++, E[y] = B[y] / D[y], C[y] += E[x]; C[A[y]] += E[y]; S[A[A[y]]].insert(B[A[y]] - D[A[y]] * E[A[y]] + E[A[y]] + C[A[y]]); S_Max.insert(*S[A[A[y]]].rbegin() + E[A[A[y]]]); S_Min.insert(*S[A[A[y]]].begin() + E[A[A[y]]]); S[A[y]].insert(B[y] - D[y] * E[y] + E[y] + C[y]); S_Max.insert(*S[A[y]].rbegin() + E[A[y]]); S_Min.insert(*S[A[y]].begin() + E[A[y]]); S_Max.insert(*S[y].rbegin() + E[y]); S_Min.insert(*S[y].begin() + E[y]); A[x] = y; } else if (opt == 2) { int x = read(); printf( %lld n , B[x] - D[x] * E[x] + E[x] + C[x] + E[A[x]]); } else printf( %lld %lld n , *S_Min.begin(), *S_Max.rbegin()); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #(PAR) m1();
m3 #(PAR) m3();
mnooverride #(10) mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #(PAR1MINUS1) m2 ();
// Packed arrays
localparam [1:0][3:0] PACKED_PARAM = { 4'h3, 4'h6 };
initial if (PACKED_PARAM != 8'h36) $stop;
endmodule
// bug 810
module m2 #(/*parameter*/ integer PAR2 = 10);
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long qr() { register long long ret = 0, f = 0; register char c = getchar(); while (c < 48 || c > 57) f |= c == 45, c = getchar(); while (c >= 48 && c <= 57) ret = ret * 10 + c - 48, c = getchar(); return f ? -ret : ret; } const int maxn = 1e5 + 5; int n, m, p; int dis[maxn]; long long sumd[maxn]; long long sumdata[maxn]; long long x[maxn]; long long y[maxn]; long long ans; deque<int> q; struct NODE { int pos, time; long long limit; NODE() { ans = pos = time = 0; } inline bool operator<(const NODE& a) const { return limit < a.limit; } inline void scan() { pos = qr(); time = qr(); limit = time - sumd[pos]; } } data[maxn]; long long dp[101][maxn]; inline void wk() { memset(dp, 5, sizeof dp); dp[0][0] = 0; deque<int>::iterator ita; for (register int i = 0; i <= m; ++i) x[i] = i; for (register int t = 1; t <= p; ++t) { for (register int i = 0; i <= m; ++i) { dp[t][i] = dp[t - 1][i]; y[i] = dp[t - 1][i] + sumdata[i]; } q.clear(); for (register int i = 1; i <= m; ++i) { q.push_back(i - 1); ita = q.begin(); while (q.size() > 1 && y[*(ita + 1)] - y[*ita] <= 1ll * data[i].limit * ((*(ita + 1)) - (*ita))) q.pop_front(), ita = q.begin(); register int j = q.front(); dp[t][i] = min(dp[t][i], dp[t - 1][j] + 1ll * (i - j) * data[i].limit - (sumdata[i] - sumdata[j])); ita = q.end() - 1; while (q.size() > 1 && (y[*ita] - 1ll * y[*(ita - 1)]) * (i - (*ita)) >= 1ll * (y[i] - y[*ita]) * ((*ita) - (*(ita - 1)))) q.pop_back(), ita = q.end() - 1; ; } } cout << dp[p][m] << endl; } int main() { n = qr(); m = qr(); p = qr(); for (register int t = 2; t <= n; ++t) sumd[t] = (dis[t] = qr()) + sumd[t - 1]; for (register int t = 1; t <= m; ++t) data[t].scan(); sort(data + 1, data + m + 1); for (register int t = 1; t <= m; ++t) sumdata[t] = data[t].limit + sumdata[t - 1]; wk(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1153][1153]; int n, m; unsigned long long int b[1153][1153]; bool pos(int minval) { memset(b, 0, sizeof(b)); int i, j, k; for (i = 0; i < n; i++) { int ccnt = 0; for (j = 0; j < 1024; j += 63) { unsigned long long int blk = 0; for (k = j; k < j + 63; k++) { blk <<= 1; if (a[i][k] >= minval) { blk |= 1; } } b[i][j] = blk; } for (j = 0; j < i; j++) { ccnt = 0; for (k = 0; k < 1024; k += 63) { unsigned long long int ret = (b[i][k] & b[j][k]); if (ret != 0) { if ((ret & (ret - 1)) == 0) ccnt++; else return true; } } if (ccnt >= 2) return true; } } return false; } int main() { int i, j; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { scanf( %d , &a[i][j]); } } int lb = 0, ub = 1000000004, mid, ans; while (lb <= ub) { mid = (lb + ub) / 2; if (pos(mid)) { lb = mid + 1; ans = mid; } else ub = mid - 1; } cout << ans << endl; return 0; }
|
//#############################################################################
//# Function: Clock synchronizer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_dsync #(parameter PS = 2, // number of sync stages
parameter DELAY = 0 // random delay
)
(
input clk, // clock
input nreset, // clock
input din, // input data
output dout // synchronized data
);
`ifdef CFG_ASIC
asic_dsync asic_dsync (.clk(clk),
.nreset(nreset),
.din(din),
.dout(dout));
`else
reg [PS:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
sync_pipe[PS:0] <= 'b0;
else
sync_pipe[PS:0] <= {sync_pipe[PS-1:0],din};
// drive randomize delay from testbench
assign dout = (DELAY & sync_pipe[PS]) | //extra cycle
(~DELAY & sync_pipe[PS-1]); //default
`endif // !`ifdef CFG_ASIC
endmodule // oh_dsync
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_PP_SYMBOL_V
|
`timescale 1ns/100ps
`define DEBUG 1
`include "../define.v"
`include "../regfile.v"
`include "../pipeline_CPU.v"
`include "../hilo_reg.v"
`include "../BranchControl.v"
`include "../HazardControl.v"
`include "../ForwardControl.v"
`include "../IF.v"
`include "../IF_ID.v"
`include "../ID.v"
`include "../ID_EX.v"
`include "../EX.v"
`include "../ALU.v"
`include "../decoder.v"
`include "../EX_MEM.v"
`include "../MEM.v"
`include "../RM_ctrl.v"
`include "../WM_ctrl.v"
`include "../MEM_WB.v"
`include "../utilities/dffe.v"
`include "../utilities/mux2x1.v"
`include "../utilities/mux4x1.v"
`include "rom.v"
`include "memory.v"
module SOPC;
reg clk;
reg rst;
wire[`RegDataWidth-1:0] data_from_mem;
wire[`MemAddrWidth-1:0] mem_addr;
wire[3:0] mem_byte_slct;
wire[`RegDataWidth-1:0] data_to_write_mem;
wire mem_we;
wire mem_re;
wire[`InstDataWidth-1:0] inst_from_rom;
wire[`InstAddrWidth-1:0] rom_addr;
wire rom_ce;
supply1 vcc;
supply0 gnd;
pipeline_CPU CPU(
.clk(clk),
.rst(rst),
.data_from_mem(data_from_mem),
.mem_addr(mem_addr),
.mem_byte_slct(mem_byte_slct),
.data_to_write_mem(data_to_write_mem),
.mem_we(mem_we),
.mem_re(mem_re),
.inst_from_rom(inst_from_rom),
.rom_addr(rom_addr),
.rom_ce(rom_ce)
);
rom #(.InstMemNum(32)) ROM(
.rst(gnd),
.ce(rom_ce),
.addr(rom_addr),
.inst(inst_from_rom)
);
memory RAM(
.rst(rst),
.ce(mem_re),
.data_i(data_to_write_mem),
.addr_i(mem_addr),
.we(mem_we),
.byte_slct(mem_byte_slct),
.data_o(data_from_mem)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
$dumpfile("test_info/dependency (forwarding)/dependency.vcd");
$dumpvars;
$readmemh("test_info/dependency (forwarding)/dependency.data", ROM.rom_data, 0, 11);
rst = `RstEnable;
#3 rst = ~`RstEnable;
#70 $finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_clksel.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_clksel
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_clksel(/*AUTOARG*/
// Outputs
clkout, sysclk_sel,
// Inputs
io_pwron_rst_l, sel, testmode_l, sysclk, divbypclk, byp_mult_sel_l,
nstepsel, jtag_clock_dr, capture_l, bypmode
);
input io_pwron_rst_l;
input [2:0] sel;
input testmode_l;
input sysclk;
input divbypclk;
input byp_mult_sel_l;
input nstepsel;
input jtag_clock_dr;
input capture_l;
input bypmode;
output clkout;
output sysclk_sel;
wire force_altclk_l;
wire altclk_sync_l;
wire tck_sync;
wire bypclk_sync_pre;
wire bypclk_sync;
wire tck_sync_pre;
wire force_alt_clk_sync;
wire mult_sel;
wire nstep_clock_dr;
wire clock_dr;
wire altclk_sync_l_bar;
wire sysclk_sel_bar;
// -----------------------------------------------
//
// N-step and jtag_clock_dr mode
// When dft_clsp_capture_l is asserted, nstep goes through,
// otherwise jtag_clock_dr goes through.
// jtag_clock_dr can be dft_jtag_clock_dr (from dft) or j_clk/io_tck2
// if dft_clsp_parallel_scan is asserted
//
// -----------------------------------------------
// Clock gating
// capture cycle:
// capture_l is low, let nstep clock through
// assign nstep_clock_dr = jtag_clock_dr & capture_l;
// capture_l changes value on neg edge of tck
ctu_and2 u_capture_l_gated (.a (jtag_clock_dr), .b(capture_l), .z(nstep_clock_dr));
// nstep_clock_dr is undefined in ctu pin base parallel scan mode
ctu_mux21 u_jtag_clock_mux_gated( .z(clock_dr), .s(testmode_l), .d0(jtag_clock_dr),
.d1(nstep_clock_dr));
// Work around Reading macro
ctu_clksel_async_synchronizer u_mult_sel_clk(
.presyncdata(mult_sel),
.syncdata (force_alt_clk_sync),
.arst_l(io_pwron_rst_l),
.aset_l(1'b1),
.clk (sysclk)
);
ctu_clksel_async_synchronizer u_byp_mult_sel_sync(
.presyncdata(altclk_sync_pre),
.syncdata (altclk_sync_l),
.arst_l(io_pwron_rst_l),
.aset_l(1'b1),
.clk (divbypclk)
);
ctu_clksel_async_synchronizer u_bypclk_sync(
.presyncdata(bypclk_sync_pre),
.syncdata (bypclk_sync),
.aset_l(io_pwron_rst_l),
.arst_l(1'b1),
.clk(divbypclk)
);
ctu_clksel_async_synchronizer u_tck_sync(
.presyncdata(tck_sync_pre),
.syncdata (tck_sync),
.arst_l(io_pwron_rst_l),
.aset_l(1'b1),
.clk(jtag_clock_dr)
);
assign mult_sel = bypmode | nstepsel;
assign force_altclk_l = sel[0];
assign altclk_sync_pre = byp_mult_sel_l;
assign bypclk_sync_pre = sel[2] ;
assign tck_sync_pre = sel[1];
bw_u1_aoi22_4x u_clkout_gated ( .a1(bypclk_sync), .a2(divbypclk),
.b1(tck_sync),.b2(clock_dr), .z(clkout));
ctu_inv u_altclk_sync_l_gated (.z(altclk_sync_l_bar), .a(altclk_sync_l));
bw_u1_oai21_4x u_sysclk_sel_bar_gated (.a (altclk_sync_l_bar),
.b1 (force_altclk_l),
.b2 (force_alt_clk_sync),
.z (sysclk_sel_bar));
ctu_inv u_sysclk_sel_gated (.z(sysclk_sel), .a(sysclk_sel_bar));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PS_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top RAT_slice_7_0_0 -prefix
// RAT_slice_7_0_0_ RAT_slice_7_3_0_sim_netlist.v
// Design : RAT_slice_7_3_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_slice_7_3_0,xlslice,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlslice,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_slice_7_0_0
(Din,
Dout);
input [17:0]Din;
output [4:0]Dout;
wire [17:0]Din;
assign Dout[4:0] = Din[12:8];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int a[4]; int main() { cin >> a[0] >> a[1] >> a[2] >> a[3]; sort(a, a + 4); if (a[0] + a[1] > a[2] || a[1] + a[2] > a[3]) { cout << TRIANGLE ; return 0; } else if (a[0] + a[1] == a[2] || a[1] + a[2] == a[3]) { cout << SEGMENT ; return 0; } else cout << IMPOSSIBLE ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_PP_BLACKBOX_V
|
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