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#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline void write(long long a) { if (a < 0) { printf( - ); a = -a; } if (a >= 10) write(a / 10); putchar(a % 10 + 0 ); } inline void writeln(long long a) { write(a); printf( n ); } long long bin[110]; int main() { long long t = read(), a = read(), b = read(); if (t == a && a == b) { if (t == 1ll) printf( inf n ); if (t != 1ll) printf( 2 n ); return 0; } if (t > a) { if (a != b) puts( 0 ); else puts( 1 ); return 0; } if (a == b) { puts( 1 ); return 0; } int len = 0, cnt = 0; if (t == 1 && a == 1 && b != 1) { puts( 0 ); return 0; } while (b) { bin[++len] = b % a; cnt += bin[len]; b /= a; } long long ans = 0; for (int i = len; i >= 1; i--) { ans = ans * t + bin[i]; } if (cnt == 1) { if (ans != a) { ans = 0; len--; bin[len] = a; for (int i = len; i >= 1; i--) ans = ans * t + bin[i]; } } printf( %d n , ans == a); }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = (crc[1:0]==0 ? 3'd0
: crc[1:0]==0 ? 3'd1
: crc[1:0]==0 ? 3'd2 : 3'd4);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[2:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h704ca23e2a83e1c5
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [2:0] in;
output reg [31:0] out;
localparam ST_0 = 0;
localparam ST_1 = 1;
localparam ST_2 = 2;
always @(posedge clk) begin
case (1'b1) // synopsys parallel_case
in[ST_0]: out <= 32'h1234;
in[ST_1]: out <= 32'h4356;
in[ST_2]: out <= 32'h9874;
default: out <= 32'h1;
endcase
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; void inputOutput() {} signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; inputOutput(); string yelo = AHIMOTUVWXY ; string s; cin >> s; long long int n = s.length(); for (long long int i = 0; i < n; i++) { if (yelo.find(s[i]) == string::npos) return cout << NO , 0; } for (long long int i = 0; i < n / 2; i++) { if (s[i] != s[n - i - 1]) return cout << NO , 0; } cout << YES ; cerr << time elapsed : << 1.0 * clock() / CLOCKS_PER_SEC << sec n ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:20:44 04/16/2015
// Design Name: BinaryExponentiation
// Module Name: H:/Users/asw011/Downloads/PrimeFactorization (1)/PrimeFactorization/test_binary_exponentiation.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: BinaryExponentiation
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_binary_exponentiation;
// Inputs
reg [8:0] base;
reg [7:0] exponent;
reg clk, reset;
// Outputs
wire [99:0] result;
wire isDone;
// Instantiate the Unit Under Test (UUT)
BinaryExponentiation uut (
.clk(clk),
.base(base),
.exponent(exponent),
.reset(reset),
.result(result),
.isDone(isDone)
);
always #2 clk = ~clk;
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
base = 0;
exponent = 0;
#10;
base = 2;
exponent = 25;
#150;
base = 3;
exponent = 17;
reset = 1;
#5;
reset = 0;
#150;
base = 5;
exponent = 30;
reset = 1;
#5;
reset = 0;
#150;
base = 11;
exponent = 1;
reset = 1;
#5;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { string s = ROYGBIV ; long long int n, i; cin >> n; for (i = 0; i < n - 3; i++) { cout << s[i % 4]; } cout << BIV ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long n, x, y, a, b, c, t, q; string s; while (cin >> n >> q) { if ((n / q) % 2 == 0) { cout << NO << endl; } else cout << YES << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; map<long long, vector<long long> > m; map<long long, bool> v; map<long long, long long> c; vector<long long> b; long long i, j, k, x, y, r; for (i = 1; i <= n; i++) { cin >> x >> y; if (x == -1) r = i; else m[x].push_back(i); v[i] = false; c[i] = y; } for (i = 1; i <= n; i++) { } queue<long long> q; q.push(r); long long f = 1; while (!q.empty()) { j = q.front(); if (c[j] == 1) f = 0; for (i = 0; i < m[j].size(); i++) { q.push(m[j][i]); if (c[m[j][i]] != 1 and !f) { f = 1; } } if (f == 0) { b.push_back(j); } f = 1; q.pop(); } if (b.size() == 0) cout << -1; else { sort(b.begin(), b.begin() + b.size()); for (i = 0; i < b.size(); i++) { cout << b[i] << ; } } }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:45:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_stub.v
// Design : system_vga_transform_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_transform,Vivado 2016.4" *)
module system_vga_transform_0_0(clk, enable, x_addr_in, y_addr_in, rot_m00,
rot_m01, rot_m10, rot_m11, t_x, t_y, x_addr_out, y_addr_out)
/* synthesis syn_black_box black_box_pad_pin="clk,enable,x_addr_in[9:0],y_addr_in[9:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],x_addr_out[9:0],y_addr_out[9:0]" */;
input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
endmodule
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#include<bits/stdc++.h> using namespace std; const int N = 3e5 + 9; const long long inf = 2e18; int a[N], c[N], n, m; long long s1[N], s2[N]; long long f(int mid) { for (int i = mid; i <= n; i++) { if (a[i] < i - mid + 1) return 0; } return 1; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= m; i++) { cin >> c[i]; s2[i] = s2[i - 1] + c[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { s1[i] = s1[i - 1] + c[a[i]]; } int l = 1, r = n; int z = n + 1; while (l <= r) { int mid = l + r >> 1; if (f(mid)) { z = mid; r = mid - 1; } else { l = mid + 1; } } long long ans = inf; for (int i = z; i <= n + 1; i++) { ans = min(ans, s1[i - 1] + s2[n - i + 1]); } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 505, M = 100500; int read(int &n) { char ch = ; int q = 0, w = 1; for (; (ch != - ) && ((ch < 0 ) || (ch > 9 )); ch = getchar()) ; if (ch == - ) w = -1, ch = getchar(); for (; ch >= 0 && ch <= 9 ; ch = getchar()) q = q * 10 + ch - 48; n = q * w; return n; } int m, n, m1; int B[M * 2][2], A[N], B0, B1[N]; int b1[N], zx[N]; double s[N][N], t[N][N], di[N][N]; void link(int q, int w) { B1[q]++, B1[w]++; B[++B0][0] = A[q]; A[q] = B0, B[B0][1] = w; B[++B0][0] = A[w]; A[w] = B0, B[B0][1] = q; } void chenans() { for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) t[i][j] = 0; for (int k = 1; k <= m; k++) for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) t[i][j] += s[i][k] * di[k][j]; for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) s[i][j] = t[i][j]; } void chen() { for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) t[i][j] = 0; for (int k = 1; k <= m; k++) for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) t[i][j] += di[i][k] * di[k][j]; for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) di[i][j] = t[i][j]; } double JC() { while (m1) { if (m1 & 1) chenans(); chen(); m1 >>= 1; } double ans = 0; for (int i = 1; i <= m; i++) ans += s[i][m]; return ans; } double b[N][N], c[N][N]; int z[N]; void GS() { for (int i = 1; i <= n; i++) { b[i][i] = c[i][i] = 1; for (int j = A[i]; j; j = B[j][0]) if (!zx[B[j][1]]) b[i][B[j][1]] -= 1.0 / B1[B[j][1]]; } for (int i = 1; i <= n; i++) { int q = i; for (int j = i + 1; j <= n; j++) if (((b[j][i]) > 0 ? (b[j][i]) : -(b[j][i])) > ((b[q][i]) > 0 ? (b[q][i]) : -(b[q][i]))) q = j; if (q != i) { for (int j = 1; j <= n; j++) swap(b[i][j], b[q][j]), swap(c[i][j], c[q][j]); } for (int j = 1; j <= n; j++) if (i != j) { double t = b[j][i] / b[i][i]; for (int k = 1; k <= n; k++) b[j][k] -= t * b[i][k], c[j][k] -= t * c[i][k]; } } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) c[i][j] /= b[i][i]; for (int i = A[1]; i; i = B[i][0]) z[B[i][1]]++; for (int i = 1; i <= n; i++) if (zx[i]) { for (int j = 1; j <= n; j++) s[zx[i]][zx[i]] += c[i][j] * ((double)z[j] / B1[1]); } for (int I = 1; I <= n; I++) if (zx[I] && B1[I]) { for (int i = 1; i <= n; i++) z[i] = 0; for (int i = A[I]; i; i = B[i][0]) z[B[i][1]]++; for (int i = 1; i <= n; i++) if (zx[i]) { for (int j = 1; j <= n; j++) di[zx[I]][zx[i]] += c[i][j] * ((double)z[j] / B1[I]); } } } int main() { int q, w; read(n), read(m), read(m1); m1 -= 2; if (m1 < 0) { printf( 0 n ); return 0; } for (int i = 1; i <= n; i++) if (read(q)) b1[++b1[0]] = i, zx[i] = b1[0]; for (int i = 1; i <= m; i++) read(q), read(w), link(q, w); GS(); m = b1[0]; printf( %.12lf n , JC()); return 0; }
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#include <bits/stdc++.h> using ll = long long; using ld = long double; using ull = unsigned long long; using namespace std; const int N = 2002, NN = 502, mod = 1e9 + 7, mod1 = 1e9 + 9, Base = 317, Base1 = 371; int n, K, pw[NN], pw1[NN], lcp[N], mn[N][11], id[N]; string s[N]; struct Hash { vector<pair<int, int> > hs; Hash() {} Hash(const string &s) : hs(((int)(s).size()) + 1, {0, 0}) { for (int i = (1); i <= (((int)(s).size())); ++i) hs[i] = {(hs[i - 1].first * 1LL * Base + s[i - 1]) % mod, (hs[i - 1].second * 1LL * Base1 + s[i - 1]) % mod1}; } pair<int, int> query(int l, int r) { pair<int, int> h = { hs[r].first - hs[l - 1].first * 1LL * pw[r - l + 1] % mod, hs[r].second - hs[l - 1].second * 1LL * pw1[r - l + 1] % mod1}; if (h.first < 0) h.first += mod; if (h.second < 0) h.second += mod; return h; } } hs[N]; int getLcp(const int &A, const int &B) { int l = 1, r = min(((int)(s[A]).size()), ((int)(s[B]).size())); while (l <= r) { int m = (l + r) >> 1; if (hs[A].query(1, m) == hs[B].query(1, m)) l = m + 1; else r = m - 1; } return r; } bool cmp(const int &A, const int &B) { int r = getLcp(A, B); if (r == ((int)(s[B]).size())) return 0; if (r == ((int)(s[A]).size())) return 1; return s[A][r] < s[B][r]; } int queryLcp(int l, int r) { int k = 31 - __builtin_clz(r - l + 1); return min(mn[l][k], mn[r - (1 << k) + 1][k]); } vector<int> solve(int l, int r) { if (l == r) return vector<int>(2, 0); vector<int> dp(r - l + 2, 0); int mid = l + 1; for (int i = (l + 2); i <= (r); ++i) if (lcp[i] < lcp[mid]) mid = i; vector<int> dpLeft = solve(l, mid - 1), dpRight = solve(mid, r); for (int i = (0); i <= (mid - l); ++i) for (int j = (0); j <= (r - mid + 1); ++j) dp[i + j] = max(dp[i + j], dpLeft[i] + dpRight[j] + i * j * lcp[mid]); return dp; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> K; for (int i = (1); i <= (n); ++i) cin >> s[i], id[i] = i, hs[i] = Hash(s[i]); sort(id + 1, id + 1 + n, cmp); for (int i = (2); i <= (n); ++i) lcp[i] = getLcp(id[i - 1], id[i]); cout << solve(1, n)[K]; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 52; struct node { int v, w, nxt; } e[N << 1]; int s, n, m, first[N], cnt = 1, siz[N], de[N]; inline void add(int u, int v, int w) { e[++cnt].v = v; e[cnt].w = w; e[cnt].nxt = first[u]; first[u] = cnt; ++de[u]; } inline void dfs(int u, int f) { for (int i = first[u]; i; i = e[i].nxt) { int v = e[i].v; if (v == f) continue; dfs(v, u); siz[u] += siz[v]; } } int dp[N << 1][N][N]; inline int solve(int i, int x, int y) { if (x + y == 0) return 0; int v = e[i].v; int &f = dp[i][x][y]; if (f != -1) return f; if (de[v] == 1) { if (y == 0) return 0; else { f = solve(i ^ 1, y, 0) + e[i].w; return f; } } int g[N]; memset(g, 0, sizeof(g)); g[0] = 0x3f3f3f3f; for (int j = first[v]; j; j = e[j].nxt) { if (j == (i ^ 1)) continue; for (int k = x; k >= 1; --k) for (int w = k; w; --w) g[k] = max(g[k], min(g[k - w], e[j].w + solve(j, w, x + y - w))); } return f = g[x]; } int main() { memset(dp, -1, sizeof(dp)); scanf( %d , &n); for (int i = 1, u, v, w; i < n; ++i) { scanf( %d%d%d , &u, &v, &w); add(u, v, w); add(v, u, w); } scanf( %d%d , &s, &m); for (int i = 1, x; i <= m; ++i) { scanf( %d , &x); siz[x]++; } dfs(s, 0); int ans = 0x3f3f3f3f; for (int i = first[s]; i; i = e[i].nxt) { int v = e[i].v; ans = min(ans, solve(i, siz[v], m - siz[v]) + e[i].w); } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int vp, vd, time_s, time_b, dist; int main() { scanf( %d%d%d%d%d , &vp, &vd, &time_s, &time_b, &dist); if (vd <= vp) { puts( 0 ); return 0; } int ans = 0; double now = 1.0 * vp * time_s; while (now < dist) { double Overtake = now / (vd - vp); double loc = now + Overtake * vp; if (loc >= dist) break; ++ans; now = loc; double Back = now / vd + 1.0 * time_b; now += Back * vp; } printf( %d n , ans); return 0; }
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/*
* Copyright 2010, Aleksander Osman, . All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module early_boot(
input CLK_I,
input RST_I,
output reg CYC_O,
output reg [31:0] DAT_O,
output reg STB_O,
output reg WE_O,
output reg [31:2] ADR_O,
output [3:0] SEL_O,
input [31:0] DAT_I,
input ACK_I,
input ERR_I,
input RTY_I,
//****************** OTHER
//finished loading
output loading_finished_o
);
assign SEL_O = 4'b1111;
assign loading_finished_o = (state == S_FINISHED) ? 1'b1 : 1'b0;
reg [3:0] state;
reg [9:0] wait_counter;
parameter [3:0]
S_CHECK_STATUS = 4'd0,
S_CHECK_STATUS_2 = 4'd1,
S_CHECK_STATUS_3 = 4'd2,
S_SET_SIZE = 4'd3,
S_SET_SIZE_2 = 4'd4,
S_SET_CONTROL = 4'd5,
S_SET_CONTROL_2 = 4'd6,
S_CHECK_FINISHED = 4'd7,
S_CHECK_FINISHED_2 = 4'd8,
S_CHECK_FINISHED_3 = 4'd9,
S_FINISHED = 4'd10;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
CYC_O <= 1'b0;
DAT_O <= 32'd0;
STB_O <= 1'b0;
WE_O <= 1'b0;
ADR_O <= 30'd0;
state <= S_CHECK_STATUS;
wait_counter <= 10'd0;
end
else if(state == S_CHECK_STATUS) begin
CYC_O <= 1'b1;
DAT_O <= 32'd0;
STB_O <= 1'b1;
WE_O <= 1'b0;
ADR_O <= 30'h30000000;
state <= S_CHECK_STATUS_2;
end
else if(state == S_CHECK_STATUS_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
if(DAT_I == 32'd2) begin
state <= S_SET_SIZE;
end
else begin
state <= S_CHECK_STATUS_3;
end
end
end
else if(state == S_CHECK_STATUS_3) begin
if(wait_counter == 10'd1023) begin
wait_counter <= 10'd0;
state <= S_CHECK_STATUS;
end
else wait_counter <= wait_counter + 10'd1;
end
else if(state == S_SET_SIZE) begin
CYC_O <= 1'b1;
DAT_O <= 32'd2048;
STB_O <= 1'b1;
WE_O <= 1'b1;
ADR_O <= 30'h30000002;
state <= S_SET_SIZE_2;
end
else if(state == S_SET_SIZE_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
state <= S_SET_CONTROL;
end
end
else if(state == S_SET_CONTROL) begin
CYC_O <= 1'b1;
DAT_O <= 32'd2;
STB_O <= 1'b1;
WE_O <= 1'b1;
ADR_O <= 30'h30000003;
state <= S_SET_CONTROL_2;
end
else if(state == S_SET_CONTROL_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
state <= S_CHECK_FINISHED;
end
end
else if(state == S_CHECK_FINISHED) begin
CYC_O <= 1'b1;
DAT_O <= 32'd0;
STB_O <= 1'b1;
WE_O <= 1'b0;
ADR_O <= 30'h30000000;
state <= S_CHECK_FINISHED_2;
end
else if(state == S_CHECK_FINISHED_2) begin
if(ACK_I == 1'b1) begin
CYC_O <= 1'b0;
STB_O <= 1'b0;
if(DAT_I == 32'd2) begin //idle
state <= S_FINISHED;
end
else begin
state <= S_CHECK_FINISHED_3;
end
end
end
else if(state == S_CHECK_FINISHED_3) begin
if(wait_counter == 10'd1023) begin
wait_counter <= 10'd0;
state <= S_CHECK_FINISHED;
end
else wait_counter <= wait_counter + 10'd1;
end
else if(state == S_FINISHED) begin
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long q; cin >> q; while (q--) { long long n, a, b; cin >> n >> a >> b; if (a + b >= n) cout << max(a, b) - (a + b - 1 - n) << endl; else cout << min(a, b) + 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { int va, id; } a[200015], b[200015]; int n, Q, rv[200015]; long long dp[200015]; inline bool cmp(node x, node y) { return x.va > y.va; } int main() { scanf( %d%d , &n, &Q); for (int i = 1; i <= n; i++) scanf( %d , &a[i].va), a[i].id = i; for (int i = 1; i <= n; i++) scanf( %d , &b[i].va), b[i].id = i; sort(a + 1, a + 1 + n, cmp); sort(b + 1, b + 1 + n, cmp); for (int i = 1; i <= n; i++) rv[b[i].id] = i; while (Q--) { int x, y; scanf( %d%d , &x, &y); swap(rv[x], rv[y]); b[rv[x]].id = x, b[rv[y]].id = y; for (int i = 1; i <= n; i++) { dp[i] = 0; if (a[i].id ^ b[i].id) dp[i] = max(dp[i], dp[i - 1] + 1ll * a[i].va * b[i].va); if (i > 1) { if ((a[i].id ^ b[i - 1].id) && (a[i - 1].id ^ b[i].id)) { dp[i] = max(dp[i], dp[i - 2] + 1ll * a[i].va * b[i - 1].va + 1ll * a[i - 1].va * b[i].va); } } if (i > 2) { if ((a[i].id ^ b[i - 2].id) && (a[i - 1].id ^ b[i].id) && (a[i - 2].id ^ b[i - 1].id)) { dp[i] = max(dp[i], dp[i - 3] + 1ll * a[i - 2].va * b[i - 1].va + 1ll * a[i - 1].va * b[i].va + 1ll * a[i].va * b[i - 2].va); } if ((a[i - 2].id ^ b[i].id) && (a[i - 1].id ^ b[i - 2].id) && (a[i].id ^ b[i - 1].id)) { dp[i] = max(dp[i], dp[i - 3] + 1ll * a[i - 2].va * b[i].va + 1ll * a[i - 1].va * b[i - 2].va + 1ll * a[i].va * b[i - 1].va); } if ((a[i].id ^ b[i - 2].id) && (a[i - 2].id ^ b[i].id) && (a[i - 1].id ^ b[i - 1].id)) { dp[i] = max(dp[i], dp[i - 3] + 1ll * a[i].va * b[i - 2].va + 1ll * a[i - 1].va * b[i - 1].va + 1ll * a[i - 2].va * b[i].va); } } } printf( %lld n , dp[n]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_4_V
`define SKY130_FD_SC_HS__FA_4_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> x(n); for (long long i = 0; i < n; i++) cin >> x[i]; unordered_map<int, int> m; for (auto num : x) { m[num]++; } if (m.size() < 3) { cout << 0; return 0; } int ans = INT_MAX; for (auto num : m) { if (ans > num.second) { ans = num.second; } } printf( %d n , ans); vector<vector<int>> v(4); for (int i = 0; i < n; i++) { if (x[i] == 1) v[1].push_back(i + 1); if (x[i] == 2) v[2].push_back(i + 1); if (x[i] == 3) v[3].push_back(i + 1); } for (long long i = 0; i < ans; i++) { printf( %d %d %d n , v[1][i], v[2][i], v[3][i]); } return 0; }
|
module cache(clk,rst_n,addr,wr_data,wdirty,we,re,rd_data,tag_out,hit,dirty);
input clk,rst_n;
input [13:0] addr; // address to be read or written, 2-LSB's are dropped
input [63:0] wr_data; // 64-bit cache line to write
input wdirty; // dirty bit to be written
input we; // write enable for cache line
input re; // read enable (for power purposes only)
output hit;
output dirty;
output [63:0] rd_data; // 64-bit/4word cache line read out
output [10:0] tag_out; // 8-bit tag. This is needed during evictions
reg [76:0] mem[0:7]; // {valid,dirty,tag[10:0],wdata[63:0]}
reg [3:0] x;
reg [76:0] line;
reg we_del;
wire we_filt;
//////////////////////////
// Glitch filter on we //
////////////////////////
always @(we)
we_del <= we;
assign we_filt = we & we_del;
///////////////////////////////////////////////////////
// Model cache write, including reset of valid bits //
/////////////////////////////////////////////////////
always @(clk or we_filt or negedge rst_n)
if (!rst_n)
for (x=0; x<8; x = x + 1)
mem[x] = {2'b00,{75{1'bx}}}; // only valid & dirty bit are cleared, all others are x
else if (~clk && we_filt)
mem[addr[2:0]] = {1'b1,wdirty,addr[13:3],wr_data};
////////////////////////////////////////////////////////////
// Model cache read including 4:1 muxing of 16-bit words //
//////////////////////////////////////////////////////////
always @(clk or re or addr)
if (clk && re) // read is on clock high
line = mem[addr[2:0]];
/////////////////////////////////////////////////////////////
// If tag bits match and line is valid then we have a hit //
///////////////////////////////////////////////////////////
assign hit = ((line[74:64]==addr[13:3]) && (re | we)) ? line[76] : 1'b0;
assign dirty = line[76]&line[75]; // if line is valid and dirty bit set
assign rd_data = line[63:0];
assign tag_out = line[74:64]; // need the tag for evictions
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 1-Bit Look-Up Table
// /___/ /\ Filename : LUT1.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/12/11 - Initial version.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 09/12/16 - ANSI ports, speed improvements
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`celldefine
module LUT1 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [1:0] INIT = 2'h0
)(
output O,
input I0
);
// define constants
localparam MODULE_NAME = "LUT1";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "LUT1_dr.v"
`else
reg [1:0] INIT_REG = INIT;
`endif
x_lut1_mux2 (O, INIT_REG[1], INIT_REG[0], I0);
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
primitive x_lut1_mux2 (o, d1, d0, s0);
output o;
input d1, d0;
input s0;
table
// d1 d0 s0 : o;
? 1 0 : 1;
? 0 0 : 0;
1 ? 1 : 1;
0 ? 1 : 0;
0 0 x : 0;
1 1 x : 1;
endtable
endprimitive
|
#include <bits/stdc++.h> using namespace std; long long int f(long long int a) { long long int i, r = 0; for (i = 1; i <= a; i++) { r += i * (9 * (pow(10, i - 1))); } return r; } int main() { long long int i, n, a; cin >> n; for (i = 1; n % (long long int)(pow(10, i)) != n; i++) ; a = f(i - 1); n = n - (pow(10, i - 1)); a = a + ((n + 1) * (i)); cout << a; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_1_V
`define SKY130_FD_SC_HS__HA_1_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_1_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus slave interface - one cycle read delay
*
*/
module rcn_slave
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
output cs,
output wr,
output [3:0] mask,
output [23:0] addr,
output [31:0] wdata,
input [31:0] rdata
);
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] rin;
reg [68:0] rin_d1;
reg [68:0] rout;
assign rcn_out = rout;
wire [23:0] my_mask = ADDR_MASK;
wire [23:0] my_base = ADDR_BASE;
wire my_req = rin[68] && rin[67] && ((rin[55:34] & my_mask[23:2]) == my_base[23:2]);
reg my_req_d1;
wire [68:0] resp;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rin_d1 <= 69'd0;
my_req_d1 <= 1'b0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rin_d1 <= rin;
my_req_d1 <= my_req;
rout <= (my_req_d1) ? resp : rin_d1;
end
assign cs = my_req;
assign wr = rin[66];
assign mask = rin[59:56];
assign addr = {rin[55:34], 2'd0};
assign wdata = rin[31:0];
assign resp = {1'b1, 1'b0, rin_d1[66:32], rdata};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, ans, num; scanf( %d , &n); for (int i = 17; i >= 1; i--) { num = (pow(2, i) - 1) * pow(2, i - 1); if (n % num == 0) { ans = num; break; } } printf( %d n , ans); }
|
`include "common.vh"
`timescale 1ns/10ps
module TwoPortRAM(
clka, ena, wea, clkb, enb, web, acka, ackb,
addra, dina, douta, addrb, dinb, doutb
);
parameter INIT = 0;
parameter ZERO = 0;
parameter LOADH = 0;
parameter LOADB = 0;
parameter LOADFILE = "default.memh";
parameter PBITS = 32; // port address bits
parameter ABITS = 10; // internal address bits
parameter DBITS = 32;
parameter SIZE = 1 << ABITS;
parameter OFFSET = 0;
input wire clka, ena, wea, clkb, enb, web;
output reg acka, ackb;
input wire[PBITS-1:0] addra, addrb;
input wire[DBITS-1:0] dina , dinb;
output reg [DBITS-1:0] douta, doutb;
reg[DBITS-1:0] store[0:SIZE - 1];
integer i;
initial begin
if (INIT)
for (i = 0; i < SIZE; i = i + 1)
store[i] = ZERO;
if (LOADH) $readmemh(LOADFILE, store);
if (LOADB) $readmemb(LOADFILE, store);
end
always @(posedge clka) begin
douta = store[addra - OFFSET];
if (wea && ena)
store[addra - OFFSET] = dina;
acka = ena;
end
always @(posedge clkb) begin
doutb = store[addrb - OFFSET];
if (web && enb)
store[addrb - OFFSET] = dinb;
ackb = enb;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 10; int n, m, cnt, counter, b[maxn * maxn], par[maxn][maxn]; char a[maxn][maxn]; vector<pair<int, int> > adj[maxn][maxn]; bool mark[maxn][maxn]; void dfs(int x, int y) { mark[x][y] = true; par[x][y] = cnt; counter++; for (int i = 0; i < adj[x][y].size(); i++) { int x1 = adj[x][y][i].first; int y1 = adj[x][y][i].second; if (!mark[x1][y1]) dfs(x1, y1); } } int f(int x, int y) { int A[4] = {0}; if (x != 0 && a[x - 1][y] == . ) A[0] = par[x - 1][y]; if (x != n - 1 && a[x + 1][y] == . ) A[1] = par[x + 1][y]; if (y != 0 && a[x][y - 1] == . ) A[2] = par[x][y - 1]; if (y != m - 1 && a[x][y + 1] == . ) A[3] = par[x][y + 1]; for (int i = 0; i < 4; i++) for (int j = i + 1; j < 4; j++) if (A[i] == A[j]) A[j] = 0; int ans = 0; if (x != 0) ans += b[A[0]]; if (x != n - 1) ans += b[A[1]]; if (y != 0) ans += b[A[2]]; if (y != m - 1) ans += b[A[3]]; ans++; ans %= 10; return ans; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (a[i][j] == . ) { if (i != 0) if (a[i - 1][j] == . ) adj[i][j].push_back(pair<int, int>(i - 1, j)); if (i != n - 1) if (a[i + 1][j] == . ) adj[i][j].push_back(pair<int, int>(i + 1, j)); if (j != 0) if (a[i][j - 1] == . ) adj[i][j].push_back(pair<int, int>(i, j - 1)); if (j != m - 1) if (a[i][j + 1] == . ) adj[i][j].push_back(pair<int, int>(i, j + 1)); } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (!mark[i][j]) { counter = 0; cnt++; dfs(i, j); b[cnt] = counter; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . ) printf( . ); else { printf( %d , f(i, j)); } } printf( n ); } }
|
#include <bits/stdc++.h> using namespace std; int a[512]; int main() { int n, t; scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); vector<int> ans; for (int i = 1; i <= n; i++) { for (int j = 1; j < n - 1; j++) { if (a[j] > a[j + 1]) { swap(a[j], a[j + 2]); swap(a[j], a[j + 1]); ans.emplace_back(j); ans.emplace_back(j); } else if (a[j + 1] > a[j + 2]) { swap(a[j], a[j + 1]); swap(a[j], a[j + 2]); ans.emplace_back(j); } } } int i; for (i = 2; i <= n; i++) if (a[i] < a[i - 1]) break; if (i <= n) printf( -1 n ); else { printf( %d n , ans.size()); for (int x : ans) printf( %d , x); ; printf( n ); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFSTP_PP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> enum { MAXN = 102 }; int reverse[MAXN], target[MAXN], init[MAXN]; int n; int eq(int *a, int *b) { int i; for (i = 1; i <= n; i++) if (a[i] != b[i]) return 0; return 1; } void proc(int *a, int *b) { int ans[MAXN], i; for (i = 1; i <= n; i++) { ans[i] = a[b[i]]; } for (i = 1; i <= n; i++) a[i] = ans[i]; } void print(int *a) { int i; for (i = 1; i <= n; i++) printf( %d , a[i]); puts( ); } int main(void) { int k, m1, m2, i; scanf( %d %d , &n, &k); for (i = 1; i <= n; i++) { scanf( %d , init + i); reverse[init[i]] = i; } for (i = 1; i <= n; i++) scanf( %d , target + i); int natur[MAXN]; for (i = 1; i <= n; i++) natur[i] = i; m1 = 0; m2 = 0; while (m1 < 1000 && !eq(natur, target)) { proc(natur, init); m1++; } if (!eq(natur, target)) m1 = -1; for (i = 1; i <= n; i++) natur[i] = i; while (m2 < 1000 && !eq(natur, target)) { proc(natur, reverse); m2++; } if (!eq(natur, target)) m2 = -1; char *ans = NO ; if (m1 == 1 && m2 == 1) { if (k == 1) ans = YES ; } else if (m1 == 1 || m2 == 1) { if (k % 2 == 1) ans = YES ; } if (m1 > 1 && (k - m1) >= 0 && (k - m1) % 2 == 0) ans = YES ; if (m2 > 1 && (k - m2) >= 0 && (k - m2) % 2 == 0) ans = YES ; puts(ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_BEHAVIORAL_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is EQUAL TO the actual rate, no more -1 BS
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd1 : bitgain = 0;
8'd2 : bitgain = 4;
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd3 : bitgain = 7;
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd0 : signal_out = signal_in[0+bw-1:0];
5'd4 : signal_out = signal_in[4+bw-1:4];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100005; int n; unordered_map<int, int> bit[MAX]; unordered_map<int, int> idx; int inf = 1000000001; void update(int pos, int t, int val) { for (; t < inf; t += (t & -t)) { bit[pos][t] += val; } } int get(int pos, int t) { int ans = 0; for (; t > 0; t -= (t & -t)) ans += bit[pos][t]; return ans; } int main() { int type, t, x; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d %d %d , &type, &t, &x); if (!idx.count(x)) idx[x] = i; int cur = idx[x]; if (type == 1) { update(idx[x], t, 1); } if (type == 2) { update(idx[x], t, -1); } if (type == 3) { int ans = get(idx[x], t); printf( %d n , ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v); template <typename A, typename B> ostream &operator<<(ostream &cout, pair<A, B> const &p) { return cout << ( << p.first << , << p.second << ) ; } template <typename A> ostream &operator<<(ostream &cout, vector<A> const &v) { cout << [ ; for (int i = 0; i < v.size(); i++) { if (i) cout << , ; cout << v[i]; } return cout << ] ; } template <typename A, typename B> istream &operator>>(istream &cin, pair<A, B> &p) { cin >> p.first; return cin >> p.second; } mt19937_64 rng(61378913); void usaco(string filename) { freopen((filename + .in ).c_str(), r , stdin); freopen((filename + .out ).c_str(), w , stdout); } const long double pi = 3.14159265358979323846; long long n, m, k, q, l, r, x, y, z; const long long template_array_size = 1e6 + 8432; long long a[template_array_size]; long long b[template_array_size]; long long c[template_array_size]; string second, t; long long ans = 0; void solve(int tc = 0) { bool dead[10] = {0}; long long v = 0; cin >> n; for (long long i = 0; i < n; i++) { char c; cin >> c >> x; if (c == | ) { for (long long j = 0; j < 10; j++) { if (x & (1 << j)) dead[j] = 1; } v |= x; } else if (c == & ) { for (long long j = 0; j < 10; j++) { if (!(x & (1 << j))) dead[j] = 1; } v &= x; } else { v ^= x; } } long long ov = 0; for (long long i = 0; i < 10; i++) { if (!dead[i]) ov += (1 << i); } cout << 2 << n ; cout << & << ov << n ; cout << ^ << v << n ; } int main() { { ios_base::sync_with_stdio(false); } { cin.tie(NULL); } cout << setprecision(12) << fixed; int tc = 1; for (int t = 0; t < tc; t++) solve(t); }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; int vis[200005]; int comp_size; int cycle_length; void dfs(int cur, int prev, int t, vector<vector<int>> &edges) { vis[cur] = t; comp_size++; for (int e : edges[cur]) { if (vis[e] == -1) { dfs(e, cur, t + 1, edges); } else if (e != prev) { if (cycle_length == 0) cycle_length = t - vis[e] + 1; } } } long long mod_exp(int a, int b) { if (b == 0) { return 1; } else if (b == 1) { return a; } long long c; if (b % 2 == 0) { c = mod_exp(a, b / 2); c = c * c % MOD; } else { c = mod_exp(a, (b - 1) / 2); c = c * c * a % MOD; } return c; } int main() { int n; memset(vis, -1, sizeof vis); cin >> n; vector<vector<int>> edges(n); for (int i = 0; i < n; i++) { int a; cin >> a; a--; edges[i].push_back(a); edges[a].push_back(i); } long long ans = 1; for (int i = 0; i < n; i++) { if (vis[i] == -1) { comp_size = 0; cycle_length = 0; dfs(i, -1, 1, edges); cycle_length = cycle_length == 0 ? 2 : cycle_length; ans = (ans * mod_exp(2, comp_size - cycle_length) % MOD) * (mod_exp(2, cycle_length) - 2) % MOD; } } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_TB_V
`define SKY130_FD_SC_MS__CONB_TB_V
/**
* conb: Constant value, low, high outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__conb.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire HI;
wire LO;
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__conb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .HI(HI), .LO(LO));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; int n, k, now, last; long long dp[2][505][505], sum[505], ans = 0, s; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> k; memset(dp[1], 0, sizeof dp[1]); dp[1][1][1] = 1; for (int i = 2; i <= n; i++) { now = i & 1; last = now ^ 1; memset(dp[now], 0, sizeof dp[now]); for (int j = 1; j < i; j++) { for (int k = 1; k < i; k++) { if (j != k) dp[now][j][k + 1] = (dp[now][j][k + 1] + dp[last][j][k]) % mod; else dp[now][j + 1][k + 1] = (dp[now][j + 1][k + 1] + dp[last][j][k]) % mod; dp[now][j][1] = (dp[now][j][1] + dp[last][j][k]) % mod; } } } memset(sum, 0, sizeof sum); for (int i = 1; i <= n; i++) for (int j = 1; j <= i; j++) sum[i] = (sum[i] + dp[now][i][j]) % mod; s = 0; for (int i = 1; i <= n; i++) s = (s + sum[i]) % mod; int t = n; for (int i = 1; i <= n; i++) { while (t * i >= k) { s = (s - sum[t] + mod) % mod; t--; } ans = (ans + sum[i] * s % mod) % mod; } ans = ans * 2 % mod; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, jump[100005]; bool visited[100005]; string s; cin >> n; cin >> s; for (int i = 0; i < n; i++) cin >> jump[i]; int pos = 0; fill(visited, visited + n, false); while (!visited[pos]) { visited[pos] = true; if (s[pos] == > ) pos += jump[pos]; else if (s[pos] == < ) pos -= jump[pos]; if (pos < 0 || pos >= n) { cout << FINITE << endl; return 0; } } cout << INFINITE << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
by_width #(1) w1 (.clk(clk));
by_width #(31) w31 (.clk(clk));
by_width #(32) w32 (.clk(clk));
by_width #(33) w33 (.clk(clk));
by_width #(63) w63 (.clk(clk));
by_width #(64) w64 (.clk(clk));
by_width #(65) w65 (.clk(clk));
by_width #(95) w95 (.clk(clk));
by_width #(96) w96 (.clk(clk));
by_width #(97) w97 (.clk(clk));
reg signed [15:0] a;
reg signed [4:0] b;
reg signed [15:0] sr,srs,sl,sls;
reg [15:0] b_s;
reg [15:0] b_us;
task check_s(input signed [7:0] i, input [7:0] expval);
//$display("check_s %x\n", i);
if (i !== expval) $stop;
endtask
task check_us(input signed [7:0] i, input [7:0] expval);
//$display("check_us %x\n", i);
if (i !== expval) $stop;
endtask
always @* begin
sr = a>>b;
srs = copy_signed(a)>>>b;
sl = a<<b;
sls = a<<<b;
// verilator lint_off WIDTH
b_s = b>>>4; // Signed
b_us = b[4:0]>>>4; // Unsigned, due to extract
check_s ( 3'b111, 8'h07);
check_s (3'sb111, 8'hff);
check_us( 3'b111, 8'h07);
check_us(3'sb111, 8'hff); // Note we sign extend ignoring function's input requirements
// verilator lint_on WIDTH
end
reg signed [32:0] bug349;
initial
begin
end
integer i;
initial begin
if ((-1 >>> 3) != -1) $stop; // Decimals are signed
// verilator lint_off WIDTH
if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned
if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers
// verilator lint_on WIDTH
if ( (3'sb000 > 3'sb000)) $stop;
if (!(3'sb000 > 3'sb111)) $stop;
if ( (3'sb111 > 3'sb000)) $stop;
if ( (3'sb000 < 3'sb000)) $stop;
if ( (3'sb000 < 3'sb111)) $stop;
if (!(3'sb111 < 3'sb000)) $stop;
if (!(3'sb000 >= 3'sb000)) $stop;
if (!(3'sb000 >= 3'sb111)) $stop;
if ( (3'sb111 >= 3'sb000)) $stop;
if (!(3'sb000 <= 3'sb000)) $stop;
if ( (3'sb000 <= 3'sb111)) $stop;
if (!(3'sb111 <= 3'sb000)) $stop;
// When we multiply overflow, the sign bit stays correct.
if ( (4'sd2*4'sd8) != 4'd0) $stop;
// From the spec:
// verilator lint_off WIDTH
i = -12 /3; if (i !== 32'hfffffffc) $stop;
i = -'d12 /3; if (i !== 32'h55555551) $stop;
i = -'sd12 /3; if (i !== 32'hfffffffc) $stop;
i = -4'sd12 /3; if (i !== 32'h00000001) $stop;
// verilator lint_on WIDTH
// verilator lint_off WIDTH
bug349 = 4'sb1111 - 1'b1;
if (bug349 != 32'he) $stop;
end
function signed [15:0] copy_signed;
input [15:0] ai;
copy_signed = ai;
endfunction
integer cyc; initial cyc=0;
wire [31:0] ucyc = cyc;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us);
`endif
case (cyc)
0: begin
a <= 16'sh8b1b; b <= 5'sh1f; // -1
end
1: begin
// Check spaces in constants
a <= 16 'sh 8b1b; b <= 5'sh01; // -1
end
2: begin
a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned
if (ucyc / 1 != 32'd2) $stop;
if (ucyc / 2 != 32'd1) $stop;
if (ucyc * 1 != 32'd2) $stop;
if (ucyc * 2 != 32'd4) $stop;
if (ucyc * 3 != 32'd6) $stop;
if (cyc * 32'sd1 != 32'sd2) $stop;
if (cyc * 32'sd2 != 32'sd4) $stop;
if (cyc * 32'sd3 != 32'sd6) $stop;
end
3: begin
a <= 16'sh0048; b <= 5'sh1f;
if (ucyc * 1 != 32'd3) $stop;
if (ucyc * 2 != 32'd6) $stop;
if (ucyc * 3 != 32'd9) $stop;
if (ucyc * 4 != 32'd12) $stop;
if (cyc * 32'sd1 != 32'sd3) $stop;
if (cyc * 32'sd2 != 32'sd6) $stop;
if (cyc * 32'sd3 != 32'sd9) $stop;
end
4: begin
a <= 16'sh4154; b <= 5'sh02;
end
5: begin
a <= 16'shc3e8; b <= 5'sh12;
end
6: begin
a <= 16'sh488b; b <= 5'sh02;
end
9: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
case (cyc)
0: ;
1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop;
3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop;
5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop;
6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop;
7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop;
8: ;
9: ;
endcase
end
endmodule
module by_width (
input clk
);
parameter WIDTH=1;
reg signed i1;
reg signed [62:0] i63;
reg signed [64:0] i65;
// verilator lint_off WIDTH
wire signed [WIDTH-1:0] i1extp /*verilator public*/ = i1;
wire signed [WIDTH-1:0] i1ext = i1;
wire signed [WIDTH-1:0] i63ext = i63;
wire signed [WIDTH-1:0] i65ext = i65;
// verilator lint_on WIDTH
integer cyc; initial cyc=0;
always @ (posedge clk) begin
cyc <= cyc + 1;
i1 <= cyc[0];
i63 <= {63{cyc[0]}};
i65 <= {65{cyc[0]}};
case (cyc)
1: begin
if (i1extp != {WIDTH{1'b0}}) $stop;
if (i1ext != {WIDTH{1'b0}}) $stop;
if (i63ext != {WIDTH{1'b0}}) $stop;
if (i65ext != {WIDTH{1'b0}}) $stop;
end
2: begin
if (i1extp != {WIDTH{1'b1}}) $stop;
if (i1ext != {WIDTH{1'b1}}) $stop;
if (i63ext != {WIDTH{1'b1}}) $stop;
if (i65ext != {WIDTH{1'b1}}) $stop;
end
default: ;
endcase
end
endmodule
|
// file: clk_200_400_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module clk_200_400_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf
(.O (clk_in1_buf),
.I (CLK_IN1));
// Instantiation of the clocking network
//--------------------------------------
clk_200_400 clknetwork
(// Clock in ports
.CLK_IN1 (clk_in1_buf),
// Clock out ports
.CLK_OUT1 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end
else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ { C_W { 1'b 0 } };
end else begin
counter <= #TCQ counter + 1'b 1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
|
#include <bits/stdc++.h> using namespace std; int aa(int n) { int a = 0; for (int i = 2; i <= n - 1; i++) if (n % i == 0) { a = 1; break; } else a = 0; return a; } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { if (aa(i) == 1 && aa(n - i) == 1) { cout << i << << n - i << endl; break; } } }
|
#include <bits/stdc++.h> using namespace std; class trio { public: long long first, second, third; }; long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long modInverse(long long a, long long m) { long long x, y; long long g = gcdExtended(a, m, &x, &y); long long res = (x % m + m) % m; return res; } long long power(long long x, long long y) { long long ans = 1, second = x; while (y) { if (y & 1) { ans *= second; ans %= 1000000007; } second *= second; second %= 1000000007; y >>= 1; } return ans; } const long long N = 51; long long dp1[N]; long long dp3[N]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; __int128 val = 1; dp1[0] = 1; dp1[1] = 1; dp1[2] = 1; for (long long i = 3; i < N; ++i) { val *= (i - 2); val = min(val, (__int128)1000000000000000001); dp1[i] = val; } dp3[0] = 1; dp3[1] = 1; for (long long i = 2; i < N; ++i) { val = 0; for (long long j = 1; j < i + 1; ++j) { val += (__int128)dp3[i - j] * dp1[j]; val = min(val, (__int128)1000000000000000001); } dp3[i] = val; } long long third; cin >> third; while (third--) { long long n, k; cin >> n >> k; long long arr[N] = {0}; if (dp3[n] < k) { cout << -1 << n ; continue; } for (long long i = 1; i <= n;) { long long len, left, st; __int128 count; for (long long j = i; j <= n; ++j) { len = j - i + 1; left = n - i - len + 1; st = j; count = (__int128)dp1[len] * dp3[left]; count = min(count, (__int128)1000000000000000001); if (count < k) { k -= (count); } else { break; } } arr[i] = st; set<long long> available; for (long long j = i; j < i + len; ++j) { available.insert(j); } available.erase(st); for (long long j = i + 1; j < i + len; ++j) { if (j == i + len - 1) { arr[j] = *(available.begin()); break; } for (auto it : available) { long long cur = it; while (cur != j && cur) { cur = arr[cur]; } if (cur == j) continue; count = (__int128)dp1[len - (j - i)] * dp3[left]; count = min(count, (__int128)1000000000000000001); if (count < k) { k -= (count); } else { arr[j] = it; break; } } available.erase(arr[j]); } i += len; } for (long long i = 1; i < n + 1; ++i) { cout << arr[i] << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; map<int, bool> childL, childR; int main() { ios::sync_with_stdio(false); cin.tie(0); ; int n, a; cin >> n; cin >> a; multiset<int> mulset; mulset.insert(a); for (int i = 1; i < n; i++) { cin >> a; auto ite = mulset.lower_bound(a); if (childL[*ite] || ite == mulset.end()) { ite--; childR[*ite] = 1; } else childL[*ite] = 1; if (i > 1) cout << ; cout << *ite; mulset.insert(a); } cout << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_2_V
`define SKY130_FD_SC_HS__EINVP_2_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_2 (
A ,
TE ,
Z ,
VPWR,
VGND
);
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__einvp_2 (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_2_V
|
#include <bits/stdc++.h> using namespace std; inline int read() { register int x = 0; register bool f = 0; register char ch = getchar(); while (!isdigit(ch)) { f ^= !(ch ^ - ); ch = getchar(); } while (isdigit(ch)) { x = ((x + (x << 2)) << 1) + (ch ^ 0 ); ch = getchar(); } return f ? -x : x; } inline void print(int x) { register int sc[30] = {0}, tot = 0; do { sc[++tot] = x % 10; x /= 10; } while (x); while (tot) putchar( 0 + sc[tot--]); } int n, maxn, k, ans; int peo[510 * 510], tot[510 * 510], h[510]; int dp[5010][5010]; int main() { n = read(); k = read(); for (register int i = 1; i <= n * k; i++) { int tmp = read(); tot[tmp]++; maxn = max(maxn, tmp); } for (register int i = 1; i <= n; i++) { int tmp = read(); peo[tmp]++; } for (register int i = 1; i <= k; i++) h[i] = read(); for (register int i = 1; i <= n; i++) for (register int j = 1; j <= n * k; j++) for (register int l = 1; l <= min(j, k); l++) dp[i][j] = max(dp[i][j], dp[i - 1][j - l] + h[l]); for (register int i = 1; i <= maxn; i++) if (peo[i]) ans += dp[peo[i]][tot[i]]; printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_8_V
`define SKY130_FD_SC_HDLL__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_8_V
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j; int n; scanf( %d , &n); if ((n * n) % 2 == 1) { printf( %d n , ((n * n) / 2) + 1); } else { printf( %d n , (n * n) / 2); } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if ((i + j) % 2 == 0) { printf( C ); } else { printf( . ); } } printf( n ); } return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:00:00 11/10/2015
// Design Name: clk_generator
// Module Name: C:/WINDOWS/system32/Timer/gen_clk_tst.v
// Project Name: Timer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clk_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module gen_clk_tst;
// Inputs
reg clk;
reg rst;
reg en;
reg [31:0] limit;
wire [31:0] count;
// Outputs
wire clk_0;
// Instantiate the Unit Under Test (UUT)
clk_generator uut (
.clk(clk),
.en(en),
.limit(limit),
.count(count),
.clk_0(clk_0)
);
clk_counter counter(
.clk(clk),
.en(en),
.rst(rst),
.count(count)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
en = 0;
limit = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
limit = 32'h000000FF;
#100;
en = 1;
end
always #5 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a, b; vector<vector<int> > adj; vector<int> col; queue<int> x, y; void colorear(int u, int c) { col[u] = c; for (int v : adj[u]) if (col[v] == -1) colorear(v, 1 - c); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; adj = vector<vector<int> >(2 * n + 2); for (int i = 0; i < n; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); x.push(a); y.push(b); if (a % 2) { adj[a].push_back(a + 1); adj[a + 1].push_back(a); } if (b % 2) { adj[b].push_back(b + 1); adj[b + 1].push_back(b); } } col = vector<int>(2 * n + 2, -1); for (int i = 1; i <= 2 * n; i++) { if (col[i] == -1) { colorear(i, 0); } } while (n--) { cout << col[x.front()] + 1 << << col[y.front()] + 1 << n ; x.pop(); y.pop(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ct[300005]; vector<pair<int, int> > val; int n, m; bool check(int vl) { for (int i = 0; i < 300005; i++) ct[i] = 0; int count = 0; for (int i = 0; i < m; i++) { if (vl != val[i].first && vl != val[i].second) { count++; ct[val[i].first]++; if (val[i].second != val[i].first) { ct[val[i].second]++; } } } if (count == 0) return true; for (int i = 1; i < 300001; i++) { if (ct[i] == count) { return true; } } return false; } int main() { cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; val.push_back(make_pair(a, b)); } int first = val[0].first; int second = val[0].second; if (check(first)) { cout << YES n ; } else if (check(second)) { cout << YES n ; } else { cout << NO n ; } }
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* RGMII PHY interface
*/
module rgmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-6, 7-series
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
parameter CLOCK_INPUT_STYLE = "BUFG",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE"
)
(
input wire clk,
input wire clk90,
input wire rst,
/*
* GMII interface to MAC
*/
output wire mac_gmii_rx_clk,
output wire mac_gmii_rx_rst,
output wire [7:0] mac_gmii_rxd,
output wire mac_gmii_rx_dv,
output wire mac_gmii_rx_er,
output wire mac_gmii_tx_clk,
output wire mac_gmii_tx_rst,
output wire mac_gmii_tx_clk_en,
input wire [7:0] mac_gmii_txd,
input wire mac_gmii_tx_en,
input wire mac_gmii_tx_er,
/*
* RGMII interface to PHY
*/
input wire phy_rgmii_rx_clk,
input wire [3:0] phy_rgmii_rxd,
input wire phy_rgmii_rx_ctl,
output wire phy_rgmii_tx_clk,
output wire [3:0] phy_rgmii_txd,
output wire phy_rgmii_tx_ctl,
/*
* Control
*/
input wire [1:0] speed
);
// receive
wire rgmii_rx_ctl_1;
wire rgmii_rx_ctl_2;
ssio_ddr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(5)
)
rx_ssio_ddr_inst (
.input_clk(phy_rgmii_rx_clk),
.input_d({phy_rgmii_rxd, phy_rgmii_rx_ctl}),
.output_clk(mac_gmii_rx_clk),
.output_q1({mac_gmii_rxd[3:0], rgmii_rx_ctl_1}),
.output_q2({mac_gmii_rxd[7:4], rgmii_rx_ctl_2})
);
assign mac_gmii_rx_dv = rgmii_rx_ctl_1;
assign mac_gmii_rx_er = rgmii_rx_ctl_1 ^ rgmii_rx_ctl_2;
// transmit
reg rgmii_tx_clk_1 = 1'b1;
reg rgmii_tx_clk_2 = 1'b0;
reg rgmii_tx_clk_rise = 1'b1;
reg rgmii_tx_clk_fall = 1'b1;
reg [5:0] count_reg = 6'd0, count_next;
always @(posedge clk) begin
if (rst) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_rise <= 1'b1;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end else begin
rgmii_tx_clk_1 <= rgmii_tx_clk_2;
if (speed == 2'b00) begin
// 10M
count_reg <= count_reg + 1;
rgmii_tx_clk_rise <= 1'b0;
rgmii_tx_clk_fall <= 1'b0;
if (count_reg == 24) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b1;
rgmii_tx_clk_rise <= 1'b1;
end else if (count_reg >= 49) begin
rgmii_tx_clk_1 <= 1'b0;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end
end else if (speed == 2'b01) begin
// 100M
count_reg <= count_reg + 1;
rgmii_tx_clk_rise <= 1'b0;
rgmii_tx_clk_fall <= 1'b0;
if (count_reg == 2) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b1;
rgmii_tx_clk_rise <= 1'b1;
end else if (count_reg >= 4) begin
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end
end else begin
// 1000M
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_rise <= 1'b1;
rgmii_tx_clk_fall <= 1'b1;
end
end
end
reg [3:0] rgmii_txd_1 = 0;
reg [3:0] rgmii_txd_2 = 0;
reg rgmii_tx_ctl_1 = 1'b0;
reg rgmii_tx_ctl_2 = 1'b0;
reg gmii_clk_en = 1'b1;
always @* begin
if (speed == 2'b00) begin
// 10M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[3:0];
if (rgmii_tx_clk_2) begin
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en;
end else begin
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
end
gmii_clk_en = rgmii_tx_clk_fall;
end else if (speed == 2'b01) begin
// 100M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[3:0];
if (rgmii_tx_clk_2) begin
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en;
end else begin
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
end
gmii_clk_en = rgmii_tx_clk_fall;
end else begin
// 1000M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[7:4];
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
gmii_clk_en = 1;
end
end
wire phy_rgmii_tx_clk_new;
wire [3:0] phy_rgmii_txd_new;
wire phy_rgmii_tx_ctl_new;
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(USE_CLK90 == "TRUE" ? clk90 : clk),
.d1(rgmii_tx_clk_1),
.d2(rgmii_tx_clk_2),
.q(phy_rgmii_tx_clk)
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(5)
)
data_oddr_inst (
.clk(clk),
.d1({rgmii_txd_1, rgmii_tx_ctl_1}),
.d2({rgmii_txd_2, rgmii_tx_ctl_2}),
.q({phy_rgmii_txd, phy_rgmii_tx_ctl})
);
assign mac_gmii_tx_clk = clk;
assign mac_gmii_tx_clk_en = gmii_clk_en;
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_gmii_tx_rst = tx_rst_reg[0];
always @(posedge mac_gmii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_gmii_rx_rst = rx_rst_reg[0];
always @(posedge mac_gmii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule
`resetall
|
///////////////////////////////////////////////////////////////////
//=================================================================
// Copyright(c) Superion Technology Group Inc., 2015
// ALL RIGHTS RESERVED
// $Id: $
//=================================================================
//
// File name: : xlr8_fdiv.v
// Author : Steve Berg
// Description : Floating point divide unit.
//
//=================================================================
///////////////////////////////////////////////////////////////////
module xlr8_fdiv
#(parameter DENOM_W = 32,
parameter NUMER_W = 32,
parameter EXP_W = 8,
parameter FRAC_W = 23,
parameter QUOTI_W = 32,
parameter REMAI_W = DENOM_W)
(input logic clk,
input logic rst_n,
input logic clken,
input logic [DENOM_W-1:0] denom,
input logic [NUMER_W-1:0] numer,
input logic start, // start a new divide
output logic [QUOTI_W-1:0] q_out
// output logic [REMAI_W-1:0] remain, // FIXME: unused
// output logic quotient_val // result valid: one shot
);
localparam MANT_W = FRAC_W+1;
localparam QUO_W = MANT_W+3;
localparam CNT_W = $clog2(MANT_W+1);
// need to do full width subtracts
// localparam SUB_W = DIVISOR_W > NUMER_W ? DIVISOR_W : NUMER_W;
localparam SUB_W = 28; //MANT_W+1;
logic sign;
logic [EXP_W-1:0] exp_q;
logic [EXP_W-1:0] temp_exp;
logic [EXP_W-1:0] exp_numer;
logic [EXP_W-1:0] exp_denom;
logic [FRAC_W-1:0] frac_numer;
logic [FRAC_W-1:0] frac_denom;
logic [MANT_W-1:0] mant_numer;
logic [MANT_W-1:0] mant_denom;
logic [MANT_W-1:0] mant_q;
logic exp_numer_0;
logic exp_denom_0;
logic exp_numer_255;
logic exp_denom_255;
logic frac_numer_0;
logic frac_denom_0;
logic numer_nan;
logic denom_nan;
logic numer_inf;
logic denom_inf;
logic numer_0;
logic denom_0;
logic [CNT_W-1:0] cnt;
logic [CNT_W-1:0] cnt_nxt;
logic [MANT_W:0] q_rnd;
// logic [MANT_W-1:0] quotient_nxt;
logic [QUO_W:0] quotient;
logic [QUO_W:0] quotient_nxt;
logic bsy;
logic [MANT_W-1:0] divisor, divisor_nxt;
logic [MANT_W:0] dividend, dividend_nxt, dividend_mux;
logic quotient_val; // result valid: one shot
logic [QUO_W:0] q_adjst;
logic [EXP_W-1:0] exp_adjst;
assign exp_numer = numer[23 +: EXP_W];
assign exp_denom = denom[23 +: EXP_W];
assign frac_numer = numer[FRAC_W-1:0];
assign frac_denom = denom[FRAC_W-1:0];
assign mant_numer = {1'b1,numer[FRAC_W-1:0]};
assign mant_denom = {1'b1,denom[FRAC_W-1:0]};
//calculate and hold sign and exp for result
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
sign <= 1'b0;
temp_exp <= 8'h0;
end
else begin
sign <= numer[31]^denom[31]; //sign - calculate and hold
temp_exp <= exp_numer - exp_denom + 'd127; //result exponent
end
always_comb begin
exp_numer_0 = exp_numer == 0;
exp_denom_0 = exp_denom == 0;
exp_numer_255 = exp_numer == 8'hff;
exp_denom_255 = exp_denom == 8'hff;
frac_numer_0 = frac_numer == 0;
frac_denom_0 = frac_denom == 0;
numer_nan = (exp_numer_255) && !frac_numer_0;
denom_nan = (exp_denom_255) && !frac_denom_0;
numer_inf = (exp_numer_255) && frac_numer_0;
denom_inf = (exp_denom_255) && frac_denom_0;
numer_0 = exp_numer_0;
denom_0 = exp_denom_0;
end
// figure out special cases up front
// assuming no denormals! If exp of operand is zero, then input is zero
always_comb begin
// nan: divide by 0, either input is NAN, both inputs==0, both inputs==inf
if (numer_nan || denom_nan || (numer_0 && denom_0) || (numer_inf && denom_inf)) begin
q_out = 32'h7fffffff;
end
// inf
else if (numer_inf || denom_0) begin
q_out = {sign,8'hff,23'h0};
end
// zero
else if (numer_0 || denom_inf) begin
q_out = {sign,31'h0};
end
else begin
// q_out = {sign,exp_q,mant_q[FRAC_W-1:0]};
q_out = {sign,exp_adjst,q_rnd[FRAC_W-1:0]};
end
end // always_comb
logic [23:0] rslt;
logic brw; // borrow bit
always_comb begin: calc_nxt
{brw,rslt} = dividend - divisor;
dividend_mux = brw ? dividend : rslt;
dividend_nxt = dividend_mux << 1;
quotient_nxt = (brw) ? {quotient[26:0],1'b0} : {quotient[26:0],1'b1};
divisor_nxt = divisor;
cnt_nxt = cnt - 'd1;
bsy = |cnt;
end
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
cnt <= {CNT_W{1'b0}};
dividend <= {25{1'b0}};
divisor <= {MANT_W{1'b0}};
quotient <= {QUO_W{1'b0}};
// End of automatics
end
else begin
if (clken) begin
cnt <= start && !bsy ? SUB_W :
bsy ? cnt_nxt : cnt;
divisor <= start && !bsy ? mant_denom :
bsy ? divisor_nxt :
divisor;
dividend <= start && !bsy ? {1'b0, mant_numer} :
bsy ? dividend_nxt :
dividend;
quotient <= start && !bsy ? '0 :
bsy ? quotient_nxt :
quotient;
end
end // else: !if(!rst_n)
logic stcky, g, r;
logic [25:0] q_inc_g;
//adjust exponent & mantissa
always_comb begin
if (quotient >= 28'h8000000) begin
exp_adjst = temp_exp ;
// mant_q = q_rnd >> 1;
q_adjst = quotient >>1;
end
else begin
q_adjst = quotient;
exp_adjst = temp_exp-1;
end // else: !if(quotient >= 25'h1000000)
end // always_comb begin
//round
// always_comb begin
// stcky = quotient[0] || |dividend;
// g = quotient[2];
// r = quotient[1];
// q_inc_g = quotient[27:2] +1;
//
// q_rnd[0] = g&&!r&&!stcky ? 1'b0 : q_inc_g[1];
// q_rnd[24:1] = q_inc_g[25:2];
//
// end
always_comb begin
stcky = q_adjst[0] || |dividend;
g = q_adjst[2];
r = q_adjst[1];
q_inc_g = q_adjst[27:2] +1;
q_rnd[0] = g&&!r&&!stcky ? 1'b0 : q_inc_g[1];
q_rnd[24:1] = q_inc_g[25:2];
end
//mantissa/exp adjust needed for case when round
//increments an all 1 case?
// logic quo_gteq;
// assign quo_gteq = q_rnd >= 25'h1000000;
// always_comb begin
// if (q_rnd >= 25'h1000000) begin
// exp_q = temp_exp;
// exp_q = exp_adjst+1;
// mant_q = q_rnd >> 1;
// end
//
// else begin
// mant_q = q_rnd;
// exp_q = exp_adjst;
// end
// end
// always_comb begin
// quotient_val = bsy && (~|cnt_nxt);
// end
always_ff @(posedge clk) begin
quotient_val <= bsy && (~|cnt_nxt);
end
//`ifndef VERILATOR
// ERROR_quoti_w_ne_numer_w: assert property
// (@(posedge clk) disable iff (!rst_n)
// start |-> (NUMER_W == QUOTI_W))
// else $error("quotient width != numer width is unsupported");
// ERROR_numer_w_lt_denom_w: assert property
// (@(posedge clk) disable iff (!rst_n)
// start |-> (NUMER_W >= DENOM_W))
// else $error("numerator width has to be at least as big as denominator width");
//`endif // `ifndef VERILATOR
endmodule // xlr8_fdiv
|
#include <bits/stdc++.h> using namespace std; struct ACfixed { static const int ASZ = 10; struct node { array<int, ASZ> to; int link = -1; int tlink = -1; int id = -1; }; vector<node> d = {{}}; int add(string s, int id) { int v = 0; for (auto C : s) { int c = C - 0 ; if (!d[v].to[c]) d[v].to[c] = d.size(), d.emplace_back(); v = d[v].to[c]; } d[v].id = id; return v; } void init() { d[0].link = -1; queue<int> q; q.push(0); while (q.size()) { int v = q.front(); q.pop(); for (int c = 0; c < ASZ; c++) { int u = d[v].to[c]; if (!u) continue; d[u].link = d[v].link == -1 ? 0 : d[d[v].link].to[c]; d[u].tlink = (d[d[u].link].id == -1) ? d[d[u].link].tlink : d[u].link; q.push(u); } if (v) for (int c = 0; c < ASZ; c++) if (!d[v].to[c]) d[v].to[c] = d[d[v].link].to[c]; } } vector<vector<int>> getAll(string &word) { vector<vector<int>> res(d.size(), vector<int>()); int v = 0; for (int i = 0; i < word.length(); i++) { v = d[v].to[word[i] - 0 ]; int cur = v; while (cur >= 0) { if (d[cur].id != -1) { res[d[cur].id].push_back(i); } cur = d[cur].tlink; } } return res; } }; vector<string> arr; int n, x; string s; string curstr = ; ACfixed ac; void gen(int cur) { if (cur == 0) { arr.push_back(curstr); return; } for (int i = 1; i <= 9; i++) { if (i > cur) continue; curstr.push_back( 0 + i); int csum = 0; bool work = true; for (int j = curstr.size() - 1; j >= 0; j--) { csum += curstr[j] - 0 ; if (csum != x && x % csum == 0) { work = false; break; } } if (work) gen(cur - i); curstr.pop_back(); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> s >> x; n = s.length(); gen(x); for (int i = 0; i < arr.size(); i++) ac.add(arr[i], i); ac.init(); vector<int> dp(ac.d.size(), 1000000009); dp[0] = 0; for (auto ch : s) { vector<int> nextdp(ac.d.size(), 1000000009); for (int state = 0; state < ac.d.size(); state++) { if (dp[state] == 1000000009) continue; nextdp[state] = min(nextdp[state], dp[state] + 1); int trans = ac.d[state].to[ch - 0 ]; if (ac.d[trans].id == -1) nextdp[trans] = min(nextdp[trans], dp[state]); } swap(dp, nextdp); } cout << *min_element(dp.begin(), dp.end()) << endl; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mpram_wrp.v: Multiported-RAM synthesis wrapper //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// configure architectural parameters
`include "config.vh"
module mpram_wrp
#( parameter MEMD = `MEMD , // memory depth
parameter DATAW = `DATAW , // data width
parameter nRPORTS = `nRPORTS, // number of reading ports
parameter nWPORTS = `nWPORTS, // number of writing ports
parameter TYPE = `TYPE , // implementation type: REG, XOR, LVTREG, LVTBIN, LVT1HT, AUTO
parameter BYP = `BYP , // Bypassing type: NON, WAW, RAW, RDW
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [nWPORTS-1:0 ] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [DATAW *nWPORTS-1:0] WData, // write data - packed from nWPORTS read ports
input [`log2(MEMD)*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output wire [DATAW *nRPORTS-1:0] RData); // read data - packed from nRPORTS read ports
// instantiate a multiported-RAM
mpram #( .MEMD (MEMD ), // positive integer: memory depth
.DATAW (DATAW ), // positive integer: data width
.nRPORTS(nRPORTS), // positive integer: number of reading ports
.nWPORTS(nWPORTS), // positive integer: number of writing ports
.TYPE (TYPE ), // text: multi-port RAM implementation type: "AUTO", "REG", "XOR", "LVTREG", "LVTBIN", or "LVT1HT"
// AUTO : Choose automatically based on the design parameters
// REG : Register-based multi-ported RAM
// XOR : XOR-based nulti-ported RAM
// LVTREG: Register-based LVT multi-ported RAM
// LVTBIN: Binary-coded I-LVT-based multi-ported RAM
// LVT1HT: Onehot-coded I-LVT-based multi-ported RAM
.BYP (BYP ), // text: Bypassing type: "NON", "WAW", "RAW", or "RDW"
// WAW: Allow Write-After-Write (need to bypass feedback ram)
// RAW: New data for Read-after-Write (need to bypass output ram)
// RDW: New data for Read-During-Write
.IFILE ("" )) // text: initializtion file, optional
mpram_inst ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port - input : [nWPORTS-1:0 ]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - input : [`log2(MEMD)*nWPORTS-1:0]
.WData (WData ), // write data - packed from nRPORTS read ports - output: [DATAW *nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - input : [`log2(MEMD)*nRPORTS-1:0]
.RData (RData )); // read data - packed from nRPORTS read ports - output: [DATAW *nRPORTS-1:0]
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("set_local.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 17;
reg [STACK_DEPTH:0] index = 1;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("set_local_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#45
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module jmp_cond (
input [4:0] logic_flags,
input [3:0] cond,
input is_cx,
input [15:0] cx,
output reg jmp
);
// Net declarations
wire of, sf, zf, pf, cf;
wire cx_zero;
// Assignments
assign of = logic_flags[4];
assign sf = logic_flags[3];
assign zf = logic_flags[2];
assign pf = logic_flags[1];
assign cf = logic_flags[0];
assign cx_zero = ~(|cx);
// Behaviour
always @(cond or is_cx or cx_zero or zf or of or cf or sf or pf)
if (is_cx) case (cond)
4'b0000: jmp <= cx_zero; /* jcxz */
4'b0001: jmp <= ~cx_zero; /* loop */
4'b0010: jmp <= zf & ~cx_zero; /* loopz */
default: jmp <= ~zf & ~cx_zero; /* loopnz */
endcase
else case (cond)
4'b0000: jmp <= of;
4'b0001: jmp <= ~of;
4'b0010: jmp <= cf;
4'b0011: jmp <= ~cf;
4'b0100: jmp <= zf;
4'b0101: jmp <= ~zf;
4'b0110: jmp <= cf | zf;
4'b0111: jmp <= ~cf & ~zf;
4'b1000: jmp <= sf;
4'b1001: jmp <= ~sf;
4'b1010: jmp <= pf;
4'b1011: jmp <= ~pf;
4'b1100: jmp <= (sf ^ of);
4'b1101: jmp <= (sf ^~ of);
4'b1110: jmp <= zf | (sf ^ of);
4'b1111: jmp <= ~zf & (sf ^~ of);
endcase
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 10; const int MOD = 1e9 + 7; const int INF = 2e9; const long long INFLL = 1e18; const double PI = acos((double)-1); inline int mult(int a, int b, int p = MOD) { return (1ll * a * b) % p; } inline int add(int a, int b, int p = MOD) { return (1ll * a + b) % p; } inline int fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } using namespace std; int main() { ios::sync_with_stdio(false); string s; cin >> s; int n = s.length(); int x = 0, y = 0; int ans = 0; for (int i = 0; i < n; i++) { if (s[i] == - ) { y++; if (x > 0) x--; else ans++; } else { x++; if (y > 0) y--; else ans++; } } cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
|
(* FASM_PARAMS="INV.TA1=TAS1;INV.TA2=TAS2;INV.TB1=TBS1;INV.TB2=TBS2;INV.BA1=BAS1;INV.BA2=BAS2;INV.BB1=BBS1;INV.BB2=BBS2" *)
(* whitebox *)
module C_FRAG (TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, TZ, CZ);
// Routing ports
input wire TBS;
input wire TAB;
input wire TSL;
input wire TA1;
input wire TA2;
input wire TB1;
input wire TB2;
input wire BAB;
input wire BSL;
input wire BA1;
input wire BA2;
input wire BB1;
input wire BB2;
(* DELAY_CONST_TAB="{iopath_TAB_TZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_TZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_TZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_TZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_TZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_TZ}" *)
output wire TZ;
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_TAB="{iopath_TAB_CZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_CZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_CZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_CZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_CZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_CZ}" *)
(* DELAY_CONST_BAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_BSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_BA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_BA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_BB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_BB2="{iopath_BB2_CZ}" *)
output wire CZ;
// Control parameters
parameter [0:0] TAS1 = 1'b0;
parameter [0:0] TAS2 = 1'b0;
parameter [0:0] TBS1 = 1'b0;
parameter [0:0] TBS2 = 1'b0;
parameter [0:0] BAS1 = 1'b0;
parameter [0:0] BAS2 = 1'b0;
parameter [0:0] BBS1 = 1'b0;
parameter [0:0] BBS2 = 1'b0;
// Input routing inverters
wire TAP1 = (TAS1) ? ~TA1 : TA1;
wire TAP2 = (TAS2) ? ~TA2 : TA2;
wire TBP1 = (TBS1) ? ~TB1 : TB1;
wire TBP2 = (TBS2) ? ~TB2 : TB2;
wire BAP1 = (BAS1) ? ~BA1 : BA1;
wire BAP2 = (BAS2) ? ~BA2 : BA2;
wire BBP1 = (BBS1) ? ~BB1 : BB1;
wire BBP2 = (BBS2) ? ~BB2 : BB2;
// 1st mux stage
wire TAI = TSL ? TAP2 : TAP1;
wire TBI = TSL ? TBP2 : TBP1;
wire BAI = BSL ? BAP2 : BAP1;
wire BBI = BSL ? BBP2 : BBP1;
// 2nd mux stage
wire TZI = TAB ? TBI : TAI;
wire BZI = BAB ? BBI : BAI;
// 3rd mux stage
wire CZI = TBS ? BZI : TZI;
// Output
assign TZ = TZI;
assign CZ = CZI;
specify
(TBS => CZ) = (0,0);
(TAB => CZ) = (0,0);
(TSL => CZ) = (0,0);
(TA1 => CZ) = (0,0);
(TA2 => CZ) = (0,0);
(TB1 => CZ) = (0,0);
(TB2 => CZ) = (0,0);
(BAB => CZ) = (0,0);
(BSL => CZ) = (0,0);
(BA1 => CZ) = (0,0);
(BA2 => CZ) = (0,0);
(BB1 => CZ) = (0,0);
(BB2 => CZ) = (0,0);
(TAB => TZ) = (0,0);
(TSL => TZ) = (0,0);
(TA1 => TZ) = (0,0);
(TA2 => TZ) = (0,0);
(TB1 => TZ) = (0,0);
(TB2 => TZ) = (0,0);
endspecify
endmodule
|
#include <bits/stdc++.h> using namespace std; void lwr(string& s) { for (int i = 0; i < s.size(); i++) { if (s[i] >= A and s[i] <= Z ) s[i] = s[i] - A + a ; } } pair<int, int> _rank(const string& s) { int ret = 0; for (int i = 0; i < s.size(); i++) ret += s[i] == r ; return pair<int, int>(ret, (int)s.size()); } map<string, int> who; const int N = 300010; pair<int, int> val[N]; vector<int> g[N], gt[N]; int vis[N]; int c[N]; vector<int> ts; void dfs(int u) { vis[u] = 1; for (int v : g[u]) if (!vis[v]) dfs(v); ts.push_back(u); } pair<int, int> valc[N]; void dfst(int u, int cmp) { vis[u] = 2; c[u] = cmp; valc[cmp] = min(valc[cmp], val[u]); for (int v : gt[u]) if (vis[v] != 2) dfst(v, cmp); } vector<int> gc[N]; pair<int, int> best[N]; pair<int, int> solve(int u) { if (best[u].first != 0x3f3f3f3f) return best[u]; best[u] = valc[u]; for (int v : gc[u]) best[u] = min(best[u], solve(v)); return best[u]; } int main() { ios::sync_with_stdio(0); int m, cnt = 0; cin >> m; vector<int> vv; for (int i = 0; i < m; i++) { string s; cin >> s; lwr(s); if (!who.count(s)) { who[s] = cnt; val[cnt] = _rank(s); cnt++; } vv.push_back(who[s]); } int n; cin >> n; for (int i = 0; i < n; i++) { string u, v; cin >> u >> v; lwr(u); lwr(v); if (!who.count(u)) { who[u] = cnt; val[cnt] = _rank(u); cnt++; } if (!who.count(v)) { who[v] = cnt; val[cnt] = _rank(v); cnt++; } int uu = who[u], vv = who[v]; g[uu].push_back(vv); gt[vv].push_back(uu); } for (int i = 0; i < cnt; i++) { if (!vis[i]) dfs(i); } int comp = 0; fill(valc, valc + N, pair<int, int>(0x3f3f3f3f, 0x3f3f3f3f)); for (int i = cnt - 1; i >= 0; i--) { if (vis[ts[i]] != 2) dfst(ts[i], comp++); } for (int u = 0; u < cnt; u++) { for (int v : g[u]) { if (c[u] != c[v]) gc[c[u]].push_back(c[v]); } } fill(best, best + N, pair<int, int>(0x3f3f3f3f, 0x3f3f3f3f)); pair<long long, long long> ans(0LL, 0LL); for (int i = 0; i < m; i++) { pair<int, int> ret = solve(c[vv[i]]); ans.first += ret.first; ans.second += ret.second; } cout << ans.first << << ans.second << n ; return 0; }
|
`timescale 1ns / 10ps
module led_controller_testbench;
reg clk;
reg reset_n;
reg test_panel_select_n;
reg [31:0] chunk_data;
reg [3:0] chunk_addr;
reg chunk_write_enable;
reg [3:0] row_addr;
reg [1:0] panel_addr;
wire serial_clk;
wire latch_enable;
wire output_enable_n;
wire [11:0] serial_data_out;
wire [15:0] row_select_n;
led_controller uut
(.clk(clk), .reset_n(reset_n), .test_panel_select_n(test_panel_select_n),
.chunk_data(chunk_data), .chunk_addr(chunk_addr),
.chunk_write_enable(chunk_write_enable), .row_addr(row_addr),
.panel_addr(panel_addr), .serial_clk(serial_clk),
.latch_enable(latch_enable), .output_enable_n(output_enable_n),
.serial_data_out(serial_data_out), .row_select_n(row_select_n)
);
always begin // 50MHz clock
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
initial begin
reset_n = 1'b0;
test_panel_select_n = 1'b0;
chunk_data = 32'hffffffff;
chunk_addr = 4'h0;
chunk_write_enable = 1'b0;
row_addr = 4'h0;
panel_addr = 2'h3;
#100;
reset_n = 1'b1;
#200;
chunk_write_enable = 1'b1;
#40;
chunk_write_enable = 1'b0;
#660;
$stop;
end // initial begin
endmodule // led_controller_testbench
|
#include <bits/stdc++.h> int n, arr[100]; bool vis[100]; int Cycle(int st) { int l = 1; int node = arr[st]; vis[st] = true; while (node != st) { if (vis[node]) return -1; l++; vis[node] = true; node = arr[node]; } return l; } long long GCD(long long a, long long b) { int max = (a > b) ? a : b, min = (a < b) ? a : b; while (min != 0) { int temp = max % min; max = min; min = temp; } return max; } long long LCM(long long a, long long b) { return a * b / GCD(a, b); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , arr + i); arr[i]--; } long long res = 1; for (int i = 0; i < n; i++) { if (!vis[i]) { long long l = Cycle(i); if (l == -1) { printf( -1 n ); return 0; } if (l % 2 == 0) l /= 2; res = LCM(res, l); } } printf( %lld n , res); return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_PI_reset for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_PI_reset
// Module Name: NPCG_Toggle_SCC_PI_reset
// File Name: NPCG_Toggle_SCC_PI_reset.v
//
// Version: v1.0.0
//
// Description: NFC phy input module reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_PI_reset
#
(
parameter NumberOfWays = 4
)
(
iSystemClock,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep,
oPM_PCommand
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
wire wModuleTriggered;
localparam State_Idle = 3'b000;
localparam State_PIResetIssue = 3'b001;
localparam State_PIWait = 3'b011;
reg [2:0] rCurState ;
reg [2:0] rNextState ;
wire wPIResetTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_PIResetIssue:State_Idle;
State_PIResetIssue:
rNextState <= (iPM_Ready)?State_PIWait:State_PIResetIssue;
State_PIWait:
rNextState <= (oLastStep)?State_Idle:State_PIWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b110010);
assign oCMDReady = (rCurState == State_Idle);
assign wPIResetTrig = (rCurState == State_PIResetIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_PIWait) & iPM_LastStep[4];
assign oPM_PCommand[7:0] = {1'b0, 1'b0, 1'b0, wPIResetTrig, 1'b0, 1'b0, 1'b0, 1'b0};
endmodule
|
module top;
reg [1:0] lv, rv;
reg res, pass;
initial begin
pass = 1'b1;
lv = 2'b00;
rv = 2'b00;
res = lv ==? rv;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
rv = 2'b01;
res = lv ==? rv;
if (res !== 1'b0) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b10;
rv = 2'b00;
res = lv ==? rv;
if (res !== 1'b0) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b1x;
rv = 2'b00;
res = lv ==? rv;
if (res !== 1'b0) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0x;
rv = 2'b00;
res = lv ==? rv;
if (res !== 1'bx) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'bx", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
rv = 2'b0x;
res = lv ==? rv;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b01;
rv = 2'b0x;
res = lv ==? rv;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0z;
rv = 2'b0x;
res = lv ==? rv;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0x;
rv = 2'b0x;
res = lv ==? rv;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
rv = 2'b00;
res = lv !=? rv;
if (res !== 1'b0) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
rv = 2'b01;
res = lv !=? rv;
if (res !== 1'b1) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b10;
rv = 2'b00;
res = lv !=? rv;
if (res !== 1'b1) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b1x;
rv = 2'b00;
res = lv !=? rv;
if (res !== 1'b1) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0x;
rv = 2'b00;
res = lv !=? rv;
if (res !== 1'bx) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'bx", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
rv = 2'b0x;
res = lv !=? rv;
if (res !== 1'b0) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b01;
rv = 2'b0x;
res = lv !=? rv;
if (res !== 1'b0) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0z;
rv = 2'b0x;
res = lv !=? rv;
if (res !== 1'b0) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
lv = 2'b0x;
rv = 2'b0x;
res = lv !=? rv;
if (res !== 1'b0) begin
$display("Failed: %b !=? %b returned 1'b%b not 1'b0", lv, rv, res);
pass = 1'b0;
end
// Check in a few other contexts.
lv = 2'b01;
rv = 2'b0x;
res = (lv ==? rv) ? 1'b1 : 1'b0;
if (res !== 1'b1) begin
$display("Failed: %b ==? %b (ternary) returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
if (lv !=? rv) begin
$display("Failed: %b ==? %b (if) returned 1'b%b not 1'b1", lv, rv, res);
pass = 1'b0;
end
lv = 2'b00;
while (lv ==? rv) lv += 2'b01;
if (lv !== 2'b10) begin
$display("Failed: %b ==? %b (while) expected lv to be 2'b10", lv, rv);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int a[n]; int count[5005] = {0}; for (int i = 0; i < n; i++) { cin >> a[i]; count[a[i]]++; } int c[n]; int d = 1; for (int i = 1; i <= 5000; i++) { if (count[i] > k) { cout << NO << n ; return 0; } } cout << YES << n ; if (k == 1) { for (int i = 0; i < n; i++) { cout << 1 << ; } } else { for (int i = 1; i <= 5000; i++) { for (int j = 0; j < n; j++) { if (a[j] == i) { c[j] = d; d++; } if (d > k) d = d % k; } } for (int i = 0; i < n; i++) { cout << c[i] << ; } } }
|
module adder(a, b, sum_ab);
parameter integer N_BITS_A = 4;
parameter integer BIN_PT_A = 3;
parameter integer SIGNED_A = 1;
parameter integer N_BITS_B = 4;
parameter integer BIN_PT_B = 2;
parameter integer SIGNED_B = 0;
// TODO
parameter integer N_BITS_OUT = 6;
parameter integer BIN_PT_OUT = 3;
parameter integer SIGNED_OUT = 1;
//0 = WRAP, 1 = SATURATE
parameter integer OVERFLOW_STRATEGY = 0;
//0 = TRUNCATE, 1 = ROUND
parameter integer QUANTIZATION_STRATEGY = 0;
input wire [N_BITS_A-1:0] a;
input wire [N_BITS_B-1:0] b;
output wire [N_BITS_OUT-1:0] sum_ab;
// if inputs are unsigned, pad with 0
localparam integer WHOLE_BITS_A = N_BITS_A-BIN_PT_A;
localparam integer WHOLE_BITS_B = N_BITS_B-BIN_PT_B;
localparam integer WHOLE_BITS_A_IN = (SIGNED_A == 1) ? WHOLE_BITS_A : (WHOLE_BITS_A+1);
localparam integer WHOLE_BITS_B_IN = (SIGNED_B == 1) ? WHOLE_BITS_B : (WHOLE_BITS_B+1);
localparam integer N_BITS_A_IN = WHOLE_BITS_A_IN + BIN_PT_A;
localparam integer N_BITS_B_IN = WHOLE_BITS_B_IN + BIN_PT_B;
wire [N_BITS_A_IN-1:0] a_in;
assign a_in[N_BITS_A-1:0] = a;
assign a_in[N_BITS_A_IN-1] = (SIGNED_A == 1) ? a[N_BITS_A-1] : 1'b0;
wire [N_BITS_B_IN-1:0] b_in;
assign b_in[N_BITS_B-1:0] = b;
assign b_in[N_BITS_B_IN-1] = (SIGNED_B == 1) ? b[N_BITS_B-1] : 1'b0;
// derived parameters for output of adder
localparam integer WHOLE_BITS_ADD_OUT = (WHOLE_BITS_A_IN > WHOLE_BITS_B_IN) ? WHOLE_BITS_A_IN: WHOLE_BITS_B_IN;
localparam integer BIN_PT_ADD_OUT = (BIN_PT_A > BIN_PT_B) ? BIN_PT_A: BIN_PT_B;
localparam integer N_BITS_ADD_OUT = WHOLE_BITS_ADD_OUT + BIN_PT_ADD_OUT + 1;
wire [N_BITS_ADD_OUT-1:0] sum;
add #(.N_BITS_A(N_BITS_A_IN),
.BIN_PT_A(BIN_PT_A),
.N_BITS_B(N_BITS_B_IN),
.BIN_PT_B(BIN_PT_B)) add0 (a_in, b_in, sum);
//TODO quantise and handle overflow if necessary
assign sum_ab = sum;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[2005]; int n, c[2005][2005], ans = 0x3f3f3f3f, was, ot[2005]; bool chk() { static int ar[2005]; int sum = 0; for (int i = (1), LIM = (n); i <= LIM; i++) ar[i] = ot[i], sum += ot[i]; sort(ar + 1, ar + 1 + n); int sm = 0; for (int i = (1), LIM = (n - 1); i <= LIM; i++) { sm += ar[i]; if (sm == i * (i - 1) / 2) return 0; } return 1; } void dfs(int u, int s) { if (u == n + 1) { if (chk()) { if (ans > s) ans = s, was = 0; if (ans == s) was++; } return; } dfs(u + 1, s); for (int i = (1), LIM = (n); i <= LIM; i++) if (c[u][i]) ot[u]--, ot[i]++; else ot[u]++, ot[i]--; for (int i = (1), LIM = (n); i <= LIM; i++) swap(c[i][u], c[u][i]); dfs(u + 1, s + 1); for (int i = (1), LIM = (n); i <= LIM; i++) if (c[u][i]) ot[u]--, ot[i]++; else ot[u]++, ot[i]--; for (int i = (1), LIM = (n); i <= LIM; i++) swap(c[i][u], c[u][i]); } int main() { scanf( %d , &n); for (int i = (1), LIM = (n); i <= LIM; i++) { scanf( %s , s + 1); for (int j = (1), LIM = (n); j <= LIM; j++) c[i][j] = (s[j] == 1 ), ot[i] += c[i][j]; } if (n <= 6) { dfs(1, 0); if (ans == 0x3f3f3f3f) puts( -1 ); else { for (int i = (1), LIM = (ans); i <= LIM; i++) was = 1ll * was * i % 998244353; printf( %d %d n , ans, was); } return 0; } else { if (chk()) { puts( 0 1 ); return 0; } for (int u = (1), LIM = (n); u <= LIM; u++) { for (int i = (1), LIM = (n); i <= LIM; i++) if (c[u][i]) ot[u]--, ot[i]++; else ot[u]++, ot[i]--; for (int i = (1), LIM = (n); i <= LIM; i++) swap(c[i][u], c[u][i]); if (chk()) was++; for (int i = (1), LIM = (n); i <= LIM; i++) if (c[u][i]) ot[u]--, ot[i]++; else ot[u]++, ot[i]--; for (int i = (1), LIM = (n); i <= LIM; i++) swap(c[i][u], c[u][i]); } printf( %d %d n , 1, was); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
`define SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int i, j, n, k, imp, c, h; int f[200]; { imp = 0; memset(f, 0, sizeof(f)); cin >> k; cin >> s; n = ((int)s.size()); h = n % 2 + n / 2; for (i = 0; i < n; i++) if (isalpha(s[i])) f[s[i] - a ]++; for (i = h - 1; i > -1; i--) { if (s[i] != s[n - i - 1]) { if (isalpha(s[i]) && isalpha(s[n - i - 1])) { imp = 1; break; } else if (isalpha(s[i])) s[n - i - 1] = s[i]; else s[i] = s[n - i - 1]; } else if (s[i] == ? ) { c = 0; for (j = k - 1; j > -1; j--) if (f[j] == 0) { c = j; f[j]++; break; } s[i] = s[n - i - 1] = a + c; } } if (imp == 0) { for (i = 0; i < k; i++) if (!f[i]) { imp = 1; break; } } if (!imp) cout << s << endl; else cout << IMPOSSIBLE << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tans, a[100005], qaq[100005], que[1 << 15]; bool vis[1 << 15]; struct node { int x, y, z; } ans[100005 << 1]; struct node2 { int ty, lst, pos; } pre[1 << 15]; void ins(int x, int y, int z) { a[x] ^= 1, a[y] ^= 1, a[z] ^= 1; ans[++tans] = (node){x, y, z}; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int sour = 0; int h = 1, t = 1, yn = min(n, 12); que[1] = sour, vis[sour] = 1; while (h <= t) { int tmp = que[h++]; for (int i = 0; i < yn; i++) qaq[i] = (tmp & (1 << i)) != 0; for (int ty = 1; ty <= 6; ty++) for (int j = 0; j < yn - ty * 2; j++) { qaq[j] ^= 1, qaq[j + ty] ^= 1, qaq[j + 2 * ty] ^= 1; int ttmp = 0; for (int j = 0; j < yn; j++) ttmp += qaq[j] * (1 << j); if (!vis[ttmp]) vis[que[++t] = ttmp] = 1, pre[ttmp] = (node2){ty, tmp, j + 1}; qaq[j] ^= 1, qaq[j + ty] ^= 1, qaq[j + 2 * ty] ^= 1; } } int tmp; for (tmp = n - 6; tmp >= 7; tmp -= 6) { int tcnt = 0, tt = 0; for (int i = tmp + 1; i <= tmp + 6; i++) tcnt += a[i]; if (tcnt == 6) ins(tmp + 1, tmp + 2, tmp + 3), ins(tmp + 4, tmp + 5, tmp + 6); else if (tcnt == 5) { if (a[tmp + 4] == 0) ins(tmp + 1, tmp + 3, tmp + 5), ins(tmp - 2, tmp + 2, tmp + 6); else if (a[tmp + 1] == 0) ins(tmp + 3, tmp + 4, tmp + 5), ins(tmp - 2, tmp + 2, tmp + 6); else { for (int i = tmp + 4; i > tmp; i--) if (a[i] && a[i + 1] && a[i + 2]) { ins(i, i + 1, i + 2); break; } for (int i = tmp + 1; i <= tmp + 6; i++) if (a[i]) que[++tt] = i; ins(que[1] - que[2] + que[1], que[1], que[2]); } } else if (tcnt) { for (int i = tmp + 1; i <= tmp + 6; i++) if (a[i]) que[++tt] = i; sort(que + 1, que + tt + 1); if (tcnt == 1) ins(tmp - que[1] + tmp, tmp, que[1]); else if (tcnt == 2) ins(tmp - que[1] + tmp, tmp, que[1]), ins(tmp - que[2] + tmp, tmp, que[2]); else if (tcnt == 3) { if (que[3] - que[1] == 2) ins(que[1], que[2], que[3]); else ins(que[1] - que[3] + que[1], que[1], que[3]), ins(tmp - que[2] + tmp, tmp, que[2]); } else { if (que[3] - que[1] == 2) ins(que[1], que[2], que[3]), ins(tmp - que[4] + tmp, tmp, que[4]); else if (que[4] - que[2] == 2) ins(que[2], que[3], que[4]), ins(tmp - que[1] + tmp, tmp, que[1]); else ins(que[1] - que[3] + que[1], que[1], que[3]), ins(que[2] - que[4] + que[2], que[2], que[4]); } } } int endr = 0; for (int i = 1; i <= min(n, 12); i++) endr += a[i] * (1 << i - 1); if (!vis[endr]) return 0 * puts( NO ); puts( YES ); while (endr != sour) { ins(pre[endr].pos, pre[endr].pos + pre[endr].ty, pre[endr].pos + 2 * pre[endr].ty); endr = pre[endr].lst; } printf( %d n , tans); for (int i = 1; i <= tans; i++) printf( %d %d %d n , ans[i].x, ans[i].y, ans[i].z); }
|
#include <bits/stdc++.h> using namespace std; long long ar[200004]; long long prefix[200004]; long long D[200004]; void calc(long n) { D[n] = 0; long long mx = -1000000000000000000; for (long i = n - 1; i >= 1; i--) { D[i] = max(mx, prefix[i + 1] - D[i + 1]); mx = max(mx, D[i]); } std::cout << D[1] << endl; } int main() { std::ios::sync_with_stdio(false); ; long n; std::cin >> n; for (long i = 1; i <= n; i++) { std::cin >> ar[i]; } prefix[0] = 0; for (long i = 1; i <= n; i++) { prefix[i] = ar[i] + prefix[i - 1]; } calc(n); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module crypt_shift_salt_1(
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s1 shifts_s1_instance1(K[55:0], Ktmp);
Delay3_salt delay3_instance_s1({K[67:56], Ktmp}, Kout, CLK);
pc2 pc2_instance(Ktmp, Ktmp_in);
crypt_step_salt crypt_step_instance1(
L,
R,
{K[67:56], Ktmp_in},
CLK,
L_out,
R_out
);
endmodule
module crypt_shift_salt_2(
input [31:0] L,
input [31:0] R,
input [67:0] K,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
wire [55:0] Ktmp;
wire [47:0] Ktmp_in;
shifts_s2 shifts_s2_instance2(K[55:0], Ktmp);
Delay3_salt delay3_instance_s2({K[67:56], Ktmp}, Kout, CLK);
pc2 pc2_instance2(Ktmp, Ktmp_in);
crypt_step_salt crypt_step_instance2(
L,
R,
{K[67:56], Ktmp_in},
CLK,
L_out,
R_out
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module Video_System_Pixel_Buffer (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [17: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; long long int lar(long long int a, long long int b) { return ((a >= b) ? a : b); } long long int les(long long int a, long long int b) { return ((a <= b) ? a : b); } int main() { string s; cin >> s; vector<string> v; long long int a = 0, b = 0; for (long long int i = 0; i < s.size(); i++) { if (s[i] == 4 ) a++; else if (s[i] == 7 ) b++; } if (a == 0 && b == 0) { cout << -1 << endl; return 0; } if (a >= b) cout << 4 << endl; else cout << 7 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool is_opening(char c) { switch (c) { case ( : case [ : case { : case < : return true; break; case ) : case ] : case } : case > : return false; break; } } bool is_match_bracket(char c1, char c2) { if (c1 == ( && c2 == ) ) { return true; } else if (c1 == [ && c2 == ] ) { return true; } else if (c1 == { && c2 == } ) { return true; } else if (c1 == < && c2 == > ) { return true; } return false; } int main(void) { string str; cin >> str; size_t len = str.length(); int ans = 0; stack<char> s; bool imp = false; for (int i = 0; i < len; ++i) { bool is_cur_opening = is_opening(str.at(i)); if (!is_cur_opening) { if (!s.empty() && is_opening(s.top())) { if (!is_match_bracket(s.top(), str.at(i))) { ++ans; } s.pop(); } else { imp = true; break; } } else { s.push(str.at(i)); } } if (imp || !s.empty()) { cout << Impossible << endl; } else { cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_BLACKBOX_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s15 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { cout << INTERCAL n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long num[100500]; long long d1[15], d2[15]; int main() { long long n; long long ans = 0; scanf( %lld , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &num[i]); } for (int i = 1; i <= n; i++) { long long digit = 0; long long a = num[i]; long long di = 1; while (a) { d1[++digit] = a % 10; a /= 10; } for (int k = 1; k <= digit; k++) { ans += d1[k] * di + d1[k] * di * 10; di *= 100; di = di % 998244353; ans = ans % 998244353; } } ans *= n; ans = ans % 998244353; printf( %lld , ans); return 0; }
|
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// This is a wrapper around the channelizer module so that it can be
// accessed from the myhdl test bench.
module dut_channelizer;
reg clk;
reg rst_n;
reg [`WIDTH-1:0] in_data;
reg in_nd;
reg [`MWIDTH-1:0] in_m;
reg [`MSG_WIDTH-1:0] in_msg;
reg in_msg_nd;
wire [`WIDTH-1:0] out_data;
wire out_nd;
wire [`MWIDTH-1:0] out_m;
wire [`MSG_WIDTH-1:0] out_msg;
wire out_msg_nd;
wire error;
wire first_channel;
initial begin
$from_myhdl(clk, rst_n, in_data, in_nd, in_m, in_msg, in_msg_nd);
$to_myhdl(out_data, out_nd, out_m, out_msg, out_msg_nd, error, first_channel);
end
channelizer #(`N, `LOG_N, `WIDTH, `MWIDTH, `FLTLEN, `LOG_FLTLEN) dut
(clk, rst_n,
in_data, in_nd, in_m, in_msg, in_msg_nd,
out_data, out_nd, out_m, out_msg, out_msg_nd,
error, first_channel);
endmodule
|
// system_acl_iface_mm_interconnect_2_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_2_avalon_st_adapter #(
parameter inBitsPerSymbol = 258,
parameter inUsePackets = 0,
parameter inDataWidth = 258,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 258,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [257:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [257:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 258)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
system_acl_iface_mm_interconnect_2_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include<bits/stdc++.h> using namespace std; const int N=1505; const int Q=11; int read() { int s=0; char c=getchar(),lc= + ; while (c< 0 || 9 <c) lc=c,c=getchar(); while ( 0 <=c&&c<= 9 ) s=s*10+c- 0 ,c=getchar(); return lc== - ?-s:s; } void write(int x) { if (x<0) putchar( - ),x=-x; if (x<10) putchar(x+ 0 ); else write(x/10),putchar(x%10+ 0 ); } void print(int x,char c= n ) { write(x); putchar(c); } bool vis[N*N]; int a[N][N],ans[N],n,q,f; int cl[2][N][Q],cu[2][N][Q],clu[2][N][Q];//color int dl[2][N][Q],du[2][N][Q],dlu[2][N][Q];//distance int tl[2][N],tu[2][N],tlu[2][N];//total inline void up(int *c,int *d,int x) { int tmpc=c[x],tmpd=d[x]; for (int i=x;i>=1;i--) c[i]=c[i-1],d[i]=d[i-1]; c[0]=tmpc; d[0]=tmpd; } inline void insert(int *c,int *d,int &t,int x) { for (int i=0;i<t;i++) d[i]++; for (int i=0;i<t;i++) if (c[i]==x) return d[i]=0,up(c,d,i),void(); if (t<=q) c[t]=x,d[t]=0,up(c,d,t),t++; else c[t-1]=x,d[t-1]=0,up(c,d,t-1); } inline void merge(int *c1,int *d1,int &t1,int *c2,int *d2,int t2) { static int c[Q],d[Q],i,j,k; for (i=0,j=0,k=0;i<t1&&j<t2&&k<=q;) if (d1[i]<d2[j]) { if (!vis[c1[i]]) { vis[c1[i]]=1; c[k]=c1[i]; d[k]=d1[i]; k++; } i++; } else { if (!vis[c2[j]]) { vis[c2[j]]=1; c[k]=c2[j]; d[k]=d2[j]; k++; } j++; } while (i<t1&&k<=q) { if (!vis[c1[i]]) { vis[c1[i]]=1; c[k]=c1[i]; d[k]=d1[i]; k++; } i++; } while (j<t2&&k<=q) { if (!vis[c2[j]]) { vis[c2[j]]=1; c[k]=c2[j]; d[k]=d2[j]; k++; } j++; } for (i=0;i<k;i++) vis[c[i]]=0; memcpy(c1,c,sizeof(c)); memcpy(d1,d,sizeof(d)); t1=k; } //int de[N][N]; signed main() { n=read(),q=read(); for (int i=1;i<=n;i++) for (int j=1;j<=n;j++) a[i][j]=read(); for (int i=1,p=0;i<=n;i++,p^=1) for (int j=1;j<=n;j++) { /////////////////////////////////////////////row memcpy(cl[p][j],cl[p][j-1],sizeof(cl[p][j])); memcpy(dl[p][j],dl[p][j-1],sizeof(dl[p][j])); tl[p][j]=tl[p][j-1]; insert(cl[p][j],dl[p][j],tl[p][j],a[i][j]); /////////////////////////////////////////////column memcpy(cu[p][j],cu[!p][j],sizeof(cu[p][j])); memcpy(du[p][j],du[!p][j],sizeof(du[p][j])); tu[p][j]=tu[!p][j]; insert(cu[p][j],du[p][j],tu[p][j],a[i][j]); /////////////////////////////////////////////square memcpy(clu[p][j],clu[!p][j-1],sizeof(clu[p][j])); memcpy(dlu[p][j],dlu[!p][j-1],sizeof(dlu[p][j])); tlu[p][j]=tlu[!p][j-1]; merge(clu[p][j],dlu[p][j],tlu[p][j],cl[p][j-1],dl[p][j-1],tl[p][j-1]); merge(clu[p][j],dlu[p][j],tlu[p][j],cu[!p][j],du[!p][j],tu[!p][j]); insert(clu[p][j],dlu[p][j],tlu[p][j],a[i][j]); /////////////////////////////////////////////calculate if (tlu[p][j]<=q) f=min(i,j); else f=min(min(i,j),dlu[p][j][q]); ans[f]++; // print(tlu[p][j],j==n? n : ); // print(tlu[p][j], : ); // for (int k=0;k<tlu[p][j];k++) print(clu[p][j][k], ); // putchar( , ); // putchar( ); // for (int k=0;k<tlu[p][j];k++) print(dlu[p][j][k], ); // puts( ); // de[i][j]=f; } // for (int i=1;i<=n;i++) // for (int j=1;j<=n;j++) print(de[i][j],j==n? n : ); for (int i=n;i>=1;i--) ans[i]+=ans[i+1]; for (int i=1;i<=n;i++) print(ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_M_V
`define SKY130_FD_SC_LP__AND2B_M_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_m (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2b_m (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); n = (int)((double)n / 3 + 0.5); cout << n / 12 << << n % 12 << n ; }
|
#include <bits/stdc++.h> using namespace std; const int ZIMAX = 3005; int n, v; int cnt[ZIMAX]; int main() { cin >> n >> v; for (int i = 1; i <= n; ++i) { int ai, bi; cin >> ai >> bi; cnt[ai] += bi; } int ans = 0; int before = 0; for (int i = 0; i < ZIMAX; ++i) { int azi = before; int ramase = v - azi; if (ramase < 0) { ans += v; before = cnt[i]; } else { azi += (cnt[i] <= ramase ? cnt[i] : ramase); ans += azi; before = max(0, cnt[i] - ramase); } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, sum, count; cin >> n; int a[n][n]; int row[n], col[n]; for (i = 0; i < n; i++) { sum = 0; for (j = 0; j < n; j++) { cin >> a[i][j]; sum += a[i][j]; } row[i] = sum; } for (j = 0; j < n; j++) { sum = 0; for (i = 0; i < n; i++) { sum += a[i][j]; } col[j] = sum; } count = 0; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (col[i] > row[j]) count++; } } cout << count << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; unordered_set<int> int_set; set<int, greater<int> > divisors; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; string a; cin >> a; if ((a.size()) == 1) { cout << a << a << n ; return 0; } else { string rev = string(a.rbegin(), a.rend()); a += rev; cout << a << n ; } return 0; }
|
//bug1061
//typedef logic [7:0] foo_t;
module ptype
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input foo_t a, // To b0 of ptype_buf.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foo_t y0, // From b0 of ptype_buf.v
output logic [7:0] y1, // From b1 of ptype_buf.v
output TYPE_T y2 // From b2 of ptype_buf.v
// End of automatics
);
ptype_buf #(.TYPE_T(foo_t)) b0
(// Outputs
.y (y0),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.TYPE_T(logic [7:0])) b1
(// Outputs
.y (y1),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.WIDTH(8)) b2
(// Outputs
.y (y2),
/*AUTOINST*/
// Inputs
.a (a));
endmodule
module ptype_buf
#(parameter WIDTH = 1,
parameter type TYPE_T = logic [WIDTH-1:0])
(output TYPE_T y,
input TYPE_T a);
assign y = a;
endmodule
///--------------
// Example in docs
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [9:0] i; // To instName of InstModule.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output upper_t o; // From instName of InstModule.v
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i[9:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// verilog-auto-inst-param-value-type:t
// End:
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100100; bool vis[maxn]; long long val[3][maxn]; long long mii[3]; vector<int> g[maxn]; vector<int> a; int ans[maxn]; int d[maxn]; void dfs(int now) { a.push_back(now); vis[now] = 1; for (int i = 0; i < g[now].size(); i++) { if (vis[g[now][i]]) continue; dfs(g[now][i]); } } int main() { int n; scanf( %d , &n); for (int j = 0; j < 3; j++) { for (int i = 1; i <= n; i++) { scanf( %d , &val[j][i]); } } for (int i = 0; i < n - 1; i++) { int f, t; scanf( %d%d , &f, &t); g[f].push_back(t); g[t].push_back(f); d[f]++; d[t]++; if (d[f] > 2 || d[t] > 2) { printf( -1 n ); return 0; } } vector<int> temp; temp.push_back(0); temp.push_back(1); temp.push_back(2); for (int i = 1; i <= n; i++) { if (d[i] == 1) { dfs(i); break; } } long long mi = 1ll << 60; for (int _ = 0; _ < 6; _++) { long long now = 0; for (int i = 0; i < n; i++) { now += val[temp[i % 3]][a[i]]; } if (now < mi) { mi = now; for (int j = 0; j < 3; j++) { mii[j] = temp[j]; } } next_permutation(temp.begin(), temp.end()); } printf( %lld n , mi); for (int i = 0; i < n; i++) { ans[a[i]] = mii[i % 3]; } for (int i = 1; i <= n; i++) { printf( %d , ans[i] + 1); } puts( ); return 0; }
|
#include <bits/stdc++.h> const double pi = 3.14159265358979323846; using namespace std; long long fastexp(long long a, long long b) { long long ans = 1; long long temp = a; while (b > 0) { if (b & 1) ans *= (temp); temp *= temp; b >>= 1; } return ans; } long long GCD(long long a, long long b) { if (a == 0) return b; return GCD(b % a, a); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long* A = new long long[n]; for (long long i = 0; i < n; i++) cin >> A[i]; long long m; cin >> m; long long* B = new long long[m]; for (long long i = 0; i < m; i++) cin >> B[i]; long long count = 0; long long i = 0; long long j = 0; bool f = true; while (i < n && j < m) { long long cum1 = A[i++]; long long cum2 = B[j++]; bool flag = false; while (i < n && j < m) { if (cum1 == cum2) { flag = true; break; } if (cum1 > cum2) { cum2 += B[j]; j++; } else { cum1 += A[i]; i++; } } if (i == n) { while (j < m) cum2 += B[j++]; } if (j == m) { while (i < n) cum1 += A[i++]; } if (cum1 == cum2) flag = true; if (!flag) { f = false; break; } count++; } if (!f) cout << -1 << n ; else cout << count << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BOI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21BOI_FUNCTIONAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BOI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000000000; const int maxn = 1e5 + 100; long long dp[maxn][2], c[maxn]; string reverse(string s) { string t = ; for (int i = s.size() - 1; i >= 0; i--) t += s[i]; return t; } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) cin >> c[i]; string last; cin >> last; dp[0][0] = 0; dp[0][1] = c[0]; for (int i = 1; i < n; i++) { string now; cin >> now; dp[i][0] = dp[i][1] = INF; if (last <= now) dp[i][0] = min(dp[i][0], dp[i - 1][0]); if (reverse(last) <= now) dp[i][0] = min(dp[i][0], dp[i - 1][1]); if (last <= reverse(now)) dp[i][1] = min(dp[i][1], dp[i - 1][0] + c[i]); if (reverse(last) <= reverse(now)) dp[i][1] = min(dp[i][1], dp[i - 1][1] + c[i]); last = now; } long long ans = min(dp[n - 1][0], dp[n - 1][1]); if (ans >= INF) cout << -1 << endl; else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int s[10], a, b, c; cin >> a >> b >> c; s[0] = a + (b * c); s[1] = a * (b + c); s[2] = a * b * c; s[3] = (a + b) * c; s[4] = a + b + c; s[5] = (a * b) + c; sort(s, s + 5, greater<int>()); cout << s[0] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, s, ans, a[200001], f[200001]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (register long long i = 1; i <= n; ++i) { cin >> a[i]; s ^= a[i]; long long x = a[i]; for (register long long j = 60; j > -1; --j) { if ((x >> j) < 1) continue; if (f[j] < 1) { f[j] = x; break; } else x ^= f[j]; } if (x > 0) ++ans; } if (s < 1) cout << -1 n ; else cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f(long long n) { long long t = n; for (long long i = 2; i * i <= n; i++) if (n % i == 0) { t = t / i * (i - 1); while (n % i == 0) n /= i; } if (n > 1) t = t / n * (n - 1); return t; } int main() { long long n, k; cin >> n >> k; for (long long i = 1; i <= k && n > 1; i += 2) n = f(n); printf( %I64d n , n % 1000000007); return 0; }
|
#include <bits/stdc++.h> using namespace std; string A, B; int has[10]; string res; void Create(int from) { for (int i = 0; i < 10; i++) { for (int j = 0; j < has[i]; j++) { res[from++] = i + 0 ; } } } int main() { cin >> A >> B; int st = 0; for (int i = 0; i < A.length(); i++) has[A[i] - 0 ]++; while (A.length() < B.length()) { A = 0 + A; st++; } res = A; for (int i = st; i < A.length(); i++) { for (int j = 10 - 1; j >= 0; j--) { if (has[j] > 0) { has[j]--; res[i] = j + 0 ; Create(i + 1); if (res <= B) break; has[j]++; } } } int pos = 0; while (res[pos] == 0 ) pos++; cout << res.substr(pos) << endl; return 0; }
|
`include "probador_Rx.v"
`include "Rx_Module.v"
module test_bench_Rxt;
//cables de comunicacion entre modulos
wire clock;
wire reset;
wire start;
wire [7:0] RX_BUF_FRAME_TYPE; //B2..0 110b: Received Cable Reset
wire [15:0] ALERT; //B3 Hard Reset
wire [7:0] RECEIVE_DETECT;
wire [7:0] RECEIVE_BYTE_COUNT;
wire tx_State_Machine_ACTIVE;
wire unexpected_GoodCRC;
wire cC_Busy, cC_IDLE;
wire [7:0] data_In;
wire [15:0] ALERTo;
wire [7:0] RECEIVE_BYTE_COUNTo;
wire GoodCRC_to_PHYo;
wire [7:0] DIR_WRITEo;
wire [7:0] DATA_to_Buffero;
//instancia del probador
probador_Rx p_Rx(.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
//instancia del registro
Rx_Module maquinita_Rx (.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
endmodule
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); double a, b, c[100005], mx; int n; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lf %lf , &a, &b); c[i] = (atan2(b, a) * 180) / pi; } sort(c, c + n); for (int i = 0; i < n - 1; i++) { mx = max(mx, c[i + 1] - c[i]); } mx = max(mx, 360 - c[n - 1] + c[0]); printf( %0.08lf n , 360 - mx); return 0; }
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