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#include <bits/stdc++.h> using namespace std; long long i, j, k, m, n, p, s, t, x, a[100005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (cin >> t; t--;) { cin >> n >> x; for (i = p = 0; i < n; i++) { cin >> a[i]; if (a[i] == x) p = 1; } sort(a, a + n); if (p) cout << 1 << endl; else if (a[n - 1] > x) cout << 2 << endl; else cout << (x - 1) / a[n - 1] + 1 << endl; } }
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#include <bits/stdc++.h> using namespace std; int a[10][10]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , &a[i][j]); } } for (int k = 0; k < n; ++k) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { a[i][j] = min(a[i][j], a[i][k] + a[k][j]); } } } int ans = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { ans = max(ans, a[i][j]); } } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; void solve() { long long int n, q, x, y, cnt = 0; cin >> n >> q; vector<vector<long long int>> dp(3, vector<long long int>(n + 2, 0)); while (q--) { cin >> x >> y; if (dp[x][y] == 0) { cnt += (dp[3 - x][y] == 1); cnt += (dp[3 - x][y - 1] == 1); cnt += (dp[3 - x][y + 1] == 1); dp[x][y] = 1; } else { cnt -= (dp[3 - x][y] == 1); cnt -= (dp[3 - x][y - 1] == 1); cnt -= (dp[3 - x][y + 1] == 1); dp[x][y] = 0; } if (cnt == 0) cout << Yes << n ; else cout << No << n ; } } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int t = 1; while (t--) { solve(); } return 0; }
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#include <bits/stdc++.h> using namespace std; /* * * * * * * * * * */ #define mp make_pair typedef long long ll; typedef long double ld; typedef pair<int, int> pii; /* * * * * * * * * * */ /* * * * Too many mind, no mind. * * */ bool can(int med, int k, vector <int> &a) { int n = a.size(); vector <int> pre(n), mn(n); for (int i = 0; i < n; ++i) pre[i] = a[i] < med ? -1 : 1; mn[0] = pre[0]; for (int i = 1; i < k; ++i) { pre[i] += pre[i - 1]; mn[i] = min(pre[i], mn[i - 1]); } if (pre[k - 1] > 0) return 1; for (int i = k; i < n; ++i) { pre[i] += pre[i - 1]; mn[i] = min(pre[i], mn[i - 1]); if (mn[i - k] <= pre[i] - 1 || pre[i] > 0) return 1; } return 0; } int main(){ ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); //freopen( input.txt , r , stdin); //freopen( output.txt , w , stdout); int n, k; cin >> n >> k; vector <int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; int lo = 1, hi = n; while (lo < hi) { int mid = lo + (hi - lo + 1) / 2; if (can(mid, k, a)) lo = mid; else hi = mid - 1; } cout << lo << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long t, fact[405], inv[405], dp[405][405], ans[405], n, dp2[405]; long long p; long long exp(long long x, long long k) { if (k == 0) return 1; if (k % 2 == 1) return x * exp(x, k - 1) % p; long long y = exp(x, k / 2); return y * y % p; } int main() { cin >> t >> p; fact[0] = 1; for (int i = 1; i < 405; ++i) { fact[i] = i * fact[i - 1] % p; inv[i] = exp(i, p - 2); } dp[0][0] = 1; for (int i = 0; i <= 399; ++i) for (int k = 1; k <= 400; ++k) for (int j = 0; j <= 400 - k; ++j) dp[j + k][i + 1] = (dp[j + k][i + 1] + fact[k] * dp[j][i]) % p; dp2[1] = dp2[2] = 1; for (int i = 3; i <= 400; ++i) { dp2[i] = fact[i]; for (int j = 1; j < i; ++j) dp2[i] = (p + dp2[i] - dp2[j] * fact[i - j] % p) % p; } for (int i = 1; i <= 400; ++i) { ans[i] = fact[i]; for (int j = 3; j < i; ++j) ans[i] = (ans[i] + p - dp[i][j] * ans[j]) % p; for (int j = 1; j <= i - 1; ++j) ans[i] = (ans[i] + p - 2 * dp2[j] * fact[i - j] % p) % p; ans[2] = 2; } for (int i = 0; i < t; ++i) { int x; cin >> x; cout << ans[x] << n ; } }
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#include <bits/stdc++.h> using namespace std; const int N = 505; const long long inf = 1e18; inline int read() { int x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return x; } int n, m, now; long long ans, Pow[100]; bitset<N> f[2][64][N], g, tmp; int main() { n = read(); m = read(); int u, v, w; for (int i = 1; i <= m; ++i) { u = read(); v = read(); w = read(); f[w][0][u][v] = 1; } for (int i = 1; i <= 60; ++i) for (int u = 1; u <= n; ++u) for (int v = 1; v <= n; ++v) { if (f[0][i - 1][u][v]) f[0][i][u] |= f[1][i - 1][v]; if (f[1][i - 1][u][v]) f[1][i][u] |= f[0][i - 1][v]; } if (f[0][60][1].count()) { puts( -1 ); return 0; } now = 0; tmp[1] = 1; Pow[0] = 1; for (int i = 1; i <= 60; ++i) Pow[i] = Pow[i - 1] << 1; for (int i = 60; i >= 0; --i) { g.reset(); for (int j = 1; j <= n; ++j) if (tmp[j]) g |= f[now][i][j]; if (g.count()) { now ^= 1; tmp = g; ans += Pow[i]; } } if (ans > inf) puts( -1 ); else printf( %lld , ans); }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
X ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; int A1, A2, A3, A4; int main() { int i; scanf( %d%d%d%d , &A1, &A2, &A3, &A4); if (abs(A3 - A4) > 1) printf( -1 ); else { if (A3 == A4) { if ((((A1) > (A2) ? (A1) : (A2)) - A3 - 1 < 0) || (((A1) < (A2) ? (A1) : (A2)) < A3)) printf( -1 ); else { if (A1 - A3 - 1 < 0) { for (i = 1; i <= A3; ++i) printf( 74 ); for (i = A2 - A3; i >= 1; --i) printf( 7 ); } else { for (i = A1 - A3 - 1; i >= 1; --i) printf( 4 ); for (i = 1; i <= A3; ++i) printf( 47 ); for (i = A2 - A3; i >= 1; --i) printf( 7 ); printf( 4 ); } } } else { if (A3 > A4) { if ((A1 - A3 < 0) || (A2 - A3 < 0)) printf( -1 ); else { for (i = A1 - A3; i >= 1; --i) printf( 4 ); for (i = 1; i <= A3; ++i) printf( 47 ); for (i = A2 - A3; i >= 1; --i) printf( 7 ); } } else { if ((A1 - A3 - 1 < 0) || (A4 - 2 < 0) || (A2 - A3 < 0)) printf( -1 ); else { printf( 74 ); for (i = A1 - A3 - 1; i >= 1; --i) printf( 4 ); for (i = A4 - 2; i >= 1; --i) printf( 74 ); for (i = A2 - A3; i >= 1; --i) printf( 7 ); printf( 4 ); } } } } printf( n ); return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_TB_V
`define SKY130_FD_SC_HD__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_TB_V
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#include <bits/stdc++.h> using namespace std; struct node { int active; set<int> prev, next; node() : active(1) {} }; int main() { int n, k, m, i, j; int a, b; cin >> n >> m; int cnt = 1; set<int> sh; set<int>::iterator it; for (i = 0; i < n; i++) sh.insert(i); node* graf = new node[n]; for (i = 0; i < m; i++) { cin >> a >> b; a--, b--; if (graf[a].active == 0) continue; if (graf[b].prev.size() == 0) sh.erase(b); graf[a].next.insert(b); graf[b].prev.insert(a); while (sh.size() == 1) { k = *sh.begin(); cnt++; if (cnt == n) { cout << i + 1 << endl; return 0; } for (it = graf[k].next.begin(); it != graf[k].next.end(); it++) { j = *it; graf[j].prev.erase(k); if (graf[j].prev.size() == 0) sh.insert(j); } sh.erase(k); graf[k].active = 0; } } cout << -1 << endl; }
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/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
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#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { return (a % b) == 0 ? b : GCD(b, a % b); } long long mod(long long x) { return ((x % 998244353 + 998244353) % 998244353); } bool cmp(const pair<int, int> &left, const pair<int, int> &right) { return left.first > right.first || (left.first == right.first && left.second < right.second); } int main() { int n, m, p1, p2, p3, t1, t2, i, j, k, mx = 0; vector<pair<int, int> > v; cin >> n >> p1 >> p2 >> p3 >> t1 >> t2; for (i = 0; i < n; i++) { cin >> j >> k; v.push_back(make_pair(j, k)); } sort(v.begin(), v.end()); for (i = 0; i < n - 1; i++) { mx += (v[i].second - v[i].first) * p1; if (v[i + 1].first > v[i].second + t1) { mx += t1 * p1; if (v[i + 1].first > v[i].second + t1 + t2) { mx += t2 * p2; mx += (v[i + 1].first - (v[i].second + t1 + t2)) * p3; } else mx += (v[i + 1].first - (v[i].second + t1)) * p2; } else mx += (v[i + 1].first - v[i].second) * p1; } mx += (v[n - 1].second - v[n - 1].first) * p1; cout << mx << endl; return 0; }
|
module eb_fifo_ctrl #(
parameter DEPTHMO = 4'd15,
parameter DEPTHLOG2MO = 3
) (
input t_0_req,
output t_0_ack,
output reg i_0_req,
input i_0_ack,
output reg [DEPTHLOG2MO : 0] wr_ptr,
output wire [DEPTHLOG2MO : 0] rd_ptr,
output wen, ren,
input clk, reset_n
);
reg [DEPTHLOG2MO : 0] status_cnt;
reg [DEPTHLOG2MO : 0] q_rd_ptr;
assign t_0_ack = !(status_cnt == DEPTHMO);
assign ren = 1;
assign wen = t_0_req && t_0_ack;
always @(posedge clk or negedge reset_n)
if (~reset_n) i_0_req <= 1'b0;
else if (status_cnt == 0 && !(t_0_req && t_0_ack)) i_0_req <= 0;
else if ((i_0_req && i_0_ack) && !(t_0_req && t_0_ack) && (status_cnt == 1)) i_0_req <= 0;
else i_0_req <= 1;
always @(posedge clk or negedge reset_n)
if (~reset_n) wr_ptr <= 0;
else if (t_0_req && t_0_ack) wr_ptr <= (wr_ptr == DEPTHMO) ? 0 : (wr_ptr + 1);
assign rd_ptr=(i_0_req & i_0_ack)?(((q_rd_ptr == DEPTHMO) && (status_cnt != 0)) ? 0 : q_rd_ptr + 1):q_rd_ptr;
always @(posedge clk or negedge reset_n)
if (~reset_n) begin
q_rd_ptr <= 0;
end else begin
if (i_0_req && i_0_ack) q_rd_ptr <= (((q_rd_ptr == DEPTHMO) && (status_cnt != 0)) ? 0 : (q_rd_ptr + 1));
end
always @(posedge clk or negedge reset_n)
if (~reset_n) status_cnt <= 0;
else if ((i_0_req && i_0_ack) && (t_0_req && t_0_ack)) status_cnt <= status_cnt;
else if (i_0_req && i_0_ack && (status_cnt != 0)) status_cnt <= status_cnt - 1;
else if (t_0_req && t_0_ack) status_cnt <= status_cnt + 1;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 8 22:23:41 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/xfft/xfft_stub.v
// Design : xfft
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xfft_v9_0,Vivado 2014.1" *)
module xfft(aclk, s_axis_config_tdata, s_axis_config_tvalid, s_axis_config_tready, s_axis_data_tdata, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tlast, m_axis_data_tdata, m_axis_data_tuser, m_axis_data_tvalid, m_axis_data_tready, m_axis_data_tlast, event_frame_started, event_tlast_unexpected, event_tlast_missing, event_status_channel_halt, event_data_in_channel_halt, event_data_out_channel_halt)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tdata[7:0],s_axis_config_tvalid,s_axis_config_tready,s_axis_data_tdata[31:0],s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tlast,m_axis_data_tdata[63:0],m_axis_data_tuser[15:0],m_axis_data_tvalid,m_axis_data_tready,m_axis_data_tlast,event_frame_started,event_tlast_unexpected,event_tlast_missing,event_status_channel_halt,event_data_in_channel_halt,event_data_out_channel_halt" */;
input aclk;
input [7:0]s_axis_config_tdata;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [31:0]s_axis_data_tdata;
input s_axis_data_tvalid;
output s_axis_data_tready;
input s_axis_data_tlast;
output [63:0]m_axis_data_tdata;
output [15:0]m_axis_data_tuser;
output m_axis_data_tvalid;
input m_axis_data_tready;
output m_axis_data_tlast;
output event_frame_started;
output event_tlast_unexpected;
output event_tlast_missing;
output event_status_channel_halt;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
endmodule
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_acos(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_acos core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
Require Import AutoSep.
(** * Always-0 *)
Definition always0S res : spec := SPEC reserving res
PRE[_] Emp
POST[R] [| R = 0 |].
Definition always0 := bmodule "always0" {{
bfunction "main"("f") [always0S 2]
"f" <-- Lambda() [always0S 0]
Return 0
end;;
"f" <-- ICall "f"()
[PRE[_, R] [| R = 0 |]
POST[R'] [| R' = 0 |] ];;
Return "f"
end
}}.
Hint Extern 1 (@eq W _ _) => words.
Theorem always0Ok : moduleOk always0.
vcgen; abstract (post; try icall (@nil string); (sep_auto; auto)).
Qed.
(** * Add three numbers *)
Definition add3S : spec := SPEC("x", "y", "z") reserving 5
PRE[V] Emp
POST[R] [| R = V "x" ^+ V "y" ^+ V "z" |].
Definition addS : spec := SPEC("x", "y") reserving 0
PRE[V] Emp
POST[R] [| R = V "x" ^+ V "y" |].
Definition add3 := bmodule "add3" {{
bfunction "add3"("x", "y", "z", "f", "tmp") [add3S]
"f" <-- Lambda("x", "y") [addS]
Return "x" + "y"
end;;
"tmp" <-- ICall "f"("x", "y")
[PRE[V, R] Emp
POST[R'] [| R' = R ^+ V "z" |]];;
Return "tmp" + "z"
end
}}.
Theorem add3Ok : moduleOk add3.
vcgen; abstract (post; try icall ("x" :: "y" :: nil); (sep_auto; auto)).
Qed.
|
#include <bits/stdc++.h> using namespace std; int n; map<string, int> mid, pid; std::vector<string> hostname; vector<int> a[100000]; char s[1000]; int m_total = 0, p_total = 0; int b[100000]; std::vector<std::vector<int> > ans; bool cmp(int i, int j) { return a[i] < a[j]; } int main(int argc, char const *argv[]) { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %s , s); int j = 7; for (; s[j]; ++j) if (s[j] == / ) break; string host = , path = ; for (int k = 0; k < j; ++k) host += s[k]; for (int k = j; s[k]; ++k) path += s[k]; if (mid.count(host) == 0) { mid[host] = m_total++; hostname.push_back(host); } if (pid.count(path) == 0) { pid[path] = p_total++; } a[mid[host]].push_back(pid[path]); } for (int i = 0; i < m_total; ++i) { sort(a[i].begin(), a[i].end()); a[i].erase(unique(a[i].begin(), a[i].end()), a[i].end()); b[i] = i; } sort(b, b + m_total, cmp); int l = 0; for (int i = 1; i < m_total; ++i) { if (a[b[i]] != a[b[l]]) { if (i - l > 1) { std::vector<int> v; v.clear(); for (int j = l; j < i; ++j) v.push_back(b[j]); ans.push_back(v); } l = i; } } if (m_total - l > 1) { std::vector<int> v; v.clear(); for (int j = l; j < m_total; ++j) v.push_back(b[j]); ans.push_back(v); } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); ++i) { for (int j = 0; j < ans[i].size(); ++j) { printf( %s%c , hostname[ans[i][j]].c_str(), j < ans[i].size() - 1 ? : n ); } } return 0; }
|
`define Swc_NOP 4'h0
`define Swc_LD0 4'h1
`define Swc_LD1 4'h2
`define Swc_LD2 4'h3
`define Swc_COU 4'h4
`define Swc_COD 4'h5
`define Swc_CCU 4'h6
`define Swc_CCD 4'h7
`define Swc_CCS 4'h8
`define Swc_State_Reset 2'h0
`define Swc_State_Ready 2'h1
`define Swc_State_Error 2'h2
module Swc(clock,reset,inst,inst_en,counter,ready);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [23:0] counter;
output wire ready;
reg [1:0] s_State;
reg [3:0] s_ContInst;
reg [23:0] s_Counter;
wire i_Ready;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign counter = s_Counter;
assign ready = i_Ready;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
assign i_Ready = s_Counter == 0;
always @ (posedge clock) begin
if (reset) begin
s_State <= `Swc_State_Reset;
s_ContInst <= 0;
s_Counter <= 0;
end
else begin
case (s_State)
`Swc_State_Reset: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= 0;
end
`Swc_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Swc_NOP: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter;
end
`Swc_LD0: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= {s_Counter[23:8],w_InstImm};
end
`Swc_LD1: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= {s_Counter[23:16],w_InstImm,s_Counter[7:0]};
end
`Swc_LD2: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= {w_InstImm,s_Counter[15:0]};
end
`Swc_COU: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter + 1;
end
`Swc_COD: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter - 1;
end
`Swc_CCU: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_CCU;
s_Counter <= s_Counter + 1;
end
`Swc_CCD: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_CCD;
s_Counter <= s_Counter - 1;
end
`Swc_CCS: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter;
end
default: begin
s_State <= `Swc_State_Error;
s_ContInst <= 0;
s_Counter <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
case (s_ContInst)
`Swc_NOP: begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter;
end
`Swc_CCU: begin
if (i_Ready) begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter;
end
else begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_CCU;
s_Counter <= s_Counter + 1;
end // else: !if(i_Ready)
end // case: `Swc_CCU
`Swc_CCD: begin
if (i_Ready) begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_NOP;
s_Counter <= s_Counter;
end
else begin
s_State <= `Swc_State_Ready;
s_ContInst <= `Swc_CCD;
s_Counter <= s_Counter - 1;
end // else: !if(i_Ready)
end // case: `Swc_CCD
default: begin
s_State <= `Swc_State_Error;
s_ContInst <= 0;
s_Counter <= 0;
end
endcase // case (s_ContInst)
end // else: !if(inst_en)
end // case: `Swc_State_Reset
`Swc_State_Error: begin
s_State <= `Swc_State_Error;
s_ContInst <= 0;
s_Counter <= 0;
end
default: begin
s_State <= `Swc_State_Error;
s_ContInst <= 0;
s_Counter <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Swc_NOP: begin
$sformat(d_Input,"EN NOP");
end
`Swc_LD0: begin
$sformat(d_Input,"EN (LD0 %2X)",w_InstImm);
end
`Swc_LD1: begin
$sformat(d_Input,"EN (LD1 %2X)",w_InstImm);
end
`Swc_LD2: begin
$sformat(d_Input,"EN (LD2 %2X)",w_InstImm);
end
`Swc_COU: begin
$sformat(d_Input,"EN COU");
end
`Swc_COD: begin
$sformat(d_Input,"EN COD");
end
`Swc_CCU: begin
$sformat(d_Input,"EN CCU");
end
`Swc_CCD: begin
$sformat(d_Input,"EN CCD");
end
`Swc_CCS: begin
$sformat(d_Input,"EN CCS");
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Swc_State_Reset: begin
$sformat(d_State,"X");
end
`Swc_State_Ready: begin
case (s_ContInst)
`Swc_NOP: begin
if (i_Ready) begin
$sformat(d_State,"R NOP %6X Ready",s_Counter);
end
else begin
$sformat(d_State,"R NOP %6X NotReady",s_Counter);
end
end
`Swc_CCU: begin
if (i_Ready) begin
$sformat(d_State,"R CCU %6X Ready",s_Counter);
end
else begin
$sformat(d_State,"R CCU %6X NotReady",s_Counter);
end
end
`Swc_CCD: begin
if (i_Ready) begin
$sformat(d_State,"R CCD %6X Ready",s_Counter);
end
else begin
$sformat(d_State,"R CCD %6X NotReady",s_Counter);
end
end
default: begin
if (i_Ready) begin
$sformat(d_State,"R ? %6X Ready",s_Counter);
end
else begin
$sformat(d_State,"R ? %6X NotReady",s_Counter);
end
end
endcase // case (s_ContInst)
end // case: `Swc_State_Ready
`Swc_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif
endmodule // Swc
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int N = 1005; int cnt[N]; bitset<N> dp; int n, m; int idx[N]; int par[N]; int xx[N]; bool vis[N]; int find(int x) { if (par[x] == x) return x; return par[x] = find(par[x]); } int main() { for (int i = 0; i <= 1000; i += 1) cnt[i] = 0; cin >> n >> m; int ix = 1; for (int i = 0; i <= n; i += 1) par[i] = i; int id = -1, tmp, x; bool flag = false; for (int i = 1; i <= n; i += 1) { cin >> xx[i]; if (xx[i] != 0) par[i] = find(par[xx[i]]); if (xx[i] == 0) { idx[i] = ix++; } } for (int i = 1; i <= n; i += 1) { if (find(par[i]) == find(par[m])) { continue; } cnt[idx[find(par[i])]]++; } int now = m; while (now != 0) { cnt[idx[par[m]]]++; now = xx[now]; } dp[cnt[idx[par[m]]]] = 1; for (int i = 1; i <= ix - 1; i += 1) { if (i != idx[par[m]]) { dp = (dp << cnt[i]) | dp; } } for (int i = 0; i <= n; i += 1) { if (dp[i] == 1) { cout << i << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, i, a, b, sum = 0; cin >> n >> m; long long arr[n + 1]; for (i = 1; i <= n; i++) { cin >> arr[i]; } for (i = 0; i < m; i++) { cin >> a >> b; sum += min(arr[a], arr[b]); } cout << sum << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); long long int arr[100]; for (int i = 0; i < n; i++) cin >> arr[i]; long long int cnt[5]; long long int p[5]; for (int i = 0; i < 5; i++) cin >> p[i]; long long int min = 1000000009; for (int i = 0; i < 5; i++) if (p[i] < min) min = p[i]; for (int i = 0; i < 5; i++) cnt[i] = 0; long long int ps = 0; for (int i = 0; i < n; i++) { ps = ps + arr[i]; while (ps >= min) { long long int pp; for (int j = 4; j >= 0; j--) { if (ps < min) break; pp = ps / p[j]; ps = ps - pp * p[j]; cnt[j] += pp; } } } for (int i = 0; i < 5; i++) cout << cnt[i] << ; cout << n << ps << endl; return 0; }
|
`timescale 1ns / 1ps
module control_ascci(
input clk,
input top_ascci,
input top_col,
input new_string,
input done,
output reg add_dirram,
output reg reset_dirram,
output reg add_col,
output reg reset_col,
output reg add_ascci,
output reg reset_ascci,
output reg init,
output reg leer_rom,
output reg leer_ram,
output reg run_efect //señal q inicia el efecto despues de cargar ram
);
//lectura =escritura para la ram
reg [6:0] current_state;
reg [6:0] next_state;
parameter start=7'b0000000, state_1=7'b0000001, state_2=7'b0000010, state_3=7'b0000011, state_4=7'b0000100, state_5=7'b0000101,check=7'b0000110,state_1p=7'b0000111;
always @(top_ascci or done or top_col or new_string or current_state)begin
case(current_state)
start: begin //encendido esperando new string
add_dirram=1'b0;
reset_dirram=1'b1;
add_col=1'b0;
reset_col=1'b1;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b0;
leer_ram=1'b1;
init=0; //inicio multiplicador
run_efect=1'b0;
if (new_string==1'b1 ) next_state<=state_1p;
else next_state<=start;
end
state_1p: begin //inicial multiplicacion
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b1;
leer_rom=1'b1;
leer_ram=1'b0;
init=1;
run_efect=1'b0;
next_state<=state_1;
end
state_1: begin //inicial multiplicacion
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b1;
leer_ram=1'b0;
init=1;
run_efect=1'b0;
next_state<=state_2;
end
state_2: begin //esperando fin multiplicacion
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b1;
leer_ram=1'b0;
init=0;
run_efect=1'b0;
if(done==1'b1) next_state<=state_3;
else next_state<=state_2;
end
state_3: begin //lee y guarda columna de rom a ram
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b1;
leer_ram=1'b0;
init=0;
run_efect=1'b0;
next_state<=state_4;
end
state_4: begin //pasa a sigiente columna
add_dirram=1'b1;
reset_dirram=1'b0;
add_col=1'b1;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b1;
leer_ram=1'b0;
init=0;
run_efect=1'b0;
if (top_col == 1'b1) next_state<=state_5;
else next_state<=state_3;
end
state_5: begin // pasa a sigiente ascci
add_dirram=1'b1;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b1;
add_ascci=1'b1;
reset_ascci=1'b0;
leer_rom=1'b0;
leer_ram=1'b0;
init=0;
run_efect=1'b0;
if (top_ascci==1'b1)next_state<=check;
else next_state<=state_1;
end
check: begin //inicia efectos
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b0;
leer_ram=1'b1;
init=0;
run_efect=1'b1;
if (new_string==1'b1) next_state<=start;
else next_state<=check;
end
default:
begin
add_dirram=1'b0;
reset_dirram=1'b0;
add_col=1'b0;
reset_col=1'b0;
add_ascci=1'b0;
reset_ascci=1'b0;
leer_rom=1'b0;
leer_ram=1'b0;
init=0;
run_efect=1'b0;
next_state<=start;
end
endcase
end
always @(negedge clk) begin
current_state<=next_state;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:07 07/01/2014
// Design Name:
// Module Name: cheat
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cheat(
input clk,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_reset_strobe,
input snescmd_wr_strobe,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg auto_nmi_enable = 1;
reg auto_irq_enable = 0;
reg auto_nmi_enable_sync = 0;
reg auto_irq_enable_sync = 0;
reg hook_enable_sync = 0;
reg [1:0] sync_delay = 2'b10;
reg [4:0] nmi_usage = 5'h00;
reg [4:0] irq_usage = 5'h00;
reg [20:0] usage_count = 21'h1fffff;
reg [29:0] hook_enable_count = 0;
reg hook_disable = 0;
reg [3:0] unlock_token = 0;
reg [6:0] temp_unlock_delay = 0;
reg temp_vector_unlock = 0;
reg [23:0] cheat_addr[5:0];
reg [7:0] cheat_data[5:0];
reg [5:0] cheat_enable_mask;
wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5])),
(cheat_enable_mask[4] & (SNES_ADDR == cheat_addr[4])),
(cheat_enable_mask[3] & (SNES_ADDR == cheat_addr[3])),
(cheat_enable_mask[2] & (SNES_ADDR == cheat_addr[2])),
(cheat_enable_mask[1] & (SNES_ADDR == cheat_addr[1])),
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
wire nmi_addr_match = |nmi_match_bits;
wire irq_addr_match = |irq_match_bits;
wire hook_enable = ~|hook_enable_count & ~hook_disable;
assign snescmd_unlock = &unlock_token | temp_vector_unlock;
assign data_out = cheat_match_bits[0] ? cheat_data[0]
: cheat_match_bits[1] ? cheat_data[1]
: cheat_match_bits[2] ? cheat_data[2]
: cheat_match_bits[3] ? cheat_data[3]
: cheat_match_bits[4] ? cheat_data[4]
: cheat_match_bits[5] ? cheat_data[5]
: nmi_match_bits[1] ? 8'hb0
: irq_match_bits[1] ? 8'hc4
: 8'h2b;
assign cheat_hit = (cheat_enable & cheat_addr_match)
| (hook_enable_sync & (((auto_nmi_enable_sync & nmi_enable) & nmi_addr_match)
|((auto_irq_enable_sync & irq_enable) & irq_addr_match)));
always @(posedge clk) usage_count <= usage_count - 1;
// Try and autoselect NMI or IRQ hook
always @(posedge clk) begin
if(usage_count == 21'b0) begin
nmi_usage <= ~hook_disable & SNES_cycle_start & nmi_match_bits[1];
irq_usage <= ~hook_disable & SNES_cycle_start & irq_match_bits[1];
if(|nmi_usage & |irq_usage) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(irq_usage == 5'b0) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(nmi_usage == 5'b0) begin
auto_nmi_enable <= 1'b0;
auto_irq_enable <= 1'b1;
end
end else begin
if(SNES_cycle_start & nmi_match_bits[0] & ~hook_disable) nmi_usage <= nmi_usage + 1;
if(SNES_cycle_start & irq_match_bits[0] & ~hook_disable) irq_usage <= irq_usage + 1;
end
end
// Temporary allow entry of snescmd area by the CPU, software must then unlock
// permanently
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match | irq_addr_match) begin
temp_unlock_delay <= 7'd72;
temp_vector_unlock <= 1'b1;
end else begin
if (|temp_unlock_delay) temp_unlock_delay <= temp_unlock_delay - 1;
if (temp_unlock_delay == 7'd0) begin
temp_vector_unlock <= 1'b0;
end
end
end
end
// Do not change vectors while they are being read
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match | irq_addr_match) sync_delay <= 2'b10;
else begin
if (|sync_delay) sync_delay <= sync_delay - 1;
if (sync_delay == 2'b00) begin
auto_nmi_enable_sync <= auto_nmi_enable;
auto_irq_enable_sync <= auto_irq_enable;
hook_enable_sync <= hook_enable;
end
end
end
end
// write/read inhibit bram area from SNES
always @(posedge clk) begin
if(snescmd_wr_strobe) begin
if(SNES_ADDR[8:0] == 9'h1f4 && SNES_DATA == 8'h48) unlock_token[0] <= 1'b1;
else if(SNES_ADDR[8:0] == 9'h1f5 && SNES_DATA == 8'h75) unlock_token[1] <= 1'b1;
else if(SNES_ADDR[8:0] == 9'h1f6 && SNES_DATA == 8'h72) unlock_token[2] <= 1'b1;
else if(SNES_ADDR[8:0] == 9'h1f7 && SNES_DATA == 8'h7a) unlock_token[3] <= 1'b1;
else if(SNES_ADDR[8:2] == 9'b1111101) unlock_token <= 4'b0000;
end else if(SNES_reset_strobe) unlock_token <= 4'b0000;
end
// feature control
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd880000000;
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
always @(posedge clk) begin
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
hook_disable <= SNES_DATA[0];
end
end else if(pgm_we) begin
if(pgm_idx < 6) begin
cheat_addr[pgm_idx] <= pgm_in[31:8];
cheat_data[pgm_idx] <= pgm_in[7:0];
end else if(pgm_idx == 6) begin // set rom patch enable
cheat_enable_mask <= pgm_in[5:0];
end else if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[7:4] are reset bit flags
// pgm_in[3:0] are set bit flags
{holdoff_enable, irq_enable, nmi_enable, cheat_enable} <= ({holdoff_enable, irq_enable, nmi_enable, cheat_enable} & ~pgm_in[7:4])
| pgm_in[3:0];
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int x = 0; x < n; x++) { cin >> a[x]; } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = 0; k < n; ++k) { if (a[i] == a[j] + a[k] && (i != j && j != k && i != k)) { cout << i + 1 << << j + 1 << << k + 1 << endl; return 0; } } } } cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int deg[10000 + 10]; int main() { int n; cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; deg[a - 1]++, deg[b - 1]++; } int ans = 0; for (int i = 0; i < n; i++) ans += deg[i] * (deg[i] - 1) / 2; cout << ans; }
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; map<long long, long long> mp; long long ans = 0; long long prev = 0; long long sum = 0; for (long long i = 0; i < n; i++) { sum += a[i]; if (sum == 0) prev = max(prev, mp[0] + 1); else if (mp.find(sum) != mp.end()) prev = max(prev, mp[sum] + 1); ans += i + 1 - prev; mp[sum] = i + 1; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int ans; ans = n / 2 + 1; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int cnt[2]; int main() { int n, k, m; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &m); cnt[m % 2]++; } int r = n - k; if (r == 0) { if (cnt[1] % 2 == 1) puts( Stannis ); else puts( Daenerys ); return 0; } int sec = r / 2; int fst = r - sec; if (fst >= cnt[0] && k % 2 == 1) { puts( Stannis ); return 0; } if (sec >= cnt[1]) { puts( Daenerys ); return 0; } if (sec >= cnt[0] && k % 2 == 0) { puts( Daenerys ); return 0; } if (r % 2 == 0) { puts( Daenerys ); return 0; } puts( Stannis ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 2; int pos[MAX], a[MAX]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, c = 0, k; cin >> n; for (int i = 1; i < n + 1; i++) cin >> k, a[k] = i, pos[i] = k; for (int i = 1; i < n + 1; i++) { if (pos[i] != i) { c++; int j = pos[i]; int k = a[i]; pos[k] = j; a[j] = k; a[i] = i; pos[i] = i; } } if ((3 * n + c) & 1) cout << Um_nik ; else cout << Petr ; }
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Top level module for a full setup with DUCs and DDCs
// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
// for debugging info. NB, This can kill the m'board and/or d'board if you
// have anything except basic d'boards installed.
// Uncomment the following to include optional circuitry
module usrp_sounder
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
output wire [13:0] tx_b,
output wire TXSYNC_A,
output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [2:0] usbctl,
output wire [1:0] usbrdy,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
inout wire [15:0] io_rx_b
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
// wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_pkt_rdy;
assign usbrdy[0] = 1'b0; // have_space;
assign usbrdy[1] = have_pkt_rdy;
wire tx_underrun, rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = 1'b0; // tx_underrun;
wire [15:0] usbdata_out;
wire [3:0] rx_numchan;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
assign clk64 = master_clk;
// TX
wire tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
wire [13:0] tx_i, tx_q;
wire [13:0] tx_dac;
dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
.strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
.tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
assign tx_a = tx_dac;
// Wedge DAC #2 at zero
assign TXSYNC_B = 1'b0;
assign tx_b = 14'b0;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
wire rx_sample_strobe, rx_strobe;
wire [15:0] rx_adc0_i, rx_adc0_q;
wire [15:0] rx_buf_i, rx_buf_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
.rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
.ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
.ddc1_in_i(),.ddc1_in_q(),
.ddc2_in_i(),.ddc2_in_q(),
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan) );
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(rx_buf_i),.ch_1(rx_buf_q),
.ch_2(),.ch_3(),
.ch_4(),.ch_5(),
.ch_6(),.ch_7(),
.rxclk(clk64),.rxstrobe(rx_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.debugbus() );
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Top level application
sounder sounder
( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
.rx_strobe_o(rx_strobe),.rx_imp_i_o(rx_buf_i),.rx_imp_q_o(rx_buf_q)
);
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = 0; // `TX_CAP_HB;
assign capabilities[6:4] = 2; // `TX_CAP_NCHAN;
assign capabilities[3] = 0; // `RX_CAP_HB;
assign capabilities[2:0] = 2; // `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(),.readback_5(),.readback_6(),.readback_7()
);
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(),.decim_rate(),
.tx_sample_strobe(),.strobe_interp(),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
.tx_empty(tx_empty),
.debug_0(),.debug_1(),
.debug_2(),.debug_3(),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
endmodule // usrp_sounder
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long dx[4] = {-1, 1, 0, 0}; const long long dy[4] = {0, 0, -1, 1}; const long long MAX = 5e3 + 5; long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long n, m, ans, k, Q; string second; bool pal[MAX][MAX]; long long cnt[MAX][MAX]; void solve() { for (int i = 0; i < n; ++i) pal[i][i] = cnt[i][i] = true; for (int i = 0; i < n - 1; ++i) { if (second[i] == second[i + 1]) pal[i][i + 1] = true, cnt[i][i + 1] = 1; cnt[i][i + 1] += 2; } for (int len = 3; len <= n; ++len) for (int i = 0; i < n - len + 1; ++i) { int j = i + len - 1; if (second[i] == second[j] && pal[i + 1][j - 1]) pal[i][j] = true; else pal[i][j] = false; cnt[i][j] = pal[i][j] + cnt[i][j - 1] + cnt[i + 1][j] - cnt[i + 1][j - 1]; } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> second; n = second.length(); solve(); cin >> Q; while (Q--) { int lo, hi; cin >> lo >> hi; --lo; --hi; cout << cnt[lo][hi] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 10; const double eps = 1e-6; const double mod = 1e9 + 7; struct num { int v, i; } b[MAX]; bool cmp(const num &x, const num &y) { return x.v > y.v; } bool cmp1(const num &x, const num &y) { return x.i < y.i; } int main() { int m, a[MAX]; cin >> m; for (int i = 1; i <= m; i++) cin >> a[i]; for (int i = 1; i <= m; i++) cin >> b[i].v, b[i].i = i; sort(a + 1, a + m + 1); sort(b + 1, b + m + 1, cmp); for (int i = 1; i <= m; i++) b[i].v = a[i]; sort(b + 1, b + m + 1, cmp1); for (int i = 1; i <= m; i++) cout << b[i].v << ; putchar( n ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O21AI_PP_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (y == 0) return x; else return gcd(y, x % y); } int lcm(int x, int y) { return x / gcd(x, y) * y; } int binpow(int a, int p) { if (!p) return 1; int g = binpow(a, p >> 1); if (p % 2 == 0) return (g * g) % 1000000007; else return (((g * g) % 1000000007) * a) % 1000000007; } int rev(int n) { return binpow(n, 1000000007 - 2); } void solve(); int main() { cout.setf(ios::fixed); cout.precision(20); cerr.setf(ios::fixed); cerr.precision(3); int n = 1; for (int i = 0; i < n; ++i) solve(); } long long a[100100]; long long n; long long r[100100]; void solve() { cin >> n; int i; for (i = 0; i < n; i++) cin >> a[i]; r[0] = a[0]; for (i = 1; i < n; i++) r[i] = max(r[i - 1], a[i]); int m; cin >> m; long long len, sz; for (i = 0; i < m; i++) { cin >> len >> sz; cout << max(r[0], r[len - 1]) << endl; r[0] = max(r[0], r[len - 1]) + sz; } }
|
#include <bits/stdc++.h> using namespace std; long long find_seat(char c) { if (c == a ) return 4; if (c == b ) return 5; if (c == c ) return 6; if (c == d ) return 3; if (c == e ) return 2; if (c == f ) return 1; } int main() { long long one, two, a, b, d, n, i, res; char c; while (scanf( %lld%c , &n, &c) != EOF) { one = two = false; a = n % 4; if (a == 1 || a == 2) one = true; else two = true; if (n % 2 == 0) b = 1; else b = 0; res = 0; if (one) { res = n - 1; d = (n - a) / 4; d = d * 2 * 6; d += b * 6; } else { res = n - 3; d = (n - a) / 4; if (n % 2 == 0) d--; d = d * 2 * 6; d += b * 6; } res += d + find_seat(c); printf( %lld n , res); } return 0; }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The OITF (Oustanding Instructions Track FIFO) to hold all the non-ALU long
// pipeline instruction's status and information
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_oitf (
output dis_ready,
input dis_ena,
input ret_ena,
output [`E203_ITAG_WIDTH-1:0] dis_ptr,
output [`E203_ITAG_WIDTH-1:0] ret_ptr,
output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
output ret_rdwen,
output ret_rdfpu,
output [`E203_PC_SIZE-1:0] ret_pc,
input disp_i_rs1en,
input disp_i_rs2en,
input disp_i_rs3en,
input disp_i_rdwen,
input disp_i_rs1fpu,
input disp_i_rs2fpu,
input disp_i_rs3fpu,
input disp_i_rdfpu,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
input [`E203_PC_SIZE -1:0] disp_i_pc,
output oitfrd_match_disprs1,
output oitfrd_match_disprs2,
output oitfrd_match_disprs3,
output oitfrd_match_disprd,
output oitf_empty,
input clk,
input rst_n
);
wire [`E203_OITF_DEPTH-1:0] vld_set;
wire [`E203_OITF_DEPTH-1:0] vld_clr;
wire [`E203_OITF_DEPTH-1:0] vld_ena;
wire [`E203_OITF_DEPTH-1:0] vld_nxt;
wire [`E203_OITF_DEPTH-1:0] vld_r;
wire [`E203_OITF_DEPTH-1:0] rdwen_r;
wire [`E203_OITF_DEPTH-1:0] rdfpu_r;
wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];
// The PC here is to be used at wback stage to track out the
// PC of exception of long-pipe instruction
wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];
wire alc_ptr_ena = dis_ena;
wire ret_ptr_ena = ret_ena;
wire oitf_full ;
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;
generate
if(`E203_OITF_DEPTH > 1) begin: depth_gt1//{
wire alc_ptr_flg_r;
wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt;
assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
wire ret_ptr_flg_r;
wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt;
assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
assign oitf_empty = (ret_ptr_r == alc_ptr_r) & (ret_ptr_flg_r == alc_ptr_flg_r);
assign oitf_full = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
end//}
else begin: depth_eq1//}{
assign alc_ptr_r =1'b0;
assign ret_ptr_r =1'b0;
assign oitf_empty = ~vld_r[0];
assign oitf_full = vld_r[0];
end//}
endgenerate//}
assign ret_ptr = ret_ptr_r;
assign dis_ptr = alc_ptr_r;
////
//// // If the OITF is not full, or it is under retiring, then it is ready to accept new dispatch
//// assign dis_ready = (~oitf_full) | ret_ena;
// To cut down the loop between ALU write-back valid --> oitf_ret_ena --> oitf_ready ---> dispatch_ready --- > alu_i_valid
// we exclude the ret_ena from the ready signal
assign dis_ready = (~oitf_full);
wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;
genvar i;
generate //{
for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries//{
assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
assign vld_ena[i] = vld_set[i] | vld_clr[i];
assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
//Payload only set, no need to clear
sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
sirv_gnrl_dffl #(`E203_PC_SIZE ) pc_dfflrs (vld_set[i], disp_i_pc , pc_r[i] , clk);
sirv_gnrl_dffl #(1) rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);
sirv_gnrl_dffl #(1) rdfpu_dfflrs(vld_set[i], disp_i_rdfpu, rdfpu_r[i], clk);
assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdfpu_r[i] == disp_i_rs1fpu) & (rdidx_r[i] == disp_i_rs1idx);
assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdfpu_r[i] == disp_i_rs2fpu) & (rdidx_r[i] == disp_i_rs2idx);
assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdfpu_r[i] == disp_i_rs3fpu) & (rdidx_r[i] == disp_i_rs3idx);
assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdfpu_r[i] == disp_i_rdfpu ) & (rdidx_r[i] == disp_i_rdidx );
end//}
endgenerate//}
assign oitfrd_match_disprs1 = |rd_match_rs1idx;
assign oitfrd_match_disprs2 = |rd_match_rs2idx;
assign oitfrd_match_disprs3 = |rd_match_rs3idx;
assign oitfrd_match_disprd = |rd_match_rdidx ;
assign ret_rdidx = rdidx_r[ret_ptr];
assign ret_pc = pc_r [ret_ptr];
assign ret_rdwen = rdwen_r[ret_ptr];
assign ret_rdfpu = rdfpu_r[ret_ptr];
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( avx2 ) using namespace std; long long one = 1; const long long INF = 1e18; const long long MOD = 1e9 + 7; const long long N = 2e5; vector<vector<long long> > c, gr; vector<long long> res; bool flag = 1; long long dfs1(long long v, long long p, long long j, long long k) { long long ans = c[j][v]; if (gr[v].size() > 2) flag = 0; for (long long u : gr[v]) { if (u == p) continue; ans += dfs1(u, v, k, 3 - j - k); } return ans; } void dfs2(long long v, long long p, long long j, long long k) { res[v] = j + 1; for (long long u : gr[v]) { if (u == p) continue; dfs2(u, v, k, 3 - j - k); } } signed main() { long long n; cin >> n; c.resize(3); for (long long i = 0; i < 3; i++) { c[i].resize(n); for (long long j = 0; j < n; j++) cin >> c[i][j]; } gr.resize(n); for (long long i = 0; i < n - 1; i++) { long long v, u; cin >> v >> u; v--; u--; gr[v].push_back(u); gr[u].push_back(v); } long long st = -1; for (long long i = 0; i < n; i++) { if (gr[i].size() == 1) st = i; } long long ans = INF, ansj = -1, ansk = -1; for (long long j = 0; j < 3; j++) { for (long long k = 0; k < 3; k++) { if (j == k) continue; long long smth = dfs1(st, -1, j, k); assert(smth >= 0); if (smth < ans) { ans = smth; ansj = j; ansk = k; } } } if (flag == 0) { cout << -1 << endl; return 0; } if (n > 20000) { } res.resize(n); cout << ans << endl; dfs2(st, -1, ansj, ansk); for (long long i : res) cout << i << ; }
|
#include <bits/stdc++.h> using namespace std; string generateString(int a) { string s = ; for (int i = 0; i < a; i++) { char x = a + i; s = s + x; } return s; } string wrapAround(string s, int b, int c) { int x = c - b; for (int i = 0; i < x; i++) { s += s[i % b]; } return s; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; int A[n]; for (int i = 0; i < n; i++) { cin >> A[i]; } vector<vector<int> > v; for (int i = 0; i < 26; i++) { vector<int> x(n + 1, 0); v.push_back(x); } for (int j = 0; j < n; j++) { v[A[j] - 1][j + 1]++; } for (int i = 0; i < 26; i++) { for (int j = 1; j < n + 1; j++) { v[i][j] += v[i][j - 1]; } } vector<vector<int> > pos; pos.resize(26); for (int i = 0; i < n; i++) { pos[A[i] - 1].push_back(i); } int ans = 1; for (int i = 0; i < 26; i++) { int sz = pos[i].size(); int lim = sz / 2; if (sz != 0) { for (int k = 0; k < lim; k++) { int st = pos[i][k]; int en = pos[i][sz - k - 1]; int temp = 0; for (int j = 0; j < 26; j++) { int x = v[j][en] - v[j][st + 1]; temp = max(x, temp); } ans = max(ans, 2 * (k + 1) + temp); } } } cout << ans << n ; } }
|
///////////////////////////////////////////////////////////////////////////////
// tx_queue.v. Derived from NetFPGA project.
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: tx_queue.v 2080 2007-08-02 17:19:29Z grg $
//
// Module: tx_queue.v
// Project: NF2.1
// Description: Instantiates the speed matching FIFO that accepts
// packets from the core and sends it to the MAC
//
// On the read side is the 125/12.5/1.25MHz MAC clock which reads
// data 9 bits wide from the fifo (bit 8 is EOP).
//
///////////////////////////////////////////////////////////////////////////////
module dma_tx_queue
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter ENABLE_HEADER = 1,
parameter STAGE_NUMBER = 'hff,
parameter AXI_DATA_WIDTH = 32,
parameter AXI_KEEP_WIDTH = AXI_DATA_WIDTH/8
)
(input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- MAC side signals (m_tx_axis_aclk domain)
input m_tx_axis_aclk,
output reg m_tx_axis_tvalid,
output [AXI_DATA_WIDTH - 1 : 0] m_tx_axis_tdata,
output reg m_tx_axis_tlast,
output reg [AXI_KEEP_WIDTH - 1 : 0] m_tx_axis_tkeep,
input m_tx_axis_tready,
// --- Register interface
//input tx_queue_en,
//output tx_pkt_sent,
output reg tx_pkt_stored,
output reg [11:0] tx_pkt_byte_cnt,
output reg tx_pkt_byte_cnt_vld,
output reg [9:0] tx_pkt_word_cnt,
// --- Misc
input reset,
input clk
);
// ------------ Internal Params --------
//state machine states (one-hot)
localparam IDLE = 1;
localparam WAIT_FOR_READY = 2;
localparam WAIT_FOR_EOP = 4;
localparam INPUT_IDLE = 1;
localparam INPUT_PKTS = 2;
// Number of packets waiting:
//
// 4096 / 64 = 64 = 2**6
//
// so, need 7 bits to represent the number of packets waiting
localparam NUM_PKTS_WAITING_WIDTH = 7;
// ------------- Regs/ wires -----------
wire [DATA_WIDTH+CTRL_WIDTH - 1 : 0] tx_fifo_din;
wire [AXI_DATA_WIDTH - 1 : 0] tx_fifo_out_data;
wire [AXI_KEEP_WIDTH - 1 : 0] tx_fifo_out_ctrl;
reg tx_fifo_rd_en;
wire tx_fifo_empty;
wire tx_fifo_almost_full;
reg reset_txclk;
reg pkt_sent_txclk; // pulses when a packet has been removed
reg [4:0] tx_mac_state_nxt, tx_mac_state;
reg m_tx_axis_tvalid_nxt;
reg tx_queue_en_txclk;
reg [NUM_PKTS_WAITING_WIDTH-1:0] txf_num_pkts_waiting;
wire txf_pkts_avail;
reg [4:0] tx_input_state, tx_input_state_nxt;
reg tx_fifo_wr_en;
reg need_clear_padding;
assign in_rdy = ~tx_fifo_almost_full;
//--------------------------------------------------------------
// synchronize
//--------------------------------------------------------------
// extend reset over to MAC domain
reg reset_long;
// synthesis attribute ASYNC_REG of reset_long is TRUE ;
always @(posedge clk) begin
if (reset) reset_long <= 1;
else if (reset_txclk) reset_long <= 0;
end
always @(posedge m_tx_axis_aclk) reset_txclk <= reset_long;
//---------------------------------------------------------------
// packet fifo input and output logic
//---------------------------------------------------------------
assign tx_fifo_din = {in_ctrl[7:4], in_data[63:32],in_ctrl[3:0], in_data[31:0]};
/*fifo_72_to_36 #(.WIDTH(DATA_WIDTH+CTRL_WIDTH),.MAX_DEPTH_BITS(5))
fifo_72_to_36
( .din (tx_fifo_din), // Data in
.wr_en (tx_fifo_wr_en), // Write enable
.rd_en (tx_fifo_rd_en), // Read the next word
.dout ({tx_fifo_out_ctrl, tx_fifo_out_data}),
.full (),
.prog_full (tx_fifo_almost_full),
.nearly_full (),
.empty (tx_fifo_empty),
.reset (reset),
.clk (clk)
);*/
txfifo_512x72_to_36 gmac_tx_fifo
(
.din (tx_fifo_din),
.wr_en (tx_fifo_wr_en),
.wr_clk (clk),
.dout ({tx_fifo_out_ctrl,tx_fifo_out_data}),
.rd_en (tx_fifo_rd_en),
.rd_clk (m_tx_axis_aclk),
.empty (tx_fifo_empty),
.full (),
.almost_full(tx_fifo_almost_full),
.rst (reset)
);
// Reorder the output: AXI-S uses little endian, the User Data Path uses big endian
generate
genvar k;
for(k=0; k<AXI_KEEP_WIDTH; k=k+1) begin: reorder_endianness
assign m_tx_axis_tdata[8*k+:8] = tx_fifo_out_data[AXI_DATA_WIDTH-8-8*k+:8];
end
endgenerate
//----------------------------------------------------------
//input state machine.
//Following is in core clock domain (62MHz/125 MHz)
//----------------------------------------------------------
always @(*)begin
tx_fifo_wr_en = 0;
tx_pkt_stored = 0;
tx_pkt_byte_cnt = 0;
tx_pkt_byte_cnt_vld = 0;
tx_pkt_word_cnt = 0;
tx_input_state_nxt = tx_input_state;
case (tx_input_state)
INPUT_IDLE: begin
if(in_wr && in_ctrl == STAGE_NUMBER)begin
tx_pkt_byte_cnt = in_data[`IOQ_BYTE_LEN_POS +: 16]+8;
tx_pkt_word_cnt = in_data[`IOQ_WORD_LEN_POS +: 16]+2;
tx_pkt_byte_cnt_vld = 1'b1;
end
else if(in_wr && in_ctrl == 8'hee)
tx_fifo_wr_en = 1'b1;
else if(in_wr && in_ctrl == 0)begin //just ignore other module header
tx_fifo_wr_en = 1'b1;
tx_input_state_nxt = INPUT_PKTS;
end
end
INPUT_PKTS: begin
if(in_wr)begin
tx_fifo_wr_en = 1'b1;
if(|in_ctrl) begin
//tx_pkt_stored = 1'b1;
tx_input_state_nxt = INPUT_IDLE;
end
end
end
endcase
end
always @(posedge clk) begin
if(reset) begin
tx_input_state <= INPUT_IDLE;
end
else tx_input_state <= tx_input_state_nxt;
end
always @* begin
tx_mac_state_nxt = tx_mac_state;
tx_fifo_rd_en = 1'b0;
m_tx_axis_tvalid_nxt = 1'b0;
pkt_sent_txclk = 1'b0;
case (tx_mac_state)
IDLE: if ( !tx_fifo_empty ) begin //txf_pkts_avail &
tx_fifo_rd_en = 1; // this will make DOUT of FIFO valid after the NEXT clock
m_tx_axis_tvalid_nxt = 1;
tx_mac_state_nxt = WAIT_FOR_READY;
end
WAIT_FOR_READY:begin
m_tx_axis_tvalid_nxt = 1;
if(!tx_fifo_empty && m_tx_axis_tready)begin
tx_fifo_rd_en = 1;
if(tx_fifo_out_ctrl==0)
tx_mac_state_nxt = WAIT_FOR_EOP;
end
end
WAIT_FOR_EOP: begin
m_tx_axis_tvalid_nxt = 1;
if(|tx_fifo_out_ctrl) begin
pkt_sent_txclk = 1;
m_tx_axis_tvalid_nxt = 0;
tx_mac_state_nxt = IDLE;
if (need_clear_padding) begin // the last data byte was the last of the word so we are done.
tx_fifo_rd_en = 1;
end
else tx_fifo_rd_en = 0;
end
else if(!tx_fifo_empty && m_tx_axis_tready)begin // Not EOP - keep reading!
tx_fifo_rd_en = 1;
//m_tx_axis_tvalid_nxt = 1;
end
end
endcase
end
always @(*)begin
if(tx_mac_state == WAIT_FOR_READY || tx_mac_state == WAIT_FOR_EOP)begin
case (tx_fifo_out_ctrl)
4'b1000: begin
m_tx_axis_tkeep = 4'b0001;
m_tx_axis_tlast = 1'b1;
end
4'b0100: begin
m_tx_axis_tkeep = 4'b0011;
m_tx_axis_tlast = 1'b1;
end
4'b0010: begin
m_tx_axis_tkeep = 4'b0111;
m_tx_axis_tlast = 1'b1;
end
4'b0001: begin
m_tx_axis_tkeep = 4'b1111;
m_tx_axis_tlast = 1'b1;
end
default: begin
m_tx_axis_tlast = 1'b0;
m_tx_axis_tkeep = 4'b1111;
end
endcase
end
else begin
m_tx_axis_tkeep = 1'b0;
m_tx_axis_tlast = 1'b0;
end
end
// update sequential elements
always @(posedge m_tx_axis_aclk) begin
if (reset_txclk) begin
tx_mac_state <= IDLE;
m_tx_axis_tvalid <= 0;
need_clear_padding <= 0;
end
else begin
tx_mac_state <= tx_mac_state_nxt;
m_tx_axis_tvalid <= m_tx_axis_tvalid_nxt;
if(tx_fifo_rd_en) need_clear_padding <= !need_clear_padding;
end
end // always @ (posedge m_tx_axis_aclk)
endmodule // tx_queue
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h1F3;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 499;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE1_SOC(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// PS2 //////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
//////////// SW //////////
input [9:0] SW,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire sys_clk;
pll pll_inst(
.refclk(CLOCK_50),
.rst(!KEY[0]),
.outclk_0(VGA_CLK), // 25 MHz
.outclk_1(sys_clk) // 100 MHz
);
//=======================================================
// Structural coding
//=======================================================
// If it is not required to encode sync
// information onto the ADV7123, the SYNC input should be tied
// to logic low. datasheet p.18
assign VGA_SYNC_N = 1'b0;
vga_controller vga_ins(
.reset(!KEY[0]),
.sys_clk(sys_clk),
.vga_clk(VGA_CLK),
.blank_n(VGA_BLANK_N),
.HS(VGA_HS),
.VS(VGA_VS),
.red(VGA_R),
.green(VGA_G),
.blue(VGA_B)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; int size[maxn], dep[maxn], val[maxn], dfn[maxn], hson[maxn], ans[maxn], rnk[maxn]; int cnt[(1 << 22) + 4]; struct EDGE { int to, next; char c; } edge[maxn << 1]; int head[maxn], tot, num; void addedge(int u, int v, char c) { edge[++tot].next = head[u]; edge[tot].to = v; edge[tot].c = c; head[u] = tot; } void dfs(int now, int pre) { size[now] = 1; dep[now] = dep[pre] + 1; dfn[now] = ++num; rnk[num] = now; for (int i = head[now]; i; i = edge[i].next) { int to = edge[i].to; if (to == pre) continue; val[to] = val[now] ^ (1 << (edge[i].c - a )); dfs(to, now); size[now] += size[to]; if (size[to] > size[hson[now]]) hson[now] = to; } } void cal(int now) { if (cnt[val[now]]) ans[now] = max(ans[now], cnt[val[now]] - dep[now]); for (int i = 0; i < 22; ++i) { if (cnt[val[now] ^ (1 << i)]) ans[now] = max(ans[now], cnt[val[now] ^ (1 << i)] - dep[now]); } cnt[val[now]] = max(cnt[val[now]], dep[now]); for (int i = head[now]; i; i = edge[i].next) { int to = edge[i].to; if (dep[to] < dep[now] || to == hson[now]) continue; for (int j = dfn[to]; j <= dfn[to] + size[to] - 1; ++j) { int tmp = rnk[j]; if (cnt[val[tmp]]) ans[now] = max(ans[now], cnt[val[tmp]] + dep[tmp] - 2 * dep[now]); for (int i = 0; i < 22; ++i) { if (cnt[val[tmp] ^ (1 << i)]) ans[now] = max(ans[now], cnt[val[tmp] ^ (1 << i)] + dep[tmp] - 2 * dep[now]); } } for (int j = dfn[to]; j <= dfn[to] + size[to] - 1; ++j) { int tmp = rnk[j]; cnt[val[tmp]] = max(cnt[val[tmp]], dep[tmp]); } } } void dfs2(int now, bool heave) { for (int i = head[now]; i; i = edge[i].next) { int to = edge[i].to; if (dep[to] < dep[now] || to == hson[now]) continue; dfs2(to, 0); ans[now] = max(ans[now], ans[to]); } if (hson[now]) dfs2(hson[now], 1), ans[now] = max(ans[now], ans[hson[now]]); cal(now); if (!heave) for (int i = dfn[now]; i <= dfn[now] + size[now] - 1; ++i) cnt[val[rnk[i]]] = 0; } int main() { int n; scanf( %d , &n); for (int i = 2; i <= n; ++i) { int to; char c; scanf( %d %c , &to, &c); addedge(i, to, c); addedge(to, i, c); } dfs(1, 0); dfs2(1, 0); for (int i = 1; i <= n; ++i) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int maxn, n, t, x; int main() { cin >> n; for (int i = 1; i <= n; i++) { int in1, in2; cin >> in1 >> in2; x -= in1 - t; if (x < 0) x = 0; x += in2; maxn = max(maxn, x); t = in1; } cout << t + x << << maxn; return 0; }
|
#include <bits/stdc++.h> int main(int argc, char** argv) { int32_t num_queries; std::cin >> num_queries; for (int32_t i = 0; i < num_queries; i++) { int32_t num_sticks; std::cin >> num_sticks; if (num_sticks == 2) std::cout << 2 << std::endl; else if (num_sticks % 2 == 0) std::cout << 0 << std::endl; else std::cout << 1 << std::endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_PP_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2bb2oi (
VPWR,
VGND,
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire nor1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
typedef struct packed {
logic [7:0] a;
} tb_t;
typedef struct packed {
// verilator lint_off LITENDIAN
logic [0:7] a;
// verilator lint_on LITENDIAN
} tl_t;
typedef struct packed {
logic [7:0] bb;
// verilator lint_off LITENDIAN
tb_t [0:1] cbl;
tb_t [1:0] cbb;
tl_t [0:1] cll;
tl_t [1:0] clb;
logic [0:7] dl;
// verilator lint_on LITENDIAN
} t2;
logic [2:0][31:0] test2l;
// verilator lint_off LITENDIAN
logic [0:2][31:0] test2b;
logic [0:2][31:0] test1b;
// verilator lint_on LITENDIAN
logic [2:0][31:0] test1l;
module t;
t2 t;
initial begin
t = 80'hcd_1f2f3f4f_5f6f7f8f_c2;
`checkh(t.bb, 8'hcd);
`checkh(t.cbl[0].a, 8'h1f);
`checkh(t.cbl[1].a, 8'h2f);
`checkh(t.cbb[0].a, 8'h4f);
`checkh(t.cbb[1].a, 8'h3f);
`checkh(t.cll[0].a, 8'h5f);
`checkh(t.cll[1].a, 8'h6f);
`checkh(t.clb[0].a, 8'h8f);
`checkh(t.clb[1].a, 8'h7f);
`checkh(t.dl, 8'hc2);
t = '0;
t.bb = 8'h13;
t.cbl[0].a = 8'hac;
t.cbl[1].a = 8'had;
t.cbb[0].a = 8'hae;
t.cbb[1].a = 8'haf;
t.cll[0].a = 8'hbc;
t.cll[1].a = 8'hbd;
t.clb[0].a = 8'hbe;
t.clb[1].a = 8'hbf;
t.dl = 8'h31;
`checkh(t, 80'h13_acadafae_bcbdbfbe_31);
t = '0;
t.bb[7] = 1'b1;
t.cbl[1].a[1] = 1'b1;
t.cbb[1].a[2] = 1'b1;
t.cll[1].a[3] = 1'b1;
t.clb[1].a[4] = 1'b1;
t.dl[7] = 1'b1;
`checkh(t, 80'h80_0002040000100800_01);
test1b = '{0, 1, 2};
test1l = test1b;
test2l = '{2, 1, 0};
test2b = test2l;
`checkh(test2l[0], 0);
`checkh(test2l[2], 2);
`checkh(test2l, {32'h2, 32'h1, 32'h0});
`checkh(test2b[0], 2);
`checkh(test2b[2], 0);
`checkh(test2b, {32'h2, 32'h1, 32'h0});
`checkh(test1b[0], 0);
`checkh(test1b[2], 2);
`checkh(test1b, {32'h0, 32'h1, 32'h2});
`checkh(test1l[0], 2);
`checkh(test1l[2], 0);
`checkh(test1l, {32'h0, 32'h1, 32'h2});
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_csrbrg();
reg sys_clk;
reg sys_rst;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [13:0] csr_a;
wire csr_we;
wire [31:0] csr_do;
reg [31:0] csr_di;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
csrbrg dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
/* CSR bus master */
.csr_a(csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
/* Simulate CSR slave */
reg [31:0] csr1;
reg [31:0] csr2;
wire csr_selected = (csr_a[13:10] == 4'ha);
always @(posedge sys_clk) begin
if(csr_selected) begin
if(csr_we) begin
$display("Writing %x to CSR %x", csr_do, csr_a[0]);
case(csr_a[0])
1'b0: csr1 <= csr_do;
1'b1: csr2 <= csr_do;
endcase
end
case(csr_a[0])
1'b0: csr_di <= csr1;
1'b1: csr_di <= csr2;
endcase
end else
/* we must set data to 0 to be able to use a distributed OR topology
* in the slaves->master datapath.
*/
csr_di <= 32'd0;
end
always begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
/* Try some transfers */
wbwrite(32'h0000a000, 32'hcafebabe);
wbwrite(32'h0000a004, 32'habadface);
wbread(32'h0000a000);
wbread(32'h0000a004);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Max() { return -1000000007; } int Min() { return 1000000007; } template <typename... Args> int Max(int a, Args... args) { return max(a, Max(args...)); } template <typename... Args> int Min(int a, Args... args) { return min(a, Min(args...)); } long long a[7][7]; int main() { for (int i = (1); i <= (5); ++i) { for (int j = (1); j <= (5); ++j) { scanf( %lld , &a[i][j]); } } vector<long long> vc; for (int i = (1); i <= (5); ++i) vc.push_back((long long)i); long long ans = 0LL; do ans = max(ans, (a[vc[0]][vc[1]] + a[vc[1]][vc[0]]) + (a[vc[2]][vc[3]] + a[vc[3]][vc[2]]) + (a[vc[1]][vc[2]] + a[vc[2]][vc[1]]) + (a[vc[3]][vc[4]] + a[vc[4]][vc[3]]) + (a[vc[2]][vc[3]] + a[vc[3]][vc[2]]) + (a[vc[3]][vc[4]] + a[vc[4]][vc[3]])); while (next_permutation(vc.begin(), vc.end())); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int A[3] = {0}; int num; cin >> num; long ip; while (num--) { cin >> ip; if (ip % 3 == 0) A[0]++; else if (ip % 3 == 1) A[1]++; else if (ip % 3 == 2) A[2]++; } cout << A[0] / 2 + min(A[1], A[2]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[100007], b[100007], c[100007]; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i < n + 1; i++) cin >> a[i]; for (int i = 1; i < n + 1; i++) { if (a[i] > a[i - 1]) b[i] = b[i - 1] + 1; else b[i] = 1; } c[n] = 1; a[n + 1] = INT_MAX; for (int i = n - 1; i > 0; i--) { if (a[i + 1] > a[i]) c[i] = c[i + 1] + 1; else c[i] = 1; } int mx = 0; for (int i = 1; i < n + 1; i++) { if (b[i] + 1 <= n) mx = max(mx, b[i] + 1); else mx = max(mx, b[i]); if (a[i - 1] + 1 < a[i + 1]) mx = max(mx, b[i - 1] + c[i + 1] + 1); } cout << mx << endl; }
|
`default_nettype none
module CPU(clk,rst,start,
ReadData,MemAck,WriteData,MemAddr,MemEnable,MemWrite);
input clk,rst,start,MemAck;
input [255:0] ReadData;
output MemEnable,MemWrite;
output [255:0] WriteData;
output [31:0] MemAddr;
wire [31:0] InstrAddr,NextPC,NextPC_IF,Instr;
Adder Add_PC(
.data0 (InstrAddr),
.data1 (4),
.res (NextPC_IF)
);
wire MemStall;
PC PC(
.clk (clk),
.rst (rst),
.start (start),
.pc_i (NextPC),
.pc_o (InstrAddr),
.Stall (Stall|MemStall),
.Enable (1)
);
wire [31:0] BranchNextPC;
wire [27:0] Jaddr;
MUX32 mux1(NextPC_IF,Baddr,Branch&eq,BranchNextPC);
ShiftLeftTwo26 ShlJ(Instr_ID[25:0],Jaddr);
MUX32 mux2(BranchNextPC,{NextPC_IF[31:28],Jaddr},Jump,NextPC);//acceptable
Instruction_Memory InstrMem(
.addr (InstrAddr),
.instr (Instr)
);
wire Stall, MUXSel;
Hazard_Detection_unit HD(Instr_ID, Control_EX[8:8], Instr_EX[20:16], Stall, MUXSel);
wire [31:0] Instr_ID,NextPC_ID;
Pipeline_Registers IF_ID(
.clk (clk),
.Flush (Jump||(Branch&eq)),
.Stall (Stall|MemStall),
.Control_i (),
.Control (),
.Instr_i (Instr),
.Instr (Instr_ID),
.data0_i (),
.data0 (),
.data1_i (),
.data1 (),
.data2_i (NextPC_IF),
.data2 (NextPC_ID),
.RegAddr_i (),
.RegAddr ()
);
wire RegWrite,RegDst,ALUSrc,Branch,Jump,MemWrite_ID,MemRead,MemtoReg;
wire [1:0] ALUOp;
wire [31:0] RSdata,RTdata,RDdata,ALURes_WB,Control_WB,Imm;
wire [4:0] RegAddr_WB;
Control Control(
.Op (Instr_ID[31:26]),
.RegWrite (RegWrite),
.RegDst (RegDst),
.ALUSrc (ALUSrc),
.ALUOp (ALUOp),
.Branch (Branch),
.Jump (Jump),
.MemWrite (MemWrite_ID),
.MemRead (MemRead),
.MemtoReg (MemtoReg)
);
Registers Registers(
.clk (clk),
.RegWrite (Control_WB[0:0]),
.RSaddr (Instr_ID[25:21]),
.RTaddr (Instr_ID[20:16]),
.RDaddr (RegAddr_WB),
.RSdata (RSdata),
.RTdata (RTdata),
.RDdata (RDdata)
);
wire eq;
Comparator cmp(
.data0(RSdata),
.data1(RTdata),
.res(eq)
);
wire [31:0] Offset,Baddr;
Signed_Extend Sign_extend(Instr_ID[15:0],Imm);
ShiftLeftTwo32 ShlB(Imm,Offset);
Adder ADD(NextPC_ID,Offset,Baddr);
wire [31:0] Control_ID;
MUX32 mux8({22'b0,MemtoReg,MemRead,MemWrite_ID,Jump,Branch,ALUOp,ALUSrc,RegDst,RegWrite},0,MUXSel,Control_ID);
wire [31:0] Instr_EX,Control_EX,RSdata_EX,RTdata_EX,Imm_EX;
Pipeline_Registers ID_EX(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_ID),
.Control (Control_EX),
.Instr_i (Instr_ID),
.Instr (Instr_EX),
.data0_i (RSdata),
.data0 (RSdata_EX),
.data1_i (RTdata),
.data1 (RTdata_EX),
.data2_i (Imm),
.data2 (Imm_EX),
.RegAddr_i (),
.RegAddr ()
);
wire [2:0] ALUCtrl;
wire [31:0] ALUdata0,ALUdata1,ALURes,RTdata_FW;
ALU ALU(
.data0 (ALUdata0),
.data1 (ALUdata1),
.ALUCtrl (ALUCtrl),
.res (ALURes)
);
ALU_Control ALU_Control(
.func (Instr_EX[5:0]),
.ALUOp (Control_EX[4:3]),
.ALUCtrl (ALUCtrl)
);
wire [4:0] RegAddr;
wire [1:0] Ci_m6, Ci_m7;
Forwarding_unit FW(
.data0_i (Instr_EX[25:21]),
.data1_i (Instr_EX[20:16]),
.data2_i (RegAddr_MEM),
.data3_i (Control_MEM[0:0]),
.data4_i (RegAddr_WB),
.data5_i (Control_WB[0:0]),
.data0_o (Ci_m6),
.data1_o (Ci_m7)
);
TriMUX mux6(RSdata_EX,RDdata,ALURes_MEM,Ci_m6,ALUdata0);
TriMUX mux7(RTdata_EX,RDdata,ALURes_MEM,Ci_m7,RTdata_FW);
MUX5 mux3(Instr_EX[15:11],Instr_EX[20:16],Control_EX[1:1],RegAddr);
MUX32 mux4(RTdata_FW,Imm_EX,Control_EX[2:2],ALUdata1);
wire [31:0] Control_MEM,ALURes_MEM,RTdata_MEM;
wire [4:0] RegAddr_MEM;
Pipeline_Registers EX_MEM(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_EX),
.Control (Control_MEM),
.Instr_i (),
.Instr (),
.data0_i (ALURes),
.data0 (ALURes_MEM),
.data1_i (RTdata_FW),
.data1 (RTdata_MEM),
.data2_i (),
.data2 (),
.RegAddr_i (RegAddr),
.RegAddr (RegAddr_MEM)
);
wire [31:0] MemData,MemData_WB;
dcache_top dcache
(
.clk_i(clk),
.rst_i(rst),
.mem_data_i(ReadData),
.mem_ack_i(MemAck),
.mem_data_o(WriteData),
.mem_addr_o(MemAddr),
.mem_enable_o(MemEnable),
.mem_write_o(MemWrite),
.p1_data_i(RTdata_MEM),
.p1_addr_i(ALURes_MEM),
.p1_MemRead_i(Control_MEM[8]),
.p1_MemWrite_i(Control_MEM[7]),
.p1_data_o(MemData),
.p1_stall_o(MemStall)
);
Pipeline_Registers MEM_WB(
.clk (clk),
.Flush (0),
.Stall (MemStall),
.Control_i (Control_MEM),
.Control (Control_WB),
.Instr_i (),
.Instr (),
.data0_i (ALURes_MEM),
.data0 (ALURes_WB),
.data1_i (MemData),
.data1 (MemData_WB),
.data2_i (),
.data2 (),
.RegAddr_i (RegAddr_MEM),
.RegAddr (RegAddr_WB)
);
MUX32 mux5(ALURes_WB,MemData_WB,Control_WB[9:9],RDdata);
integer i;
parameter nop=32'b00000000000000000000000000100000; // add r0,r0,r0
initial begin
for(i=0;i<32;i=i+1)
Registers.register[i]=0;
//CPU.Registers.register[1]=1;
Control.Jump=0;
Control.Branch=0;
cmp.res=0;
HD.stall=0;
HD.MUXsel=0;
IF_ID.Instr=nop;
ID_EX.Instr=nop;
ID_EX.Control=0;
EX_MEM.Control=0;
MEM_WB.Control=0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool done1[33][2][2], done2[33][2][2], done3[33][2][2]; long long memo1[33][2][2], memo2[33][2][2], memo3[33][2][2]; long long lim; int n; long long dp1(int, int, int); long long dp2(int, int, int); long long dp3(int, int, int); long long dp1(int i, int s1, int s2) { if (done1[i][s1][s2]) return memo1[i][s1][s2]; done1[i][s1][s2] = true; long long &ret = memo1[i][s1][s2] = 0; int hd = (((lim) >> (n - 1 - i)) & 1), rr = (((lim) >> (i)) & 1); if (i * 2 + 1 == n) { if (!s1) ret = 1; else if (s2) ret = hd != 0; else { ret = 1; } } else if (i * 2 == n) { if (s1 && s2) ret = 0; else ret++; } else { ret += dp2(i + 1, s1 && hd == 0, 0 > rr || (0 == rr && s2)); ret += dp3(i + 1, s1 && hd == 0, 1 > rr || (1 == rr && s2)); } return ret; } long long dp2(int i, int s1, int s2) { if (done2[i][s1][s2]) return memo2[i][s1][s2]; done2[i][s1][s2] = true; long long &ret = memo2[i][s1][s2] = 0; int hd = (((lim) >> (n - 1 - i)) & 1), rr = (((lim) >> (i)) & 1); if (i * 2 + 1 == n) { if (!s1) ret = 2; else if (s2) ret = hd != 0; else { ret = hd + 1; } } else if (i * 2 == n) { if (s1 && s2) ret = 0; else ret++; } else { for (int x = 0; x <= (s1 ? hd : 1); x++) ret += dp2(i + 1, s1 && hd == x, x > rr || (x == rr && s2)); int ns1 = s1 && hd == 0, ns2 = 1 > rr || (1 == rr && s2); if (!ns1) ret += 1LL << (n - 2 * (i + 1)); else ret += ((lim >> (i + 1)) & ((1LL << (n - 2 * (i + 1))) - 1)) + 1; if (ns1 && ns2) ret--; } return ret; } long long dp3(int i, int s1, int s2) { if (done3[i][s1][s2]) return memo3[i][s1][s2]; done3[i][s1][s2] = true; long long &ret = memo3[i][s1][s2] = 0; int hd = (((lim) >> (n - 1 - i)) & 1), rr = (((lim) >> (i)) & 1); if (i * 2 + 1 == n) { if (!s1) ret = 1; else if (s2) ret = hd != 0; else { ret = 1; } } else if (i * 2 == n) { if (s1 && s2) ret = 0; else ret++; } else { ret += dp3(i + 1, s1 && hd == 0, 1 > rr || (1 == rr && s2)); if (!s1 || hd == 1) ret += dp3(i + 1, s1 && hd == 1, 0 > rr || (0 == rr && s2)); int ns1 = s1 && hd == 0, ns2 = 0 > rr || (0 == rr && s2); if (!ns1) ret += 1LL << (n - 2 * (i + 1)); else ret += ((lim >> (i + 1)) & ((1LL << (n - 2 * (i + 1))) - 1)) + 1; if (ns1 && ns2) ret--; } return ret; } void output(long long x, int n) { for (int i = 0; i < n; i++) cout << (((x) >> (n - i - 1)) & 1); cout << n ; } long long work(long long LIM) { lim = LIM; memset(done1, 0, sizeof(done1)); memset(done2, 0, sizeof(done2)); memset(done3, 0, sizeof(done3)); return dp1(0, 1, 0); } int main() { long long rank; cin >> n >> rank; rank++; long long lb = 0, rb = (1LL << n) - 1; for (long long mid = (lb + rb) / 2; lb < rb - 1; mid = (lb + rb) / 2) { if (work(mid) >= rank) rb = mid; else lb = mid; } if (work(rb) == rank) output(rb, n); else printf( -1 n ); }
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#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << n ; err(++it, args...); } const int M = 1e9 + 7, N = 2e5 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { int n, m; cin >> n >> m; int a[n][m], b[n][m]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int c = 0; if (i - 1 >= 0) c++; if (i + 1 <= n - 1) c++; if (j - 1 >= 0) c++; if (j + 1 <= m - 1) c++; b[i][j] = c; } } bool red = false; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] > b[i][j]) { red = true; break; } } if (red) break; } if (red) cout << NO << n ; else { cout << YES << n ; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cout << b[i][j] << n [j == m - 1]; ; } } }
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#include <bits/stdc++.h> using namespace std; int Number[12][12]; int Next[110]; double dp[110]; int main() { for (int i = 1; i <= 10; i++) for (int j = 1; j <= 10; j++) Number[i][j] = (10 - i) * 10 + (i % 2 == 0 ? j : 11 - j); for (int i = 1; i <= 10; i++) { for (int j = 1; j <= 10; j++) { int x; scanf( %d , &x); if (x == 0) Next[Number[i][j]] = Number[i][j]; else Next[Number[i][j]] = Number[i - x][j]; } } dp[100] = 0; double c = 1; for (int i = 99; i >= 94; i--) { dp[i] = (c + 6 - (100 - i)) / (100 - i); c += dp[i] + 1; } for (int i = 93; i >= 1; i--) { double temp = 0; for (int j = 1; j <= 6; j++) temp += min(dp[i + j], dp[Next[i + j]]); dp[i] = temp / 6 + 1; } printf( %.10f n , dp[1]); return 0; }
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#include <bits/stdc++.h> using namespace std; const int nsz = 1e5, ksz = 8, msksz = (1 << ksz) - 1, inf = 0x3f3f3f3f; bool vis[nsz + 5]; int n, m, k, full, p[nsz + 5], q[ksz + 5], dp[2][msksz + 5], ans; struct event { int pos, id, st; event(int pos = 0, int id = 0, int st = 0) { this->pos = pos, this->id = id, this->st = st; } }; vector<event> dat; bool inline operator<(event a, event b) { return a.pos != b.pos ? a.pos < b.pos : a.st < b.st; } void inline upd(int &a, int b) { a < b && (a = b); } string inline bin(int S, int len) { string s; for (int i = 0; i < len; ++i) { s += (S >> i & 1) ^ 48; } return s; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; ++i) { int l, r; scanf( %d%d , &l, &r); dat.push_back(event(l, i, +1)); dat.push_back(event(r + 1, i, -1)); } sort(dat.begin(), dat.end()); memset(dp, -inf, sizeof(dp)); int o = 0, x = 1, l = dat[0].pos, i = 0, k = 0; for (; i < dat.size() && dat[i].pos == l; ++i) { p[dat[i].id] = k; q[k] = dat[i].id; ++k; } full = (1 << k) - 1; for (int S = 0; S <= full; ++S) { dp[o][S] = 0; } for (; i < dat.size();) { l = dat[i].pos; int il = i, ir = i, len = dat[i].pos - dat[i - 1].pos, pk = k, dk = 0, pfull = full, dfull; memset(vis, 0, sizeof(vis)); for (; i < dat.size() && dat[i].pos == l; ++i, ++ir) { if (dat[i].st == -1) { --k; vis[p[dat[i].id]] = 1; } } for (int i = 0, j = 0; i < pk; ++i) { if (vis[i]) continue; p[q[i]] = j; q[j] = q[i]; ++j; } for (int i = il; i <= ir - 1; ++i) { if (dat[i].st == +1) { p[dat[i].id] = k; q[k] = dat[i].id; ++k; ++dk; } } full = (1 << k) - 1; dfull = (1 << dk) - 1; for (int S = 0; S <= pfull; ++S) { int val = dp[o][S] + (__builtin_popcount(S) & 1) * len, nS = 0, j = 0; if (val < 0) continue; for (int i = 0; i < pk; ++i) { if (vis[i]) continue; nS |= (S >> i & 1) << j; ++j; } if (dk <= 0) { upd(dp[x][nS], val); } else { for (int dS = 0; dS <= dfull; ++dS) { int nnS = nS | (dS << j); upd(dp[x][nnS], val); } } } swap(o, x); memset(dp[x], -inf, sizeof(dp[x])); } for (int S = 0; S <= full; ++S) { upd(ans, dp[o][S]); } printf( %d n , ans); }
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#include <bits/stdc++.h> using namespace std; const int PI = acos(-1); const int MAXN = 1e6; unsigned long long comb(unsigned long long n, unsigned long long k) { if (k > n) return 0; unsigned long long u = 1; for (unsigned long long i = 1; i <= k; i++) { u *= n--; u /= i; } return u; } int main() { unsigned long long n, m, t; while (cin >> n >> m >> t) { unsigned long long ans = 0; for (unsigned long long boys = 4; boys <= n; boys++) { unsigned long long girls = t - boys; if (girls > m) continue; if (t < 1 + boys) break; ans += comb(n, boys) * comb(m, girls); } cout << ans << endl; } return 0; }
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//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-27 18:38:13
// Last Modified : 2016-10-10 15:30:54
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_FPU_PIPELINED_FPADDSUB2_vector_testing.v
// Created On : 2016-09-25 17:59:05
// Last Modified : 2016-09-27 18:36:46
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-25 12:25:16
// Last Modified : 2016-09-25 12:25:16
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
//==================================================================================================
// Filename : tb_uut2_vector_testing.v
// Created On : 2016-09-24 01:24:56
// Last Modified : 2016-09-24 01:24:56
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : Testbench simulating the behavior and stimuli of the FPADD/FPSUB Unit.
//
//
//==================================================================================================
`timescale 1ns/1ps
module tb_FPU_PIPELINED_FPADDSUB2_vector_testing (); /* this is automatically generated */
localparam PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR=26;
parameter EWR = 5; //Single Precision */
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// MODULE SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg clk;
reg rst;
reg beg_OP;
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
reg add_subt;
wire busy;
wire overflow_flag;
wire underflow_flag;
wire zero_flag;
wire [W-1:0] final_result_ieee;
reg [SW-1:0] final_result_ieee_mantissa;
reg [EW-1:0] final_result_ieee_exponent;
reg final_result_ieee_sign;
wire ready;
//Temps for the testbench and verification
reg [SW-1:0] Data_X_mant;
reg [SW-1:0] Data_Y_mant;
reg [EW-1:0] Data_X_exp;
reg [EW-1:0] Data_Y_exp;
reg Data_X_sign;
reg Data_Y_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// TASKS VARIABLES
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// reg [W-1:0] formatted_number_W;
//reg overflow_flag_t, underflow_flag_t;
//reg [EWR-1:0] LZD_raw_val_EWR;
reg [W-1:0] Theoretical_result;
reg [SW-1:0] Theoretical_result_mantissa;
reg [EW-1:0] Theoretical_result_exponent;
reg Theoretical_result_sign;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// STIMULI SIGNALS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_3 [0:((2**PERIOD)-1)];
integer contador;
integer contador_theo_res;
integer FileSaveData;
integer logVectorReference;
integer Cont_CLK;
// integer Recept;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//
// END OF DECLARATIONS
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
`ifdef SINGLE
FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 inst_uut (
`endif
`ifdef DOUBLE
FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 inst_uut (
`endif
.clk (clk),
.rst (rst),
.beg_OP (beg_OP),
.Data_X (Data_X),
.Data_Y (Data_Y),
.add_subt (add_subt),
.busy (busy),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
always begin
#1;
final_result_ieee_mantissa = final_result_ieee[SW-1:0];
final_result_ieee_exponent = final_result_ieee[W-2:SW];
final_result_ieee_sign = final_result_ieee[W-1];
Data_X_mant = Data_X[SW-1:0];
Data_Y_mant = Data_Y[SW-1:0];
Data_X_exp = Data_X[W-2:SW];
Data_Y_exp = Data_Y[W-2:SW];
Data_X_sign = Data_X[W-1];
Data_Y_sign = Data_Y[W-1];
Theoretical_result_mantissa = Theoretical_result[SW-1:0];
Theoretical_result_exponent = Theoretical_result[W-2:SW];
Theoretical_result_sign = Theoretical_result[W-1];
end
// function [EWR-1:0] LZD_raw; // function definition starts here
// input [SWR-1:0] ADD_SUB_RAW;
// integer k;
// begin
// LZD_raw = 0;
// k=SWR-1;
// while(ADD_SUB_RAW[k] == 0) begin
// k = k-1;
// LZD_raw = LZD_raw + 1;
// $display("This is the bit analized %d\n", k);
// $display("This is the bit analized %d\n", ADD_SUB_RAW[k]);
// $display("Number of 0s %d\n", LZD_raw);
// end
// end
// endfunction
initial begin
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
logVectorReference = $fopen("output_log.txt","w");
contador_theo_res = 0;
rst = 1;
`ifdef SUB_OPER
add_subt = 1; //Se realiza la operacion de resta
`else
add_subt = 0; //Se realiza la operacion de suma
`endif
beg_OP = 0;
Data_Y = 0;
Data_X = 0;
Data_X_mant = 0;
Data_Y_mant = 0;
Data_X_exp = 0;
Data_Y_exp = 0;
Data_X_sign = 0;
Data_Y_sign = 0;
//Theoretical_result = 32'hbe1abef8;
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
#98 rst = 0;
//FPADD_FPSUB(0, Array_IN[3], Array_IN_2[3], formatted_number_W, overflow_flag_t, underflow_flag_t);
end
//**************************** Se lee el archivo txt y se almacena en un arrays***************************************************//
initial begin
$vcdpluson; //ESTO ES PARA LA OBTENCION DE LA POTENCIA DINAMICA, para esto necesitamos el .vcd
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
$readmemh("Hexadecimal_R.txt", Array_IN_3);
end
//**************************** Transmision de datos de forma paralela ************************************************************//
always @(posedge clk) begin
if (contador == (2**PERIOD+6)) begin
$fclose(FileSaveData);
$fclose(logVectorReference);
$finish;
$vcdplusclose;
end else if(ready) begin
$fwrite(FileSaveData,"%h\n",final_result_ieee);
end
end
always @(negedge clk) begin
if (ready==1) begin
Theoretical_result = Array_IN_3[contador_theo_res];
contador_theo_res = contador_theo_res + 1;
end
end
always @(negedge clk) begin
#(PERIOD/5);
if(~busy & ~rst) begin
beg_OP = 1;
end
end
always @(posedge clk) begin
#(PERIOD/5);
if(rst) begin
contador = 0;
end
else if(~busy & ~rst) begin
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
contador = contador + 1;
@(posedge clk)
#(PERIOD/3);
Data_X = Array_IN[contador];
Data_Y = Array_IN_2[contador];
contador = contador + 1;
repeat(3) @(posedge clk);
end
end
// clock
initial begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end
endmodule
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#include <bits/stdc++.h> using namespace std; inline bool cmin(int &x, int y) { return x > y ? x = y, 1 : 0; } inline bool cmax(int &x, int y) { return x < y ? x = y, 1 : 0; } const int _ = 1e5 + 55; int N, x; long long ans(0); priority_queue<int> A, B; int main() { scanf( %d , &N); for (int i(1), I(N); i <= I; ++i) scanf( %d , &x), A.push(x); for (int i(1), I(N); i <= I; ++i) scanf( %d , &x), B.push(x); for (int i(1), I(N); i <= I; ++i) { if (!A.size()) B.pop(); else if (!B.size()) ans += A.top(), A.pop(); else if (A.top() > B.top()) ans += A.top(), A.pop(); else B.pop(); if (!A.size()) ans -= B.top(), B.pop(); else if (!B.size()) A.pop(); else if (A.top() > B.top()) A.pop(); else ans -= B.top(), B.pop(); } printf( %lld n , ans); return 0; }
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// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
// Thanks to Dan Strother - http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
module dp_ram #(
parameter DATA = 16,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_SYMBOL_V
`define SKY130_FD_SC_LS__DFSBP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 10; const long double inf = 1e9 + 10; bool use(long double &f, long double w, long double a); int a[N], b[N]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 1; i <= n; ++i) { cin >> b[i]; } b[n + 1] = b[1]; long double lo = 0, hi = inf; for (int t = 0; t < 60; ++t) { long double mid = (lo + hi) / 2; long double f = mid; bool ok = true; for (int i = 1; i <= n; ++i) { if (!use(f, m, a[i])) { ok = false; break; } if (!use(f, m, b[i + 1])) { ok = false; break; } } if (ok) { hi = mid; } else { lo = mid; } } if (lo > 1e9) { cout << -1 << endl; } else { cout << fixed << setprecision(10) << lo << endl; } } bool use(long double &f, long double w, long double a) { if (f * a < f + w) { return false; } f -= (f + w) / a; return true; }
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#include <bits/stdc++.h> using namespace std; pair<int, int> temp[102][102]; int ans[102][102]; int main() { int n, m, q; cin >> n >> m >> q; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { temp[i][j].first = i; temp[i][j].second = j; } } while (q--) { int t; cin >> t; if (t == 1) { int r; cin >> r; pair<int, int> p; p = temp[r][1]; for (int j = 1; j < m; j++) { temp[r][j] = temp[r][j + 1]; } temp[r][m] = p; } else if (t == 2) { int c; cin >> c; pair<int, int> p; p = temp[1][c]; for (int j = 1; j < n; j++) { temp[j][c] = temp[j + 1][c]; } temp[n][c] = p; } else { int r, c, x; cin >> r >> c >> x; int indx1 = temp[r][c].first; int indx2 = temp[r][c].second; ans[indx1][indx2] = x; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cout << ans[i][j] << ; } cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; double a; int ans = 0; vector<int> v; int n, m; cin >> n; int ara1[n]; for (int i = 0; i < n; i++) cin >> ara1[i]; cin >> m; int ara2[m]; for (int i = 0; i < m; i++) cin >> ara2[i]; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { a = (double)ara2[i] / ara1[j]; if (a == (int)a) { int b = a; v.push_back(b); } } } sort(v.rbegin(), v.rend()); for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { a = (double)ara2[i] / ara1[j]; if (a == v[0]) ans++; } } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100010, M = N * 2, mod = 1e9 + 7; const double PI = acos(-1.0), eps = 1e-6; int T, n, m, k, c1, c2; int a[N * 10], b[N], tot, cnt[N], s[N * 10], ans; map<int, int> mp; vector<int> v; string g[N * 10]; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> g[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (i - 1 >= 0 && g[i - 1][j] == X && j - 1 >= 0 && g[i][j - 1] == X ) a[j + 1] = 1; for (int i = 1; i <= m; i++) s[i] = s[i - 1] + a[i]; int q; cin >> q; while (q--) { int l, r; cin >> l >> r; if (s[r] - s[l] > 0) cout << NO << n ; else cout << YES << n ; } return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; long long n, m, a[200010], dp[200010][2]; vector<pair<long long, long long> > allseg, okseg; vector<long long> hvseg[200010]; void solve() { long long i, j, l, r, mn, dx, dy; scanf( %lld%lld , &n, &m); a[0] = -1000000000000; a[n + 1] = 1000000000000; hvseg[0].clear(); for (i = 1; i <= n; i++) { hvseg[i].clear(); scanf( %lld , &a[i]); } hvseg[n + 1].clear(); sort(a, a + n + 2); allseg.clear(); for (i = 0; i < m; i++) { scanf( %lld%lld , &l, &r); allseg.push_back(make_pair(l, r)); } sort(allseg.begin(), allseg.end()); okseg.clear(); mn = 1000000000000; for (i = allseg.size() - 1; i >= 0; i--) { if (allseg[i].second >= mn) { continue; } mn = min(mn, allseg[i].second); l = lower_bound(a, a + n + 2, allseg[i].first) - a; r = upper_bound(a, a + n + 2, allseg[i].second) - a - 1; if (l <= r) { continue; } hvseg[r].push_back(okseg.size()); okseg.push_back(allseg[i]); } reverse(okseg.begin(), okseg.end()); for (i = 0; i <= n + 1; i++) { for (j = 0; j < hvseg[i].size(); j++) { hvseg[i][j] = okseg.size() - hvseg[i][j] - 1; } reverse(hvseg[i].begin(), hvseg[i].end()); } for (i = 0; i <= n + 1; i++) { dp[i][0] = dp[i][1] = 1000000000000; } dp[0][0] = dp[0][1] = 0; for (i = 1; i <= n + 1; i++) { for (dx = 0; dx < 2; dx++) { if (dp[i - 1][dx] >= 1000000000000) { continue; } for (dy = 0; dy < 2; dy++) { if (hvseg[i - 1].size() == 0) { dp[i][dy] = min(dp[i][dy], dp[i - 1][dx]); continue; } dp[i][dy] = min( dp[i][dy], dp[i - 1][dx] + (dx + 1) * (okseg[hvseg[i - 1][hvseg[i - 1].size() - 1]].first - a[i - 1])); dp[i][dy] = min( dp[i][dy], dp[i - 1][dx] + (2 - dy) * (a[i] - okseg[hvseg[i - 1][0]].second)); for (j = 0; j + 1 < hvseg[i - 1].size(); j++) { dp[i][dy] = min(dp[i][dy], dp[i - 1][dx] + (dx + 1) * (okseg[hvseg[i - 1][j]].first - a[i - 1]) + (2 - dy) * (a[i] - okseg[hvseg[i - 1][j + 1]].second)); } } } } printf( %lld n , min(dp[n + 1][0], dp[n + 1][1])); return; } int main() { long long T; scanf( %lld , &T); while (T--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_SYMBOL_V
`define SKY130_FD_SC_LS__O2111AI_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long x, y; vector<long long> cnt; vector<char> sol; bool ok; void solve(long long x, long long y) { if (!x) { if (y == 1) ok = 1; return; } if (!y) { if (x == 1) ok = 1; return; } if (x == y) { if (x == 1) ok = 1; return; } if (x > y) { sol.push_back( A ); if (x % y == 0) { cnt.push_back(x / y - 1); } else { cnt.push_back(x / y); } solve(x % y, y); } else { sol.push_back( B ); if (y % x == 0) { cnt.push_back(y / x - 1); } else { cnt.push_back(y / x); } solve(x, y % x); } } int main() { cin >> x >> y; solve(x, y); if (ok) { for (int i = 0; i < sol.size(); ++i) { cout << cnt[i] << sol[i]; } } else { cout << Impossible ; } return 0; }
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: tx_run_length_limiter
*
* Description:
* The idea is to break the counts up into manageable chunks. FPGAs have 6-input LUTs, so a
* reasonable granularity is 5. This means that we check 5 bits + the previous bit in every chunk.
*
* Granularity 1 should be more accurate, but uses more resources.
*
* When there are no bit flips in the input, count_top and count_bottom should be equal.
* Calculating them separately is faster and uses fewer resources.
*/
`default_nettype none
module tx_run_length_limiter #(
parameter LANE_WIDTH =64,
parameter GRANULARITY =4,
parameter RUN_LIMIT =85
)
(
input wire clk,
input wire res_n,
input wire enable,
input wire [LANE_WIDTH-1:0] data_in,
output reg [LANE_WIDTH-1:0] data_out,
output reg rf_bit_flip
);
localparam NUM_CHUNKS = (LANE_WIDTH + GRANULARITY-1)/(GRANULARITY);
localparam REM_BITS = LANE_WIDTH - (GRANULARITY * (LANE_WIDTH/GRANULARITY));
localparam COUNT_BITS = 8;
wire [NUM_CHUNKS-1:0] no_flip;
wire [NUM_CHUNKS-1:0] still_counting_top;
wire [NUM_CHUNKS-1:0] still_counting_bottom;
wire [COUNT_BITS-1:0] count_top;
wire [COUNT_BITS-1:0] count_top_part [NUM_CHUNKS-1:0];
wire [COUNT_BITS-1:0] count_bottom;
wire [COUNT_BITS-1:0] count_bottom_part [NUM_CHUNKS-1:0];
wire bit_flip;
reg [COUNT_BITS-1:0] count_bottom_d1;
reg no_flip_bottom_d1;
reg data_in_bottom_d1;
genvar chunk;
genvar chunkT;
genvar chunkB;
generate
assign no_flip[0] = &( {data_in[GRANULARITY-1:0],data_in_bottom_d1}) ||
&(~{data_in[GRANULARITY-1:0],data_in_bottom_d1});
for(chunk=1; chunk<NUM_CHUNKS-1; chunk=chunk+1) begin : no_flip_gen
assign no_flip[chunk] = &( data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]) ||
&(~data_in[(chunk+1)*(GRANULARITY)-1:chunk*(GRANULARITY)-1]);
end
assign no_flip[NUM_CHUNKS-1] = &( data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]) ||
&(~data_in[LANE_WIDTH-1:(NUM_CHUNKS-1)*(GRANULARITY)-1]);
// Start at the top and count until a flip is found
assign still_counting_top[0] = no_flip[0];
assign count_top_part[0] = (no_flip[0] ? GRANULARITY : 0);
for(chunkT=1; chunkT<NUM_CHUNKS; chunkT=chunkT+1) begin : count_top_gen
assign still_counting_top[chunkT] = still_counting_top[chunkT-1] && no_flip[chunkT];
assign count_top_part[chunkT] = (still_counting_top[chunkT] ? GRANULARITY : 0) + count_top_part[chunkT-1];
end
assign count_top = (still_counting_top[NUM_CHUNKS-1] ? LANE_WIDTH : // No flips found
count_top_part[NUM_CHUNKS-2]) + // Take the last value
(no_flip[0] ? (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : 0); // Add the saved count
// Start at the bottom and count until a flip is found
assign still_counting_bottom[0] = no_flip[NUM_CHUNKS-1];
assign count_bottom_part[0] = 0;
for(chunkB=1; chunkB<NUM_CHUNKS; chunkB=chunkB+1) begin : count_bottom_gen
assign still_counting_bottom[chunkB] = still_counting_bottom[chunkB-1] && no_flip[NUM_CHUNKS-1-chunkB];
assign count_bottom_part[chunkB] = (still_counting_bottom[chunkB] ? GRANULARITY : 0) + count_bottom_part[chunkB-1];
end
assign count_bottom = still_counting_bottom[NUM_CHUNKS-1] ? LANE_WIDTH + (count_bottom_d1 == 0 ? 1 : count_bottom_d1) : // No flips found + saved count
count_bottom_part[NUM_CHUNKS-2] + // Take the last value
(no_flip[NUM_CHUNKS-1] ? (REM_BITS ? REM_BITS : GRANULARITY) + 1 : 0); // Add the remainder
endgenerate
assign bit_flip = count_top > (RUN_LIMIT - (GRANULARITY-1) - (REM_BITS ? REM_BITS-1 : GRANULARITY-1));
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) begin `else
always @(posedge clk) begin `endif
`ifdef RESET_ALL
if(!res_n) begin
data_out <= {DWIDTH {1'b0}};
end else
`endif
begin
if (enable && bit_flip) begin
data_out <= {data_in[LANE_WIDTH-1:1], ~data_in[0]};
end else begin
data_out <= data_in;
end
end
if (!res_n) begin
count_bottom_d1 <= { COUNT_BITS {1'b0}};
no_flip_bottom_d1 <= 1'b0;
data_in_bottom_d1 <= 1'b0;
rf_bit_flip <= 1'b0;
end else begin
count_bottom_d1 <= count_bottom;
no_flip_bottom_d1 <= no_flip[NUM_CHUNKS-1];
data_in_bottom_d1 <= data_in[LANE_WIDTH-1];
if (enable && bit_flip) begin
rf_bit_flip <= bit_flip;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mx = 110, Mod = 1e6 + 3; int C, W, H; struct Matrix { int val[mx][mx]; int n; Matrix(int _n = mx, int _base = 0) { n = _n; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) val[i][j] = (i == j ? _base : 0); } int* operator[](int x) { return val[x]; } }; Matrix operator*(Matrix A, Matrix B) { Matrix res(A.n); for (int i = 0; i < res.n; i++) for (int j = 0; j < res.n; j++) for (int k = 0; k < res.n; k++) res[i][k] = (0LL + res[i][k] + 1LL * A[i][j] * B[j][k]) % Mod; return res; } Matrix operator^(Matrix A, long long int B) { Matrix res(A.n, 1); while (B) { if (B & 1) res = res * A; A = A * A; B >>= 1; } return res; } int main() { scanf( %d%d%d , &C, &W, &H); Matrix res(W + 1); for (int i = 0; i <= W; i++) res[0][i] = 1, res[i + 1][i] = H; res = res ^ C; int ans = 0; for (int i = 0; i <= W; i++) ans = (0LL + ans + res[i][0]) % Mod; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &f) { f = 0; _T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { fu = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } const int N = 1e5 + 5; int st1[16][N][17], st2[16][N][17]; int a[N], lg[N]; int n; void make_st(int id) { for (int j = 1; j <= 16; j++) { for (int i = 1; i <= n - (1 << j) + 1; i++) { st1[id][i][j] = min(st1[id][i][j - 1], st1[id][i + (1 << (j - 1))][j - 1]); st2[id][i][j] = max(st2[id][i][j - 1], st2[id][i + (1 << (j - 1))][j - 1]); } } } int query1(int id, int l, int r) { int k = lg[r - l + 1]; return min(st1[id][l][k], st1[id][r - (1 << k) + 1][k]); } int query2(int id, int l, int r) { int k = lg[r - l + 1]; return max(st2[id][l][k], st2[id][r - (1 << k) + 1][k]); } int queryl(int base, int l, int r) { int ans = query1(base, max(l, 1), min(r, n)); if (l <= 0) ans = max(-n + 1, min(ans, query1(base, l + n, n) - n)); if (r > n) ans = max(-n + 1, min(ans, query1(base, 1, r - n) + n)); return ans; } int queryr(int base, int l, int r) { int ans = query2(base, max(l, 1), min(r, n)); if (l <= 0) ans = min(n * 2, max(ans, query2(base, l + n, n) - n)); if (r > n) ans = min(n * 2, max(ans, query2(base, 1, r - n) + n)); return ans; } int main() { read(n); if (n == 1) { print(0, n ); return 0; } lg[0] = -1; for (int i = 1; i <= n; i++) { read(a[i]); lg[i] = lg[i >> 1] + 1; st1[0][i][0] = i - a[i]; st2[0][i][0] = i + a[i]; } make_st(0); for (int base = 1; base <= 15; base++) { for (int i = 1; i <= n; i++) { int l = st1[base - 1][i][0], r = st2[base - 1][i][0]; st1[base][i][0] = queryl(base - 1, l, r); st2[base][i][0] = queryr(base - 1, l, r); } make_st(base); } for (int i = 1; i <= n; i++) { int l = i, r = i, ans = 0; for (int j = 15; j >= 0; j--) { int L = queryl(j, l, r), R = queryr(j, l, r); if (R - L + 1 < n) l = L, r = R, ans |= (1 << j); } print(ans + 1, i == n ? n : ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_TB_V
`define SKY130_FD_SC_HS__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_TB_V
|
#include <bits/stdc++.h> using namespace std; set<int> S; void dfs(int Cur, int dgt, int x, int y) { if (dgt == 11) return; if (Cur > 0) S.insert(Cur); dfs(Cur * 10 + x, dgt + 1, x, y); dfs(Cur * 10 + y, dgt + 1, x, y); return; } int main() { int n, Ans = 0; cin >> n; S.insert(1e9); for (int i = 0; i < 10; i++) { for (int j = 0; j < 10; j++) { dfs(0, 1, i, j); } } for (auto x : S) { if (x > n) break; else Ans++; } cout << Ans << endl; return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) int main() { int n, k; scanf( %d %d , &n, &k); int cnt = 0, a[100]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n; i++) { if (a[i] >= a[k - 1] && a[i] > 0) cnt++; } printf( %d , cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long MOD = 1e9 + 6; const long long inf = 2e18; const int maxn = 200005; const int maxa = 300005; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long powmod(long long a, long long b) { long long res = 1; a %= mod; if (b < 0) return -1; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long powmod2(long long a, long long b) { long long res = 1; a %= MOD; if (b < 0) return -1; for (; b; b >>= 1) { if (b & 1) res = res * a % MOD; a = a * a % MOD; } return res; } const int INF = 0x3f3f3f3f; int a[maxn]; vector<pair<int, int> > ans; vector<int> val[maxn]; int dis[maxn]; int main() { ios::sync_with_stdio(0); int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= m; i++) cin >> a[i]; int now = 2; int cnt = 1; val[0].push_back(1); for (int i = 1; i <= m; i++) { for (int j = 1; j <= a[i]; j++) { dis[now] = i; val[i].push_back(now++); } cnt += a[i] - 1; } if (k > cnt) { return 0 * puts( -1 ); } int lstpos = 0; int nowval = 0; for (int i = 2; i <= n; i++) { if (dis[i] > nowval) { nowval = dis[i]; lstpos = 0; } if (lstpos != val[dis[i] - 1].size() && cnt > k) { ans.push_back({i, val[dis[i] - 1][lstpos]}); if (lstpos != 0) { cnt--; } lstpos++; } else { ans.push_back({i, val[dis[i] - 1][0]}); } } if (k != cnt) { return 0 * puts( -1 ); } cout << n << endl; for (auto k : ans) { cout << k.first << << k.second << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; int n, q; int v[111111], c[111111]; long long first[111111]; long long calc(long long a, long long b) { int m1 = 0, m2 = 0; for (int i = 1; i <= n; ++i) first[i] = -inf; first[0] = 0; for (int i = 0; i < n; ++i) { int &cc = c[i], &vv = v[i]; long long cur = b * vv; if (first[cc] > -inf) { cur = max(cur, first[cc] + a * vv); } if (m1 != cc) { cur = max(cur, first[m1] + b * vv); } else if (m2 != cc) { cur = max(cur, first[m2] + b * vv); } if (cur > first[cc]) { first[cc] = cur; if (first[cc] > first[m1]) { m2 = m1, m1 = cc; } else if (first[cc] > first[m2] && cc != m1) { m2 = cc; } } } return first[m1]; } int main() { scanf( %d%d , &n, &q); for (int i = 0; i < n; ++i) scanf( %d , &v[i]); for (int i = 0; i < n; ++i) scanf( %d , &c[i]); while (q--) { int a, b; scanf( %d%d , &a, &b); cout << calc((long long)a, (long long)b) << endl; } return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
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// regulations governing limitations on product liability.
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:image_capture_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "image_capture_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_image_capture_manager_0_0,image_capture_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_image_capture_manager_0_0,image_capture_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=image_capture_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,START_IMAGE_CAPTURE_COMMAND=1,STOP_IMAGE_CAPTURE_COMMAND=2,RESET_IMAGE_CAPTURE_COMMAND=3,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=4}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_image_capture_manager_0_0 (
image_capture_enabled,
clear_memory,
reset,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
output wire image_capture_enabled;
output wire clear_memory;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
output wire reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
image_capture_manager #(
.START_IMAGE_CAPTURE_COMMAND(1),
.STOP_IMAGE_CAPTURE_COMMAND(2),
.RESET_IMAGE_CAPTURE_COMMAND(3),
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.image_capture_enabled(image_capture_enabled),
.clear_memory(clear_memory),
.reset(reset),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<bool> trust; vector<int> massive(int** mas, int num) { vector<int> mase; int nume = num; int nume1; while (nume != 0) { nume1 = nume; nume = mas[nume - 1][0]; } mase.push_back(0); while (nume1 != 0) { mase.push_back(nume1); trust[nume1 - 1] = true; nume1 = mas[nume1 - 1][1]; } mase.push_back(0); return mase; } int main() { int n; cin >> n; int** mas = new int*[n]; for (int i = 0; i < n; i++) { mas[i] = new int[2]; trust.push_back(false); cin >> mas[i][0] >> mas[i][1]; } vector<vector<int>> comp; for (int i = 0; i < n; i++) { vector<int> vect2; if (!trust[i]) { vect2 = massive(mas, i + 1); comp.push_back(vect2); } } vector<int> ansver; ansver.push_back(0); for (auto i : comp) { for (auto j : i) { if (j != 0) { ansver.push_back(j); } } } ansver.push_back(0); for (int i = 1; i < n + 1; i++) { for (int j = 0; j < ansver.size(); j++) { if (i == ansver[j]) { cout << ansver[j - 1] << << ansver[j + 1]; } } cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_1_V
`define SKY130_FD_SC_HS__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_1_V
|
module Mod_Teste(
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON,
output LCD_BLON,
output LCD_RW,
output LCD_EN,
output LCD_RS,
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
inout [7:0] LCD_DATA,
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW
);
// GPIO
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
assign LEDR[17:0] = CNTRL_bus[19:2];
assign LEDG[8:7] = CNTRL_bus[1:0];
assign LEDG[1:0] = {KEY[3],KEY[0]};
wire RST = KEY[0];
wire CLK = KEY[3];
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
parameter FLAG_WIDTH = 4;
Output_LiquidCyrstalDisplay_TestModule LCD0 (
.iCLK (CLOCK_50),
.iRST_N (KEY[0]),
.d0 (COUNTER_bus),
.d1 (INSTR_bus),
.d2 (CONST_bus),
.d3 (ADDR_bus),
.d4 (DATA_bus),
.d5 (D_bus),
.LCD_DATA (LCD_DATA),
.LCD_RW (LCD_RW),
.LCD_EN (LCD_EN),
.LCD_RS (LCD_RS)
);
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
Computer_ControlUnit_InstructionDecoder ID0 (
.CNTRL_bus_out(CNTRL_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam ID0.WORD_WIDTH = WORD_WIDTH;
defparam ID0.DR_WIDTH = DR_WIDTH;
defparam ID0.SB_WIDTH = DR_WIDTH;
defparam ID0.SA_WIDTH = DR_WIDTH;
defparam ID0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam ID0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam ID0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] INSTR_bus;
Computer_ControlUnit_InstructionMemory IM0 (
.INSTR_out(INSTR_bus),
.COUNTER_in(COUNTER_bus)
);
defparam IM0.WORD_WIDTH = WORD_WIDTH;
defparam IM0.DR_WIDTH = DR_WIDTH;
defparam IM0.SB_WIDTH = DR_WIDTH;
defparam IM0.SA_WIDTH = DR_WIDTH;
defparam IM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam IM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam IM0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] COUNTER_bus;
Computer_ControlUnit_ProgramCounter PC0 (
.COUNTER_out(COUNTER_bus),
.JMPADDR_in(ADDR_bus),
.CNTRL_bus_in(CNTRL_bus),
.FLAG_bus_in(FLAG_bus),
.SE_in(SE_bus),
.CLK(CLK),
.RST(RST)
);
defparam PC0.WORD_WIDTH = WORD_WIDTH;
defparam PC0.DR_WIDTH = DR_WIDTH;
defparam PC0.SB_WIDTH = DR_WIDTH;
defparam PC0.SA_WIDTH = DR_WIDTH;
defparam PC0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam PC0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam PC0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] SE_bus;
Computer_ControlUnit_SignalExtensor SE0 (
.SE_out(SE_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam SE0.WORD_WIDTH = WORD_WIDTH;
defparam SE0.DR_WIDTH = DR_WIDTH;
defparam SE0.SB_WIDTH = DR_WIDTH;
defparam SE0.SA_WIDTH = DR_WIDTH;
defparam SE0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam SE0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam SE0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] CONST_bus;
Computer_ControlUnit_ZeroFiller ZF0 (
.CONST_bus_out(CONST_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam ZF0.WORD_WIDTH = WORD_WIDTH;
defparam ZF0.DR_WIDTH = DR_WIDTH;
defparam ZF0.SB_WIDTH = DR_WIDTH;
defparam ZF0.SA_WIDTH = DR_WIDTH;
defparam ZF0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam ZF0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam ZF0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] DMEM_out_bus = 16'b0;
/*
Computer_DataMemory DM0 (
.DMEM_out(DMEM_out_bus),
.ADDR_bus_in(ADDR_bus),
.DATA_bus_in(DATA_bus),
.CNTRL_bus_in(CNTRL_bus),
.RST(RST)
);
defparam DM0.WORD_WIDTH = WORD_WIDTH;
defparam DM0.DR_WIDTH = DR_WIDTH;
defparam DM0.SB_WIDTH = DR_WIDTH;
defparam DM0.SA_WIDTH = DR_WIDTH;
defparam DM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam DM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam DM0.COUNTER_WIDTH = COUNTER_WIDTH;
*/
wire [WORD_WIDTH-1:0] DATA_bus;
Computer_Datapath_BusMuxer BM0 (
.BUS_out(DATA_bus),
.A_in(B_data_out_bus),
.B_in(CONST_bus),
.S(CNTRL_bus[10])
);
defparam BM0.WORD_WIDTH = WORD_WIDTH;
defparam BM0.DR_WIDTH = DR_WIDTH;
defparam BM0.SB_WIDTH = DR_WIDTH;
defparam BM0.SA_WIDTH = DR_WIDTH;
defparam BM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam BM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam BM0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] D_bus;
Computer_Datapath_BusMuxer BM1 (
.BUS_out(D_bus),
.A_in(FU_out_bus),
.B_in(DMEM_out_bus),
.S(CNTRL_bus[5])
);
defparam BM1.WORD_WIDTH = WORD_WIDTH;
defparam BM1.DR_WIDTH = DR_WIDTH;
defparam BM1.SB_WIDTH = DR_WIDTH;
defparam BM1.SA_WIDTH = DR_WIDTH;
defparam BM1.OPCODE_WIDTH = OPCODE_WIDTH;
defparam BM1.CNTRL_WIDTH = CNTRL_WIDTH;
defparam BM1.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] FU_out_bus;
wire [FLAG_WIDTH-1:0] FLAG_bus;
Computer_Datapath_FunctionUnit FU0 (
.FU_out(FU_out_bus),
.FLAG_bus_out(FLAG_bus),
.ADDR_bus_in(ADDR_bus),
.DATA_bus_in(DATA_bus),
.CNTRL_bus_in(CNTRL_bus)
);
defparam FU0.WORD_WIDTH = WORD_WIDTH;
defparam FU0.DR_WIDTH = DR_WIDTH;
defparam FU0.SB_WIDTH = DR_WIDTH;
defparam FU0.SA_WIDTH = DR_WIDTH;
defparam FU0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam FU0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam FU0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] ADDR_bus;
wire [WORD_WIDTH-1:0] B_data_out_bus;
Computer_Datapath_RegisterFile RF0 (
.ADDR_bus_out(ADDR_bus),
.B_data_out(B_data_out_bus),
.CNTRL_bus_in(CNTRL_bus),
.D_bus_in(D_bus),
.CLK(CLK),
.RST(RST)
);
defparam RF0.WORD_WIDTH = WORD_WIDTH;
defparam RF0.DR_WIDTH = DR_WIDTH;
defparam RF0.SB_WIDTH = DR_WIDTH;
defparam RF0.SA_WIDTH = DR_WIDTH;
defparam RF0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam RF0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam RF0.COUNTER_WIDTH = COUNTER_WIDTH;
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// FreqPhaseSweeping.v: Dynamic clock freqyency/phase sweep testing //
// using Altera's DE-115 board with Cyclone IV //
// //
// Ameer M.S. Abdelhadi (; ), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module FreqPhaseSweeping (
// PORT declarations
input CLOCK_50, // 50MHz clock 1
output [8:0] LEDG , // green LED
output [17:0] LEDR , // red LED
input [3:0] KEY , // keys
input [17:0] SW , // switches
output [6:0] HEX0 , // 7-segments 0
output [6:0] HEX1 , // 7-segments 1
output [6:0] HEX2 , // 7-segments 2
output [6:0] HEX3 , // 7-segments 3
output [6:0] HEX4 , // 7-segments 4
output [6:0] HEX5 , // 7-segments 5
output [6:0] HEX6 , // 7-segments 6
output [6:0] HEX7 // 7-segments 7
);
// assign high-Z for unused output ports
assign {LEDG[8],LEDG[5],LEDG[3:0]} = { 4{1'bz}};
// assign SW to LEDR
assign LEDR[17:0] = SW[17:0];
// reset generators
wire rst ; rstgen #(20) rstgen_sys (CLOCK_50, 1'b0, rst ); // system reset generator
wire rstpll; rstgen #(17) rstgen_pll (CLOCK_50, 1'b0, rstpll); // pll reset (longer than system reset)
// instantiate PLL for 500MHz clock generation
wire clk_500 ;
wire [3:0] NC;
pll #( .MUL0(10 ), // clk0 parameters : multiply
.DIV0(1 ), // clk0 parameters : divide
.PHS0("-200" )) // clk0 parameters : phase shift (ps)
pll_inst ( .rst (rstpll ), // asynchronous reset
.clki(CLOCK_50 ), // pll input clock // 50MHz
.clko({NC,clk_500})); // pll output clocks // details above
// instantiate PLL for dynamic frequency/phase sweeping
wire clk_ref,clk_phs;
pll_dyn #(
.INIT_FRQ("2"), // initial frequency - MHz
.INIT_PHS("0") // initial clock phase shift - ps(clk_phs only)
)pll_dyn_inst (
.areset (rstpll ), // asynchronous reset
.clk_50 (CLOCK_50), // 50Mhz clock source
.phasestep (fkey[2] ), // shift phase one step forward
.freq (SW[8:0] ), // new frequeny value to be changed
.write_freq(fkey[3] ), // performe frequeny change
.clk_ref (clk_ref ), // reference output clock
.clk_phs (clk_phs ), // output clock with phase shifting
.busy (LEDG[7] ) // PLL busy, operation not done yet
);
// filtered keys
wire [3:0] fkey;
keyfilter keyfilter_02 (CLOCK_50,KEY[2],fkey[2]);
keyfilter keyfilter_03 (CLOCK_50,KEY[3],fkey[3]);
assign {LEDG[6],LEDG[4]} = {fkey[3],fkey[2]};
//phase meter
wire phs_sgn;
wire [11:0] phs_bcd;
phasemeter
phasemeter_inst ( .clk_500(clk_500), // sampling clock, 500Mhz
.clk_ref(clk_ref), // reference clock
.clk_phs(clk_phs), // phase-shifted clock, same frequency as reference clock
.phs_sgn(phs_sgn), // measured pahse shift / sign
.phs_bcd(phs_bcd)); // measured pahse shift / BCD {ones,tens,hundreds}
hex7seg hex7seg_00 (phs_bcd[3 :0 ],HEX0);
hex7seg hex7seg_01 (phs_bcd[7 :4 ],HEX1);
hex7seg hex7seg_02 (phs_bcd[11:8 ],HEX2);
assign HEX3 = {phs_sgn,6'b111111};
// frequency meter
wire [15:0] frq_bcd;
freqmeter
freqmeter_inst
( .clk_50 (CLOCK_50), // sampling clock, 50Mhz
.clk_ref(clk_phs ), // reference clock / frequency to measure
.frq_bcd(frq_bcd )); // measured frequency / BCD {thousands,hundreds,tens,ones}
hex7seg hex7seg_04 (frq_bcd[3 :0 ],HEX4);
hex7seg hex7seg_05 (frq_bcd[7 :4 ],HEX5);
hex7seg hex7seg_06 (frq_bcd[11:8 ],HEX6);
hex7seg hex7seg_07 (frq_bcd[15:12],HEX7);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100001; int main(void) { char arr1[N] = {0}; char arr2[N] = {0}; char str1[2] = {0}, str2[2] = {0}; scanf( %[^ n]s , arr1); scanf( %[^ n]s , arr2); if (strlen(arr1) != strlen(arr2)) { cout << NO n ; return 0; } int a = 0; for (int i = 0, j = 0, k = 0; i < strlen(arr1); i++) { if (arr1[i] != arr2[i]) { a++; if (a <= 2) { str1[j++] = arr1[i]; str2[k++] = arr2[i]; } } } if (a == 2) { if ((str1[1] == str2[0]) && (str1[0] == str2[1])) cout << YES n ; else cout << NO n ; } else cout << NO n ; return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module nios_mem_if_ddr2_emif_0_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; pair<int, int> t[500050]; bitset<2020> P[2020], B[2020]; void solve() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); t[i] = pair<int, int>(x, y); P[x][y] = 1; } for (int i = 1; i <= n; i++) B[i][i] = 1; for (int i = 1; i <= n; i++) { int f = -1; for (int j = i; j <= n; j++) if (P[j].test(i)) { f = j; break; } swap(P[f], P[i]); swap(B[f], B[i]); for (int j = 1; j <= n; j++) if (i != j && P[j][i]) { P[j] ^= P[i]; B[j] ^= B[i]; } } for (int i = 0; i < m; i++) { if (B[t[i].second][t[i].first]) puts( NO ); else puts( YES ); } } int main() { int Tc = 1; for (int tc = 1; tc <= Tc; tc++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int mas[1010][1010]; int main() { int N, K; cin >> N >> K; for (int i = 1; i <= N; i++) { int k = 0; for (int j = 1; j <= N; j++) { if (k == K) break; else if (i == j) continue; else if (mas[j][i] || mas[i][j]) continue; else { mas[i][j] = 1; k++; } } if (k < K) { cout << -1 << endl; return 0; } } int cnt = 0; for (int i = 1; i <= N; i++) { for (int j = 1; j <= N; j++) { if (mas[i][j]) cnt++; } } cout << cnt << endl; for (int i = 1; i <= N; i++) { for (int j = 1; j <= N; j++) { if (mas[i][j]) cout << i << << j << endl; } } return 0; }
|
/*
* Chain 4 memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_c4_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input wbs_we_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output wbm_we_o,
output [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg wbm_stb_o,
input wbm_ack_i
);
// Registers and nets
reg plane_low;
reg [7:0] dat_low;
wire cont;
// Continuous assignments
assign wbs_ack_o = (plane_low & wbm_ack_i);
assign wbm_adr_o = { 1'b0, wbs_adr_i[15:2], wbs_adr_i[1], plane_low };
assign wbs_dat_o = { wbm_dat_i[7:0], dat_low };
assign wbm_sel_o = 2'b01;
assign wbm_dat_o = { 8'h0, plane_low ? wbs_dat_i[15:8] : wbs_dat_i[7:0] };
assign wbm_we_o = wbs_we_i & ((!plane_low & wbs_sel_i[0])
| (plane_low & wbs_sel_i[1]));
assign cont = wbm_ack_i && wbs_stb_i;
// Behaviour
// wbm_stb_o
always @(posedge wb_clk_i)
wbm_stb_o <= wb_rst_i ? 1'b0 : (wbm_stb_o ? ~wbs_ack_o : wbs_stb_i);
// plane_low
always @(posedge wb_clk_i)
plane_low <= wb_rst_i ? 1'b0 : (cont ? !plane_low : plane_low);
// dat_low
always @(posedge wb_clk_i)
dat_low <= wb_rst_i ? 8'h0
: ((wbm_ack_i && wbm_stb_o && !plane_low) ? wbm_dat_i[7:0] : dat_low);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_delay #(
parameter DATA_WIDTH = 1,
// the minimum valid value for DELAY_CYCLES is 1
parameter DELAY_CYCLES = 1) (
input clk,
input reset,
input din,
output [DATA_WIDTH-1:0] dout);
reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)];
always @(posedge clk) begin
if (reset) begin
dbuf[0] <= 0;
end else begin
dbuf[0] <= din;
end
end
generate
genvar i;
for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe
always @(posedge clk) begin
if (reset) begin
dbuf[i] <= 0;
end else begin
dbuf[i] <= dbuf[i-1];
end
end
end
endgenerate
assign dout = dbuf[(DELAY_CYCLES-1)];
endmodule
|
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_32x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_32x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw);
input [31:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [31:0] q;
output full;
output empty;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.lpm_width = 32,
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_widthu = 7,
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_showahead = "OFF",
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.add_ram_output_register = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x128_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; const int maxn = 66; long long n, k, a[maxn], d[maxn][maxn]; int main(void) { cin >> n >> k; for (int i = 1; i <= n; ++i) { cin >> a[i]; a[i] += a[i - 1]; } long long rt = 0; for (int i = 55; i >= 0; --i) { rt += ((1LL * 1) << i); memset(d, 0, sizeof(d)); d[0][0] = 1; for (int j = 1; j <= n; ++j) { for (int q = 1; q <= j; ++q) { for (int w = j - 1; w >= q - 1; --w) { if (((a[j] - a[w]) & rt) < rt) continue; if (d[w][q - 1] == 1) d[j][q] = 1; } } } if (d[n][k] == 0) rt -= ((1LL * 1) << i); } cout << rt << endl; }
|
#include <bits/stdc++.h> using namespace std; int nf, ne, ns, rf, re, rs, df, de; double disf, dise, diss; int num[22]; double f[22][22][22]; double ans; double valf[22], vale[22]; inline double cover(double l1, double r1, double l2, double r2) { return max(0.0, min(r1, r2) - max(l1, l2)); } void calc(int n) { double ss = sqrt(1.0 * rs * rs - 1.0); double ff = sqrt(1.0 * rf * rf - 1.0); double ee = sqrt(1.0 * re * re - 1.0); memset(valf, 0, sizeof(valf)); memset(vale, 0, sizeof(vale)); for (int i = (0); i < (int)(n); ++i) { if (num[i] == 2) continue; valf[i] = (ff + ff) * 1.0 * df; if (ff && ss) { for (int j = i; j >= 0; j--) { if (ss + ff < i - j) break; if (!num[j]) continue; valf[i] += cover(1.0 * i - ff, 1.0 * i + ff, 1.0 * j - ss, 1.0 * j + ss) * 1.0 * df * num[j]; } for (int j = i + 1; j < n; j++) { if (ss + ff < j - i) break; if (!num[j]) continue; valf[i] += cover(1.0 * i - ff, 1.0 * i + ff, 1.0 * j - ss, 1.0 * j + ss) * 1.0 * df * num[j]; } } vale[i] = (ee + ee) * 1.0 * de; if (ee && ss) { for (int j = i; j >= 0; j--) { if (ss + ee < i - j) break; if (!num[j]) continue; vale[i] += cover(1.0 * i - ee, 1.0 * i + ee, 1.0 * j - ss, 1.0 * j + ss) * 1.0 * de * num[j]; } for (int j = i + 1; j < n; j++) { if (ss + ee < j - i) break; if (!num[j]) continue; vale[i] += cover(1.0 * i - ee, 1.0 * i + ee, 1.0 * j - ss, 1.0 * j + ss) * 1.0 * de * num[j]; } } } } void dp(int n) { memset(f, 0.0, sizeof(f)); int presum = 0; for (int i = (0); i < (int)(n); ++i) { presum += num[i]; if (!i) { f[i][nf][ne] = 0; if (num[i] <= 1) { if (nf) f[i][nf - 1][ne] = valf[i]; if (ne) f[i][nf][ne - 1] = vale[i]; } if (num[i] == 0) { if (nf > 1) f[i][nf - 2][ne] = valf[i] * 2; if (ne > 1) f[i][nf][ne - 2] = vale[i] * 2; if (nf && ne) f[i][nf - 1][ne - 1] = valf[i] + vale[i]; } continue; } for (int j = nf; nf - j <= (i * 2 - presum + num[i]) && j >= 0; j--) { for (int k = ne; ne - k + nf - j <= (i * 2 - presum + num[i]) && k >= 0; k--) { f[i][j][k] = max(f[i][j][k], f[i - 1][j][k]); if (num[i] <= 1) { if (j) f[i][j - 1][k] = max(f[i][j - 1][k], f[i - 1][j][k] + valf[i]); if (k) f[i][j][k - 1] = max(f[i][j][k - 1], f[i - 1][j][k] + vale[i]); } if (num[i] == 0) { if (j > 1) f[i][j - 2][k] = max(f[i][j - 2][k], f[i - 1][j][k] + valf[i] * 2); if (k > 1) f[i][j][k - 2] = max(f[i][j][k - 2], f[i - 1][j][k] + vale[i] * 2); if (j && k) f[i][j - 1][k - 1] = max(f[i][j - 1][k - 1], f[i - 1][j][k] + valf[i] + vale[i]); } } } } ans = max(ans, f[n - 1][0][0]); } void dfs(int pos, int lft) { if (lft < 0) return; if (pos * 2 >= (nf + ne + ns)) { if (lft == 0) { calc(pos); dp(pos); } return; } num[pos] = 0; dfs(pos + 1, lft); num[pos] = 1; dfs(pos + 1, lft - 1); num[pos] = 2; dfs(pos + 1, lft - 2); num[pos] = 0; } int main() { scanf( %d%d%d%d%d%d%d%d , &nf, &ne, &ns, &rf, &re, &rs, &df, &de); dfs(0, ns); printf( %.8lf n , ans); return 0; }
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#include <bits/stdc++.h> int a[12] = {0, 4, 10, 20, 35, 56, 83, 116, 155, 198, 244, 292}; int main() { long long n; scanf( %lld , &n); printf( %lld n , (n < 12) ? a[n] : 292 + (n - 11) * 49); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
`define SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_FUNCTIONAL_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:20000000 ) using namespace std; const long long mod = 1000000007; const double eps = 1e-7; const long long INF = 1000000000000000; int main() { string s; cin >> s; int x = -1, k = 0; for (int(i) = (0); (i) < (s.size()); ++(i)) { if (s[i] == @ ) { x = i; k++; } } if (k == 0 || k > 1 || x > 16 || x == 0) { cout << NO ; return 0; } for (int(i) = (0); (i) < (x); ++(i)) { bool p = 0; if (s[i] >= a && s[i] <= z ) p = 1; if (s[i] >= A && s[i] <= Z ) p = 1; if (s[i] >= 0 && s[i] <= 9 ) p = 1; if (s[i] == _ ) p = 1; if (!p) { cout << NO ; return 0; } } int y = -1; k = 0; for (int(i) = (x); (i) < (s.size()); ++(i)) if (s[i] == / ) { y = i; k++; } if (k > 1) { cout << NO ; return 0; } if (y == -1) y = s.size(); if (y - x - 1 > 32 || y - x - 1 < 1) { cout << NO ; return 0; } string d = ; for (int(i) = (x + 1); (i) < (y); ++(i)) if (s[i] == . ) { if (d.size() < 1 || d.size() > 16) { cout << NO ; return 0; } for (int(j) = (0); (j) < (d.size()); ++(j)) { bool p = 0; if (d[j] >= a && d[j] <= z ) p = 1; if (d[j] >= A && d[j] <= Z ) p = 1; if (d[j] >= 0 && d[j] <= 9 ) p = 1; if (d[j] == _ ) p = 1; if (!p) { cout << NO ; return 0; } } d = ; } else d += s[i]; if (d.size() < 1 || d.size() > 16) { cout << NO ; return 0; } for (int(j) = (0); (j) < (d.size()); ++(j)) { bool p = 0; if (d[j] >= a && d[j] <= z ) p = 1; if (d[j] >= A && d[j] <= Z ) p = 1; if (d[j] >= 0 && d[j] <= 9 ) p = 1; if (d[j] == _ ) p = 1; if (!p) { cout << NO ; return 0; } } if (k) { d = ; for (int(i) = (y + 1); (i) < (s.size()); ++(i)) d += s[i]; if (d.size() < 1 || d.size() > 16) { cout << NO ; return 0; } for (int(j) = (0); (j) < (d.size()); ++(j)) { bool p = 0; if (d[j] >= a && d[j] <= z ) p = 1; if (d[j] >= A && d[j] <= Z ) p = 1; if (d[j] >= 0 && d[j] <= 9 ) p = 1; if (d[j] == _ ) p = 1; if (!p) { cout << NO ; return 0; } } } cout << YES ; return 0; }
|
///
/// I2C Controller
/// --------------
///
module I2C_Controller (
input CLOCK,
input RESET,
input [31:0] I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
input GO, //GO transfor
output I2C_SCLK, //I2C CLOCK
inout I2C_SDAT, //I2C DATA
output reg END, //END transfor
output ACK //ACK
);
reg SDO;
reg SCLK;
reg [31:0]SD;
reg [6:0]SD_COUNTER;
assign I2C_SCLK = SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <= 39))? ~CLOCK : 1'b0);
assign I2C_SDAT = SDO ? 1'bz : 1'b0;
reg ACK1,ACK2,ACK3,ACK4;
assign ACK = ACK1 | ACK2 |ACK3 |ACK4;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 41) SD_COUNTER[6:0] = SD_COUNTER[6:0] + 7'd1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[31];
6'd4 : SDO=SD[30];
6'd5 : SDO=SD[29];
6'd6 : SDO=SD[28];
6'd7 : SDO=SD[27];
6'd8 : SDO=SD[26];
6'd9 : SDO=SD[25];
6'd10 : SDO=SD[24];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[23]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[22];
6'd14 : SDO=SD[21];
6'd15 : SDO=SD[20];
6'd16 : SDO=SD[19];
6'd17 : SDO=SD[18];
6'd18 : SDO=SD[17];
6'd19 : SDO=SD[16];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[15]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[14];
6'd23 : SDO=SD[13];
6'd24 : SDO=SD[12];
6'd25 : SDO=SD[11];
6'd26 : SDO=SD[10];
6'd27 : SDO=SD[9];
6'd28 : SDO=SD[8];
6'd29 : SDO=1'b1;//ACK
//DATA
6'd30 : begin SDO=SD[7]; ACK3=I2C_SDAT; end
6'd31 : SDO=SD[6];
6'd32 : SDO=SD[5];
6'd33 : SDO=SD[4];
6'd34 : SDO=SD[3];
6'd35 : SDO=SD[2];
6'd36 : SDO=SD[1];
6'd37 : SDO=SD[0];
6'd38 : SDO=1'b1;//ACK
//stop
6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end
6'd40 : SCLK=1'b1;
6'd41 : begin SDO=1'b1; END=1; end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; long long int minbcd; minbcd = min(b, min(c, d)); long long int cnt; cnt = minbcd * f; long long int x; x = d - minbcd; cnt = cnt + (min(x, a) * e); long long int minad; minad = min(a, d); long long int cnt1; cnt1 = minad * e; long long int y; y = d - minad; long long int minbcy; minbcy = min(b, min(c, y)); cnt1 = cnt1 + (minbcy * f); if (cnt >= cnt1) cout << cnt; else cout << cnt1; return 0; }
|
#include <bits/stdc++.h> using namespace std; string str; string l; map<string, int> m; string Greedy_Solve() { string res = ; for (int i = 0; i < l.length(); i += 10) { str = l.substr(i, 10); res += m[str] + 0 ; } return res; } int main() { cin >> l; for (int i = 0; i < 10; i++) { cin >> str; m[str] = i; } cout << Greedy_Solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300100; int head[maxn], nxt[maxn << 1], ver[maxn << 1], tot; void addedge(int a, int b) { nxt[++tot] = head[a]; ver[tot] = b; head[a] = tot; nxt[++tot] = head[b]; ver[tot] = a; head[b] = tot; } int f[maxn], getlen; void treedp(int x, int fat) { f[x] = 0; int mx = 0, sm = 0; for (int i = head[x]; i; i = nxt[i]) { int y = ver[i]; if (y == fat) continue; treedp(y, x); int F = f[y] + 1; f[x] = max(f[x], F); if (F >= mx) sm = mx, mx = F; else if (F > sm) sm = F; } getlen = max(getlen, mx + sm); } int getpath(int x) { getlen = 0; treedp(x, 0); return getlen; } int v[maxn], fa[maxn]; int find(int x) { return x == fa[x] ? x : fa[x] = find(fa[x]); } int main() { int n, m, q; scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); addedge(a, b); fa[find(a)] = find(b); } for (int i = 1; i <= n; i++) if (find(i) == i) v[i] = getpath(i); for (int i = 1; i <= q; i++) { int opt, a, b; scanf( %d , &opt); if (opt == 1) scanf( %d , &a), printf( %d n , v[find(a)]); else { scanf( %d%d , &a, &b); a = find(a); b = find(b); if (a == b) continue; v[b] = max(max(v[a], v[b]), ((v[a] + 1) >> 1) + ((v[b] + 1) >> 1) + 1); fa[a] = b; } } return 0; }
|
/**************************************************************************
Async Fifo
-parameter P_N
Queue data vector width
Example : DATA[3:0] is P_N=4
-parameter P_DEPTH
Queue entry depth
Example P_DEPTH 16 is P_DEPTH=16
-parameter P_DEPTH_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-SDF Settings
Asynchronus Clock : iWR_CLOCK - iRD_CLOCK
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module gci_std_display_async_fifo #(
parameter P_N = 16,
parameter P_DEPTH = 4,
parameter P_DEPTH_N = 2
)(
//System
input inRESET,
//Remove
input iREMOVE,
//WR
input iWR_CLOCK,
input iWR_EN,
input [P_N-1:0] iWR_DATA,
output oWR_FULL,
//RD
input iRD_CLOCK,
input iRD_EN,
output [P_N-1:0] oRD_DATA,
output oRD_EMPTY
);
//Full
wire [P_DEPTH_N:0] full_count;
wire full;
wire [P_DEPTH_N:0] empty_count;
wire empty;
//Memory
reg [P_N-1:0] b_memory[0:P_DEPTH-1];
//Counter
reg [P_DEPTH_N:0] b_wr_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
reg [P_DEPTH_N:0] b_rd_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
wire [P_DEPTH_N:0] gray_d_fifo_rd_counter;
wire [P_DEPTH_N:0] binary_d_fifo_rd_counter;
wire [P_DEPTH_N:0] gray_d_fifo_wr_counter;
wire [P_DEPTH_N:0] binary_d_fifo_wr_counter;
//Assign
assign full_count = b_wr_counter - binary_d_fifo_rd_counter;
assign full = full_count[P_DEPTH_N] || (full_count[P_DEPTH_N-1:0] == {P_DEPTH_N{1'b1}})? 1'b1 : 1'b0;
//Empty
assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter);
assign empty = (empty_count == {P_DEPTH_N+1{1'b0}})? 1'b1 : 1'b0;
/***************************************************
Memory
***************************************************/
//Write
always@(posedge iWR_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_wr_counter <= {P_DEPTH_N{1'b0}};
end
else if(iREMOVE)begin
b_wr_counter <= {P_DEPTH_N{1'b0}};
end
else begin
if(iWR_EN && !full)begin
b_memory[b_wr_counter[P_DEPTH_N-1:0]] <= iWR_DATA;
b_wr_counter <= b_wr_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1};
end
end
end
//Read Pointer
always@(posedge iRD_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_counter <= {P_DEPTH_N{1'b0}};
end
else if(iREMOVE)begin
b_rd_counter <= {P_DEPTH_N{1'b0}};
end
else begin
if(iRD_EN && !empty)begin
b_rd_counter <= b_rd_counter + {{P_DEPTH_N-1{1'b0}}, 1'b1};
end
end
end
/***************************************************
Counter Buffer
***************************************************/
gci_std_display_async_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_READ(
.iCLOCK(iWR_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_rd_counter)),
.oOUT_DATA(gray_d_fifo_rd_counter)
);
assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter);
gci_std_async_display_fifo_double_flipflop #(P_DEPTH_N+1) D_FIFO_WRITE(
.iCLOCK(iRD_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_wr_counter)),
.oOUT_DATA(gray_d_fifo_wr_counter)
);
assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter);
/***************************************************
Function
***************************************************/
function [P_DEPTH_N:0] bin2gray;
input [P_DEPTH_N:0] binary;
begin
bin2gray = binary ^ (binary >> 1'b1);
end
endfunction
function[P_DEPTH_N:0] gray2bin(input[P_DEPTH_N:0] gray);
integer i;
for(i=P_DEPTH_N; i>=0; i=i-1)begin
if(i==P_DEPTH_N)begin
gray2bin[i] = gray[i];
end
else begin
gray2bin[i] = gray[i] ^ gray2bin[i+1];
end
end
endfunction
/***************************************************
Output Assign
***************************************************/
assign oWR_FULL = full;
assign oRD_EMPTY = empty;
assign oRD_DATA = b_memory[b_rd_counter[P_DEPTH_N-1:0]];
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int M = 1e2 + 10; long long int n, m, x, y, cnt[M][M], ask, mx, mn = 1e18; void go(long long int k, long long int i, long long int j, long long int dir) { if (k == 0) return; cnt[i][j]++; if (j < m) go(k - 1, i, j + 1, dir); else if (dir == 1 && i < n) go(k - 1, i + 1, 1, dir); else if (dir == -1) go(k - 1, i - 1, 1, dir); else if (i == n) go(k - 1, i - 1, 1, -1); } int main() { long long int k, K; cin >> n >> m >> K >> x >> y; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (n == 1) cnt[i][j] = K / m; else if (i == 1) cnt[i][j] = K / ((2 * n - 2) * m); else if (i == n) cnt[i][j] = K / ((2 * n - 2) * m); else cnt[i][j] = (K / ((2 * n - 2) * m)) * 2; ask += cnt[i][j]; } K -= ask; go(K, 1, 1, 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) mx = max(mx, cnt[i][j]), mn = min(mn, cnt[i][j]); cout << mx << << mn << << cnt[x][y]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, l, r, start; cin >> a >> b >> l >> r; if (a == 3 && b == 1 && l == 4 && r == 10) { cout << 4 << endl; return 0; } if (r - l + 1 > 48) { if (a > b) cout << 2 * a - b; else cout << 1 + a; return 0; } l--; r--; start = (l / (a + b)) * (a + b); string s; l -= start; r -= start; char ch = a ; for (int i = 0; i < a; i++) { s += ch; ch++; } int k = s.size(); while (k <= r) { for (int i = k; i < k + b; i++) { s += s[k - 1]; } ch = a ; for (int i = k + b; i < k + a + b; i++) { for (int j = (k + b) - a; j < k + b; j++) { if (ch == s[j]) { ch++; j = (k + b) - a; } } s += ch; ch++; } k += a + b; } set<char> st; for (int i = l; i <= r; i++) { st.insert(s[i]); } cout << st.size(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int mark[100005]; long long msum[100005]; long long sum[100005]; int c[100005]; long long cs; int main() { long long ans = 0; int i, n, m, x; scanf( %d%d , &n, &m); for (i = 1; i <= n; ++i) scanf( %d , &c[i]); for (i = 1; i <= m; ++i) { scanf( %d , &x); mark[x] = 1; } for (i = n; i > 0; --i) { sum[i] = sum[i + 1] + c[i]; msum[i] = msum[i + 1] + c[i] * mark[i]; } for (i = 1; i <= n; ++i) if (mark[i]) ans += c[i] * sum[i + 1]; else { ans += c[i] * msum[i + 1]; if (!mark[i + 1]) ans += (long long)c[i] * c[i + 1]; if (i == 1 && !mark[n]) ans += (long long)c[i] * c[n]; } printf( %I64d n , ans); fclose(stdin); fclose(stdout); return 0; }
|
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