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#include <bits/stdc++.h> const int maxn = 100005; int nbs[maxn], ev[maxn * 2], next[maxn * 2], color[maxn], d[maxn], ans[maxn], size[2], view[maxn], n, m, k; void addedge(int x, int y) { next[++k] = nbs[x]; ev[k] = y; nbs[x] = k; } void init() { scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { int x, y; scanf( %d%d , &x, &y); addedge(x, y); addedge(y, x); ++d[x]; ++d[y]; } } void dfs(int x, int col) { color[x] = col; ++size[col]; for (int i = nbs[x]; i; i = next[i]) { if (color[ev[i]] == -1) dfs(ev[i], col ^ 1); } } void output(int x) { int y = 0; for (int i = 1; i <= n; ++i) { if (!ans[i] && color[i] == 0) { ans[i] = x; ++y; if (y % 3 == 0) ++x; } } for (int i = 1; i <= n; ++i) { if (!ans[i] && color[i] == 1) { ans[i] = x; ++y; if (y % 3 == 0) ++x; } } printf( YES n ); for (int i = 1; i <= n; ++i) printf( %d , ans[i]); printf( n ); } void solve(int x, int y = 1) { memset(view, 0, sizeof(view)); ans[x] = y; for (int i = nbs[x]; i; i = next[i]) view[ev[i]] = 1; int k = 0; for (int i = 1; i <= n && k < 2; ++i) { if (!ans[i] && color[i] != color[x] && !view[i]) { ans[i] = y; ++k; } } } void work() { memset(color, -1, sizeof(color)); for (int i = 1; i <= n; ++i) { if (color[i] == -1) dfs(i, 0); } if (size[0] % 3 == 0) output(1); else { int col = size[0] % 3 - 1, find = 0; for (int i = 1; i <= n && !find; ++i) { if (color[i] == col && d[i] + 2 <= size[col ^ 1]) { solve(i); find = 1; } } if (find) output(find + 1); else { col ^= 1; int t = 0; for (int i = 1; i <= n && find < 2; ++i) { if (color[i] == col && d[i] + 2 <= size[col ^ 1]) { solve(i, find + 1); ++find; } } if (find == 2) output(find + 1); else printf( NO n ); } } } int main() { init(); work(); return 0; }
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#include <bits/stdc++.h> using namespace std; map<string, int> H; string s; int l, rs; void Read_Input() { cin >> s; l = s.length(); rs = 0; int i, j, k; for (i = 0; i < l; i++) for (j = i + 1; j < l; j++) { for (k = 0; j + k < l && s[i + k] == s[j + k]; k++) ; if (rs < k) rs = k; } cout << rs << endl; } int main() { Read_Input(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 4e4 + 1; int n, m, x[N], y[N], freq[N], q[N], vis[N], match[N], T, ans[N]; vector<int> g[N]; bool get(int u) { vis[u] = T; for (auto i : g[u]) { if (match[i] != -1 && vis[match[i]] == T) continue; if (match[i] == -1 || get(match[i])) { match[i] = u; return 1; } } return false; } int main() { scanf( %d%d , &n, &m); if (!m) return puts( 0 ), 0; memset(match, -1, sizeof match); for (int i = 0; i < m; i++) scanf( %d %d , x + i, y + i), x[i], y[i], freq[x[i]]++, freq[y[i]]++; int id = n + 1; for (int i = 0; i < m; i++) { g[x[i]].push_back(id); g[y[i]].push_back(id++); } int can = 0; queue<int> q; for (int i = 1; i <= n; i++) q.push(i); while (q.size()) { int x = q.front(); q.pop(); if (freq[x]) { freq[x]--; T++; if (get(x)) q.push(x), ans[x]++; } } for (int i = 1; i <= n; i++) can = max(can, ans[i]); printf( %d n , can); for (int i = 0; i < m; i++) if (match[i + n + 1] == y[i]) printf( %d %d n , y[i], x[i]); else printf( %d %d n , x[i], y[i]); }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14.10.2017 19:53:13
// Design Name:
// Module Name: control_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_tb();
reg [5:0] instru;
reg clk;
//salidas
wire RegDest;
wire SaltoCond;
wire LeerMem;
wire MemaReg;
wire [1:0] ALUOp;
wire EscrMem;
wire FuenteALU;
wire EscrReg;
control uut(
.instru(instru),
.clk(clk),
.RegDest(RegDest),
.SaltoCond(SaltoCond),
.LeerMem(LeerMem),
.MemaReg(MemaReg),
.ALUOp(ALUOp),
.EscrMem(EscrMem),
.FuenteALU(FuenteALU),
.EscrReg(EscrReg)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
instru=6'b000000;
#100
instru=6'b000000;
#100
instru=6'b100011;
#100
instru=6'b101011;
#100
instru=6'b000100;
#100;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int a, b, l, r; void load() { cin >> a >> b >> l >> r; } string s; bool jel[30]; void konstrukcija() { s = ; for (int i = 0; i < a; i++) { char c = i + a ; s += c; } char c = s[s.size() - 1]; for (int i = 0; i < b; i++) s += c; memset(jel, 0, sizeof(jel)); for (int i = s.size() - a; i < s.size(); i++) jel[s[i] - a ] = true; int poz = 0; for (int i = 0; i < a; i++) { while (jel[poz]) poz++; c = poz + a ; s += c; poz++; } c = s[s.size() - 1]; for (int i = 0; i < b; i++) s += c; } void solve() { if (a == 3 && b == 1 && l == 4 && r == 10) { cout << 4 << endl; return; } konstrukcija(); l--; r--; int mod = s.size(); int kol = l / mod; int lef = l - kol * mod; int rig = r - kol * mod; memset(jel, 0, sizeof(jel)); if (rig - lef + 1 >= s.size()) { for (int i = 0; i < s.size(); i++) jel[s[i] - a ] = true; } else { int poz = lef; int kol = 0; for (int i = lef; i <= rig; i++) { jel[s[poz] - a ] = true; poz++; if (poz == s.size()) { poz = 0; kol++; } if (kol == 2) break; } } int cnt = 0; for (int i = 0; i < 30; i++) if (jel[i]) cnt++; cout << cnt << endl; } int main() { load(); solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; struct edge { int t, nxt; } e[600010]; int n, cnt, be[300010], mn_mx[300010], f, vid[300010], tot; void add(const int& x, const int& y) { e[++cnt].t = y, e[cnt].nxt = be[x], be[x] = cnt; } void dfs(const int& x) { if (!be[x]) return (void)(++tot, vid[x] = 1); if (mn_mx[x]) { vid[x] = 1e9; for (int i = be[x]; i; i = e[i].nxt) dfs(e[i].t), vid[x] = min(vid[x], vid[e[i].t]); } else for (int i = be[x]; i; i = e[i].nxt) dfs(e[i].t), vid[x] += vid[e[i].t]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &mn_mx[i]); for (int i = 2; i <= n; ++i) scanf( %d , &f), add(f, i); dfs(1), printf( %d , tot - vid[1] + 1); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 100; vector<int> ans; set<pair<int, int>> add[MAX], rem[MAX], cur; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; add[x].insert({y, i}); rem[y + 1].insert({y, i}); } for (int i = 1; i < MAX; i++) { for (auto p : rem[i]) { cur.erase(p); } for (auto p : add[i]) { cur.insert(p); } while (cur.size() > k) { set<pair<int, int>>::iterator it; it = prev(cur.end()); ans.push_back((*it).second); cur.erase(it); } } cout << ans.size() << endl; for (int x : ans) { cout << x << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 305; struct sss { int a, b, c; bool operator<(const sss& a) const { return c < a.c; } }; vector<sss> v[MAXN * MAXN]; int cost(int a, int b, int c, int d) { return abs(a - c) + abs(b - d); } int main() { int m, n, i, j, k, p; cin >> m >> n >> p; for (i = 1; i <= m; i++) { for (j = 1; j <= n; j++) { int num; cin >> num; v[num].push_back({i, j, 999999999}); } } i = 1; for (j = 0; j < v[i].size(); j++) { v[i][j].c = cost(v[i][j].a, v[i][j].b, 1, 1); } for (i = 2; i <= p; i++) { sort((v[i - 1]).begin(), (v[i - 1]).end()); for (j = 0; j < v[i].size(); j++) { for (k = 0; k < min((int)v[i - 1].size(), m + n + 2); k++) { v[i][j].c = min(v[i][j].c, v[i - 1][k].c + cost(v[i - 1][k].a, v[i - 1][k].b, v[i][j].a, v[i][j].b)); } } } int ans = 999999999; i = p; for (j = 0; j < v[i].size(); j++) ans = min(ans, v[i][j].c); cout << ans << endl; }
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: Line_Buffer1.v
// Megafunction Name(s):
// altshift_taps
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Line_Buffer1 (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x);
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps0x;
output [11:0] taps1x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [11:0] sub_wire3;
wire [23:12] sub_wire1 = sub_wire0[23:12];
wire [11:0] sub_wire2 = sub_wire0[11:0];
wire [11:0] taps1x = sub_wire1[23:12];
wire [11:0] taps0x = sub_wire2[11:0];
wire [11:0] shiftout = sub_wire3[11:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire3)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 2,
altshift_taps_component.tap_distance = 1280,
altshift_taps_component.width = 12;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: cnet_reprogram.v
// Project: CPCI (PCI Control FPGA)
// Description: Manages the reprogramming of the CNET device.
// Programming is performed using Slave SelectMAP mode
// (refer to Chapter 4 of the Virtex II Pro User's Guide).
//
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module cnet_reprogram(
// Interface within the CPCI
input [`PCI_DATA_WIDTH-1:0] prog_data, // Data being written from the PCI interface
input prog_data_vld, // Data on pci_data is valid
input prog_reset, // Reset the programming process
output cnet_reprog, // Indicates that reprogramming is occuring
output overflow, // Indicates a reprogramming buffer overflow
output reg error, // Indicate an error during programming
output reg empty, // Indicate the Write FIFO is now empty
output reg init, // Indicates that the FPGA is in initializaion
output reg done, // Indicates programming is complete
// Interface to the CNET
output reg rp_prog_b,
input rp_init_b,
output rp_cclk,
output rp_cs_b,
output rp_rdwr_b,
output reg [7:0] rp_data,
input rp_done,
// If we ever do PCI-66:
// input rp_busy,
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Tprogram is defined as the minimum duration for a pulse on prog_b
// and is 300ns.
//
// At 33MHz this translates to approximately 10 clocks
`define PROG_B_CLOCKS 'd10
// prog_b counters - this size would allow up to 32
reg [4:0] prog_b_cnt, prog_b_cnt_nxt;
// Keep track of which byte from the FIFO is currently being programmed
reg [1:0] curr_byte, curr_byte_nxt;
// Count the number of clocks we spend in wait to make sure that the CNET
// is up
reg [2:0] wait_cnt, wait_cnt_nxt;
// Fifo data out
wire [`PCI_DATA_WIDTH - 1:0] fifo_data;
reg rp_prog_b_nxt;
reg fifo_rd_en, fifo_rd_en_nxt;
reg error_nxt;
// Negative edge signals to be made positive edge
reg init_ne, done_ne;
wire fifo_empty;
always @(posedge clk) empty <= fifo_empty;
// ==================================================================
// Instantiate a fifo
// ==================================================================
fifo_8x32 reprog_fifo(
.din (prog_data),
.wr_en (prog_data_vld),
.rd_en (fifo_rd_en),
.dout (fifo_data),
.full (fifo_full),
.empty (fifo_empty),
.reset (reset | overflow | error | prog_reset),
.clk (clk)
);
// ==================================================================
// Main state machine
// ==================================================================
/* The state machine has the following states:
* RP_Idle - Currently not reprogramming the CNET
* RP_Prog_B - Asserting prog_b - must be asserted for at
* least 300ns
* RP_Wait_For_Init - Waiting for the init_b signal to go high to
* indicate that clearing of the FPGA is complete
* RP_Download - Downloading data
* RP_Wait - Waiting for device to come up
*/
reg [2:0] curr_state, curr_state_nxt;
`define RP_Idle 3'h0
`define RP_Prog_B 3'h1
`define RP_Wait_For_Init 3'h2
`define RP_Download 3'h3
`define RP_Wait 3'h4
always @(posedge clk)
begin
curr_state <= curr_state_nxt;
prog_b_cnt <= prog_b_cnt_nxt;
rp_prog_b <= rp_prog_b_nxt;
curr_byte <= curr_byte_nxt;
wait_cnt <= wait_cnt_nxt;
fifo_rd_en <= fifo_rd_en_nxt;
error <= error_nxt;
end
always @*
begin
// Set defaults
curr_state_nxt = curr_state;
prog_b_cnt_nxt = prog_b_cnt;
rp_prog_b_nxt = rp_prog_b;
curr_byte_nxt = curr_byte;
wait_cnt_nxt = wait_cnt;
fifo_rd_en_nxt = 1'b0;
error_nxt = 1'b0;
// Go to the idle state on reset
if (reset) begin
curr_state_nxt = `RP_Idle;
prog_b_cnt_nxt = 'h0;
rp_prog_b_nxt = 1'b1;
curr_byte_nxt = 2'b0;
wait_cnt_nxt = 'h0;
end
else
case (curr_state)
`RP_Idle : begin
// Check if there is data being applied to the prog_data bus
if (prog_reset) begin
curr_state_nxt = `RP_Prog_B;
prog_b_cnt_nxt = 'h0;
rp_prog_b_nxt = 1'b0;
end
end
`RP_Prog_B : begin
// Check if the timer has expired
if (prog_b_cnt == (`PROG_B_CLOCKS - 1)) begin
curr_state_nxt = `RP_Wait_For_Init;
rp_prog_b_nxt = 1'b1;
end
else
// Increment the counter
prog_b_cnt_nxt = prog_b_cnt + 1;
end
`RP_Wait_For_Init : begin
// Wait for init to be de-asserted
if (!init) begin
curr_state_nxt = `RP_Download;
curr_byte_nxt = 2'b0;
end
end
`RP_Download : begin
// Check for reset
if (prog_reset) begin
curr_state_nxt = `RP_Prog_B;
prog_b_cnt_nxt = 'h0;
rp_prog_b_nxt = 1'b0;
end
// Check if download is complete
else if (done) begin
curr_state_nxt = `RP_Wait;
wait_cnt_nxt = 'h0;
end
// Check for download errors
else if (init) begin
// An error occurred. Return to the Prog_B state
curr_state_nxt = `RP_Prog_B;
prog_b_cnt_nxt = 'h0;
rp_prog_b_nxt = 1'b0;
error_nxt = 1'b1;
end
// Check if we have data in the buffer
else if (!fifo_empty) begin
// Assert the read signal 1 byte early
if (curr_byte == 2'h2) begin
fifo_rd_en_nxt = 1'b1;
end
// Move to the next byte
curr_byte_nxt = curr_byte + 'h1;
end
end
`RP_Wait : begin
// Check for reset
if (prog_reset) begin
curr_state_nxt = `RP_Prog_B;
prog_b_cnt_nxt = 'h0;
rp_prog_b_nxt = 1'b0;
end
else if (wait_cnt == 'h7)
curr_state_nxt = `RP_Idle;
wait_cnt_nxt = wait_cnt + 'h1;
end
default : begin
curr_state_nxt = `RP_Idle;
end
endcase
end
// ==================================================================
// Sample signals returning from the CNET
// ==================================================================
always @(negedge clk)
begin
init_ne <= ~rp_init_b;
done_ne <= rp_done;
end
always @(posedge clk)
begin
init <= init_ne;
done <= done_ne;
end
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
// Always in programming mode - don't want to read it back
assign rp_rdwr_b = 0;
// We want cs to be ~fifo_empty, therefore cs_b is ~(~fifo_empty)
assign rp_cs_b = !(!fifo_empty && curr_state == `RP_Download);
// Note that the bit allocations for each byte are reversed as per
// Xilinx App Note 502: http://direct.xilinx.com/bvdocs/appnotes/xapp502.pdf
always @*
begin
case (curr_byte)
2'b00 : rp_data <= {fifo_data[0],
fifo_data[1],
fifo_data[2],
fifo_data[3],
fifo_data[4],
fifo_data[5],
fifo_data[6],
fifo_data[7]};
2'b01 : rp_data <= {fifo_data[8],
fifo_data[9],
fifo_data[10],
fifo_data[11],
fifo_data[12],
fifo_data[13],
fifo_data[14],
fifo_data[15]};
2'b10 : rp_data <= {fifo_data[16],
fifo_data[17],
fifo_data[18],
fifo_data[19],
fifo_data[20],
fifo_data[21],
fifo_data[22],
fifo_data[23]};
2'b11 : rp_data <= {fifo_data[24],
fifo_data[25],
fifo_data[26],
fifo_data[27],
fifo_data[28],
fifo_data[29],
fifo_data[30],
fifo_data[31]};
endcase
end
// The programming clock should be the inverse of the system clock
assign rp_cclk = ~clk;
assign cnet_reprog = curr_state != `RP_Idle;
assign overflow = fifo_full & prog_data_vld & ~fifo_rd_en;
endmodule // cnet_reprogram
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; int main() { long long a = 0, b = 0; bool gr = 0; cout << ? << 0 << << 0 << endl; fflush(stdout); int g; cin >> g; if (g == 1) gr = 1; else gr = 0; for (int i = 29; i >= 0; i--) { cout << ? << (a + (1 << i)) << << b << endl; fflush(stdout); int a1, a2; cin >> a1; cout << ? << a << << (b + (1 << i)) << endl; fflush(stdout); cin >> a2; if (a1 == a2) { if (gr) { a += (1 << i); if (a1 == 1) gr = 1; else gr = 0; } else { b += (1 << i); if (a1 == 1) gr = 1; else gr = 0; } } if (a1 != a2) { if (a1 == -1) { a += (1 << i); b += (1 << i); } } } cout << ! << a << << b << endl; return 0; }
|
`timescale 1ns/1ps
`define period 10
// http://www.nxp.com/documents/data_sheet/PCF8570.pdf
// iverilog -o test i2c_sram_embedded.v sram.v i2c_mock_master.v tb_i2c_sram.v && vvp test
module i2c_sram_embedded (
sda,
scl,
my_addr,
curr_data,
rcvd_device_address,
state,
rcvd_mode
);
inout sda;
input scl;
wire sda_in;
reg sda_is_slave_write;
reg sda_out;
input [6:0] my_addr;
output reg [6:0] rcvd_device_address;
reg [7:0] rcvd_data;
output reg rcvd_mode;
reg [8:0] counter;
output reg [32:0] state;
output reg [7:0] curr_data;
assign sda_in = sda;
assign sda = sda_is_slave_write ? sda_out: 1'bZ;
/* operation:
* at write, curr_data will be replaced by rcvd_data
* at read, curr_data will be replaced by curr_data * curr_data
*/
//parameter `period = 10;
parameter STOP = 1;
parameter START = 2;
parameter GET_DEVICE_ADDRESS = 3;
parameter GET_MODE = 4;
parameter READ_ADDRESS_PUT_ACK = 5;
parameter GET_ACK = 6;
// parameter SRAM_READ_GET_MEMORY_ADDRESS = 7;
// parameter SRAM_READ_GET_MEMORY_ADDRESS_PUT_ACK = 8;
parameter SRAM_READ_RETURN_VALUE_PART1 = 9;
parameter SRAM_READ_RETURN_VALUE_PART1_GET_ACK = 10;
parameter SRAM_READ_RETURN_VALUE_PART2 = 11;
parameter SRAM_READ_RETURN_VALUE_PART2_GET_ACK = 12;
parameter SRAM_READ_CONTINUE = 13;
parameter SRAM_READ_INCREMENT_MEM_ADDRESS = 14;
parameter SRAM_WRITE_GET_MEMORY_ADDRESS = 15;
parameter SRAM_WRITE_GET_MEMORY_ADDRESS_PUT_ACK = 16;
parameter SRAM_WRITE_GET_DATA_PART1 = 17;
parameter SRAM_WRITE_GET_DATA_PART1_PUT_ACK = 18;
parameter SRAM_WRITE_GET_DATA_PART2 = 19;
parameter SRAM_WRITE_GET_DATA_PART2_PUT_ACK = 20;
parameter SRAM_WRITE_CONTINUE = 21;
parameter SRAM_WRITE_INCREMENT_MEM_ADDRESS = 22;
reg clk;
reg [7:0] address;
wire [15:0] data_read;
reg [15:0] data_write;
inout [15:0] data;
reg chip_enable;
reg write_enable;
reg output_enable;
reg reset;
reg [15:0] data_read2;
// cache for received data for writing to sram
reg [7:0] cache_data_write_p1;
reg [7:0] cache_data_write_p2;
wire do_write;
wire do_enable;
wire do_read;
assign do_write = !write_enable;
assign do_enable_chip = !chip_enable;
assign do_read = output_enable;
assign data = (do_write && do_enable_chip && do_read) ? data_write : 'bz;
assign data_read = data;
sram U_SRAM(
.address(address),
.data(data),
.chip_enable(chip_enable),
.write_enable(write_enable),
.output_enable(output_enable),
.reset(reset)
);
initial begin
state = STOP;
sda_is_slave_write = 0;
counter = 0;
curr_data = 0;
end
always @(negedge sda_in) begin
if (scl == 1)
state <= START;
end
always @(posedge sda_in) begin
if (scl == 1)
state <= STOP;
end
always @(posedge scl) begin
case (state)
GET_DEVICE_ADDRESS: rcvd_device_address[counter] <= sda_in;
GET_MODE: rcvd_mode <= sda_in;
// SRAM_READ_GET_MEMORY_ADDRESS: rcvd_data[counter] <= sda_in;
SRAM_WRITE_GET_MEMORY_ADDRESS: rcvd_data[counter] <= sda_in;
SRAM_WRITE_GET_DATA_PART1: rcvd_data[counter] <= sda_in;
SRAM_WRITE_GET_DATA_PART2: rcvd_data[counter] <= sda_in;
endcase
end
always @(negedge scl) begin
case (state)
START: begin
state <= GET_DEVICE_ADDRESS;
counter <= 3'h6;
end
GET_DEVICE_ADDRESS: begin
if (counter == 0) begin
state <= GET_MODE;
end else begin
counter <= counter - 1;
end
end
GET_MODE: begin
//#`period
if (rcvd_device_address == my_addr) begin
sda_is_slave_write <= 1;
sda_out <= 0;
output_enable <= 0; // active low / opposite
chip_enable <= 0; // active low / opposite
write_enable <= 1; // read (active low) / opposite
end else begin
sda_is_slave_write <= 0;
sda_out <= 1;
end
state <= READ_ADDRESS_PUT_ACK;
end
READ_ADDRESS_PUT_ACK: begin
output_enable <= 0; // active low / opposite
chip_enable <= 1; // active low / opposite
write_enable <= 1; // read (active low) / opposite
if (rcvd_mode == 0) begin
sda_is_slave_write <= 1;
sda_out <= 0;
state <= SRAM_WRITE_GET_MEMORY_ADDRESS;
counter <= 7;
end else begin
sda_out <= 0;
curr_data <= rcvd_data;
address <= rcvd_data;
chip_enable <= 0;
assign data_read2 = data;
address <= curr_data;
counter <= 14; // prepare for sending first 8 bits of data
state <= SRAM_READ_RETURN_VALUE_PART1;
address <= curr_data;
sda_is_slave_write <= 1;
sda_out <= data_read[15];
end
end
SRAM_READ_RETURN_VALUE_PART1: begin
$display("%d\tdata_read[%d]=%d\tsda_out=%d\tdata=%b",$time,counter,data_read[counter],sda_out,data_read);
if (counter == 7) begin
state <= SRAM_READ_RETURN_VALUE_PART1_GET_ACK;
sda_is_slave_write <= 0;
counter <= 6;
end else begin
sda_is_slave_write <= 1; // prepare for writing sda, write data
counter <= counter - 1;
sda_out <= data_read[counter];
end
end
SRAM_READ_RETURN_VALUE_PART1_GET_ACK : begin
sda_is_slave_write <= 1; // prepare for getting ack (readonly sda)
sda_out <= data_read[7];
// $display("State=%d", SRAM_READ_RETURN_VALUE_PART1_GET_ACK);
state <= SRAM_READ_RETURN_VALUE_PART2;
end
SRAM_READ_RETURN_VALUE_PART2: begin
sda_is_slave_write <= 1; // prepare for writing sda, write data
sda_out <= data_read[counter];
counter <= counter - 1;
// $display("sram_counter: %d\tsda_out:%b\tdata_read:%b\tdataread[c]:%b", counter, sda_out, data_read, data_read[counter]);
if (counter == 0) begin
state <= SRAM_READ_RETURN_VALUE_PART2_GET_ACK;
sda_is_slave_write <= 0;
end
end
SRAM_READ_RETURN_VALUE_PART2_GET_ACK : begin
//#`period
// prepare for getting ack (readonly sda)
if (sda_out == 0) begin // looop again, increment address and send next first 8 bit of next 16 bits
address <= address + 1;
state <= STOP;
counter <= 15; // prepare for sending first 8 bits of data
end else begin // end comms
state <= STOP; // comm ends if no ack received.
end
end
SRAM_WRITE_GET_MEMORY_ADDRESS: begin
if (counter == 0) begin
sda_out <= 0;
state <= SRAM_WRITE_GET_MEMORY_ADDRESS_PUT_ACK;
curr_data <= rcvd_data;
address <= rcvd_data; // received address goes to memory address param
sda_is_slave_write <= 1;
end else begin
counter <= counter - 1;
sda_is_slave_write <= 0;
end
end
SRAM_WRITE_GET_MEMORY_ADDRESS_PUT_ACK: begin
//#`period
// Prepare reading from SRAM
chip_enable <= 1; // turn off sram
output_enable <= 1; // output is disable
write_enable <= 0;
// send out ack from slave to master
sda_is_slave_write <= 0;
sda_out <= 0;
counter <= 7; // prepare for sending first 8 bits of data
state <= SRAM_WRITE_GET_DATA_PART1;
end
SRAM_WRITE_GET_DATA_PART1: begin
if (counter == 0) begin
state <= SRAM_WRITE_GET_DATA_PART1_PUT_ACK;
cache_data_write_p1 <= rcvd_data;
sda_is_slave_write <= 1;
end else begin
counter <= counter - 1;
sda_is_slave_write <= 0;
end
end
SRAM_WRITE_GET_DATA_PART1_PUT_ACK: begin
//#`period
// send out ack from slave to master
sda_is_slave_write <= 0; //cheat
sda_out <= 0;
counter <= 7; // prepare for sending first 8 bits of data
state <= SRAM_WRITE_GET_DATA_PART2;
end
SRAM_WRITE_GET_DATA_PART2: begin
if (counter == 0) begin
chip_enable <= 0;
state <= SRAM_WRITE_GET_DATA_PART2_PUT_ACK;
cache_data_write_p2 <= rcvd_data;
sda_is_slave_write <= 1;
end else begin
counter <= counter - 1;
sda_is_slave_write <= 0;
end
end
SRAM_WRITE_GET_DATA_PART2_PUT_ACK: begin
data_write <= {cache_data_write_p1, cache_data_write_p2};// do the writing to memory
#`period
// send out ack from slave to master
sda_is_slave_write <= 0; //cheat
sda_out <= 0;
counter <= 7; // prepare for sending first 8 bits of data
state <= STOP;
chip_enable <= 1;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 10000; vector<int> vec(N); int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> vec[i]; } sort(vec.begin(), vec.begin() + n); int sum = 0; for (int i = 0; i < m; i++) { sum += vec[i]; } cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, MOD = 1e9 + 7; const int n_ = 3010; long long gcd(long long a, long long b) { return (a ? gcd(b % a, a) : b); } long long power(long long a, long long n) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; } n >>= 1; a *= a; } return p; } long long power(long long a, long long n, long long mod) { long long p = 1; while (n > 0) { if (n % 2) { p = p * a; p %= mod; } n >>= 1; a *= a; a %= mod; } return p % mod; } int n, dp[n_][3], a[n_][3]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int j = 0; j < 3; j++) { for (int i = 0; i < n; i++) cin >> a[i][j]; } dp[0][1] = -INF; for (int i = 0; i < n; i++) { dp[i + 1][1] = max(dp[i][0] + a[i][0], dp[i][1] + a[i][1]); dp[i + 1][0] = max(dp[i][1] + a[i][2], dp[i][0] + a[i][1]); } cout << dp[n][1] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, d, val, ind = 0, counter = 0, ans = 0; cin >> n >> d; string v; cin >> v; while (ind <= n - 1) { counter++; ans = 0; for (int i = d; i >= 1; i--) { if (v[ind + i] == 1 ) { ind += i; ans = 1; break; } } if (!ans) break; if (ind == n - 1) { ans = 1; break; } } if (ans) cout << counter << endl; else cout << -1 << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: ETAII_N16_Q4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ETAII_N16_Q4(
input [15:0] in1,
input [15:0] in2,
output [16:0] res
);
wire [2:0] temp1;
wire [4:0] temp2,temp3,temp4,temp5,temp6,temp7,temp8;
assign temp1[2:0] = in1[ 1: 0] + in2[ 1: 0];
assign temp2[4:0] = in1[ 3: 0] + in2[ 3: 0];
assign temp3[4:0] = in1[ 5: 2] + in2[ 5: 2];
assign temp4[4:0] = in1[ 7: 4] + in2[ 7: 4];
assign temp5[4:0] = in1[ 9: 6] + in2[ 9: 6];
assign temp6[4:0] = in1[11: 8] + in2[11: 8];
assign temp7[4:0] = in1[13:10] + in2[13:10];
assign temp8[4:0] = in1[15:12] + in2[15:12];
assign res[16:0] = {temp8[4:2],temp7[3:2],temp6[3:2],temp5[3:2],temp4[3:2],temp3[3:2],temp2[3:2],temp1[1:0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_4_V
`define SKY130_FD_SC_LS__A21O_4_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_4 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21o_4 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n, m; cin >> n >> m; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; priority_queue<int> pq; long long int res[n]; pq.push(a[0]); res[0] = 0; long long int cursum = a[0]; long long int curcount = 0; for (long long int i = 1; i < n; i++) { if (cursum + a[i] <= m) { pq.push(a[i]); cursum += a[i]; res[i] = curcount; } else { vector<long long int> temp; while (cursum + a[i] > m) { long long int x = pq.top(); cursum = cursum - x; temp.push_back(x); pq.pop(); curcount++; } res[i] = curcount; temp.push_back(a[i]); sort(temp.begin(), temp.end()); long long int ab = 0; curcount++; while (cursum <= m and ab < temp.size()) { pq.push(temp[ab]); ab++; cursum += temp[ab - 1]; curcount--; } } } for (int i = 0; i < n; i++) cout << res[i] << ; return 0; }
|
module s27 (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, x; cin >> n, x = n; long long cnt = 0, d = n; for (int i = 2; 1LL * i * i <= x; i++) { if (x % i == 0) { cnt++, d = i; while (x % i == 0) x /= i; } if (cnt > 2) break; } if (x > 1) cnt++; if (cnt <= 1) cout << d; else cout << 1; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEIVE",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_1_0 (
Din,
Dout
);
input wire [23 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(24),
.DIN_FROM(22),
.DIN_TO(7)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int i, j, k, m; int a[100010]; long long f[110][100010], n; long long dfs(int n, long long m) { if (!n) return m; if (m < 100010 && f[n][m] >= 0) return f[n][m]; long long A = dfs(n - 1, m) - dfs(n - 1, m / a[n]); if (m < 100010) f[n][m] = A; return A; } int main() { scanf( %I64d%d , &n, &m); for (i = 1; i <= m; i++) scanf( %d , &a[i]); sort(a + 1, a + m + 1); memset(f, 255, sizeof(f)); printf( %I64d n , dfs(m, n)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_TB_V
`define SKY130_FD_SC_LP__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int a[N], b[N], par[N], val[N], sz[N], lst[N]; vector<int> his; pair<int, int> get(int v) { if (par[v] == v) return make_pair(v, val[v]); pair<int, int> g = get(par[v]); g.second ^= val[v]; return g; } bool merge(int u, int v) { pair<int, int> gu = get(u), gv = get(v); u = gu.first; v = gv.first; if (u == v) return false; if (sz[v] < sz[u]) swap(u, v), swap(gu, gv); par[u] = v; val[u] = gu.second ^ gv.second ^ 1; sz[v] += sz[u]; his.push_back(u); return true; } void undo(int cnt) { while (cnt--) { int u = his.back(); his.pop_back(); sz[par[u]] -= sz[u]; par[u] = u; val[u] = 0; } } void solve(int l, int r, int R) { if (r < l) return; int m = (l + r) >> 1, cnt = 0; for (int i = l; i < m; i++) if (merge(a[i], b[i])) cnt++; if (l < r) { bool f = merge(a[m], b[m]); solve(m + 1, r, R); if (f) undo(1); } lst[m] = m; for (int i = R; i >= m; i--) { if (get(a[i]) == get(b[i])) { lst[m] = i; break; } if (merge(a[i], b[i])) cnt++; } undo(cnt); cnt = 0; for (int i = R; i > lst[m]; i--) if (merge(a[i], b[i])) cnt++; solve(l, m - 1, lst[m]); undo(cnt); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, q; cin >> n >> m >> q; for (int i = 1; i <= m; i++) cin >> a[i] >> b[i], lst[i] = m + 1; for (int i = 1; i <= n; i++) par[i] = i, sz[i] = 1; int ptr = 1; while (ptr <= m && get(a[ptr]) != get(b[ptr])) merge(a[ptr], b[ptr]), ptr++; if (m < ptr) { while (q--) cout << NO n ; return 0; } undo(his.size()); solve(1, ptr, m); while (q--) { int l, r; cin >> l >> r; cout << (ptr < l || r < lst[l] ? YES : NO ) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200100; int arr[MAXN], tmp[MAXN]; vector<int> ve[MAXN]; map<pair<int, int>, vector<int> > mapa; int ind[MAXN]; vector<int> out[MAXN]; int sol = 0; vector<int> t1, t2; vector<int> comp; map<int, int> aaa; void tour(int x, int i) { while (ind[x] < ve[x].size()) { int y = ve[x][ind[x]++]; int ind = mapa[{x, y}].back(); mapa[{x, y}].pop_back(); tour(y, ind); } out[sol].push_back(i); return; } int main() { ios_base::sync_with_stdio(false); int n, s; cin >> n >> s; for (int i = (0); i < (n); i++) { cin >> arr[i]; comp.push_back(arr[i]); } sort(comp.begin(), comp.end()); comp.resize(unique(comp.begin(), comp.end()) - comp.begin()); for (int i = (0); i < (comp.size()); i++) { aaa[comp[i]] = i; } for (int i = (0); i < (n); i++) { arr[i] = aaa[arr[i]]; tmp[i] = arr[i]; } sort(tmp, tmp + n); for (int i = (0); i < (n); i++) { if (arr[i] != tmp[i]) { mapa[{tmp[i], arr[i]}].push_back(i); ve[tmp[i]].push_back(arr[i]); } } int uk = 0; for (int i = (0); i < (n); i++) { tour(tmp[i], i); out[sol].pop_back(); if (out[sol].size()) { reverse(out[sol].begin(), out[sol].end()); uk += out[sol].size(); sol++; } } if (uk > s) { cout << -1 n ; return 0; } int m = min(sol, s - uk); for (int i = (0); i < (m); i++) { sol--; for (int x : out[sol]) t1.push_back(x); t2.push_back(out[sol][0]); } if (m == 1) sol++; if (m <= 1) { cout << sol << endl; for (int i = (0); i < (sol); i++) { cout << out[i].size() << n ; for (int x : out[i]) cout << x + 1 << ; cout << n ; } } else { reverse(t2.begin(), t2.end()); cout << sol + 2 << endl; cout << t1.size() << endl; for (int x : t1) cout << x + 1 << ; cout << endl; cout << t2.size() << endl; for (int x : t2) cout << x + 1 << ; cout << endl; for (int i = (0); i < (sol); i++) { cout << out[i].size() << n ; for (int x : out[i]) cout << x + 1 << ; cout << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int u, int v) { return (v != 0) ? gcd(v, u % v) : u; } struct disjoint_sets { int parent[100000 + 10]; int ccOfParent[100000 + 10]; int cc; disjoint_sets(int V) { cc = V; for (int i = 1; i <= V; i++) parent[i] = i, ccOfParent[i] = 1; } int getParent(int a) { if (parent[a] == a) return a; return parent[a] = getParent(parent[a]); } void link(int a, int b) { ccOfParent[getParent(b)] += ccOfParent[getParent(a)]; ccOfParent[getParent(a)] = ccOfParent[getParent(b)]; parent[getParent(a)] = getParent(b); } bool unionSets(int a, int b) { int p1 = getParent(a); int p2 = getParent(b); if (p1 == p2) return 0; link(a, b); cc--; return 1; } }; vector<int> adj[100000 + 10]; int V, E; vector<pair<int, int> > vec; bool vis[100000 + 10] = {0}; double solve() { disjoint_sets s(V); long long total = 0; for (int i = 0; i < V; i++) { int a = vec[i].second; long long cost = vec[i].first; for (int j = 0; j < adj[a].size(); j++) { int b = adj[a][j]; if (!vis[b]) continue; int cc1 = s.ccOfParent[s.getParent(a)]; int cc2 = s.ccOfParent[s.getParent(b)]; if (s.unionSets(a, b)) total += 2 * cost * cc1 * cc2; } vis[a] = 1; } return (total / ((double)V * (V - 1))); } int main() { ios_base::sync_with_stdio(false); cin >> V >> E; vec.resize(V); for (int i = 1; i <= V; i++) cin >> vec[i - 1].first, vec[i - 1].second = i; int a, b; for (int j = 0; j < E; j++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } sort(vec.rbegin(), vec.rend()); double res = solve(); cout << res << endl; }
|
#include <bits/stdc++.h> long long MOD = 1000000007; using namespace std; bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { return (a.second < b.second); } long long POW(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a % MOD; long long temp = POW(a, b / 2); if (b % 2 == 0) return (temp * temp) % MOD; else return (((temp * temp) % MOD) * a) % MOD; } vector<char> capl = { A , B , C , D , E , F , G , H , I , J , K , L , M , N , O , P , Q , R , S , T , U , V , W , X , Y , Z }; vector<char> sml = { a , b , c , d , e , f , g , h , i , j , k , l , m , n , o , p , q , r , s , t , u , v , w , x , y , z }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; map<int, int> m; for (int i = 1; i < 201; i++) { m[i]++; } for (int i = 0; i < n; i++) { cin >> arr[i]; m[arr[i]]--; } int b[2 * n]; for (int i = 0; i < n; i++) { b[2 * i] = arr[i]; for (auto x : m) { if (x.first > arr[i] && x.second != 0) { b[2 * i + 1] = x.first; m[x.first] = 0; break; } } } int c[2 * n], f = 0; copy(b, b + 2 * n, c); sort(c, c + 2 * n); for (int i = 0; i < 2 * n; i++) { if (c[i] != i + 1) { f = 1; break; } } if (f == 1) { cout << -1 n ; } else { for (int i = 0; i < 2 * n; i++) { cout << b[i] << ; } cout << n ; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_2_V
`define SKY130_FD_SC_HDLL__NAND3B_2_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3b_2 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3b_2 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_TB_V
`define SKY130_FD_SC_HVL__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int mas[n]; for (int i = 0; i < n; i++) { cin >> mas[i]; } int d = 0; int t = 0; for (int i = 0; i < n; i++) { if (mas[i] - d == 1) { t++; d = mas[i]; } } if (!d) { cout << 0 ; return 0; } cout << t << endl; d = 0; for (int i = 0; i < n; i++) { if (mas[i] - d == 1) { d = mas[i]; cout << 2000 + i + 1 << ; } } }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1e5 + 10; const long long MAXL = 20; long long n, m; long long v[MAXN], s[MAXN]; long long rmq[MAXL][MAXN]; long long resp[MAXN]; long long best[MAXN]; void buildRMQ() { for (long long k = 0; k < n; k++) rmq[0][k] = s[k]; for (long long i = 1; i < MAXL; i++) for (long long k = 0; k < MAXN; k++) if (k + (1 << i) <= n) rmq[i][k] = max(rmq[i - 1][k], rmq[i - 1][k + (1 << i - 1)]); } long long RMQ(long long a, long long b) { long long size = b - a + 1; long long log = 31 - __builtin_clz(size); return max(rmq[log][a], rmq[log][b - (1 << log) + 1]); } long long bs(long long ini, long long fim, long long pos) { while (ini < fim) { long long mid = (ini + fim + 1) / 2; if (RMQ(mid, pos - 1) >= s[pos]) ini = mid; else fim = mid - 1; } return ini; } int main() { scanf( %lld %lld , &n, &m); for (long long i = 0; i < n; i++) scanf( %lld , &v[i]); s[0] = 0; for (long long i = 1; i < n; i++) s[i] = abs(v[i] - v[i - 1]); buildRMQ(); while (m--) { long long p, q; scanf( %lld %lld , &p, &q); p--; q--; long long ans = 0; stack<pair<long long, long long> > st; for (long long i = p; i <= q; i++) { while (st.size() && st.top().first <= s[i]) st.pop(); if (st.size()) best[i] = st.top().second; else best[i] = 0; st.push(pair<long long, long long>(s[i], i)); } for (long long i = p; i <= q; i++) { resp[i] = 0; long long bt = best[i]; if (s[bt] >= s[i]) { resp[i] = s[i] * (i - bt) + resp[bt]; } else { resp[i] = s[i] * (i - p); } ans += resp[i]; } printf( %lld n , ans); } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pll = pair<ll, ll>; using vll = vector<ll>; using vpll = vector<pll>; struct d_ { template <typename T> d_& operator,(const T& x) { cerr << << x; return *this; } } d_t; int mix[1024]; int main(void) { ios_base::sync_with_stdio(false); ll n; cin >> n; ; fill(begin(mix), end(mix), (int)1e9 + 7); int st = 2; for (ll i(0); i < 10; i++) { for (ll k(0); k < 2; k++) { set<int> vals; for (ll j(0); j < n; j++) { if (j % st < st / 2 and k == 0) { vals.insert(j); } else if (j % st >= st / 2 and k == 1) { vals.insert(j); } } if (vals.empty()) continue; char* sp = ; cout << vals.size() << n ; for (auto e : vals) { cout << sp << e + 1; sp = ; } cout << endl; for (ll j(0); j < n; j++) { ll vl; cin >> vl; ; if (!vals.count(j)) { mix[j] = min(mix[j], (int)vl); } } cout << endl; } st *= 2; } cout << -1 << endl; char* sp = ; for (ll i(0); i < n; i++) { cout << sp << mix[i]; sp = ; } return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_112x256_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_112x256_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [111:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [111:0] q;
output [7:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "112"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "112"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "192"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "112"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 112 0 INPUT NODEFVAL "data[111..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 112 0 OUTPUT NODEFVAL "q[111..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 112 0 data 0 0 112 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 112 0 @q 0 0 112 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_112x256_la_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s = 1, i; cin >> n; int a[n]; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == s) { s++; } } cout << s - 1 << endl; s = 1; for (i = 0; i < n; i++) { if (a[i] == s) { cout << i + 2001 << ; s++; } } }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* 17-bit, 17-cycle unsigned integer divider, non pipelined */
module tmu2_divider17(
input sys_clk,
input sys_rst,
input start,
input [16:0] dividend,
input [16:0] divisor,
output ready,
output [16:0] quotient,
output [16:0] remainder
);
reg [33:0] qr;
assign remainder = qr[33:17];
assign quotient = qr[16:0];
reg [4:0] counter;
assign ready = (counter == 5'd0);
reg [16:0] divisor_r;
wire [17:0] diff = qr[33:16] - {1'b0, divisor_r};
always @(posedge sys_clk) begin
if(sys_rst)
counter = 5'd0;
else begin
if(start) begin
counter = 5'd17;
qr = {17'd0, dividend};
divisor_r = divisor;
end else begin
if(~ready) begin
if(diff[17])
qr = {qr[32:0], 1'b0};
else
qr = {diff[16:0], qr[15:0], 1'b1};
counter = counter - 5'd1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v; int n, m; cin >> n >> m; int maks = 0; for (int i = 0; i < n; i++) v.push_back(i + 1); do { int res = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { int x = 100; for (int k = i; k <= j; k++) x = min(x, v[k]); res += x; } } maks = max(res, maks); } while (next_permutation(v.begin(), v.end())); v.clear(); for (int i = 0; i < n; i++) v.push_back(i + 1); do { int res = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { int x = 100; for (int k = i; k <= j; k++) x = min(x, v[k]); res += x; } } if (res == maks) { m--; if (m > 0) continue; for (int i = 0; i < n; i++) cout << v[i] << ; cout << n ; break; } } while (next_permutation(v.begin(), v.end())); }
|
#include <bits/stdc++.h> using namespace std; int is_prime[5000010 + 10], primes[5000010 + 10], firstp[5000010 + 10], prime_cnt; void get_primes() { memset(is_prime, -1, sizeof(is_prime)); for (int i = 2; i <= 5000010; i++) { if (is_prime[i]) { primes[prime_cnt++] = i; firstp[i] = i; } for (int j = 0; j < prime_cnt && primes[j] * i <= 5000010; j++) { firstp[i * primes[j]] = primes[j]; is_prime[i * primes[j]] = 0; if (i % primes[j] == 0) break; } } } long long bin[5000010], f[5000010], t, l, r; int main() { get_primes(); scanf( %I64d %I64d %I64d , &t, &l, &r); long long ans = 0, pre = 1; for (int i = 2; i < (5000001); i++) f[i] = (f[i / firstp[i]] + (1LL * i * (firstp[i] - 1)) / 2 % 1000000007) % 1000000007; for (int i = l; i < (r + 1); i++) { ans = (ans + pre * f[i] % 1000000007) % 1000000007; pre = pre * t % 1000000007; } printf( %I64d n , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BLACKBOX_V
|
#include <iostream> #include <cstdio> #include <cstring> using namespace std; char s[5010]; int n; bool ok(int x,int y,int fx,int fy){ if(x==fx && y==fy)return 0; return 1; } bool check(int fx,int fy){ int x=0,y=0; for(int i=1;i<=n;i++){ if(s[i]== D ){ if(ok(x,y-1,fx,fy))y--; } if(s[i]== U ){ if(ok(x,y+1,fx,fy))y++; } if(s[i]== L ){ if(ok(x-1,y,fx,fy))x--; } if(s[i]== R ){ if(ok(x+1,y,fx,fy))x++; } } if(x==0 && y==0)return 1; else return 0; } void work(){ int x=0,y=0; for(int i=1;i<=n;i++){ if(s[i]== D ){ if(check(x,y-1)){ printf( %d %d n ,x,y-1); return; } else y--; } else if(s[i]== U ){ if(check(x,y+1)){ printf( %d %d n ,x,y+1); return; } else y++; } else if(s[i]== L ){ if(check(x-1,y)){ printf( %d %d n ,x-1,y); return; } else x--; } else if(s[i]== R ){ if(check(x+1,y)){ printf( %d %d n ,x+1,y); return; } else x++; } } puts( 0 0 ); return; } int main(){ int T; scanf( %d ,&T); while(T--){ scanf( %s ,s+1); n=strlen(s+1); if(check(5001,5001)){ printf( 5001 5001 n ); continue; } work(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_4_V
`define SKY130_FD_SC_HS__SDLCLKP_4_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_4 (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_4 (
GCLK,
GATE,
CLK ,
SCE
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_4_V
|
#include <bits/stdc++.h> using namespace std; string A[18][18], s; int n, m, U[101], us, J[3][3]; bool B[1001]; int r1, c1, r2, c2, size; int tonum(char ch) { if (ch == C ) return 1; if (ch == D ) return 2; if (ch == H ) return 3; if (ch == S ) return 4; if (ch == T ) return 8; if (ch == J ) return 9; if (ch == Q ) return 10; if (ch == K ) return 11; if (ch == A ) return 12; return (int)ch - 50; } inline bool inside(int a, int b, int c) { if (b > c) swap(b, c); return (b <= a && a <= c); } inline bool ff(int r, int c) { bool B[13]; for (int i = 0; i <= 12; i++) B[i] = false; for (int i = r; i <= r + 2; i++) for (int j = c; j <= c + 2; j++) { if (B[tonum(A[i][j][0])]) return false; B[tonum(A[i][j][0])] = true; } return true; } inline bool check() { for (int i = 1; i <= size; i++) for (int j = i + 1; j <= size; j++) { r1 = (i % m) ? i / m + 1 : i / m; c1 = (i % m) ? (i % m) : m; r2 = (j % m) ? j / m + 1 : j / m; c2 = (j % m) ? (j % m) : m; if (!(inside(r2, r1, r1 + 2) && inside(c2, c1, c1 + 2)) && !(inside(r2, r1, r1 + 2) && inside(c2 + 2, c1, c1 + 2)) && inside(r1 + 2, 1, n) && inside(r2 + 2, 1, n) && inside(c1 + 2, 1, m) && inside(c2 + 2, 1, m)) { if (ff(r1, c1) && ff(r2, c2)) return true; } } return false; } char torank(int k) { int r = (k % 4) ? k / 4 + 1 : k / 4; if (r <= 8) return (char)(r + 49); if (r == 9) return T ; if (r == 10) return J ; if (r == 11) return Q ; if (r == 12) return K ; if (r == 13) return A ; } char tosuit(int k) { int r = k % 4; if (r == 0) return S ; if (r == 1) return C ; if (r == 2) return D ; if (r == 3) return H ; } inline bool replacee(int j, int k) { if (J[j][1] == 0) return false; A[J[j][1]][J[j][2]][0] = torank(k); A[J[j][1]][J[j][2]][1] = tosuit(k); return true; } string print(int k) { char A[3]; A[0] = torank(k); A[1] = tosuit(k); A[2] = 0 ; string str(A); return str; } void printt() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cout << A[i][j][0] << A[i][j][1] << ; cout << endl; } cout << endl; } int main() { bool rep1, rep2; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> s; A[i][j].assign(s); if (s[0] == J ) { if (s[1] == 1 ) { J[1][1] = i; J[1][2] = j; } else if (s[1] == 2 ) { J[2][1] = i; J[2][2] = j; } } B[tonum(s[0]) * 4 + tonum(s[1])] = true; } size = n * m; for (int i = 1; i <= 52; i++) if (!B[i]) U[us++] = i; for (int i = 0; i < us; i++) for (int j = 0; j < us; j++) if (i != j) { rep1 = replacee(1, U[i]); rep2 = replacee(2, U[j]); if (check()) { cout << Solution exists. << endl; if (!rep1 && !rep2) cout << There are no jokers. << endl; else if (rep1 && rep2) cout << Replace J1 with << print(U[i]) << and J2 with << print(U[j]) << . << endl; else if (rep1) cout << Replace J1 with << print(U[i]) << . << endl; else if (rep2) cout << Replace J2 with << print(U[j]) << . << endl; cout << Put the first square to ( << r1 << , << c1 << ). << endl; cout << Put the second square to ( << r2 << , << c2 << ). << endl; return 0; } } cout << No solution. << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[3], ans; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3); ans = (a[1] - a[0]) + (a[2] - a[1]); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int ss, x, y, flag = 0, kk, flag2 = 1; scanf( %d%d%d , &ss, &x, &y); if (x == 1 || x == ss) flag++; if (y == 1 || y == ss) flag++; if (x >= ss / 2 && x <= ss / 2 + 1 && y >= ss / 2 && y <= ss / 2 + 1) flag2 = 0; if (flag == 0) kk = 9; if (flag == 1) kk = 6; if (flag == 2) kk = 4; printf( %s n , (ss * ss >= kk * 2 && flag2) ? YES : NO ); }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus bridge.
*
*/
module rcn_bridge
(
input rst,
input clk,
input [68:0] main_rcn_in,
output [68:0] main_rcn_out,
input [68:0] sub_rcn_in,
output [68:0] sub_rcn_out
);
parameter ID_MASK = 0;
parameter ID_BASE = 1;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] main_rin;
reg [68:0] main_rout;
reg [68:0] sub_rin;
reg [68:0] sub_rout;
assign main_rcn_out = main_rout;
assign sub_rcn_out = sub_rout;
wire [5:0] my_id_mask = ID_MASK;
wire [5:0] my_id_base = ID_BASE;
wire [23:0] my_addr_mask = ADDR_MASK;
wire [23:0] my_addr_base = ADDR_BASE;
wire main_req = main_rin[68] && main_rin[67];
wire main_rsp = main_rin[68] && !main_rin[67];
wire main_id_match = ((main_rin[65:60] & my_id_mask) == my_id_base);
wire main_addr_match = ((main_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
wire sub_req = sub_rin[68] && sub_rin[67];
wire sub_rsp = sub_rin[68] && !sub_rin[67];
wire sub_id_match = ((sub_rin[65:60] & my_id_mask) == my_id_base);
wire sub_addr_match = ((sub_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
wire main_2_main = (main_req && !main_addr_match) || (main_rsp && !main_id_match);
wire sub_2_sub = (sub_req && sub_addr_match) || (sub_rsp && sub_id_match);
wire no_cross = main_2_main || sub_2_sub;
wire main_2_sub = (main_req && main_addr_match) || (main_rsp && main_id_match);
wire sub_2_main = (sub_req && !sub_addr_match) || (sub_rsp && !sub_id_match);
always @ (posedge clk or posedge rst)
if (rst)
begin
main_rin <= 69'd0;
main_rout <= 69'd0;
sub_rin <= 69'd0;
sub_rout <= 69'd0;
end
else
begin
main_rin <= main_rcn_in;
main_rout <= (sub_2_main && !no_cross) ? sub_rin :
(main_2_sub && !no_cross) ? 69'd0 : main_rin;
sub_rin <= sub_rcn_in;
sub_rout <= (main_2_sub && !no_cross) ? main_rin :
(sub_2_main && !no_cross) ? 69'd0 : sub_rin;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_0_V
`define SKY130_FD_SC_LP__A31OI_0_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_0 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_FUNCTIONAL_PP_V
|
module ADT7310P32S16L (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int res[100010], k = 0; struct edge { int id, v, w, next; } e[100010]; int head[100010], cnt = 0; void adde(int u, int v, int w, int id) { e[cnt].id = id; e[cnt].v = v; e[cnt].w = w; e[cnt].next = head[u]; head[u] = cnt++; } int ind[100010]; queue<int> q; int lev[100010]; int tl; bool check(int lim) { memset(ind, 0, sizeof ind); memset(lev, 0, sizeof lev); tl = 0; while (!q.empty()) q.pop(); for (int i = 0; i < cnt; ++i) if (e[i].w > lim) ++ind[e[i].v]; for (int i = 1; i <= n; ++i) if (ind[i] == 0) q.push(i); while (!q.empty()) { int u = q.front(); q.pop(); lev[u] = tl++; for (int i = head[u], v, w; ~i; i = e[i].next) { v = e[i].v; w = e[i].w; if (w <= lim) continue; --ind[v]; if (ind[v] == 0) { q.push(v); } } } for (int i = 1; i <= n; ++i) if (ind[i]) return false; return true; } int main() { memset(head, -1, sizeof head); scanf( %d%d , &n, &m); int L = 0, R = 0, mid, ans; for (int i = 1, u, v, w; i <= m; ++i) { scanf( %d%d%d , &u, &v, &w); adde(u, v, w, i); R = max(R, w); } ++R; while (L < R) { mid = (L + R) >> 1; if (check(mid)) { ans = R = mid; } else { L = mid + 1; } } check(ans); for (int u = 1; u <= n; ++u) { for (int i = head[u], v, w; ~i; i = e[i].next) { v = e[i].v; w = e[i].w; if (w > ans) continue; if (lev[u] > lev[v]) res[++k] = e[i].id; } } printf( %d %d n , ans, k); for (int i = 1; i <= k; ++i) printf( %d%c , res[i], (i == k ? n : )); return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_rdq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Dqta Queue Buffer
// Top level Module: jbi_min_rdq_buf
// Where Instantiated: jbi_min_rdq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_rq_rdq_buf(/*AUTOARG*/
// Outputs
rdq_rdata,
// Inputs
clk, cpu_clk, arst_l, hold, rst_tri_en, rdq_wr_en, rdq_rd_en,
rdq_waddr, rdq_raddr, wdq_rdq_wdata
);
input clk;
input cpu_clk;
input arst_l;
input hold;
input rst_tri_en;
input rdq_wr_en;
input rdq_rd_en;
input [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_waddr;
input [`JBI_RDQ_ADDR_WIDTH-1:0] rdq_raddr;
input [`JBI_RDQ_WIDTH-1:0] wdq_rdq_wdata;
output [`JBI_RDQ_WIDTH-1:0] rdq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_RDQ_WIDTH-1:0] rdq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
///////////////////////////////////////////////////////////////////////
wire [3:0] dangle;
//
// Code start here
//
jbi_1r1w_16x160 u_rdq_buf
(// outputs
.dout ( {dangle[3:0],
rdq_rdata} ),
// read inputs
.rdclk (cpu_clk),
.read_en (rdq_rd_en),
.rd_adr (rdq_raddr),
// write inputs
.wrclk (clk),
.wr_en (rdq_wr_en),
.wr_adr (rdq_waddr),
.din ( {4'b0000,
wdq_rdq_wdata} ),
// other inputs
.rst_l (arst_l),
.hold (hold),
.testmux_sel (1'b1), // always want data from FF
.rst_tri_en (rst_tri_en)
);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/mem/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_P_SYMBOL_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$P (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_SYMBOL_V
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module MIO_BUS(clk,
rst,
BTN,
SW,
mem_w,
Cpu_data2bus, //data from CPU
addr_bus,
ram_data_out,
led_out,
counter_out,
counter0_out,
counter1_out,
counter2_out,
Cpu_data4bus, //write to CPU
ram_data_in, //from CPU write to Memory
ram_addr, //Memory Address signals
data_ram_we,
GPIOf0000000_we,
GPIOe0000000_we,
counter_we,
Peripheral_in
);
input clk,rst,mem_w;
input counter0_out,counter1_out,counter2_out;
input [3:0]BTN;
input [7:0]SW,led_out;
input [31:0] Cpu_data2bus,ram_data_out,addr_bus,counter_out;
output data_ram_we,GPIOe0000000_we,GPIOf0000000_we,counter_we;
output [31:0]Cpu_data4bus,ram_data_in,Peripheral_in;
output [9:0] ram_addr;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.0/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbp (
RESET_B,
D ,
GATE ,
Q ,
Q_N
);
input RESET_B;
input D ;
input GATE ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_BLACKBOX_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 13: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 10240,
the_altsyncram.numwords_a = 10240,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 14;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// The code as shown makes a really big file name with Verilator.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Todd Strader.
`define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
`define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
`define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie
module t ();
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
logic `LONG_NAME_VAR;
`LONG_NAME_MOD
`LONG_NAME_SUB
();
endmodule
module `LONG_NAME_MOD ();
// Force Verilator to make a new class
logic a1 /* verilator public */;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; int main(void) { ios_base::sync_with_stdio(false); cin.tie(0); cin >> N; int x = 0; int res = 0; if (N == 1) { printf( 1 n ); printf( 1 n ); return 0; } for (int i = 1; i <= N; i++) { x += i; if (x > N) { res = i - 1; break; } } printf( %d n , res); for (int i = 1; i < res; i++) { printf( %d , i); N -= i; } printf( %d n , N); }
|
#include <bits/stdc++.h> using namespace std; struct ii { int a, b; bool operator<(ii o) const { return make_tuple(a, b) < make_tuple(o.a, o.b); } }; struct iii { int a, b, c; bool operator<(iii o) const { return make_tuple(a, b, c) < make_tuple(o.a, o.b, o.c); } }; int TC, N, M, K, Q, x, y, z; int arr[35005], par[35005], now[35005], st[4 * 35005], lz[4 * 35005], dp[55][35005]; void build(int p, int l, int r, int rem) { if (l == r) { st[p] = dp[rem][l]; lz[p] = 0; return; } int m = (l + r) >> 1; build(p << 1, l, m, rem); build(p << 1 | 1, m + 1, r, rem); st[p] = max(st[p << 1], st[p << 1 | 1]); lz[p] = 0; } void update(int p, int l, int r, int b1, int b2, int v) { if (lz[p]) { st[p] += lz[p]; if (l < r) { lz[p << 1] += lz[p]; lz[p << 1 | 1] += lz[p]; } lz[p] = 0; } if (b1 <= l && r <= b2) { st[p] += v; if (l < r) { lz[p << 1] += v; lz[p << 1 | 1] += v; } return; } if (r < b1 || b2 < l) return; int m = (l + r) >> 1; update(p << 1, l, m, b1, b2, v); update(p << 1 | 1, m + 1, r, b1, b2, v); st[p] = max(st[p << 1], st[p << 1 | 1]); } int query(int p, int l, int r, int b1, int b2) { if (lz[p]) { st[p] += lz[p]; if (l < r) { lz[p << 1] += lz[p]; lz[p << 1 | 1] += lz[p]; } lz[p] = 0; } if (b1 <= l && r <= b2) { return st[p]; } if (r < b1 || b2 < l) return 0; int m = (l + r) >> 1; return max(query(p << 1, l, m, b1, b2), query(p << 1 | 1, m + 1, r, b1, b2)); } int main() { scanf( %d%d , &N, &K); for (int i = 0; i <= N; i++) now[i] = N; for (int i = 0; i < N; i++) scanf( %d , &arr[i]); for (int i = N - 1; i >= 0; i--) { par[i] = now[arr[i]]; now[arr[i]] = i; } for (int rem = 1; rem <= K; rem++) { build(1, 0, N, rem - 1); for (int pos = N; pos >= 0; pos--) { if (pos == N) { dp[rem][pos] = 0; } else { update(1, 0, N, pos + 1, par[pos], 1); dp[rem][pos] = query(1, 0, N, pos + 1, N - rem + 1); } } } printf( %d n , dp[K][0]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_TB_V
`define SKY130_FD_SC_MS__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_TB_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocm_mem.v
*
* Date : 2012-11
*
* Description : Mimics OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocm_mem();
`include "processing_system7_bfm_v2_0_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, cost = 0, r, min = 100000000; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = 1; i <= a[n - 1]; i++) { t = i; for (int j = 0; j < n; j++) { if (a[j] - t > 1) { cost = cost + a[j] - (t + 1); } else if (t - a[j] > 1) { cost = cost + t - 1 - a[j]; } } if (cost < min) { min = cost; r = t; } cost = 0; } cout << r << << min; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Octoate, Nilquader
// ACID Reverse engineering by nocash
//
// Create Date : 00:45:53 09/03/2010
// Design Name : amsacid
// Module Name : amsacid
// Project Name :
// Target Devices: Xilinx XC9572
// Tool versions :
// Description : Reverse engineered Amstrad 40908 "ACID" Chip
//
// Revision:
// Revision 0.05
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module amsacid(PinCLK, PinA, PinOE, PinCCLR, PinSIN);
input PinCLK;
input [7:0]PinA;
input PinOE;
input PinCCLR;
output [7:0]PinSIN;
wire PinCLK;
reg [16:0]ShiftReg = 17'h1FFFF;
wire [16:0]CmpVal;
wire [16:0]XorVal;
assign CmpVal = 17'h13596 ^ (PinA[0] ? 17'h0000c : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h000c0 : 0)
^ (PinA[3] ? 17'h00030 : 0)
^ (PinA[4] ? 17'h18000 : 0)
^ (PinA[5] ? 17'h00003 : 0)
^ (PinA[6] ? 17'h00600 : 0)
^ (PinA[7] ? 17'h01800 : 0);
assign XorVal = 17'h0C820 ^ (PinA[0] ? 17'h00004 : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h00080 : 0)
^ (PinA[3] ? 17'h00020 : 0)
^ (PinA[4] ? 17'h08000 : 0)
^ (PinA[5] ? 17'h00000 : 0)
^ (PinA[6] ? 17'h00000 : 0)
^ (PinA[7] ? 17'h00800 : 0);
always@(negedge PinCLK)
begin
if (PinCCLR) // not in reset state
begin
if (!PinOE && ((ShiftReg | 17'h00100) == CmpVal))
begin
ShiftReg <= (ShiftReg ^ XorVal) >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16] ^ XorVal[0]; // hier xorval mit berüchsichtigen
end
else
begin
ShiftReg <= ShiftReg >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16];
end
end
else
begin
ShiftReg <= 17'h1FFFF;
end
end
//assign PinSIN = ShiftReg[7:0] ^ 8'hff;
assign PinSIN = ShiftReg[7:0];
//assign PinSIN[0] = PinCLK;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2bb2o (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using P = pair<ll, ll>; constexpr ll inf = 1000000000; constexpr ll mod = 1000000007; constexpr long double eps = 1e-6; template <typename T1, typename T2> ostream& operator<<(ostream& os, pair<T1, T2> p) { os << to_string(p.first) << << to_string(p.second); return os; } template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (ll i = (0); i < (ll)(v.size()); i++) { if (i) os << ; os << v[i]; } return os; } struct modint { ll n; public: modint(const ll n = 0) : n((n % mod + mod) % mod) {} static modint pow(modint a, int m) { modint r = 1; while (m > 0) { if (m & 1) { r *= a; } a = (a * a); m /= 2; } return r; } modint& operator++() { *this += 1; return *this; } modint& operator--() { *this -= 1; return *this; } modint operator++(int) { modint ret = *this; *this += 1; return ret; } modint operator--(int) { modint ret = *this; *this -= 1; return ret; } modint operator~() const { return (this->pow(n, mod - 2)); } friend bool operator==(const modint& lhs, const modint& rhs) { return lhs.n == rhs.n; } friend bool operator<(const modint& lhs, const modint& rhs) { return lhs.n < rhs.n; } friend bool operator>(const modint& lhs, const modint& rhs) { return lhs.n > rhs.n; } friend modint& operator+=(modint& lhs, const modint& rhs) { lhs.n += rhs.n; if (lhs.n >= mod) lhs.n -= mod; return lhs; } friend modint& operator-=(modint& lhs, const modint& rhs) { lhs.n -= rhs.n; if (lhs.n < 0) lhs.n += mod; return lhs; } friend modint& operator*=(modint& lhs, const modint& rhs) { lhs.n = (lhs.n * rhs.n) % mod; return lhs; } friend modint& operator/=(modint& lhs, const modint& rhs) { lhs.n = (lhs.n * (~rhs).n) % mod; return lhs; } friend modint operator+(const modint& lhs, const modint& rhs) { return modint(lhs.n + rhs.n); } friend modint operator-(const modint& lhs, const modint& rhs) { return modint(lhs.n - rhs.n); } friend modint operator*(const modint& lhs, const modint& rhs) { return modint(lhs.n * rhs.n); } friend modint operator/(const modint& lhs, const modint& rhs) { return modint(lhs.n * (~rhs).n); } }; istream& operator>>(istream& is, modint m) { is >> m.n; return is; } ostream& operator<<(ostream& os, modint m) { os << m.n; return os; } long long extgcd(long long a, long long b, long long& x, long long& y) { long long d = a; if (b != 0) { d = extgcd(b, a % b, y, x); y -= (a / b) * x; } else { x = 1; y = 0; } return d; } long long mod_inverse(long long a, long long m) { long long x, y; if (extgcd(a, m, x, y) == 1) return (m + x % m) % m; else return -1; } vector<long long> fact(1010101 + 1, inf); long long mod_fact(long long n, long long& e) { if (fact[0] == inf) { fact[0] = 1; if (1010101 != 0) fact[1] = 1; for (ll i = 2; i <= 1010101; ++i) { fact[i] = (fact[i - 1] * i) % mod; } } e = 0; if (n == 0) return 1; long long res = mod_fact(n / mod, e); e += n / mod; if ((n / mod) % 2 != 0) return (res * (mod - fact[n % mod])) % mod; return (res * fact[n % mod]) % mod; } long long mod_comb(long long n, long long k) { if (n < 0 || k < 0 || n < k) return 0; long long e1, e2, e3; long long a1 = mod_fact(n, e1), a2 = mod_fact(k, e2), a3 = mod_fact(n - k, e3); if (e1 > e2 + e3) return 0; return (a1 * mod_inverse((a2 * a3) % mod, mod)) % mod; } using mi = modint; mi mod_pow(mi a, ll n) { mi ret = 1; mi tmp = a; while (n > 0) { if (n % 2) ret *= tmp; tmp = tmp * tmp; n /= 2; } return ret; } ll gcd(ll a, ll b) { if (b == 0) return a; return gcd(b, a % b); } struct SuffixArray { vector<int> SA; const string s; SuffixArray(const string& str) : s(str) { SA.resize(s.size()); iota(begin(SA), end(SA), 0); sort(begin(SA), end(SA), [&](int a, int b) { return s[a] == s[b] ? a > b : s[a] < s[b]; }); vector<int> classes(s.size()), c(s.begin(), s.end()), cnt(s.size()); for (int len = 1; len < s.size(); len <<= 1) { for (int i = 0; i < s.size(); i++) { if (i > 0 && c[SA[i - 1]] == c[SA[i]] && SA[i - 1] + len < s.size() && c[SA[i - 1] + len / 2] == c[SA[i] + len / 2]) { classes[SA[i]] = classes[SA[i - 1]]; } else { classes[SA[i]] = i; } } iota(begin(cnt), end(cnt), 0); copy(begin(SA), end(SA), begin(c)); for (int i = 0; i < s.size(); i++) { int s1 = c[i] - len; if (s1 >= 0) SA[cnt[classes[s1]]++] = s1; } classes.swap(c); } } int operator[](int k) const { return SA[k]; } size_t size() const { return s.size(); } bool lt_substr(const string& t, int si = 0, int ti = 0) { int sn = (int)s.size(), tn = (int)t.size(); while (si < sn && ti < tn) { if (s[si] < t[ti]) return true; if (s[si] > t[ti]) return false; ++si, ++ti; } return si >= sn && ti < tn; } int lower_bound(const string& t) { int low = -1, high = (int)SA.size(); while (high - low > 1) { int mid = (low + high) / 2; if (lt_substr(t, SA[mid])) low = mid; else high = mid; } return high; } pair<int, int> lower_upper_bound(string& t) { int idx = lower_bound(t); int low = idx - 1, high = (int)SA.size(); t.back()++; while (high - low > 1) { int mid = (low + high) / 2; if (lt_substr(t, SA[mid])) low = mid; else high = mid; } t.back()--; return {idx, high}; } void output() { for (int i = 0; i < size(); i++) { cout << i << : << s.substr(SA[i]) << endl; } } }; struct LongestCommonPrefixArray { const SuffixArray& SA; vector<int> LCP, rank; LongestCommonPrefixArray(const SuffixArray& SA) : SA(SA), LCP(SA.size()) { rank.resize(SA.size()); for (int i = 0; i < SA.size(); i++) { rank[SA[i]] = i; } for (int i = 0, h = 0; i < SA.size(); i++) { if (rank[i] + 1 < SA.size()) { for (int j = SA[rank[i] + 1]; max(i, j) + h < SA.size() && SA.s[i + h] == SA.s[j + h]; ++h) ; LCP[rank[i] + 1] = h; if (h > 0) --h; } } } int operator[](int k) const { return LCP[k]; } size_t size() const { return LCP.size(); } void output() { for (int i = 0; i < size(); i++) { cout << i << : << LCP[i] << << SA.s.substr(SA[i]) << endl; } } }; int main() { cin.tie(0); ios::sync_with_stdio(false); string x; cin >> x; int n = (int)x.size(); SuffixArray sa(x); LongestCommonPrefixArray lcpa(sa); vector<vector<int>> pd(n, vector<int>(n)); vector<int> rev(n); for (ll i = (0); i < (ll)(n); i++) rev[sa[i]] = i; for (ll i = (0); i < (ll)(n - 1); i++) { int a = sa[i]; int mn = lcpa[i + 1]; for (int j = i + 1; j < n; j++) { mn = min(mn, lcpa[j]); int b = sa[j]; pd[a][b] = pd[b][a] = mn; } } vector<vector<pair<int, int>>> dp( n, vector<pair<int, int>>(n, make_pair(0, inf))); vector<vector<pair<int, int>>> acm( n, vector<pair<int, int>>(n, make_pair(0, inf))); for (ll i = (0); i < (ll)(n); i++) { for (ll j = (0); j < (ll)(n); j++) { if (i + 1 < j + 1) continue; if (x[i - j] == 0 ) continue; if (i + 1 == j + 1) { dp[i][j].first = 1; dp[i][j].second = 1; } else { if (j) { dp[i][j].first = acm[i - j - 1][j - 1].first; dp[i][j].second = acm[i - j - 1][j - 1].second + 1; } if (i - j - 1 - j < 0) continue; if (pd[i - j - 1 - j][i - j] >= j + 1) { dp[i][j].first += dp[i - j - 1][j].first; dp[i][j].first %= mod; dp[i][j].second = min(dp[i][j].second, dp[i - j - 1][j].second + 1); } else if (rev[i - j - 1 - j] < rev[i - j]) { dp[i][j].first += dp[i - j - 1][j].first; dp[i][j].first %= mod; dp[i][j].second = min(dp[i][j].second, dp[i - j - 1][j].second + 1); } } } acm[i][0] = dp[i][0]; for (ll j = (1); j < (ll)(n); j++) { acm[i][j].first = acm[i][j - 1].first + dp[i][j].first; acm[i][j].first %= mod; acm[i][j].second = min(acm[i][j - 1].second, dp[i][j].second); } } mi ans1 = acm[n - 1][n - 1].first; ll ans2 = inf * inf; ll tmp = 0; bool good = false; for (int i = n - 1; i >= 0; i--) { if (x[i] == 1 ) tmp += mod_pow(2, n - 1 - i).n; if (good && n - 1 - i > 8) break; if (n - 1 - i > 8) tmp %= mod; if (acm[n - 1][n - 1 - i].second != inf) { good = true; if (n - 1 - i > 8) { ans2 = tmp + acm[n - 1][n - 1 - i].second; break; } else { ans2 = min(ans2, tmp + acm[n - 1][n - 1 - i].second); } } } ans2 %= mod; cout << ans1 << endl; cout << ans2 << endl; return 0; }
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestinationPrev;
wire [15:0] wSourceData0,wSourceData1,wSourceData0_RAM,wSourceData1_RAM,wResultPrev,wIPInitialValue,wImmediateValue;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0_RAM ),
.oDataOut1( wSourceData1_RAM )
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void _DBG(const char *s, _T x) { cerr << s << = << x << n ; } template <typename _T, typename... args> void _DBG(const char *s, _T x, args... a) { while (*s != , ) cerr << *s++; cerr << = << x << , ; _DBG(s + 1, a...); } vector<int> A; vector<int> modded; int main() { int n; cin >> n; A.resize(n); modded.resize(n); for (int i = 0; i < n; i++) { cin >> A[i]; } int res = 0; for (int i = 0; i < 27; i++) { for (int j = 0; j < n; j++) { modded[j] = A[j] % (1 << (i + 1)); } sort((modded).begin(), (modded).end()); int l, r, cnt = 0; for (int j = 0; j < n; j++) { auto beg = modded.begin() + j + 1; auto end = modded.end(); l = lower_bound(beg, end, (1 << i) - modded[j]) - modded.begin(); r = lower_bound(beg, end, (1 << (i + 1)) - modded[j]) - modded.begin(); cnt += (r - l); l = lower_bound(beg, end, (1 << (i + 1)) + (1 << i) - modded[j]) - modded.begin(); r = upper_bound(beg, end, (1 << (i + 2)) - 2 - modded[j]) - modded.begin(); cnt += (r - l); } if (cnt & 1) { res |= (1 << i); } } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool check(string new_l, string old_l) { int len_1; int col_izm; col_izm = 0; len_1 = new_l.length(); if (len_1 == old_l.length()) { for (int i = 0; i < len_1; i++) { if (new_l[i] == old_l[i]) { col_izm++; } else if (((new_l[i] == 1 ) || (new_l[i] == i ) || (new_l[i] == l ) || (new_l[i] == I ) || (new_l[i] == L )) && ((old_l[i] == 1 ) || (old_l[i] == i ) || (old_l[i] == l ) || (old_l[i] == I ) || (old_l[i] == L ))) { col_izm++; } else if (((new_l[i] == 0 ) || (new_l[i] == o ) || (new_l[i] == O )) && ((old_l[i] == 0 ) || (old_l[i] == o ) || (old_l[i] == O ))) { col_izm++; } else if (((new_l[i] - old_l[i]) == 32) || ((new_l[i] - old_l[i]) == -32)) { col_izm++; } else return true; } if (col_izm == len_1) return false; else return true; } else return true; } int main() { string n_login, login; int col; cin >> n_login; cin >> col; for (int i = 0; i < col; i++) { cin >> login; if (!check(n_login, login)) { cout << No << endl; return 0; } } cout << Yes << endl; return 0; }
|
`timescale 1ns/10ps
module system_acl_iface_pll(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2011
//
// VGA scandoubler
module video_vga_double(
input wire clk,
input wire hsync_start,
input wire scanin_start,
input wire [ 5:0] pix_in,
input wire scanout_start,
output reg [ 5:0] pix_out
);
/*
addressing of non-overlapping pages:
pg0 pg1
0xx 1xx
2xx 3xx
4xx 5xx
*/
reg [9:0] ptr_in; // count up to 720
reg [9:0] ptr_out; //
reg pages; // swapping of pages
reg wr_stb;
wire [ 7:0] data_out;
always @(posedge clk) if( hsync_start )
pages <= ~pages;
// write ptr and strobe
always @(posedge clk)
begin
if( scanin_start )
begin
ptr_in[9:8] <= 2'b00;
ptr_in[5:4] <= 2'b11;
end
else
begin
if( ptr_in[9:8]!=2'b11 ) // 768-720=48
begin
wr_stb <= ~wr_stb;
if( wr_stb )
begin
ptr_in <= ptr_in + 10'd1;
end
end
end
end
// read ptr
always @(posedge clk)
begin
if( scanout_start )
begin
ptr_out[9:8] <= 2'b00;
ptr_out[5:4] <= 2'b11;
end
else
begin
if( ptr_out[9:8]!=2'b11 )
begin
ptr_out <= ptr_out + 10'd1;
end
end
end
//read data
always @(posedge clk)
begin
if( ptr_out[9:8]!=2'b11 )
pix_out <= data_out[5:0];
else
pix_out <= 6'd0;
end
mem1536 line_buf( .clk(clk),
.wraddr({ptr_in[9:8], pages, ptr_in[7:0]}),
.wrdata({2'b00,pix_in}),
.wr_stb(wr_stb),
.rdaddr({ptr_out[9:8], (~pages), ptr_out[7:0]}),
.rddata(data_out)
);
endmodule
// 3x512b memory
module mem1536(
input wire clk,
input wire [10:0] wraddr,
input wire [ 7:0] wrdata,
input wire wr_stb,
input wire [10:0] rdaddr,
output reg [ 7:0] rddata
);
reg [7:0] mem [0:1535];
always @(posedge clk)
begin
if( wr_stb )
begin
mem[wraddr] <= wrdata;
end
rddata <= mem[rdaddr];
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tg_status.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct point { int x, y; point() {} point(int a, int b) { x = a, y = b; } }; template <class T> T sqr(T a) { return a * a; } template <class T> T power(T n, T p) { T res = 1; for (int i = 0; i < p; i++) res *= n; return res; } template <class T> double getdist(T a, T b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } template <class T> T extract(string s, T ret) { stringstream ss(s); ss >> ret; return ret; } template <class T> string tostring(T n) { stringstream ss; ss << n; return ss.str(); } long long mod = 1000000009; long long arr[300010], F[300010]; namespace fibonacci { void gen(int n) { F[1] = F[2] = 1; for (int i = 3; i <= n; i++) F[i] = (F[i - 1] + F[i - 2]) % mod; } long long kth_fibo(long long f1, long long f2, long long k) { if (k == 1) return f1; if (k == 2) return f2; long long ret = (F[k - 1] * f2) % mod; ret += (F[k - 2] * f1) % mod; ret %= mod; return ret; } long long sum(long long f1, long long f2, long long k) { long long ret = (kth_fibo(f1, f2, k + 2) - f2) % mod; ret += mod; return ret % mod; } } // namespace fibonacci struct node { long long f1, f2, sum; node(long long sum = 0, long long f1 = 0, long long f2 = 0) : sum(sum), f1(f1), f2(f2){}; void add(long long _f1, long long _f2, long long k) { f1 += _f1; f2 += _f2; f1 %= mod; f2 %= mod; sum += fibonacci::sum(_f1, _f2, k); sum %= mod; } }; node segtree[300010 * 4]; void build(int l, int r, int cur) { if (l == r) { segtree[cur] = node(arr[l] % mod); return; } int lchild = cur << 1, rchild = lchild | 1, m = (l + r) >> 1; build(l, m, lchild); build(m + 1, r, rchild); segtree[cur].sum = segtree[lchild].sum + segtree[rchild].sum; segtree[cur].sum %= mod; } void push_down(int l, int r, int cur) { if (segtree[cur].f1 == 0 && segtree[cur].f2 == 0) return; if (l == r) return; int lchild = cur << 1, rchild = lchild | 1, m = (l + r) >> 1; long long f1, f2, nf1, nf2; f1 = segtree[cur].f1; f2 = segtree[cur].f2; segtree[lchild].add(f1, f2, m - l + 1); nf1 = fibonacci::kth_fibo(f1, f2, max(1, m - l + 2)); nf2 = fibonacci::kth_fibo(f1, f2, max(2, m - l + 3)); segtree[rchild].add(nf1, nf2, r - m); segtree[cur].sum = segtree[lchild].sum + segtree[rchild].sum; segtree[cur].sum %= mod; segtree[cur].f1 = segtree[cur].f2 = 0; } void update(int L, int R, int l, int r, int cur) { push_down(l, r, cur); if (l > R || r < L) return; if (l >= L && r <= R) { long long f1 = F[l - L + 1]; long long f2 = F[l - L + 2]; segtree[cur].add(f1, f2, r - l + 1); return; } int lchild = cur << 1, rchild = lchild | 1, m = (l + r) >> 1; update(L, R, l, m, lchild); update(L, R, m + 1, r, rchild); segtree[cur].sum = segtree[lchild].sum + segtree[rchild].sum; segtree[cur].sum %= mod; } long long query(int L, int R, int l, int r, int cur) { push_down(l, r, cur); if (l > R || r < L) return 0; if (l >= L && r <= R) return segtree[cur].sum; int lchild = cur << 1, rchild = lchild | 1, m = (l + r) >> 1; return (query(L, R, l, m, lchild) + query(L, R, m + 1, r, rchild)) % mod; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, i, q, l, r; cin >> n >> m; for (i = 1; i <= n; i++) cin >> arr[i]; fibonacci::gen(n); build(1, n, 1); while (m--) { cin >> q >> l >> r; if (q == 1) update(l, r, 1, n, 1); else cout << query(l, r, 1, n, 1) << n ; } return 0; }
|
// testbench for chan_ctrl.v
`timescale 10ns/1ns
`define HALF_CLK (5.0)
class channel_data;
bit [13:0] base;
bit [19:0] size;
bit [19:0] loop; // actually loop-size
bit [ 5:0] add_int;
bit [11:0] add_frac;
bit [19:0] offset_int;
bit [11:0] offset_frac;
bit surround;
bit loopena;
bit [ 5:0] vol_left;
bit [ 5:0] vol_right;
function void init();
base = $random()>>(32-14);
add_int = $random()>>(32-6);
add_frac = $random()>>(32-12);
offset_int = $random()>>(32-20);
offset_frac = $random()>>(32-12);
size = $random()>>(32-10); // TODO: greater sizes
loop = {20{1'b1}};
while(loop>=size)
loop = $random()>>(32-10); // TODO: greater sizes
surround = $random()>>(32-1);
loopena = $random()>>(32-1);
vol_left = $random()>>(32-6);
vol_right = $random()>>(32-6);
endfunction
function void update();
bit cy;
int new_off;
bit [21:0] addr;
{cy,offset_frac} = {1'b0, offset_frac} + {1'b0, add_frac};
new_off = {31'd0, cy} + {26'd0,add_int} + {12'd0,offset_int};
if( new_off >= size )
begin
new_off = new_off - size + loop;
end
offset_int = new_off[19:0];
endfunction
function int get_word(input int wnum);
// return words suitable for channels state
if( wnum==0 )
get_word = {offset_int,offset_frac};
else if( wnum==1 )
get_word = {add_int, add_frac, loopena, surround, vol_left, vol_right};
else if( wnum==2 )
get_word = { (4'd0|$random()), size, base[7:0] };
else if( wnum==3 )
get_word = { (4'd0|$random()), loop-size, 2'b0, base[13:8] };
else
$stop;
endfunction
function bit [21:0] get_addr();
get_addr = base*256 + offset_int;
endfunction
function bit [6:0] get_vol_left();
get_vol_left = {1'b0, vol_left};
endfunction
function bit [6:0] get_vol_right();
if( surround )
get_vol_right = 7'h7F - {1'b0, vol_right};
else
get_vol_right = {1'b0, vol_right};
endfunction
function bit [7:0] get_frac();
get_frac = offset_frac[11:4];
endfunction
endclass
module tb;
reg clk;
reg rst_n;
// sync counter
integer sync_cnt;
bit pre_sync;
// DUT connections
wire [ 6:0] rd_addr;
tri0 [31:0] rd_data;
wire [ 6:0] wr_addr;
wire [31:0] wr_data;
wire wr_stb;
reg sync_stb;
reg [31:0] ch_enas;
wire [ 7:0] out_data;
wire out_stb_addr;
wire out_stb_mix;
// channels memory
reg [31:0] channels_mem [0:127];
// test data
channel_data chans[0:31];
// generation fifos
reg [7:0] mix_fifo[$];
reg [7:0] addr_fifo[$];
// init tb data structures
initial
begin : chans_create
int i;
for(i=0;i<32;i++) chans[i] = new;
mix_fifo.delete();
addr_fifo.delete();
end
// clock and reset gen
initial
begin
rst_n = 1'b0;
clk = 1'b1;
forever #(`HALF_CLK) clk = ~clk;
end
//
initial
begin
#(1);
repeat (3) @(posedge clk);
rst_n <= 1'b1;
end
// sync generator
initial
begin
sync_cnt = 0;
pre_sync = 1'b0;
sync_stb = 1'b0;
end
//
always @(posedge clk)
if( !rst_n )
begin
sync_cnt <= 637;
pre_sync <= 1'b0;
sync_stb <= 1'b0;
end
else
begin
if( sync_cnt<(640-1) )
sync_cnt <= sync_cnt + 1;
else
sync_cnt <= 0;
pre_sync <= !sync_cnt;
sync_stb <= pre_sync;
end
// channels memory emulator
reg [31:0] rd_data_reg;
assign rd_data = rd_data_reg;
//
always @(posedge clk)
rd_data_reg <= channels_mem[rd_addr];
//
always @(posedge clk)
if( wr_stb )
channels_mem[wr_addr] <= wr_data;
// fill queues off the output data
always @(posedge clk)
if( out_stb_mix ) mix_fifo.push_back(out_data);
//
always @(posedge clk)
if( out_stb_addr ) addr_fifo.push_back(out_data);
// channel generator/checker
always @(posedge clk)
if( sync_stb )
begin : chans
int i;
// if there was previous iteration, check it
// init channels for new iteration
for(i=0;i<32;i++)
begin
chans[i].init();
channels_mem[i*4+0] = chans[i].get_word(0);
channels_mem[i*4+1] = chans[i].get_word(1);
channels_mem[i*4+2] = chans[i].get_word(2);
channels_mem[i*4+3] = chans[i].get_word(3);
chans[i].update();
end
end
always @(posedge clk)
ch_enas = 32'hFFFF_FFFF;
// DUT
chan_ctrl chan_ctrl
(
.clk (clk ),
.rst_n(rst_n),
.rd_addr(rd_addr),
.rd_data(rd_data),
.wr_addr(wr_addr),
.wr_data(wr_data),
.wr_stb (wr_stb ),
.sync_stb(sync_stb),
.ch_enas(ch_enas),
.out_data (out_data ),
.out_stb_addr(out_stb_addr),
.out_stb_mix (out_stb_mix )
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : YUV 2 RGB Converter
// File : hbi_yuv2rgb.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// red = y + f(v)
// blue = y + f(u)
// green = y - (f(u) + f(v))
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module hbi_yuv2rgb
(
input hb_clk, // Host clock
input [31:0] hbi_din, // PCI data
input [2:0] mw_dp_mode, // memory window datapath mode (YUV, etc)
input [9:0] lut_v0, // for red
input [9:0] lut_v1, // for green
input [9:0] lut_u0, // for blue
input [9:0] lut_u1, // for green
input ycbcr_sel_n, //1=yuv, 0=ycbcr
input select, // signal from mw control
output reg [31:0] pci_data,
output reg [7:0] lut_u0_index, // index to uLUT
output reg [7:0] lut_v0_index // index to vLUT
);
reg [10:0] green_uv0;
reg [10:0] red0, green0, blue0;
reg [10:0] red1, green1, blue1;
reg [7:0] red0_pix, green0_pix, blue0_pix;
reg [7:0] red1_pix, green1_pix, blue1_pix;
reg [31:0] hbi_del;
reg [2:0] mw_dp_mode_del;
reg select_del;
wire [7:0] y0, y1, y2, y3;
// We are delaying the inputs lut_* by one cycle. Now we must delay all
// associated signals that are needed.
always @(posedge hb_clk) begin
hbi_del <= hbi_din;
mw_dp_mode_del <= mw_dp_mode;
select_del <= select;
end
assign y0[7:0] = hbi_del[15:8];
assign y1[7:0] = hbi_del[31:24];
/*
* Map incoming PCI data to y,u,v (or y,Cb,Cr). Y's are used directly
* below, U,V form indices to look-up tables. Also, mux the yuv_lut_index
* register to the LUTs when in readback mode.
*/
always @* begin
// lut indexes
if (ycbcr_sel_n) begin
//yuv: ~MSB is tricky way of adding 128
lut_u0_index = {~hbi_din[7],hbi_din[6:0]};
lut_v0_index = {~hbi_din[23],hbi_din[22:16]};
end else begin
//ycbcr
lut_u0_index = hbi_din[7:0];
lut_v0_index = hbi_din[23:16];
end // else: !if(y_cbcr_sel_n)
end // always @ (hbi_din or yuv_adr or lut_rdback_en_p or ycbcr_sel_n)
/*
* common term u+v for green calc
*/
always @* begin
green_uv0[10:0] = {lut_u1[9],lut_u1[9:0]} + {lut_v1[9],lut_v1[9:0]};
end
// Create Pixel 0
always @* begin
// convert to rgb and round in one step
red0[10:0] = {y0[7:0],1'b1} + {lut_v0[9],lut_v0[9:0]};
blue0[10:0] = {y0[7:0],1'b1} + {lut_u0[9],lut_u0[9:0]};
green0[10:0] = {y0[7:0],1'b1} - {green_uv0[10],green_uv0[10:1]};
// rgb data is in bits [8:1], fix overflows, underflows
case (red0[10:9])
2'b00: // no overflow/underflow
red0_pix = red0[8:1];
2'b01: // overflow
red0_pix = 8'hff;
2'b10, 2'b11: // underflow
red0_pix = 8'h0;
endcase // case (red0[10:9])
case (green0[10:9])
2'b00: // no overflow/underflow
green0_pix = green0[8:1];
2'b01: // overflow
green0_pix = 8'hff;
2'b10, 2'b11: // underflow
green0_pix = 8'h0;
endcase // case (green0[10:9])
case (blue0[10:9])
2'b00: // no overflow/underflow
blue0_pix = blue0[8:1];
2'b01: // overflow
blue0_pix = 8'hff;
2'b10, 2'b11: // underflow
blue0_pix = 8'h0;
endcase // case (blue0[10:9])
end // always @ (y0, lut_v0, lut_v1, lut_u0, lut_u1)
// Create Pixel 1
always @* begin
// convert to rgb and round in one step
red1[10:0] = {y1[7:0],1'b1} + {lut_v0[9],lut_v0[9:0]};
blue1[10:0] = {y1[7:0],1'b1} + {lut_u0[9],lut_u0[9:0]};
green1[10:0] = {y1[7:0],1'b1} - {green_uv0[10],green_uv0[10:1]};
// rgb data is in bits [8:1], fix overflows, underflows
case (red1[10:9])
2'b00: // no overflow/underflow
red1_pix = red1[8:1];
2'b01: // overflow
red1_pix = 8'hff;
2'b10, 2'b11: // underflow
red1_pix = 8'h0;
endcase // case (red1[10:9])
case (green1[10:9])
2'b00: // no overflow/underflow
green1_pix = green1[8:1];
2'b01: // overflow
green1_pix = 8'hff;
2'b10, 2'b11: // underflow
green1_pix = 8'h0;
endcase // case (green1[10:9])
case (blue1[10:9])
2'b00: // no overflow/underflow
blue1_pix = blue1[8:1];
2'b01: // overflow
blue1_pix = 8'hff;
2'b10, 2'b11: // underflow
blue1_pix = 8'h0;
endcase // case (blue1[10:9])
end // always @ (y1, lut_v0, lut_v1, lut_u0, lut_u1)
// Output data formatter: Put data on the appropriate bits, depending on data
// path mode.
always @* begin
casex ({mw_dp_mode_del, select_del}) // synopsys parallel_case
4'b001x: // YUV_422_16_555
pci_data = {1'b0,red1_pix[7:3],green1_pix[7:3],blue1_pix[7:3],
1'b0,red0_pix[7:3],green0_pix[7:3],blue0_pix[7:3]};
4'b010x: // YUV_422_16_565
pci_data = {red1_pix[7:3],green1_pix[7:2],blue1_pix[7:3],
red0_pix[7:3],green0_pix[7:2],blue0_pix[7:3]};
4'b0110: // YUV_422_32
pci_data = {8'h0, red0_pix, green0_pix, blue0_pix};
4'b0111: // YUV_422_32
pci_data = {8'h0, red1_pix, green1_pix, blue1_pix};
4'b100x: // YUV_444_16_555
pci_data = {2{1'b0,red0_pix[7:3],green0_pix[7:3],blue0_pix[7:3]}};
4'b101x: // YUV_444_16_565
pci_data = {2{red0_pix[7:3],green0_pix[7:2],blue0_pix[7:3]}};
4'b110x: // YUV_444_32
pci_data = {8'h0, red0_pix, green0_pix, blue0_pix};
default: // direct linear
pci_data = hbi_del;
endcase // case (mw_dp_mode)
end // always @ (hbi_din or red0_pix or green0_pix or blue0_pix or red1_pix...
endmodule // HBI_YUV2RGB
|
#include <bits/stdc++.h> using namespace std; long long sqr(long long a) { return a * a; } int main() { ios_base::sync_with_stdio(0); int n, m; cin >> n >> m; vector<long long> sumx(n, 0ll); vector<long long> sumy(m, 0ll); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { long long c; cin >> c; sumx[i] += c; sumy[j] += c; } } vector<long long> ansx(n + 1, 0ll); vector<long long> ansy(m + 1, 0ll); for (int i = 0; i <= n; i++) { for (int j = 0; j < n; j++) { ansx[i] += sumx[j] * sqr((2 * j + 1) - 2 * i); } } for (int i = 0; i <= m; i++) { for (int j = 0; j < m; j++) { ansy[i] += sumy[j] * sqr((2 * j + 1) - 2 * i); } } pair<long long, pair<int, int> > res = make_pair((long long)1e18, make_pair(-1, -1)); for (int i = 0; i <= n; i++) { for (int j = 0; j <= m; j++) { res = min(res, make_pair(ansx[i] + ansy[j], make_pair(i, j))); } } cout << 4 * res.first << endl; cout << res.second.first << << res.second.second << endl; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module hardmodle (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 4}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> s; long long n = s.size(); long long a = 0, b = 0; for (auto f : s) { a += (f == 1 ); b += (f == 0 ); } long long z = n - a - b; if (a < b + z) { cout << 00 << endl; } if (n % 2 == 0 && s[n - 1] != 0 ) { long long a1 = a, b1 = b; if (s[n - 1] == ? ) { a1++; } if (a1 <= n / 2 && b1 <= n / 2) { cout << 01 << endl; } } else if (s[n - 1] != 0 ) { long long a1 = a, b1 = b; if (s[n - 1] == ? ) { a1++; } if (a1 <= n / 2 + 1 && b1 <= n / 2) { cout << 01 << endl; } } if (n % 2 == 0 && s[n - 1] != 1 ) { long long a1 = a, b1 = b; if (s[n - 1] == ? ) { b1++; } if (a1 <= n / 2 && b1 <= n / 2) { cout << 10 << endl; } } else if (s[n - 1] != 1 ) { long long a1 = a, b1 = b; if (s[n - 1] == ? ) { b1++; } if (a1 <= n / 2 + 1 && b1 <= n / 2) { cout << 10 << endl; } } if (a + z > b + 1) { cout << 11 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = sizeof(long long) == sizeof(long long) ? 0x3f3f3f3f3f3f3f3fLL : 0x3f3f3f3f; const long long MOD = (long long)(1e9) + 7; const double PI = acos(-1); const double EPS = 1e-9; using pii = pair<long long, long long>; template <typename T, typename S> istream &operator>>(istream &is, pair<T, S> &p) { is >> p.first >> p.second; return is; } template <typename T, typename S> ostream &operator<<(ostream &os, pair<T, S> &p) { os << p.first << << p.second; return os; } template <typename T> void printvv(const vector<vector<T>> &v) { cerr << endl; for (long long i = (0); i < (v.size()); i++) for (long long j = (0); j < (v[i].size()); j++) { if (typeid(v[i][j]).name() == typeid(INF).name() and v[i][j] == INF) { cerr << INF ; } else cerr << v[i][j]; cerr << (j == v[i].size() - 1 ? n : ); } cerr << endl; } void YES(bool f) { cout << (f ? YES : NO ) << endl; } void Yes(bool f) { cout << (f ? Yes : No ) << endl; } template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return true; } return false; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return true; } return false; } template <long long MOD> struct ModInt { static const long long Mod = MOD; unsigned x; ModInt() : x(0) {} ModInt(signed sig) { long long sigt = sig % MOD; if (sigt < 0) sigt += MOD; x = sigt; } ModInt(signed long long sig) { long long sigt = sig % MOD; if (sigt < 0) sigt += MOD; x = sigt; } long long get() const { return (long long)x; } ModInt &operator+=(ModInt that) { if ((x += that.x) >= MOD) x -= MOD; return *this; } ModInt &operator-=(ModInt that) { if ((x += MOD - that.x) >= MOD) x -= MOD; return *this; } ModInt &operator*=(ModInt that) { x = (unsigned long long)x * that.x % MOD; return *this; } ModInt &operator/=(ModInt that) { return *this *= that.inverse(); } ModInt operator+(ModInt that) const { return ModInt(*this) += that; } ModInt operator-(ModInt that) const { return ModInt(*this) -= that; } ModInt operator*(ModInt that) const { return ModInt(*this) *= that; } ModInt operator/(ModInt that) const { return ModInt(*this) /= that; } ModInt inverse() const { signed a = x, b = MOD, u = 1, v = 0; while (b) { signed t = a / b; a -= t * b; std::swap(a, b); u -= t * v; std::swap(u, v); } if (u < 0) u += MOD; ModInt res; res.x = (unsigned)u; return res; } }; template <long long MOD> ostream &operator<<(ostream &os, const ModInt<MOD> &m) { return os << m.x; } template <long long MOD> istream &operator>>(istream &is, ModInt<MOD> &m) { signed long long s; is >> s; m = ModInt<MOD>(s); return is; }; template <long long MOD> ModInt<MOD> pow(ModInt<MOD> a, unsigned long long k) { ModInt<MOD> r = 1; while (k) { if (k & 1) r *= a; a *= a; k >>= 1; } return r; } using mint = ModInt<1000000007>; vector<mint> fact, factinv; void nCr_compute_factinv(long long N) { N = min(N, mint::Mod - 1); fact.resize(N + 1); factinv.resize(N + 1); fact[0] = 1; for (long long i = (1); i < (N + 1); i++) fact[i] = fact[i - 1] * i; factinv[N] = fact[N].inverse(); for (long long i = N; i >= 1; i--) factinv[i - 1] = factinv[i] * i; } mint nCr(long long n, long long r) { if (n >= mint::Mod) return nCr(n % mint::Mod, r % mint::Mod) * nCr(n / mint::Mod, r / mint::Mod); return r > n ? 0 : fact[n] * factinv[n - r] * factinv[r]; } mint nHr(long long n, long long r) { return r == 0 ? 1 : nCr(n + r - 1, r); } mint f(long long x, long long y) { if (x != y) return mint(y) * pow(mint(x), x - y - 1); else return mint(1); } signed main(signed argc, char *argv[]) { long long N, M; cin >> N >> M; long long a, b; cin >> a >> b; nCr_compute_factinv(N + M + 10); mint ans; for (long long i = (0); i < (N - 1); i++) { if (N - 2 - i >= 0 and i <= M - 1) { ; ; ans += fact[N - 2] / fact[N - 2 - i] * nCr(M - 1, i) * pow(mint(M), N - 1 - i - 1) * f(N, i + 2); ; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1005][1005], i, m, ans, k, l, j, q, x, n, ma, mi; string s; int main() { cin >> n >> k; if (k >= (n + 1) / 2) { cout << -1; return 0; } cout << n * k << endl; for (int i = 1; i <= n; i++) { int w = k; for (int j = 1; j <= n; j++) { if (a[i][j] == 1 || i == j) continue; cout << i << << j << endl; a[i][j] = 1; a[j][i] = 1; w--; if (!w) break; } } }
|
#include <bits/stdc++.h> using namespace std; using LL = long long; const int MAXN = 200010; vector<int> x[MAXN], y[MAXN]; int v[MAXN], out[MAXN], sg[MAXN]; int xr[MAXN]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> v[i]; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; --a; --b; x[a].push_back(b); y[b].push_back(a); ++out[a]; } queue<int> Q; for (int i = 0; i < n; ++i) { if (out[i] == 0) Q.push(i); } int maxsg = 0; while (!Q.empty()) { int a = Q.front(); Q.pop(); for (int b : y[a]) { --out[b]; if (out[b] == 0) { Q.push(b); } } set<int> s; for (int b : x[a]) s.insert(sg[b]); for (int i = 0; i < n; ++i) { if (s.find(i) == s.end()) { sg[a] = i; break; } } maxsg = max(maxsg, sg[a]); } for (int i = 0; i < n; ++i) { xr[sg[i]] ^= v[i]; } bool win = false; for (int i = maxsg; i >= 0; --i) { if (xr[i] != 0) { win = true; int p = -1; for (int j = 0; j < n; ++j) { if (sg[j] != i) continue; if (p == -1) { p = j; continue; } if ((v[j] ^ xr[i]) <= v[j]) p = j; } xr[i] ^= v[p]; v[p] = xr[i]; xr[i] = 0; for (int b : x[p]) { if (xr[sg[b]] != 0) { v[b] ^= xr[sg[b]]; xr[sg[b]] = 0; } } break; } } if (win) { cout << WIN n ; for (int i = 0; i < n; ++i) cout << v[i] << ; cout << n ; } else { cout << LOSE n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, x; cin >> n >> x; int arr[n]; int o, e; o = e = 0; int i = 0; for (int j = 0; j < 10; j++) { } for (int j = 0; j < 10; j++) { } for (int j = 0; j < 10; j++) { } while (i < n) { int x; cin >> x; if (x % 2 == 0) { e++; } else o++; i++; } if (o == 0) cout << No << endl; else { bool pos = false; i = 1; while (i <= o) { if (i > x) break; if ((x - i) <= e) { pos = true; break; } i = i + 2; } if (!pos) cout << No << endl; else cout << Yes << endl; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_hl_isowell_tap with
* size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1_V
|
#include <bits/stdc++.h> long long tt, x, y, z, sum, n, i, j, h, k, t, d, m, l, ll, rr, r, a[1000006], b[1000006], f[1000006]; using namespace std; long long xl(long long i) { long long res = 0; for (j = 1; j <= d; j++) b[j] = a[j]; l = 1; r = i; tt = 1; z = b[1]; x = 1; while (r <= n) { if (b[x] > i) { l += b[x] - b[x] % i - i; r += b[x] - b[x] % i - i; b[x] -= (b[x] - b[x] % i - i); } y = 0; t = (l + r) / 2; while (z < t) tt++, z += a[tt]; while (y < i) { if (b[x] > i - y) { res += (i - y) * abs(f[x] - f[tt]); b[x] -= (i - y); y = i; } else { res += b[x] * abs(f[x] - f[tt]); y += b[x]; x++; } } l += i; r += i; } return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cin >> n; for (i = 1; i <= n; i++) { cin >> j; sum += j; if (j > 0) d++, a[d] = j, f[d] = i; } if (sum == 1) cout << -1; else { n = sum; i = 2; m = 1e18; while (i <= sqrt(sum)) { if (sum % i == 0) m = min(m, xl(i)); while (sum % i == 0) sum /= i; i++; } if (sum > 1) m = min(m, xl(sum)); cout << m; } }
|
#include <bits/stdc++.h> using namespace std; void print(vector<int> s) { for (int i = 0; i < s.size(); i++) cout << s[i] << ; cout << endl; } const int INF = 1e9 + 7; char next(char v) { if (v == R ) return L ; if (v == L ) return R ; if (v == U ) return D ; if (v == D ) return U ; } int now(char v) { if (v == R ) return 1; if (v == L ) return 3; if (v == U ) return 0; if (v == D ) return 2; } int main() { int n; cin >> n; string s; cin >> s; vector<int> dp(n, INF); dp[0] = 1; vector<int> last(4, -1); last[now(s[0])] = 0; for (int i = 1; i < n; i++) { int a = last[now(next(s[i]))]; int b = last[(now(s[i]) + 1) % 4]; int c = last[(now(s[i]) + 3) % 4]; int d = min(b, c); last[now(s[i])] = i; if (a == -1 && d == -1) { dp[i] = 1; continue; } if (a == -1) { dp[i] = min(dp[i], dp[d] + 1); continue; } if (d == -1) { dp[i] = min(dp[i], dp[a] + 1); continue; } dp[i] = min(dp[i], dp[max(a, d)] + 1); } cout << dp[n - 1] << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_4_V
`define SKY130_FD_SC_LP__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtn_4 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; map<int, int> mp; long long ans = 0, mx = 1e6; for (int i = 0; i < n; i++) { int first; scanf( %d , &first); int second = 1; long long yy = 1; for (int j = 2; j * j <= first; j++) if (first % j == 0) { int cnt = 0; while (first % j == 0) cnt++, first /= j; cnt %= k; if (cnt) { for (int t = 0; t < cnt; t++) second *= j; for (int t = cnt; t < k; t++) yy = min(mx, yy * j); } } if (first > 1) { int cnt = 1, j = first; for (int t = 0; t < cnt; t++) second *= j; for (int t = cnt; t < k; t++) yy = min(mx, yy * j); } if (mp.count(yy)) ans += mp[yy]; mp[second]++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[1005]; int w[1005]; int main() { int n, k; cin >> n >> k; if (n - k - 1 < k) return cout << -1, 0; cout << n * k << endl; for (int i = 1; i <= n; i++) { int t = w[i]; for (int j = i + 1; j <= n; j++) { if (w[i] < k) printf( %d %d n , i, j), w[i]++; else if (w[j] < k) printf( %d %d n , j, i), w[j]++; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void Read(int &n) { int sign = 1; n = 0; char c; do { c = getchar(); } while (!isdigit(c) && c != - ); if (c == - ) { c = getchar(); sign = -1; } do { n = n * 10 + c - 48; c = getchar(); } while (isdigit(c)); n *= sign; } void Read(long long &n) { int sign = 1; n = 0; char c; do { c = getchar(); } while (!isdigit(c) && c != - ); if (c == - ) { c = getchar(); sign = -1; } do { n = n * 10ll + c - 48; c = getchar(); } while (isdigit(c)); n *= sign; } void Write(int n) { if (n == 0) { putchar( 0 ); return; } else if (n < 0) putchar( - ), n = -n; char C[30]; int d = 0; while (n) { C[++d] = (n % 10) + 48; n /= 10; } for (int i = d; i >= 1; --i) putchar(C[i]); } void Write(long long n) { if (n == 0) { putchar( 0 ); return; } else if (n < 0) putchar( - ), n = -n; char C[30]; int d = 0; while (n) { C[++d] = (n % 10ll) + 48; n /= 10ll; } for (int i = d; i >= 1; --i) putchar(C[i]); } const int maxn = 1005; char S[maxn]; int P1 = 0, P2 = 0; bool DigitOrDot(char c) { return ( 0 <= c && c <= 9 ) || c == . ; } void Solve(int s, int e) { int val = 0; int pos = -1; for (int i = s; i <= e; ++i) { if (S[i] == . ) { pos = i; continue; } val = val * 10 + (S[i] - 0 ); } if (e - pos == 2) { P1 += val / 100; P2 += val % 100; } else P1 += val; } int main() { scanf( %s , S + 1); int n = strlen(S + 1); for (int i = 1; i <= n; ++i) { int s = i, e, j = i; if (DigitOrDot(S[i])) while (j <= n && DigitOrDot(S[j])) ++j; e = j - 1; if (s <= e) Solve(s, e); i = j; } P1 += P2 / 100; P2 %= 100; string ans = ; if (P2 != 0) for (int i = 1; i <= 2; ++i) ans += char((P2 % 10) + 0 ), P2 /= 10; if (ans != ) ans += . ; int d = 0; if (P1 == 0) ans += 0 ; while (P1) { ans += (char)((P1 % 10) + 0 ); P1 /= 10; d++; if (d == 3) d = 0, ans += . ; } if (ans[ans.size() - 1] == . ) ans.erase(ans.size() - 1); reverse(ans.begin(), ans.end()); cout << ans; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ab.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No user `defines in this module
module ent_ab
//
// Generated Module inst_ab
//
(
port_ab_1, // Use internally test1
port_ab_2, // Use internally test2, no port generated
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
input [6:0] sig_14;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/******************************************************************************
* File Name : ec_alu.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : This file contains the module for ALU of the
* elliptic curve processor for the curve
* y^2 + xy = x^3 + a.x^2 + b
* where a = 1
******************************************************************************/
`timescale 1ns / 1ps
`ifndef __ECALU_V__
`define __ECALU_V__
//`include "ff/multiplier.v"
//`include "ff/sqr.v"
//`include "mux8.v"
//`include "mux4.v"
/*---------------------------------------------------------------------------
* Module Name : ec_alu
* Synopsis : Elliptic Curve ALU
* Finite field elements are instantiated over here
* 1. Multiplier
* 2. Squarers
*--------------------------------------------------------------------------*/
module ec_alu(cw, a0, a1, a2, a3, c0, c1);
input wire [232:0] a0, a1, a2, a3; /* the inputs to the alu */
input wire [9:0] cw; /* the control word */
output wire [232:0] c0, c1; /* the alu outputs */
/* Temporary results */
wire [232:0] a0sq, a0qu;
wire [232:0] a1sq, a1qu;
wire [232:0] a2sq, a2qu;
wire [232:0] sa2, sa4, sa5, sa7, sa8, sa8_1;
wire [232:0] sc1;
wire [232:0] sd2, sd2_1;
/* Multiplier inputs and output */
wire [232:0] minA, minB, mout;
multiplier mul(minA, minB, mout);
squarer sq1_p0(a0, a0sq);
squarer sq_p1(a1, a1sq);
squarer sq_p2(a2, a2sq);
squarer sq2_p2(a2sq, a2qu);
squarer sq2_p1(a1sq, a1qu);
squarer sq2_p3(a0sq, a0qu);
/* Choose the inputs to the Multiplier */
mux8 muxA(a0, a0sq, a2, sa7, sd2, a1, a1qu, 233'd0, cw[2:0], minA);
mux8 muxB(a1, a1sq, sa4, sa8, sd2_1, a3, a2qu,a1qu, cw[5:3], minB);
/* Choose the outputs of the ALU */
mux4 muxC(mout, sa2, a1sq, sc1, cw[7:6], c0);
mux4 muxD(sa8_1, sa5, a1qu, sd2, cw[9:8], c1);
assign sa2 = mout ^ a2;
assign sa4 = a1sq ^ a2;
assign sa5 = mout ^ a2sq ^ a0;
assign sa7 = a0 ^ a2;
assign sa8 = a1 ^ a3;
assign sa8_1 = mout ^ a0;
assign sc1 = mout ^ a3;
assign sd2 = a0qu ^ a1;
assign sd2_1 = a2sq ^ a3 ^ a1;
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int arr[150]; int main() { int n, k, i, j, ans = 0, curr, temp; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &curr); arr[curr]++; } for (i = 1; i <= 100; i++) { ans += (arr[i] / 2); } ans /= 2; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int z, n, m; while (cin >> n >> m) { if (m > n) z = -1; else { if (n % 2 == 0) z = n / 2; else z = (n / 2) + 1; while (z % m != 0) { z++; } } cout << z; } return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( boolean_expr ) statement ;
// D: Note that initial has to be before always to execute!
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5D always if ( bool_expr) statement \n");
else
$display("PASSED");
$finish;
end
always if( 1'b1 && 1'b1 ) begin
# 1;
value1 = value1 + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class t> t mag(t a) { return a > 0 ? a : -a; } template <class T, class U> T cdiv(T num, U den) { return (num / den) + ((num % den) > 0); } std::ifstream term( /dev/tty ); std::string tempstring; using ll = int_fast64_t; using ii = pair<int, int>; using vi = vector<int>; using vl = vector<ll>; using vii = vector<ii>; const int sij = 60; const ll mod = 1000000007ll; vi took[sij]; int m, n; int esc(int tcase) { cin >> m >> n; for (auto i = 0; i != m; i++) { int tp; cin >> tp; for (auto j = 0; j != tp; j++) { int k; cin >> k; took[i].push_back(k); } sort(took[i].begin(), took[i].end()); } for (auto i = 0; i != m - 1; i++) { set<int> vv; ; for (auto &e : took[i]) { for (auto j = i + 1; j != m; j++) { ; ; if (binary_search(took[j].begin(), took[j].end(), e)) { vv.insert(j); } } }; if (vv.size() + i + 1 != m) { cout << impossible n ; exit(0); } } cout << possible n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc = 1; for (int i = 1; i <= tc; i++) esc(i); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FA_FUNCTIONAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_FUNCTIONAL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:16 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_stub.v
// Design : zynq_design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module zynq_design_1_xbar_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000; set<pair<long long, long long> > q; long long prod(pair<long long, long long> a, pair<long long, long long> b) { return a.first * b.second - a.second * b.first; } bool check(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { return (prod({b.first - a.first, b.second - a.second}, {c.first - a.first, c.second - a.second}) > 0); } const long double eps = 1e-12; void addPoint(long long x, long long y) { while (q.size()) { auto it = q.lower_bound({x, 0}); if (it != q.end() && it->first == x) { if (it->second > y) q.erase(it); else return; } else break; } auto it1 = q.lower_bound({x, 0}); if (it1 != q.end()) { if (it1->second <= y) return; auto it2 = q.lower_bound({x, 0}); it2--; if (!check(*it2, {x, y}, *it1)) return; } while (q.size() > 1) { auto it1 = q.lower_bound({x, 0}); if (it1 == q.end()) break; auto it2 = q.upper_bound(*it1); if (it2 == q.end()) break; if (!check({x, y}, *it1, *it2)) q.erase(it1); else break; } while (q.size()) { auto it1 = q.lower_bound({x, 0}); if (it1 == q.begin()) break; it1--; if (it1 == q.begin()) break; auto it2 = q.lower_bound({x, 0}); it2--; it2--; if (!check(*it2, *it1, {x, y})) q.erase(it1); else break; } q.insert({x, y}); } long long maxx = 0, yy = 0; long double f(long double x) { if ((long double)q.rbegin()->first + eps < x) return 1e14; pair<int, int> it1 = *q.lower_bound({(long long)(x - eps), 0}); if (abs(it1.first - x) < eps) return it1.second; auto kek = q.lower_bound({(long long)(x - eps), 0}); kek--; pair<int, int> it2 = *kek; long double X = it1.first, Y = it1.second, XX = it2.first, YY = it2.second; long double a = YY - Y, b = X - XX, c = -a * X - b * Y; return (-a * x - c) / b; } int main() { ios::sync_with_stdio(0); int qq; long long m; cin >> qq >> m; int j = 0; q.insert({0, 0}); int k = 0; for (int i = 1; i <= qq; i++) { int k, a, b; cin >> k >> a >> b; if (k == 1) { long long x = (a + j) % MOD + 1; long long y = (b + j) % MOD + 1; if (x > maxx) { maxx = x; yy = y; } else if (x == maxx) yy = min(yy, y); addPoint(x, y); } else { k++; long long t = (a + j) % MOD + 1; long long h = (b + j) % MOD + 1; long long x = (h + t - 1) / t; auto it1 = q.lower_bound({x, 0}); bool ok = 0; if (it1 != q.end()) { auto it2 = prev(it1); long long a = it1->second - it2->second, b = it2->first - it1->first, c = -it1->first * a - it1->second * b; if (b < 0) a *= -1, b *= -1, c *= -1; if (-a * h - c * t <= m * b) ok = true; } if (ok) { j = i; cout << YES n ; } else cout << NO n ; } } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostCyc2Wrap_usb1t11.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// Top level module wrapper.
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module usbHostCyc2Wrap_usb1t11(
clk_i,
rst_i,
address_i,
data_i,
data_o,
we_i,
strobe_i,
ack_o,
irq,
usbClk,
USBWireVPin,
USBWireVMin,
USBWireVPout,
USBWireVMout,
USBWireOE_n,
USBFullSpeed
);
input clk_i;
input rst_i;
input [7:0] address_i;
input [7:0] data_i;
output [7:0] data_o;
input we_i;
input strobe_i;
output ack_o;
output irq;
input usbClk;
input USBWireVPin /* synthesis useioff=1 */;
input USBWireVMin /* synthesis useioff=1 */;
output USBWireVPout /* synthesis useioff=1 */;
output USBWireVMout /* synthesis useioff=1 */;
output USBWireOE_n /* synthesis useioff=1 */;
output USBFullSpeed /* synthesis useioff=1 */;
wire clk_i;
wire rst_i;
wire [7:0] address_i;
wire [7:0] data_i;
wire [7:0] data_o;
wire irq;
wire usbClk;
wire USBWireDataOutTick;
wire USBWireDataInTick;
wire USBFullSpeed;
//internal wiring
wire hostSOFSentIntOut;
wire hostConnEventIntOut;
wire hostResumeIntOut;
wire hostTransDoneIntOut;
wire slaveSOFRxedIntOut;
wire slaveResetEventIntOut;
wire slaveResumeIntOut;
wire slaveTransDoneIntOut;
wire slaveNAKSentIntOut;
wire USBWireCtrlOut;
wire [1:0] USBWireDataIn;
wire [1:0] USBWireDataOut;
assign irq = hostSOFSentIntOut | hostConnEventIntOut |
hostResumeIntOut | hostTransDoneIntOut;
assign USBWireDataIn = {USBWireVPin, USBWireVMin};
assign {USBWireVPout, USBWireVMout} = USBWireDataOut;
assign USBWireOE_n = ~USBWireCtrlOut;
//Parameters declaration:
defparam usbHostInst.HOST_FIFO_DEPTH = 64;
parameter HOST_FIFO_DEPTH = 64;
defparam usbHostInst.HOST_FIFO_ADDR_WIDTH = 6;
parameter HOST_FIFO_ADDR_WIDTH = 6;
usbHost usbHostInst (
.clk_i(clk_i),
.rst_i(rst_i),
.address_i(address_i),
.data_i(data_i),
.data_o(data_o),
.we_i(we_i),
.strobe_i(strobe_i),
.ack_o(ack_o),
.usbClk(usbClk),
.hostSOFSentIntOut(hostSOFSentIntOut),
.hostConnEventIntOut(hostConnEventIntOut),
.hostResumeIntOut(hostResumeIntOut),
.hostTransDoneIntOut(hostTransDoneIntOut),
.USBWireDataIn(USBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(USBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(USBWireCtrlOut),
.USBFullSpeed(USBFullSpeed));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> edge[100005]; int v[100005]; bool cycle = false; int mx = -1, last; void dfs(int u, int dis = 0) { v[u] = 1; if (dis > mx) { mx = dis; last = u; } for (int i = 0; i <= (int)((int)edge[u].size() - 1); i++) { int first = edge[u][i]; if (!v[first]) dfs(first, dis + 1); } } int main() { int T, n, m, a, b; scanf( %d , &n); scanf( %d , &m); for (int i = 1; i <= (int)(m); i++) { scanf( %d%d , &a, &b); edge[a].push_back(b); edge[b].push_back(a); } dfs(1); memset(v, 0, sizeof(v)); mx = -1; dfs(last); printf( %d , mx); return 0; }
|
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