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#include <bits/stdc++.h> using namespace std; int main() { int N, F, M; cin >> N >> F >> M; int FR[200], MO[200]; vector<int> V; int mi = 10000; for (int i = 0; i < F; ++i) cin >> FR[i]; for (int j = 0; j < M; ++j) cin >> MO[j]; for (int i = 0; i < F; ++i) { int cnt = 0; for (int j = 0; j < M; ++j) if (MO[j] % FR[i] == 0) cnt++; if (cnt < mi) { V.clear(); V.push_back(i + 1); mi = cnt; } else if (mi == cnt) V.push_back(i + 1); } cout << V.size() << endl; for (int i = 0; i < V.size(); ++i) { if (i < V.size() - 1) cout << V[i] << ; else cout << V[i] << endl; } }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } int main() { int t; cin >> t; while (t--) { int n; string s; cin >> n >> s; int a = n, b = n; for (int i = 0; i < n; i++) if (s[i] == > ) { a = i; break; } for (int i = n - 1; i >= 0; i--) if (s[i] == < ) { b = n - i - 1; break; } printf( %d n , min(a, b)); } return 0; }
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//////////////////////////////////////////////////////////////////////////////////
// SCFIFO_80x64_withCount for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: Single clock FIFO (288 width, 16 depth) wrapper
// Module Name: DRSCFIFO_288x16_withCount
// File Name: DRSCFIFO_288x16_withCount.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DRSCFIFO_288x16_withCount
(
input iClock ,
input iReset ,
input [287:0] iPushData ,
input iPushEnable ,
output oIsFull ,
output [287:0] oPopData ,
input iPopEnable ,
output oIsEmpty ,
output [3:0] oDataCount
);
DRSCFIFO288x16WC
Inst_DPBSCFIFO288x16WC
(
.clk (iClock ),
.srst (iReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty ),
.data_count (oDataCount )
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long cdiff, d, diff, rem, c, n, m, i, k = 0, j, flag = 0, x, minstep = 10000000000; cin >> n; long long b[n]; for (i = 0; i < n; i++) cin >> b[i]; if (n < 3) cout << 0 ; else { cdiff = b[0] - b[n - 1]; diff = abs(b[0] - b[n - 1]); rem = diff % (n - 1); d = cdiff / (n - 1); if (rem > 2 && rem < n - 3) cout << -1 << endl; else { if (rem == 2 || rem == 0 || rem == 1) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] - (i * d)) > 1 || b[i] - (b[0] - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (rem == 2 || rem == 0 || rem == 1) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] + 1 - (i * d)) > 1 || b[i] - (b[0] + 1 - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] + 1 - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (rem == 2 || rem == 0 || rem == 1) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] - 1 - (i * d)) > 1 || b[i] - (b[0] - 1 - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] - 1 - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (cdiff > 0) x = 1; else if (cdiff < 0) x = -1; else x = 0; d = (cdiff / (n - 1)) + x; if (rem == n - 2 || rem == n - 3) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] - (i * d)) > 1 || b[i] - (b[0] - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (rem == n - 3 || rem == n - 2) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] + 1 - (i * d)) > 1 || b[i] - (b[0] + 1 - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] + 1 - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (rem == n - 3 || rem == n - 2) { c = 0; flag = 0; for (i = 0; i < n; i++) { if (b[i] - (b[0] - 1 - (i * d)) > 1 || b[i] - (b[0] - 1 - (i * d)) < -1) { flag = 1; break; } else if (b[i] - (b[0] - 1 - (i * d)) != 0) { c++; } } if (flag == 0) minstep = min(c, minstep); } if (minstep == 10000000000) cout << -1 << endl; else cout << minstep << endl; } } return 0; }
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#include <bits/stdc++.h> using namespace std; long long n, root, val, rem; int main() { cin >> n; root = floor((sqrt(1.0 + 8.0 * n) - 1.0) / 2.0); val = root * (root + 1) / 2; if (n == val) --root; val = root * (root + 1) / 2; rem = n - val; cout << rem << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/14/2016 06:25:09 AM
// Design Name:
// Module Name: Exp_operation_m
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation_m
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//underflow
input wire load_b_i,//overflow
input wire load_c_i,//result
input wire [EW:0] Data_A_i,
input wire [EW:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
///////////////////////////////////////////////
wire [EW:0] Data_S;
wire Overflow_A;
wire Overflow_flag_A;
wire underflow_exp_reg;
wire [EW:0] U_Limit;
/////////////////////////////Exponent calculation///
add_sub_carry_out #(.W(EW+1)) exp_add_subt_m(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S ({Overflow_A,Data_S})
);
RegisterMult #(.W(EW+1)) exp_result_m(
.clk (clk),
.rst (rst),
.load (load_c_i),
.D (Data_S),
.Q (Data_Result_o)
);
//Overflow/////////////////////////////////
RegisterMult#(.W(1)) Oflow_A_m (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Overflow_A),
.Q(Overflow_flag_A)
);
assign Overflow_flag_o = Overflow_flag_A | Data_Result_o[EW];
//Underflow//////////////////////////////
Comparator_Less #(.W(EW+1)) Exp_unflow_Comparator_m (
.Data_A(Data_S),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) Underflow_m (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(underflow_exp_reg),
.Q(Underflow_flag_o)
);
generate
if (EW == 8)
assign U_Limit = 9'd127;
else
assign U_Limit = 12'd1023;
endgenerate
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::istream& operator>>(std::istream& i, pair<T, U>& p) { i >> p.first >> p.second; return i; } template <typename T> std::istream& operator>>(std::istream& i, vector<T>& t) { for (auto& v : t) { i >> v; } return i; } template <typename T, typename U> std::ostream& operator<<(std::ostream& o, const pair<T, U>& p) { o << p.first << << p.second; return o; } template <typename T> std::ostream& operator<<(std::ostream& o, const vector<T>& t) { if (t.empty()) o << n ; for (size_t i = 0; i < t.size(); ++i) { o << t[i] << n [i == t.size() - 1]; } return o; } template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T, vector<T>, less<T>>; template <typename T> bool in(T a, T b, T c) { return a <= b && b < c; } unsigned int logceil(long long first) { return first ? 8 * sizeof(long long) - __builtin_clzll(first) : 0; } namespace std { template <typename T, typename U> struct hash<pair<T, U>> { hash<T> t; hash<U> u; size_t operator()(const pair<T, U>& p) const { return t(p.first) ^ (u(p.second) << 7); } }; } // namespace std template <typename T, typename F> T bsh(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { l = m + 1; r = m; } else { h = m - 1; } } return r; } template <typename F> double bshd(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { l = m; } else { h = m; } } return (l + h) / 2; } template <typename T, typename F> T bsl(T l, T h, const F& f) { T r = -1, m; while (l <= h) { m = (l + h) / 2; if (f(m)) { h = m - 1; r = m; } else { l = m + 1; } } return r; } template <typename F> double bsld(double l, double h, const F& f, double p = 1e-9) { unsigned int r = 3 + (unsigned int)log2((h - l) / p); while (r--) { double m = (l + h) / 2; if (f(m)) { h = m; } else { l = m; } } return (l + h) / 2; } template <typename T> T gcd(T a, T b) { if (a < b) swap(a, b); return b ? gcd(b, a % b) : a; } template <typename T> class vector2 : public vector<vector<T>> { public: vector2() {} vector2(size_t a, size_t b, T t = T()) : vector<vector<T>>(a, vector<T>(b, t)) {} }; template <typename T> class vector3 : public vector<vector2<T>> { public: vector3() {} vector3(size_t a, size_t b, size_t c, T t = T()) : vector<vector2<T>>(a, vector2<T>(b, c, t)) {} }; template <typename T> class vector4 : public vector<vector3<T>> { public: vector4() {} vector4(size_t a, size_t b, size_t c, size_t d, T t = T()) : vector<vector3<T>>(a, vector3<T>(b, c, d, t)) {} }; template <typename T> class vector5 : public vector<vector4<T>> { public: vector5() {} vector5(size_t a, size_t b, size_t c, size_t d, size_t e, T t = T()) : vector<vector4<T>>(a, vector4<T>(b, c, d, e, t)) {} }; class ENeatness { public: int N, A, B, X, Y; string Sol; vector<vector<bool>> L, V; vector<int> LOX, HIX, LOY, HIY; constexpr char op(char c) { switch (c) { case L : return R ; case R : return L ; case D : return U ; case U : return D ; case 1 : return 2 ; case 2 : return 1 ; default: return x ; } } void goUp() { if (A == 0) return; while (B > 0 && L[A][B - 1]) { add( L ); --B; } while (B < N - 1 && !L[A - 1][B] && L[A][B + 1]) { add( R ); ++B; } if (L[A - 1][B]) { --A; add( U ); goUp(); } } void goDown() { if (A == N - 1) return; while (B > 0 && L[A][B - 1]) { add( L ); --B; } while (B < N - 1 && !L[A + 1][B] && L[A][B + 1]) { add( R ); ++B; } if (L[A + 1][B]) { ++A; add( D ); goDown(); } } void turnOffAndDown() { if (A == X) return; int b = -1; for (int i = 0; i < N; ++i) { if (L[A][i] && L[A + 1][i]) { b = i; } } while (B > 0 && L[A][B - 1]) { add( L ); --B; } while (B < N - 1 && L[A][B + 1]) { if (B != b) { add( 2 ); L[A][B] = false; } add( R ); ++B; } if (B != b) { add( 2 ); L[A][B] = false; } while (B != b) { add( L ); --B; } add( 2 ); L[A][B] = false; add( D ); ++A; turnOffAndDown(); } void turnOffAndUp() { int b = Y; if (A != X) { for (int i = 0; i < N; ++i) { if (L[A][i] && L[A - 1][i]) { b = i; } } } while (B > 0 && L[A][B - 1]) { add( L ); --B; } while (B < N - 1 && L[A][B + 1]) { if (B != b) { add( 2 ); L[A][B] = false; } add( R ); ++B; } if (B != b) { add( 2 ); L[A][B] = false; } while (B != b) { add( L ); --B; } add( 2 ); L[A][B] = false; if (A == X) return; add( U ); --A; turnOffAndUp(); } void add(char c) { if (!Sol.empty() && Sol.back() == op(c)) Sol.pop_back(); else Sol.push_back(c); } void bfs(int i, int j) { if (V[i][j]) return; V[i][j] = true; if (!L[i][j]) { add( 1 ); L[i][j] = true; LOX[i] = min(LOX[i], j); HIX[i] = max(HIX[i], j); LOY[j] = min(LOY[j], i); HIY[j] = max(HIY[j], i); } if (LOX[i] < j) { add( L ); bfs(i, j - 1); add( R ); } if (HIX[i] > j) { add( R ); bfs(i, j + 1); add( L ); } if (LOY[j] < i) { add( U ); bfs(i - 1, j); add( D ); } if (HIY[j] > i) { add( D ); bfs(i + 1, j); add( U ); } } void solve(istream& cin, ostream& cout) { cin >> N >> A >> B; L = vector2<bool>(N, N); V = vector2<bool>(N, N, false); for (auto& l : L) { for (int i = 0; i < N; ++i) { bool c; cin >> c; l[i] = c; } } LOX.assign(N, N); LOY.assign(N, N); HIX.assign(N, -1); HIY.assign(N, -1); for (int i = 0; i < N; ++i) { for (int j = 0; j < N; ++j) { if (L[i][j]) { LOX[i] = min(LOX[i], j); HIX[i] = max(HIX[i], j); LOY[j] = min(LOY[j], i); HIY[j] = max(HIY[j], i); } } } --A; --B; X = A; Y = B; bfs(A, B); goUp(); turnOffAndDown(); goDown(); turnOffAndUp(); for (int i = 0; i < N; ++i) { for (int j = 0; j < N; ++j) { if (L[i][j]) { cout << NO n ; return; } } } cout << YES n << Sol << n ; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); ENeatness solver; std::istream& in(std::cin); std::ostream& out(std::cout); solver.solve(in, out); return 0; }
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#include <iostream> #include <cstdio> #define mod 998244353 #define int long long using namespace std; int n,k,sa[200005],rk[200005]; int num; inline int Qpow(register int a,register int p){ if (p==0)return 1; register int t=Qpow(a,p/2); t=t*t%mod; if (p%2==1)t=t*a%mod; return t; } inline int inv(register int x){ return Qpow(x,mod-2); } inline int C(register int n,register int m){ if (n<m||m<0)return 0; register int ans=1; for (register int i=1;i<=n;i++)ans=ans*i%mod; for (register int i=1;i<=m;i++)ans=ans*inv(i)%mod; for (register int i=1;i<=n-m;i++)ans=ans*inv(i)%mod; return ans; } signed main(){ cin>>n>>k; for (register int i=1;i<=n;i++){ scanf( %d ,&sa[i]); sa[i]++; rk[sa[i]]=i; } for (register int i=1;i<n;i++) if (rk[sa[i]+1]>rk[sa[i+1]+1])k--; cout<<C(n+k-1,k-1)<<endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
`define SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; inline int in() { int x; scanf( %d , &x); return x; } template <typename T> inline istream& operator>>(istream& i, vector<T>& v) { for (int j = 0; j < ((int)(v).size()); ++j) i >> v[j]; return i; } template <typename T> string join(const vector<T>& v) { stringstream s; for (int i = 0; i < ((int)(v).size()); ++i) s << << v[i]; return s.str().substr(1); } template <typename T> inline ostream& operator<<(ostream& o, const vector<T>& v) { if ((int)(v).size()) o << join(v); return o; } template <typename T1, typename T2> inline istream& operator>>(istream& i, pair<T1, T2>& v) { return i >> v.first >> v.second; } template <typename T1, typename T2> inline ostream& operator<<(ostream& o, const pair<T1, T2>& v) { return o << v.first << , << v.second; } template <typename T> inline long long int suma(const vector<T>& a) { long long int res(0); for (auto&& x : a) res += x; return res; } const double eps = 1e-10; const long long int LINF = 1001002003004005006ll; const int INF = 1001001001; const int MX = 200005; int n, m; int dp[55][55][55]; struct Q { int l, r, x, c; int cost(int i, int h) { if (l <= i && i < r && h > x) return c; return 0; } }; vector<Q> q; int dfs(int l, int r, int h) { if (l == r) return 0; int& now = dp[l][r][h]; if (now != -1) return now; now = 0; if (h) now = dfs(l, r, h - 1); for (int i = l; i < r; ++i) { int c = h * h; for (int k = 0; k < (m); ++k) { if (l <= q[k].l && q[k].r <= r) c -= q[k].cost(i, h); } c += dfs(l, i, h) + dfs(i + 1, r, h); (now = max(now, c)); } return now; } int main() { int h; cin >> n >> h >> m; q = vector<Q>(m); for (int i = 0; i < (m); ++i) { int l, r, x, c; scanf( %d%d%d%d , &l, &r, &x, &c); --l; q[i] = (Q){l, r, x, c}; } for (int i = 0; i < (n); ++i) for (int j = 0; j < (n + 1); ++j) for (int k = 0; k < (h + 1); ++k) dp[i][j][k] = -1; int ans = dfs(0, n, h); cout << ans << endl; return 0; }
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module ArithAlu(
/* verilator lint_off UNUSED */
clk,
opMode,
srca,
srcb,
dst,
sri,
sro
);
input clk;
input[4:0] opMode;
input[31:0] srca;
input[31:0] srcb;
output[31:0] dst;
input[3:0] sri;
output[3:0] sro;
parameter[4:0] UOP_NONE = 5'h00;
parameter[4:0] UOP_ADD = 5'h01;
parameter[4:0] UOP_SUB = 5'h02;
parameter[4:0] UOP_MUL = 5'h03;
parameter[4:0] UOP_AND = 5'h04;
parameter[4:0] UOP_OR = 5'h05;
parameter[4:0] UOP_XOR = 5'h06;
parameter[4:0] UOP_SHL = 5'h07;
parameter[4:0] UOP_SHR = 5'h08;
parameter[4:0] UOP_SAR = 5'h09;
parameter[4:0] UOP_ADDC = 5'h14;
parameter[4:0] UOP_ADDV = 5'h15;
parameter[4:0] UOP_SUBC = 5'h16;
parameter[4:0] UOP_SUBV = 5'h17;
parameter[4:0] UOP_TEST = 5'h18;
parameter[4:0] UOP_CMPEQ = 5'h1B;
parameter[4:0] UOP_CMPGT = 5'h1C;
parameter[4:0] UOP_CMPGE = 5'h1D;
parameter[4:0] UOP_CMPHS = 5'h1E;
parameter[4:0] UOP_CMPHI = 5'h1F;
/* verilator lint_off UNOPTFLAT */
reg[31:0] tDst;
reg[5:0] tShl;
reg[3:0] tSr;
reg tCvo;
assign dst=tDst;
assign sro=tSr;
always @ (opMode) begin
tSr=sri;
case(opMode)
UOP_ADD: begin
tDst = srca+srcb;
end
UOP_SUB: begin
tDst = srca-srcb;
end
UOP_MUL: begin
tDst = srca*srcb;
end
UOP_AND: begin
tDst = srca&srcb;
end
UOP_OR: begin
tDst = srca|srcb;
end
UOP_XOR: begin
tDst = srca^srcb;
end
UOP_SHL: begin
tShl = srcb[5:0];
tDst = srca<<tShl;
end
UOP_SHR: begin
tShl = srcb[5:0];
tDst = srca>>tShl;
end
UOP_SAR: begin
tShl = srcb[5:0];
tDst = srca>>>tShl;
end
UOP_ADDC: begin
if(sri[0])
tDst = srca+srcb+1;
else
tDst = srca+srcb;
tSr[0]=tDst[31]^srca[31];
end
UOP_ADDV: begin
{tCvo, tDst} = {srca[31], srca} + {srcb[31], srcb};
tSr[0]=tDst[31]^tCvo;
end
UOP_SUBC: begin
if(sri[0])
tDst = srca-srcb-1;
else
tDst = srca-srcb;
tSr[0]=tDst[31]^srca[31];
end
UOP_SUBV: begin
{tCvo, tDst} = {srca[31], srca} - {srcb[31], srcb};
tSr[0]=tDst[31]^tCvo;
end
UOP_TEST: begin
tDst = srca&srcb;
tSr[3:2]=sri[3:2];
tSr[0]=(tDst==0);
end
UOP_CMPEQ: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]==srcb[31:0]);
end
UOP_CMPGT: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
end
UOP_CMPGE: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
end
UOP_CMPHS: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
end
UOP_CMPHI: begin
tDst = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
end
default: begin
tDst = 32'h0000_0000;
tSr=sri;
end
endcase
end
endmodule
|
// Released under GPL2.0
// (c) 2002 Tom Verbeure
module main;
integer myInt;
reg [39:0] myReg40;
reg [0:39] myReg40r;
reg [0:38] myReg39r;
reg [13:0] myReg14;
reg [7:0] myReg8;
reg [31:0] myReg32;
initial begin
$display("============================ myReg14 = -10");
myReg14 = -10;
$display(">|16374|");
$display("*|%d|", myReg14);
$display("*|%0d|", myReg14);
$display("*|",myReg14,"|");
$display("============================ myReg14 = 65");
myReg14 = 65;
$display(">| 65|");
$display("*|%d|", myReg14);
$display("*|",myReg14,"|");
$display(">|65|");
$display("*|%0d|", myReg14);
$display(">|0041|");
$display("*|%h|", myReg14);
$display(">|41|");
$display("*|%0h|", myReg14);
$display(">|00101|");
$display("*|%o|", myReg14);
$display(">|101|");
$display("*|%0o|", myReg14);
$display(">|00000001000001|");
$display("*|%b|", myReg14);
$display(">||");
$display("*|%0b|", myReg14);
$display(">| A|");
$display("*|%s|", myReg14);
$display(">|A|");
$display("*|%0s|", myReg14);
$display("============================ myInt = -10");
myInt = -10;
$display(">| -10|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|-10|");
$display("*|%0d|", myInt);
$display(">|fffffff6|");
$display("*|%h|", myInt);
$display("*|%0h|", myInt);
$display(">|37777777766|");
$display("*|%o|", myInt);
$display("*|%0o|", myInt);
$display(">|11111111111111111111111111110110|");
$display("*|%b|", myInt);
$display("*|%0b|", myInt);
$display("============================ myReg32 = -10");
myReg32 = -10;
$display(">||");
$display("*|%d|", myReg32);
$display("*|%0d|", myReg32);
$display("*|",myReg32,"|");
$display(">|fffffff6|");
$display("*|%h|", myReg32);
$display("*|%0h|", myReg32);
$display(">|37777777766|");
$display("*|%o|", myReg32);
$display("*|%0o|", myReg32);
$display("============================ myInt = 65");
myInt = 65;
$display(">| 65|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|65|");
$display("*|%0d|", myInt);
$display(">|00000041|");
$display("*|%h|", myInt);
$display(">|41|");
$display("*|%0h|", myInt);
$display(">|00000000101|");
$display("*|%o|", myInt);
$display(">|101|");
$display("*|%0o|", myInt);
$display(">|00000000000000000000000001000001|");
$display("*|%b|", myInt);
$display(">||");
$display("*|%0b|", myInt);
$display("*| A|");
$display(">|%s|", myInt);
$display("*|A|");
$display(">|%0s|", myInt);
$display("============================ Print \" A\"");
$display("*| A|");
$display(">|%s|", " A");
$display(">|%0s|", " A");
$display("============================ Print $time");
$display("*| 0|");
$display(">|%t|", $time);
$display("*|0|");
$display(">|%0t|", $time);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T, class U> struct SegmentTree { struct Node { bool hasCarry = 0; int b = 0, e = 0; U carry = U(); T val = T(); Node() {} void join(const Node &l, const Node &r) { val = l.val + r.val; b = l.b; e = r.e; } void update(const U &u) { carry += u; u.update(val, b, e); hasCarry = 1; } void pushDown(Node &l, Node &r) { if (!hasCarry) return; l.update(carry); r.update(carry); carry = U(); hasCarry = 0; } }; vector<Node> V; int N; SegmentTree(int N) : V(4 * N), N(N) {} template <class I> void create(const vector<I> &VEC, int n = 1, int b = 0, int e = -1) { if (e == -1) e = N - 1; if (b == e) { V[n].val = T(VEC[b]), V[n].b = b, V[n].e = e; } else { int m = (b + e) / 2; create(VEC, 2 * n, b, m); create(VEC, 2 * n + 1, m + 1, e); V[n].join(V[2 * n], V[2 * n + 1]); } } T query(int i, int j, int n = 1, int b = 0, int e = -1) { if (e == -1) e = N - 1; if (i <= b && e <= j) return V[n].val; else { V[n].pushDown(V[2 * n], V[2 * n + 1]); int m = (b + e) / 2; if (i > m) return query(i, j, 2 * n + 1, m + 1, e); if (j <= m) return query(i, j, 2 * n, b, m); return query(i, j, 2 * n, b, m) + query(i, j, 2 * n + 1, m + 1, e); } } void update(int i, int j, const U &v, int n = 1, int b = 0, int e = -1) { if (e == -1) e = N - 1; if (i <= b && e <= j) V[n].update(v); else if (i > e || j < b) return; else { V[n].pushDown(V[2 * n], V[2 * n + 1]); int m = (b + e) / 2; update(i, j, v, 2 * n, b, m); update(i, j, v, 2 * n + 1, m + 1, e); V[n].join(V[2 * n], V[2 * n + 1]); } } int findOkPrefix(int i, const function<bool(T)> &isOk) { vector<int> stk; stk.reserve(20); stk.push_back(1); T acum; int sz = 0; while (stk.size()) { int t = stk.back(); stk.pop_back(); Node &n = V[t]; if (n.e < i) continue; T newAcum = sz == 0 ? n.val : (acum + n.val); if (i <= n.b) { if (isOk(newAcum)) { sz += n.e - n.b + 1; acum = newAcum; } else { if (n.b == n.e) return sz; V[t].pushDown(V[t << 1], V[t << 1 | 1]); stk.push_back(2 * t + 1); stk.push_back(2 * t); } } else { V[t].pushDown(V[t << 1], V[t << 1 | 1]); stk.push_back(2 * t + 1); stk.push_back(2 * t); } } } }; struct RRange { int tL, tR, sz; RRange(int v = 0) : tR(v), tL(v), sz(1) {} RRange operator+(const RRange &m) const { RRange r; r.sz = sz + m.sz; r.tL = max(tL, m.tL - sz); r.tR = max(tR - m.sz, m.tR); return r; } friend ostream &operator<<(ostream &os, const RRange &range) { os << ( << range.tL << , << range.tR << ) ; return os; } void normalize(int N) { if (tL + tR + 1 >= N) { tL = 0; tR = N - 1; } sz = 1; } int size() { return tL + tR + 1; } }; struct Void { void update(RRange &m, int b, int e) const {} void operator+=(const Void &s) {} }; int main() { int N; cin >> N; vector<RRange> V(N); for (int i = 0; i < N; ++i) { int n; cin >> n; V[i] = RRange(n); V[i].normalize(N); } vector<vector<RRange>> T(20, vector<RRange>(N)); vector<SegmentTree<RRange, Void>> STS; T[0] = V; auto fn = [](int i, int j, SegmentTree<RRange, Void> &ST, int N) { RRange r = ST.query(max(i, 0), min(j, N - 1)); if (i < 0) r = ST.query(N + i, N - 1) + r; if (j >= N) r = r + ST.query(0, j % N); return r; }; for (int i = 1; i < 20; ++i) { STS.push_back(SegmentTree<RRange, Void>(N)); STS.back().create(T[i - 1]); auto &ST = STS.back(); for (int j = 0; j < N; ++j) { T[i][j] = fn(j - T[i - 1][j].tL, j + T[i - 1][j].tR, ST, N); T[i][j].tL += T[i - 1][j].tL; T[i][j].tR += T[i - 1][j].tR; T[i][j].normalize(N); } } for (int i = 0; i < N; ++i) { RRange mx(0); int ans = 0; for (int j = STS.size() - 1; j >= 0; --j) { RRange t = fn(i - mx.tL, i + mx.tR, STS[j], N); t.tL += mx.tL; t.tR += mx.tR; t.normalize(N); if (t.size() < N) { mx = t; ans |= 1 << j; } } if (mx.size() < N) ans++; cout << ans << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<long long int, long long int> mp; int main() { int n, c = 0, x = 0, a[200], i, j; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; c += a[i]; } if (n == 1) x = 1; if (n == 2 && a[0] == a[1]) x = 1; if (x == 1) cout << -1; else { cout << 1 << endl; for (i = 0; i < n; i++) { if (2 * a[i] != c) { cout << i + 1; break; } } } return 0; }
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module jtag_bus
#(
parameter CPCI_NF2_ADDR_WIDTH = 27,
parameter CPCI_NF2_DATA_WIDTH = 32
)
(
// --- These are sigs to/from pins going to CPCI device
input jtag_rd_wr_L,
input jtag_req,
input [CPCI_NF2_ADDR_WIDTH-1:0] jtag_addr,
input [CPCI_NF2_DATA_WIDTH-1:0] jtag_wr_data,
output wire [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data,
//output wire control_port_read_datavalid,
output reg cpci_wr_rdy,
output /*reg xCG*/ cpci_rd_rdy,
// --- Internal signals to/from register rd/wr logic
//
output fifo_empty, // functions like a bus_req signal
input fifo_rd_en,
output wire bus_rd_wr_L,
output [CPCI_NF2_ADDR_WIDTH-1:0] bus_addr,
output [CPCI_NF2_DATA_WIDTH-1:0] bus_wr_data,
input wire [CPCI_NF2_DATA_WIDTH-1:0] bus_rd_data,
input bus_rd_vld,
// --- Misc
input reset,
input core_clk
);
// --------------------------------------------------------
// Local registers/wires
// --------------------------------------------------------
// all p2n_* signals are cpci signals registered
reg p2n_rd_wr_L;
reg p2n_req;
reg p2n_req_d1;
reg [CPCI_NF2_ADDR_WIDTH-1:0] p2n_addr;
reg [CPCI_NF2_DATA_WIDTH-1:0] p2n_wr_data;
reg p2n_wr_rdy;
reg p2n_rd_rdy;
reg cpci_wr_rdy_nxt;
reg cpci_rd_rdy_nxt;
//reg cpci_wr_rdy;
//reg cpci_rd_rdy;
wire p2n_almost_full;
wire p2n_prog_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] n2p_rd_data;
wire n2p_rd_rdy;
// Read/write enables for the N2P fifo
wire n2p_rd_en;
wire n2p_wr_en;
// Full/empty signals for n2p fifo
wire n2p_fifo_empty;
wire n2p_almost_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] cpci_rd_data_nxt;
reg [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data_reg;
reg jtag_rd_datavalid_reg;
// -----------------------------------------------------------------
// - Registering of all P2N signals
// -----------------------------------------------------------------
/* We register everything coming in from the pins so that we have a
timing-consistent view of the signals.
Note: the wr_rdy and rd_rdy signals are recorded as we need to be able to
identify whether the other would have recorded the operation as a success
or failure
*/
always @(posedge core_clk) begin
p2n_rd_wr_L <= jtag_rd_wr_L;
p2n_addr <= jtag_addr;
p2n_req <= jtag_req;
p2n_wr_data <= jtag_wr_data;
p2n_wr_rdy <= cpci_wr_rdy;
p2n_rd_rdy <= cpci_rd_rdy;
end
always @(*) begin
//if (bus_rd_vld) begin
jtag_rd_data_reg = bus_rd_data;
jtag_rd_datavalid_reg = bus_rd_vld;
//end xCG
end
assign jtag_rd_data = jtag_rd_data_reg;
assign control_port_read_datavalid = jtag_rd_datavalid_reg;
assign cpci_rd_rdy = jtag_rd_datavalid_reg; //xCG
/*
-----------------------------------------------------------------
- CPCI -> NF2 requests
-----------------------------------------------------------------
*/
// All requests get funnelled into a 60-bit wide FIFO.
// 60-bits = 32 (data) + 27 (address) + 1 (rd_wr_L)
// Write in new addr/data when req and wr_rdy are high
// In the current design, the CPCI chip PCI clock period is 30ns, the register
// access interface between the CPCI chip and the NetFPGA chip has clock period 16ns,
// the NetFPGA chip internal clock period is 8ns.
// The pkt DMA TX is through the register access interface at this moment (to be
// changed to use the dedicated DMA interface later). So there are a few performance
// requirements:
// 1. When DMA TX is in progress, the register access interface will see register
// write requests back to back on two consecutive clock cycles sometimes.
// 2. The reg_grp and the DMA module must finish acking to DMA TX register write request
// in no more than 3 clock cycles (3 * 8ns = 24ns < 30ns) to prevent the p2n fifo
// from filling up and overflowing. The DMA TX queue full signal to CPCI chip
// is currently indicating whether the cpu queue is full, not whether the pci2net_fifo
// is full.
reg [1:0] p2n_state;
reg [1:0] p2n_state_nxt;
reg p2n_wr_en;
wire p2n_full;
localparam
P2N_IDLE = 2'h 0,
READING = 2'h 1,
P2N_RD_DONE = 2'h 2;
// this state machine runs in the pci-clk domain
always @* begin
// set default values
p2n_wr_en = 1'b0;
p2n_state_nxt = p2n_state;
if (reset)
p2n_state_nxt = P2N_IDLE;
else begin
case (p2n_state)
P2N_IDLE: begin
// Only process the request if the PCI2NET fifo has space for the
// request
if (p2n_req && !p2n_full) begin
p2n_wr_en = 1'b1;
if (p2n_rd_wr_L)
p2n_state_nxt = READING;
end // if
end // P2N_IDLE
READING: begin
// Wait until the result is ready to return
if (p2n_rd_rdy)
p2n_state_nxt = P2N_RD_DONE;
end //READING
P2N_RD_DONE:
// Don't return to idle until the other side deasserts the request
// signal
if ( ! p2n_req )
p2n_state_nxt = P2N_IDLE;
endcase
end
end
always @(posedge core_clk) begin
p2n_state <= p2n_state_nxt;
end
always @*
if (reset) begin
cpci_wr_rdy_nxt = 1'b0;
cpci_rd_rdy_nxt = 1'b0;
end
else begin
cpci_wr_rdy_nxt = !p2n_prog_full;
//cpci_rd_rdy_nxt = !fifo_empty; xCG, original fifo was in different direction
end
always @(posedge core_clk) begin
//cpci_rd_rdy <= cpci_rd_rdy_nxt; xCG
cpci_wr_rdy <= cpci_wr_rdy_nxt;
end
/*
-----------------------------------------------------------------
- NF2 -> CPCI responses
-----------------------------------------------------------------
*/
// Fifo to cross from the PCI clock domain to the core domain
/*
pci2net_16x60 pci2net_fifo (
.din ({p2n_rd_wr_L, p2n_addr, p2n_wr_data}),
.rd_clk (core_clk),
.rd_en (fifo_rd_en),
.rst (reset),
.wr_clk (pci_clk),
.wr_en (p2n_wr_en),
.almost_full (p2n_almost_full),
.prog_full (p2n_prog_full),
.dout ({bus_rd_wr_L, bus_addr, bus_wr_data}),
.empty (fifo_empty),
.full (p2n_full)
);
*/
pci2net_16x60 pci2net_fifo (
.aclr ( reset ),
.clock ( core_clk ),
.data ( {p2n_rd_wr_L, p2n_addr, p2n_wr_data} ),
.rdreq ( fifo_rd_en ),
.wrreq ( p2n_wr_en ),
.almost_empty ( ),
.almost_full ( p2n_prog_full ),
.empty ( fifo_empty ),
.full ( p2n_full ),
.q ( {bus_rd_wr_L, bus_addr, bus_wr_data} ),
.usedw ( )
);
// synthesis translate_on
endmodule // cpci_bus
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/03 11:30:00
// Design Name:
// Module Name: lab3_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab3_tb();
reg INPUT,Clk, reset;
parameter DELAY=10;
parameter TIME=150;
wire OUT;
integer i;
lab3_d DUT (.INPUT(INPUT), .Clk(Clk), .OUT(OUT), .reset(reset));
initial
begin
#TIME $finish;
end
initial begin
Clk = 0;
for (i = 0; i < (TIME/DELAY); i = i + 1) begin
#DELAY Clk = ~Clk;
end
end
initial
begin
reset = 1; INPUT = 0;
#(2*DELAY) reset = 0;
#DELAY INPUT=1;
#(2*DELAY) INPUT=1;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=1;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=0;
#(2*DELAY) INPUT=0;
#DELAY;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0; bool flg = false; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) flg = true; for (; isdigit(ch); ch = getchar()) x = (x << 3) + (x << 1) + (ch ^ 48); return flg ? -x : x; } int n; struct P { long long x, y; } p[100010]; P operator-(const P &x, const P &y) { return P{x.x - y.x, x.y - y.y}; } long long cross(const P &x, const P &y) { return x.x * y.y - x.y * y.x; } long long dot(const P &x, const P &y) { return x.x * y.x + x.y * y.y; } long long dot(const P &x) { return x.x * x.x + x.y * x.y; } bool solve() { n = read(); for (int i(1), _i(n); i <= _i; i++) { int x = read(), y = read(); p[i] = P{x, y}; } p[n + 1] = p[1]; if (n & 1) return 0; int m = n >> 1; for (int i(1), _i(m); i <= _i; i++) { if (cross(p[i + m + 1] - p[i + m], p[i + 1] - p[i])) return 0; if (dot(p[i + m + 1] - p[i + m], p[i + 1] - p[i]) >= 0) return 0; if (dot(p[i + m + 1] - p[i + m]) != dot(p[i + 1] - p[i])) return 0; } return 1; } int main() { for (int T = 1; T--;) puts(solve() ? yes : no ); return 0; }
|
//
// $ ../nli handshake.n
// $ iverilog tb_handshake.v handshake.v
//
`timescale 1ns/1ns
module tb_handshake;
reg clk, rst;
wire [31:0] channel_out_data;
wire channel_out_en;
reg channel_out_ack;
reg [31:0] channel_in_data;
reg channel_in_en;
wire channel_in_ack;
initial begin
clk <= 0;
rst <= 1;
channel_out_ack <= 0;
channel_in_data <= 0;
channel_in_en <= 0;
#105
rst <= 0;
#1000
$finish;
end
always begin
#10 clk = ~clk;
end
always @(posedge clk) begin
if (!rst) begin
if (!channel_in_ack) begin
channel_in_data <= 123;
channel_in_en <= 1;
end else begin
channel_in_en <= 0;
end
if (channel_out_en && !channel_out_ack) begin
channel_out_ack <= 1;
$display("data output %d [%t]", channel_out_data, $time);
end else begin
channel_out_ack <= 0;
end
end
end
handshake dut(.clk(clk), .rst(rst),
.channel_out_data(channel_out_data),
.channel_out_en(channel_out_en),
.channel_out_ack(channel_out_ack),
.channel_in_data(channel_in_data),
.channel_in_en(channel_in_en),
.channel_in_ack(channel_in_ack));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 502; int n, m, l = -1, ok = 1, r; string s[N]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int j = 0; j < n; j++) { l = r = -1; for (int i = 0; i < s[j].length(); i++) { if (l == -1 && s[j][i] == X ) l = r = i; else if (l != -1 && s[j][i] == X ) { r = i; } } if (l != -1) break; } if (l == -1) { cout << NO ; return 0; } for (int i = 0; i < n; i++) { int cnt = 0; for (int j = l; j <= r; j++) if (s[i][j] == X ) cnt++; if (cnt != r - l + 1 && cnt != 0) ok = 0; } if (ok == 1) for (int i = 0; i < n; i++) for (int j = 0; j < s[i].length(); j++) if ((j < l || j > r) && s[i][j] == X ) ok = 0; if (ok) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void setup() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(15); } int dx[] = {1, -1, 0, 0, 0, 0}; int dy[] = {0, 0, 1, -1, 0, 0}; int dz[] = {0, 0, 0, 0, 1, -1}; int k, n, m; int ANS = 0; string x[10][10]; int vis[10][10][10]; void dfs(int sz, int sx, int sy) { int i; ANS++; vis[sx][sy][sz] = 1; int nx, ny, nz; for (i = 0; i < 6; i++) { nx = sx + dx[i]; ny = sy + dy[i]; nz = sz + dz[i]; if (nx >= 0 && nx < n && ny >= 0 && ny < m && nz >= 0 && nz < k) if (!vis[nx][ny][nz] && x[nz][nx][ny] == . ) dfs(nz, nx, ny); } } int main() { int i, j, tx, ty; cin >> k >> n >> m; string blank; for (i = 0; i < k; i++) { for (j = 0; j < n; j++) cin >> x[i][j]; } cin >> tx >> ty; tx--, ty--; if (x[0][tx][ty] == . ) dfs(0, tx, ty); cout << ANS << n ; return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_and_gate.v
//
// *Module Description:
// Generic AND gate cell for the openMSP430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_and_gate (
// OUTPUTs
y, // AND gate output
// INPUTs
a, // AND gate input A
b // AND gate input B
);
// OUTPUTs
//=========
output y; // AND gate output
// INPUTs
//=========
input a; // AND gate input A
input b; // AND gate input B
//=============================================================================
// 1) SOME COMMENTS ON THIS MODULE
//=============================================================================
//
// In its ASIC version, some combinatorial pathes of the openMSP430 are
// sensitive to glitches, in particular the ones generating the wakeup
// signals.
// To prevent synthesis from optmizing combinatorial clouds into glitchy
// logic, this AND gate module has been instanciated in the critical places.
//
// Make sure that synthesis doesn't ungroup this module. As an alternative,
// a standard cell from the library could also be directly instanciated here
// (don't forget the "dont_touch" attribute)
//
//
//=============================================================================
// 2) AND GATE
//=============================================================================
assign y = a & b;
endmodule // omsp_and_gate
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, ans1 = 0, ans2 = 0; cin >> n; vector<int> c(n); for (int i = 0; i < n; i++) cin >> c[i]; cin >> a >> b; if (a > b) swap(a, b); a--; b--; for (int i = a; i < b; i++) { ans1 += c[i]; } for (int i = 0; i < a; i++) { ans2 += c[i]; } for (int i = b; i < n; i++) { ans2 += c[i]; } cout << min(ans1, ans2); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:04 03/31/2015
// Design Name: zlozony
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/sr/lab4/zlozony/src/tb_zlozony.v
// Project Name: zlozony
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: zlozony
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_zlozony;
// Inputs
reg clk;
reg ce;
reg [17:0] a;
reg [7:0] b;
reg [11:0] c;
reg [7:0] d;
reg [13:0] e;
reg [18:0] f;
// Outputs
wire [36:0] y;
// Instantiate the Unit Under Test (UUT)
zlozony uut (
.clk(clk),
.ce(ce),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.y(y)
);
integer i;
initial begin
// Initialize Inputs
clk = 0;
ce = 1;
//Sta³e wygenerowane w matlabie skryptem gen_tb_data
a = 18'h39ba9;
b = 8'h3b;
c = 12'hd8a;
d = 8'h24;
e = 14'h3380;
f = 19'h10d1f;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for(i = 0; i < 20; i = i + 1)
begin
clk <= 1; #1;
clk <= 0; #1;
end
if(y != 37'h1ffac0469a) $stop;
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long inf = 10000000; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } inline bool isLeapYear(long long year) { return (year % 400 == 0) || (year % 4 == 0 && year % 100 != 0); } inline void normal(long long &a) { a %= MOD; (a < 0) && (a += MOD); } inline long long modMul(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a * b) % MOD; } inline long long modAdd(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); return (a + b) % MOD; } inline long long modSub(long long a, long long b) { a %= MOD, b %= MOD; normal(a), normal(b); a -= b; normal(a); return a; } inline long long modPow(long long b, long long p) { long long r = 1; while (p) { if (p & 1) r = modMul(r, b); b = modMul(b, b); p >>= 1; } return r; } inline long long modInverse(long long a) { return modPow(a, MOD - 2); } inline long long modDiv(long long a, long long b) { return modMul(a, modInverse(b)); } inline bool checkBit(long long n, int i) { return n & (1LL << i); } inline long long setBit(long long n, int i) { return n | (1LL << i); ; } inline long long resetBit(long long n, int i) { return n & (~(1LL << i)); } int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; void input(long long n, const long long a[], int co = 0) { long long i = 1; for (; i <= n; i++) { if (co == 0) scanf( %lld , &a[i]); else printf( %lld , a[i]); } } int n, k; int dp[55][2], a[55], sm; int dfs(int ps, int k) { if (ps == n) return 0; int &rs = dp[ps][k]; if (rs != -1) return rs; rs = 0; if (k == 0) rs = max(a[ps] + dfs(ps + 1, 1), dfs(ps + 1, 0)); else rs = min(a[ps] + dfs(ps + 1, 1), dfs(ps + 1, 0)); return rs; } bool cmp() {} void solve() { memset(dp, -1, sizeof dp); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); sm += a[i]; } int rs = dfs(0, 0); printf( %d %d n , sm - rs, rs); } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int xx[8] = {0, 0, 1, -1, 1, -1, 1, -1}; int yy[8] = {-1, 1, 0, 0, 1, -1, -1, 1}; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; bool flag = true; vector<long long int> v(n); for (long long int i = 0; i < n; i++) cin >> v[i]; long long int pos1 = -1, pos2 = -1; for (long long int i = 0; i < n; i++) { if (v[i] == 1) { pos1 = i; break; } } if (pos1 == -1) { cout << 0 ; return 0; } for (int j = n - 1; j >= 0; j--) { if (v[j] == 1) { pos2 = j; break; } } long long int c = 1, ans = 1; if (pos1 == pos2) { cout << 1 << n ; return 0; } else { for (long long int i = pos1; i < pos2 + 1; i++) { if (v[i] == 0) { c++; } else { ans *= c; c = 1; } } cout << ans << n ; } return 0; }
|
`timescale 1ns / 1ps
module dff_async_rst_tb;
// Inputs
reg clk;
reg rst;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dff_async_rst uut (
.clk(clk),
.rst(rst),
.d(d),
.q(q)
);
task expect;
input exp_out;
if (q !== exp_out) begin
$display("TEST FAILED");
$display("At time %0d rst=%0b, d=%0b, q=%0b",
$time, rst, d, q );
$display("q should be %0b", exp_out );
$finish;
end
else begin
$display("At time %0d rst=%0b, d=%0b, q=%0b",
$time, rst, d, q );
end
endtask
// Clock and async reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold async reset for next 2 cc
repeat(4) #10 clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #10 clk = ~clk;
end
// Stimulus
initial begin
// Initialize Input d to 1 to observe effect of reset
d = 1'b1;
// Observe effect of async reset
@(negedge clk);
expect(1'b0);
// wait for reset to deassert
@(negedge rst);
// as d is still set to 1, we should get q as 1 next
@(negedge clk)
expect(1'b1);
// set d to 0, we should get q as 0 next
d = 1'b0;
@(negedge clk);
expect(1'b0);
$display("TEST PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #include <climits> #define F first #define S second #define all(v) v.begin(),v.end() #define li long int #define lli long long int #define pb push_back #define loop(a,b,i) for(lli i=a ; i<b ; i++) #define rev_loop(a,b,i) for(lli i=a ; i>=b ; i--) #define MAX(a,b) (a>b)?a:b #define lele(arr, n) loop(0,n,i) cin>>arr[i]; #define VAL 10005 #define N 1005 using namespace std; void solve(){ int n; cin>>n; long int arr[2*n], mx=0; loop(0, 2*n, i){ cin>>arr[i]; if(arr[i] > arr[mx]) mx = i; } int i; bool flag; for(i=0 ; i<2*n ; i++){ // O(n) if(i == mx) continue; multiset<int> tmp; loop(0, 2*n, j){ // O(n) if(j == i || j == mx) continue; tmp.insert(arr[j]); } long int lastMx = arr[mx], curMx; flag=true; while(!tmp.empty()){ curMx = *tmp.rbegin(); tmp.erase(tmp.find(curMx)); if(tmp.find(lastMx - curMx) == tmp.end()){ flag = false; break; } tmp.erase(tmp.find(lastMx - curMx)); lastMx = curMx; } if(flag) break; } if(!flag){ cout<< NO n ; return; } cout<< YES n ; cout<<arr[mx] + arr[i]<<endl; cout<<arr[mx]<< <<arr[i]<<endl; multiset<int> tmp; loop(0, 2*n, j){ // O(n) if(j == i || j == mx) continue; tmp.insert(arr[j]); } long int lastMx = arr[mx]; while(!tmp.empty()){ long int x = *tmp.rbegin(), y = *tmp.find(lastMx - x); cout<<x<< <<y<< n ; tmp.erase(tmp.find(x)); tmp.erase(tmp.find(lastMx - x)); lastMx = x; } return; } int main() { int t; cin>>t; while(t--){ solve(); } return 0; }
|
#include <bits/stdc++.h> int main() { int dem = 1, i, n, c; scanf( %d %d , &n, &c); int a[n]; for (i = 0; i < n; i++) { scanf( %d , &a[i]); } for (i = 1; i < n; i++) { if (a[i] - a[i - 1] <= c) { dem++; } if (a[i] - a[i - 1] > c) { dem = 1; } } printf( %d , dem); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 4e5 + 1; int a[MAXN], b[MAXN]; const int MOD = 1e9 + 7; int bit[MAXN]; void add(int pos, int val) { while (pos < MAXN) { (bit[pos] += val) %= MOD; pos += pos & -pos; } } int query(int pos) { int val = 0; while (pos) { val += bit[pos]; val %= MOD; pos -= pos & -pos; } return val; } map<pair<int, int>, int> bad; int mn[MAXN * 2]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d%d , &a[i], &b[i]); } int mx = 0; int t; scanf( %d , &t); int y = 0; memset(mn, -63, sizeof(mn)); for (int Z = 1; Z <= t; ++Z) { int i; scanf( %d , &i); mn[b[i]] = a[i]; bad[make_pair(a[i], b[i])] = 1; mx = max(mx, b[i]); if (b[i] == mx) y = a[i]; } for (int i = n + n; i >= 1; --i) mn[i] = max(mn[i], mn[i + 1]); vector<pair<int, int> > r; for (int i = 1; i <= n; ++i) { if (b[i] <= mx) { r.push_back(make_pair(a[i], b[i])); } } sort(r.begin(), r.end()); int ans = 0; int cnt = 0; int tot = 0; for (auto it : r) { int val = 1; val += tot; val %= MOD; val -= query(it.second); val += MOD; val %= MOD; if (mn[it.second] < it.first && !bad[it]) (val += MOD - 1) %= MOD; (tot += val) %= MOD; (ans += val) %= MOD; ans %= MOD; add(it.second, val); cnt++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 10; const int mod = 1e9 + 7; int n, k, a[maxn], f[maxn], g[maxn]; int fast_pow(int a, int b) { int ret = 1; for (; b; b >>= 1, a = 1ll * a * a % mod) if (b & 1) ret = 1ll * ret * a % mod; return ret; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= min(k + 2, n); i++) a[i] = (a[i - 1] + fast_pow(i, k)) % mod; if (n <= k + 2) { printf( %d n , a[n]); return 0; } int now, ans = 0; now = f[0] = g[0] = 1; for (int i = 1; i <= k + 2; i++) { now = 1ll * now * (n - i) % mod; f[i] = 1ll * f[i - 1] * i % mod; g[i] = 1ll * -g[i - 1] * i % mod; } for (int i = 1; i <= k + 2; i++) ans = (ans + 1ll * a[i] * now % mod * fast_pow(n - i, mod - 2) % mod * fast_pow(1ll * f[i - 1] * g[k + 2 - i] % mod, mod - 2) % mod) % mod; ans = (ans + mod) % mod; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(0); int cases, caseno = 0, n, i, j, k, cnt, sum; cin >> n >> j >> k; for (i = 1; i <= 10000; i++) { if (n == 2) { cout << Final! ; return 0; } if ((j + 1) / 2 == (k + 1) / 2) { cout << i; return 0; } j = (j + 1) / 2; k = (k + 1) / 2; n /= 2; } return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ()
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 2. Squate waves with variable timmer, configurable frequency and envelope functions.
////////////////////////////////////////////////////////////////////////////////////
module SoundCtrlMX //parameters
(
input wire iClock, //CPU CLOCK, 4194304Hz
input wire iReset,
input wire iOsc262k, //OSC2 clock 131072Hz
input wire [4:0] iOut1, // Channel 1.
input wire [4:0] iOut2, // Channel 2.
input wire [4:0] iOut3, // Channel 3.
input wire [4:0] iOut4, // Channel 4.
input wire [7:0] iNR50, // Left/Right enable + Left/Right volume.
input wire [7:0] iNR51, // Enable channel 1/2/3/4 in Left/Right.
output reg [4:0] oSO1, // Left channel.
output reg [4:0] oSO2, // Right channel.
output wire [1:0] oChSel,
output wire oChClk
);
reg [7:0] rNR50, rNR51;
reg [4:0] rSO1_PRE, rSO2_PRE;
reg rSer_clk; // 8kHz clock, used for serializer.
reg [1:0] rSer_sel; // Indicates which channel data were sent.
//Registers load
always @ (posedge iClock) begin
if (iReset) begin
rNR50 <= iNR50;
rNR51 <= iNR51;
rSer_sel <= 2'b0;
rSer_clk <= 1'b0;
rSO1_PRE <= 5'd15;
rSO2_PRE <= 5'd15;
end
end
//Serializer
always @ (posedge iOsc262k) begin
rSer_clk <= ~rSer_clk;
rSer_sel <= (~rSer_clk) ? rSer_sel + 1 : rSer_sel;
end
//Volume control
always @ (*) begin
case (rSer_sel)
2'd0: begin
rSO1_PRE = (rNR51[0]) ? iOut1 : 5'd15;
rSO2_PRE = (rNR51[4]) ? iOut1 : 5'd15;
end
2'd1: begin
rSO1_PRE = (rNR51[1]) ? iOut2 : 5'd15;
rSO2_PRE = (rNR51[5]) ? iOut2 : 5'd15;
end
2'd2: begin
rSO1_PRE = (rNR51[2]) ? iOut3 : 5'd15;
rSO2_PRE = (rNR51[6]) ? iOut3 : 5'd15;
end
2'd3: begin
rSO1_PRE = (rNR51[3]) ? iOut4 : 5'd15;
rSO2_PRE = (rNR51[7]) ? iOut4 : 5'd15;
end
default: begin
rSO1_PRE = 5'dX;
rSO2_PRE = 5'dX;
end
endcase
oSO1 = rSO1_PRE >> (3'd7-rNR50[2:0]);
oSO2 = rSO1_PRE >> (3'd7-rNR50[6:4]);
end
assign oChSel = rSer_sel;
assign oChClk = rSer_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long N = 1e5 + 1; const long long INF = -1e17; long long n; long long ans, cnt, mx = 0; string s; int main() { ios_base::sync_with_stdio(false); cin >> n; getline(cin, s); getline(cin, s); for (long long i = 0; i < s.size(); i++) { if (s[i] > 64 and s[i] < 95) { ans++; mx = max(ans, mx); } else if (s[i] == ) { mx = max(ans, mx); ans = 0; } } cout << mx; }
|
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Palette Control
// File : pal_ctl.v
// Author : Jim MacLeod
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
//
// This manages the processor read and write modes to the palette.
// it uses the processor wr / rd clocks for processor
// commands and the passes the data to the pix clk domain
// to performs the actual sequencing of data to the palette.
//
// for proc. read from palette, the read address is always on by default
// That is: OE for this read port is always on
//
// for proc write to palettes, addr / data are
// setup 1 cycle before the write pulse
// the address is held one cycle after the write pulse.
//
/////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module pal_ctl
(
hclk,
hresetn,
wrn,
rdn,
wr_mode,
rd_mode,
colres,
pal_data1,
pal_data2,
pal_data3, // cpu data pre filtered
red2pal,
grn2pal,
blu2pal, // final data to pal
palred,
palgrn,
palblu , // raw data from pal
cp_addr,
paladr,
palwr,
pal2cpu,
pal_wradr
);
input hclk,
hresetn,
wrn,
rdn,
wr_mode,
rd_mode,
colres;
input [7:0] pal_data1, // Data from host to pal.
pal_data2,
pal_data3,
pal_wradr;
input [7:0] palred, // Data read from pal RAM.
palgrn,
palblu;
input [2:0] cp_addr; // Read/ Write Address from host.
output [7:0] paladr; //
output palwr ;
output [7:0] red2pal, // to be written to pal.
grn2pal,
blu2pal ;
output [7:0] pal2cpu;
parameter PAL_WADR = 3'h0, // Palette Write Address register.
PAL_RADR = 3'h3; // Palette Read Address register.
reg [7:0] pal2cpu;
reg [7:0] red2pal, grn2pal, blu2pal ;
reg palwr ;
reg [7:0] paladr ;
reg wr1, wr2;
reg rd1, rd2;
reg wr_enable, rd_enable, inc_adr;
//---------- sync the processor interface to the palette clock
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn)
begin
wr2 <= 1'b0;
wr1 <= 1'b0;
rd2 <= 1'b0;
rd1 <= 1'b0;
end
else begin
wr2 <= wr1;
wr1 <= wrn;
rd2 <= rd1;
rd1 <= rdn;
end
end
wire wr_pulse = wr1 & !wr2;
wire rd_pulse = rd1 & !rd2;
wire init_rd = wr_pulse & (cp_addr == PAL_RADR);
wire init_wr = wr_pulse & (cp_addr == PAL_WADR);
wire init_ptr = init_wr | init_rd;
wire pal_access = wr_enable | rd_enable;
reg [2:0] byte_ptr;
//--------wr pointer update-------------//
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn) byte_ptr <= 3'b100;
else if (init_ptr) byte_ptr[2:0] <= 3'b100 ;
else if (pal_access) byte_ptr[2:0] <= {byte_ptr[0],byte_ptr[2:1]};
end
//---------------------------------------------------//
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn)
begin
wr_enable <= 1'b0;
red2pal <= 8'h00;
blu2pal <= 8'h00;
grn2pal <= 8'h00;
end
else if (wr_pulse & wr_mode & (cp_addr == 3'h1))
begin
red2pal <= colres ? pal_data3[7:0] : {pal_data3[5:0] , 2'b00};
grn2pal <= colres ? pal_data2[7:0] : {pal_data2[5:0] , 2'b00};
blu2pal <= colres ? pal_data1[7:0] : {pal_data1[5:0] , 2'b00};
wr_enable <= 1'b1;
end
else wr_enable <= 1'b0;
end
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn)
begin
rd_enable <= 1'b0;
pal2cpu <= 8'h00;
end
else begin
case (byte_ptr)
3'b100 : pal2cpu <= colres ? palred[7:0] : {2'b00 , palred[7:2]};
3'b010 : pal2cpu <= colres ? palgrn[7:0] : {2'b00 , palgrn[7:2]};
default : pal2cpu <= colres ? palblu[7:0] : {2'b00 , palblu[7:2]};
endcase
if (rd_pulse & rd_mode & (cp_addr == 3'h1))
rd_enable <= 1'b1;
else rd_enable <= 1'b0;
end
end
//-------------------------------------------------------------
//--------generate pal rd / wr_pulse---& auto inc controls-----------
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn)
begin
palwr <= 1'b0;
inc_adr <= 1'b0;
end
else begin
if ((wr_enable) & (byte_ptr == 3'b001)) palwr <= 1'b1;
else palwr <= 1'b0;
if ((rd_enable | wr_enable) & (byte_ptr == 3'b001))inc_adr<= 1'b1;
else inc_adr<= 1'b0;
end end
//--------auto increment the palette address------------
always @(posedge hclk or negedge hresetn)
begin
if (!hresetn) paladr <= 8'b0;
else if (init_wr) paladr <= pal_wradr;
else if (init_rd) paladr <= pal_wradr;
else if (inc_adr) paladr <= paladr + 8'b1;
end
//---------------------------------------------------//
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file read operands mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Mux for two register file read operands. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_operandmuxes.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_operandmuxes(
// Clock and reset
clk, rst,
// Internal i/f
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze;
input [width-1:0] rf_dataa;
input [width-1:0] rf_datab;
input [width-1:0] ex_forw;
input [width-1:0] wb_forw;
input [width-1:0] simm;
input [`OR1200_SEL_WIDTH-1:0] sel_a;
input [`OR1200_SEL_WIDTH-1:0] sel_b;
output [width-1:0] operand_a;
output [width-1:0] operand_b;
output [width-1:0] muxed_a;
output [width-1:0] muxed_b;
//
// Internal wires and regs
//
reg [width-1:0] operand_a;
reg [width-1:0] operand_b;
reg [width-1:0] muxed_a;
reg [width-1:0] muxed_b;
reg saved_a;
reg saved_b;
//
// Operand A register
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
operand_a <= 32'd0;
saved_a <= 1'b0;
end else if (!ex_freeze && id_freeze && !saved_a) begin
operand_a <= muxed_a;
saved_a <= 1'b1;
end else if (!ex_freeze && !saved_a) begin
operand_a <= muxed_a;
end else if (!ex_freeze && !id_freeze)
saved_a <= 1'b0;
end
//
// Operand B register
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
operand_b <= 32'd0;
saved_b <= 1'b0;
end else if (!ex_freeze && id_freeze && !saved_b) begin
operand_b <= muxed_b;
saved_b <= 1'b1;
end else if (!ex_freeze && !saved_b) begin
operand_b <= muxed_b;
end else if (!ex_freeze && !id_freeze)
saved_b <= 1'b0;
end
//
// Forwarding logic for operand A register
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casez (sel_a) // synopsys parallel_case infer_mux
`else
casez (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_a = wb_forw;
default:
muxed_a = rf_dataa;
endcase
end
//
// Forwarding logic for operand B register
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casez (sel_b) // synopsys parallel_case infer_mux
`else
casez (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
`OR1200_SEL_EX_FORW:
muxed_b = ex_forw;
`OR1200_SEL_WB_FORW:
muxed_b = wb_forw;
default:
muxed_b = rf_datab;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { long long int n, i, j, k, t; scanf( %lld , &n); long long int prev = 0, ans = 0, count = 0, diff = 0, sum = 0, powe = 0; long long int a[n]; for (i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); if (n == 1) { cout << 0 << endl; return 0; } prev = a[1] - a[0]; ans = prev; count = 2; for (i = 2; i < n; i++) { count = (count * 2) % 1000000007; powe = (count - 1) % 1000000007; diff = (a[i] - a[i - 1]) % 1000000007; sum = ((2 * prev) % 1000000007 + (diff * powe) % 1000000007) % 1000000007; ans = ((ans) % 1000000007 + (sum) % 1000000007) % 1000000007; prev = sum % 1000000007; } cout << ans % 1000000007 << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_SYMBOL_V
`define SKY130_FD_SC_HVL__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_2_V
`define SKY130_FD_SC_HS__A21O_2_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a21o_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int k, w; long long n; cin >> k >> n >> w; int l{}; for (int i = 1; i <= w; i++) { l = l + i; } int s = (l * k) - n; if (s > 0) cout << s; else cout << 0; return 0; }
|
`timescale 1 ps / 1 ps
module mult_add_fix8bx4 (
input clock,
input resetn,
input ivalid,
input iready,
output ovalid,
output oready,
input wire [7:0] dataa_0, // dataa_0.dataa_0
input wire [7:0] datab_0, // datab_0.datab_0
input wire [7:0] dataa_1, // dataa_1.dataa_1
input wire [7:0] datab_1, // datab_1.datab_1
input wire [7:0] dataa_2, // dataa_2.dataa_2
input wire [7:0] datab_2, // datab_2.datab_2
input wire [7:0] dataa_3, // dataa_3.dataa_3
input wire [7:0] datab_3, // datab_3.datab_3
output wire [31:0] result // result.result
);
wire [17:0] result_18b;
assign ovalid = 1'b1;
assign oready = 1'b1;
// ivalid, iready, resetn are ignored
assign result = {{14{result_18b[17]}}, result_18b};
//assign result = {14'd0, result_18b};
mult_add_fix8bx4_0002 mult_add_fix8bx4_inst (
.result (result_18b), // result.result
.dataa_0 (dataa_0), // dataa_0.dataa_0
.dataa_1 (dataa_1), // dataa_1.dataa_1
.dataa_2 (dataa_2), // dataa_2.dataa_2
.dataa_3 (dataa_3), // dataa_3.dataa_3
.datab_0 (datab_0), // datab_0.datab_0
.datab_1 (datab_1), // datab_1.datab_1
.datab_2 (datab_2), // datab_2.datab_2
.datab_3 (datab_3), // datab_3.datab_3
.clock0 (clock) // clock0.clock0
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; int32_t main() { cin >> n >> k; if ((n / k) & 1) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int tux; cin >> tux; int foo, bar, baz, quz, pur, oo; foo = bar = baz = 0; quz = 1; while (tux) { cin >> pur; foo += pur; bar++; if (foo * quz > bar * baz) { baz = foo; quz = bar; } tux--; } cout.precision(5); cout << fixed << (baz * 1. / quz); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a; cin >> a; if (a % 2 == 0) { cout << NO ; return 0; } if ((a - 3) / 2 < 1) { cout << NO ; return 0; } cout << 1 << << (a - 3) / 2; }
|
#include <bits/stdc++.h> using namespace std; int n, k, a, ans; set<pair<int, int> > s; int x, m; bool used[1000000]; int solve(int x) { return (x + 1) / (a + 1); } void go(int x) { set<pair<int, int> >::iterator it = s.upper_bound(make_pair(x, 1000000000)); --it; pair<int, int> cur = *it; s.erase(it); ans -= solve(cur.second - cur.first + 1); if (x != cur.first) { ans += solve(x - cur.first); s.insert(make_pair(cur.first, x - 1)); } if (x != cur.second) { ans += solve(cur.second - x); s.insert(make_pair(x + 1, cur.second)); } } int main() { cin >> n >> k >> a; s.insert(make_pair(1, n)); ans = solve(n); cin >> m; for (int i = 1; i <= m; i++) { cin >> x; if (used[x]) continue; used[x] = 1; go(x); if (ans < k) { cout << i; return 0; } } cout << -1; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:56:01 10/14/2015
// Design Name: gray_couter
// Module Name: C:/Users/djnakka/Downloads/hw1/gray_counter/gray_counter_tb.v
// Project Name: gray_counter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: gray_couter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module gray_counter_tb;
// Inputs
reg rst;
reg clk;
// Outputs
wire [3:0] grayout;
// Instantiate the Unit Under Test (UUT)
gray_couter uut (
.rst(rst),
.clk(clk),
.grayout(grayout)
);
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
forever #1 clk = ~clk;
end
initial begin
// Initialize Inputs
rst = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
#20
rst = 1;
#2
rst = 0;
end
endmodule
|
module display_logic( input pxl_clk,
input [9:0] hcount,
input [9:0] vcount,
input [9:0] ball_y,
input [9:0] ball_x,
input [5:0] player_position,
input [3:0] block_num,
input vsync,
input lose,
input win,
output reg drawing_player,
output reg drawing_block,
output reg [2:0] rgb );
`include "defines.v"
reg [2:0] flash;
reg [3:0] flash_time;
reg flash_hold;
always @ (hcount, vcount, ball_y, ball_x, player_position, block_num, lose, win, flash)
begin : display_decoder
drawing_player = 0;
drawing_block = 0;
if (hcount > `screen_right || vcount > `screen_bottom) rgb <= 3'b000;
else if (win) rgb <= flash;
else if (lose) rgb <= `red;
else if (vcount < `bottom_edge && hcount < `left_edge) rgb <= `green;
else if (vcount < `bottom_edge && hcount > `right_edge) rgb <= `green;
else if (vcount < `top_edge ) rgb <= `green;
else if (vcount > `bottom_edge) rgb <= `red;
else if (vcount < ball_y + 3 && vcount > ball_y - 3 &&
hcount < ball_x + 3 && hcount > ball_x - 3) rgb <= `white;
else if ( vcount > `player_vstart && vcount < (`player_vstart + `player_width ) &&
hcount > (player_position << 5) - `player_hlength + `left_edge &&
hcount < ((player_position << 5) + `player_hlength + `left_edge) )
begin
rgb <= `white;
drawing_player <= 1;
end
else if (vcount > `blocks_vstart && vcount <= `blocks_vend && hcount > `blocks_hstart && hcount <= `blocks_hend && |block_num)
begin
drawing_block <= 1;
if ( |block_num[2:0] ) rgb <= block_num[2:0];
else rgb <= block_num[2:0] + 3;
// rgb <= ~|block_num[3:0] ? block_num[2:0] : block_num[2:0] + 3'd3;
end
else rgb <= `black;
end
always @ (posedge pxl_clk)
begin
if (!vsync)
begin
if (!flash_hold) flash_time <= flash_time + 1;
flash_hold <= 1;
end
else
begin
flash_hold <= 0;
end
if (flash_time == 0)
begin
flash <= `black;
end
else if (flash_time == 3)
begin
if (win) flash <= `white;
else if (lose) flash <= `red;
end
else if (flash_time >= 6)
begin
flash_time <= 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXBP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_0_V
`define SKY130_FD_SC_LP__XOR2_0_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_BLACKBOX_V
`define SKY130_FD_SC_MS__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, a, b, c, d, s = 0, i; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> a >> b >> c >> d; s = s + (c - a + 1) * (d - b + 1); } cout << s; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 31867 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w124,
w123,
w31744,
w31867;
assign w1 = i_data0;
assign w123 = w124 - w1;
assign w124 = w31 << 2;
assign w31 = w32 - w1;
assign w31744 = w31 << 10;
assign w31867 = w123 + w31744;
assign w32 = w1 << 5;
assign o_data0 = w31867;
//multiplier_block area estimate = 5624.94231249706;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`include "defines.v"
`include "HRnode.v"
`timescale 1ns/1ps
/*module HRnode
#(parameter addr = 4'b0010)
(
input `control_w port0_i,
input `control_w port1_i,
input `control_w port0_local_i,
input `control_w port1_local_i,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_o,
output `control_w port1_o,
output `control_w port0_local_o,
output `control_w port1_local_o
);*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
HRnode r(
.clk(clk),
.rst(rst),
.port0_i(flit0c), .port0_o(port0_co),
.port1_i(flit1c), .port1_o(port1_co),
.port0_local_i(flitl0), .port0_local_o(portl0_co),
.port1_local_i(flitl1), .port1_local_o(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1851;
flit1c = 144'h0123456789abcdef0123456789abcdef1852;
flitl1 = 144'h0123456789abcdef0123456789abcdef1855;
flitl0 = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double Pi = acos((double)-1); const double Eps = 1E-6; int read() { int $x; scanf( %d , &$x); return $x; } long long sqr(long long $x) { return $x * $x; } int x[100000], N, A, B; int main() { A = read(), B = read(); N = A + B + 1; x[0] = 1; int i = 0, t; t = 1; while (A--) x[++i] = ++t; t = 1; while (B--) x[++i] = --t; for (i = 0; i < N; ++i) printf( %d , x[i] - t + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool cur1; int n, m, K; int L[100005 * 120], R[100005 * 120], res[100005 * 120], tt, rt[100005 * 3]; int update(int p, int l, int r, int x, int v) { int c = ++tt; L[c] = L[p], R[c] = R[p]; if (l == r) { res[c] = min((p ? res[p] : 0x3f3f3f3f), v); return c; } int mid = (l + r) >> 1; if (x <= mid) L[c] = update(L[p], l, mid, x, v); else R[c] = update(R[p], mid + 1, r, x, v); res[c] = max(res[L[c]], res[R[c]]); return c; } int query(int p, int u, int v, int l, int r) { if (u <= l && r <= v) { return res[p]; } int mid = (l + r) >> 1; int ans = 0; if (u <= mid) ans = max(ans, query(L[p], u, v, l, mid)); if (v > mid) ans = max(ans, query(R[p], u, v, mid + 1, r)); return ans; } struct seg { int a, b, c; bool operator<(const seg &_) const { if (a != _.a) return a < _.a; if (c != _.c) return c < _.c; if (b != _.b) return b > _.b; } } Sg[100005 * 3]; int B[100005 * 3]; void solve() { tt = 0; int tot = 0; scanf( %d %d %d , &n, &m, &K); for (int a, b, c, i = 1; i <= K; i++) { scanf( %d %d %d , &a, &b, &c); B[i] = a; Sg[i] = (seg){a, b, c}; } sort(B + 1, B + K + 1); sort(Sg + 1, Sg + K + 1); tot = unique(B + 1, B + 1 + K) - B - 1; for (int i = 1; i <= n; i++) rt[tot + 1] = update(rt[tot + 1], 1, n, i, 0x3f3f3f3f); Sg[K + 1].a = 0x3f3f3f3f; for (int i = K; i >= 1; i--) { int t = lower_bound(B + 1, B + 1 + tot, Sg[i].a) - B; if (Sg[i].a != Sg[i + 1].a) { rt[t] = update(rt[t + 1], 1, n, Sg[i].c, Sg[i].b); } else rt[t] = update(rt[t], 1, n, Sg[i].c, Sg[i].b); } while (m--) { int a, b, c, d; scanf( %d %d %d %d , &a, &b, &c, &d); if (c > B[tot]) { puts( no ); fflush(stdout); continue; } else { int t = lower_bound(B + 1, B + 1 + tot, c) - B; if (query(rt[t], a, b, 1, n) <= d) puts( yes ); else puts( no ); } fflush(stdout); } } bool cur2; int main() { solve(); return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Priority Encoder Sub-Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/08/07 08:00:43 rudi
//
//
// Split up priority encoder modules to separate files
//
//
//
//
//
//
`include "wb_dma_defines.v"
// Priority Encoder
//
// Determines the channel with the highest priority, also takes
// the valid bit in consideration
module wb_dma_pri_enc_sub(valid, pri_in, pri_out);
parameter [3:0] ch_conf = 4'b0000;
parameter [1:0] pri_sel = 2'd0;
input valid;
input [2:0] pri_in;
output [7:0] pri_out;
wire [7:0] pri_out;
reg [7:0] pri_out_d;
reg [7:0] pri_out_d0;
reg [7:0] pri_out_d1;
reg [7:0] pri_out_d2;
assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;
// Select Configured Priority
always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2)
case(pri_sel) // synopsys parallel_case full_case
2'd0: pri_out_d = pri_out_d0;
2'd1: pri_out_d = pri_out_d1;
2'd2: pri_out_d = pri_out_d2;
endcase
// 8 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100;
else
if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000;
else
if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000;
else
if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000;
else
if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000;
else pri_out_d2 = 8'b1000_0000;
// 4 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100;
else pri_out_d1 = 8'b0000_1000;
// 2 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d0 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001;
else pri_out_d0 = 8'b0000_0010;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_TB_V
`define SKY130_FD_SC_LS__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_TB_V
|
#include <bits/stdc++.h> using namespace std; int const oo = 1e9, bound = 1e6, mod = oo + 7; long long const OO = 1e18; int n, m, k, aa[20]; int cc[20][20]; long long dp[18][1 << 18]; long long rec(int idx, int msk) { long long &ret = dp[idx][msk]; if (ret != -1) return ret; int cop = msk, e = 0; while (cop) { if (cop & 1) e++; cop >>= 1; } if (e == m) return ret = 0; for (int(i) = 0; (i) < (n); (i)++) { if (!((msk >> i) & 1)) ret = max(ret, rec(i, (1 << i) | msk) + aa[i] + (msk != 0 ? cc[idx][i] : 0)); } return ret; } int main() { memset(dp, -1, sizeof dp); scanf( %d , &n), scanf( %d , &m), scanf( %d , &k); for (int(i) = 0; (i) < (n); (i)++) scanf( %d , &aa[i]); for (int(i) = 0; (i) < (k); (i)++) { int a, b, c; scanf( %d , &a), scanf( %d , &b), scanf( %d , &c); a--, b--; cc[a][b] = c; } long long mx = rec(0, 0); printf( %lld n , mx); return 0; }
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Mon Nov 03 20:58:05 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/lp_FIR_stub.v
// Design : lp_FIR
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.2" *)
module lp_FIR(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[23:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [23:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [23:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[100]; bool cmp(int a, int b) { return a > b; } int highest(int n) { int i = 1, fact = 0; while (2 * i <= n) { i *= 2; fact++; } return fact; } void permute(int left, int right, int pos, int last) { if (!pos || (!last && pos == 1)) return; int t = highest(pos); pos -= (1 << t); if (!last) { left = right - t - 1; swap(v[left + 1], v[right]); sort(v + left + 2, v + right, cmp); permute(left, right, pos, t); return; } swap(v[left], v[right]); --right; if (last - t != 1) { ++left; sort(v + left, v + right + 1); permute(left, right, pos + (1 << t), 0); return; } permute(left, right, pos, t); } int main() { int n, m, num = 1, piv = 0, pos, t; cin >> n >> m; for (int i = 0; i < n; ++i) v[i] = i + 1; permute(0, n - 1, m, 0); for (int i = 0; i < n; ++i) cout << v[i] << ; return 0; }
|
//==================================================================================================
// Filename : uart_min.v
// Created On : 2015-01-10 15:58:09
// Last Modified : 2015-05-24 21:21:39
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : UART module. Configuration: 115200, 8N1. No flow control
// Minimal version (no slave port)
// Based on the Rx module from XUM project.
// Author: Grant Ayers ()
//==================================================================================================
module uart_min #(
parameter FIFO_ADDR_WIDTH = 8, // 2^ADDR_WIDTH words of FIFO space
parameter BUS_FREQ = 100.0 // Bus frequency
)(
input clk,
input rst,
input write, // Write data to fifo (Tx)
input [7:0] data_i, // Input data
input read, // Read data from fifo (Rx)
output [7:0] data_o, // Output data
output data_ready, // Data available to read
output [FIFO_ADDR_WIDTH:0] rx_count, // Number of bytes inside the Rx fifo
output [FIFO_ADDR_WIDTH:0] tx_count, // Number of bytes inside the Tx fifo
output tx_free, // indicate tx ready
// Interrupt: Data available in Rx fifo, or fifo full
output uart_rx_ready_int, //
output uart_rx_full_int, //
// Off chip I/O
input uart_rx, // Rx pin
output uart_tx // Tx pin
);
//--------------------------------------------------------------------------
// Rx/Tx "clocks"
//--------------------------------------------------------------------------
wire uart_tick;
wire uart_tick_16x;
//--------------------------------------------------------------------------
// Rx signals
//--------------------------------------------------------------------------
wire [7:0] rx_data; // Raw bytes coming in from uart
wire rx_data_ready; // Synchronous pulse indicating data from Rx
wire rx_fifo_empty;
//--------------------------------------------------------------------------
// Tx signals
//--------------------------------------------------------------------------
reg tx_fifo_deQ = 0;
reg tx_start = 0;
wire tx_fifo_empty;
wire [7:0] tx_fifo_data_out;
//--------------------------------------------------------------------------
// Handle Tx FIFO
//--------------------------------------------------------------------------
assign uart_rx_ready_int = ~rx_fifo_empty;
assign data_ready = ~rx_fifo_empty;
always @(posedge clk) begin
if (rst) begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
else begin
if (~tx_fifo_empty & tx_free & uart_tick) begin
tx_fifo_deQ <= 1;
tx_start <= 1;
end
else begin
tx_fifo_deQ <= 0;
tx_start <= 0;
end
end
end
//--------------------------------------------------------------------------
// Instantiate modules
//--------------------------------------------------------------------------
uart_clock #(
.BUS_FREQ (BUS_FREQ))
clks (
.clk ( clk ),
.uart_tick ( uart_tick ),
.uart_tick_16x ( uart_tick_16x )
);
uart_tx tx (
.clk ( clk ),
.rst ( rst ),
.uart_tick ( uart_tick ),
.TxD_data ( tx_fifo_data_out ),
.TxD_start ( tx_start ),
.ready ( tx_free ),
.TxD ( uart_tx )
);
uart_rx rx (
.clk ( clk ),
.rst ( rst ),
.RxD ( uart_rx ),
.uart_tick_16x ( uart_tick_16x ),
.RxD_data ( rx_data ),
.ready ( rx_data_ready )
);
fifo #(
.DATA_WIDTH (8),
.ADDR_WIDTH (FIFO_ADDR_WIDTH))
tx_buffer (
.clk ( clk ),
.rst ( rst ),
.enqueue ( write ),
.dequeue ( tx_fifo_deQ ),
.data_i ( data_i ),
.data_o ( tx_fifo_data_out ),
.count ( tx_count ),
.empty ( tx_fifo_empty ),
.full ( )
);
fifo #(
.DATA_WIDTH (8),
.ADDR_WIDTH (FIFO_ADDR_WIDTH))
rx_buffer (
.clk ( clk ),
.rst ( rst ),
.enqueue ( rx_data_ready ),
.dequeue ( read ),
.data_i ( rx_data ),
.data_o ( data_o ),
.count ( rx_count ),
.empty ( rx_fifo_empty ),
.full ( uart_rx_full_int )
);
endmodule
|
`define PERIOD 10
module main;
reg CLK;
integer counter;
initial begin // reset and clock generator
counter = 0;
CLK = 0;
#2; // wait 2, and then...
repeat(10) // generate 5 clock cycles
#(`PERIOD/2) CLK = !CLK;
$display("time %0t; the counter is %0d", $time, counter);
$finish(0);
end
task test1;
begin
@(posedge CLK);
$display("test1 increment; reading counter as %0d", counter);
// the function call is necessary to get the problem
counter = _$Fadd32(counter, 1'b1);
end
endtask
task test2;
begin
@(posedge CLK);
$display("test2 increment; reading counter as %0d", counter);
counter = _$Fadd32(counter, 1'b1);
end
endtask
function [31:0] _$Fadd32;
input l,r;
reg [31:0] l,r;
_$Fadd32 = l+r;
endfunction
endmodule // main
module trig1;
always begin
#`PERIOD;
top.main.test1;
end
endmodule
module trig2;
always begin
#`PERIOD;
top.main.test2;
end
endmodule
module top;
main main();
trig1 trig1();
trig2 trig2();
endmodule
|
// Copyright (c) 2012, 2013 Rich Porter - see LICENSE for further details
`include "example.h"
module sim_ctrl (
output reg sim_ctrl_clk_op `EXM_VLTOR_PUBLIC_RW,
output sim_ctrl_rst_op `EXM_VLTOR_PUBLIC_RW
); // sim_ctrl
`ifdef EXM_USE_DPI
import "DPI-C" context task sim_ctrl_scope_t ();
`ifdef verilator
export "DPI-C" task sim_ctrl_sig_t;
`endif
`endif
/*
* Clock generation
*
* Does need to be done differently across platforms
*
* Needs some thought when verilated code runs in lock step to event
* driven RTL.
*
*/
task sim_ctrl_sig_t;
sim_ctrl_clk_op
`ifdef verilator
=
`else
<=
`endif
~sim_ctrl_clk_op;
endtask : sim_ctrl_sig_t
initial
begin
sim_ctrl_clk_op = `false;
`ifdef verilator
// driven externally via sim_ctrl_sig_t task
sim_ctrl_scope_t; // register this scope
`else
// event driven simulations
forever #1 sim_ctrl_sig_t;
`endif
end
/*
* Generate reset
*/
integer sim_ctrl_cycles_i `EXM_VLTOR_PUBLIC_RD;
integer sim_ctrl_cycles_freq_i `EXM_VLTOR_PUBLIC_RW;
integer sim_ctrl_rst_i `EXM_VLTOR_PUBLIC_RW;
integer sim_ctrl_timeout_i `EXM_VLTOR_PUBLIC_RW;
reg sim_ctrl_finish_r `EXM_VLTOR_PUBLIC_RW;
always @(posedge sim_ctrl_clk_op)
begin
sim_ctrl_cycles_i <= sim_ctrl_cycles_i + 1;
if (sim_ctrl_cycles_i % sim_ctrl_cycles_freq_i == 0)
`EXM_INFORMATION("%10d cycles", sim_ctrl_cycles_i);
if (sim_ctrl_cycles_i > sim_ctrl_timeout_i)
sim_ctrl_finish_r <= `true;
end
initial sim_ctrl_rst_i = 5;
assign sim_ctrl_rst_op = sim_ctrl_cycles_i < sim_ctrl_rst_i;
/*
* Timeout for end of simulation
*/
initial sim_ctrl_timeout_i = 10;
always @(sim_ctrl_timeout_i)
`EXM_INFORMATION("%m : timeout set to %d", sim_ctrl_timeout_i);
initial sim_ctrl_cycles_i = 0;
initial sim_ctrl_cycles_freq_i = 1000;
/*
* End of simulation
*/
initial sim_ctrl_finish_r = `false;
always @(posedge sim_ctrl_finish_r)
begin
`EXM_INFORMATION("End of simulation at %d", sim_ctrl_cycles_i);
$finish;
end
/*
* invoke python shell
*/
initial `EXM_PYTHON();
/*
* waveform trace for non verilator
*/
initial
begin : sim_ctrl_vcd_l
integer sim_ctrl_vcd_depth_r = 0;
reg [`std_char_sz_c*128-1:0] sim_ctrl_vcd_filename_r;
reg sim_ctrl_vcd_r;
sim_ctrl_vcd_r = `EXM_WAVES(sim_ctrl_vcd_filename_r, sim_ctrl_vcd_depth_r);
if (sim_ctrl_vcd_r)
begin
`ifndef verilator
$dumpfile(sim_ctrl_vcd_filename_r);
$dumpvars(sim_ctrl_vcd_depth_r);
`EXM_INFORMATION("Enabling waves depth %d, dumping to file %s", sim_ctrl_vcd_depth_r, sim_ctrl_vcd_filename_r);
`endif
end
end
endmodule : sim_ctrl
module arr (
input clk
); // arr
parameter LENGTH = 1;
reg [LENGTH-1:0] sig0 `EXM_VLTOR_PUBLIC_RW;
reg [LENGTH-1:0] sig1 `EXM_VLTOR_PUBLIC_RW;
reg verbose `EXM_VLTOR_PUBLIC_RW;
always @(posedge clk)
begin
if (sig0 != sig1) `EXM_ERROR("%m : %x != %x", sig0, sig1);
else if (verbose) `EXM_INFORMATION("%m : %x == %x", sig0, sig1);
end
endmodule : arr
module duv (
input duv_clk_ip,
input duv_rst_ip
); // duv
parameter instances = 255;
genvar i;
generate
for (i=1; i<=255; i=i+1) begin : arr
arr #(.LENGTH(i)) arr(.clk(duv_clk_ip));
end
endgenerate
reg single_bit `EXM_VLTOR_PUBLIC_RW;
reg [31:0] mem [0:1023] `EXM_VLTOR_PUBLIC_RW;
reg [31:0] mem_array [0:15] [0:3] [0:3] `EXM_VLTOR_PUBLIC_RW;
`ifdef IVERILOG
// seems icarus optimizes the signals away if they're not used
wire dummy = single_bit || mem[0][0] || mem_array[0][0][0][0];
`endif
reg test_message `EXM_VLTOR_PUBLIC_RW = 0;
always @(posedge duv_clk_ip)
if (test_message)
begin
`EXM_NOTE("test_message %d", test_message);
`EXM_NOTE("octal %08o", 255);
`EXM_NOTE("hex %012x %h", 32'hee_55_aa_ff, 32'hff_aa_55_ee);
`EXM_NOTE("float %f", 6.9);
`EXM_NOTE("float %2.3f : %m, %1.2e", 6.9, 2.099);
`EXM_NOTE("%b %m %h %m %%many", 64, 16'haa);
test_message = 0;
end
endmodule : duv
module duv_grey_box (
input duv_clk_ip,
input duv_rst_ip
); // duv_grey_box
endmodule : duv_grey_box
module example;
wire
example_clk_w,
example_rst_w;
sim_ctrl simctrl_0_u (
.sim_ctrl_clk_op(example_clk_w),
.sim_ctrl_rst_op(example_rst_w)
);
duv duv_0_u (
.duv_clk_ip(example_clk_w),
.duv_rst_ip(example_rst_w)
);
duv_grey_box duv_grey_box_0_u (
.duv_clk_ip(duv_0_u.duv_clk_ip),
.duv_rst_ip(duv_0_u.duv_clk_ip)
);
endmodule : example
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbn (
VPWR ,
VGND ,
Q ,
Q_N ,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hs__u_dl_p_pg `UNIT_DELAY u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_FUNCTIONAL_V
|
module priority_encoder_40to6 (
binary_out,
valid,
encoder_in,
enable
);
output[5:0] binary_out;
output valid;
input[39:0] encoder_in;
input enable;
assign valid = (|encoder_in) & enable;
assign binary_out = (!enable) ? 6'd0 : (
(encoder_in[0]) ? 6'd0 :
(encoder_in[1]) ? 6'd1 :
(encoder_in[2]) ? 6'd2 :
(encoder_in[3]) ? 6'd3 :
(encoder_in[4]) ? 6'd4 :
(encoder_in[5]) ? 6'd5 :
(encoder_in[6]) ? 6'd6 :
(encoder_in[7]) ? 6'd7 :
(encoder_in[8]) ? 6'd8 :
(encoder_in[9]) ? 6'd9 :
(encoder_in[10]) ? 6'd10 :
(encoder_in[11]) ? 6'd11 :
(encoder_in[12]) ? 6'd12 :
(encoder_in[13]) ? 6'd13 :
(encoder_in[14]) ? 6'd14 :
(encoder_in[15]) ? 6'd15 :
(encoder_in[16]) ? 6'd16 :
(encoder_in[17]) ? 6'd17 :
(encoder_in[18]) ? 6'd18 :
(encoder_in[19]) ? 6'd19 :
(encoder_in[20]) ? 6'd20 :
(encoder_in[21]) ? 6'd21 :
(encoder_in[22]) ? 6'd22 :
(encoder_in[23]) ? 6'd23 :
(encoder_in[24]) ? 6'd24 :
(encoder_in[25]) ? 6'd25 :
(encoder_in[26]) ? 6'd26 :
(encoder_in[27]) ? 6'd27 :
(encoder_in[28]) ? 6'd28 :
(encoder_in[29]) ? 6'd29 :
(encoder_in[30]) ? 6'd30 :
(encoder_in[31]) ? 6'd31 :
(encoder_in[32]) ? 6'd32 :
(encoder_in[33]) ? 6'd33 :
(encoder_in[34]) ? 6'd34 :
(encoder_in[35]) ? 6'd35 :
(encoder_in[36]) ? 6'd36 :
(encoder_in[37]) ? 6'd37 :
(encoder_in[38]) ? 6'd38 :
(encoder_in[39]) ? 6'd39 : {6{1'bx}});
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; void test_case() { int n; scanf( %d , &n); vector<int> a(n); const int INF = 1e9 + 5; long long L = 1, R = INF; set<long long> s; long long offset = 0; int dp = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); if (i % 2 == 1) { int diff = a[i] - a[i - 1]; L += diff; R += diff; offset += diff; } L = max(L, 1LL); R = min(R, a[i] - 1LL); while (!s.empty() && *s.begin() + offset < 1) { s.erase(s.begin()); } while (!s.empty() && *s.rbegin() + offset >= a[i]) { s.erase(prev(s.end())); } if (L <= R || !s.empty()) { if (i != 0) { dp++; } if (a[i] % 2 == 0) { if ((L <= a[i] / 2 && a[i] / 2 <= R) || s.count(a[i] / 2 - offset)) { dp++; L = R = a[i] / 2; s.clear(); } else { s.insert(a[i] / 2 - offset); } } } else { L = 1; R = a[i] - 1; if (a[i] % 2 == 0) { L = R = a[i] / 2; dp++; } } } debug() << [ << dp : << (dp) << ] ; printf( %d n , 2 * n - dp); } int main() { int T; scanf( %d , &T); while (T--) { test_case(); } }
|
#include <bits/stdc++.h> using namespace std; const long long M = 1e9 + 7; const long long INF = LLONG_MAX / 2; const long long N = 2e5 + 1; struct event { long long sa; long long ea; long long sb; long long eb; }; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); { long long n; cin >> n; vector<event> a(n); for (long long i = 0; i < n; i++) cin >> a[i].sa >> a[i].ea >> a[i].sb >> a[i].eb; vector<pair<double, double> > p; multiset<pair<double, double> > s1; multiset<pair<double, double> > s2; bool ans = 1; for (long long i = 0; i < n; i++) { p.push_back({a[i].sa, i}); p.push_back({a[i].ea + 0.5, i}); } sort(p.begin(), p.end()); for (auto i : p) { pair<double, double> c = {a[i.second].sb, a[i.second].eb}; if (s1.count(c)) { s1.erase(s1.find(c)); s2.erase(s2.find({c.second, c.first})); } else { if (s1.empty() || (*s1.rbegin()).first <= c.second && (*s2.begin()).first >= c.first) { s1.insert(c); s2.insert({c.second, c.first}); } else { ans = 0; break; } } } s1.clear(); s2.clear(); p = vector<pair<double, double> >(0); for (long long i = 0; i < n; i++) { p.push_back({a[i].sb, i}); p.push_back({a[i].eb + 0.5, i}); } sort(p.begin(), p.end()); for (auto i : p) { pair<double, double> c = {a[i.second].sa, a[i.second].ea}; if (s1.count(c)) { s1.erase(s1.find(c)); s2.erase(s2.find({c.second, c.first})); } else { if (s1.empty() || (*s1.rbegin()).first <= c.second && (*s2.begin()).first >= c.first) { s1.insert(c); s2.insert({c.second, c.first}); } else { ans = 0; break; } } } if (ans) cout << YES ; else cout << NO ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mp[2010][2010]; long long sum1[2010][2010], sum2[2010][2010]; int n; int check(int x, int y, int xx, int yy) { int remy = abs(yy - y); int remx = abs(xx - x); if (remy == remx) return 0; return 1; } long long getsum(int i, int j) { long long s1 = 0, s2 = 0; int x1 = j - 1 + i, y1 = 1; if (x1 <= n) s1 = sum2[x1][y1]; int x2 = n, y2 = j - n + i; if (y2 >= 1) s1 = sum2[x2][y2]; x1 = n - j + i, y1 = n; if (x1 <= n) s2 = sum1[x1][y1]; x2 = n, y2 = j + n - i; if (y2 <= n) s2 = sum1[x2][y2]; return s1 + s2 - mp[i][j]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %I64d , &mp[i][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) sum1[i][j] = sum1[i - 1][j - 1] + mp[i][j]; for (int i = 1; i <= n; i++) for (int j = n; j >= 1; j--) sum2[i][j] = sum2[i - 1][j + 1] + mp[i][j]; long long maxv1 = sum2[1][1] + sum1[n][n] - 1; long long maxv2 = sum2[2][1] + sum1[n - 1][n] - 1; int x = 1, y = 1, xx = 1, yy = 2; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { long long sum = getsum(i, j); if ((i + j) % 2 == 1 && sum > maxv2) { x = i; y = j; maxv2 = sum; } if ((i + j) % 2 == 0 && sum > maxv1) { maxv1 = sum; xx = i; yy = j; } } } printf( %I64d n%d %d %d %d n , maxv1 + maxv2, x, y, xx, yy); }
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10; long long gi() { long long x = 0, o = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) o = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * o; } int n, tt; long long m, k, d[N]; pair<long long, long long> p[N]; int main() { int T = gi(); while (T--) { m = gi(); n = gi(); k = gi(); for (int i = 1; i <= n; i++) d[i] = gi(); d[++n] = m; for (int i = n; i; i--) d[i] -= d[i - 1]; if (!k) { cout << *max_element(d + 1, d + n + 1) - *min_element(d + 1, d + n + 1) << n ; continue; } long long l = 1, r = 1e15; while (l < r) { long long mid = (l + r + 1) >> 1, sum = 0; for (int i = 1; i <= n; i++) { sum += d[i] / mid - 1; if (sum >= k) break; } if (sum >= k) l = mid; else r = mid - 1; } long long mx = l; l = 1, r = 1e15; while (l < r) { long long mid = (l + r) >> 1, sum = 0; for (int i = 1; i <= n; i++) { sum += (d[i] + mid - 1) / mid - 1; if (sum > k) break; } if (sum <= k) r = mid; else l = mid + 1; } long long mn = l; tt = 0; for (int i = 1; i <= n; i++) { if ((d[i] + mn - 1) / mn > d[i] / mx) { long long t = d[i] / mx; p[++tt].first = d[i] / (t + 1); t = (d[i] + mn - 1) / mn; if (t == 1) p[tt].second = 1e18; else p[tt].second = (d[i] + t - 2) / (t - 1); } } sort(p + 1, p + tt + 1); long long low = mn, ans = 1e18; for (int i = 1, j; i <= tt; i = j + 1) { j = i; while (j < tt && p[j + 1].first == p[i].first) ++j; ans = min(ans, low - p[i].first); for (int k = i; k <= j; k++) low = max(low, p[k].second); } ans = min(ans, low - mx); cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = ~0ull / 2; const int maxn = 100100; int seen[maxn]; int ind[maxn]; int par[maxn][22]; int bd[maxn]; int h[maxn]; vector<int> adj[maxn]; vector<int> adlist[maxn]; vector<int> tree[maxn]; vector<pair<int, int> > edges; void dfs1(int root, int dad = -1) { seen[root] = 1; bd[root] = h[root]; for (auto v : adj[root]) { if (!seen[v]) { h[v] = h[root] + 1; dfs1(v, root); bd[root] = min(bd[v], bd[root]); if (!(bd[v] > h[root])) { adlist[root].push_back(v); adlist[v].push_back(root); } else { edges.push_back(make_pair(root, v)); } } else { if (v != dad) { adlist[root].push_back(v); adlist[v].push_back(root); bd[root] = min(bd[root], h[v]); } } } } void dfs2(int root, int t) { seen[root] = 2; ind[root] = t; for (auto v : adlist[root]) { if (seen[v] == 1) { dfs2(v, t); } } } void dfs3(int root, int dad) { par[root][0] = dad; for (auto v : tree[root]) { if (v != dad) { h[v] = h[root] + 1; dfs3(v, root); } } } int dis(int x, int y) { x = ind[x]; y = ind[y]; if (h[x] < h[y]) swap(x, y); int X = x; int Y = y; int t = 20; while (h[x] != h[y]) { if (h[par[x][t]] >= h[y]) x = par[x][t]; t--; } if (x == y) return h[X] - h[x]; int A; t = 20; while (par[x][0] != par[y][0] and t >= 0) { if (par[x][t] != par[y][t]) { x = par[x][t]; y = par[y][t]; } t--; } A = par[x][0]; return (h[X] + h[Y] - 2 * h[A]); } int main() { ios::sync_with_stdio(false), cin.tie(0); int n, m, k; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; adj[a].push_back(b); adj[b].push_back(a); } dfs1(0); int t = 1; for (int i = 0; i < n; i++) { if (seen[i] == 1) { dfs2(i, t); t++; } } for (auto e : edges) { int x = e.first; int y = e.second; x = ind[x]; y = ind[y]; tree[x].push_back(y); tree[y].push_back(x); } h[0] = 0; h[1] = 1; dfs3(1, 0); fill(par[0], par[0] + 22, 0); for (int i = 1; i < 22; i++) for (int j = 1; j < t; j++) par[j][i] = par[par[j][i - 1]][i - 1]; cin >> k; for (int i = 0; i < k; i++) { int s, l; cin >> s >> l; s--, l--; cout << dis(s, l) << n ; } }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; constexpr int MAXN = 100005; int n; string type[MAXN], word[MAXN]; bitset<30> to_bs(const string& s) { bitset<30> res; for (char c : s) { res[c - a ] = true; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; bitset<30> all = to_bs( abcdefghijklmnopqrstuvwxyz ); int ans = 0; for (int i = 0; i < n; ++i) { cin >> type[i] >> word[i]; bitset<30> cur = to_bs(word[i]); if (type[i][0] == ! ) { if (all.count() <= 1) { ans += 1; } all = all & cur; } else if (type[i][0] == . ) { all = all & cur.flip(); } else { if (all.count() == 1) ans += 1; all.reset(word[i][0] - a ); } } cout << max(0, ans - 1) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 10; const int INF = 1e9 + 9; const int B = 1e9 + 7; long long p[N], s[N]; int fp(int first) { return first == p[first] ? first : p[first] = fp(p[first]); } void u(int a, int b, int d) { s[fp(a)] += 4 * d; if (fp(a) == fp(b)) return; s[fp(b)] += s[fp(a)]; p[fp(a)] = fp(b); } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long> a(n + 1); long long ans = 0; for (int i = int(2); i <= int(n); ++i) p[i] = i, s[i] = 0; for (int i = int(n); i >= int(2); --i) for (int j = 2; i * j <= n; ++j) u(i, i * j, j); for (int i = int(2); i <= int(n); ++i) ans = max(ans, s[fp(i)]); cout << ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, o; string s; cin >> n >> s; o = s[n - 1] - 0 ; for (int i = 0; i < n - 1; i++) o += (s[i] == 0 ? 0 : s[i] - 47); cout << o << endl; } return 0; }
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module mrfm_compensator (input clock, input reset, input strobe_in,
input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data,
input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out);
wire [15:0] a11,a12,a21,a22;
reg [15:0] i_in_reg, q_in_reg;
wire [30:0] product;
reg [3:0] phase;
wire [15:0] data,coeff;
wire [7:0] shift;
wire [33:0] accum;
wire [15:0] scaled_accum;
wire enable_acc;
setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(a11),.changed());
setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(a12),.changed());
setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(a21),.changed());
setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(a22),.changed());
setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset),
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out(shift),.changed());
mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() );
acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(),
.addend(product),.sum(accum) );
shifter shifter (.in(accum),.out(scaled_accum),.shift(shift));
always @(posedge clock)
if(reset)
begin
i_in_reg <= #1 16'd0;
q_in_reg <= #1 16'd0;
end
else if(strobe_in)
begin
i_in_reg <= #1 i_in;
q_in_reg <= #1 q_in;
end
always @(posedge clock)
if(reset)
phase <= #1 4'd0;
else if(strobe_in)
phase <= #1 4'd1;
else if(strobe_in != 4'd8)
phase <= #1 phase + 4'd1;
assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg :
((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0;
assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 :
(phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0;
assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8);
assign enable_acc = ~clear_acc;
always @(posedge clock)
if(reset)
i_out <= #1 16'd0;
else if(phase == 4'd4)
i_out <= #1 scaled_accum;
always @(posedge clock)
if(reset)
q_out <= #1 16'd0;
else if(phase == 4'd7)
q_out <= #1 scaled_accum;
endmodule // mrfm_compensator
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#include <algorithm> #include <array> #include <cassert> #include <chrono> #include <cmath> #include <cstring> #include <functional> #include <iomanip> #include <iostream> #include <map> #include <numeric> #include <queue> #include <random> #include <set> #include <vector> using namespace std; template<typename A, typename B> ostream& operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } template<typename T_container, typename T = typename enable_if<!is_same<T_container, string>::value, typename T_container::value_type>::type> ostream& operator<<(ostream &os, const T_container &v) { os << { ; string sep; for (const T &x : v) os << sep << x, sep = , ; return os << } ; } void dbg_out() { cerr << endl; } template<typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } #ifdef NEAL_DEBUG #define dbg(...) cerr << ( << #__VA_ARGS__ << ): , dbg_out(__VA_ARGS__) #else #define dbg(...) #endif const int INF = int(1e9) + 5; int main() { ios::sync_with_stdio(false); #ifndef NEAL_DEBUG cin.tie(nullptr); #endif int N, A, B; string str; cin >> N >> A >> B >> str; vector<int> S(N); vector<int> char_to_index(128, -1); string chars; int C = 0; for (int i = 0; i < N; i++) { char ch = str[i]; if (char_to_index[ch] < 0) { char_to_index[ch] = C++; chars += ch; } S[i] = char_to_index[ch]; } dbg(chars); vector<int> char_start(C, INF); vector<int> char_end(C, -INF); vector<int> occur(C, 0); for (int i = 0; i < N; i++) { char_start[S[i]] = min(char_start[S[i]], i); char_end[S[i]] = max(char_end[S[i]], i + 1); occur[S[i]]++; } vector<bool> succeeds(1 << C, false); for (int mask = 1; mask < 1 << C; mask++) { int start = INF, end = -INF, count = 0; for (int c = 0; c < C; c++) if (mask >> c & 1) { start = min(start, char_start[c]); end = max(end, char_end[c]); count += occur[c]; } succeeds[mask] = count * B >= (end - start) * A; if (succeeds[mask]) dbg(mask, succeeds ); } vector<int> dp(1 << C, 0); for (int c = 0; c < C; c++) dp[1 << c] = 1 << c; for (int mask = 0; mask < 1 << C; mask++) { for (int split = 0; split < C; split++) { int lower = mask & ((1 << split) - 1); int upper = mask & -(1 << split); assert((lower | upper) == mask && (lower & upper) == 0); if (succeeds[lower] && dp[lower] != 0) dp[mask] |= dp[upper]; if (succeeds[upper] && dp[upper] != 0) dp[mask] |= dp[lower]; } for (int single = 0; single < C; single++) if (mask >> single & 1) { int without = mask & ~(1 << single); if (succeeds[without] && dp[without] != 0) dp[mask] |= 1 << single; } dbg(mask, dp[mask]); } int answer = dp[(1 << C) - 1]; cout << __builtin_popcount(answer); string sorted; for (int c = 0; c < C; c++) if (answer >> c & 1) sorted += chars[c]; sort(sorted.begin(), sorted.end()); for (auto &ch : sorted) cout << << ch; cout << n ; }
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//==================================================================================================
// Filename : musb_branch_unit.v
// Created On : 2014-09-27 20:14:58
// Last Modified : 2015-05-24 21:00:28
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Branch detection.
//==================================================================================================
`include "musb_defines.v"
module musb_branch_unit(
input [5:0] opcode, // Instruction opcode
input [31:0] id_pc_add4, // Instruction address + 4
input [31:0] id_data_rs, // Data from R0
input [31:0] id_data_rt, // Data from R1
input [25:0] op_imm26, // imm21/Imm16
output reg [31:0] pc_branch_address, // Destination address
output reg take_branch // Valid branch
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire beq;
wire bne;
wire bgez;
wire bgtz;
wire blez;
wire bltz;
wire [31:0] long_jump;
wire [31:0] short_jump;
wire [5:0] inst_function;
wire [4:0] op_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign beq = id_data_rs == id_data_rt;
assign bne = ~beq;
assign bgez = ~id_data_rs[31];
assign bgtz = id_data_rs > 32'b0;
assign blez = ~bgtz;
assign bltz = id_data_rs[31];
assign long_jump = {id_pc_add4[31:28], op_imm26, 2'b00 };
assign short_jump = $signed(id_pc_add4) + $signed( { op_imm26[`MUSB_INSTR_IMM16], 2'b00 } );
assign inst_function = op_imm26[`MUSB_INSTR_FUNCT];
assign op_rt = op_imm26[`MUSB_INSTR_RT];
//--------------------------------------------------------------------------
// Get branch address
//--------------------------------------------------------------------------
always @(*) begin
case (opcode)
`OP_BEQ : begin pc_branch_address <= short_jump; take_branch <= beq; end
`OP_BGTZ : begin pc_branch_address <= short_jump; take_branch <= bgtz; end
`OP_BLEZ : begin pc_branch_address <= short_jump; take_branch <= blez; end
`OP_BNE : begin pc_branch_address <= short_jump; take_branch <= bne; end
`OP_J : begin pc_branch_address <= long_jump; take_branch <= 1'b1; end
`OP_JAL : begin pc_branch_address <= long_jump; take_branch <= 1'b1; end
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin pc_branch_address <= short_jump; take_branch <= bgez; end
`RT_OP_BGEZAL : begin pc_branch_address <= short_jump; take_branch <= bgez; end
`RT_OP_BLTZ : begin pc_branch_address <= short_jump; take_branch <= bltz; end
`RT_OP_BLTZAL : begin pc_branch_address <= short_jump; take_branch <= bltz; end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
`OP_TYPE_R : begin
case(inst_function)
`FUNCTION_OP_JALR : begin pc_branch_address <= id_data_rs; take_branch <= 1'b1; end
`FUNCTION_OP_JR : begin pc_branch_address <= id_data_rs; take_branch <= 1'b1; end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
default : begin pc_branch_address <= 32'bx00; take_branch <= 1'b0; end
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int mara = (int)(1e6) + 5; vector<long long> a(mara), prime(mara), v(mara), luck; map<long long, bool> flag; long long bigmod(long long a, long long b, long long m) { long long res = 1; while (b) { if (b & 1) { res = (res * a) % m; b--; } else { b /= 2; a = (a * a) % m; } } return res; } void soln() { long long a, b, sum = 0; cin >> a >> b; for (long long i = 1; i <= 10; i++) { long long as = i * b; as %= 10; sum += as; } long long vajok = 10 * b; long long div = a / vajok; long long rem = a % vajok; long long res = sum * div; for (long long i = b; i <= rem; i += b) { long long temp = i; temp %= 10; res += temp; } cout << res << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { soln(); } return 0; }
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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dffsle_ns.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// dffrle_ns -- Positive-edge triggered flop with set_l, enable, without scan.
// _____________________________________________________________________________
//
// Description:
// Wrapper around a 'dffe_ns' flip-flop to create a Positive-edge triggered flop
// with set_l, enable, without scan.
// _____________________________________________________________________________
module dffsle_ns (/*AUTOARG*/
// Outputs
q,
// Inputs
din, en, set_l, clk
);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] din; // data in
input en; // functional enable
input set_l; // set
input clk; // clk
output [SIZE-1:0] q; // output
wire en_wire;
wire [SIZE-1:0] din_wire, q_wire;
// Enable Interpretation. Ultimate interpretation depends on design
//
// set_l en out
//---------------------
// 0 x 1 ; set dominates
// 1 1 din
// 1 0 q
//
//// synopsys sync_set_reset "set_l"
//always @ (posedge clk)
// if (!set_l)
// q[SIZE-1:0] <= {SIZE{1'b1}};
// else if (en)
// q[SIZE-1:0] <= din[SIZE-1:0];
// When 'set_l' is asserted, the value of '1' is forced onto the .din flop input and the .en pin
// is forced on to load the '1' into the flop on the next clock.
assign din_wire[SIZE-1:0] = ((en)? din[SIZE-1:0]: q_wire[SIZE-1:0]) | {SIZE{(~set_l)}};
assign en_wire = en || (~set_l);
dffe_ns #(SIZE) dff_reg (.din(din_wire[SIZE-1:0]), .en(en_wire), .q(q_wire[SIZE-1:0]), .clk(clk));
assign q = q_wire;
endmodule
// Local Variables:
// verilog-library-directories:()
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_int_arb")
// End:
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// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2011/08/15 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
reg_clk, // Avalon slave - clock
reg_rd, // Avalon slave - read
reg_wr, // Avalon slave - write
reg_addr, // Avalon slave - address
reg_data_in, // Avalon slave - writedata
reg_data_out, // Avalon slave - readdata
reg_busy, // Avalon slave - waitrequest
reset_reg_clk, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
rx_clk,
tx_clk,
rx_clkena,
tx_clkena,
gmii_rx_dv,
gmii_rx_d,
gmii_rx_err,
gmii_tx_en,
gmii_tx_d,
gmii_tx_err,
mii_rx_dv,
mii_rx_d,
mii_rx_err,
mii_tx_en,
mii_tx_d,
mii_tx_err,
mii_col,
mii_crs,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
set_10,
set_100,
set_1000,
hd_ena,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link);
parameter PHY_IDENTIFIER = 32'h 00000000 ;
parameter DEV_VERSION = 16'h 0001 ;
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_reg_clk; // Asynchronous Reset - clk Domain
output rx_clk; // MAC Receive clock
output tx_clk; // MAC Transmit clock
output rx_clkena; // MAC Receive Clock Enable
output tx_clkena; // MAC Transmit Clock Enable
output gmii_rx_dv; // GMII Receive Enable
output [7:0] gmii_rx_d; // GMII Receive Data
output gmii_rx_err; // GMII Receive Error
input gmii_tx_en; // GMII Transmit Enable
input [7:0] gmii_tx_d; // GMII Transmit Data
input gmii_tx_err; // GMII Transmit Error
output mii_rx_dv; // MII Receive Enable
output [3:0] mii_rx_d; // MII Receive Data
output mii_rx_err; // MII Receive Error
input mii_tx_en; // MII Transmit Enable
input [3:0] mii_tx_d; // MII Transmit Data
input mii_tx_err; // MII Transmit Error
output mii_col; // MII Collision
output mii_crs; // MII Carrier Sense
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
input reg_clk; // Register Interface Clock
input reg_rd; // Register Read Enable
input reg_wr; // Register Write Enable
input [4:0] reg_addr; // Register Address
input [15:0] reg_data_in; // Register Input Data
output [15:0] reg_data_out; // Register Output Data
output reg_busy; // Access Busy
output led_crs; // Carrier Sense
output led_link; // Valid Link
output hd_ena; // Half-Duplex Enable
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
output set_10; // 10Mbps Link Indication
output set_100; // 100Mbps Link Indication
output set_1000; // Gigabit Link Indication
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire gmii_rx_dv;
wire [7:0] gmii_rx_d;
wire gmii_rx_err;
wire mii_rx_dv;
wire [3:0] mii_rx_d;
wire mii_rx_err;
wire mii_col;
wire mii_crs;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire [15:0] reg_data_out;
wire reg_busy;
wire led_crs;
wire led_link;
wire hd_ena;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire set_10;
wire set_100;
wire set_1000;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk),
.reset_tx_clk(reset_tx_clk),
.reset_reg_clk(reset_reg_clk),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_d(gmii_rx_d),
.gmii_rx_err(gmii_rx_err),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_d(gmii_tx_d),
.gmii_tx_err(gmii_tx_err),
.mii_rx_dv(mii_rx_dv),
.mii_rx_d(mii_rx_d),
.mii_rx_err(mii_rx_err),
.mii_tx_en(mii_tx_en),
.mii_tx_d(mii_tx_d),
.mii_tx_err(mii_tx_err),
.mii_col(mii_col),
.mii_crs(mii_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(reg_clk),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.reg_addr(reg_addr),
.reg_data_in(reg_data_in),
.reg_data_out(reg_data_out),
.reg_busy(reg_busy),
.powerdown(powerdown),
.set_10(set_10),
.set_100(set_100),
.set_1000(set_1000),
.hd_ena(hd_ena),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline void write(int x) { if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(int x) { write(x); putchar( n ); } const int N = 1000005; struct node { int l, r; } b[N]; struct que { int l, r, id; } c[N]; int now; int Ans[N]; int n, k, q; int Mx[N * 4], pos[N * 4]; int Mxdis[N]; int stkc[N], topc; int Pos, ans; inline bool cmp2(node a, node b) { return a.r < b.r || (a.r == b.r && a.l > b.l); } inline bool cmp3(que a, que b) { return a.r < b.r || (a.r == b.r && a.l > b.l); } inline void change(int x, int y) { int l = 1, r = n, num = 1; while (1) { int mid = (l + r) >> 1; if (Mx[num] < y) pos[num] = x, Mx[num] = y; if (l == r) break; if (x <= mid) r = mid, num = (num << 1); else l = mid + 1, num = (num << 1 | 1); } } inline void query(int num, int l, int r, int x, int y) { if (x <= l && r <= y) { if (Mx[num] > ans) { Pos = pos[num]; ans = Mx[num]; } return; } int mid = (l + r) >> 1; if (x <= mid) query(num << 1, l, mid, x, y); if (y > mid) query(num << 1 | 1, mid + 1, r, x, y); } int main() { n = read(); k = read(); for (int i = 1; i <= k; ++i) b[i].l = read(), b[i].r = read(); q = read(); for (int i = 1; i <= q; ++i) c[i].l = read(), c[i].r = read(), c[i].id = i; sort(b + 1, b + k + 1, cmp2); sort(c + 1, c + q + 1, cmp3); now = 1; for (int i = 1; i <= n; ++i) Mxdis[i] = i; for (int i = 1; i <= q; ++i) { while (now <= k && b[now].r <= c[i].r) { if (Mxdis[b[now].l] < b[now].r) { change(b[now].l, b[now].r); Mxdis[b[now].l] = b[now].r; } ++now; } topc = 0; stkc[++topc] = c[i].l; int last = c[i].l; while (1) { int x = stkc[topc]; Pos = 0, ans = 0; query(1, 1, n, last, Mxdis[x]); if (ans > Mxdis[x]) stkc[++topc] = Pos, last = Mxdis[x]; else break; } int mm = Mxdis[stkc[topc--]]; while (topc > 0) { change(stkc[topc], mm); Mxdis[stkc[topc--]] = mm; } Ans[c[i].id] = mm; } for (int i = 1; i <= q; ++i) writeln(Ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<int> st; int x; int sz = 0; for (int i = 0; i < n; i++) { cin >> x; if (sz > 3) continue; if (st.find(x) == st.end()) { sz++; st.insert(x); } } if (sz > 3) cout << NO << endl; else if (sz < 3) cout << YES << endl; else { auto it = st.begin(); int a, b, c; a = *it; it++; b = *it; it++; c = *it; if (b - a == c - b) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 410000; char ch[N]; int a[N]; int n, t; int main() { scanf( %d%d , &n, &t); scanf( %s , ch + 1); if (t == 0) { printf( %s , ch + 1); return 0; } int s = 0; for (int i = 1; i <= n; i++) { if (ch[i] == . ) s = i + 1; else if (s == 0) a[i + 1] = ch[i] - 0 ; else a[i] = ch[i] - 0 ; } int ok = 0; for (int i = s; i <= n; i++) if (a[i] >= 5) { n = i - 1; ok = 1; t--; a[i - 1]++; break; } if (ok == 0) { printf( %s , ch + 1); return 0; } while (t && n >= s && a[n] >= 5) { a[n - 1]++; a[n] %= 10; if (a[n]) t--; n--; } while (n >= s && a[n] == 0) n--; for (int i = n - 1; i >= 1; i--) a[i] += a[i + 1] / 10, a[i + 1] %= 10; if (a[1]) printf( %d , a[1]); for (int i = 2; i <= n; i++) { if (i == s) printf( . ); printf( %d , a[i]); } }
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#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; int m, n; pii a[100001]; vector<int> adj[100001]; bool is_chosen[100001]; bool is_visited[100001]; int cnt = 0; template <typename T> inline T read() { T x = 0; T multiplier = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) { multiplier = -1; } ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch & 15); ch = getchar(); } return x * multiplier; } void dfs(int u, int prt) { if (is_chosen[a[u].first] && is_chosen[a[u].second]) { return; } if (is_visited[u]) { return; } is_visited[u] = true; bool x = is_chosen[a[u].first], y = is_chosen[a[u].second]; if (!x) { is_chosen[a[u].first] = true; is_chosen[a[u].second] = true; for (auto v : adj[a[u].first]) { if (v != prt) { dfs(v, u); } } } if (!y) { is_chosen[a[u].first] = true; is_chosen[a[u].second] = true; for (auto v : adj[a[u].second]) { if (v != prt) { dfs(v, u); } } } is_chosen[a[u].first] = true; is_chosen[a[u].second] = true; } int main() { n = read<int>(), m = read<int>(); for (int i = 1; i <= m; i++) { a[i].first = read<int>(); a[i].second = read<int>(); } sort(a + 1, a + m + 1); for (int i = 1; i <= m; i++) { adj[a[i].first].push_back(i); adj[a[i].second].push_back(i); } for (int i = 1; i <= m; i++) { if (!is_visited[i]) { dfs(i, -1); } } for (int i = 1; i <= m; i++) { cnt += !is_visited[i]; } printf( %d n , cnt); return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cyclone2_dmem.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cyclone2_dmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address[9..0]
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC byteena[1..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cyclone2_dmem_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003, 2007 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
parameter bitwidth = 16;
parameter zwidth = 16;
input clock;
input reset;
input enable;
input [bitwidth-1:0] xi, yi;
output [bitwidth-1:0] xo, yo;
input [zwidth-1:0] zi;
output [zwidth-1:0] zo;
reg [bitwidth+1:0] x0,y0;
reg [zwidth-2:0] z0;
wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
// Compute consts. Would be easier if vlog had atan...
// see gen_cordic_consts.py
localparam c00 = 15'd8192;
localparam c01 = 15'd4836;
localparam c02 = 15'd2555;
localparam c03 = 15'd1297;
localparam c04 = 15'd651;
localparam c05 = 15'd326;
localparam c06 = 15'd163;
localparam c07 = 15'd81;
localparam c08 = 15'd41;
localparam c09 = 15'd20;
localparam c10 = 15'd10;
localparam c11 = 15'd5;
localparam c12 = 15'd3;
localparam c13 = 15'd1;
localparam c14 = 15'd1;
localparam c15 = 15'd0;
localparam c16 = 15'd0;
always @(posedge clock)
if(reset)
begin
x0 <= 0; y0 <= 0; z0 <= 0;
end
else// if(enable)
begin
z0 <= zi[zwidth-2:0];
case (zi[zwidth-1:zwidth-2])
2'b00, 2'b11 :
begin
x0 <= xi_ext;
y0 <= yi_ext;
end
2'b01, 2'b10 :
begin
x0 <= -xi_ext;
y0 <= -yi_ext;
end
endcase // case(zi[zwidth-1:zwidth-2])
end // else: !if(reset)
// FIXME need to handle variable number of stages
// FIXME should be able to narrow zwidth but quartus makes it bigger...
// This would be easier if arrays worked better in vlog...
cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
assign xo = x12[bitwidth:1];
assign yo = y12[bitwidth:1];
//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
//assign yo = y12[bitwidth+1:2];
assign zo = z12;
endmodule // cordic
|
#include <bits/stdc++.h> using namespace std; int main() { int n; double x, r1 = 0, p1 = 0, p2 = 999999999999, a, b; cin >> n; while (n--) { cin >> x; r1 = max(r1, x); } cin >> n; while (n--) { cin >> x; p1 = max(p1, x); } cin >> n; while (n--) { cin >> x; p2 = min(p2, x); } cin >> a >> b; x = b * p1; double up = x * r1 * r1, down = a * p2 + x; cout << setprecision(10) << sqrt(up / down); }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module writes data to the Audio DAC on the Altera DE2 board. *
* *
******************************************************************************/
module altera_up_audio_out_serializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
left_channel_data,
left_channel_data_en,
right_channel_data,
right_channel_data_en,
// Bidirectionals
// Outputs
left_channel_fifo_write_space,
right_channel_fifo_write_space,
serial_audio_out_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input [DW: 0] left_channel_data;
input left_channel_data_en;
input [DW: 0] right_channel_data;
input right_channel_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] left_channel_fifo_write_space;
output reg [ 7: 0] right_channel_fifo_write_space;
output reg serial_audio_out_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_left_channel;
wire read_right_channel;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [ 6: 0] left_channel_fifo_used;
wire [ 6: 0] right_channel_fifo_used;
wire [DW: 0] left_channel_from_fifo;
wire [DW: 0] right_channel_from_fifo;
// Internal Registers
reg left_channel_was_read;
reg [DW: 0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_fifo_write_space <= 8'h00;
else
left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_channel_fifo_write_space <= 8'h00;
else
right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_audio_out_data <= 1'b0;
else
serial_audio_out_data <= data_out_shift_reg[DW];
end
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_was_read <= 1'b0;
else if (read_left_channel)
left_channel_was_read <= 1'b1;
else if (read_right_channel)
left_channel_was_read <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= 'h0;
else if (read_left_channel)
data_out_shift_reg <= left_channel_from_fifo;
else if (read_right_channel)
data_out_shift_reg <= right_channel_from_fifo;
else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
data_out_shift_reg <= 'h0;
else if (bit_clk_falling_edge)
data_out_shift_reg <=
{data_out_shift_reg[(DW - 1):0], 1'b0};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_left_channel = left_right_clk_rising_edge &
~left_channel_fifo_is_empty &
~right_channel_fifo_is_empty;
assign read_right_channel = left_right_clk_falling_edge &
left_channel_was_read;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_sync_fifo Audio_Out_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_channel_data_en & ~left_channel_fifo_is_full),
.write_data (left_channel_data),
.read_en (read_left_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_from_fifo)
);
defparam
Audio_Out_Left_Channel_FIFO.DW = DW,
Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Left_Channel_FIFO.AW = 6;
altera_up_sync_fifo Audio_Out_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (right_channel_data_en & ~right_channel_fifo_is_full),
.write_data (right_channel_data),
.read_en (read_right_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_from_fifo)
);
defparam
Audio_Out_Right_Channel_FIFO.DW = DW,
Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Right_Channel_FIFO.AW = 6;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, c, ans[4010]; scanf( %d %d %d %d , &n, &a, &b, &c); memset(ans, -1, sizeof(ans)); ans[0] = 0; for (int i = 0; i <= n; i++) { if (i >= a && ans[i - a] != -1) ans[i] = ans[i - a] + 1; if (i >= b && ans[i - b] != -1) ans[i] = max(ans[i], ans[i - b] + 1); if (i >= c && ans[i - c] != -1) ans[i] = max(ans[i], ans[i - c] + 1); } printf( %d n , ans[n]); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:33:51 11/06/2015
// Design Name: Booth_Multiplier_II
// Module Name: /home/sidharth/Documents/Xilinx Projects/NEW2/Booth_Tester_2.v
// Project Name: NEW2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Booth_Multiplier_II
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Booth_Tester_2;
// Inputs
reg [3:0] multiplicand;
reg [3:0] multiplier;
// Outputs
wire [7:0] product;
// Instantiate the Unit Under Test (UUT)
Booth_Multiplier_II uut (
.product(product),
.multiplicand(multiplicand),
.multiplier(multiplier)
);
initial begin
// Initialize Inputs
multiplicand = 4'b1100;
multiplier = 4'b1011;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y) { if (y == 0) return 1; long long int d = power(x, y / 2) % 1000000007; if (y % 2 == 0) return (d * d) % 1000000007; else return (((x * d) % 1000000007) * d) % 1000000007; } long long int divmod(long long int num, long long int den) { return (num * (power(den, 1000000007 - 2))) % 1000000007; } int mobius[100001]; int mob(int x) { int cnt = 0; for (int i = 2; i * i <= x; i++) { if (x % i == 0) { x = x / i; cnt++; } if (x % i == 0) { return 0; } } if (x > 1) { cnt++; } if (cnt & 1) return -1; return 1; } long long int nmod(long long int x) { return (x % 1000000007 + 1000000007) % 1000000007; } long long int fact[100001]; long long int ncr(long long int n, long long int r) { long long int num = fact[n]; long long int den = fact[r] * fact[n - r]; den %= 1000000007; return divmod(num, den); } long long int calc(long long int n, long long int k, long long int x) { n = n / x; n = n - k; if (n < 0) return 0; if (n == 0) return 1; return ncr(n + k - 1, k - 1); } void solve() { int n, k; scanf( %d , &n); scanf( %d , &k); vector<int> f; for (int i = 1; i * i <= n; i++) { if (i * i == n) { f.push_back(i); break; } if (n % i == 0) { f.push_back(i); f.push_back(n / i); } } long long int ans = 0; for (int i = 0; i < f.size(); i++) { if (mobius[f[i]] == 0) continue; ans = ans + mobius[f[i]] * calc(n, k, f[i]); } ans = nmod(ans); printf( %lld n , ans); } int main() { fact[0] = 1; for (int i = 1; i <= 100000; i++) fact[i] = (i * fact[i - 1]) % 1000000007; mobius[1] = 1; for (int i = 2; i <= 100000; i++) { mobius[i] = mob(i); } int q; scanf( %d , &q); for (int i = 0; i < q; i++) solve(); }
|
#include <bits/stdc++.h> inline int in() { int x = 0; char c = getchar(); bool f = false; while (c < 0 || c > 9 ) f |= c == - , c = getchar(); while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return f ? -x : x; } const int N = 105; int t[N], f[N * N][N], tot; int main() { int n = in(), res = 1; for (int i = 1; i <= n; ++i) { int a = in(); if (!t[a]) ++tot; ++t[a]; } if (tot <= 2) { printf( %d n , n); return 0; } f[0][0] = 1; for (int i = 1; i <= 100; ++i) if (t[i]) { for (int j = 10000; j; --j) for (int k = 1; k <= n; ++k) for (int l = 1; l <= t[i] && l <= k && l * i <= j; ++l) f[j][k] += f[j - l * i][k - l]; } for (int i = 1; i <= 100; ++i) if (t[i]) for (int j = 1; j <= t[i]; ++j) if (f[i * j][j] == 1) res = std::max(res, j); printf( %d n , res); return 0; }
|
`timescale 1ns/1ns
module usb_tx_data
(input c,
input [7:0] d,
input dv,
output [7:0] sie_d,
output sie_dv);
// no need for FIFO: just delay it one clock (after SYNC) and compute CRC16
// on the fly
localparam ST_IDLE = 4'd0;
localparam ST_SYNC = 4'd1;
localparam ST_DATA = 4'd2;
localparam ST_CRC_HI = 4'd3;
localparam ST_CRC_LO = 4'd4;
localparam ST_DONE = 4'd5;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [7:0] d_d1;
d1 #(8) d_d1_r(.c(c), .d(d), .q(d_d1));
//wire [15:0] crc = 16'h1234;
wire [15:0] crc;
wire crc_dv;
usb_crc16 usb_crc16_inst
(.c(c), .d(d_d1), .dv(crc_dv), .rst(state == ST_IDLE), .crc(crc));
wire [1:0] sie_d_sel;
wire [7:0] sie_mux_z;
gmux #(.DWIDTH(8), .SELWIDTH(2)) sie_d_gmux
(.d({crc, d_d1, 8'b10000000}),
.sel(sie_d_sel),
.z(sie_mux_z));
wire [7:0] sie_d_i = sie_dv_i ? sie_mux_z : 8'h0;
always @* begin
case (state)
ST_IDLE:
if (dv) ctrl = { ST_SYNC , 5'b00_00_1 };
else ctrl = { ST_IDLE , 5'b00_00_0 };
ST_SYNC: ctrl = { ST_DATA , 5'b00_01_1 };
ST_DATA:
if (~dv) ctrl = { ST_CRC_LO, 5'b01_01_1 };
else ctrl = { ST_DATA , 5'b01_01_1 };
ST_CRC_LO: ctrl = { ST_CRC_HI, 5'b00_10_1 };
ST_CRC_HI: ctrl = { ST_DONE , 5'b00_11_1 };
ST_DONE: ctrl = { ST_IDLE , 5'b00_11_0 };
default: ctrl = { ST_IDLE , 5'b00_00_0 };
endcase
end
wire sie_dv_i = ctrl[0];
assign sie_d_sel = ctrl[2:1];
assign crc_dv = ctrl[3];
// help timing a bit
d1 #(8) sie_d1_d_r (.c(c), .d(sie_d_i ), .q(sie_d ));
d1 sie_d1_dv_r(.c(c), .d(sie_dv_i), .q(sie_dv));
endmodule
|
`timescale 1ns/10ps
/*
功能：读写请求控制，写优先级高于读
输入：nrst-0复位
clk-时钟
wr_req-写请求
rd_req-读请求
输出：wr_sta-写状态，1可写
rd_sta-读状态，1可读
修改：eleqian 2016-01-22
*/
module rw_ctrl(nrst, clk, wr_req, rd_req, wr_sta, rd_sta);
input nrst;
input clk;
input wr_req;
input rd_req;
output wr_sta; // 处于写状态
output rd_sta; // 处于读状态
reg wr_sta;
reg rd_pend; // 读请求pending信号
// 写状态转换
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
wr_sta <= 1'b0;
end else begin
wr_sta <= wr_req;
end
end
// 读pending状态转换
always @(posedge clk or negedge nrst) begin
if (~nrst) begin
rd_pend <= 1'b0;
end else if (rd_req) begin
rd_pend <= 1'b1;
end else if (rd_sta) begin
rd_pend <= 1'b0;
end
end
// 当写状态无效且读pending时才可读
assign rd_sta = rd_pend & ~wr_sta;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; const long long MOD = 1000000007; void solve_test() { int n; cin >> n; vector<int> arr(n); vector<int> ct(101); for (int i = 0; i < n; i++) { cin >> arr[i]; ct[arr[i]]++; } int max_val = -1; int max_freq = -1; for (int i = 1; i <= 100; i++) { if (ct[i] > max_freq) { max_freq = ct[i]; max_val = i; } } unordered_map<int, int> um; int ans = 0; for (int i = 1; i <= 100; i++) { if (max_val == i) continue; um.clear(); int st = 0; um[0] = -1; for (int j = 0; j < n; j++) { if (arr[j] == i) { st++; } else if (arr[j] == max_val) { st--; } if (um.find(st) == um.end()) { um[st] = j; } else { ans = max(ans, j - um[st]); } } } cout << ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); int tests; tests = 1; while (tests--) { solve_test(); } return 0; }
|
//-----------------------------------------------------
// Design Name : uart
// File Name : uart.v
// Function : Simple UART
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module uart (
reset ,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out ,
tx_empty ,
rxclk ,
uld_rx_data ,
rx_data ,
rx_enable ,
rx_in ,
rx_empty
);
// Port declarations
input reset ;
input txclk ;
input ld_tx_data ;
input [7:0] tx_data ;
input tx_enable ;
output tx_out ;
output tx_empty ;
input rxclk ;
input uld_rx_data ;
output [7:0] rx_data ;
input rx_enable ;
input rx_in ;
output rx_empty ;
// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ;
reg [3:0] tx_cnt ;
reg tx_out ;
reg [7:0] rx_reg ;
reg [7:0] rx_data ;
reg [3:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;
// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg <= 0;
rx_data <= 0;
rx_sample_cnt <= 0;
rx_cnt <= 0;
rx_frame_err <= 0;
rx_over_run <= 0;
rx_empty <= 1;
rx_d1 <= 1;
rx_d2 <= 1;
rx_busy <= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if (!rx_busy && !rx_d2) begin
rx_busy <= 1;
rx_sample_cnt <= 1;
rx_cnt <= 0;
end
// Start of frame detected, Proceed with rest of data
if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin
rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin
rx_busy <= 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err <= 1;
end else begin
rx_empty <= 0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded,
rx_over_run <= (rx_empty) ? 0 : 1;
end
end
end
end
end
end
if (!rx_enable) begin
rx_busy <= 0;
end
end
// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg <= 0;
tx_empty <= 1;
tx_over_run <= 0;
tx_out <= 1;
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin
if (!tx_empty) begin
tx_over_run <= 0;
end else begin
tx_reg <= tx_data;
tx_empty <= 0;
end
end
if (tx_enable && !tx_empty) begin
tx_cnt <= tx_cnt + 1;
if (tx_cnt == 0) begin
tx_out <= 0;
end
if (tx_cnt > 0 && tx_cnt < 9) begin
tx_out <= tx_reg[tx_cnt -1];
end
if (tx_cnt == 9) begin
tx_out <= 1;
tx_cnt <= 0;
tx_empty <= 1;
end
end
if (!tx_enable) begin
tx_cnt <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, x[N], y[N], xs[N], ys[N], cnt[2][2]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &x[i], &y[i]); xs[i] = x[i], ys[i] = y[i]; } sort(xs + 1, xs + n + 1); sort(ys + 1, ys + n + 1); int m = (n + 1) / 2; int cx = xs[m], cy = ys[m]; int dx = xs[m + 1] - xs[m], dy = ys[m + 1] - ys[m]; if (n & 1) { dx = min(dx, xs[m] - xs[m - 1]); dy = min(dy, ys[m] - ys[m - 1]); } long long ans = 0; bool flag = 0; for (int i = 1; i <= n; i++) { ans += abs(x[i] - cx) + abs(y[i] - cy); ++cnt[x[i] <= cx][y[i] <= cy]; if (x[i] == cx && y[i] == cy) flag = 1; } if (cnt[0][0] && cnt[0][1] && cnt[1][1] && cnt[1][0]) { if (n % 2 == 0 || flag) ans -= min(dx, dy); } printf( %lld n , ans * 2); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_0_V
`define SKY130_FD_SC_LP__A211OI_0_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_0 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_0_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.size(); queue<int> pos; int arr[n]; arr[0] = 0; int lastb = -1; for (int i = 0; i < n; i++) { if (s[i] == b ) { if (i + 3 < n) { if (s.substr(i, 4) == bear ) { pos.push(i); lastb = i; } } } if (i > 0) { arr[i] = arr[i - 1]; } if (s[i] == r ) { if (lastb != -1 && i - lastb <= 3) { arr[i] = arr[i - 1] + 1; } } } int k = 0; int ans = 0; for (int i = 0; i < n; i++) { if (!pos.empty() && i > pos.front()) { k++; pos.pop(); } for (int j = i + 1; j < n; j++) { if (arr[j] - k > 0) { ans++; } } } cout << ans; }
|
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