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module adder(
input wire a,
input wire b,
input wire ci,
output reg s,
output reg co
);
always @ (*)
{co, s} = a + b + ci;
endmodule
module mult(
input wire [3:0] opA,
input wire [3:0] opB,
output wire [7:0] result
);
wire a [11:0];
wire b [11:0];
wire c [11:0];
wire s [11:0];
assign result = {c[11] ,s[11], s[10], s[9], s[8], s[4], s[0], (opA[0] & opB[0])};
adder add0( .a(opA[0] & opB[1]), .b(opA[1] & opB[0]), .ci(1'b0), .s(s[0]), .co(c[0]) );
adder add1( .a(opA[2] & opB[0]), .b(opA[1] & opB[1]), .ci(c[0]), .s(s[1]), .co(c[1]) );
adder add2( .a(opA[3] & opB[0]), .b(opA[2] & opB[1]), .ci(c[1]), .s(s[2]), .co(c[2]) );
adder add3( .a(1'b0), .b(opA[3] & opB[1]), .ci(c[2]), .s(s[3]), .co(c[3]) );
adder add4( .a(s[1]), .b(opA[0] & opB[2]), .ci(1'b0), .s(s[4]), .co(c[4]) );
adder add5( .a(s[2]), .b(opA[1] & opB[2]), .ci(c[4]), .s(s[5]), .co(c[5]) );
adder add6( .a(s[3]), .b(opA[2] & opB[2]), .ci(c[5]), .s(s[6]), .co(c[6]) );
adder add7( .a(c[3]), .b(opA[3] & opB[2]), .ci(c[6]), .s(s[7]), .co(c[7]) );
adder add8( .a(s[5]), .b(opA[0] & opB[3]), .ci(1'b0), .s(s[8]), .co(c[8]) );
adder add9( .a(s[6]), .b(opA[1] & opB[3]), .ci(c[8]), .s(s[9]), .co(c[9]) );
adder add10( .a(s[7]), .b(opA[2] & opB[3]), .ci(c[9]), .s(s[10]), .co(c[10]) );
adder add11( .a(c[7]), .b(opA[3] & opB[3]), .ci(c[10]), .s(s[11]), .co(c[11]) );
endmodule
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_BEHAVIORAL_V
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#include <bits/stdc++.h> using namespace std; set<pair<long long int, long long int> > s; pair<long long int, long long int> p; long long int d[300000], x, n, k, l = 0, di = 0; vector<long long int> v[300000]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> x; d[i] = x; v[x].push_back(i); di = max(x, di); } if (v[0].size() > 1 || v[1].size() > k) { cout << -1; return 0; } for (int i = 0; i <= di; i++) if (v[i].size() == 0) { cout << -1; return 0; } for (int i = 0; i < v[1].size(); i++) s.insert({v[0][0], v[1][i]}); for (int i = 2; i <= di; i++) { if (v[i - 1].size() * (k - 1) < v[i].size()) { cout << -1; return 0; } x = 1; l = 0; for (int j = 0; j < v[i].size(); j++) { if (x > k - 1) { l++; x = 1; } s.insert({v[i - 1][l], v[i][j]}); x++; } } cout << s.size() << endl; while (!s.empty()) { p = *s.begin(); cout << p.first << << p.second << n ; s.erase(s.begin()); } return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
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#include <bits/stdc++.h> using namespace std; const long long maxn = 200010; const long long MOD = 1e9 + 7; const long long INF = 1e9; const long long LINF = 1e18; long long n, m, a[maxn], b[maxn]; map<long long, long long> M, N; string s, ss; set<long long> S; long long l, r, h; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long ans = 0; for (long long i = 0; i < n; i++) ans += ((a[i] % 10007) * (a[n - i - 1] % 10007)) % 10007, ans %= 10007; cout << ans; }
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#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int INFINITE = 0x3f3f3f3f; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> inline T lowbit(T n) { return (n ^ (n - 1)) & n; } template <class T> inline int countbit(T n) { return (n == 0) ? 0 : (1 + countbit(n & (n - 1))); } typedef vector<int> VI; typedef vector<VI> VII; typedef vector<string> VS; int dx[4] = {1, 0, 0, -1}; int dy[4] = {0, 1, -1, 0}; bool isright(int x1, int y1, int x2, int y2, int x3, int y3) { int l12 = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); int l23 = (x2 - x3) * (x2 - x3) + (y2 - y3) * (y2 - y3); int l31 = (x3 - x1) * (x3 - x1) + (y3 - y1) * (y3 - y1); if (l12 == 0 || l23 == 0 || l31 == 0) return false; return (l12 + l23 == l31 || l12 + l31 == l23 || l23 + l31 == l12); } int main() { ios::sync_with_stdio(false); int p[3][2]; cin >> p[0][0] >> p[0][1] >> p[1][0] >> p[1][1] >> p[2][0] >> p[2][1]; if (isright(p[0][0], p[0][1], p[1][0], p[1][1], p[2][0], p[2][1])) { cout << RIGHT n ; return 0; } for (int n = (int)(0); n < (int)(3); n++) for (int i = (int)(0); i < (int)(4); i++) { p[n][0] += dx[i], p[n][1] += dy[i]; if (isright(p[0][0], p[0][1], p[1][0], p[1][1], p[2][0], p[2][1])) { cout << ALMOST n ; return 0; } p[n][0] -= dx[i], p[n][1] -= dy[i]; } cout << NEITHER n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int xp, nb; cin >> xp >> nb; cout << min(xp, min(nb, (xp + nb) / 3)); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> v[100005]; bool d[100005]; int s[100005]; void del(int i, int par) { if (v[i].size() <= 2) { d[i] = true; for (int j : v[i]) if (j != par) del(j, i); } } int main() { int n; cin >> n; int a, b; for (int i = 1; i < n; i++) { cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } for (int i = 1; i <= n; i++) { if (v[i].size() == 1) del(i, 0); } for (int i = 1; i <= n; i++) { for (int j : v[i]) if (d[j]) s[i] = min(s[i] + 1, 2); } for (int i = 1; i <= n; i++) if (!d[i]) { int cnt = 0; for (int j : v[i]) if (!d[j] && v[j].size() - s[j] > 1) cnt++; if (cnt > 2) { cout << No n ; return 0; } } cout << Yes n ; return 0; }
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#include <bits/stdc++.h> int main() { int n, m; while (scanf( %d %d , &n, &m) != EOF) { if (n * m < 2) { printf( 0 n ); } else { printf( %d n , n * m / 2); } } }
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#include <bits/stdc++.h> using namespace std; map<pair<int, int>, int> ord; vector<pair<int, int> > edges; vector<int> adj[200000]; int n; int main() { cin >> n; cout << n - 1 << endl; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; edges.push_back(make_pair(a, b)); ord[make_pair(a, b)] = ord[make_pair(b, a)] = i; adj[a].push_back(b); adj[b].push_back(a); cout << 2 << a << << b << endl; } for (int i = 1; i <= n; i++) for (int j = 0; j < adj[i].size() - 1; j++) cout << ord[make_pair(i, adj[i][j])] << << ord[make_pair(i, adj[i][j + 1])] << endl; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 6, MAX = 2e5 + 5, OO = 1000000009; long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long lcm(long long x, long long y) { return (x * y / gcd(x, y)); } long long fact(long long z) { return (z <= 1) ? 1 : z * fact(z - 1); } int a, b, aa, bb, ans; void Check(int p) { while (a % p == 0) { a /= p; aa++; } while (b % p == 0) { b /= p; bb++; } ans += abs(aa - bb); aa = bb = 0; } int main() { scanf( %d %d , &a, &b); Check(2); Check(3); Check(5); return printf( %d , a == b ? ans : -1), 0; }
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#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const long long INF = 2e18; const int N = 1231234; int n, m; int a[N], b[N]; bool ok(long long x) { int i, j; for (i = 0, j = 0; i < m; ++i) { while (j < n && abs(b[i] - a[j]) <= x) j++; } return j == n; } int main() { while (cin >> n >> m) { int i, j; for (i = 0; i < n; ++i) scanf( %d , &a[i]); for (i = 0; i < m; ++i) scanf( %d , &b[i]); long long l = 0, r = INF; while (l <= r) { long long mid = (l + r) >> 1; if (ok(mid)) r = mid - 1; else l = mid + 1; } printf( %I64d n , l); } }
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`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("25.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; int main() { ios::sync_with_stdio(0); cin.tie(0); int q; cin >> q; for (int cas = 0; cas < q; ++cas) { ll a, b, m; cin >> a >> b >> m; if (a == b) { cout << 1 << << a << n ; continue; } if (b - a <= m) { cout << 2 << << a << << b << n ; continue; } bool poss = false; for (ll ans = 3; ans <= 50; ++ans) { vector<ll> sum(ans + 1, 0); sum[1] = a; sum[2] = a + 1; bool loc = true; for (int i = 3; i <= ans; ++i) { for (int j = 1; j < i; ++j) { sum[i] += sum[j]; if (sum[i] > b) { loc = false; break; } } sum[i]++; if (sum[i] > b) loc = false; if (!loc) break; } if (!loc) continue; vector<ll> v(ans + 1, 1); for (int i = 2; i <= ans; ++i) { ll l = 0, r = m; for (int j = 0; j < 50; ++j) { ll mm = (l + r) / 2; if (i == ans) { if (sum[ans] + mm > b) r = mm; else l = mm; } else { if (sum[ans] + mm * (1LL << (ans - (i + 1LL))) > b) r = mm; else l = mm; } } v[i] += l; if (i == ans) sum[ans] += l; else sum[ans] += (l * (1LL << (ans - (i + 1LL)))); } if (sum[ans] > b) break; if (sum[ans] == b) { cout << ans << ; ll curr = a; vector<ll> res(ans + 1, 0); res[1] = a; for (int i = 2; i <= ans; ++i) { for (int j = 1; j < i; ++j) res[i] += res[j]; res[i] += v[i]; } for (int i = 1; i <= ans; ++i) cout << res[i] << ; cout << n ; poss = true; break; } } if (!poss) cout << -1 << n ; } return 0; }
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#include <bits/stdc++.h> long long a[10000]; using namespace std; int main() { long long n, i, j, c; cin >> n; for (i = 1; i < n + 1; i++) cin >> a[i]; for (i = 1; i < n + 1; i++) { for (j = i + 1; j < n + 1; j++) { if (a[i] > a[j]) { c = a[i]; a[i] = a[j]; a[j] = c; } } } i = 1; while ((a[i] == 0) && (i < n + 1)) i++; int rez = 0; j = i; while ((a[j] != a[j + 2]) && (j < n)) { if (a[j] == a[j + 1]) rez++; j++; } if (i == n + 1) cout << rez; else { if (j == n) cout << rez; else cout << -1; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> T prod(const T &a, const T &b, const T &mod) { return ((a % mod) * (b % mod)) % mod; } template <typename T> T pow_(const T &a, const T &b) { if (!b) return 1; T p = pow_(a, b / 2); p *= p; return (b % 2) ? (p * a) : p; } template <typename T> T modpow(const T &a, const T &b, const T &mod) { if (!b) return 1; T p = modpow(a, b / 2); p = prod(p, p); return (b % 2) ? (prod(p, a)) : p; } template <typename T> T max(const T &a, const T &b, const T &c) { return max(a, max(b, c)); } template <typename T> T min(const T &a, const T &b, const T &c) { return min(a, min(b, c)); } template <typename T> void dbg(const vector<T> &a, int l, int r) { for (long long int i = l; i <= r; i++) cout << a[i] << ; cout << endl; } template <typename T> void dbg(const vector<T> &a) { for (long long int i = 0; i <= a.size() - 1; i++) cout << a[i] << ; cout << endl; } void main_() { long long int n; cin >> n; vector<long long int> a(n + 1, 0); for (long long int i = 1; i <= n; i++) { cin >> a[i]; a[i] += a[i - 1]; } long long int x, y, z; long long int res = -LLONG_MAX; for (long long int i = 0; i <= n; i++) { long long int m1 = -LLONG_MAX, m2 = -LLONG_MAX; long long int y_, x_, z_; y_ = i; for (long long int j = 0; j <= i; j++) { if (m1 < a[j]) { m1 = a[j]; x_ = j; } } for (long long int j = i; j <= n; j++) { if (m2 < a[j]) { m2 = a[j]; z_ = j; } } long long int sum = 2 * (a[x_] + a[z_] - a[y_]) - a[n]; if (res < sum) { res = sum; x = x_; y = y_; z = z_; } } cout << x << << y << << z << endl; } int main() { { main_(); } return 0; }
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#include <bits/stdc++.h> using namespace std; using int64 = long long; using pii = pair<int, int>; using vchar = vector<char>; using vvchar = vector<vchar>; using vint = vector<int>; using vint64 = vector<int64>; using vvint = vector<vint>; using vbool = vector<bool>; using vpii = vector<pii>; template <typename T> T sqr(T x) { return x * x; } template <typename T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } pair<int, vint> solveD(vvint g, int k) { enum { NOT_VISITED, STARTED, FINISHED }; const int n = g.size(); vint depth(n, -1); depth[0] = 0; vint parent(n, -1); vint loopState(n, NOT_VISITED); pair<int, vint> result; result.first = 0; std::function<void(int)> DFS = [&](int v) { loopState[v] = STARTED; const int previous = parent[v]; if (result.first != 0) return; int backVertex = -1; int backDepth = -1; for (auto to : g[v]) { if (to == previous) continue; if (loopState[to] == STARTED && depth[to] > backDepth) { backVertex = to; backDepth = depth[to]; } } if (backVertex != -1) { vint loop; for (int u = v; u != backVertex; u = parent[u]) { loop.push_back(u); } loop.push_back(backVertex); reverse(std::begin(loop), std::end(loop)); assert(depth[v] - depth[backVertex] + 1 == loop.size()); const int loopLength = loop.size(); if (loopLength > k) { result.first = 1; for (int i = 0; i < loop.size(); i += 2) { result.second.push_back(loop[i]); } result.second.resize((k + 1) / 2); } else { result.first = 2; result.second = loop; } return; } for (auto to : g[v]) { if (loopState[to] == NOT_VISITED) { parent[to] = v; depth[to] = depth[v] + 1; DFS(to); if (result.first != 0) return; } } loopState[v] = FINISHED; }; DFS(0); if (result.first != 0) { return result; } vint colors(n, -1); std::function<void(int, int)> biColor = [&](int v, int color) { colors[v] = color; for (auto to : g[v]) { if (colors[to] == -1) { biColor(to, 1 - color); } } }; biColor(0, 0); int colorCount[2] = {0}; for (int i = 0; i < n; ++i) { colorCount[colors[i]]++; } const int bestColor = colorCount[0] > colorCount[1] ? 0 : 1; result.first = 1; for (int i = 0; i < n; ++i) { if (colors[i] == bestColor) { result.second.push_back(i); } } result.second.resize((k + 1) / 2); return result; } int main() { int T = 1; std::ios::sync_with_stdio(false); while (T--) { int n; cin >> n; ; int m; cin >> m; ; int k; cin >> k; ; vvint g(n); while (m--) { int u; cin >> u; ; int v; cin >> v; ; u--, v--; g[u].push_back(v); g[v].push_back(u); } auto result = solveD(g, k); assert(result.first == 1 || result.first == 2); cout << result.first << endl; for (int& v : result.second) { v++; } if (result.first == 2) { cout << result.second.size() << endl; } std::copy(std::begin(result.second), std::end(result.second), ostream_iterator<int>(cout, )); cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int MAX = 1000000007; const long long int MAXN = 100010; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; if (n % 2 == 0 && k % 2 == 1) cout << NO << endl; else if (n % 2 == 1 && k % 2 == 0) cout << NO << endl; else { if (k * k <= n) cout << YES << endl; else cout << NO << endl; } } return 0; }
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#include <bits/stdc++.h> const long long _INF = 1e18; const int INF = 1e9; using namespace std; int T; void solved() { long long n = 0; cin >> n; if (n % 2 == 1) n++; if (n <= 6) cout << 15 << n ; else cout << n * 5 / 2 << n ; } int main() { setbuf(stdout, NULL); ios::sync_with_stdio(0); cin.tie(0); cin >> T; for (int i = 0; i < (T); i++) { solved(); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e7 + 5; const int maxm = 2e5 + 5; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const double eps = 1e-9; const double pi = acos(-1); int m, n, w, k; void init() {} bool judge(int now) {} long long quickpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } char c[1005]; int main() { int t; scanf( %d , &t); while (t--) { scanf( %d , &n); scanf( %s , c); int first = -1, second = -1; for (int i = 0; i < n; i++) if (c[i] == 1 ) { first = i + 1; break; } for (int i = n - 1; i >= 0; i--) if (c[i] == 1 ) { second = i + 1; break; } if (first == -1) printf( %d n , n); else printf( %d n , 2 * max(second, n - first + 1)); } }
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SD_DAT (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire bidir_port;
wire clk_en;
reg data_dir;
wire data_in;
reg data_out;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign bidir_port = data_dir ? data_out : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata;
end
endmodule
|
#include <bits/stdc++.h> const int MAX_N = 500000; const int MAX_M = 500000; const int MOD = 998244353; int l[MAX_M], r[MAX_M], val[MAX_M]; int smen[1 + MAX_N + 1], left[1 + MAX_N], dp[1 + MAX_N], _sp[1 + 1 + MAX_N], *sp = _sp + 1; int solve(int n, int m, int bit) { int last = 0, p = 0; for (int i = 1; i <= n; ++i) { smen[i] = 0; left[i] = 0; } smen[n + 1] = left[n + 1] = 0; for (int i = 0; i < m; ++i) if ((1 << bit) & val[i]) { smen[l[i]]++; smen[r[i] + 1]--; } else left[r[i] + 1] = std::max(left[r[i] + 1], l[i]); sp[0] = 1; dp[0] = 1; for (int i = 1; i <= n + 1; ++i) { p += smen[i]; last = std::max(last, left[i]); if (p == 0) { dp[i] = (sp[i - 1] + MOD - sp[last - 1]) % MOD; } else dp[i] = 0; sp[i] = (sp[i - 1] + dp[i]) % MOD; } return dp[n + 1]; } int main() { int n, k, m; scanf( %d%d%d , &n, &k, &m); for (int i = 0; i < m; ++i) scanf( %d%d%d , &l[i], &r[i], &val[i]); int res = 1; for (int i = 0; i < k; ++i) res = (long long)res * solve(n, m, i) % MOD; printf( %d , res); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD0_TB_V
`define SKY130_FD_SC_LP__BUSHOLD0_TB_V
/**
* bushold0: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates internal node weak driver).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold0.v"
module top();
// Inputs are registered
reg RESET;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
RESET = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 RESET = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 RESET = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 RESET = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 RESET = 1'bx;
end
sky130_fd_sc_lp__bushold0 dut (.RESET(RESET), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD0_TB_V
|
#include <bits/stdc++.h> int main() { unsigned short n; unsigned short ac1; unsigned short i; unsigned short w; unsigned short ac2; unsigned short gw; if (scanf( %hu , &n) != 1) return -1; if (n < 1 || n > 100) return -1; ac1 = 0; for (i = 0; i < n; i++) { if (scanf( %hu , &w) != 1) return -1; if (w != 100 && w != 200) return -1; if (w == 100) ac1++; } ac2 = n - ac1; gw = 50 * (ac1 + 2 * ac2); if (!(gw % 200) || (!(gw % 100) && ac1)) printf( YES n ); else printf( NO n ); return 0; }
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_8 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5,
read_6,
write_6,
EN_write_6,
read_7,
write_7,
EN_write_7
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
output [DATA_SZ-1:0] read_6;
input [DATA_SZ-1:0] write_6;
input EN_write_6;
output [DATA_SZ-1:0] read_7;
input [DATA_SZ-1:0] write_7;
input EN_write_7;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
wire [DATA_SZ-1:0] wire_7;
wire [DATA_SZ-1:0] wire_8;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign wire_7 = EN_write_6 ? write_6 : wire_6;
assign wire_8 = EN_write_7 ? write_7 : wire_7;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
assign read_6 = wire_6;
assign read_7 = wire_7;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_8;
end
end
endmodule
|
#include <bits/stdc++.h> const int mod = 1000000007; using namespace std; pair<int, int> a[12345]; vector<int> ans[3]; map<pair<int, int>, bool> used; map<int, int> cnts; int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( %d , &a[i].first); a[i].second = i + 1; cnts[a[i].first]++; } int x = 0, y = 0; for (map<int, int>::iterator it = cnts.begin(); it != cnts.end(); ++it) { if (it->second >= 3) y++; else { if (it->second == 2) { x++; } } } if (x >= 2 || y >= 1) { puts( YES ); sort(a, a + n); for (int i = 0; i < n; ++i) { ans[0].push_back(a[i].second); if (i != n) { used[make_pair(i, i + 1)] = false; used[make_pair(i + 1, i)] = false; } } int temp; for (int i = 0; i < n - 1; ++i) { if (!used[make_pair(i, i + 1)] && a[i].first == a[i + 1].first) { temp = a[i].second; a[i].second = a[i + 1].second; a[i + 1].second = temp; used[make_pair(i, i + 1)] = true; used[make_pair(i + 1, i)] = true; break; } } for (int i = 0; i < n; ++i) { ans[1].push_back(a[i].second); } for (int i = 0; i < n - 1; ++i) { if (!used[make_pair(i, i + 1)] && a[i].first == a[i + 1].first) { temp = a[i].second; a[i].second = a[i + 1].second; a[i + 1].second = temp; used[make_pair(i, i + 1)] = true; used[make_pair(i + 1, i)] = true; break; } } for (int i = 0; i < n; ++i) { ans[2].push_back(a[i].second); } for (int i = 0; i < 3; ++i) { for (int j = 0; j < ans[i].size(); ++j) { printf( %d , ans[i][j]); } printf( n ); } } else { cout << NO << endl; return 0; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2111O_2_V
`define SKY130_FD_SC_HD__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2111O_2_V
|
#include <bits/stdc++.h> using namespace std; int n, m, a[200010], w[200010], f[3010][3010], g[3010][3010], inv[3010 * 2], sum[3]; const int mod = 998244353; int getInverse(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = (long long)ret * x % mod; x = (long long)x * x % mod; y >>= 1; } return ret; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= n; ++i) { cin >> w[i]; sum[a[i]] += w[i]; sum[2] += w[i]; } for (int i = max(0, m - sum[0]); i <= 2 * m; ++i) inv[i] = getInverse(sum[2] + i - m, mod - 2); for (int i = m; i >= 0; --i) { f[i][m - i] = g[i][m - i] = 1; for (int j = min(m - i - 1, sum[0]); j >= 0; --j) { f[i][j] = ((long long)(sum[1] + i + 1) * f[i + 1][j] + (long long)(sum[0] - j) * f[i][j + 1]) % mod * inv[i - j + m] % mod; g[i][j] = ((long long)(sum[1] + i) * g[i + 1][j] + (long long)(sum[0] - j - 1) * g[i][j + 1]) % mod * inv[i - j + m] % mod; } } for (int i = 1; i <= n; ++i) cout << ((long long)w[i] * (a[i] ? f[0][0] : g[0][0])) % mod << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct rua { char s[100001]; int n, a[100001], b[100001], x, y; void _() { int cnt = 0; for (int i = 1; i <= n; i++) if (s[i] == A ) a[i] = ++cnt, b[i] = b[i - 1]; else a[i] = cnt = 0, b[i] = b[i - 1] + 1; } void get(int l, int r) { x = b[r] - b[l - 1]; if (!x) y = r - l + 1; else y = a[r]; } } s, t; int Q, a, b, c, d; int main() { scanf( %s , s.s + 1), s.n = strlen(s.s + 1); scanf( %s , t.s + 1), t.n = strlen(t.s + 1); s._(), t._(); scanf( %d , &Q); while (Q--) { scanf( %d%d%d%d , &a, &b, &c, &d); s.get(a, b), t.get(c, d); if (!s.x && t.x) if (s.y > t.y) s.x += 2, s.y = t.y; else s.y--; if (s.y < t.y) { printf( 0 ); continue; } if ((s.y - t.y) % 3) s.x += 2; if (s.x > t.x || (t.x - s.x) & 1) { printf( 0 ); continue; } printf( 1 ); } return printf( n ), 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110, MOD = 1e9 + 7; long long dp[MAXN][2]; int main() { ios_base::sync_with_stdio(NULL); cin.tie(nullptr); cout.tie(nullptr); int n, k, d; cin >> n >> k >> d; dp[0][0] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= min(k, i); j++) { if (j >= d) { dp[i][1] += (dp[i - j][0] + dp[i - j][1]); dp[i][1] %= MOD; } else { dp[i][0] += dp[i - j][0]; dp[i][1] += dp[i - j][1]; dp[i][1] %= MOD; dp[i][0] %= MOD; } } } cout << dp[n][1] << n ; }
|
#include <bits/stdc++.h> const int mod = 200003; const int gmod = 2; const int inf = 1039074182; const long long llinf = 1LL * inf * inf; template <typename T1, typename T2> inline void chmin(T1 &x, T2 b) { if (b < x) x = b; } template <typename T1, typename T2> inline void chmax(T1 &x, T2 b) { if (b > x) x = b; } template <typename T1, typename T2> inline void chadd(T1 &x, T2 b) { x += b; if (x >= mod) x -= mod; } template <typename T1, typename T2> inline void chmul(T1 &x, T2 b) { x = 1LL * x * b % mod; } template <typename T1, typename T2> inline void chmod(T1 &x, T2 b) { x %= b, x += b; if (x >= b) x -= b; } using namespace std; template <typename T> ostream &operator<<(ostream &cout, vector<T> vec) { cout << { ; for (int i = 0; i < vec.size(); i++) { cout << vec[i]; if (i != (int)vec.size() - 1) cout << , ; } cout << } ; return cout; } template <typename T1, typename T2> ostream &operator<<(ostream &cout, pair<T1, T2> p) { cout << ( << p.first << , << p.second << ) ; return cout; } template <typename T> ostream &operator<<(ostream &cout, set<T> s) { vector<T> t; for (auto x : s) t.push_back(x); cout << t; return cout; } template <typename T> ostream &operator<<(ostream &cout, queue<T> q) { vector<T> t; while (q.size()) { t.push_back(q.front()); q.pop(); } cout << t; return cout; } template <typename T1, typename T2> ostream &operator<<(ostream &cout, map<T1, T2> m) { for (auto &x : m) { cout << Key: << x.first << << Value: << x.second << endl; } return cout; } template <typename T> T operator*(vector<T> v1, vector<T> v2) { assert(v1.size() == v2.size()); int n = v1.size(); T res = 0; for (int i = 0; i < n; i++) { res += v1[i] * v2[i]; } return res; } template <typename T1, typename T2> pair<T1, T2> operator+(pair<T1, T2> x, pair<T1, T2> y) { return make_pair(x.first + y.first, x.second + y.second); } template <typename T1, typename T2> pair<T1, T2> operator-(pair<T1, T2> x) { return make_pair(-x.first, -x.second); } template <typename T> vector<vector<T> > operator~(vector<vector<T> > vec) { vector<vector<T> > v; int n = vec.size(), m = vec[0].size(); v.resize(m); for (int i = 0; i < m; i++) { v[i].resize(n); } for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { v[i][j] = vec[j][i]; } } return v; } void print0x(int x) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } std::reverse(vec.begin(), vec.end()); for (int i = 0; i < vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } template <typename T> void print0x(T x, int len) { std::vector<int> vec; while (x) { vec.push_back(x & 1); x >>= 1; } reverse(vec.begin(), vec.end()); for (int i = vec.size(); i < len; i++) { putchar( 0 ); } for (int i = 0; i < vec.size(); i++) { std::cout << vec[i]; } std::cout << ; } using namespace std; const int basic = 500000; int n; int a[300005], b[300005]; char buf[500005]; vector<int> sum[basic * 2 + 5]; int m1, m2, m3, m4; int b1, b2; int besta, bestb; int best; inline void calc(int k) { int res = 0; chmax(res, b1); chmax(res, b2); int zx = max(m2, m3); int nx = max(m1, m4); int tx = (nx - zx) / 2; chmax(tx, 0); chmax(res, -tx + nx); if (res < best) { best = res; besta = tx; if (besta == 0 && k == 0) besta++; bestb = besta + k; } } inline void read(int &a, int &b) { a = 0; b = 0; char c = 0; while (c != N && c != B ) c = getchar(); while (c == N || c == B ) { if (c == B ) b++; else a++; c = getchar(); } } int main() { cin >> n; m1 = -inf, m2 = -inf, m3 = -inf, m4 = -inf; b1 = -inf, b2 = -inf; int k = basic; for (int i = 0; i < n; i++) { read(a[i], b[i]); sum[b[i] - a[i] + basic].push_back(i); chmax(b2, a[i] + k - b[i]); chmax(m3, k - b[i]); chmax(m4, a[i]); } best = inf; calc(basic); for (k = basic - 1; k >= -basic; k--) { m1++; b1++; m3--; b2--; for (auto id : sum[k + basic]) { int x0 = a[id]; int y0 = b[id]; chmax(m1, y0 - k); chmax(m2, -x0); chmax(b1, y0 - (x0 + k)); } calc(k); } cout << best << endl; for (int i = 0; i < bestb; i++) { putchar( B ); } for (int i = 0; i < besta; i++) { putchar( N ); } return 0; }
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// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the Audio DAC on the Altera DE2 board. *
* *
******************************************************************************/
module altera_up_audio_out_serializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
left_channel_data,
left_channel_data_en,
right_channel_data,
right_channel_data_en,
// Bidirectionals
// Outputs
left_channel_fifo_write_space,
right_channel_fifo_write_space,
serial_audio_out_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input [DW: 0] left_channel_data;
input left_channel_data_en;
input [DW: 0] right_channel_data;
input right_channel_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] left_channel_fifo_write_space;
output reg [ 7: 0] right_channel_fifo_write_space;
output reg serial_audio_out_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_left_channel;
wire read_right_channel;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [ 6: 0] left_channel_fifo_used;
wire [ 6: 0] right_channel_fifo_used;
wire [DW: 0] left_channel_from_fifo;
wire [DW: 0] right_channel_from_fifo;
// Internal Registers
reg left_channel_was_read;
reg [DW: 0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_fifo_write_space <= 8'h00;
else
left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_channel_fifo_write_space <= 8'h00;
else
right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_audio_out_data <= 1'b0;
else
serial_audio_out_data <= data_out_shift_reg[DW];
end
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_was_read <= 1'b0;
else if (read_left_channel)
left_channel_was_read <= 1'b1;
else if (read_right_channel)
left_channel_was_read <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= 'h0;
else if (read_left_channel)
data_out_shift_reg <= left_channel_from_fifo;
else if (read_right_channel)
data_out_shift_reg <= right_channel_from_fifo;
else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
data_out_shift_reg <= 'h0;
else if (bit_clk_falling_edge)
data_out_shift_reg <=
{data_out_shift_reg[(DW - 1):0], 1'b0};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_left_channel = left_right_clk_rising_edge &
~left_channel_fifo_is_empty &
~right_channel_fifo_is_empty;
assign read_right_channel = left_right_clk_falling_edge &
left_channel_was_read;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_sync_fifo Audio_Out_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_channel_data_en & ~left_channel_fifo_is_full),
.write_data (left_channel_data),
.read_en (read_left_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_from_fifo)
);
defparam
Audio_Out_Left_Channel_FIFO.DW = DW,
Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Left_Channel_FIFO.AW = 6;
altera_up_sync_fifo Audio_Out_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (right_channel_data_en & ~right_channel_fifo_is_full),
.write_data (right_channel_data),
.read_en (read_right_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_from_fifo)
);
defparam
Audio_Out_Right_Channel_FIFO.DW = DW,
Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Right_Channel_FIFO.AW = 6;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long long n, arr[100000], arr1[100000]; cin >> n; string s = ; for (int x = 0; x < n; x++) cin >> arr[x], arr1[x] = arr[x]; sort(arr1, arr1 + n); for (int x = 0; x <= arr1[n - 1]; x++) { for (int y = 0; y < n - 1; y++) { if (arr[y] != 0) s += P , arr[y]--; s += R ; } for (int z = n - 1; z > 0; z--) { if (arr[z] != 0) s += P , arr[z]--; s += L ; } } for (int x = s.size(); x >= 0; x--) if (s[x] == P ) { s.erase(x + 1, s.size()); break; } cout << s; return 0; }
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#include <bits/stdc++.h> using namespace std; signed long long int a[100000 + 5], b[100000 + 5]; int n, m; signed long long int func(signed long long int x) { signed long long int ans = 0; for (int i = 1; i <= n; ++i) { if (a[i] < x) ans += x - a[i]; } for (int i = 1; i <= m; ++i) { if (x < b[i]) ans += b[i] - x; } return ans; } signed long long int ter(signed long long int i, signed long long int j) { if (i == j) return i; if (j - i == 2) { signed long long int mi = j - 1; if (func(mi) < func(i) && func(mi) < func(j)) return mi; if (func(i) < func(j) && func(i) < func(mi)) return i; return j; } signed long long int l, r; l = i + (j - i) / 3; r = j - (j - i) / 3; if (func(l) > func(r)) return ter(l, j); else return ter(i, r); } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) cin >> b[i]; cout << func(ter(0, 2 * 1000000007 + 1)); }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k, a[105], nr = 0, poz = 0; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (a[i] <= k) nr++; else { poz = i; break; } } if (poz || nr == 0) for (int i = n - 1; i > poz; i--) if (a[i] <= k) nr++; else break; cout << nr; }
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: linetest.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To test that the txuart and rxuart modules work properly, by
// buffering one line's worth of input, and then piping that line
// to the transmitter while (possibly) receiving a new line.
//
// With some modifications (discussed below), this RTL should be able to
// run as a top-level testing file, requiring only the transmit and receive
// UART pins and the clock to work.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
// }}}
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// {{{
//
// Two versions of the UART can be found in the rtl directory: a full featured
// UART, and a LITE UART that only handles 8N1 -- no break sending, break
// detection, parity error detection, etc. If we set USE_LITE_UART here, those
// simplified UART modules will be used.
// }}}
// `define USE_LITE_UART
//
`default_nettype none
//
module linetest(
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
input i_uart_rx,
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg [7:0] buffer [0:255];
reg [7:0] head, tail;
reg pwr_reset;
wire rx_stb, rx_break, rx_perr, rx_ferr;
/* verilator lint_off UNUSED */
wire rx_ignored;
/* verilator lint_on UNUSED */
wire [7:0] rx_data;
wire [7:0] nxt_head;
wire [7:0] nused;
reg [7:0] lineend;
reg run_tx;
wire tx_break, tx_busy;
reg [7:0] tx_data;
reg tx_stb;
wire cts_n;
// }}}
// i_setup
// {{{
// If i_setup isnt set up as an input parameter, it needs to be set.
// We do so here, to a setting appropriate to create a 115200 Baud
// comms system from a 100MHz clock. This also sets us to an 8-bit
// data word, 1-stop bit, and no parity.
`ifdef OPT_STANDALONE
wire [30:0] i_setup;
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
`endif
// }}}
// pwr_reset
// {{{
// Create a reset line that will always be true on a power on reset
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// The UART Receiver
// {{{
// This is where everything begins, by reading data from the UART.
//
// Data (rx_data) is present when rx_stb is true. Any parity or
// frame errors will also be valid at that time. Finally, we'll ignore
// errors, and even the clocked uart input distributed from here.
`ifdef USE_LITE_UART
rxuartlite #(24'd868)
receiver(i_clk, i_uart_rx, rx_stb, rx_data);
`else
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
rx_break, rx_perr, rx_ferr, rx_ignored);
`endif
// }}}
// nxt_head, and write to the buffer
// {{{
// The next step in this process is to dump everything we read into a
// FIFO. First step: writing into the FIFO. Always write into FIFO
// memory. (The next step will step the memory address if rx_stb was
// true ...)
assign nxt_head = head + 8'h01;
always @(posedge i_clk)
buffer[head] <= rx_data;
// }}}
// head
// {{{
// Select where in our FIFO memory to write. On reset, we clear the
// memory. In all other cases/respects, we step the memory forward.
//
// However ... we won't step it forward IF ...
// rx_break - we are in a BREAK condition on the line
// (i.e. ... it's disconnected)
// rx_perr - We've seen a parity error
// rx_ferr - Same thing for a frame error
// nxt_head != tail - If the FIFO is already full, we'll just drop
// this new value, rather than dumping random garbage
// from the FIFO until we go round again ... i.e., we
// don't write on potential overflow.
//
// Adjusting this address will make certain that the next write to the
// FIFO goes to the next address--since we've already written the FIFO
// memory at this address.
initial head= 8'h00;
always @(posedge i_clk)
if (pwr_reset)
head <= 8'h00;
else if ((rx_stb)&&(!rx_break)&&(!rx_perr)&&(!rx_ferr)&&(nxt_head != tail))
head <= nxt_head;
// }}}
// How much of the FIFO is in use? head - tail. What if they wrap
// around? Still: head-tail, but this time truncated to the number of
// bits of interest. It can never be negative ... so ... we're good,
// this just measures that number.
assign nused = head-tail;
// run_tx, lineend
// {{{
// Here's the guts of the algorithm--setting run_tx. Once set, the
// buffer will flush. Here, we set it on one of two conditions: 1)
// a newline is received, or 2) the line is now longer than 80
// characters.
//
// Once the line has ben transmitted (separate from emptying the buffer)
// we stop transmitting.
initial run_tx = 0;
initial lineend = 0;
always @(posedge i_clk)
if (pwr_reset)
begin
run_tx <= 1'b0;
lineend <= 8'h00;
end else if(((rx_data == 8'h0a)||(rx_data == 8'hd))&&(rx_stb))
begin
// Start transmitting once we get to either a newline
// or a carriage return character
lineend <= head+8'h1;
run_tx <= 1'b1;
end else if ((!run_tx)&&(nused>8'd80))
begin
// Start transmitting once we get to 80 chars
lineend <= head;
run_tx <= 1'b1;
end else if (tail == lineend)
// Line buffer has been emptied
run_tx <= 1'b0;
// }}}
// UART transmitter
// {{{
// Now ... let's deal with the transmitter
assign tx_break = 1'b0;
// When do we wish to transmit?
//
// Any time run_tx is true--but we'll give it an extra clock.
initial tx_stb = 1'b0;
always @(posedge i_clk)
tx_stb <= run_tx;
// We'll transmit the data from our FIFO from ... wherever our tail
// is pointed.
always @(posedge i_clk)
tx_data <= buffer[tail];
// We increment the pointer to where we read from any time 1) we are
// requesting to transmit a character, and 2) the transmitter was not
// busy and thus accepted our request. At that time, increment the
// pointer, and we'll be ready for another round.
initial tail = 8'h00;
always @(posedge i_clk)
if(pwr_reset)
tail <= 8'h00;
else if ((tx_stb)&&(!tx_busy))
tail <= tail + 8'h01;
// Bypass any hardwaare flow control
assign cts_n = 1'b0;
`ifdef USE_LITE_UART
txuartlite #(24'd868)
transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
`else
txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
`endif
// }}}
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int t, x; cin >> t; while (t--) { cin >> x; while (x > 0) { if (x % 3 == 0) x = x % 3; else if (x % 7 == 0) x = x % 7; else { x -= 7; x -= 3; } } if (x == 0) cout << YES << endl; else cout << NO << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_SYMBOL_V
`define SKY130_FD_SC_MS__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_SYMBOL_V
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#include <bits/stdc++.h> using namespace std; int main() { int i, n, x, y, c; cin >> n >> x >> y; int a[n]; for (i = 0; i < n; i++) cin >> a[i]; if (x > y) cout << n << endl; else { c = 0; for (i = 0; i < n; i++) if (a[i] <= x) c++; if (c % 2 == 1) c = c / 2 + 1; else c /= 2; cout << c << endl; } }
|
#include <bits/stdc++.h> using namespace std; int L, R; int main() { int n, m, i, j, u, v; cin >> n >> m; int ans = 100001; for (i = 0; i < m; i++) { scanf( %d%d , &L, &R); ans = min(ans, R - L + 1); } cout << ans << endl; for (i = 1; i <= n; i++) cout << i % ans << ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_BLACKBOX_V
`define SKY130_FD_SC_HD__OR3B_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct HashMap { vector<pair<int, int> > g[1000007]; void ins(int x, int y) { int id = ((long long)x * 1000000007 + y) % 1000007; g[id].push_back(make_pair(x, y)); } bool get(int x, int y) { int id = ((long long)x * 1000000007 + y) % 1000007; for (int i = 0; i < g[id].size(); i++) if (g[id][i].first == x && g[id][i].second == y) return true; return false; } }; int n; HashMap mp; vector<int> row[100011]; vector<int> rateB; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); row[y].push_back(x); mp.ins(x, y); } int di = (int)sqrt(n); long long int ans = 0; for (int a = 0; a <= 100000; a++) { if (row[a].size() != 0) { sort(row[a].begin(), row[a].end()); if (row[a].size() <= di) { for (int i = 0; i < row[a].size(); i++) { for (int j = i + 1; j < row[a].size(); j++) { int x1 = row[a][i]; int x2 = row[a][j]; int dis = x2 - x1; if (mp.get(x1, a + dis) && mp.get(x2, a + dis)) ans++; if (a - dis >= 0 && row[a - dis].size() > di && (mp.get(x1, a - dis) && mp.get(x2, a - dis))) ans++; } } } else rateB.push_back(a); } } for (int i = 0; i < rateB.size(); i++) { for (int j = i + 1; j < rateB.size(); j++) { int a = rateB[i]; int b = rateB[j]; int u = 0, p = 0; int dis = b - a; while (u < row[a].size() && p < row[b].size()) { if (row[a][u] < row[b][p]) u++; else if (row[a][u] > row[b][p]) p++; else { int x1 = row[a][u]; if (mp.get(x1 + dis, a) && mp.get(x1 + dis, b)) ans++; u++; p++; } } } } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, m, in[N], out[N], id[N], dep[N]; vector<int> v[N]; int idx; void dfs(int pos, int dd) { in[pos] = ++idx; id[idx] = pos; dep[idx] = dd; for (auto &i : v[pos]) dfs(i, dd + 1); out[pos] = ++idx; id[idx] = pos; dep[idx] = dd; } int fa[N], ch[N][2], mn[N], mx[N], val[N], sz[N]; inline void pushup(int x) { sz[x] = sz[ch[x][0]] + sz[ch[x][1]] + 1; mn[x] = mx[x] = dep[x]; mn[x] = min({mn[x], mn[ch[x][0]], mn[ch[x][1]]}); mx[x] = max({mx[x], mx[ch[x][0]], mx[ch[x][1]]}); } int build(int l, int r) { int mid = (l + r) >> 1, x = mid; if (l < mid) ch[x][0] = build(l, mid - 1), fa[ch[x][0]] = x; if (mid < r) ch[x][1] = build(mid + 1, r), fa[ch[x][1]] = x; pushup(x); return x; } inline void push(int x, int v) { val[x] += v; dep[x] += v; mn[x] += v; mx[x] += v; } inline void pushdown(int x) { if (val[x]) { if (ch[x][0]) push(ch[x][0], val[x]); if (ch[x][1]) push(ch[x][1], val[x]); val[x] = 0; } } inline bool sd(int x) { return ch[fa[x]][1] == x; } void rotate(int x) { int y = fa[x], z = fa[y], k = sd(x); if (z) ch[z][sd(y)] = x; fa[x] = z; fa[y] = x; if (ch[x][!k]) fa[ch[x][!k]] = y; ch[y][k] = ch[x][!k]; ch[x][!k] = y; pushup(y); pushup(x); } void splay(int x, int target = 0) { static int stk[N], ptr; stk[ptr = 1] = x; int tmp = x; while (fa[tmp] != target) stk[++ptr] = tmp = fa[tmp]; while (ptr) pushdown(stk[ptr--]); while (fa[x] != target) { int y = fa[x]; if (fa[y] != target) rotate(sd(x) == sd(y) ? y : x); rotate(x); } pushup(x); } int kth(int x, int kk) { pushdown(x); if (mn[ch[x][1]] <= kk && mx[ch[x][1]] >= kk) return kth(ch[x][1], kk); if (dep[x] == kk) { splay(x); return id[x]; } return kth(ch[x][0], kk); } inline int split(int l, int r) { splay(l); splay(r, l); return ch[r][0]; } int pre(int x) { splay(x); x = ch[x][0]; while (ch[x][1]) x = ch[x][1]; splay(x); return x; } int suf(int x) { splay(x); x = ch[x][1]; while (ch[x][0]) x = ch[x][0]; splay(x); return x; } int erase(int l, int r) { int lp = pre(l), rp = suf(r), p = split(lp, rp), v = fa[p]; ch[v][0] = fa[p] = 0; return p; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; i++) { int kk; cin >> kk; v[i].resize(kk); for (int j = 0; j < kk; j++) cin >> v[i][j]; } mn[0] = INT_MAX >> 1; dfs(1, 0); build(1, idx); while (m--) { int op; cin >> op; if (op == 1) { int t1, t2; cin >> t1 >> t2; splay(in[t1]); int rk1 = sz[ch[in[t1]][0]] + 1, ans = dep[in[t1]]; splay(in[t2]); int rk2 = sz[ch[in[t2]][0]] + 1; ans += dep[in[t2]]; if (rk1 > rk2) swap(t1, t2); t1 = split(in[t1], out[t2]); ans -= (mn[t1] - 1) * 2; cout << ans << endl; } else if (op == 2) { int t1, t2; cin >> t1 >> t2; int val = t2 - 1; splay(in[t1]); t2 = kth(ch[in[t1]][0], dep[in[t1]] - t2); t1 = erase(in[t1], out[t1]); push(t1, -val); int xx = pre(out[t2]); splay(xx); splay(out[t2], xx); ch[out[t2]][0] = t1; fa[t1] = out[t2]; pushup(out[t2]); pushup(xx); } else { int k; cin >> k; splay(1); cout << kth(1, k) << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> yarr(51, 0); vector<int> xarr(51, 0); int q = 4 * n + 1; vector<pair<int, int>> trav; for (int i = 0; i < q; i++) { int x, y; cin >> x >> y; trav.push_back(make_pair(x, y)); xarr[x]++; yarr[y]++; } int maxy = 0; int maxx = 0; int minx = 1000, miny = 1000; int indexx = 0, indexy = 0; for (int i = 0; i < 51; i++) { if (yarr[i] >= n && i > maxy) { maxy = i; } if (xarr[i] >= n && i > maxx) { maxx = i; } if (yarr[i] >= n && i < miny) { miny = i; } if (xarr[i] >= n && i < minx) { minx = i; } } for (int i = 0; i < trav.size(); i++) { if (trav[i].first == minx && trav[i].second >= miny && trav[i].second <= maxy) continue; if (trav[i].first == maxx && trav[i].second >= miny && trav[i].second <= maxy) continue; if (trav[i].second == miny && trav[i].first >= minx && trav[i].first <= maxx) continue; if (trav[i].second == maxy && trav[i].first >= minx && trav[i].first <= maxx) continue; cout << trav[i].first << << trav[i].second << n ; break; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, a, b; cin >> a >> b >> x; if (a >= b) { cout << 0 ; if (x % 2 == 0) { for (int i = 1; i < x / 2; i++) cout << 10 ; for (int i = 0; i <= b - x / 2; i++) cout << 1 ; for (int i = 1; i <= a - x / 2; i++) cout << 0 ; } if (x % 2 == 1) { for (int i = 1; i <= x / 2; i++) cout << 10 ; for (int i = 1; i < a - x / 2; i++) cout << 0 ; for (int i = 0; i < b - x / 2; i++) cout << 1 ; } } if (b > a) { cout << 1 ; if (x % 2 == 0) { for (int i = 1; i < x / 2; i++) cout << 01 ; for (int i = 0; i <= a - x / 2; i++) cout << 0 ; for (int i = 1; i <= b - x / 2; i++) cout << 1 ; } if (x % 2 == 1) { for (int i = 1; i <= x / 2; i++) cout << 01 ; for (int i = 1; i < b - x / 2; i++) cout << 1 ; for (int i = 0; i < a - x / 2; i++) cout << 0 ; } } return 0; }
|
// usb_ft232.v
`timescale 1 ns / 1 ps
module usb_ft232
(
input clk,
input reset,
// FT232 interface
output wr_n,
output rd_n,
output oe_n,
inout [7:0]data,
input txe_n,
input rxf_n,
output siwu_n,
// tx fifo interface
output tx_read,
input [15:0]tx_data,
input [1:0]tx_mask,
input tx_ready,
// rx fifo interface
output reg rx_write,
output reg [15:0]rx_data,
output reg rx_mask,
input rx_ready
);
// === transmitter ========================================================
wire tx_ena;
wire tx_wait;
wire tx_skip;
reg tx_upper;
wire tx_is_send = tx_ready && !tx_mask[0];
wire tx_is_16bit = tx_ready && tx_mask[1];
// tx_data -> data transfer; flow control with tx_ena & tx_wait
wire wr = !txe_n && tx_ready && tx_ena && !tx_is_send;
assign wr_n = !wr;
assign oe_n = !wr_n;
assign tx_read = (wr && !tx_wait) || tx_skip;
assign data = oe_n ? (tx_upper ? tx_data[15:8] : tx_data[7:0]) : 8'hzz;
assign tx_skip = tx_is_send;
// 16 bit transfer
always @(posedge clk or posedge reset)
begin
if (reset) tx_upper <= 0;
else if (wr) tx_upper = tx_is_16bit && !tx_upper;
end
assign tx_wait = tx_is_16bit && !tx_upper;
// send immediate
reg tx_si;
reg tx_siwu;
reg [4:0]send_delay;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
tx_si <= 0;
tx_siwu <= 0;
send_delay <= 0;
end
else
begin
if (tx_is_send && !tx_si) tx_si <= 1;
if (tx_si && (send_delay == 0)) tx_siwu <= 1;
if (tx_si && (send_delay == 16))
begin
tx_si <= 0;
tx_siwu <= 0;
end
if (tx_si || !(send_delay == 5'd0)) send_delay = send_delay + 5'b1;
end
end
assign siwu_n = !tx_siwu;
// === receiver ===========================================================
wire rx_ena;
wire rx_rd = !rxf_n && rx_ready && rx_ena;
reg rx_upper;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
rx_upper <= 0;
rx_mask <= 0;
rx_write <= 0;
rx_data <= 0;
end
else if (rx_ready)
begin
rx_upper <= !rx_upper && rx_rd;
rx_mask <= rx_upper && rx_rd;
rx_write <= rx_upper;
if (rx_rd && !rx_upper) rx_data[7:0] <= data;
if (rx_rd && rx_upper) rx_data[15:8] <= data;
end
end
assign rd_n = !rx_rd;
// === priority logic =====================================================
assign tx_ena = !tx_si;
assign rx_ena = !(tx_ready && !txe_n);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const double EPS = 1e-9; int n, m, t[210][210], d[210][210]; bool active[210]; vector<pair<int, int> > x_sorted; double calc(int x, int y) { double ans = INF; vector<pair<int, int> > s; multiset<int> up; int down = -INF; for (int i = 1; i <= n; i++) { int tmp = t[x][y] + d[y][i] - d[x][i]; active[i] = false; if (tmp < 0) down = max(down, t[x][y] + d[y][i]); else if (tmp > 2 * t[x][y]) { active[i] = true; } else { s.push_back(make_pair(tmp, i)); active[i] = true; } } active[0] = true; s.push_back(make_pair(0, -1)); s.push_back(make_pair(2 * t[x][y], -1)); sort(s.begin(), s.end()); int _x_sorted = 0; for (int i = 0; i + 1 < s.size(); i++) { if (s[i].second > -1) { active[s[i].second] = false; down = max(down, t[x][y] + d[y][s[i].second]); } while (!active[x_sorted[_x_sorted].second]) ++_x_sorted; int up_best = x_sorted[_x_sorted].first; int z = down - up_best; z = max(s[i].first, z); z = min(s[i + 1].first, z); ans = min(ans, max(up_best + 0.5 * z, down - 0.5 * z)); } return ans; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) t[i][j] = INF; while (m--) { int x, y, z; scanf( %d %d %d , &x, &y, &z); t[x][y] = t[y][x] = z; } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) d[i][j] = i == j ? 0 : t[i][j]; for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) d[i][j] = min(d[i][j], d[i][k] + d[k][j]); double ans = INF; for (int i = 1; i <= n; i++) { x_sorted.clear(); for (int j = 1; j <= n; j++) x_sorted.push_back(make_pair(d[i][j], j)); x_sorted.push_back(make_pair(-1, 0)); sort(x_sorted.begin(), x_sorted.end()); reverse(x_sorted.begin(), x_sorted.end()); for (int j = 1; j < i; j++) ans = min(ans, calc(i, j)); } printf( %.9lf n , ans); }
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100006]; vector<int> located[100006]; int parent[100006], level[100006], visited[100006]; int ancestor[100006][18]; vector<int> st[100006][18]; void dfs(int u) { visited[u] = 1; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (visited[v] == 0) { parent[v] = u; level[v] = level[u] + 1; dfs(v); } } } void merge(vector<int>& a, vector<int>& b) { sort(a.begin(), a.end()); sort(b.begin(), b.end()); vector<int> tmp; int cnt = 0; int l1 = a.size(), l2 = b.size(); int i = 0, j = 0; while (i < l1 && j < l2 && cnt < 10) { if (a[i] < b[j]) tmp.push_back(a[i++]); else tmp.push_back(b[j++]); cnt++; } while (i < l1 && cnt < 10) { tmp.push_back(a[i++]); cnt++; } while (j < l2 && cnt < 10) { tmp.push_back(b[j++]); cnt++; } a.clear(); for (i = 0; i < cnt; i++) a.push_back(tmp[i]); } int main() { int tc = 1; for (int t = 1; t <= tc; t++) { int n, m, q; scanf( %d , &(n)); scanf( %d , &(m)); scanf( %d , &(q)); for (int j = 1; j < 18; j++) { for (int i = 1; i <= n; i++) { ancestor[i][j] = -1; } } for (int i = 1; i < n; i++) { int u, v; scanf( %d , &(u)); scanf( %d , &(v)); g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= m; i++) { int tmp; scanf( %d , &(tmp)); located[tmp].push_back(i); } parent[1] = -1; level[1] = 1; dfs(1); for (int i = 1; i <= n; i++) ancestor[i][0] = parent[i]; for (int j = 1; j < 18; j++) { for (int i = 1; i <= n; i++) { if (ancestor[i][j - 1] != -1) ancestor[i][j] = ancestor[ancestor[i][j - 1]][j - 1]; } } for (int i = 1; i <= n; i++) { st[i][0] = located[i]; vector<int> vi; merge(st[i][0], vi); } for (int j = 1; j < 18; j++) { for (int i = 1; i <= n; i++) { st[i][j] = st[i][j - 1]; if (ancestor[i][j - 1] == -1) continue; merge(st[i][j], st[ancestor[i][j - 1]][j - 1]); } } while (q--) { int u, v, a; scanf( %d , &(u)); scanf( %d , &(v)); scanf( %d , &(a)); if (level[u] < level[v]) { int tmp = u; u = v; v = tmp; } vector<int> tmp; for (int j = 17; j >= 0; j--) { if (ancestor[u][j] != -1 && level[ancestor[u][j]] >= level[v]) { merge(tmp, st[u][j]); u = ancestor[u][j]; } } if (u != v) { for (int j = 17; j >= 0; j--) { if (ancestor[u][j] != -1 && ancestor[u][j] != ancestor[v][j]) { merge(tmp, st[u][j]); merge(tmp, st[v][j]); u = ancestor[u][j]; v = ancestor[v][j]; } } merge(tmp, st[u][0]); merge(tmp, st[v][0]); u = parent[u]; v = parent[v]; } merge(tmp, st[u][0]); int cnt = 0; int len = tmp.size(); cout << min(a, len); for (int it = 0; it < tmp.size() && cnt < a; it++, cnt++) { printf( ); printf( %d , (tmp[it])); } printf( n ); } } }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 2,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @ (posedge clk) begin
ce_r <= ce;
end
always @ (posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r?dout_i:dout_r;
endmodule
|
#include <bits/stdc++.h> const int N = 7 + 1e9; using namespace std; const int p = 1e6 + 10; int arr[p]; int power(int x, int y); void pre() { int j = 1; for (int i = 1; i < p; i++) { if (i % 3 != 0) { if (i % 10 != 3) { arr[j] = i; j++; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); pre(); long long T; cin >> T; while (T--) { long long n; cin >> n; cout << arr[n] << n ; } return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the add-compare
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules,
*/
`include "acs.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_acs();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [3:0] new_pm; // Output signal npm
wire decision; // Output signal d
// Declare "reg" signals: inputs to the DUT
reg [1:0] brch_m1; // Input signal - bm1
reg [1:0] brch_m2; // Input signal - bm2
reg [3:0] path_m1; // Input signal - pm1
reg [3:0] path_m2; // Input signal - pm2
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
add_compare_select acs_cir (
// instance_name(signal name),
// Signal name can be the same as the instance name
new_pm,decision,path_m1,brch_m1,path_m2,brch_m2);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
path_m1 = 4'd0;
brch_m1 = 2'd0;
path_m2 = 4'd0;
brch_m2 = 2'd0;
// @t=1,
#1
path_m1 = 4'd0;
brch_m1 = 2'd1;
path_m2 = 4'd6;
brch_m2 = 2'd2;
// @t=2,
#1
path_m1 = 4'd7;
brch_m1 = 2'd2;
path_m2 = 4'd0;
brch_m2 = 2'd3;
// @t=3,
#1
path_m1 = 4'd14;
brch_m1 = 2'd1;
path_m2 = 4'd13;
brch_m2 = 2'd0;
// @t=4,
#1
path_m1 = 4'd9;
brch_m1 = 2'd3;
path_m2 = 4'd8;
brch_m2 = 2'd1;
// @t=5,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd0;
// @t=6,
#1
path_m1 = 4'd15;
brch_m1 = 2'd1;
path_m2 = 4'd15;
brch_m2 = 2'd2;
// @t=7,
#1
path_m1 = 4'd13;
brch_m1 = 2'd3;
path_m2 = 4'd14;
brch_m2 = 2'd2;
// @t=8,
#1
path_m1 = 4'd14;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=9,
#1
path_m1 = 4'd15;
brch_m1 = 2'd3;
path_m2 = 4'd15;
brch_m2 = 2'd3;
// @t=10,
#1
path_m1 = 4'd16;
brch_m1 = 2'd8;
path_m2 = 4'd2;
brch_m2 = 2'd3;
// @t=11,
#1
path_m1 = 4'd12;
brch_m1 = 2'd2;
path_m2 = 4'd12;
brch_m2 = 2'd1;
// @t=12,
#1
path_m1 = 4'd9;
brch_m1 = 2'd1;
path_m2 = 4'd10;
brch_m2 = 2'd2;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int singles, doubles, n; cin >> n >> singles >> doubles; int refused = 0, partlyOccDoubles = 0; for (int i = 0; i < n; i++) { int cur; cin >> cur; if (cur == 1) { if (singles > 0) { singles--; } else if (doubles > 0) { doubles--; partlyOccDoubles++; } else if (partlyOccDoubles > 0) { partlyOccDoubles--; } else { refused += cur; } } else { if (doubles == 0) refused += cur; else doubles--; } } cout << refused; return 0; }
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; using namespace std; const double eps = 1e-8; const double pi = acos(-1.0); inline double sqr(double x) { return x * x; } int cmp(double x) { if (fabs(x) < eps) return 0; if (x > 0) return 1; return -1; } int n; struct point { double x, y; point() {} point(double a, double b) : x(a), y(b) {} void input() { scanf( %lf%lf , &x, &y); } friend point operator+(const point &a, const point &b) { return point(a.x + b.x, a.y + b.y); } friend point operator-(const point &a, const point &b) { return point(a.x - b.x, a.y - b.y); } friend bool operator==(const point &a, const point &b) { return cmp(a.x - b.x) == 0 && cmp(a.y - b.y) == 0; } friend point operator*(const point &a, const double &b) { return point(a.x * b, a.y * b); } friend point operator*(const double &a, const point &b) { return point(a * b.x, a * b.y); } friend point operator/(const point &a, const double &b) { return point(a.x / b, a.y / b); } double norm() { return sqrt(sqr(x) + sqr(y)); } double norm1() { return sqr(x) + sqr(y); } } P[200]; double det(const point &a, const point &b) { return a.x * b.y - a.y * b.x; } point Cir(point a, point b, point c) { point cp; double a1 = b.x - a.x, b1 = b.y - a.y, c1 = (a1 * a1 + b1 * b1) / 2; double a2 = c.x - a.x, b2 = c.y - a.y, c2 = (a2 * a2 + b2 * b2) / 2; double d = a1 * b2 - a2 * b1; cp.x = a.x + (c1 * b2 - c2 * b1) / d; cp.y = a.y + (a1 * c2 - a2 * c1) / d; return cp; } double dot(const point &a, const point &b) { return a.x * b.y + a.y * b.x; } double dist(const point &a, const point &b) { return (a - b).norm(); } double dist2(const point &a, const point &b) { return (a - b).norm1(); } bool JudgeRet(int a, int b, int c) { double dis1 = dist2(P[a], P[b]); double dis2 = dist2(P[a], P[c]); double dis3 = dist2(P[b], P[c]); if ((cmp(dis1 + dis2 - dis3) == 1) && (cmp(dis2 + dis3 - dis1) == 1) && (cmp(dis1 + dis3 - dis2) == 1)) return true; else if (cmp(dis1 + dis2 - dis3) == 0 || cmp(dis1 + dis3 - dis2) == 0 || cmp(dis2 + dis3 - dis1) == 0) { if (cmp(dis1 + dis2 - dis3) == 0) { for (int i = 1; i <= n; i++) { if (cmp(P[i].x - (P[b].x + P[c].x - P[a].x)) == 0 && cmp(P[i].y - (P[b].y + P[c].y - P[a].y)) == 0) { return true; } } } else if (cmp(dis1 + dis3 - dis2) == 0) { for (int i = 1; i <= n; i++) { if (cmp(P[i].x - (P[a].x + P[c].x - P[b].x)) == 0 && cmp(P[i].y - (P[a].y + P[c].y - P[b].y)) == 0) { return true; } } } else { for (int i = 1; i <= n; i++) { if (cmp(P[i].x - (P[a].x + P[b].x - P[c].x)) == 0 && cmp(P[i].y - (P[a].y + P[b].y - P[c].y)) == 0) { return true; } } } return false; } else return false; } void Compute() { double Max = -1; JudgeRet(2, 3, 5); for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { for (int k = j + 1; k <= n; k++) { if (JudgeRet(i, j, k)) { point center = Cir(P[i], P[j], P[k]); double r = dist(center, P[i]); bool ret = true; for (int i = 1; i <= n; i++) { if (cmp(dist(center, P[i]) - r) == -1) { ret = false; break; } } if (ret) Max = max(Max, r); } } } } if (Max == -1) printf( -1 n ); else printf( %.6f n , Max); } int main() { double x, y; while (~scanf( %d , &n)) { for (int i = 1; i <= n; i++) { scanf( %lf%lf , &x, &y); P[i] = point(x, y); } Compute(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<long long>> dp(10, vector<long long>(1000005, 0)); long long g(long long n) { if (n < 10) return n; long long ans = 1; while (n) { if (n % 10) ans *= (n % 10); n /= 10; } return g(ans); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); for (long long i = 1; i <= 1000000; i++) dp[g(i)][i]++; for (long long i = 0; i < 10; i++) { for (long long j = 2; j <= 1000000; j++) { dp[i][j] += dp[i][j - 1]; } } long long t; cin >> t; while (t--) { long long l, r, k; cin >> l >> r >> k; cout << dp[k][r] - dp[k][l - 1] << n ; } }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module receiver_logic
#(
parameter DSIZE = 10
)
(
input wire RESET,
input wire WCLK,
input wire FCLK,
input wire FCLK2X,
input wire FCLK2X_IOCE,
input wire BUS_CLK,
input wire RX_DATA,
input wire read,
output wire [23:0] data,
output wire empty,
output wire full,
output wire rec_sync_ready,
output reg [7:0] lost_err_cnt,
output reg [7:0] decoder_err_cnt,
output reg [15:0] fifo_size,
input wire invert_rx_data,
input wire enable_rx,
input wire FIFO_CLK
);
wire RESET_WCLK;
flag_domain_crossing reset_domain_crossing_wclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(WCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_WCLK)
);
wire RESET_FCLK;
flag_domain_crossing reset_domain_crossing_fclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(FCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_FCLK)
);
reg enable_rx_buf, enable_rx_buf2, enable_rx_wclk;
always @ (posedge WCLK)
begin
enable_rx_buf <= enable_rx;
enable_rx_buf2 <= enable_rx_buf;
enable_rx_wclk <= enable_rx_buf2;
end
// data to clock phase alignment
wire RX_DATA_SYNC; //, USEAOUT, USEBOUT, USECOUT, USEDOUT;
sync_master sync_master_inst(
.clk(FCLK), // clock input
.clk_2x(FCLK2X), // clock 90 input
.clk_2x_ioce(FCLK2X_IOCE),
.datain(RX_DATA), // data inputs
.rst(RESET_FCLK), // reset input
.useaout(), // useA output for cascade
.usebout(), // useB output for cascade
.usecout(), // useC output for cascade
.usedout(), // useD output for cascade
.ctrlout(), // ctrl outputs for cascade
.sdataout(RX_DATA_SYNC)
);
// 8b/10b record sync
wire [9:0] data_8b10b;
reg decoder_err;
rec_sync #(
.DSIZE(DSIZE)
) rec_sync_inst (
.reset(RESET_WCLK),
.datain(invert_rx_data ? ~RX_DATA_SYNC : RX_DATA_SYNC),
.data(data_8b10b),
.WCLK(WCLK),
.FCLK(FCLK),
.rec_sync_ready(rec_sync_ready),
.decoder_err(decoder_err)
);
wire write_8b10b;
assign write_8b10b = rec_sync_ready & enable_rx_wclk;
reg [9:0] data_to_dec;
integer i;
always @ (*) begin
for (i=0; i<10; i=i+1)
data_to_dec[(10-1)-i] = data_8b10b[i];
end
reg dispin;
wire dispout;
always@(posedge WCLK) begin
if(RESET_WCLK)
dispin <= 1'b0;
else// if(write_8b10b)
dispin <= dispout;
// if(RESET_WCLK)
// dispin <= 1'b0;
// else
// if(write_8b10b)
// dispin <= ~dispout;
// else
// dispin <= dispin;
end
wire dec_k;
wire [7:0] dec_data;
wire code_err, disp_err;
decode_8b10b decode_8b10b_inst (
.datain(data_to_dec),
.dispin(dispin),
.dataout({dec_k,dec_data}), // control character, data out
.dispout(dispout),
.code_err(code_err),
.disp_err(disp_err)
);
always@(negedge WCLK) begin // avoid glitches from code_err or disp_err
if(RESET_WCLK)
decoder_err <= 1'b0;
else
decoder_err <= code_err | disp_err;
end
// Invalid symbols may or may not cause
// disparity errors depending on the symbol
// itself and the disparities of the previous and
// subsequent symbols. For this reason,
// DISP_ERR should always be combined
// with CODE_ERR to detect all errors.
always@(posedge WCLK) begin
if(RESET_WCLK)
decoder_err_cnt <= 0;
else
if(decoder_err && write_8b10b && decoder_err_cnt != 8'hff)
decoder_err_cnt <= decoder_err_cnt + 1;
else
decoder_err_cnt <= decoder_err_cnt;
end
reg [2:0] byte_sel;
always@(posedge WCLK) begin
if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
byte_sel <= 0;
else if(write_8b10b)
byte_sel <= byte_sel + 1;
// if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
// byte_sel <= 0;
// else
// if(write_8b10b)
// byte_sel <= byte_sel + 1;
// else
// byte_sel <= byte_sel;
end
reg [7:0] data_dec_in [2:0];
always@(posedge WCLK) begin
for (i=0; i<3; i=i+1)
data_dec_in[i] <= data_dec_in[i];
if(RESET_WCLK)
for (i=0; i<3; i=i+1)
data_dec_in[i] <= 8'b0;
else
if(write_8b10b && dec_k==0)
data_dec_in[byte_sel] <= dec_data;
end
reg write_dec_in;
always@(posedge WCLK) begin
if(RESET_WCLK)
write_dec_in <= 0;
else
if(write_8b10b && dec_k==0 && byte_sel==2)
write_dec_in <= 1;
else
write_dec_in <= 0;
end
wire cdc_fifo_full, cdc_fifo_empty;
always@(posedge WCLK) begin
if(RESET_WCLK)
lost_err_cnt <= 0;
else
if(cdc_fifo_full && write_dec_in && lost_err_cnt != 8'hff)
lost_err_cnt <= lost_err_cnt + 1;
else
lost_err_cnt <= lost_err_cnt;
end
wire [23:0] cdc_data_out;
wire [23:0] wdata;
assign wdata = {data_dec_in[0],data_dec_in[1],data_dec_in[2]};
// generate delayed and long reset
reg [5:0] rst_cnt;
always@(posedge BUS_CLK) begin
if(RESET)
rst_cnt <= 5'd8;
else if(rst_cnt != 5'd7)
rst_cnt <= rst_cnt +1;
end
wire rst_long = rst_cnt[5];
reg cdc_sync_ff;
always @(posedge WCLK) begin
cdc_sync_ff <= rst_long;
end
//assign FIFO_CLK = BUS_CLK;
cdc_syncfifo #(
.DSIZE(24),
.ASIZE(2)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(cdc_fifo_full),
.rempty(cdc_fifo_empty),
.wdata(wdata),
.winc(write_dec_in),
.wclk(WCLK),
.wrst(cdc_sync_ff),
.rinc(!full),
.rclk(FIFO_CLK),
.rrst(rst_long)
);
wire [10:0] fifo_size_int;
gerneric_fifo #(
.DATA_SIZE(24),
.DEPTH(2048)
) fifo_i (
.clk(FIFO_CLK),
.reset(rst_long),
.write(!cdc_fifo_empty),
.read(read),
.data_in(cdc_data_out),
.full(full),
.empty(empty),
.data_out(data),
.size(fifo_size_int)
);
always @(posedge FIFO_CLK) begin
fifo_size <= {5'b0, fifo_size_int};
end
`ifdef SYNTHESIS_NOT
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(FCLK),
.TRIG0({dec_k, dec_data, data_to_dec, rec_sync_ready, 1'b0, USEAOUT, USEBOUT, USECOUT, USEDOUT, RX_DATA_SYNC, RX_DATA})
);
`endif
endmodule
|
module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI );
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits:0] DOR ;
reg [total_bits:0] DOR ;
output [total_bits:0] DOI ;
reg [total_bits:0] DOI ;
reg signed [total_bits+2 :0] dx5;
reg signed [total_bits-1 :0] dx7;
reg signed [total_bits-1 :0] dii;
reg signed [total_bits : 0] dt;
wire signed [total_bits+3 : 0] dx5p;
wire signed [total_bits+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [total_bits:0] doo ;
reg [total_bits:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2; //1_0100_1110_0111_1011
if (DS) begin // 1_0101_00T0_1000_0T0T
dx5<=DR+(DR <<2); //multiply by 5
dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3
dt<=dii;
end
doo<=dot >>>3;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T
assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T
endmodule
|
/**
* microcode_rom.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "microcodedefs.v"
module microcode_rom(
input wire clk, /* clock input */
input wire [`OFFSET_WIDTH - 1 : 0] offset, /* ROM address */
output reg [`MCROM_WIDTH - 1 : 0] mc_word /* ROM word output */
);
always @(posedge clk) begin
case(offset)
/* fetch */
`OFFSET_WIDTH'h00:
mc_word = `MCROM_WIDTH'b1_000001_xxx_xxx_0_0_1_0_xx_0_xx_0_x_0_xx;
/* decode */
`OFFSET_WIDTH'h01:
mc_word = `MCROM_WIDTH'b0_xxxxxx_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
/* clear accumulator register */
`OFFSET_WIDTH'h02:
mc_word = `MCROM_WIDTH'b1_000000_110_101_0_1_0_1_00_0_xx_0_x_1_10;
/* load immediate into accumulator */
`OFFSET_WIDTH'h03:
mc_word = `MCROM_WIDTH'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_1_11;
/* load from immediate memory address into accumulator */
`OFFSET_WIDTH'h04:
mc_word = `MCROM_WIDTH'b1_000101_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h05:
mc_word = `MCROM_WIDTH'b1_000110_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h06:
mc_word = `MCROM_WIDTH'b1_000111_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h07:
mc_word = `MCROM_WIDTH'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_1_01;
/* store from accumulator into immediate memory address */
`OFFSET_WIDTH'h08:
mc_word = `MCROM_WIDTH'b1_001001_xxx_xxx_0_0_0_0_xx_1_11_1_1_0_xx;
`OFFSET_WIDTH'h09:
mc_word = `MCROM_WIDTH'b1_000000_xxx_xxx_1_0_0_1_00_0_xx_0_x_0_xx;
/* add from immediate memory address into accumulator */
`OFFSET_WIDTH'h0a:
mc_word = `MCROM_WIDTH'b1_001011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h0b:
mc_word = `MCROM_WIDTH'b1_001100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h0c:
mc_word = `MCROM_WIDTH'b1_001101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h0d:
mc_word = `MCROM_WIDTH'b1_000000_000_111_0_1_0_1_00_0_xx_0_x_1_10;
/* absolute branch to immediate address or conditional branch taken */
`OFFSET_WIDTH'h0e:
mc_word = `MCROM_WIDTH'b1_000000_xxx_xxx_0_0_0_1_01_0_xx_0_x_0_xx;
/* conditional branch not taken */
`OFFSET_WIDTH'h0f:
mc_word = `MCROM_WIDTH'b1_000000_xxx_xxx_0_0_0_1_00_0_xx_0_x_0_xx;
/* increment accumulator */
`OFFSET_WIDTH'h10:
mc_word = `MCROM_WIDTH'b1_000000_000_001_0_1_0_1_00_0_xx_0_x_1_10;
/* compare with immediate constant */
`OFFSET_WIDTH'h11:
mc_word = `MCROM_WIDTH'b1_000000_010_110_0_1_0_1_00_0_xx_0_x_0_xx;
/* compare with value at immediate address */
`OFFSET_WIDTH'h12:
mc_word = `MCROM_WIDTH'b1_010011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h13:
mc_word = `MCROM_WIDTH'b1_010100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h14:
mc_word = `MCROM_WIDTH'b1_010101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h15:
mc_word = `MCROM_WIDTH'b1_000000_010_111_0_1_0_1_00_0_xx_0_x_0_xx;
/* subtract from immediate memory address into accumulator */
`OFFSET_WIDTH'h16:
mc_word = `MCROM_WIDTH'b1_010111_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h17:
mc_word = `MCROM_WIDTH'b1_011000_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h18:
mc_word = `MCROM_WIDTH'b1_011001_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h19:
mc_word = `MCROM_WIDTH'b1_000000_010_111_0_1_0_1_00_0_xx_0_x_1_10;
/* exclusive OR from immediate memory address into accumulator */
`OFFSET_WIDTH'h1a:
mc_word = `MCROM_WIDTH'b1_011011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h1b:
mc_word = `MCROM_WIDTH'b1_011100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h1c:
mc_word = `MCROM_WIDTH'b1_011101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h1d:
mc_word = `MCROM_WIDTH'b1_000000_110_111_0_1_0_1_00_0_xx_0_x_1_10;
/* NOR from immediate memory address into accumulator */
`OFFSET_WIDTH'h1e:
mc_word = `MCROM_WIDTH'b1_011111_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h1f:
mc_word = `MCROM_WIDTH'b1_100000_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h20:
mc_word = `MCROM_WIDTH'b1_100001_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h21:
mc_word = `MCROM_WIDTH'b1_000000_101_111_0_1_0_1_00_0_xx_0_x_1_10;
/* NAND from immediate memory address into accumulator */
`OFFSET_WIDTH'h22:
mc_word = `MCROM_WIDTH'b1_100011_xxx_xxx_0_0_0_0_xx_0_xx_1_1_0_xx;
`OFFSET_WIDTH'h23:
mc_word = `MCROM_WIDTH'b1_100100_xxx_xxx_0_0_0_0_xx_0_xx_0_x_0_xx;
`OFFSET_WIDTH'h24:
mc_word = `MCROM_WIDTH'b1_100101_xxx_xxx_0_0_0_0_xx_1_01_0_x_0_xx;
`OFFSET_WIDTH'h25:
mc_word = `MCROM_WIDTH'b1_000000_100_111_0_1_0_1_00_0_xx_0_x_1_10;
/* add immediate into accumulator */
`OFFSET_WIDTH'h26:
mc_word = `MCROM_WIDTH'b1_000000_000_110_0_1_0_1_00_0_xx_0_x_1_10;
/* invert accumulator */
`OFFSET_WIDTH'h27:
mc_word = `MCROM_WIDTH'b1_000000_110_011_0_1_0_1_00_0_xx_0_x_1_10;
/* shift right arithmetic accumulator */
`OFFSET_WIDTH'h28:
mc_word = `MCROM_WIDTH'b1_000000_111_101_0_1_0_1_00_0_xx_0_x_1_10;
/* shift left arithmetic accumulator */
`OFFSET_WIDTH'h29:
mc_word = `MCROM_WIDTH'b1_000000_000_101_0_1_0_1_00_0_xx_0_x_1_10;
/* halt condition */
default:
mc_word = {{(`OFFSET_WIDTH+1){1'b1}},
{(`MCROM_WIDTH - `OFFSET_WIDTH - 1){1'b0}}};
endcase
end
endmodule
`include "microcodeundefs.v"
/* vim: set ts=4 tw=79 syntax=verilog */
|
#include <bits/stdc++.h> using namespace std; long long read() { long long a = 0, b = getchar(), c = 1; while (!isdigit(b)) c = b == - ? -1 : 1, b = getchar(); while (isdigit(b)) a = a * 10 + b - 0 , b = getchar(); return a * c; } void print(long long x) { if (x < 0) putchar( - ), x = -x; int y = x % 10 + 0 ; if (x >= 10) print(x / 10); putchar(y); } int n, x, y, a[100005]; int main() { n = read(), x = read(), y = read(); for (int i = 0; i < n; i++) a[i] = read(); for (int i = 0; i < n; i++) { bool z = true; for (int j = max(0, i - x); j < i; j++) if (a[j] <= a[i]) z = false; for (int j = min(n - 1, i + y); j > i; j--) if (a[j] <= a[i]) z = false; if (z) return print(i + 1), 0; } return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'pop' primitive
//
//===----------------------------------------------------------------------===//
module acl_pop (
clock,
resetn,
// input stream from kernel pipeline
dir,
valid_in,
data_in,
stall_out,
predicate,
// downstream, to kernel pipeline
valid_out,
stall_in,
data_out,
// feedback downstream, from feedback acl_push
feedback_in,
feedback_valid_in,
feedback_stall_out
);
parameter DATA_WIDTH = 32;
parameter string STYLE = "REGULAR"; // REGULAR vs COALESCE
// this will pop garbage off of the feedback
localparam POP_GARBAGE = STYLE == "COALESCE" ? 1 : 0;
input clock, resetn, stall_in, valid_in, feedback_valid_in;
output stall_out, valid_out, feedback_stall_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH-1:0] feedback_in;
wire feedback_downstream, data_downstream;
reg pop_garbage;
reg last_dir;
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
pop_garbage = 0;
end
else if ( valid_in && ~dir && last_dir ) begin
pop_garbage = POP_GARBAGE;
end
end
always @(posedge clock or negedge resetn)
begin
if ( !resetn ) begin
last_dir = 0;
end
else if ( valid_in ) begin
last_dir = dir;
end
end
assign feedback_downstream = valid_in & ~dir & feedback_valid_in;
assign data_downstream = valid_in & dir;
assign valid_out = feedback_downstream | ( data_downstream & (~pop_garbage | feedback_valid_in ) ) ;
assign data_out = ~dir ? feedback_in : data_in;
//assign stall_out = stall_in;
//assign stall_out = valid_in & ~((feedback_downstream | data_downstream) & ~stall_in);
// assign stall_out = ~((feedback_downstream | data_downstream) & ~stall_in);
// stall upstream if
// downstream is stalling (stall_in)
// I'm waiting for data from feedback (valid_in&~dir&~feedback_valiid_in)
assign stall_out = ( valid_in & ( ( ~dir & ~feedback_valid_in ) | ( dir & ~feedback_valid_in & pop_garbage ) ) ) | stall_in;
// don't accept data if:
// downstream cannot accept data (stall_in)
// data from upstream is selected (data_downstream)
// no thread exists to read data (~valid_in)
// predicate is high
assign feedback_stall_out = stall_in | (data_downstream & ~pop_garbage) | ~valid_in | predicate;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[1000005]; int main() { int n, k; while (scanf( %d%d , &n, &k) != EOF) { if (k > n || (n > 1 && k == 1)) { printf( -1 n ); break; } else { if ((n - k) % 2) { for (int i = 1; i <= n - k + 1; i++) { s[i] = a ; s[i + 1] = b ; i++; } s[n - k + 2] = a ; int c = 99; for (int i = n - k + 3; i <= n; i++) { s[i] = c; c++; } } else { for (int i = 1; i <= n - k; i++) { s[i] = a ; s[i + 1] = b ; i++; } int c = 97; for (int i = n - k + 1; i <= n; i++) { s[i] = c; c++; } } } for (int i = 1; i <= n; i++) printf( %c , s[i]); cout << endl; } return 0; }
|
module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
wire [5:0] offset = idx << 2;
assign slice_up = data[offset +: 4];
assign slice_down = data[offset + 3 -: 4];
endmodule
module partsel_test002 (
input clk, rst,
input [7:0] a,
input [0:7] b,
input [1:0] s,
output [7:0] x1, x2, x3,
output [0:7] x4, x5, x6,
output [7:0] y1, y2, y3,
output [0:7] y4, y5, y6,
output [7:0] z1, z2, z3,
output [0:7] z4, z5, z6,
output [7:0] w1, w2, w3,
output [0:7] w4, w5, w6,
output [7:0] p1, p2, p3, p4, p5, p6,
output [0:7] q1, q2, q3, q4, q5, q6,
output reg [7:0] r1,
output reg [0:7] r2
);
assign x1 = a, x2 = a + b, x3 = b;
assign x4 = a, x5 = a + b, x6 = b;
assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];
assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];
assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];
assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];
assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];
assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];
assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];
assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];
always @(posedge clk) begin
if (rst) begin
{ r1, r2 } = 16'h1337 ^ {a, b};
end else begin
case (s)
0: begin
r1[3:0] <= r2[0:3] ^ x1;
r2[4:7] <= r1[7:4] ^ x4;
end
1: begin
r1[2 +: 3] <= r2[5 -: 3] + x1;
r2[3 +: 3] <= r1[6 -: 3] + x4;
end
2: begin
r1[6 -: 3] <= r2[3 +: 3] - x1;
r2[7 -: 3] <= r1[4 +: 3] - x4;
end
3: begin
r1 <= r2;
r2 <= r1;
end
endcase
end
end
endmodule
module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
assign dout = din[a*b +: 2];
endmodule
module partsel_test004 (
input [31:0] din,
input signed [4:0] n,
output reg [31:0] dout
);
always @(*) begin
dout = 0;
dout[n+1 +: 2] = din[n +: 2];
end
endmodule
module partsel_test005 (
input [31:0] din,
input signed [4:0] n,
output reg [31:0] dout
);
always @(*) begin
dout = 0;
dout[n+1] = din[n];
end
endmodule
module partsel_test006 (
input [31:-32] din,
input signed [4:0] n,
output reg [31:-32] dout
);
always @(*) begin
dout = 0;
dout[n+1 +: 2] = din[n +: 2];
end
endmodule
module partsel_test007 (
input [31:-32] din,
input signed [4:0] n,
output reg [31:-32] dout
);
always @(*) begin
dout = 0;
dout[n+1] = din[n];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; int n; string s; while (t--) { cin >> n >> s; int x = 0, y = 0; map<pair<int, int>, int> m; int l = 0, r = n + 1; m[{0, 0}] = 1; for (int i = 0; i < n; i++) { if (s[i] == L ) x--; if (s[i] == R ) x++; if (s[i] == U ) y++; if (s[i] == D ) y--; if (m[{x, y}]) { if (i - m[{x, y}] < r - l) { l = m[{x, y}]; r = i; } } m[{x, y}] = i + 2; } if (l == 0) { cout << -1 << n ; } else { cout << l << << r + 1 << n ; } } }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video streams from the Terasic CCD cameras. *
* *
******************************************************************************/
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0), eps = 1e-8; const int inf = ~0U >> 2; int mod = 1e9 + 7; int Pow(int x, long long t) { int r = 1; for (; t; t >>= 1, x = (long long)x * x % mod) if (t & 1) r = (long long)r * x % mod; return r; } const int N = 101010; int n, K; struct P { long long x, y; void in() { cin >> x >> y; } P(long long _x = 0, long long _y = 0) { x = _x, y = _y; } double dis() { return sqrt(x * x + y * y); } long long operator^(const P& b) { return x * b.y - y * b.x; } P operator-(const P& b) { return P(x - b.x, y - b.y); } } p[N << 1], q; long long mul(P& o, P& a, P& b) { return (a - o) ^ (b - o); } bool in(P q) { double a = 0; for (int i = 0; i < n; ++i) { long long aera = mul(q, p[i], p[i + 1]); double disa = (p[i] - q).dis(), disb = (p[i + 1] - q).dis(), disc = (p[i] - p[i + 1]).dis(); double angle = acos(((disa) * (disa) + (disb) * (disb) - (disc) * (disc)) / 2.0 / disa / disb); if (aera > 0) a += angle; else a -= angle; } return fabs(a) >= 1; } long long wk() { q.in(); if (!in(q)) return 0; long long ans = (long long)n * (n - 1) * (n - 2) / 6; for (int i = 0, j = 1; i < n; ++i) { while (mul(p[i], p[j], q) <= 0) ++j; int del = (j + n - i) % n; int rm = n - del; ans -= (long long)rm * (rm - 1) / 2; } return ans; } int main() { cin >> n; for (int i = 0; i < n; ++i) p[i].in(), p[i + n] = p[i]; cin >> K; for (int i = 0; i < K; ++i) cout << wk() << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; long long int cal(long long int num) { return (num * (num + 1)) / 2ll; } void solve() { long long int n; scanf( %lld , &n); n--; long long int ans = 0, k = 1; for (long long int i = 1; i <= n; i <<= 1) { ans += ((n - i) / (i << 1) + 1) * i; } printf( %lld n , ans); } int main() { int t = 1; while (t--) { solve(); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:23 10/06/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_rx(clk, reset, wren, rden, din, dout, rxin, addr);
input clk, reset, wren, rden;
input [7:0] din;
output [8:0] dout;
input rxin; //serial data in
input [2:0] addr;
reg [8:0] dout, frame_error;
reg [9:0] shift;
reg [7:0] control;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [2:0] nstate, pstate;
reg in_one, in_two, hold, frame_ready, loaded, load, clr_load;
`define period 3'b100
`define rx_reg 3'b101
`define control 3'b111
`define RXEN control[0]
`define DATARDY control[1]
`define OVERRUN control[2]
`define ERROR frame_error[8]
`define STOP shift[9]
`define START shift[0]
`define HOLD 3'b000
`define WAIT 3'b001
`define SHIFT1 3'b010
`define SHIFT2 3'b011
`define LD_FIFO 3'b100
`define RX_NOT_READY 3'b101
wire [7:0] dout_baud;
wire [8:0] dout_fifo;
wire baud, full, empty;
parameter PERIOD = 8'h1A; //must have this initial value
//baud generator
//module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
//input wren, rden, reset, clk, sclr;
//input [7:0] din;
//output baud;
//output [7:0] dout;
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
//fifo ipcore
//input clk;
//input srst;
//input [8 : 0] din;
//input wr_en;
//input rd_en;
//output [8 : 0] dout;
//output full;
//output empty;
fifo_rx fifo1(
.clk (clk),
.srst (hold),
.din (frame_error),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (dout_fifo),
.full (full),
.empty (empty)
);
// input flip flops
always @(posedge clk) begin
//first flip flop
in_one <= rxin;
//second flip flop
in_two <= in_one;
end
// shift register
always @(posedge clk or posedge reset) begin
if(reset) begin
shift <= 10'b1111111111;
load = 0;
end
else begin
if(ld_shift) begin
shift <= {in_two, shift[9:1]};
load = 1;
end
else
load = 0;
end
end
// loaded flag
always @(negedge clk or posedge reset) begin
if(reset) begin
loaded = 0;
end
else begin
if(load)
loaded = 1;
if(clr_load)
loaded = 0;
end
end
// frame check
always @(posedge clk or posedge reset) begin
if(reset) begin
frame_error <= 8'b00000000;
frame_ready <= 0;
end
else begin
if(rd_shift)begin
frame_error[7:0] <= shift[8:1];
if(`START | ~`STOP)
`ERROR <= 1;
else
`ERROR <= 0;
frame_ready <= 1;
end
else
frame_ready <= 0;
end
end
//address write
always @* begin
wr_baud = 0;
wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
//address read
always @* begin
rd_baud = 0;
rd_fifo = 0;
dout = 9'b000000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`rx_reg: begin
if(rden)
rd_fifo = 1;
dout = dout_fifo;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// control register
always @(posedge clk or posedge reset) begin
if(reset)
control[7:0] <= 8'b00000000;
else begin
`DATARDY <= ~empty;
if(wr_control)
control[0] <= din[0];
if(frame_ready & full)
`OVERRUN <= 1;
if(~`RXEN) begin
`DATARDY <= 0;
`OVERRUN <= 0;
end
end
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `HOLD;
else begin
pstate <= nstate;
if(`OVERRUN)
pstate <= `RX_NOT_READY;
end
end
//fsm
always @* begin
hold = 0;
ld_shift = 0; clr_load = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0; wr_fifo = 0;
nstate = pstate;
case (pstate)
`HOLD: begin
hold = 1;
stop = 1;
if(`RXEN == 1)
nstate = `WAIT;
end
`WAIT: begin
stop = 1;
if(~rxin) begin
stop = 0;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `LD_FIFO;
finish = 1;
rd_shift = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(bittimer == 4'b1000 & ~loaded)
ld_shift = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
clr_load = 1;
nstate = `SHIFT1;
end
end
`LD_FIFO: begin
wr_fifo = 1;
nstate = `WAIT;
end
`RX_NOT_READY: begin
if(~`OVERRUN)
nstate = `HOLD;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> const long long N = 1000006; using namespace std; const long long MOD = 1000000007LL; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T power(T x, T y, long long m = MOD) { T ans = 1; while (y > 0) { if (y & 1LL) ans = (ans * x) % m; y >>= 1LL; x = (x * x) % m; } return ans % m; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; if (n == 1) { cout << 0 ; return 0; } multiset<long long> l, r; vector<pair<long long, long long> > v; for (long long(i) = (0); i < (n); i++) { long long x, y; cin >> x >> y; l.insert(x); r.insert(y); v.emplace_back(make_pair(x, y)); } long long ans = 0; for (long long(i) = (0); i < (n); i++) { l.erase(l.find(v[i].first)); r.erase(r.find(v[i].second)); long long dist = max(0LL, *r.begin() - *l.rbegin()); ans = max(ans, dist); l.insert(v[i].first); r.insert(v[i].second); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(0); int n, x; cin >> n; vector<vector<int>> adj(n); for (int i = 1; i < n; i++) cin >> x, x--, adj[x].push_back(i), adj[i].push_back(x); queue<int> q; q.push(0); map<int, int> depth, count; depth[0] = 0; count[0]++; while (!q.empty()) { int cur = q.front(); q.pop(); for (auto nxt : adj[cur]) if (depth.find(nxt) == depth.end()) depth[nxt] = depth[cur] + 1, count[depth[nxt]]++, q.push(nxt); } int ret = 0; for (auto it : count) ret += it.second % 2; cout << ret << endl; return 0; }
|
Require Import Coq.Sets.Ensembles.
Require Import List.
From OakIFC Require Import
Lattice
Parameters
GenericMap
ModelSemUtils
RuntimeModel
State
Events.
Import ListNotations.
Arguments Ensembles.In {U}.
Arguments Ensembles.Add {U}.
Arguments Ensembles.Subtract {U}.
Arguments Ensembles.Singleton {U}.
From RecordUpdate Require Import RecordSet.
Import RecordSetNotations.
Local Open Scope map_scope.
Local Open Scope ev_notation.
(*
The top-level security condition compares traces involving both states (as
in "state" in RuntimeModel.v) and events. This file augments the semantics
in RuntimeModel.v with rules that also produce labeled Events (in Events.v)
that represent values that are inputs/outputs to/from nodes. It also builds
traces that are sequences of pairs of states and events. In the future,
events will also represent downgrades of values. These events are abstract
objects that are used in the specification of the security condition.
The "input" event during the read is the one that is really strictly needed.
The model of a node does not contain any state corresponding to values.
So a purely state-based security condition would not say anything about values
that are read by a node.
I considered whether traces can be JUST sequences of events
rather than sequences of state/event pairs. I think the answer is no
because then it might be possible to leak information via
the handles a node has. (Even though the call of a node does not contain
informtion because the choice of call is always essentially non-deterministic,
so the call is a piece of state that probably does not matter at the moment)
When downgrades events are added, a trace might need to be
list (state * (Ensemble event)) (Ensembles are sets)
rather than
list (state * event)
since individual calls might produce more than one event. For example,
when a read call does a declassification it would produce an input event
and a downgrade event.
*)
Definition trace := list (state * event_l).
(* This is used for state/event pairs in EvAug.
* The type is slightly awkward now post refactor *)
Definition head_st (t: trace) :=
match t with
| nil => None
| (s', _)::_ => Some s'
end.
Inductive step_node_ev (id: node_id): call -> state -> state -> event_l -> Prop :=
| SWriteChanEv s nlbl han msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WriteChannel han msg) s s' ->
step_node_ev id (WriteChannel han msg) s s' (nlbl ---> msg)
(* The notations used for events on this last line and others
is in Events.v *)
| SReadChanEv s nlbl han chan msg s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ReadChannel han) s s' ->
msg_is_head chan msg ->
step_node_ev id (ReadChannel han) s s' (nlbl <--- msg)
| SCreateChanEv s nlbl clbl s':
(* It seems clear that no event is needed since nodes only observe
* contents of channels indirectly via reads *)
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateChannel clbl) s s' ->
step_node_ev id (CreateChannel clbl) s s' (nlbl --- )
| SCreateNodeEv s nlbl new_lbl h s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (CreateNode new_lbl h) s s' ->
step_node_ev id (CreateNode new_lbl h) s s' ( -- nlbl -- )
| SWaitOnChannelsEv s hs nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (WaitOnChannels hs) s s' ->
step_node_ev id (WaitOnChannels hs) s s' (nlbl ---)
| SChannelCloseEv s han nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id (ChannelClose han) s s' ->
step_node_ev id (ChannelClose han) s s' (nlbl ---)
| SNodeLabelReadEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id NodeLabelRead s s' ->
step_node_ev id NodeLabelRead s s' (nlbl <--L nlbl)
| SChannelLabelReadEv s han nlbl clbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
(s.(chans) .[?han]).(lbl) = clbl ->
step_node id (ChannelLabelRead han) s s' ->
step_node_ev id (ChannelLabelRead han) s s' (nlbl <--L clbl)
| SInternalEv s nlbl s':
(s.(nodes) .[?id]).(lbl) = nlbl ->
step_node id Internal s s' ->
step_node_ev id Internal s s' (nlbl ---).
Inductive step_system_ev: state -> state -> event_l -> Prop :=
| SytsemEvSkip s ell: step_system_ev s s (ell ---)
| SystemEvStepNode id n c c' s s' e:
(s.(nodes).[?id]).(obj) = Some n ->
n.(ncall) = c ->
step_node_ev id c s s' e ->
let s'' := (s_set_call s' id c') in
(* Here c' is an arbitrary command. The next ABI call
that the node makes after the one executed here is an arbitrary one
of that node's choosing *)
step_system_ev s s'' e.
(* TODO
Theorem that proves that step_system_ev is sound/complete for step_system.
(* should be trivial ? *)
The reason why there is more than one state transition relation is that the
'events' are just an abstract concept meant to state the security theorems,
so it seemed useful to keep them separate from the main specification of
behavior.
Alternatively, we could just decide that actually including events in the
main specification of behavior is just fine, and then we just replace
step_sytem with step_system_ev.
*)
Inductive step_system_ev_t: trace -> trace -> Prop :=
| StepTrace t s s' e:
head_st t = Some s ->
step_system_ev s s' e ->
step_system_ev_t t ((s', e) :: t).
Inductive step_system_ev_multi: trace -> trace -> Prop :=
| multi_system_ev_refl t t':
step_system_ev_t t t' ->
step_system_ev_multi t t'
| multi_system_ev_tran t1 t2 t3:
step_system_ev_t t2 t3 ->
step_system_ev_multi t1 t2 ->
step_system_ev_multi t1 t3.
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex5_dmem.v when simulating
// the core, virtex5_dmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex5_dmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex5_dmem is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_1_V
`define SKY130_FD_SC_MS__CLKBUF_1_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_1_V
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; const int inf = 0x7FFFFFFF; template <class T> inline void checkmin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkmax(T &a, T b) { if (b > a) a = b; } template <class T> inline T sqr(T x) { return x * x; } template <class T> void show(T a, int n) { for (int i = 0; i < n; ++i) cout << a[i] << ; cout << endl; } template <class T> void show(T a, int r, int l) { for (int i = 0; i < r; ++i) show(a[i], l); cout << endl; } struct S { long long w, h; long long bord, space; string tp; vector<int> son; int vis; void init(int x, int y, string t) { w = x, h = y; bord = space = 0; tp = t; son.clear(); vis = false; } void dfs(); } s[100000]; char buf[10000]; void S::dfs() { vis = true; if (son.size() > 0) { for (int i = 0; i < son.size(); i++) if (!s[son[i]].vis) { s[son[i]].dfs(); } if (tp == VBox ) { for (int i = 0; i < son.size(); i++) { int v = son[i]; w = max(s[v].w, w); if (i > 0) h += space; h += s[v].h; } w += 2 * bord; h += 2 * bord; } else if (tp == HBox ) { for (int i = 0; i < son.size(); i++) { int v = son[i]; h = max(s[v].h, h); if (i > 0) w += space; w += s[v].w; } w += 2 * bord; h += bord * 2; } } } string nn[10000]; struct SS { string s; long long x, y; const bool operator<(const SS &b) const { return s < b.s; } } ss[10000]; int main() { int n; while (cin >> n) { map<string, int> mp; int cnt = 0; for (int i = 0; i < n; i++) { scanf( %[^ n] , buf); bool newtp = true; for (int i = 0; buf[i]; i++) if (buf[i] == ( || buf[i] == ) || buf[i] == . || buf[i] == , ) { if (buf[i] == . ) newtp = false; buf[i] = ; } istringstream sin(buf); string t, nm, nm2; sin >> t; if (t == Widget || t == VBox || t == HBox ) { int x = 0, y = 0; sin >> nm; mp[nm] = cnt; nn[cnt] = nm; if (t == Widget ) { sin >> x >> y; } s[cnt].init(x, y, t); cnt++; } else { nm = t; int x; sin >> t; if (t == set_border ) { sin >> x; s[mp[nm]].bord = x; } else if (t == set_spacing ) { sin >> x; s[mp[nm]].space = x; } else if (t == pack ) { sin >> nm2; s[mp[nm]].son.push_back(mp[nm2]); } else puts( fuck ); } } for (int i = 0; i < cnt; i++) { if (!s[i].vis) s[i].dfs(); } for (int i = 0; i < cnt; i++) { ss[i].s = nn[i]; ss[i].x = s[i].w; ss[i].y = s[i].h; } sort(ss, ss + cnt); for (int i = 0; i < cnt; i++) { cout << ss[i].s << << ss[i].x << << ss[i].y << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int FFF = 200005; int a[FFF], b[FFF]; int qsearch(int x, int r) { int l = 1, mid; while (l <= r) { mid = (l + r) >> 1; if (b[mid] < x) l = mid + 1; else r = mid - 1; } return r; } int main() { int n, m; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); scanf( %d , &m); for (int i = 1; i <= m; i++) scanf( %d , &b[i]); sort(b + 1, b + m + 1); long long suma, sumb, cha; suma = n * 2; sumb = m * 2; cha = suma - sumb; for (int now = 0; now < n; now++) { int t = qsearch(a[now], m); long long tt1 = now * 2 + 3 * (n - now); long long tt2 = t * 2 + (m - t) * 3; long long tmp = tt1 - tt2; if (tmp > cha) { cha = tmp; suma = tt1; sumb = tt2; } else if (tmp == cha && suma < tt1) { suma = tt1; sumb = tt2; } } cout << suma << : << sumb << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; int n, x[2], need[N][2]; pair<int, int> p[N]; int main() { ios::sync_with_stdio(false); cin >> n >> x[0] >> x[1]; for (int i = 0; i < n; i++) { int c; cin >> c; p[i] = {c, i}; } sort(p, p + n); for (int i = 0; i < n; i++) for (int j = 0; j < 2; j++) { int c = p[i].first; need[i][j] = (x[j] + c - 1) / c; } for (int i = n - 1; i >= 0; i--) { if (i + need[i][0] < n && need[i][0] + need[i + need[i][0]][1] <= n - i) { vector<int> a, b; for (int j = i; j < i + need[i][0]; j++) a.push_back(p[j].second); for (int j = i + need[i][0]; j < i + need[i][0] + need[i + need[i][0]][1]; j++) b.push_back(p[j].second); cout << Yes n ; cout << a.size() << << b.size() << n ; for (int x : a) cout << x + 1 << ; cout << n ; for (int x : b) cout << x + 1 << ; cout << n ; return 0; } if (i + need[i][1] < n && need[i][1] + need[i + need[i][1]][0] <= n - i) { vector<int> a, b; for (int j = i; j < i + need[i][1]; j++) b.push_back(p[j].second); for (int j = i + need[i][1]; j < i + need[i][1] + need[i + need[i][1]][0]; j++) a.push_back(p[j].second); cout << Yes n ; cout << a.size() << << b.size() << n ; for (int x : a) cout << x + 1 << ; cout << n ; for (int x : b) cout << x + 1 << ; cout << n ; return 0; } } cout << No n ; return 0; }
|
#include<bits/stdc++.h> #define ll long long #define ull unsigned long long #define in(ar,n) for(int i=0;i<n;i++)cin>>ar[i]; #define invec(ar,n)for(int i =0 ; i<n;i++){int temp;cin>>temp;ar.push_back(temp);} #define in2d(ar,n,m) for(int i=0;i<n;i++)for(int i=0;i<m;i++)cin>>ar[i] #define out(ar,n) for(int i=0;i<n;i++) cout<<ar[i]<< ; cout<<endl; #define swap(a,b) int t = a; a = b; b = t; #define print(val) cout<<val<<endl; #define set(ar,n,val) for(int i=0;i<n;i++)ar[i]=val #define for2d(n,m) for(int i=0;i<n;i++)for(int j=0;j<m;j++) #define minar(ar,n,mn) for(int i=0;i<n;i++)mn =min(mn,ar[i]) #define maxar(ar,n,mx) for(int i=0;i<n;i++)mx =max(mx,ar[i]) #define fori(i,a,b) for(ll i=a;i<b;++i) #define all(ar) ar.begin(),ar.end() using namespace std; typedef pair<ll,ll> pll; typedef pair<int,int> pii; typedef vector<vector<int>> vvi; const ll mod = 1e9 + 7; int main(){ int t;cin>>t; while(t--){ int n;cin>>n; string s;cin>>s; vector<int> ar,ans; fori(i,0,n){ ar.push_back(s[i]- 0 ); } ans.push_back(1); int c = ar[0]+1; fori(i,1,n){ if(c==2){ if(ar[i]==1){ ans.push_back(0); c = 1; } else { ans.push_back(1); c = 1; } } else if(c==1){ if(ar[i]==1){ ans.push_back(1); c = 2; } else {ans.push_back(0);c = 0;} } else { if(ar[i]==0){ ans.push_back(1); c = 1; } else { ans.push_back(1); c = 2; } } } fori(i,0,n){ cout<<ans[i]; } cout<<endl; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc2_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc2_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, w[101], i, j, S, Sum, k, C, a, t; int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d , &k); for (j = 1; j <= k; j++) { scanf( %d , &a); Sum += a; t = j * 2 - k; if (t == 1) w[C++] = -a; else if (t <= 0) S += a; } } sort(w, w + C); for (i = 0; i < C; i += 2) S -= w[i]; printf( %d %d n , S, Sum - S); }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; struct MCMF { enum { MAXN = 6500 }; struct Edge { int x, y; int cap, cost; }; vector<Edge> E; vector<int> adj[MAXN]; int N, prev[MAXN]; int dist[MAXN], phi[MAXN]; MCMF(int NN) : N(NN) {} void add(int x, int y, int cap, int cost) { Edge e1 = {x, y, cap, cost}, e2 = {y, x, 0, -cost}; adj[e1.x].push_back(E.size()); E.push_back(e1); adj[e2.x].push_back(E.size()); E.push_back(e2); } vector<queue<int> > Q; void mcmf(int s, int t, int &flowVal, int &flowCost) { int x; flowVal = flowCost = 0; memset(phi, 0, sizeof(phi)); Q.resize(6500); while (true) { for (x = 0; x < N; x++) prev[x] = -1; for (x = 0; x < N; x++) dist[x] = 1000000000; dist[s] = prev[s] = 0; Q[dist[s]].push(s); for (int i = 0; i < 6400; i++) { while (!Q[i].empty()) { x = Q[i].front(); Q[i].pop(); if (dist[x] < i) continue; vector<int>::iterator it; for (it = adj[x].begin(); it != adj[x].end(); it++) { const Edge &e = E[*it]; if (e.cap <= 0) continue; int cc = e.cost + phi[x] - phi[e.y]; if (dist[x] + cc < dist[e.y]) { dist[e.y] = dist[x] + cc; prev[e.y] = *it; Q[dist[e.y]].push(e.y); } } } } if (prev[t] == -1) break; int z = 1000000000; for (x = t; x != s; x = E[prev[x]].x) z = min(z, E[prev[x]].cap); for (x = t; x != s; x = E[prev[x]].x) { E[prev[x]].cap -= z; E[prev[x] ^ 1].cap += z; } flowVal += z; flowCost += z * (dist[t] - phi[s] + phi[t]); for (x = 0; x < N; x++) if (prev[x] != -1) phi[x] += dist[x]; } } } * mc; int a[90][90]; int main() { int i, j, k, n, m; scanf( %d %d , &n, &m); mc = new MCMF(n * m + 10); for (i = 0; i < n; i++) for (j = 0; j < m; j++) cin >> a[i][j]; int src = n * m + 1; int dest = n * m + 2; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if ((i + j) % 2 == 0) mc->add(src, i * m + j, 1, 0); else { mc->add(i * m + j, dest, 1, 0); continue; } for (k = 0; k < 4; k++) { int ni = i + dx[k]; int nj = j + dy[k]; if (ni < n && nj < m && ni >= 0 && nj >= 0) { mc->add(i * m + j, ni * m + nj, 1, a[i][j] != a[ni][nj]); } } } } int fval, fcost; mc->mcmf(src, dest, fval, fcost); cout << fcost << endl; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_dispv.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom_dispv (
address,
clock,
q);
input [5:0] address;
input clock;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire [5:0] q = sub_wire0[5:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({6{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./mif/disp_v.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 36,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 6,
altsyncram_component.width_a = 6,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./mif/disp_v.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "36"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "6"
// Retrieval info: PRIVATE: WidthData NUMERIC "6"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./mif/disp_v.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "36"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL "address[5..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q_a 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[5][5]; int b[] = {0, 1, 2, 3, 4}; long long sol() { int p0 = b[0]; int p1 = b[1]; int p2 = b[2]; int p3 = b[3]; int p4 = b[4]; long long p = a[p0][p1] + a[p1][p0] + a[p2][p3] + a[p3][p2]; p += a[p1][p2] + a[p2][p1] + a[p3][p4] + a[p4][p3]; p += a[p2][p3] + a[p3][p2]; p += a[p3][p4] + a[p4][p3]; return p; } int main() { for (long long i = 0; i < 5; i++) for (long long j = 0; j < 5; j++) cin >> a[i][j]; long long m = 0; do { m = max(sol(), m); } while (next_permutation(b, b + 5)); cout << m; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/17.0std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2017/01/22 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_stall.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`include "cross_module.h"
// L2 banks randomly stall PCX
// (stall is gated if it will cause a CAS1_RQ and CAS2_RQ to be separated, since
// this is legal only if the L2 IQ is full.)
module pcx_stall();
reg active;
wire clk;
wire cas1_grant_0, cas1_grant_1, cas1_grant_2, cas1_grant_3;
wire stall0, stall1, stall2, stall3;
reg stall0_d1, stall1_d1, stall2_d1, stall3_d1;
integer seed, max_stall, min_stall;
integer count0, count1, count2, count3, count4;
reg randstall0, randstall1, randstall2, randstall3, randstall4;
// pcx stall and release signals driven by pli event.
reg [3:0] stall_on;
reg [3:0] free_on;
wire [3:0] pli_stall_next;
reg [3:0] pli_stall;
initial begin
randstall0 = 0;
randstall1 = 0;
randstall2 = 0;
randstall3 = 0;
randstall4 = 0;
count0 = 0;
count1 = 0;
count2 = 0;
count3 = 0;
count4 = 0;
stall_on = 0;
free_on = 0;
pli_stall = 0;
if($test$plusargs("pcx_stall")) begin
active = 1;
if($value$plusargs("pcx_max_stall=%d", max_stall)) begin
end
else begin
max_stall = 150;
end
if($value$plusargs("pcx_min_stall=%d", min_stall)) begin
end
else begin
min_stall = 1;
end
if($value$plusargs("tg_seed=%d", seed)) begin
$display("Random PCX stalling activated (tg_seed = %d, max stall = %d, min stall = %d)", seed, max_stall, min_stall);
end
else begin
seed = 0;
$display("Random PCX stalling activated (default seed = 0, max stall = %d, min_stall=%d)", max_stall, min_stall);
end
end
else begin
active = 0;
end
end
`ifdef MSS_SAT
`else
always @(posedge clk) begin
$pc_trigger_event(4, 1, stall_on, free_on);
end
`endif
`ifdef RTL_CCX
assign clk = `TOP_DESIGN.ccx.rclk;
assign cas1_grant_0 = (`TOP_DESIGN.ccx.pcx.arb0.ccx_dest_data_rdy_x & `TOP_DESIGN.ccx.pcx.arb0.ccx_dest_atom_x);
assign cas1_grant_1 = (`TOP_DESIGN.ccx.pcx.arb1.ccx_dest_data_rdy_x & `TOP_DESIGN.ccx.pcx.arb1.ccx_dest_atom_x);
assign cas1_grant_2 = (`TOP_DESIGN.ccx.pcx.arb2.ccx_dest_data_rdy_x & `TOP_DESIGN.ccx.pcx.arb2.ccx_dest_atom_x);
assign cas1_grant_3 = (`TOP_DESIGN.ccx.pcx.arb3.ccx_dest_data_rdy_x & `TOP_DESIGN.ccx.pcx.arb3.ccx_dest_atom_x);
assign stall0 = (randstall0 | pli_stall[0]) & (`TOP_DESIGN.sctag0.iqctl.que_cnt < 5'd10);
assign stall1 = (randstall1 | pli_stall[1]) & (`TOP_DESIGN.sctag1.iqctl.que_cnt < 5'd10);
assign stall2 = (randstall2 | pli_stall[2]) & (`TOP_DESIGN.sctag2.iqctl.que_cnt < 5'd10);
assign stall3 = (randstall3 | pli_stall[3]) & (`TOP_DESIGN.sctag3.iqctl.que_cnt < 5'd10);
assign pli_stall_next = (stall_on | pli_stall) & ~free_on;
always @(posedge clk) begin
stall0_d1 <= stall0;
stall1_d1 <= stall1;
stall2_d1 <= stall2;
stall3_d1 <= stall3;
pli_stall <= pli_stall_next;
// 1) CAS1_RQ and CAS2_RQ must not be separated by this stall while in-flight to the L2
// 2) stall should be asserted only when L2 IQ has < 10 entries, so that it does not interfere with
// the stall from the L2
force `TOP_DESIGN.ccx.pcx.arb0.arbctl.stall2_a = stall0 & ~(~stall0_d1 & cas1_grant_0);
force `TOP_DESIGN.ccx.pcx.arb1.arbctl.stall2_a = stall1 & ~(~stall1_d1 & cas1_grant_1);
force `TOP_DESIGN.ccx.pcx.arb2.arbctl.stall2_a = stall2 & ~(~stall2_d1 & cas1_grant_2);
force `TOP_DESIGN.ccx.pcx.arb3.arbctl.stall2_a = stall3 & ~(~stall3_d1 & cas1_grant_3);
// FP1 and FP2 can be separated while in-flight to the FPU
force `TOP_DESIGN.ccx.pcx.arb4.arbctl.stall1_a = randstall4;
end
// L2 Bank 0
always @(posedge clk) begin
if(active) begin
count0 = ({$random(seed)} % max_stall) + min_stall;
repeat(count0) @(posedge clk);
randstall0 = 1;
count0 = ({$random(seed)} % max_stall) + min_stall;
repeat(count0) @(posedge clk);
randstall0 = 0;
end
else begin
randstall0 = 0;
end
end
// L2 Bank 1
always @(posedge clk) begin
if(active) begin
count1 = ({$random(seed)} % max_stall) + min_stall;
repeat(count1) @(posedge clk);
randstall1 = 1;
count1 = ({$random(seed)} % max_stall) + min_stall;
repeat(count1) @(posedge clk);
randstall1 = 0;
end
else begin
randstall1 = 0;
end
end
// L2 Bank 2
always @(posedge clk) begin
if(active) begin
count2 = ({$random(seed)} % max_stall) + min_stall;
repeat(count2) @(posedge clk);
randstall2 = 1;
count2 = ({$random(seed)} % max_stall) + min_stall;
repeat(count2) @(posedge clk);
randstall2 = 0;
end
else begin
randstall2 = 0;
end
end
// L2 Bank 3
always @(posedge clk) begin
if(active) begin
count3 = ({$random(seed)} % max_stall) + min_stall;
repeat(count3) @(posedge clk);
randstall3 = 1;
count3 = ({$random(seed)} % max_stall) + min_stall;
repeat(count3) @(posedge clk);
randstall3 = 0;
end
else begin
randstall3 = 0;
end
end
// IOB & FPU
always @(posedge clk) begin
if(active) begin
count4 = ({$random(seed)} % max_stall) + min_stall;
repeat(count4) @(posedge clk);
randstall4 = 1;
count4 = ({$random(seed)} % max_stall) + min_stall;
repeat(count4) @(posedge clk);
randstall4 = 0;
end
else begin
randstall4 = 0;
end
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_TB_V
`define SKY130_FD_SC_LP__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 10; int n, a[MAXN], d[MAXN]; bool pic[MAXN]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int temp; scanf( %d , &temp); pic[temp] = 1; } fill(d, d + MAXN, 1); int ans = 0; for (int i = 1; i < MAXN; i++) { if (pic[i]) ans = max(ans, d[i]); if (pic[i]) for (int j = i + i; j < MAXN; j += i) d[j] = max(d[j], d[i] + 1); } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k, t, a[200010], f[200010]; long long ans; struct nood { int x, id; } b[200010]; int cmp(nood a, nood b) { return a.x > b.x; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i].x = a[i]; b[i].id = i; } sort(b + 1, b + n + 1, cmp); for (int i = 1; i <= m * k; i++) { f[b[i].id] = 1; ans = ans + b[i].x; } printf( %lld n , ans); for (int i = 1; i <= n; i++) { if (f[i] == 1) t++; if (t == m + 1) { printf( %d , i - 1); t = 1; } } }
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module cselect(addr, cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7, cs_);
input [31:0] addr;
input cs_;
output cs0;
output cs1;
output cs2;
output cs3;
output cs4;
output cs5;
output cs6;
output cs7;
reg cs0 = 1;
reg cs1 = 1;
reg cs2 = 1;
reg cs3 = 1;
reg cs4 = 1;
reg cs5 = 1;
reg cs6 = 1;
reg cs7 = 1;
always @(*)
case( { addr[31:22], cs_ } )
11'h0: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
11'h2: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
11'h4: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
11'h6: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1 };
11'h8: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 };
11'ha: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 };
11'hc: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1 };
11'he: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 };
default: { cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7 } <= { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
endcase
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo_reg_based
*
*/
`default_nettype none
module openhmc_sync_fifo_reg_based #(
`ifdef CAG_ASSERTIONS
parameter DISABLE_EMPTY_ASSERT = 0,
parameter DISABLE_FULL_ASSERT = 0,
parameter DISABLE_SHIFT_OUT_ASSERT = 0,
parameter DISABLE_XCHECK_ASSERT = 0,
`endif
parameter DWIDTH = 8,
parameter ENTRIES = 4
) (
input wire clk,
input wire res_n,
input wire shift_in,
input wire shift_out,
input wire [DWIDTH-1:0] d_in,
output wire[DWIDTH-1:0] d_out,
output reg full,
output reg empty,
output reg almost_full,
output reg almost_empty
);
//the fifo_reg can currently only have up to 2047 entries
localparam LG_ENTRIES = (ENTRIES <= 2) ? 1 :
(ENTRIES <= 4) ? 2 :
(ENTRIES <= 8) ? 3 :
(ENTRIES <= 16) ? 4 :
(ENTRIES <= 32) ? 5 :
(ENTRIES <= 64) ? 6 : 7;
reg [DWIDTH-1:0] entry [0:ENTRIES-1];
reg [LG_ENTRIES:0] wp;
integer i;
wire shiftout_clean, shiftin_clean;
// first stage of fifo is output
assign d_out = entry[0];
assign shiftout_clean = shift_out && !empty;
assign shiftin_clean = shift_in && !full;
`ifdef ASYNC_RES
always @(posedge clk or negedge res_n) `else
always @(posedge clk) `endif
begin
if(!res_n) begin
wp <= {LG_ENTRIES+1 {1'b0}};
full <= 1'b0;
empty <= 1'b1;
almost_empty <= 1'b1;
almost_full <= 1'b0;
`ifdef FULL_RES
for (i=0; i<ENTRIES; i=i+1)
entry[i] <= {DWIDTH {1'b0}};
`endif
end else begin
case ({shiftin_clean, shiftout_clean})
2'b01: // only shift-out, move entries, decrement WP if not already 0 and check status signals
begin
for (i=1; i<ENTRIES; i=i+1)
entry[i-1] <= entry[i];
if (|wp)
wp <= wp - 1'b1;
empty <= (wp == {{LG_ENTRIES {1'b0}}, 1'b1});
full <= 1'b0;
almost_full <= (wp >= ENTRIES+1-1);
almost_empty <= (wp < 1 + 2);
end
2'b10: // only shift-in, write at next free entry, increment WP and check status signals
begin
entry[wp[LG_ENTRIES-1:0]] <= d_in;
wp <= wp + 1'b1;
empty <= 1'b0;
full <= (wp >= ENTRIES - 1);
almost_full <= (wp >= ENTRIES-1-1);
almost_empty <= (wp < 1);
end
2'b11: //simultaneous shift-in and -out, move entries through shift registers
begin
for (i=1; i<ENTRIES; i=i+1)
entry[i-1] <= entry[i];
entry[wp[LG_ENTRIES-1:0]-1'b1] <= d_in;
end
default: begin
end
endcase
end
end
`ifdef CAG_COVERAGE
full_cov: cover property (@(posedge clk) disable iff(!res_n) (full == 1'b1));
almost_full_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_full == 1'b1));
empty_cov: cover property (@(posedge clk) disable iff(!res_n) (empty == 1'b1));
almost_empty_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_empty == 1'b1));
covergroup shift_in_and_out @(posedge clk);
shift_in_and_out_cp: coverpoint ({shift_in, shift_out}) iff (shift_in || shift_out)
{
bins count[] = {[1:3]};
}
endgroup
shift_in_and_out shift_in_and_out_I;
initial begin
shift_in_and_out_I = new();
shift_in_and_out_I.set_inst_name("shift_in_and_out_I");
end
`endif // CAG_COVERAGE
`ifdef CAG_ASSERTIONS
// when the FIFO signals empty, it must logically also be almost empty
empty_means_aempty : assert property (@(posedge clk) disable iff(!res_n) empty |-> almost_empty);
wp_eq_0_means_empty_A : assert property (@(posedge clk) disable iff(!res_n) (wp==0) |-> empty);
wp_eq_0_means_empty_B : assert property (@(posedge clk) disable iff(!res_n) empty |-> (wp==0));
aempty_condition_A : assert property (@(posedge clk) disable iff(!res_n) (wp>1) |-> !almost_empty);
aempty_condition_B : assert property (@(posedge clk) disable iff(!res_n) !almost_empty |-> (wp>1));
shift_in_and_full: assert property (@(posedge clk) disable iff(!res_n) (shift_in |-> !full));
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_FULL_ASSERT == 0)
begin
assert_full_set: assert (!full);
assert_almost_full_set: assert (!almost_full);
end
if (DISABLE_EMPTY_ASSERT == 0)
begin
assert_write_pointer_not_zero: assert (wp == 0);
assert_almost_empty_not_set: assert (almost_empty);
assert_empty_not_set: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, m; char mp[510][510]; int minln, maxln, minrw, maxrw, cnt; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %s , mp[i] + 1); minln = n + 1; maxln = 0; minrw = m + 1; maxrw = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (mp[i][j] == X ) { minln = min(i, minln); minrw = min(j, minrw); maxln = max(i, maxln); maxrw = max(j, maxrw); cnt++; } if (minln > maxln || minrw > maxrw || (maxln - minln + 1) * (maxrw - minrw + 1) != cnt) printf( NO n ); else printf( YES n ); return 0; }
|
`include "defines.v"
module connectRouter
#(parameter addr = 4'b0000) //No. 0 connect router, port 0
(
input `control_w port_in,
input `control_w inj,
input clk,
input rst,
output `control_w port_out,
output `control_w bout,
output accept,
input can_pop,
output [2:0] size,
output bfull
);
wire `control_w port_0;
assign port_0 = (rst) ? `control_n'd0 : port_in;
wire bfull;
wire productive;
wire can_push;
wire can_pop;
wire `control_w bout;
wire [2:0] bsize;
buffer bf(
.in(port_r_0),
.clk(clk),
.rst(rst),
.push(can_push),
.pop(can_pop),
.out(bout),
.full(bfull),
.bsize(size)
);
/************* STAGE 1 *************/
reg `control_w port_r_0, port_r_1;
wire `control_w port_1, port_2;
always @(posedge clk) begin
port_r_0 <= port_0;
end
assign productive = (port_r_0[`dest_f] < 4 || port_r_0[`dest_f] > 11)? 0 : 1;
assign can_push = productive && ~bfull;
assign port_1 = can_push ? 0 : port_r_0;
assign accept = (~port_1[`valid_f] & inj[`valid_f]);
assign port_2 = accept ? inj : port_1;
/*********** STAGE 2 ***************/
always @ (posedge clk) begin
port_r_1 <= port_2;
end
assign port_out = port_r_1;
endmodule
module buffer
#(parameter buffersize = 8)
(
input `control_w in,
input clk,
input rst,
output `control_w out,
input push,
input pop,
output full,
output [2:0] bsize
);
reg [2:0] head, tail;
reg [2:0] size;
integer n;
reg `control_w rf[buffersize-1:0];
always @ rst begin
head <= 0;
tail <= 0;
size <= 0;
for (n = 0; n < 8; n = n + 1)
rf[n] <= 0;
end
assign out = rf[head];
assign full = (size == 7);
assign bsize = size;
always @ (posedge clk) begin
if (push && pop) begin
rf[tail] <= in;
tail <= tail + 1;
head <= head + 1;
end
else if (push) begin
rf[tail] <= in;
tail <= tail + 1;
size <= size + 1;
end
else if (pop) begin
head <= head + 1;
size = size - 1;
end
else
;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int cnt; string s; stack<int> st; int main() { cin >> s; for (int i = 0; i < s.size(); ++i) { if (s[i] == ( || s[i] == [ || s[i] == { || s[i] == < ) { st.push(int(s[i])); } else { if (st.empty()) { cout << Impossible ; return 0; } if (st.top() == 40) { if (int(s[i]) != 41) { cnt++; } if (!st.empty()) st.pop(); } else { if (st.top() + 2 != int(s[i])) { cnt++; } if (!st.empty()) st.pop(); } } } if (!st.empty()) { cout << Impossible ; return 0; } cout << cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; const long long int P = 1000000007; const double eps = 1e-6; int val[N]; int deg[N]; vector<int> gr[N]; vector<long long int> mx(N); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; long long int ans = 0; for (int i = 0; i < n; i++) { cin >> val[i]; ans += val[i]; } for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; gr[u].push_back(v); gr[v].push_back(u); deg[u]++, deg[v]++; } int start; cin >> start; start--; stack<int> st; for (int i = 0; i < n; i++) if (deg[i] == 1 && i != start) st.push(i); long long int maxall = 0; while (!st.empty()) { int now = st.top(); st.pop(); deg[now]--; ans -= val[now]; for (auto i : gr[now]) { if (deg[i]) { deg[i]--; if (deg[i] == 1 && i != start) st.push(i); mx[i] = max((long long int)mx[i], (long long int)mx[now] + (long long int)val[now]); maxall = max(maxall, mx[i]); } } } cout << ans + maxall; cerr << nTime elapsed : << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int main() { int x, y, a, b; cin >> x >> y >> a >> b; int t = gcd(a, b); a /= t; b /= t; x /= a; y /= b; cout << a * min(x, y) << << b * min(x, y); cin >> a; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int vp, vd, t, f, c, ans = 0; double tempt; double curs = 0; cin >> vp >> vd >> t >> f >> c; curs = vp * t; if (vp >= vd) { cout << 0 << endl; return 0; } while (curs < c) { tempt = curs / (vd - vp); curs += tempt * vp; if (curs >= c) break; else curs += (tempt + f) * vp; ans++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int max(int a, int b) { if (a > b) return a; else return b; } int main() { int n, m, p, r, x, y, c, i, j, zb, maxz; int max1, max2, max3, max4, minz; scanf( %d %d , &n, &m); scanf( %d , &c); for (i = 1; i <= c; i++) { scanf( %d %d , &x, &y); if (i == 1) max1 = x + y, max2 = x - y, max3 = -x + y, max4 = -x - y; if (i > 1 && x + y > max1) max1 = x + y; if (i > 1 && x - y > max2) max2 = x - y; if (i > 1 && -x + y > max3) max3 = -x + y; if (i > 1 && -x - y > max4) max4 = -x - y; } scanf( %d , &r); for (i = 1; i <= r; i++) { scanf( %d %d , &x, &y); maxz = max(max1 - (x + y), max2 - (x - y)); maxz = max(maxz, max3 - (-x + y)); maxz = max(maxz, max4 - (-x - y)); if (i == 1) minz = maxz, zb = 1; if (i > 1 && maxz < minz) minz = maxz, zb = i; } printf( %d n , minz); printf( %d n , zb); }
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#include <bits/stdc++.h> using namespace std; int find_set(int v, vector<int> &p) { if (v == p[v]) return v; return p[v] = find_set(p[v], p); } void union_set(int a, int b, vector<int> &p) { a = find_set(a, p); b = find_set(b, p); if (a != b) { p[b] = a; } } long long int ans = 0; void dfs(int i, vector<int> &vis, vector<int> adj[]) { vis[i] = 1; for (int k = 0; k < adj[i].size(); k++) { if (vis[adj[i][k]] == 0) { dfs(adj[i][k], vis, adj); } } } void solve() { int n, m; cin >> n >> m; vector<int> adj[n]; int a, b; for (int i = 0; i < m; i++) { cin >> a >> b; a--; b--; adj[a].push_back(b); adj[b].push_back(a); } vector<int> vis(n, 0); dfs(0, vis, adj); if (find(vis.begin(), vis.end(), 0) != vis.end()) { cout << NO << endl; return; } if (m - n + 1 == 1) { cout << FHTAGN! << endl; return; } cout << NO << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int T; T = 1; while (T--) { solve(); } return 0; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:06 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axi_gpio_1_0 -prefix
// design_1_axi_gpio_1_0_ design_1_axi_gpio_1_0_stub.v
// Design : design_1_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module design_1_axi_gpio_1_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
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#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; const int N = 3e3; long long dmod(long long x) { return x % MOD; } int n, k; int h[N + 5]; long long memo[N + 5][2 * N + 5]; long long dp(int idx, int gap) { if (idx > n) { if (gap > 0) return 1; return 0; } long long &ret = memo[idx][gap + N]; if (ret != -1) return ret; ret = 0ll; if (h[idx] == h[idx % n + 1]) { ret = dmod((long long)k * dp(idx + 1, gap)); } else { ret = dp(idx + 1, gap + 1); ret = dmod(ret + dp(idx + 1, gap - 1)); ret = dmod(ret + dmod((long long)(k - 2) * dp(idx + 1, gap))); } return ret; } int main() { memset(memo, -1, sizeof(memo)); scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { scanf( %d , &h[i]); } printf( %lld n , dp(1, 0)); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_BEHAVIORAL_V
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