text
stringlengths 59
71.4k
|
|---|
// File: fifo_mem.v
// Generated by MyHDL 0.10
// Date: Tue Aug 21 12:53:38 2018
`timescale 1ns/10ps
module fifo_mem (
wr,
rd,
data_in,
fifo_full,
fifo_empty,
fifo_threshold,
fifo_overflow,
fifo_underflow,
data_out,
clk,
rst_n,
clear
);
// Input:
// wr(bool):write signal
// rd(bool):write signal
// data_in(8bit): data to be writen
// clk(bool): clock
// rst_n(bool): negtive reset signal
// clear(bool): signal to clear clear memeory to 0
//
// Output:
// fifo_full(bool): signal indicating the fifo memory is full
// fifo_empty(bool):signal indicating the fifo memory is empty
// fifo_threshold(bool): signal indicating that the fifo is about to overflow
// fifo_overflow(bool): signal indicating that the fifo has overflowed
// fifo_underflow(bool): signal indicating that the fifo has underflowed
// data_out(8bit): data to be read out
input wr;
input rd;
input [7:0] data_in;
output fifo_full;
wire fifo_full;
output fifo_empty;
wire fifo_empty;
output fifo_threshold;
wire fifo_threshold;
output fifo_overflow;
wire fifo_overflow;
output fifo_underflow;
wire fifo_underflow;
output [7:0] data_out;
wire [7:0] data_out;
input clk;
input rst_n;
input clear;
wire [4:0] wptr;
wire fifo_we;
wire [4:0] rptr;
wire fifo_rd;
wire write_pointer0_0_1_fifo_we_i;
reg [4:0] write_pointer0_0_1_wptr_i = 0;
wire read_pointer0_0_1_fifo_rd_i;
reg [4:0] read_pointer0_0_1_rptr_i = 0;
reg fifoStatus0_0_1_underflow_set = 0;
reg signed [4:0] fifoStatus0_0_1_pointer_result = 0;
reg fifoStatus0_0_1_pointer_equal = 0;
reg fifoStatus0_0_1_overflow_set = 0;
reg fifoStatus0_0_1_fifo_underflow_i = 0;
reg fifoStatus0_0_1_fifo_threshold_i = 0;
reg fifoStatus0_0_1_fifo_overflow_i = 0;
reg fifoStatus0_0_1_fifo_full_i = 0;
reg fifoStatus0_0_1_fifo_empty_i = 0;
reg fifoStatus0_0_1_fbit_comp = 0;
reg [7:0] memory_array0_0_1_data_out_i [0:16-1];
initial begin: INITIALIZE_MEMORY_ARRAY0_0_1_DATA_OUT_I
integer i;
for(i=0; i<16; i=i+1) begin
memory_array0_0_1_data_out_i[i] = 0;
end
end
assign write_pointer0_0_1_fifo_we_i = ((!fifo_full) && wr);
always @(posedge clk, negedge rst_n) begin: FIFO_MEM_WRITE_POINTER0_0_1_POINTERUPDATE
if (rst_n) begin
write_pointer0_0_1_wptr_i <= 0;
end
else if (write_pointer0_0_1_fifo_we_i) begin
write_pointer0_0_1_wptr_i <= (write_pointer0_0_1_wptr_i + 1);
end
else begin
write_pointer0_0_1_wptr_i <= write_pointer0_0_1_wptr_i;
end
end
assign fifo_we = write_pointer0_0_1_fifo_we_i;
assign wptr = write_pointer0_0_1_wptr_i;
assign read_pointer0_0_1_fifo_rd_i = ((!fifo_empty) && rd);
always @(posedge clk, negedge rst_n) begin: FIFO_MEM_READ_POINTER0_0_1_POINTERUPDATE
if (rst_n) begin
read_pointer0_0_1_rptr_i <= 0;
end
else if (read_pointer0_0_1_fifo_rd_i) begin
read_pointer0_0_1_rptr_i <= (read_pointer0_0_1_rptr_i + 1);
end
else begin
read_pointer0_0_1_rptr_i <= read_pointer0_0_1_rptr_i;
end
end
assign fifo_rd = read_pointer0_0_1_fifo_rd_i;
assign rptr = read_pointer0_0_1_rptr_i;
always @(posedge clk) begin: FIFO_MEM_MEMORY_ARRAY0_0_1_UPTAKE
if (fifo_we) begin
memory_array0_0_1_data_out_i[wptr[4-1:0]] <= data_in;
end
end
assign data_out = memory_array0_0_1_data_out_i[rptr[4-1:0]];
always @(negedge clear) begin: FIFO_MEM_MEMORY_ARRAY0_0_1_CLEARMEM
integer i;
for (i=0; i<16; i=i+1) begin
memory_array0_0_1_data_out_i[i] <= 0;
end
end
always @(fifoStatus0_0_1_fifo_full_i, fifoStatus0_0_1_fifo_empty_i, rd, wptr, wr, rptr) begin: FIFO_MEM_FIFOSTATUS0_0_1_LOGIC1
fifoStatus0_0_1_fbit_comp = (wptr[4] ^ rptr[4]);
if (($signed({1'b0, wptr[3-1:0]}) - rptr[3-1:0])) begin
fifoStatus0_0_1_pointer_equal = 0;
end
else begin
fifoStatus0_0_1_pointer_equal = 1;
end
fifoStatus0_0_1_pointer_result = (wptr[4-1:0] - rptr[4-1:0]);
fifoStatus0_0_1_overflow_set = (fifoStatus0_0_1_fifo_full_i & wr);
fifoStatus0_0_1_underflow_set = (fifoStatus0_0_1_fifo_empty_i & rd);
end
always @(fifoStatus0_0_1_fbit_comp, fifoStatus0_0_1_pointer_result, fifoStatus0_0_1_pointer_equal) begin: FIFO_MEM_FIFOSTATUS0_0_1_LOGIC2
fifoStatus0_0_1_fifo_full_i = (fifoStatus0_0_1_fbit_comp & fifoStatus0_0_1_pointer_equal);
fifoStatus0_0_1_fifo_empty_i = ((!fifoStatus0_0_1_fbit_comp) & fifoStatus0_0_1_pointer_equal);
if ((fifoStatus0_0_1_pointer_result[4] || fifoStatus0_0_1_pointer_result[3])) begin
fifoStatus0_0_1_fifo_threshold_i = 1;
end
else begin
fifoStatus0_0_1_fifo_threshold_i = 0;
end
end
always @(posedge clk, negedge rst_n) begin: FIFO_MEM_FIFOSTATUS0_0_1_OVERFLOWCONTROL
if (rst_n) begin
fifoStatus0_0_1_fifo_overflow_i <= 0;
end
else if (((fifoStatus0_0_1_overflow_set == 1) && (fifo_rd == 0))) begin
fifoStatus0_0_1_fifo_overflow_i <= 1;
end
else if (fifo_rd) begin
fifoStatus0_0_1_fifo_overflow_i <= 0;
end
else begin
fifoStatus0_0_1_fifo_overflow_i <= fifoStatus0_0_1_fifo_overflow_i;
end
end
always @(posedge clk, negedge rst_n) begin: FIFO_MEM_FIFOSTATUS0_0_1_UNDERFLOWCONTROL
if (rst_n) begin
fifoStatus0_0_1_fifo_underflow_i <= 0;
end
else if (((fifoStatus0_0_1_underflow_set == 1) && (fifo_we == 0))) begin
fifoStatus0_0_1_fifo_underflow_i <= 1;
end
else if (fifo_we) begin
fifoStatus0_0_1_fifo_underflow_i <= 0;
end
else begin
fifoStatus0_0_1_fifo_underflow_i <= fifoStatus0_0_1_fifo_underflow_i;
end
end
assign fifo_full = fifoStatus0_0_1_fifo_full_i;
assign fifo_empty = fifoStatus0_0_1_fifo_empty_i;
assign fifo_threshold = fifoStatus0_0_1_fifo_threshold_i;
assign fifo_overflow = fifoStatus0_0_1_fifo_overflow_i;
assign fifo_underflow = fifoStatus0_0_1_fifo_underflow_i;
endmodule
|
#pragma GCC optimize( Ofast ) #include bits/stdc++.h typedef long long ll; using namespace std; #define sim template < class c #define ris return * this #define dor > debug & operator << #define eni(x) sim > typename enable_if<sizeof dud<c>(0) x 1, debug&>::type operator<<(c i) { sim > struct rge { c b, e; }; sim > rge<c> range(c i, c j) { return rge<c>{i, j}; } sim > auto dud(c* x) -> decltype(cerr << *x, 0); sim > char dud(...); struct debug { // #ifdef LOCAL ~debug() { cerr << endl; } eni(!=) cerr << boolalpha << i; ris; } eni(==) ris << range(begin(i), end(i)); } sim, class b dor(pair < b, c > d) { ris << ( << d.first << , << d.second << ) ; } sim dor(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; ris << ] ; } // sim dor(const c&) { ris; } }; #ifdef ASJKD } #endif #define imie(...) [ << #__VA_ARGS__ : << (__VA_ARGS__) << ] #define read(x) for(auto &i : (x)){cin>>i;} #define all(x) begin(x), end(x) #define pb push_back #define pii pair<int,int> #define maxn 100005 ll mod = 1e9+7; int INF = 1e9+1e8+1e7; ll INF64 = 1e18; long long binpow(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1){ res = res * a % m; } a = a * a % m; b >>= 1; } return res; } vector<vector<int>> pfs(maxn); vector<bool> isprime(maxn, 1); void sieve(int mx){ for(int i=2;i<mx;i++){ if(isprime[i]){ for(int j=i;j<mx;j+=i){ isprime[j]=0; pfs[j].pb(i); } } } } void test_case(int tnum){ int n,q; cin>>n>>q; vector<int> a(n); read(a); vector<int> go(n+1, n); vector<int> last(maxn, n); for(int i=n-1;i>=0;i--){ for(int j : pfs[a[i]]){ go[i]=min(go[i], last[j]); last[j] = min(last[j], i); } go[i] = min(go[i], go[i+1]); } // debug() << imie(go); vector<vector<int>> lift(20, vector<int>(n+1, n)); for(int i=0;i<n;i++){ lift[0][i] = go[i]; } for(int i=1;i<20;i++){ for(int j=0;j<n;j++){ lift[i][j]=lift[i-1][lift[i-1][j]]; } } for(int rep=0;rep<q;rep++){ int l, r; cin>>l>>r; --l,--r; int cur=l; int ans =0; while(true){ if(go[cur] > r){ ans++; break; } for(int i=19;i>=0;i--){ if(lift[i][cur]<=r){ ans += 1<<(i); cur = lift[i][cur]; break; } } } cout<<ans<< n ; } } int main(){ cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(false); int t=1; sieve(maxn); // cin>>t; for(int test=1;test<=t;test++){ test_case(test); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { int n, tmp = 1, res = 1; cin >> n; int A[n][2]; for (int i = 0; i < n; i++) cin >> A[i][0] >> A[i][1]; for (int i = 0; i < n - 1; i++) { if ((A[i][0] == A[i + 1][0]) && (A[i][1] == A[i + 1][1])) { tmp++; if (res < tmp) res = tmp; } else tmp = 1; } cout << res << endl; return EXIT_SUCCESS; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 707406378; const int maxn = 1.5e7 + 10; void read(long long &x) { char ch; bool flag = 0; for (ch = getchar(); !isdigit(ch) && ((flag |= (ch == - )) || 1); ch = getchar()) ; for (x = 0; isdigit(ch); x = (x << 1) + (x << 3) + ch - 48, ch = getchar()) ; x *= 1 - 2 * flag; } int main() { long long n, x, y; cin >> n; long long ans = 0; for (int i = 0; i < n; i++) { cin >> x >> y; ans = max(ans, x + y); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a[345678], b[456111], c, n, i, l, s = 0, k = 0, m, j, t, x, y; string p, q, r, rr; int main() { cin >> n >> m; for (i = 0; i < m; i++) { a[i] = n / m; } for (i = 1; i <= n % m; i++) a[i]++; for (i = 0; i < m; i++) { for (j = 0; j < m; j++) { if ((i * i + j * j) % m == 0) { s += a[i] * a[j]; } } } cout << s << endl; }
|
#include <bits/stdc++.h> using namespace std; int AA[100010]; int BB[100010]; long long dp[100010]; int N; vector<long long> M; vector<long long> B; bool bad(long long l1, long long l2, long long l3) { long double XX1 = 1.00000 * (M[l1] - M[l2]) / (M[l1] - M[l3]); long double XX2 = 1.00000 * (B[l2] - B[l1]) / (B[l3] - B[l1]); return XX1 < XX2; } void add(long long m, long long b) { M.push_back(m); B.push_back(b); while (M.size() >= 3 && bad(M.size() - 3, M.size() - 2, M.size() - 1)) { M.erase(M.end() - 2); B.erase(B.end() - 2); } } int pointer; long long query(long long x) { if (pointer >= M.size()) pointer = M.size() - 1; while (pointer < M.size() - 1 && M[pointer + 1] * x + B[pointer + 1] > M[pointer] * x + B[pointer]) pointer++; return M[pointer] * x + B[pointer]; } int main() { ios_base::sync_with_stdio(0); cin >> N; for (int i = 1; i <= N; i++) { cin >> AA[i]; } for (int i = 1; i <= N; i++) { cin >> BB[i]; } dp[1] = 0LL; add(-BB[1], -dp[1]); for (int i = 2; i <= N; i++) { dp[i] = -1LL * query(AA[i]); add(-BB[i], -dp[i]); } cout << dp[N] << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long n, m, cnt[55], used[55], add[55]; bool vis[55]; vector<long long> v[55], p; pair<long long, long long> it[55]; long long fa[55]; long long getfa(long long x) { if (x == fa[x]) return x; else return fa[x] = getfa(fa[x]); } void update(long long x, long long y) { x = getfa(x); y = getfa(y); fa[x] = y; } void dfs(long long x) { if (vis[x]) return; vis[x] = 1; p.emplace_back(x); for (auto u : v[x]) { dfs(u); } } signed main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; long long x, y; for (long long i = 1; i <= m; i++) { cin >> x >> y; v[x].emplace_back(y); v[y].emplace_back(x); } long long cnt = 0; for (long long i = 1; i <= n; i++) if (!vis[i]) { p.clear(); dfs(i); long long lst = cnt; for (auto u : p) { if (v[u].size() > 2) { cout << NO ; return 0; } if (v[u].size() == 1) { if (cnt && it[cnt].second == 0) { it[cnt].second = u; } else { it[++cnt].first = u; } } if (v[u].empty()) { it[++cnt] = make_pair(u, u); } } if (lst == cnt) { if (p.size() == n) { cout << YES n0 ; return 0; } else { cout << NO ; return 0; } } } for (long long i = 1; i <= n; i++) fa[i] = i; for (long long i = 1; i <= cnt; i++) { if (it[i].first > it[i].second) swap(it[i].first, it[i].second); used[it[i].first]++; used[it[i].second]++; add[it[i].first] = add[it[i].second] = i; } sort(it + 1, it + cnt + 1); cout << YES n ; cout << cnt << n ; for (long long i = 1; i <= n; i++) { while (used[i]) { bool f = 1; for (long long j = i + 1; j <= n; j++) if (used[j]) { if (getfa(add[i]) != getfa(add[j])) { cout << i << << j << n ; update(add[i], add[j]); used[i]--; used[j]--; f = 0; break; } } if (f) break; } } for (long long i = 1; i <= n; i++) { while (used[i]) { cout << i << ; used[i]--; } } return 0; }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'h98967;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 35175;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 9;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_PP_SYMBOL_V
|
module Datapath(
output [3:0] FLAG_out, // Flag Bus
output [WORD_WIDTH-1:0] A_bus, // Address out Bus
output [WORD_WIDTH-1:0] D_bus, // Data out Bus
output [WORD_WIDTH-1:0] D_bus_internal, // Internal data bus output for monitoring
input [WORD_WIDTH-1:0] D_in, // Data in bus
input [CNTRL_WIDTH-1:0] CNTRL_in, // Instruction Bus
input [WORD_WIDTH-1:0] CONST_in, // Constant In Bus
input CLK
);
assign D_bus_internal = BMD_out;
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter CNTRL_WIDTH = SB_WIDTH+SA_WIDTH+DR_WIDTH+11;
wire [DR_WIDTH:0] DA = CNTRL_in[];
wire [SA_WIDTH:0] AA = CNTRL_in[];
wire [SA_WIDTH:0] BA = CNTRL_in[];
wire [WORD_WIDTH-1:0] RF0_out_B, BMD_out, FU0_out;
Datapath_RegisterFile RF0(
.A_data(A_bus),
.B_data(RF0_out_B),
.D_data(BMD_out),
.BA(CNTRL_in[SB_WIDTH-1+11:11]),
.AA(CNTRL_in[SA_WIDTH-1+SB_WIDTH+11:SB_WIDTH+11]),
.DA(CNTRL_in[DR_WIDTH-1+SB_WIDTH+SA_WIDTH+11:SB_WIDTH+SA_WIDTH+11]),
.RW(CNTRL_in[0]),
.CLK(CLK)
);
defparam RF0.WORD_WIDTH = WORD_WIDTH;
defparam RF0.DR_WIDTH = DR_WIDTH;
Datapath_BusMuxer BMB(
.out(D_bus),
.A_in(RF0_out_B),
.B_in(CONST_in),
.S(CNTRL_in[6])
);
defparam BMB.WORD_WIDTH = WORD_WIDTH;
defparam BMB.DR_WIDTH = DR_WIDTH;
Datapath_BusMuxer BMD(
.out(BMD_out),
.A_in(FU0_out),
.B_in(D_in),
.S(CNTRL_in[1])
);
defparam BMD.WORD_WIDTH = WORD_WIDTH;
defparam BMD.DR_WIDTH = DR_WIDTH;
Datapath_FunctionUnit FU0(
.F(FU0_out),
.V(FLAG_out[3]),
.C(FLAG_out[2]),
.N(FLAG_out[1]),
.Z(FLAG_out[0]),
.A(A_bus),
.B(D_bus),
.FS(CNTRL_in[9:6])
);
defparam FU0.WORD_WIDTH = WORD_WIDTH;
defparam FU0.DR_WIDTH = DR_WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; int lim = 1e6; int inf = 1e9 + 7; bool ispal(string s) { int n = s.size(); bool ans = true; for (int i = 0; i < n / 2; i++) { if (s[i] != s[n - i - 1]) { ans = false; break; } } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { string s; cin >> s; if (!ispal(s)) { cout << s << n ; ; } else { char x = s[0]; bool check = false; string ans = s; for (int i = 1; i < s.size(); i++) { if (x != s[i]) { check = true; ans[0] = ans[i]; ans[i] = x; break; } } if (check) { cout << ans << n ; ; } else { cout << -1 << n ; ; } } } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, count = 0; cin >> n; for (int i = 0; i < n; i++) { int x; scanf( %1d , &x); if (x) { count++; continue; } break; } cout << min(count + 1, n); return 0; }
|
#include <bits/stdc++.h> using namespace std; char mat[110][110]; int main() { int r, c; int cnt = 0; int status = 0; int i, j; scanf( %d%d , &r, &c); for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { scanf( %c , &mat[i][j]); } getchar(); } for (i = 0; i < c; i++) { if (status == 0 && mat[r - 1][i] == B ) { status = 1; cnt++; } if (mat[r - 1][i] == . ) { status = 0; } } printf( %d n , cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; int inf = (1 << 30) - 1, n, X, x, y, z, f[510][510], c[510], R, g[510][510], size[510], h[2][510], H[2][510][510], q[510], L[510]; int Lng[510]; double a[510][510]; vector<int> E[510]; void read(int &x) { char ch = getchar(); int mark = 1; for (; ch != - && (ch < 0 || ch > 9 ); ch = getchar()) ; if (ch == - ) mark = -1, ch = getchar(); for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 48; x *= mark; } double Solve(int m, int n) { bool flag = 1; for (; flag;) { flag = 0; for (int i = 1; i <= n; i++) if (a[0][i] > 0) { double Min = inf; int l; for (int j = 1; j <= m; j++) if (a[j][i] < 0) { double tmp = -a[j][0] / a[j][i]; if (Min > tmp) Min = tmp, l = j; } if (Min == inf) continue; flag = 1; double tmp = -a[l][i]; a[l][i] = -1; for (int j = 0; j <= n; j++) a[l][j] /= tmp; for (int j = 0; j <= m; j++) if (a[j][i] && j != l) { for (int k = 0; k <= n; k++) if (k != i) a[j][k] += a[j][i] * a[l][k]; a[j][i] *= a[l][i]; } } } return a[0][0]; } void dfs(int u, int pre) { int cnt = 0; for (int i = 0; i < E[u].size(); i++) if (E[u][i] != pre) { dfs(E[u][i], u); ++cnt; Lng[u] = max(Lng[u], min(Lng[E[u][i]] + f[u][E[u][i]], inf)); } size[u] = 1; int A = 0; for (int j = 0; j <= R; j++) h[A][j] = inf; for (int Bg = 0; Bg <= cnt; Bg++) for (int j = 0; j <= R; j++) H[A][Bg][j] = inf; H[A][0][0] = inf - 1; h[A][1] = 0; cnt = 0; L[0] = -inf; for (int i = 0; i < E[u].size(); i++) if (E[u][i] != pre) { int v = E[u][i]; q[++cnt] = v; L[cnt] = min(inf, f[u][v] + Lng[v]); A ^= 1; for (int j = 0; j <= R; j++) h[A][j] = inf; for (int Bg = 0; Bg <= cnt; Bg++) for (int j = 0; j <= R; j++) H[A][Bg][j] = inf; for (int k = 0; k <= size[u] && k <= R; k++) for (int j = 0; j <= size[v] && j + k <= R; j++) { if (j == 0 && max(h[A ^ 1][k], Lng[v] + f[u][v]) <= X) h[A][j + k] = 0; if (j && g[v][j] != inf && max(h[A ^ 1][k], min(g[v][j], f[u][v])) <= X) h[A][j + k] = 0; } for (int Bg = 0; Bg < cnt; Bg++) for (int k = 0; k <= size[u] && k <= R; k++) if (H[A ^ 1][Bg][k] != inf) { for (int j = 1; j + k <= R && j <= size[v]; j++) if (g[v][j] <= X) H[A][Bg][j + k] = min(H[A][Bg][j + k], min(H[A ^ 1][Bg][k], g[v][j] + f[u][v])); if (L[cnt] > L[Bg]) H[A][cnt][k] = min(H[A][cnt][k], H[A ^ 1][Bg][k]); else H[A][Bg][k] = min(H[A][Bg][k], H[A ^ 1][Bg][k]); } size[u] += size[v]; } for (int j = 0; j <= R; j++) g[u][j] = h[A][j]; for (int Bg = 0; Bg <= cnt; Bg++) for (int j = 0; j <= R; j++) if (H[A][Bg][j] + L[Bg] <= X) g[u][j] = min(g[u][j], H[A][Bg][j]); } bool check() { for (int i = 1; i <= n; i++) for (int j = 0; j <= n; j++) g[i][j] = inf; dfs(1, 0); return (g[1][R] <= X); } int main() { read(n); read(X); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) f[i][j] = inf; f[i][i] = 0; read(c[i]); R += c[i]; } for (int i = 1; i < n; i++) { read(x); read(y); read(z); f[x][y] = f[y][x] = z; E[x].push_back(y); E[y].push_back(x); } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) if (i ^ k) for (int j = 1; j <= n; j++) if ((i ^ j) && (k ^ j)) f[i][j] = min(f[i][k] + f[k][j], f[i][j]); if (!check()) { printf( -1 n ); return 0; } a[0][n + 1] = -R; for (int i = 1; i <= n; i++) { a[0][i] = 1; a[i][n + 1] = 1; a[i][0] = c[i] ^ 1; for (int j = 1; j <= n; j++) a[i][j] = -(f[i][j] <= X); } printf( %.0lf n , Solve(n, n + 1)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_4TO2_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_MUX_4TO2_SYMBOL_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_mux_4to2 (
//# {{data|Data Signals}}
input A0,
input A1,
input A2,
input A3,
output X ,
//# {{control|Control Signals}}
input S0,
input S1
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_4TO2_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4B_PP_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, i, ans, arr[100005]; ans = 0; cin >> n; for (i = 0; i < n; i++) cin >> arr[i]; for (i = 1; i < n; i++) { if (arr[i] < arr[i - 1]) ans += arr[i - 1] - arr[i]; } cout << ans; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
string s[] = { "hello", "sad", "sad", "world" };
initial begin
int d[];
int de[]; // Empty
int qv[$]; // Value returns
int qvunused[$]; // Value returns (unused)
int qi[$]; // Index returns
int i;
string v;
d = '{1, 2, 2, 4, 3};
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h4, 'h3} ");
d = {1, 2, 2, 4, 3};
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h4, 'h3} ");
// sort/rsort with clause is the field to use for the sorting
d.sort;
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h3, 'h4} ");
d.sort with (10 - item);
v = $sformatf("%p", d); `checks(v, "'{'h4, 'h3, 'h2, 'h2, 'h1} ");
d.sort(x) with (10 - x);
v = $sformatf("%p", d); `checks(v, "'{'h4, 'h3, 'h2, 'h2, 'h1} ");
de.sort(x) with (10 - x);
v = $sformatf("%p", de); `checks(v, "'{}");
d.rsort;
v = $sformatf("%p", d); `checks(v, "'{'h4, 'h3, 'h2, 'h2, 'h1} ");
d.rsort with (10 - item);
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h3, 'h4} ");
de.rsort(x) with (10 - x);
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h3, 'h4} ");
d = '{2, 2, 4, 1, 3};
qv = d.unique;
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h4, 'h1, 'h3} ");
qv = de.unique;
`checkh(qv.size(), 0);
qi = d.unique_index; qv.sort;
v = $sformatf("%p", qi); `checks(v, "'{'h0, 'h2, 'h3, 'h4} ");
qi = de.unique_index;
`checkh(qi.size(), 0);
d.reverse;
v = $sformatf("%p", d); `checks(v, "'{'h3, 'h1, 'h4, 'h2, 'h2} ");
de.reverse;
`checkh(de.size(), 0);
d.shuffle(); d.sort;
v = $sformatf("%p", d); `checks(v, "'{'h1, 'h2, 'h2, 'h3, 'h4} ");
de.shuffle();
`checkh(de.size(), 0);
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = d.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} ");
qv = d.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = d.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = d.find with (item == 20);
`checkh(qv.size, 0);
qv = d.find_first with (item == 20);
`checkh(qv.size, 0);
qv = d.find_last with (item == 20);
`checkh(qv.size, 0);
// Check gate eater with Lambda variable removal
qvunused = d.find with (item == 20);
qi = d.find_index with (item == 2);
qi.sort; v = $sformatf("%p", qi); `checks(v, "'{'h1, 'h2} ");
qi = d.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'h1} ");
qi = d.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
i = 2;
qi = d.find_index with (item == i);
qi.sort; v = $sformatf("%p", qi); `checks(v, "'{'h1, 'h2} ");
qi = d.find_index with (item == 20); qi.sort;
`checkh(qi.size, 0);
qi = d.find_first_index with (item == 20);
`checkh(qi.size, 0);
qi = d.find_last_index with (item == 20);
`checkh(qi.size, 0);
qi = d.find_index with (item.index == 2);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
qv = d.min;
v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
qv = d.max;
v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
qv = de.min;
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = de.max;
v = $sformatf("%p", qv); `checks(v, "'{}");
// Reduction methods
i = d.sum;
`checkh(i, 32'hc);
i = d.sum with (item + 1);
`checkh(i, 32'h11);
i = d.sum(myi) with (myi + 1);
`checkh(i, 32'h11);
i = d.sum with (1); // unused 'index'
`checkh(i, 32'h5);
i = d.sum(unused) with (1); // unused 'unused'
`checkh(i, 32'h5);
i = d.product;
`checkh(i, 32'h30);
i = d.product with (item + 1);
`checkh(i, 32'h168);
i = de.sum;
`checkh(i, 32'h0);
i = de.product;
`checkh(i, 32'h0);
d = '{32'b1100, 32'b1010};
i = d.and;
`checkh(i, 32'b1000);
i = d.and with (item + 1);
`checkh(i, 32'b1001);
i = d.or;
`checkh(i, 32'b1110);
i = d.or with (item + 1);
`checkh(i, 32'b1111);
i = d.xor;
`checkh(i, 32'b0110);
i = d.xor with (item + 1);
`checkh(i, 32'b0110);
i = de.and;
`checkh(i, 32'b0);
i = de.or;
`checkh(i, 32'b0);
i = de.xor;
`checkh(i, 32'b0);
`checks(s[1], "sad");
qi = s.find_first_index with (item == "sad");
`checkh(qi.size, 1);
`checkh(qi[0], 1);
qi = s.find_last_index with (item == "sad");
`checkh(qi.size, 1);
`checkh(qi[0], 2);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ee_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ee_e.v,v 1.1 2006/04/10 15:42:06 wig Exp $
// $Date: 2006/04/10 15:42:06 $
// $Log: inst_ee_e.v,v $
// Revision 1.1 2006/04/10 15:42:06 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ee_e
//
// No user `defines in this module
module inst_ee_e
//
// Generated module inst_ee
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ee_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; class p1328D { public: void solve() { int q; cin >> q; while (q--) { int n; cin >> n; vector<int> t(n); for (int i = 0; i < n; i++) cin >> t[i]; int sum = 1; for (int i = 1; i < n; i++) { if (t[i] == t[i - 1]) sum++; } if (sum == n) { cout << 1 << endl; for (int i = 0; i < n; i++) cout << 1 << ; cout << endl; } else if (n % 2 == 0 || t.back() == t.front()) { cout << 2 << endl; for (int i = 0; i < n; i++) cout << i % 2 + 1 << ; cout << endl; } else if (sum > 1) { cout << 2 << endl; bool can = true; for (int i = 0; i < n; i++) { if (can && i > 0 && t[i] == t[i - 1]) { cout << (i - 1) % 2 + 1 << ; can = false; } else if (!can) cout << (i - 1) % 2 + 1 << ; else cout << i % 2 + 1 << ; } cout << endl; } else { cout << 3 << endl; for (int i = 0; i < n - 1; i++) cout << i % 2 + 1 << ; cout << 3 << endl; } } } }; class p1327E { public: long long MOD = 998244353; long long fastpow(long long x, long long n) { if (n == 0) return 1ll; if (n == 1) return x; long long temp = fastpow(x, n / 2); if (n % 2 == 0) return (temp * temp) % MOD; else return (((x * temp) % MOD) * temp) % MOD; } void solve() { int n; cin >> n; if (n < 2) { cout << 10 << endl; return; } int maxn = 2e5 + 10; vector<long long> dp(maxn, 1); for (int i = 1; i <= maxn; i++) { dp[i] = (dp[i - 1] * 10) % MOD; } for (int i = 1; i < n; i++) { long long res = 2 * 10 * 9 * dp[n - i - 1] % MOD; res += (n - i - 1) * 10 * 9 * 9 * dp[n - i - 2] % MOD; cout << res % MOD << ; } cout << 10 << endl; } }; class p161D { public: long long res, k, n; vector<vector<int>> e; vector<vector<long long>> dp; void dfs(int cur, int fa) { dp[cur][0] = 1; for (int c : e[cur]) { if (c == fa) continue; dfs(c, cur); for (int i = 1; i <= k; i++) { dp[cur][i] += dp[c][i - 1]; } } res += dp[cur][k]; long long temp = 0; for (int c : e[cur]) { if (c == fa) continue; for (int i = 0; k - 2 - i >= 0; i++) { temp += dp[c][i] * (dp[cur][k - i - 1] - dp[c][k - i - 2]); } } res += temp / 2; } void solve() { cin >> n >> k; e = vector<vector<int>>(n + 1); dp = vector<vector<long long>>(n + 1, vector<long long>(k + 1, 0)); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; e[a].push_back(b); e[b].push_back(a); } res = 0; dfs(1, 0); cout << res << endl; } }; class p1437C { public: void solve() { int q; cin >> q; while (q--) { int n; cin >> n; vector<int> t(n); for (int i = 0; i < n; i++) cin >> t[i]; sort(t.begin(), t.end()); vector<vector<int>> dp(2 * n + 1, vector<int>(n + 1, 0x3f3f3f3f)); dp[0][0] = 0; int res = 0x3f3f3f3f; for (int k = 1; k <= 2 * n; k++) { for (int i = 1; i <= n; i++) { for (int pre = 0; pre <= k - 1; pre++) { dp[k][i] = min(dp[k][i], dp[pre][i - 1] + abs(t[i - 1] - k)); } } res = min(res, dp[k][n]); } cout << res << endl; } } }; class p1038D { public: void solve() { int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; if (n == 1) { cout << a[0] << endl; return; } long long ans = 0, minval = 0x3f3f3f3f; bool pos = 0, neg = 0; for (int i = 0; i < n; i++) { ans += abs(a[i]); pos |= (a[i] >= 0); neg |= (a[i] <= 0); minval = min(minval, abs(a[i])); } if (pos && neg) cout << ans << endl; else cout << ans - 2 * minval << endl; } }; class p1286A { public: void solve() { int n; cin >> n; vector<int> p(n); unordered_set<int> cnt; for (int i = 1; i <= n; i++) cnt.insert(i); for (int i = 0; i < n; i++) { cin >> p[i]; if (p[i] != 0) cnt.erase(p[i]); } int odd = 0, even = 0; for (int i : cnt) if (i % 2) odd++; else even++; vector<vector<vector<int>>> dp( n + 1, vector<vector<int>>(n + 1, vector<int>(2, 0x3f3f3f3f))); dp[0][0][0] = dp[0][0][1] = 0; for (int i = 1; i <= n; i++) { int cur = p[i - 1] % 2; for (int j = 0; j <= min(odd, i); j++) { if (p[i - 1] != 0) { dp[i][j][cur] = min(dp[i - 1][j][0] + (0 ^ cur), dp[i - 1][j][1] + (1 ^ cur)); } else { if (j >= 1) { dp[i][j][1] = min( dp[i][j][1], min(dp[i - 1][j - 1][0] + 1, dp[i - 1][j - 1][1])); } dp[i][j][0] = min(dp[i][j][0], min(dp[i - 1][j][0], dp[i - 1][j][1] + 1)); } } } cout << min(dp[n][odd][0], dp[n][odd][1]) << endl; } }; class p580D { public: void solve() { int n, m, k; cin >> n >> m >> k; vector<long long> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<long long>> cost(n + 1, vector<long long>(n + 1, 0)); vector<vector<long long>> dp(1 << n, vector<long long>(n + 1, 0)); for (int i = 0; i < k; i++) { long long x, y, c; cin >> x >> y >> c; cost[x][y] = c; } long long ans = 0; for (int i = 1; i <= n; i++) { dp[1 << (i - 1)][i] = a[i]; } for (int i = 1; i < (1 << n); i++) { int cnt = bitset<32>(i).count(); for (int j = 1; j <= n; j++) { if ((i & (1 << (j - 1))) != 0) { int pre = i ^ (1 << (j - 1)); for (int k = 1; k <= n; k++) { if ((pre & (1 << (k - 1))) == 0) continue; dp[i][j] = max(dp[i][j], dp[pre][k] + cost[k][j] + a[j]); } if (cnt == m) ans = max(ans, dp[i][j]); } } } cout << ans << endl; } }; class p1335E2 { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int>> sum(n + 1, vector<int>(205, 0)); vector<vector<int>> pos(205); int res = 0; for (int i = 1; i <= n; i++) { sum[i][a[i]]++; for (int j = 1; j <= 200; j++) { sum[i][j] += sum[i - 1][j]; res = max(res, sum[i][j]); } pos[a[i]].push_back(i); } for (int i = 1; i <= 200; i++) { int len = pos[i].size(); for (int k = 0; k < len - 1 - k; k++) { int l = pos[i][k], r = pos[i][len - 1 - k] - 1; int mid = 0; for (int j = 1; j <= 200; j++) { mid = max(mid, sum[r][j] - sum[l][j]); } res = max(res, 2 * (k + 1) + mid); } } cout << res << endl; } } }; class p1221D { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<long long> a(n + 1), b(n + 1); a[0] = 0; for (int i = 1; i <= n; i++) cin >> a[i] >> b[i]; vector<vector<long long>> dp(n + 1, vector<long long>(4, -1)); dp[0][0] = dp[0][1] = dp[0][2] = dp[0][3] = 0; long long res = LONG_LONG_MAX; for (long long i = 1; i <= n; i++) { for (long long j = 0; j <= 2; j++) { for (int k = 0; k <= 2; k++) { if (a[i] + j != a[i - 1] + k) { auto cur = j * b[i] + dp[i - 1][k]; dp[i][j] = dp[i][j] == -1 ? cur : min(dp[i][j], cur); } } if (i == n) res = min(res, dp[i][j]); } } cout << res << endl; } } }; class p543A { public: void solve() { int n, m, b, md; cin >> n >> m >> b >> md; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int>> dp(m + 1, vector<int>(b + 1, 0)); dp[0][0] = 1; for (int i = 1; i <= n; i++) { for (int k = 0; k <= m; k++) { for (int j = 0; j <= b; j++) { if (j >= a[i] && k > 0) dp[k][j] = (dp[k][j] + dp[k - 1][j - a[i]]) % md; } } } long long res = 0; for (int i = 0; i <= b; i++) res = (res + dp[m][i]) % md; cout << res << endl; } }; class p1142A { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int left = a[0]; bool ok = 1; int mx = 0; for (int i = 1; i < n; i++) { if (mx > a[i]) { ok = false; break; } a[i] -= mx; if (left >= a[i]) left = a[i]; else { mx += a[i] - left; } } if (ok) cout << YES << endl; else cout << NO << endl; } } }; class p1244D { public: vector<int> node; vector<vector<int>> e; void dfs(int cur, int fa) { node.push_back(cur); for (int c : e[cur]) { if (c == fa) continue; dfs(c, cur); } } void solve() { int n; cin >> n; vector<vector<long long>> cost(n + 1, vector<long long>(3, 0)); for (int j = 0; j < 3; j++) { for (int i = 1; i <= n; i++) { cin >> cost[i][j]; } } e = vector<vector<int>>(n + 1); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; e[u].push_back(v); e[v].push_back(u); if (e[u].size() > 2 || e[v].size() > 2) { cout << -1 << endl; return; } } int start = -1; for (int i = 1; i <= n; i++) { if (e[i].size() == 1) { start = i; break; } } dfs(start, -1); long long res = 4e18; int x = -1, y = -1; for (int i = 0; i < 3; i++) { for (int k = 0; k < 3; k++) { if (k == i) continue; long long temp = 0; temp += cost[node[0]][i] + cost[node[1]][k]; int a = i, b = k; for (int j = 2; j < node.size(); j++) { for (int l = 0; l < 3; l++) { if (l == a || l == b) continue; temp += cost[node[j]][l]; a = b; b = l; break; } } if (temp < res) { res = temp; x = i; y = k; } } } cout << res << endl; vector<int> ans(n + 1, 0); ans[node[0]] = x; ans[node[1]] = y; for (int i = 2; i < node.size(); i++) { for (int l = 0; l < 3; l++) { if (l == x || l == y) continue; ans[node[i]] = l; x = y; y = l; break; } } for (int i = 1; i <= n; i++) cout << ans[i] + 1 << ; cout << endl; } }; class p519D { public: void solve() { vector<long long> cnt(26, 0); for (int i = 0; i < 26; i++) cin >> cnt[i]; string s; cin >> s; int n = s.size(); vector<long long> sum(n + 1, 0); for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + cnt[s[i - 1] - a ]; } long long res = 0; unordered_map<long long, long long> mp[26]; for (int i = 1; i <= n; i++) { int cur = s[i - 1] - a ; res += mp[cur][sum[i] - cnt[cur]]; mp[cur][sum[i]]++; } cout << res << endl; } }; class p1096D { public: void solve() { int n; cin >> n; string s; cin >> s; vector<long long> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } unordered_map<char, int> cnt; cnt[ h ] = 0; cnt[ a ] = 1; cnt[ r ] = 2; cnt[ d ] = 3; vector<long long> dp(4, 0); for (int i = 0; i < n; i++) { if (!cnt.count(s[i])) continue; if (s[i] == h ) dp[0] += a[i]; else dp[cnt[s[i]]] = min(dp[cnt[s[i]] - 1], dp[cnt[s[i]]] + a[i]); } cout << dp[3] << endl; } }; class p1296E1 { public: void solve() { int n; cin >> n; string s; cin >> s; vector<int> res(n); res[0] = 0; char first = s[0]; char second = a - 1; for (int i = 1; i < n; i++) { if (s[i] >= first) { res[i] = 0; first = s[i]; } else { if (s[i] >= second) { res[i] = 1; second = s[i]; } else { cout << NO << endl; return; } } } cout << YES << endl; for (int i : res) cout << i; cout << endl; } }; class p1296E2 { public: void solve() { int n; cin >> n; string s; cin >> s; vector<int> dp(26, 0); int res = 0; vector<int> ans; for (int i = 0; i < n; i++) { int d = 1; for (int j = s[i] - a + 1; j < 26; j++) { d = max(d, dp[j] + 1); } dp[s[i] - a ] = d; ans.emplace_back(d); } for (int i = 0; i < 26; i++) res = max(res, dp[i]); cout << res << endl; for (auto c : ans) cout << c << ; cout << endl; } }; class D { public: void solve() { int t; cin >> t; for (int i = 1; i <= t; i++) { int n, q; cin >> n >> q; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); vector<long long> sum(n + 1, 0); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i - 1]; unordered_set<long long> cnt; cnt.insert(sum[n]); queue<pair<long long, long long>> que; que.emplace(0, n - 1); while (!que.empty()) { auto u = que.front(); que.pop(); if (u.first > u.second) continue; auto l = a[u.first], r = a[u.second]; cnt.insert(sum[u.second + 1] - sum[u.first]); if (u.first == u.second) continue; long long mid = (l + r) / 2; auto it = upper_bound(a.begin() + u.first, a.begin() + u.second + 1, mid) - a.begin(); if (it - 1 >= u.first && it - 1 != u.second) que.emplace(u.first, it - 1); if (it <= u.second && it != u.first) que.emplace(it, u.second); } while (q--) { long long s; cin >> s; if (cnt.count(s)) cout << YES << endl; else cout << NO << endl; } } } }; class p1462F { public: void solve() { int t; cin >> t; while (t--) { int n; cin >> n; vector<pair<long long, long long>> c; vector<int> a, b; c.clear(); for (int i = 0; i < n; i++) { long long l, r; cin >> l >> r; a.push_back(l); b.push_back(r); c.emplace_back(l, r); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); int res = n; for (int i = 0; i < n; i++) { auto leftcnt = lower_bound(b.begin(), b.end(), c[i].first) - b.begin(); auto rightcnt = upper_bound(a.begin(), a.end(), c[i].second) - a.begin(); res = min(res, (int)(leftcnt + n - rightcnt)); } cout << res << endl; } } }; class p1324F { public: vector<int> a; vector<int> dp; int n; vector<vector<int>> e; vector<int> fa; int dfs(int cur, int f) { dp[cur] = a[cur]; for (int child : e[cur]) { if (child == f) continue; int next = dfs(child, cur); dp[cur] += max(0, next); } return dp[cur]; } void dfs2(int cur, int fa) { dp[cur] = max(dp[cur], dp[cur] + max(0, dp[fa] - max(0, dp[cur]))); for (int c : e[cur]) { if (c == fa) continue; dfs2(c, cur); } } void solve() { cin >> n; a = vector<int>(n + 1); e = vector<vector<int>>(n + 1); dp = vector<int>(n + 1, 0); fa = vector<int>(n + 1, 0); for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 0) a[i] = -1; } for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; e[u].emplace_back(v); e[v].emplace_back(u); } dfs(1, 0); dfs2(1, 0); for (int i = 1; i <= n; i++) { cout << dp[i] << ; } cout << endl; } }; class p1446B { public: void solve() { int n, m; cin >> n >> m; string s, t; cin >> s >> t; vector<vector<int>> dp(n + 1, vector<int>(m + 1, 0)); int res = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (s[i - 1] == t[j - 1]) { dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + 2); } dp[i][j] = max(dp[i][j], max(dp[i - 1][j] - 1, dp[i][j - 1] - 1)); res = max(res, dp[i][j]); } } cout << res << endl; } }; class p1283E { public: void solve() { int n; cin >> n; vector<int> x(n); for (int i = 0; i < n; i++) cin >> x[i]; int maxn = 200005; int ans1 = 0, ans2 = 0; unordered_map<int, int> cnt; for (int i : x) cnt[i]++; for (int i = 1; i <= n; i++) { if (cnt[i] > 0) { ans1++; i += 2; } } for (int i = 1; i <= n + 1; i++) { if (cnt[i - 1] == 0 && cnt[i] > 0) { cnt[i - 1]++; cnt[i]--; } if (cnt[i] > 1) { cnt[i]--; cnt[i + 1]++; } } for (int i = 0; i <= n + 1; i++) { if (cnt[i] > 0) ans2++; } printf( %d %d n , ans1, ans2); } }; class p148D { public: vector<vector<vector<double>>> dp; double dfs(int w, int b, int cur) { if (dp[w][b][cur] >= 0.0) return dp[w][b][cur]; if (w == 0) { if (cur == 0) dp[w][b][cur] = 0.0; else dp[w][b][cur] = 1.0; return dp[w][b][cur]; } if (b == 0) { dp[w][b][cur] = 1.0; return 1.0; } dp[w][b][cur] = 1.0 * w / (w + b); if (cur == 0) { dp[w][b][cur] += (1.0 - dfs(w, b - 1, 1 - cur)) * (1.0 * b / (w + b)); } else { dp[w][b][cur] += (1.0 - dfs(w - 1, b - 1, 1 - cur)) * (1.0 * b / (w + b)) * (1.0 * w / (w + b - 1)); if (b >= 2) { dp[w][b][cur] += (1.0 - dfs(w, b - 2, 1 - cur)) * (1.0 * b / (w + b)) * (1.0 * (b - 1) / (w + b - 1)); } } return dp[w][b][cur]; } void solve() { int w, b; cin >> w >> b; dp = vector<vector<vector<double>>>( w + 1, vector<vector<double>>(b + 1, vector<double>(2, -1))); double res = dfs(w, b, 0); printf( %.9lf n , res); } }; class p95B { public: string ans, s; bool dfs(int id, int sum4, int sum7, bool ok) { if (id >= s.size()) return 1; if (ok) { ans.append(sum4, 4 ); ans.append(sum7, 7 ); return 1; } if (s[id] <= 4 && sum4) { ans.push_back( 4 ); if (dfs(id + 1, sum4 - 1, sum7, s[id] < 4 )) return true; ans.pop_back(); } if (s[id] <= 7 && sum7) { ans.push_back( 7 ); if (dfs(id + 1, sum4, sum7 - 1, s[id] < 7 )) return 1; ans.pop_back(); } return 0; } void solve() { cin >> s; ans.clear(); s.clear(); s.append(100000, 4 ); cout << s << endl; int n = s.size(); if (n % 2 || !dfs(0, n / 2, n / 2, 0)) { ans.append((n + 2) / 2, 4 ); ans.append((n + 2) / 2, 7 ); cout << ans << endl; } else cout << ans << endl; } }; class p182E { public: void solve() { int n, h; cin >> n >> h; vector<vector<vector<int>>> dp( h + 1, vector<vector<int>>(n + 1, vector<int>(2, 0))); for (int i = 0; i < n; i++) dp[0][i][0] = dp[0][i][1] = 1; vector<pair<long long, long long>> a(n); for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } long long res = 0; for (int i = 1; i <= h; i++) { for (int j = 0; j < n; j++) { int l = a[j].first, w = a[j].second; if (i == l) dp[i][j][0] = (dp[i][j][0] + 1) % 1000000007; if (i == w && l != w) dp[i][j][1] = (dp[i][j][1] + 1) % 1000000007; for (int k = 0; k < n; k++) { if (k == j) continue; int pl = a[k].first, pw = a[k].second; if (i > l) { dp[i][j][0] = (dp[i][j][0] + dp[i - l][k][0] * (l == pw)) % 1000000007; dp[i][j][0] = (dp[i][j][0] + dp[i - l][k][1] * (l == pl)) % 1000000007; } if (i > w && l != w) { dp[i][j][1] = (dp[i][j][1] + dp[i - w][k][0] * (w == pw)) % 1000000007; dp[i][j][1] = (dp[i][j][1] + dp[i - w][k][1] * (w == pl)) % 1000000007; } } if (i == h) res = (res + dp[i][j][0] + dp[i][j][1]) % 1000000007; } } cout << res << endl; } }; class p180E { public: void solve() { int n, m, k; cin >> n >> m >> k; unordered_map<int, vector<int>> cnt; for (int i = 0; i < n; i++) { int x; cin >> x; cnt[x].push_back(i); } int res = 0; for (auto it : cnt) { auto v = it.second; int sz = v.size(); deque<int> q; for (int r = 0; r < sz; r++) { q.push_back(v[r]); while (!q.empty() && q.back() - q.front() + 1 - q.size() > k) q.pop_front(); res = max(res, (int)q.size()); } } cout << res << endl; } }; class p30C { public: struct node { long long x, y, t; double p; node(long long xx, long long yy, long long tt, double pp) : x(xx), y(yy), t(tt), p(pp){}; node(){}; bool operator<(const node &rhs) const { return t < rhs.t; } }; void solve() { int n; cin >> n; vector<node> a; for (int i = 0; i < n; i++) { long long x, y, t; double p; cin >> x >> y >> t >> p; a.emplace_back(x, y, t, p); } sort(a.begin(), a.end()); vector<double> dp(a.size() + 1, 0.0); double res = 0.0; for (int i = 0; i < n; i++) { dp[i] = a[i].p; for (int j = 0; j < i; j++) { long long dis = abs(a[i].x - a[j].x) * abs(a[i].x - a[j].x) + abs(a[i].y - a[j].y) * abs(a[i].y - a[j].y); long long dt = (a[i].t - a[j].t) * (a[i].t - a[j].t); if (dis <= dt) dp[i] = max(dp[i], dp[j] + a[i].p); } res = max(res, dp[i]); } printf( %.7lf , res); } }; class p49D { public: void solve() { int n; cin >> n; string s; cin >> s; vector<vector<int>> dp(n, vector<int>(2, 0x3f3f3f3f)); dp[0][0] = s[0] != 0 ; dp[0][1] = s[0] != 1 ; for (int i = 1; i < n; i++) { dp[i][0] = s[i] != 0 ; dp[i][1] = s[i] != 1 ; dp[i][0] += dp[i - 1][1]; dp[i][1] += dp[i - 1][0]; } cout << min(dp[n - 1][0], dp[n - 1][1]) << endl; } }; class p721C { public: void solve() { int n, m, T; cin >> n >> m >> T; vector<vector<pair<long long, long long>>> e(n + 1); vector<int> in(n + 1, 0); for (int i = 0; i < m; i++) { int u, v, t; cin >> u >> v >> t; e[u].emplace_back(v, t); in[v]++; } queue<int> q; for (int i = 1; i <= n; i++) { if (!in[i]) q.push(i); } vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0x3f3f3f3f)); vector<vector<int>> f(n + 1, vector<int>(n + 1, 0)); dp[1][1] = 0; while (!q.empty()) { int u = q.front(); q.pop(); for (auto &[v, w] : e[u]) { for (int j = 2; j <= n; j++) { if (dp[v][j] > dp[u][j - 1] + w) { dp[v][j] = dp[u][j - 1] + w; f[v][j] = u; } } in[v]--; if (!in[v]) q.push(v); } } int ans = -1; for (int j = n; j >= 1; j--) { if (dp[n][j] <= T) { ans = j; break; } } cout << ans << endl; vector<int> out; for (int i = n, j = ans; f[i][j] != 0; i = f[i][j], j--) out.push_back(i); out.push_back(1); reverse(out.begin(), out.end()); for (int i : out) cout << i << ; cout << endl; } }; class p830A { public: void solve() { long long n, k, p; cin >> n >> k >> p; vector<long long> a(n + 1, 0); vector<long long> b(k + 1, 0); for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= k; i++) cin >> b[i]; sort(a.begin(), a.end()); sort(b.begin(), b.end()); vector<vector<long long>> dp(n + 1, vector<long long>(k + 1, 1e18)); for (int i = 0; i <= k; i++) dp[0][i] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= k; j++) { dp[i][j] = min(dp[i][j - 1], max(dp[i - 1][j - 1], abs(a[i] - b[j]) + abs(p - b[j]))); } } cout << dp[n][k] << endl; } }; class p983B { public: void solve() { int n; cin >> n; vector<int> a(n + 1); vector<vector<int>> f(n + 1, vector<int>(n + 1, 0)); vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0)); for (int i = 1; i <= n; i++) { cin >> a[i]; dp[i][i] = f[i][i] = a[i]; } for (int i = n; i >= 1; i--) { for (int j = i + 1; j <= n; j++) { f[i][j] = f[i][j - 1] ^ f[i + 1][j]; dp[i][j] = max(dp[i][j], f[i][j]); dp[i][j] = max(dp[i][j], max(dp[i + 1][j], dp[i][j - 1])); } } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; cout << dp[l][r] << endl; } } }; class p671A { public: struct node { long long id; double at, bt; node(int _id, double t, double a, double b) : id(_id), at(a - t), bt(b - t){}; }; void solve() { long long ax, ay, bx, by, tx, ty; cin >> ax >> ay >> bx >> by >> tx >> ty; int n; cin >> n; vector<node> bt1, bt2; auto distance = [](long long x1, long long y1, long long x2, long long y2) { long long dx = abs(x1 - x2); long long dy = abs(y1 - y2); return 1.0 * sqrt(dx * dx + dy * dy); }; double res = 0.0; for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; auto dt = distance(x, y, tx, ty); auto da = distance(x, y, ax, ay); auto db = distance(x, y, bx, by); res += 2.0 * dt; bt1.emplace_back(i, dt, da, db); bt2.emplace_back(i, dt, da, db); } sort(bt1.begin(), bt1.end(), [](const node &a, const node &b) { return a.at < b.at; }); sort(bt2.begin(), bt2.end(), [](const node &a, const node &b) { return a.bt < b.bt; }); int i = 0, j = 0; double temp = min(res + bt1[i].at, res + bt2[j].bt); if (bt1[i].id != bt2[j].id) { res += bt1[i].at; res += bt2[j].bt; } else { res += min(bt1[0].at + (bt2.size() > 1 ? bt2[1].bt : 0), bt2[0].bt + (bt1.size() > 1 ? bt1[1].at : 0)); } res = min(temp, res); printf( %.15f n , res); } }; class p274B { public: int n; vector<vector<int>> edge; vector<long long> v; pair<long long, long long> dfs(int cur, int fa) { long long now = v[cur]; long long curp = 0, curg = 1e18; for (int i : edge[cur]) { if (i == fa) continue; auto next = dfs(i, cur); curp = max(next.first, curp); if (next.second != 0) curg = min(next.second, curg); } if (curg == 1e18) { curg = 0; } now += -curg - curp; if (now >= 0) curp += now; else curg += now; return {curp, curg}; } void solve() { cin >> n; edge = vector<vector<int>>(n + 1); v = vector<long long>(n + 1); for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; edge[a].push_back(b); edge[b].push_back(a); } for (int i = 1; i <= n; i++) cin >> v[i]; pair<long long, long long> it = dfs(1, 0); cout << abs(it.first) + abs(it.second) << endl; } }; class p933A { public: void solve() { int n; cin >> n; vector<int> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<int> two(n + 2, 0), one(n + 1, 0); if (a.back() == 2) two[n]++; for (int i = n - 1; i >= 1; i--) { two[i] += two[i + 1]; if (a[i] == 2) two[i]++; } for (int i = 1; i <= n; i++) { one[i] += one[i - 1]; if (a[i] == 1) one[i]++; } int res = 0; for (int l = 1; l <= n; l++) { int s = 0, t = 0; for (int r = l; r <= n; r++) { if (a[r] == 1) { s = max(s, t) + 1; } else { t++; } res = max(res, one[l - 1] + two[r + 1] + max(s, t)); } } cout << res << endl; } }; class p527D { public: void solve() { int n; cin >> n; vector<pair<long long, long long>> v(n); for (int i = 0; i < n; i++) { cin >> v[i].first >> v[i].second; } sort(v.begin(), v.end(), [](const pair<long long, long long> &a, const pair<long long, long long> &b) { return a.first + a.second < b.first + b.second; }); long long res = 1; int last = 0; for (int i = 1; i < n; i++) { if (v[i].first - v[i].second >= v[last].first + v[last].second) { res++; last = i; } } cout << res << endl; } }; class p1083A { public: vector<vector<pair<long long, long long>>> edge; vector<long long> dp; long long ans = 0; vector<long long> w; void dfs(int u, int fa) { dp[u] = w[u]; for (auto &[v, c] : edge[u]) { if (v == fa) continue; dfs(v, u); ans = max(ans, dp[u] + dp[v] - c); dp[u] = max(dp[u], w[u] + dp[v] - c); } } void solve() { int n; cin >> n; w = vector<long long>(n + 1); ans = 0; for (int i = 1; i <= n; i++) { cin >> w[i]; ans = max(ans, w[i]); } edge = vector<vector<pair<long long, long long>>>(n + 1); dp = vector<long long>(n + 1, 0); for (int i = 0; i < n - 1; i++) { long long u, v, c; cin >> u >> v >> c; edge[u].emplace_back(v, c); edge[v].emplace_back(u, c); } dfs(1, 0); cout << ans << endl; } }; class p909C { public: void solve() { int n; cin >> n; string s(n, ); for (int i = 0; i < n; i++) cin >> s[i]; vector<vector<long long>> dp(n, vector<long long>(n + 1, 0)); dp[0][0] = 1; for (int i = 1; i < n; i++) { if (s[i - 1] == f ) { for (int j = 0; j < n; j++) { dp[i][j + 1] = dp[i - 1][j]; } } else { long long cur = 0; for (int k = n; k >= 0; k--) { cur = (cur + dp[i - 1][k]) % 1000000007; dp[i][k] = (dp[i][k] + cur) % 1000000007; } } } long long res = 0; for (int i = 0; i <= n; i++) res = (res + dp[n - 1][i]) % 1000000007; cout << res << endl; } }; class p743D { public: int n; vector<long long> a; vector<vector<long long>> edge; vector<vector<long long>> dp; long long ans = 0; void dfs(int u, int fa) { dp[u][0] = a[u]; dp[u][1] = -4e18; long long mx1 = -4e18, mx2 = -4e18; for (int v : edge[u]) { if (v == fa) continue; dfs(v, u); dp[u][0] += dp[v][0]; if (dp[v][1] >= mx1) { mx2 = mx1; mx1 = dp[v][1]; } else if (dp[v][1] >= mx2) mx2 = dp[v][1]; dp[u][1] = max(dp[u][1], dp[v][1]); } if (mx1 != -4e18 && mx2 != -4e18) ans = max(ans, mx1 + mx2); dp[u][1] = max(dp[u][0], dp[u][1]); } void solve() { cin >> n; a = vector<long long>(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; edge = vector<vector<long long>>(n + 1); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; edge[u].push_back(v); edge[v].push_back(u); } if (n <= 2) { cout << Impossible << endl; return; } dp = vector<vector<long long>>(n + 1, vector<long long>(2, 0)); ans = -4e18; dfs(1, 0); if (ans == -4e18) cout << Impossible << endl; else cout << ans << endl; } }; class p869C { public: void solve() { int a, b, c; cin >> a >> b >> c; vector<vector<long long>> f(5005, vector<long long>(5005, 0)); long long md = 998244353; f[0][0] = 1; for (int i = 1; i <= 5000; i++) { f[i][0] = 1; for (int j = 1; j <= i; j++) { f[i][j] = (f[i - 1][j - 1] + f[i - 1][j]) % md; } } long long ans1 = 0, ans2 = 0, ans3 = 0; auto compute = [&f, &md](long long &ans, int a, int b) { long long cur = 1; for (long long k = 0; k <= min(a, b); k++, cur *= k, cur %= md) { ans += (((f[a][k] * f[b][k] + md) % md) * cur) % md; ans %= md; } return ans; }; long long res = ((compute(ans1, a, b) * compute(ans2, b, c) % md) * compute(ans3, a, c)) % md; cout << (res + md) % md << endl; } }; class p768C { public: void solve() { int n, k, x; cin >> n >> k >> x; vector<int> a(n); int freq[1024]; memset(freq, 0, sizeof(freq)); for (int i = 0; i < n; i++) { cin >> a[i]; freq[a[i]]++; } while (k--) { vector<int> tmp(1024, 0); for (int i = 0; i < 1024; i++) tmp[i] = freq[i]; int pre = 0; for (int i = 0; i < 1024; i++) { if (tmp[i] <= 0) continue; int cnt = 0; if (pre == 0) cnt = (tmp[i] + 1) / 2; else cnt = (tmp[i]) / 2; freq[i] -= cnt; freq[i ^ x] += cnt; pre ^= tmp[i] & 1; } } int mi = 2048, mx = 0; for (int i = 0; i < 1024; i++) { if (freq[i] > 0) { mi = min(mi, i); mx = max(mx, i); } } cout << mx << << mi << endl; } }; class p1107D { public: void solve() { int n; cin >> n; vector<vector<int>> g(n + 1, vector<int>(n + 1, 0)); auto f = [](char c) { if (c <= 9 ) return c - 0 ; else return 10 + (c - A ); }; for (int i = 1; i <= n; i++) { string s; cin >> s; for (int j = 0; j < s.size(); j++) { int cur = f(s[j]); for (int k = 3; k >= 0; k--) { g[i][j * 4 + 4 - k] = (cur & (1 << k)) != 0 ? 1 : 0; } } } vector<vector<int>> sum(n + 1, vector<int>(n + 1, 0)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { sum[i][j] = sum[i][j - 1] + sum[i - 1][j] + g[i][j] - sum[i - 1][j - 1]; } } auto getSub = [&sum](int l, int r, int x) { return sum[l + x - 1][r + x - 1] - sum[l - 1][r + x - 1] - sum[l + x - 1][r - 1] + sum[l - 1][r - 1]; }; for (int x = n; x > 0; x--) { if ((n % x) == 0) { bool ok = true; for (int i = 1; i <= n; i += x) { for (int j = 1; j <= n; j += x) { int cur = getSub(i, j, x); if (cur != x * x && cur != 0) { ok = false; break; } } if (!ok) break; } if (ok) { cout << x << endl; break; } } } } }; class p917A { public: long long ans = 0; vector<int> dp; void solve() { ans = 0; string s; cin >> s; int n = s.size(); vector<vector<int>> f(n + 1, vector<int>(n + 1, 0)); vector<vector<int>> g(n + 1, vector<int>(n + 1, 0)); for (int i = 0; i < n; i++) { bool ok = true; int cnt = 0; for (int j = i; j < n; j++) { if (s[j] == ) ) cnt--; else cnt++; if (cnt < 0) ok = false; f[i][j] = ok; } } for (int i = 0; i < n; i++) { int cnt = 0; bool ok = true; for (int j = i; j >= 0; j--) { if (s[j] == ( ) cnt--; else cnt++; if (cnt < 0) ok = false; g[j][i] = ok; } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j += 2) { if (f[i][j] && g[i][j]) ans++; } } cout << ans << endl; } }; class p946D { public: void solve() { int n, m, k; cin >> n >> m >> k; vector<string> a(n + 1); for (int i = 1; i <= n; i++) cin >> a[i]; vector<vector<int>> dp(n + 1, vector<int>(k + 1, 0x3f3f3f3f)); for (int i = 0; i <= k; i++) dp[0][i] = 0; vector<vector<int>> cnt(n + 1, vector<int>(k + 1, 0x3f3f3f3f)); for (int i = 1; i <= n; i++) { unordered_map<int, int> last; int sum = 0, total = 0; for (int j = 1; j <= m; j++) total += (a[i][j - 1] == 1 ? 1 : 0); last[0] = 0; for (int j = 1; j <= m; j++) { if (a[i][j - 1] == 1 ) sum++; last[sum] = j; for (int l = 0; l <= min(total, k); l++) { if (last.count(sum - total + l)) { cnt[i][l] = min(cnt[i][l], j - last[sum - total + l]); } } } for (int l = 0; l <= k; l++) { for (int r = 0; r <= min(total, l); r++) { dp[i][l] = min(dp[i][l], dp[i - 1][l - r] + cnt[i][r]); } } } cout << dp[n][k] << endl; } }; class p666A { public: void solve() { string s; cin >> s; int n = s.size(); vector<vector<int>> dp(n + 1, vector<int>(2, -1)); set<string> res; dp[n][0] = dp[n][1] = 1; dp[n - 2][0] = 1; if (n >= 7) res.insert(s.substr(n - 2, 2)); dp[n - 3][1] = 1; if (n >= 8) res.insert(s.substr(n - 3, 3)); for (int i = n - 4; i >= 5; i--) { if (dp[i + 2][1] == 1 || (dp[i + 2][0] == 1 && (s[i] != s[i + 2] || s[i + 1] != s[i + 3]))) { dp[i][0] = 1; res.insert(s.substr(i, 2)); } if (dp[i + 3][0] == 1 || (dp[i + 3][1] == 1 && (s[i] != s[i + 3] || s[i + 1] != s[i + 4] || s[i + 2] != s[i + 5]))) { dp[i][1] = 1; res.insert(s.substr(i, 3)); } } cout << res.size() << endl; for (string s : res) cout << s << endl; } }; class p1016C { public: void solve() { long long n; cin >> n; vector<vector<long long>> a(2, vector<long long>(n + 1, 0)); for (int i = 0; i < 2; i++) { for (int j = 1; j <= n; j++) cin >> a[i][j]; } vector<vector<long long>> sum1(2, vector<long long>(n + 1, 0)), sum2(2, vector<long long>(n + 1, 0)), sum3(2, vector<long long>(n + 1, 0)); for (int i = 0; i < 2; i++) { for (int j = 1; j <= n; j++) { sum3[i][j] += sum3[i][j - 1] + a[i][j]; sum1[i][j] += sum1[i][j - 1] + (j - 1) * a[i][j]; sum2[i][j] += sum2[i][j - 1] + (n - j) * a[i][j]; } } long long res = 0; long long cur = 0; for (int c = 0; c < 2 * n; c++) { int j = c / 2 + 1; int i = ((j % 2) + (c % 2) + 1) % 2; cur += c * a[i][j]; if ((j % 2) == i) continue; long long aa = (sum1[i][n] - sum1[i][j] + (c + 1 - j) * (sum3[i][n] - sum3[i][j])); long long bb = (sum2[1 ^ i][n] - sum2[1 ^ i][j - 1] + (n + j - 1) * (sum3[1 ^ i][n] - sum3[1 ^ i][j - 1])); res = max(res, cur + aa + bb); } cout << res << endl; } }; class p1133E { public: void solve() { int n, k; cin >> n >> k; vector<vector<long long>> dp(n + 1, vector<long long>(k + 1, -1)); vector<long long> a(n, 0); for (int i = 0; i <= n - 1; i++) cin >> a[i]; sort(a.begin(), a.end()); for (int i = 0; i <= n; i++) dp[i][0] = 0; long long res = 0; for (int j = 1; j <= k; j++) { for (int i = 1; i <= n; i++) { dp[i][j] = dp[i - 1][j]; auto it = lower_bound(a.begin(), a.end(), a[i - 1] - 5); if (it == a.end()) { if (dp[0][j - 1] != -1) dp[i][j] = max(dp[i][j], dp[0][j - 1] + 1); } else { int pre = it - a.begin(); if (dp[pre][j - 1] != -1) { dp[i][j] = max(dp[i][j], dp[pre][j - 1] + i - pre); } } res = max(res, dp[i][j]); } } cout << res << endl; } }; class p2345H { public: void solve() { string s; cin >> s; int n = s.size(); vector<vector<int>> dp(n + 1, vector<int>(n + 1, 0)); vector<vector<bool>> ok(n + 2, vector<bool>(n + 1, 0)); for (int i = 1; i <= n; i++) { ok[i][i] = dp[i][i] = 1; ok[i + 1][i] = 1; } for (int len = 2; len <= n; len++) { for (int i = 1; i + len - 1 <= n; i++) { int j = i + len - 1; dp[i][j] = dp[i][j - 1] + dp[i + 1][j] - dp[i + 1][j - 1]; if (s[i - 1] == s[j - 1]) { ok[i][j] = ok[i + 1][j - 1]; if (ok[i][j] != 0) dp[i][j] += 1; } } } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; printf( %lld n , dp[l][r]); } } }; class p733C { public: void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int k; cin >> k; vector<int> b(k); for (int i = 0; i < k; i++) cin >> b[i]; vector<tuple<int, char>> res; int start = 0; bool flag = true; for (int i = 0; i < k && start < n; i++) { int sum = 0; int mx = start, end = start; while (sum < b[i] && end < n) { sum += a[end]; if (a[end] > a[mx]) mx = end; end++; } if (sum != b[i]) { flag = false; break; } if (end - start == 1) { start++; continue; } int k = start; bool ok = false; for (; k < end; k++) { if (a[k] == a[mx]) { if (k > start && a[k - 1] < a[k]) ok = true; if (k + 1 < end && a[k + 1] < a[k]) ok = true; } if (ok) break; } if (!ok) { flag = false; break; } if (k > start && a[k - 1] < a[k]) { for (int l = k; l > start; l--) res.emplace_back(i + l - start + 1, L ); for (int r = k; r < end - 1; r++) res.emplace_back(i + 1, R ); } else { for (int r = k; r < end - 1; r++) res.emplace_back(i + k - start + 1, R ); for (int l = k; l > start; l--) res.emplace_back(i + l - start + 1, L ); } start = end; } if (!flag || res.size() != n - k) cout << NO << endl; else { cout << YES << endl; for (auto &[x, y] : res) { cout << x << << y << endl; } } } }; class p914C { public: static const int maxn = 1005; long long f[maxn]; long long c[maxn][maxn]; void init() { const int maxn = 1001; f[1] = 0; for (int i = 2; i < maxn; i++) { int cnt = bitset<32>(i).count(); f[i] = 1 + f[cnt]; } memset(c, 0, sizeof(c)); c[0][0] = 1; for (int i = 1; i < maxn; i++) { c[i][0] = 1; for (int j = 1; j <= i; j++) { c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % 1000000007; } } } void solve() { int k; string s; cin >> s >> k; int n = s.size(); if (k == 0) { if (s[0] >= 1) cout << 1 << endl; else cout << 0 << endl; return; } if (k == 1) { cout << n - 1 << endl; return; } init(); long long res = 0; vector<long long> dp(n, 0); int cnt = 0; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { for (int j = 0; j <= n - i - 1; j++) { if (f[cnt + j] == k - 1) { res = (res + c[n - i - 1][j]) % 1000000007; } } cnt++; } } if (f[cnt] == k - 1) res = (res + 1) % 1000000007; cout << res << endl; } }; class p358D { public: static const int maxn = 3001; int n; int a[maxn], b[maxn], c[maxn]; int dp[maxn][2][2]; void solve() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) scanf( %d , &b[i]); for (int i = 0; i < n; i++) scanf( %d , &c[i]); memset(dp, -1, sizeof(dp)); dp[0][0][1] = b[0]; dp[0][0][0] = a[0]; for (int i = 1; i < n; i++) { dp[i][0][0] = max(dp[i - 1][1][1] + a[i], dp[i - 1][0][1] + a[i]); dp[i][0][1] = max(dp[i - 1][1][1] + b[i], dp[i - 1][0][1] + b[i]); dp[i][1][0] = max(dp[i - 1][1][0] + b[i], dp[i - 1][0][0] + b[i]); dp[i][1][1] = max(dp[i - 1][1][0] + c[i], dp[i - 1][0][0] + c[i]); } cout << max(dp[n - 1][1][0], dp[n - 1][0][0]) << endl; } }; class p700B { public: unordered_set<int> us; vector<vector<int>> edge; vector<int> seq; vector<int> dis; vector<int> lg; vector<vector<int>> dp; void dfs(int u, int fa, int depth) { dis[u] = depth; if (us.count(u)) seq.push_back(u); dp[u][0] = fa; for (int i = 1; (1 << i) <= depth; i++) { dp[u][i] = dp[dp[u][i - 1]][i - 1]; } for (auto c : edge[u]) { if (c == fa) continue; dfs(c, u, depth + 1); } } int lca(int x, int y) { if (dis[x] < dis[y]) swap(x, y); while (dis[x] > dis[y]) x = dp[x][lg[dis[x] - dis[y]] - 1]; if (x == y) return x; for (int k = lg[dis[x]] - 1; k >= 0; k--) { if (dp[x][k] != dp[y][k]) { x = dp[x][k]; y = dp[y][k]; } } return dp[x][0]; } void solve() { int n, k; cin >> n >> k; lg = vector<int>(n + 1, 0); dp = vector<vector<int>>(n + 1, vector<int>(21, 0)); for (int i = 1; i <= n; i++) { lg[i] = lg[i - 1]; if (i == (1 << lg[i - 1])) lg[i]++; } us.clear(); seq.clear(); for (int i = 0; i < 2 * k; i++) { int a; cin >> a; us.insert(a); } edge = vector<vector<int>>(n + 1); dis = vector<int>(n + 1); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; edge[x].push_back(y); edge[y].push_back(x); } dfs(1, 0, 0); long long res = 0; for (int i = 0; i < k; i++) { int u = lca(seq[i], seq[i + k]); res += dis[seq[i]] + dis[seq[i + k]] - 2 * dis[u]; } cout << res << endl; } }; class p700b { public: vector<vector<int>> edge; set<int> us; long long sum = 0; long long dfs(int u, int fa) { long long cnt = 0; if (us.count(u)) cnt++; for (int c : edge[u]) { if (c == fa) continue; long long t = dfs(c, u); sum += min(t, (long long)(us.size() - t)); cnt += t; } return cnt; } void solve() { int n, k; cin >> n >> k; for (int i = 0; i < 2 * k; i++) { int a; cin >> a; us.insert(a); } edge = vector<vector<int>>(n + 1); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; edge[x].push_back(y); edge[y].push_back(x); } sum = 0; dfs(1, 0); cout << sum << endl; } }; class p822D { public: void solve() { long long t, l, r; cin >> t >> l >> r; vector<long long> f(r + 1, 0); for (int i = 2; i <= r; i++) f[i] = i; for (long long i = 2; i * i <= r; i++) { if (f[i] == i) { for (long long j = i * i; j <= r; j += i) { f[j] = min(f[j], i); } } } vector<long long> dp(r + 1, 0); for (long long i = 2; i <= r; i++) { dp[i] = 1ll * 0x3f3f3f3f * 0x3f3f3f3f; for (long long j = i; j != 1; j /= f[j]) { dp[i] = min(dp[i], dp[i / f[j]] + i * (f[j] - 1) / 2); } } long long res = 0; long long k = 1; for (int i = l; i <= r; i++) { res = (res + k * (dp[i] % 1000000007)) % 1000000007; k = (k * t) % 1000000007; } cout << res << endl; } }; class p747D { public: void solve() { int n, k; cin >> n >> k; vector<int> t(n); vector<int> cnt; for (int i = 0; i < n; i++) cin >> t[i]; for (int i = 0; i < n; i++) { if (t[i] < 0) { cnt.push_back(i); } } if (cnt.size() > k) { cout << -1 << endl; return; } if (cnt.size() == 0) { cout << 0 << endl; return; } int res = 1, last = cnt.back(); k -= cnt.size(); for (int i = 0; i < cnt.size() - 1; i++) { cnt[i] = cnt[i + 1] - cnt[i] - 1; } cnt.pop_back(); sort(cnt.begin(), cnt.end()); for (int i : cnt) { if (i == 0) continue; if (i <= k) k -= i; else res += 2; } if (k < n - last - 1) res++; cout << res << endl; } }; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); p747D ans; ans.solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.length(); s += s; int ans = -1; int len = 1; for (int i = 1; i < 2 * n; i++) { if (s[i] != s[i - 1]) len++; else { if (len <= n) ans = max(len, ans); len = 1; } } if (len <= n) ans = max(len, ans); if (len > n) ans = n; cout << ans << endl; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the advanced register file
// Import the modules that will be tested for in this testbench
`include "regfileww.v"
// IMPORTANT: To run this, try: ncverilog -f regfileww.f +gui
module tb_regfileww();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the advanced register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// rd1data or rd2data output signals
wire [127:0] rd1_d,rd2_d;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren,rd1en,rd2en;
reg clock,wr_en,r1_en,r2_en;
// wrdata
reg [127:0] wr_d;
// wraddr, rd1addr, rd2addr
reg [4:0] w_addr,r1_addr,r2_addr;
// wrbyteen
reg [15:0] wrbytn;
// 32 Words of 128-bits
reg r[0:31];
reg [127:0] r_row;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#2.5 clock = 0;
#2.5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
RegFileWW rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
rd1_d,rd2_d,wr_d,r1_addr,r2_addr,w_addr,r1_en,r2_en,
wr_en,wrbytn,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/*
for(count=0;count<=size_of_input;count=count+1)
begin
#10
//$display("Next");
r_row=r[count];
$display("Next",r_row);
end
*/
// Write to 8 data locations
#20
wr_d=128'h787897ea12fec60cae787897eac22354;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd0;
wrbytn=16'hff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h72348973465465465464645664654666;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd1;
wrbytn=16'h7f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48545618548486131875531264684565;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd2;
wrbytn=16'h3f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h48646517897894613514684987984614;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd3;
wrbytn=16'h1f;
r1_en=0;
r2_en=0;
wr_en=1;
// ===================================
#20
wr_d=128'hcaacecce09c4ae54864c6ae464ca3544;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd4;
wrbytn=16'hfff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hceac45564c1ae151c53ae15c153ae1c4;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd5;
wrbytn=16'h7ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'hdc46da456c1ad561c65ad1c6ad61c455;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd6;
wrbytn=16'h3ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
//wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
wr_d=128'hc65da4654cad646c5d4a564cd56ca552;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd7;
wrbytn=16'h1ff;
r1_en=0;
r2_en=0;
wr_en=1;
// Read the data from the aforementioned locations
#20
wr_d=128'd12345;
r1_addr=5'd0;
r2_addr=5'd7;
w_addr=5'd20;
wrbytn=16'hffff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd1;
r2_addr=5'd6;
w_addr=5'd20;
wrbytn=16'h7fff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd2;
r2_addr=5'd5;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd3;
r2_addr=5'd4;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// ====================================================
#20
wr_d=128'd12345;
r1_addr=5'd4;
r2_addr=5'd3;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd5;
r2_addr=5'd2;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd6;
r2_addr=5'd1;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd7;
r2_addr=5'd0;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> string tos(T a) { stringstream ss; string ret; ss << a; ss >> ret; return ret; } int n, a; vector<int> arr; int main() { while (cin >> n) { arr.clear(); for (int(i) = (0); (i) < (n); (i)++) { cin >> a; arr.push_back(a); } int boro = *max_element((arr).begin(), (arr).end()); if (boro == 1) { sort(arr.begin(), arr.end()); arr[arr.size() - 1] = 2; } else { for (int(i) = (0); (i) < (n); (i)++) { if (arr[i] == boro) { arr[i] = 1; break; } } sort(arr.begin(), arr.end()); } for (int(i) = (0); (i) < (n); (i)++) { if (i) cout << ; cout << arr[i]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int K = 64, N = 3e5 + 7; int a[N]; int sum[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 1; i <= n; i++) { long long x; cin >> x; a[i] = __builtin_popcountll(x); sum[i] = sum[i - 1] + a[i]; } long long ans = 0; int odd = 0, even = 1; for (int i = 1; i <= n; i++) { if (sum[i] % 2) { ans += odd; odd++; } else { ans += even; even++; } int mx = 0, sm = 0; for (int j = 0; j < K && j < i; j++) { int cur = i - j; mx = max(mx, a[cur]); sm += a[cur]; if (sm % 2 == 0 && 2 * mx > sm) ans--; } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mxN = 210; int n, a[mxN], pos[mxN][3]; int next(int i) { if (pos[a[i]][0] == i) return pos[a[i]][1]; return pos[a[i]][0]; } void upd(int u, int v) { if (pos[a[u]][0] == u) pos[a[u]][0] = v; else pos[a[u]][1] = v; } bool gd() { for (int i = 1; i < 2 * n; i += 2) { if (a[i] != a[i - 1]) return false; } return true; } void prnt() { cout << Array << endl; for (int i = 0; i < 2 * n; i++) { cout << a[i] << ; } cout << endl << endl; } int main() { memset(pos, -1, sizeof pos); cin >> n; for (int i = 0; i < 2 * n; i++) { cin >> a[i]; if (pos[a[i]][0] == -1) pos[a[i]][0] = i; else pos[a[i]][1] = i; } int cnt = 0; while (!gd()) { for (int i = 0; i < 2 * n; i++) { if (i + 1 < 2 * n && a[i] == a[i + 1]) continue; if (i && a[i] == a[i - 1]) continue; if (i + 1 < 2 * n && next(i) > i && next(i + 1) < next(i)) { upd(i, i + 1); upd(i + 1, i); swap(a[i], a[i + 1]); cnt++; } else if (i && next(i) < i && next(i - 1) > next(i)) { upd(i, i - 1); upd(i - 1, i); swap(a[i], a[i - 1]); cnt++; } } } cout << cnt << endl; return 0; }
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Avalon-ST to AXI stream
*/
module avst2axis #(
parameter DATA_WIDTH = 8,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH),
parameter BYTE_REVERSE = 0
)
(
input wire clk,
input wire rst,
output wire avst_ready,
input wire avst_valid,
input wire [DATA_WIDTH-1:0] avst_data,
input wire avst_startofpacket,
input wire avst_endofpacket,
input wire [EMPTY_WIDTH-1:0] avst_empty,
input wire avst_error,
output wire [DATA_WIDTH-1:0] axis_tdata,
output wire [KEEP_WIDTH-1:0] axis_tkeep,
output wire axis_tvalid,
input wire axis_tready,
output wire axis_tlast,
output wire axis_tuser
);
parameter BYTE_WIDTH = KEEP_ENABLE ? DATA_WIDTH / KEEP_WIDTH : DATA_WIDTH;
assign avst_ready = axis_tready;
generate
genvar n;
if (BYTE_REVERSE) begin : rev
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin
assign axis_tdata[n*BYTE_WIDTH +: BYTE_WIDTH] = avst_data[(KEEP_WIDTH-n-1)*BYTE_WIDTH +: BYTE_WIDTH];
end
end else begin
assign axis_tdata = avst_data;
end
endgenerate
assign axis_tkeep = KEEP_ENABLE ? {KEEP_WIDTH{1'b1}} >> avst_empty : 0;
assign axis_tvalid = avst_valid;
assign axis_tlast = avst_endofpacket;
assign axis_tuser = avst_error;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 20:40:34 09/08/2015
// Design Name: SN74LS195A Gate Level Module
// Module Name: SN74LS195Agates
//////////////////////////////////////////////////////////////////////////////////
module SN74LS195Agates(Q, P, Q3not, PE, J, K, CP, MR);
parameter LENGTH = 4;
input PE, J, K, CP, MR;
input [LENGTH-1:0] P;
output [LENGTH-1:0] Q;
output Q3not;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
wire w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, w21;
wire Ki, PEi, CPi;
wire Clear;
not N1(Ki, K);
not N2(PEi, PE);
not N3(CPi, CP);
buf B1(Clear, MR);
and U1(w1, w18, J, PE);
and U2(w2, PE, K, Q[0]);
and U3(w3, PEi, P[0]);
and U4(w4, Q[0], PE);
and U5(w5, PEi, P[1]);
and U6(w6, Q[1], PE);
and U7(w7, PEi, P[2]);
and U8(w8, Q[2], PE);
and U9(w9, PEi, P[3]);
nor U10(w10, w1, w2, w3);
nor U11(w11, w4, w5);
nor U12(w12, w6, w7);
nor U13(w13, w8, w9);
not U14(w14, w10);
not U15(w15, w11);
not U16(w16, w12);
not U17(w17, w13);
not U18(w18, Q[0]);
not U19(Q3not, Q[3]);
SRffwithClear RS0(w14, w10, CPi, MR, Q[0]);
SRffwithClear RS1(w15, w11, CPi, MR, Q[1]);
SRffwithClear RS2(w16, w12, CPi, MR, Q[2]);
SRffwithClear RS3(w17, w13, CPi, MR, Q[3]);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int n, rock = 0, peper = 0, sec = 0, de = 0; cin >> n; cin >> rock >> peper >> sec; string s, ans; cin >> s; for (long long int i = 0; i < n; i++) { if (s[i] == R && peper > 0) { ans = ans + P ; peper--; de++; continue; } else if (s[i] == P && sec > 0) { sec--; ans = ans + S ; de++; continue; } else if (s[i] == S && rock > 0) { rock--; ans = ans + R ; de++; continue; } else { ans = ans + 1 ; } } for (long long int i = 0; i < n; i++) { if (ans[i] == 1 ) { if (rock > 0) { ans[i] = R ; rock--; } else if (peper > 0) { ans[i] = P ; peper--; } else if (sec > 0) { sec--; ans[i] = S ; } } } if (n % 2 == 0) n = n / 2; else n = (n + 1) / 2; if (de >= n) { cout << YES << n ; cout << ans << n ; } else cout << NO << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, k, d, t1, t2, kol; bool f; f = false; cin >> n; cin >> t; cin >> k; cin >> d; t1 = 0; t2 = 0; kol = 0; while (kol < n) { t1++; if (t1 % t == 0) { kol = kol + k; } } kol = 0; while (kol < n) { t2++; if (f == true) { if ((t2 - d) % t == 0) { kol = kol + k; } } if (t2 % t == 0) { kol = kol + k; } if (t2 % d == 0) { f = true; } } if (t1 > t2) { cout << YES ; } else { cout << NO ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_PP_BLACKBOX_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__macro_sparecell (
LO ,
VGND,
VNB ,
VPB ,
VPWR
);
output LO ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long int N = 2e5 + 5; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } long long int n, k; long long int a[N]; long long int month[2 * N]; long long int sum(long long int days) { return (days * (days + 1) / 2); } void solve() { cin >> n >> k; for (long long int i = 0; i < n; i++) { cin >> a[i]; month[i] = a[i]; month[n + i] = a[i]; } long long int j = 0; long long int hugs = 0, days = 0, best = 0; for (long long int i = 0; i < 2 * n; i++) { hugs += sum(month[i]); days += month[i]; while (days > k) { days -= month[j]; hugs -= sum(month[j]); j++; } long long int curr = hugs; if (j > 0) { long long int skips = month[j - 1] + days - k; curr += sum(month[j - 1]) - sum(skips); } best = max(best, curr); } cout << best << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
`define SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_BLACKBOX_V
|
`timescale 1ps / 1ps
module main;
reg clk = 0;
always #1400 clk = !clk;
reg [35:0] in = "1111111111111111111111111111111111";
reg [6:0] out;
reg [6:0] out_golden;
integer seed = 1234;
integer rvec_file;
integer ret;
integer soe0 = 0;
integer soe1 = 0;
integer soe2 = 0;
integer soe3 = 0;
integer soe4 = 0;
integer soe5 = 0;
integer soe6 = 0;
initial begin
$sdf_annotate("mydesign.sdf",DUT,,,"MAXIMUM");
$dumpfile("test.vcd");
$dumpvars(0,main);
assert($urandom(seed));
`ifdef GENTEST
rvec_file = $fopen("../c432.rvec", "w");
`else
rvec_file = $fopen("../c432.rvec", "r");
`endif
if (rvec_file == 0) begin
$display("data_file handle was NULL");
$finish;
end
end
integer num_cycles = 0;
integer max_cycles = 100000;
always @ (posedge clk) begin
std::randomize(in);
if (num_cycles == max_cycles) begin
$display("SoE: %d,%d,%d,%d,%d,%d,%d\n",soe0,soe1,soe2,soe3,soe4,soe5,soe6);
$fclose(rvec_file);
$finish;
end
num_cycles = num_cycles + 1;
end
c432_wrap DUT ({in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7],in[8],in[9],
in[10],in[11],in[12],in[13],in[14],in[15],in[16],in[17],in[18],in[19],
in[20],in[21],in[22],in[23],in[24],in[25],in[26],in[27],in[28],in[29],
in[30],in[31],in[32],in[33],in[34],in[35]},
{out[0],out[1],out[2],out[3],out[4],out[5],out[6]},
clk);
always @ (posedge clk) begin
`ifdef GENTEST
// write output to generate golden result
$fwrite(rvec_file, "%b,%b,%b,%b,%b,%b,%b\n", out[0],out[1],out[2],out[3],out[4],out[5],out[6]);
`else
$fscanf(rvec_file, "%b,%b,%b,%b,%b,%b,%b\n", out_golden[0],out_golden[1],out_golden[2],out_golden[3],out_golden[4],out_golden[5],out_golden[6]);
if (out[0] != out_golden[0]) begin
//$display("ERROR At time %t: out[0]=%b",$time,out[0]);
soe0 = soe0 + 1;
end
if (out[1] != out_golden[1]) begin
soe1 = soe1 + 1;
end
if (out[2] != out_golden[2]) begin
soe2 = soe2 + 1;
end
if (out[3] != out_golden[3]) begin
soe3 = soe3 + 1;
end
if (out[4] != out_golden[4]) begin
soe4 = soe4 + 1;
end
if (out[5] != out_golden[5]) begin
soe5 = soe5 + 1;
end
if (out[6] != out_golden[6]) begin
soe6 = soe6 + 1;
end
`endif
end // always @ (posedge clk)
always @(posedge clk) begin
//$display("At time %t: out[0]=%b,%b - out[1]=%b,%b",$time,out[0],out_golden[0],out[1],out_golden[1]);
end
endmodule
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Module to send tri-state signals to a radio for operation a RC switch.
*
* The following wavefroms are used for the tri-states (each pulse is 350us):
*
* Tri-state "0" Bit
* _ _
* | |___| |___
* 1 3 1 3
*
* Tri-state "1" Bit
* ___ ___
* | |_| |_
* 3 1 3 1
*
* Tri-state "F" Bit
* _ ___
* | |___| |_
* 1 3 3 1
*
* "Sync" Bit
* _
* | |_______________________________
* 1 31
*
* A message to an RC switch has the following format:
*
* <address><channel><status>
*
* <address> is a 5 bit field. Most switches use 11111 as default.
* <channel> is A, B, C, D
* <status> is 0 (off) or 1 (on)
*
* To turn channel A on the switch at address 11111 ON, the message would look like this:
*
* 11111A1
*
* For the module, this needs to be translated to tri-state wave form like so:
*
* 0 in tri-state is F => 10001110
* 1 in tri-state is 0 => 10001000
*
* Thus, the address 11111 is in tri-state: 10001000_10001000_10001000_10001000_10001000
*
* The channel translates like this:
*
* A in tri-state is 0FFFF => 10001000_10001110_10001110_10001110_10001110
* B in tri-state is F0FFF => 10001110_10001000_10001110_10001110_10001110
* C in tri-state is FF0FF => 10001110_10001110_10001000_10001110_10001110
* D in tri-state is FFF0F => 10001110_10001110_10001110_10001000_10001110
*
* Then the state could be mapped like this:
*
* 0/off in tri-state is 0F => 10001000_10001110
* 1/on in tri-state is F0 => 10001110_10001000
*
* And finally the sync bit is a constant:
*
* sync => 10000000_00000000_00000000_00000000
*
*****************************************************************************
* Also it should be noted, that a message needs to be sent multible times (2-10).
* Otherwise it is very likely that the switch will not work!
*****************************************************************************
*
* inputs:
* clk on the positive edge, the next bit is shifted to the radio
* the clock needs to provide 350us per cycle (from rising
* edge to rising edge)
* rst reset
* send if set to 1, the complete message (addr+chan+stat+sync) is send
* over and over again until send is set back to 0
* addr the address in tri-state wave-form
* e.g. 40'b10001000_10001000_10001000_10001000_10001000 = 11111
* chan the channel identifier in tri-state wave-form
* e.g. 40'b10001000_10001110_10001110_10001110_10001110 = chan A
* stat the status in tri-state wave-form
* e.g. 16'b10001000_10001110 = ON
* outputs:
* ready 1 if module is ready to send, 0 if sending is already in progrss
* out the bits shifted out to the radio
*/
module rcswitch_send(
input clk,
input rst,
input send,
input [39:0] addr,
input [39:0] chan,
input [15:0] stat,
output ready,
output out
);
reg r_out;
reg r_ready;
reg [7:0] pos;
reg [127:0] msg;
initial begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
msg <= 0;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
end
else begin
// start a new message
if(send && pos == 0) begin
pos <= 128;
r_ready <= 0;
msg[127:0] <= {addr[39:0], chan[39:0], stat[15:0], 32'b10000000_00000000_00000000_00000000};
end
// shift out the bits for the message
else if(pos > 0) begin
pos <= pos - 1;
r_out <= msg >> pos;
// message is done - prepare for repeat
if(pos == 0) begin
r_ready <= 1;
r_out <= 0;
pos <= 0;
end
else begin
r_ready <= 0;
end
end
else begin
msg <= ~msg;
end
end
end
assign ready = r_ready;
assign out = r_out;
endmodule
/**
* Module to detect tri-state wave forms.
*
* The module will detect a combination of high/low and count the clk cycles for
* each of the two phases:
*
* +---------+ +--
* __| |_________|
* count_h count_l
*
* inputs:
* clk clock used for the counter of high/low times. the clock should be
* a lot faster then the clock of the wave form
* rst reset
* in the input from the radio
* outputs:
* count_h clk counts for the time the wave-form was high
* count_l clk counts for the time the wave-form was low
* detected 1 if tri-state was detected, 0 otherwise
*/
module tri_state_detect (
input clk,
input rst,
input in,
output [31:0] count_h,
output [31:0] count_l,
output detected
);
reg [31:0] ticks;
reg [31:0] t1;
reg [31:0] t2;
reg synced;
reg [31:0] r_count_h;
reg [31:0] r_count_l;
initial begin
ticks <= 0;
t1 <= 0;
t2 <= 0;
synced <= 0;
r_count_h <= 0;
r_count_l <= 0;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
ticks <= 0;
end
else begin
ticks <= ticks + 1;
end
end
always @(negedge in or posedge rst) begin
if(rst) begin
t2 <= 0;
end
else begin
if(t1 > 0) begin
t2 <= ticks;
end
end
end
always @(posedge in or posedge rst) begin
if(rst) begin
t1 <= 0;
r_count_h <= 0;
r_count_l <= 0;
synced <= 0;
end
else begin
if(t2 > t1) begin
r_count_h = t2 - t1;
r_count_l = ticks - t2;
synced <= 1;
end
else begin
synced <= 0;
end
t1 <= ticks;
end
end
assign count_h = r_count_h;
assign count_l = r_count_l;
assign detected = (synced & in);
endmodule
/**
* Module to receive tri-state signals for RC switches send by a radio.
*
* inputs:
* clk clock used for the counter of high/low times. the clock should be
* a lot faster then the clock of the wave form
* rst reset
* in the input from the radio
* outputs:
* addr address received (see rcswitch_send)
* chan channel received (see rcswitch_send)
* stat status received (see rcswitch_send)
* ready 1 if complete message was received, 0 otherwise
*/
module rcswitch_receive(
input clk,
input rst,
input in,
output [39:0] addr,
output [39:0] chan,
output [15:0] stat,
output ready
);
reg [8:0] count;
reg [95:0] msg;
reg [39:0] r_addr;
reg [39:0] r_chan;
reg [15:0] r_stat;
reg r_ready;
initial begin
count <= 0;
msg <= 0;
r_addr <= 0;
r_chan <= 0;
r_stat <= 0;
r_ready <= 0;
end
wire [31:0] count_h;
wire [31:0] count_l;
wire detected;
tri_state_detect tsd_inst (
.clk(clk),
.rst(rst),
.in(in),
.count_h(count_h),
.count_l(count_l),
.detected(detected)
);
always @(posedge detected or posedge rst) begin
if(rst) begin
count <= 0;
r_addr <= 0;
r_chan <= 0;
r_stat <= 0;
r_ready <= 0;
end
else begin
// detected SYNC
if(count_h * 10 < count_l) begin
count <= 0;
msg <= 0;
end
// detected 1000
else if(count_h < count_l) begin
msg <= (msg << 4) | 96'b1000;
count <= count + 1;
end
// detected 1110
else if(count_l < count_h) begin
msg <= (msg << 4) | 96'b1110;
count <= count + 1;
end
// message complete?
if(count == 24) begin
{r_addr[39:0], r_chan[39:0], r_stat[15:0]} <= msg;
r_ready <= 1;
count <= 0;
msg <= 0;
end
else begin
r_ready <= 0;
end
end
end
assign ready = r_ready;
assign addr = r_addr;
assign chan = r_chan;
assign stat = r_stat;
endmodule
|
// DESCRIPTION: Verilator: Dedupe optimization test.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty.
// SPDX-License-Identifier: CC0-1.0
// Contributed 2012 by Varun Koyyalagunta, Centaur Technology.
//
// Test consists of the follow logic tree, which has many obvious
// places for dedupe:
/*
output
+
--------------/ \--------------
/ \
+ +
----/ \----- ----/ \----
/ + / +
+ / \ + / \
-/ \- a b -/ \- a b
/ \ / \
+ + + +
/ \ / \ / \ / \
a b c d a b c d
*/
module t(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left,right;
add add(sum,left,right,clk);
l l(left,a,b,c,d,clk);
r r(right,a,b,c,d,clk);
endmodule
module l(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
ll ll(left,a,b,c,d,clk);
lr lr(right,a,b,c,d,clk);
endmodule
module ll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
lll lll(left,a,b,c,d,clk);
llr llr(right,a,b,c,d,clk);
endmodule
module lll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module llr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,c,d,clk);
endmodule
module lr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module r(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
rl rl(left,a,b,c,d,clk);
rr rr(right,a,b,c,d,clk);
endmodule
module rr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add add(sum,a,b,clk);
endmodule
module rl(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
wire left, right;
add add(sum,left,right,clk);
rll rll(left,a,b,c,d,clk);
rlr rlr(right,a,b,c,d,clk);
endmodule
module rll(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add2 add(sum,a,b,clk);
endmodule
module rlr(sum,a,b,c,d,clk);
output sum;
input a,b,c,d,clk;
add2 add(sum,c,d,clk);
endmodule
module add(sum,x,y,clk);
output reg sum;
input x,y,clk;
reg t1,t2;
always @(posedge clk) begin
sum <= x + y;
end
endmodule
module add2(sum,x,y,clk);
output reg sum;
input x,y,clk;
reg t1,t2;
always @(posedge clk) begin
sum <= x + y;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, m, k, i; bool t = 0; cin >> n >> m >> k; if ((2 * m * n) % k > 0) cout << NO ; else { if (k == 2) cout << YES n0 0 n << n << 0 n0 << m; else { k = (2 * m * n) / k; if (m >= n) { for (i = max(1, (int)(k / m)); i <= n; i++) { if (k % i == 0 && k / i <= m) { t = 1; break; } } if (!t) cout << NO ; else cout << YES n0 0 n << i << 0 n0 << k / i; } else { for (i = max(1, (int)(k / n)); i <= m; i++) { if (k % i == 0 && k / i <= n) { t = 1; break; } } if (!t) cout << NO ; else cout << YES n0 0 n << k / i << 0 n0 << i; } } } return 0; }
|
// Verilog netlist generated by Workcraft 3
module VME (d, lds, dtack, dsr, dsw, ldtack);
input dsr, dsw, ldtack;
output d, lds, dtack;
wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;
IND3D1 U1 (.ZN(U1_ON), .A1(OUT_BUBBLE3_ON), .B1(ldtack), .B2(dsr));
// This inverter should have a short delay
INVD1 IN_BUBBLE3 (.ZN(IN_BUBBLE3_ON), .I(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE5 (.ZN(IN_BUBBLE5_ON), .I(ldtack));
OAI221D1 U7 (.ZN(U7_ON), .A1(IN_BUBBLE3_ON), .A2(d), .B1(IN_BUBBLE5_ON), .B2(OUT_BUBBLE3_ON), .C(dsw));
ND2D1 U8 (.ZN(d), .A1(U7_ON), .A2(U1_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE10 (.ZN(IN_BUBBLE10_ON), .I(OUT_BUBBLE3_ON));
INVD1 OUT_BUBBLE1 (.ZN(OUT_BUBBLE1_ON), .I(U14_ON));
OAI221D1 U14 (.ZN(U14_ON), .A1(d), .A2(dsr), .B1(dsr), .B2(OUT_BUBBLE2_ON), .C(IN_BUBBLE10_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE16 (.ZN(IN_BUBBLE16_ON), .I(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE18 (.ZN(IN_BUBBLE18_ON), .I(dsw));
OAI31D1 U20 (.ZN(U20_ON), .A1(IN_BUBBLE18_ON), .A2(IN_BUBBLE16_ON), .A3(d), .B(OUT_BUBBLE3_ON));
C2 U21 (.Q(lds), .A(U20_ON), .B(OUT_BUBBLE1_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE23 (.ZN(IN_BUBBLE23_ON), .I(OUT_BUBBLE3_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE25 (.ZN(IN_BUBBLE25_ON), .I(OUT_BUBBLE2_ON));
AOI221D1 U26 (.ZN(dtack), .A1(IN_BUBBLE23_ON), .A2(dsw), .B1(d), .B2(OUT_BUBBLE3_ON), .C(IN_BUBBLE25_ON));
// This inverter should have a short delay
INVD1 IN_BUBBLE28 (.ZN(IN_BUBBLE28_ON), .I(OUT_BUBBLE3_ON));
INVD1 OUT_BUBBLE2 (.ZN(OUT_BUBBLE2_ON), .I(U31_ON));
OAI222D1 U31 (.ZN(U31_ON), .A1(IN_BUBBLE28_ON), .A2(dsw), .B1(OUT_BUBBLE2_ON), .B2(d), .C1(d), .C2(lds));
// This inverter should have a short delay
INVD1 IN_BUBBLE33 (.ZN(IN_BUBBLE33_ON), .I(d));
INVD1 OUT_BUBBLE3 (.ZN(OUT_BUBBLE3_ON), .I(U36_ON));
AOI32D1 U36 (.ZN(U36_ON), .A1(IN_BUBBLE33_ON), .A2(ldtack), .A3(OUT_BUBBLE2_ON), .B1(ldtack), .B2(OUT_BUBBLE3_ON));
// signal values at the initial state:
// U1_ON IN_BUBBLE3_ON IN_BUBBLE5_ON U7_ON !d IN_BUBBLE10_ON !OUT_BUBBLE1_ON U14_ON IN_BUBBLE16_ON IN_BUBBLE18_ON U20_ON !lds IN_BUBBLE23_ON IN_BUBBLE25_ON !dtack IN_BUBBLE28_ON !OUT_BUBBLE2_ON U31_ON IN_BUBBLE33_ON !OUT_BUBBLE3_ON U36_ON !dsr !dsw !ldtack
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:35:03 06/30/2013
// Design Name: qadd
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Tes_add.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tes_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + ;
end
end
end
endmodule
|
module SingleCycleProcessor (
output reg [31:0] PC,
output reg [31:0] datain,
output reg [31:0] address,
output reg MW,
input [31:0] instruction,
input [31:0] dataout,
input clk,
input reset_n
);
reg [31:0] nextPC, counter, nextReg, seIM, zfIM;
reg [31:0] R[0:31];
reg RW;
wire [14:0] IM;
wire [4:0] AA, BA, DA;
wire [6:0] op;
wire [3:0] FS;
parameter NOP = 7'b0000000;
parameter MOVA = 7'b1000000;
parameter ADD = 7'b0000010;
parameter SUB = 7'b0000101;
parameter AND = 7'b0001000;
parameter OR = 7'b0001001;
parameter XOR = 7'b0001010;
parameter NOT = 7'b0001011;
parameter ADI = 7'b0100010;
parameter SBI = 7'b0100101;
parameter ANI = 7'b0101000;
parameter ORI = 7'b0101001;
parameter XRI = 7'b0101010;
parameter AIU = 7'b1000010;
parameter SIU = 7'b1000101;
parameter MOVB = 7'b0001100;
parameter LSR = 7'b0001101;
parameter LSL = 7'b0001110;
parameter LD = 7'b0010000;
parameter ST = 7'b0100000;
parameter JMR = 7'b1110000;
parameter SLT = 7'b1100101;
parameter BZ = 7'b1100000;
parameter BNZ = 7'b1001000;
parameter JMP = 7'b1101000;
parameter JML = 7'b0110000;
integer i;
// PC
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
PC <= 0;
for (i = 0; i < 32; i = i + 1) begin
R[i] = 0;
end
end else begin
if (counter == 0) begin
counter <= counter + 1;
PC <= nextPC;
end else begin
counter <= 0;
PC <= nextPC;
if (RW == 1'b1 && DA != 0) begin
R[DA] = nextReg;
end
end
end
end
// Decoder
assign AA = instruction[19:15];
assign BA = instruction[14:10];
assign DA = instruction[24:20];
assign op = instruction[31:25];
assign IM = instruction[14:0];
assign SH = instruction[4:0];
always @(*) begin
if (IM[14] == 1'b0) begin
seIM = {17'd0, IM};
zfIM = {17'd0, IM};
end else begin
seIM = {17'd1, IM};
zfIM = {17'd0, IM};
end
end
always @(*) begin
RW = 1'b0;
MW = 1'b1;
nextReg = 0;
address = 0;
datain = 0;
if (counter == 1) begin
case(op)
MOVA: begin
nextReg = R[AA];
RW = 1'b1;
end
ADD: begin
nextReg = R[AA] + R[BA];
RW = 1'b1;
end
SUB: begin
nextReg = R[AA] + (~R[BA]) + 1;
RW = 1'b1;
end
AND: begin
nextReg = R[AA] & R[BA];
RW = 1'b1;
end
OR: begin
nextReg = R[AA] | R[BA];
RW = 1'b1;
end
XOR: begin
nextReg = R[AA] ^ R[BA];
RW = 1'b1;
end
NOT: begin
nextReg = ~R[AA];
RW = 1'b1;
end
ADI: begin
nextReg = R[AA] + seIM;
RW = 1'b1;
end
SBI: begin
nextReg = R[AA] + (~seIM) + 1;
RW = 1'b1;
end
ANI: begin
nextReg = R[AA] & zfIM;
RW = 1'b1;
end
ORI: begin
nextReg = R[AA] | zfIM;
RW = 1'b1;
end
XRI: begin
nextReg = R[AA] ^ zfIM;
RW = 1'b1;
end
AIU: begin
nextReg = R[AA] + zfIM;
RW = 1'b1;
end
SIU: begin
nextReg = R[AA] + (~zfIM) + 1;
RW = 1'b1;
end
MOVB: begin
nextReg = R[BA];
RW = 1'b1;
end
LSR: begin
nextReg = R[AA] >> SH;
RW = 1'b1;
end
LSL: begin
nextReg = R[AA] << SH;
RW = 1'b1;
end
LD: begin
nextReg = dataout;
RW = 1'b1;
end
ST: begin
address = R[AA];
datain = R[BA];
MW = 1'b0;
end
SLT: begin
if (R[AA] < R[BA]) begin
nextReg = 1;
RW = 1'b1;
end else begin
nextReg = 0;
RW = 1'b1;
end
end
JMR: begin
nextPC = R[AA];
end
JMP: begin
nextPC = PC + 1 + seIM;
end
JML: begin
nextPC = PC + 1 + seIM;
end
BZ: begin
if (R[AA] == 0)
nextPC = PC + 1 + seIM;
else
nextPC = PC + 1;
end
BNZ: begin
if (R[AA] != 0)
nextPC = PC + 1 + seIM;
else
nextPC = PC + 1;
end
default: begin
nextPC = PC + 1;
end
endcase
end else begin
if (op == LD) begin
address = R[AA];
MW = 1'b1;
end
nextPC = PC;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; int result = a; int temp = 0; while ((a + temp) >= b) { int t1 = temp; result += (a + temp) / b; temp = (a + temp) % b; a = (a + t1) / b; } cout << result << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_TB_V
`define SKY130_FD_SC_MS__XOR2_TB_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__xor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_TB_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:52 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P5 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_28_CI, intadd_28_n4, intadd_28_n3, intadd_28_n2, intadd_28_n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18;
CMPR32X2TS intadd_28_U5 ( .A(in2[1]), .B(in1[1]), .C(intadd_28_CI), .CO(
intadd_28_n4), .S(res[1]) );
CMPR32X2TS intadd_28_U4 ( .A(in2[2]), .B(in1[2]), .C(intadd_28_n4), .CO(
intadd_28_n3), .S(res[2]) );
CMPR32X2TS intadd_28_U3 ( .A(in2[3]), .B(in1[3]), .C(intadd_28_n3), .CO(
intadd_28_n2), .S(res[3]) );
CMPR32X2TS intadd_28_U2 ( .A(in2[4]), .B(in1[4]), .C(intadd_28_n2), .CO(
intadd_28_n1), .S(res[4]) );
XOR2XLTS U2 ( .A(in1[6]), .B(in2[6]), .Y(n6) );
AO22XLTS U3 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .B1(in1[2]), .Y(n10) );
CLKAND2X2TS U4 ( .A(in2[1]), .B(in1[1]), .Y(n2) );
CLKAND2X2TS U5 ( .A(in2[0]), .B(in1[0]), .Y(intadd_28_CI) );
AOI222X4TS U6 ( .A0(n13), .A1(n12), .B0(n13), .B1(n11), .C0(n12), .C1(n11),
.Y(n14) );
AOI2BB2XLTS U7 ( .B0(in1[5]), .B1(n8), .A0N(n8), .A1N(in1[5]), .Y(n9) );
INVX2TS U8 ( .A(in2[5]), .Y(n8) );
CMPR32X2TS U9 ( .A(in1[2]), .B(in2[2]), .C(n2), .CO(n3) );
CMPR32X2TS U10 ( .A(in1[3]), .B(in2[3]), .C(n3), .CO(n4) );
CMPR32X2TS U11 ( .A(in1[4]), .B(in2[4]), .C(n4), .CO(n5) );
CMPR32X2TS U12 ( .A(in1[5]), .B(in2[5]), .C(n5), .CO(n7) );
XOR2XLTS U13 ( .A(n7), .B(n6), .Y(res[6]) );
AOI2BB1XLTS U14 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_28_CI), .Y(res[0])
);
XNOR2X1TS U15 ( .A(intadd_28_n1), .B(n9), .Y(res[5]) );
OAI21X1TS U16 ( .A0(in2[3]), .A1(in1[3]), .B0(n10), .Y(n13) );
INVX2TS U17 ( .A(in2[4]), .Y(n12) );
INVX2TS U18 ( .A(in1[4]), .Y(n11) );
AOI222X1TS U19 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n14), .C0(in1[5]), .C1(n14), .Y(n17) );
INVX2TS U20 ( .A(in2[6]), .Y(n16) );
INVX2TS U21 ( .A(in1[6]), .Y(n15) );
AOI222X4TS U22 ( .A0(n17), .A1(n16), .B0(n17), .B1(n15), .C0(n16), .C1(n15),
.Y(n18) );
CMPR32X2TS U23 ( .A(in2[7]), .B(in1[7]), .C(n18), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R1_P5_syn.sdf");
endmodule
|
#include <bits/stdc++.h> using namespace std; long long used[100001], last, a[100001]; vector<long long> v[1000001], verr[100001]; void build(long long tv, long long tl, long long tr) { if (tl == tr) v[tv].push_back(used[tl]); else { long long tm = (tl + tr) / 2; build(tv * 2, tl, tm); build(tv * 2 + 1, tm + 1, tr); long long x = 0, y = 0; while (x < v[tv * 2].size() && y < v[tv * 2 + 1].size()) { if (v[tv * 2][x] < v[tv * 2 + 1][y]) { v[tv].push_back(v[tv * 2][x]); x++; } else { v[tv].push_back(v[tv * 2 + 1][y]); y++; } } while (x < v[tv * 2].size()) { v[tv].push_back(v[tv * 2][x]); x++; } while (y < v[tv * 2 + 1].size()) { v[tv].push_back(v[tv * 2 + 1][y]); y++; } } } long long ans(long long tv, long long tl, long long tr, long long l, long long r, long long z) { if (r < tl || tr < l) return 0; if (l <= tl && tr <= r) { long long x, y; x = 0; y = v[tv].size() - 1; while (x + 1 < y) { long long mm = (x + y) / 2; if (v[tv][mm] < z) x = mm; else y = mm; } if (v[tv][y] < z) return y + 1; if (v[tv][x] < z) return x + 1; return 0; } long long tm = (tl + tr) / 2; return ans(tv * 2, tl, tm, l, r, z) + ans(tv * 2 + 1, tm + 1, tr, l, r, z); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long n, k, i, j, l, r, x, y, q; cin >> n >> k; for (i = 1; i <= n; i++) { cin >> a[i]; verr[a[i]].push_back(i); } for (i = 1; i <= 100000; i++) { for (j = 0; j < verr[i].size(); j++) { if (j + 1 - k > 0) { used[verr[i][j]] = verr[i][j - k]; } } } build(1, 1, n); cin >> q; for (i = 1; i <= q; i++) { cin >> x >> y; l = (x + last) % n + 1; r = (y + last) % n + 1; if (l > r) swap(l, r); last = ans(1, 1, n, l, r, l); cout << last << n ; } }
|
#include <bits/stdc++.h> using namespace std; vector<int> vec; int result[50000]; int MIN(int i, int j) { int ans = 1e9; for (int a = i; a <= j; a++) { ans = min(ans, vec[a]); } return ans; } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < (n); i++) vec.push_back(i + 1); int limit = 1; for (int i = 0; i < (n); i++) limit *= (i + 1); int sum, mx = 0, realsum = 0; for (int z = 0; z < (limit); z++) { for (int i = 0; i < (n); i++) { sum = 0; for (int j = i; j < n; j++) sum += MIN(i, j); ; realsum += sum; } if (realsum > mx) mx = realsum; result[z] = realsum; realsum = 0; next_permutation(vec.begin(), vec.end()); } vector<int> sol; for (int i = 0; i < (n); i++) sol.push_back(i + 1); int cnt = 0; for (int z = 0; z < (limit); z++) { if (result[z] == mx) { cnt++; if (cnt == m) { printf( %d , sol[0]); for (int i = 1; i < n; i++) printf( %d , sol[i]); printf( n ); break; } } next_permutation(sol.begin(), sol.end()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; constexpr int N = 3e3 + 1; int a[N], nxt[N], prv[N], lst[N]; uint16_t dp[N][N]; int main() { cin.tie(0), ios::sync_with_stdio(0); int t, n; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i], --a[i]; } memset(lst, -1, n * sizeof *lst); n = unique(a, a + n) - a; memset(prv, -1, n * sizeof *prv); memset(nxt, 127, n * sizeof *nxt); for (int i = 0; i < n; ++i) { if (lst[a[i]] != -1) { prv[i] = lst[a[i]]; nxt[lst[a[i]]] = i; } lst[a[i]] = i; } for (int i = n - 1; i > -1; --i) for (int j = i + 1; j < n; ++j) { auto t = dp[i + 1][j]; for (int z = nxt[i]; z <= j; z = nxt[z]) { t = max(t, uint16_t(dp[i + 1][z - 1] + dp[z][j] + 1)); } dp[i][j] = t; } cout << n - dp[0][n - 1] - 1 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_LP2_V
`define SKY130_FD_SC_LP__ISO1N_LP2_V
/**
* iso1n: ????.
*
* Verilog wrapper for iso1n with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso1n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1n_lp2 (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.KAGND(KAGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso1n_lp2 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso1n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_LP2_V
|
#include <bits/stdc++.h> using namespace std; const int mv4[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const int mv8[8][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; const int inf = (int)1e9; const char *boo[2] = { NO , YES }; const char *inv = Impossible ; inline void term(string msg = inv) { cout << msg << endl; exit(0); } const char *in = in.txt ; const char *out = out.txt ; struct Point { long long y, x; Point(long long y = 0, long long x = 0) : y(y), x(x) {} Point operator-(const Point &a) { return Point(y - a.y, x - a.x); } }; inline unsigned long long sq(long long d) { return d * d; } inline unsigned long long sqdist(const Point &a, const Point &b) { return sq(a.x - b.x) + sq(a.y - b.y); } inline long long dot(const Point &a, const Point &b) { return a.x * b.x + a.y * b.y; } const int MAX = 1000; int main() { cin.sync_with_stdio(0); cout.sync_with_stdio(0); int n; unsigned long long r = 0; cin >> n; vector<Point> v(n); unordered_map<int, int> dup, ddown; for (int i = 0; i < n; i++) { cin >> v[i].x >> v[i].y; dup[v[i].y - v[i].x]++; ddown[v[i].y + v[i].x]++; } for (auto e : dup) { unsigned long long t = (e.second * (e.second - 1)) / 2; r += t; } for (auto e : ddown) { unsigned long long t = (e.second * (e.second - 1)) / 2; r += t; } cout << r << n ; exit(0); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, i; cin >> n; int la, ra; int cnt00 = 0, cnt01 = 0, cnt10 = 0, cnt11 = 0; for (i = 0; i < n; i++) { cin >> la >> ra; if (la == 1) { if (ra == 0) cnt10++; else cnt11++; } else { if (ra == 0) cnt00++; else cnt01++; } } int a00 = cnt01 + cnt10 + 2 * cnt11; int a01 = cnt11 + cnt00 + 2 * cnt10; int a10 = cnt11 + cnt00 + 2 * cnt01; int a11 = cnt01 + cnt10 + 2 * cnt00; cout << min(a00, min(a01, min(a10, a11))); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; string s[11]; int a[11]; int n, k; int ans = 0x7fffffff; string t[11]; int num[11]; int main() { cin >> n >> k; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < k; i++) { a[i] = i; } do { for (int i = 0; i < n; i++) { for (int j = 0; j < k; j++) { t[i][j] = s[i][a[j]]; } } for (int i = 0; i < n; i++) { int tt = 0; for (int j = 0; j < k; j++) { tt = tt * 10 + t[i][j] - 0 ; } num[i] = tt; } sort(num, num + n); ans = min(ans, num[n - 1] - num[0]); } while (next_permutation(a, a + k)); cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:38:56 06/14/2016
// Design Name:
// Module Name: LZD_16bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_16bit( in, out, valid
);
input [15:0]in;
output reg [3:0]out;
output reg valid;
wire v1,v2;
wire [2:0]l1, l2;
initial
begin
out<=4'b0000;
valid<=0;
end
LZD_8bit d5( .in(in[7:0]), .out(l1), .valid(v1));
LZD_8bit d6( .in(in[15:8]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2)
begin
if(v2==0&&v1==1)
begin
out<={{~v2},{l1}} ;
end
/*
here l1, l2 are 3 bits each and v1,v2 are 1bit
when v2=0
eg- 0000_0000_0010_0100
v2=0,l2=3'b000, v1=1, l1=3'b010
out= {{1},{010}}= {1010}=10 there are 10 leading zeros in 0000_0000_0010_0100
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*eg- 0000_0100_0010_0100
v2=0,l2=3'b101, v1=1, l1=3'b010
out= {{1},{101}}= {0101}=5 there are 5 leading zeros in 0000_0100_0010_0100
*/
valid<= v1|v2 ; /* valid = in[15]|in[14]|in[13]|in[12]|in[11]|in[10]|in[9]|in[8]
|in[7]|in[6]|in[5]|in[4]|in[3]|in[2]|in[1]|in[0]*/
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0LL) return a; return gcd(b, a % b); } long long bigmod(long long a, long long b, long long mod) { if (b == 0LL) return 1LL; long long sq = bigmod(a, b / 2LL, mod); sq = (sq * sq) % mod; if (b & 1LL) return (sq * (a % mod)) % mod; return sq; } vector<int> primes; vector<int> sieve(const int n) { vector<int> primes(n + 1, 0); primes[1] = 1; for (int p = 2; p * p <= n; p++) { if (!primes[p]) { for (int i = p * p; i <= n; i += p) primes[i] = p; } } for (int i = 2; i <= n; i++) if (!primes[i]) primes[i] = i; return primes; } map<int, int> getDivs(int x) { map<int, int> divs; while (x > 1) { int div = primes[x]; int cnt = 0; while (x % div == 0) { x /= div; cnt++; } divs[div] = cnt; } return divs; } void solve() { int n; cin >> n; vector<int> a(n); vector<int> cm(n + 1, 100000000); for (auto &x : (a)) { cin >> x; } for (int i = n - 1; i >= 0; i--) { cm[i] = min(cm[i + 1], a[i]); } int ans = 0; for (int i = 1; i < n; i++) { if (cm[i] < a[i - 1]) ans++; } cout << ans << endl; } int main() { int t = 1; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int arr[n], i, c = 0; for (i = 0; i < n; i++) { cin >> arr[i]; if (arr[i] == 1) c++; } if (c == n) { for (i = 0; i < n - 1; i++) cout << 1 << ; cout << 2 << n ; } else { sort(arr, arr + n); cout << 1 << ; for (i = 0; i < n - 1; i++) cout << arr[i] << ; cout << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s1, s2; cin >> s1 >> s2; int flag = 0; if (n % 2 != 0) flag = 1; int mid; if (flag) mid = (n + 1) / 2; else mid = n / 2; int cnt = 0; for (int i = 0; i < n / 2; i++) { int l = i, r = n - i - 1; int a[30]; fill(a, a + 30, 0); a[s1[l] - a ]++; a[s1[r] - a ]++; a[s2[l] - a ]++; a[s2[r] - a ]++; int k = 0; int b[4]; int counts = 0; for (int j = 0; j < 30; j++) { if (a[j]) k++; if (a[j]) { b[counts++] = a[j]; } } sort(b, b + k); if (k == 4) { cnt += 2; continue; } if (k == 3) { if (s1[l] == s1[r]) cnt += 2; else cnt++; } if (k == 2) { if (b[1] == 3) { cnt++; } } } if (flag) if (s1[mid - 1] != s2[mid - 1]) cnt++; cout << cnt; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100, LEN = 21, M = 1 << LEN, inF = N * 30; int n, len, ps[N], dp0[N], dp1[N], mini[M][LEN]; string s[N]; void _min(int &a, int b) { a = min(a, b); } int same(string a, string b) { int A = 0, B = 0, res = 0; for (int i = 0; i < len; i++) { A |= (a[len - i - 1] - 0 ) << i; B = (B << 1) | (b[i] - 0 ); if (A == B) res = i + 1; } return res; } int dif(string a, string b) { return len - same(a, b); } void add(int dex) { _min(mini[0][0], dp1[dex] - ps[dex] + len - 0); int val = 0; for (int i = 1; i <= len; i++) val |= (s[dex - 1][len - i] - 0 ) << (i - 1), _min(mini[val][i], dp1[dex] - ps[dex] + len - i); } void find_dp() { dp0[0] = dp1[0] = len; for (int i = 1; i < n; i++) { dp0[i] = min(dp0[i - 1], dp1[i - 1]) + dif(s[i - 1], s[i]); dp1[i] = min((i == 1 ? len << 1 : dp1[i - 1] + dif(s[i - 2], s[i])), ps[i - 1] + len); int val = 0; _min(dp1[i], mini[val][0] + ps[i - 1]); for (int j = 1; j <= len; j++) val = (val << 1) | (s[i][j - 1] - 0 ), _min(dp1[i], mini[val][j] + ps[i - 1]); if (i != n - 1) add(i); } } int main() { for (int i = 0; i < M; i++) fill(mini[i], mini[i] + LEN, inF); cin >> n; for (int i = 0; i < n; i++) { cin >> s[i]; ps[i] = (i ? ps[i - 1] + dif(s[i - 1], s[i]) : len = s[i].length()); } find_dp(); cout << min(dp0[n - 1], dp1[n - 1]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, sum, sum1, count = 1; cin >> n; int arr[4 * n + 1]; arr[0] = 0; for (i = 1; i <= 4 * n - 3; i = i + 4) { cin >> arr[i] >> arr[i + 1] >> arr[i + 2] >> arr[i + 3]; if (i == 1) sum = arr[1] + arr[2] + arr[3] + arr[4]; else { sum1 = arr[i] + arr[i + 1] + arr[i + 2] + arr[i + 3]; if (sum1 > sum) count++; } } cout << count; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s = ; vector<int> fib; fib.push_back(1); fib.push_back(1); for (int i = 2; i < 17; ++i) { fib.push_back(fib[i - 1] + fib[i - 2]); } for (int i = 1; i <= n; ++i) { if (binary_search(fib.begin(), fib.end(), i) == 1) { s.append(1u, O ); } else { s.append(1u, o ); } } cout << s << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; int k = 1; int r = 0; int index1, index2; cin >> n; vector<pair<pair<int, int>, pair<int, int>>> s(n); vector<int> t(3); for (int i = 0; i < n; i++) { scanf( %i%i%i , &t[0], &t[1], &t[2]); sort(t.begin(), t.end()); s[i].first.first = t[2]; s[i].first.second = t[1]; s[i].second.first = t[0]; s[i].second.second = i; if (t[0] > r) { index1 = i; r = t[0]; } } sort(s.begin(), s.end()); for (int i = 0; i < s.size() - 1; i++) { if (s[i].first.first == s[i + 1].first.first && s[i].first.second == s[i + 1].first.second) { int temp = min(s[i].second.first + s[i + 1].second.first, min(s[i].first.first, s[i].first.second)); if (temp > r) { r = temp; index1 = s[i].second.second; index2 = s[i + 1].second.second; k = 2; } } } cout << k << endl; if (k == 1) { cout << index1 + 1 << endl; } else cout << index1 + 1 << << index2 + 1 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_TB_V
`define SKY130_FD_SC_HS__A21BOI_TB_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a21boi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21boi dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_TB_V
|
#include <bits/stdc++.h> using namespace std; struct pvec { long long int x, y; pvec(long long int x = 0, long long int y = 0) : x(x), y(y) {} pvec operator-(pvec p) { return pvec(x - p.x, y - p.y); } bool operator==(pvec p) { return x == p.x and y == p.y; } long long int dot(pvec p) { return x * p.x + y * p.y; } long long int abs2() { return x * x + y * y; } }; pvec v[12], Q[12], R[12]; long long int Qi[12], Ri[12]; long long int perm[][3] = {{1, 2, 3}, {1, 3, 2}, {2, 1, 3}, {2, 3, 1}, {3, 1, 2}, {3, 2, 1}}; inline bool quadrado() { for (long long int i = 0; i < 6; i++) { pvec p0 = Q[0]; pvec p1 = Q[perm[i][0]]; pvec p2 = Q[perm[i][1]]; pvec p3 = Q[perm[i][2]]; pvec v1 = p1 - p0, v2 = p2 - p1, v3 = (p2 - p3), v4 = (p3 - p0); if (!(v1 == v3 and v2 == v4)) continue; if (v1.abs2() != v2.abs2()) continue; if (v1.dot(v2) != 0) continue; return true; } return false; } inline bool retangulo() { for (long long int i = 0; i < 6; i++) { pvec p0 = R[0]; pvec p1 = R[perm[i][0]]; pvec p2 = R[perm[i][1]]; pvec p3 = R[perm[i][2]]; pvec v1 = p1 - p0, v2 = p2 - p1, v3 = (p2 - p3), v4 = (p3 - p0); if (!(v1 == v3 and v2 == v4)) continue; if (v1.dot(v2) != 0) continue; return true; } return false; } bool da(long long int u, long long int quad, long long int ret) { if (quad > 4 or ret > 4) return false; if (u == 8) { if (quadrado() and retangulo()) return true; return false; } Q[quad] = v[u]; Qi[quad] = u; if (da(u + 1, quad + 1, ret)) return true; R[ret] = v[u]; Ri[ret] = u; if (da(u + 1, quad, ret + 1)) return true; return false; } int main() { for (long long int i = 0; i < 8; i++) { long long int x, y; cin >> x >> y; v[i] = pvec(x, y); } if (!da(0, 0, 0)) { cout << NO << endl; } else { cout << YES << endl; for (long long int i = 0; i < 4; i++) { if (i) printf( ); cout << Qi[i] + 1; } cout << endl; for (long long int i = 0; i < 4; i++) { if (i) printf( ); cout << Ri[i] + 1; } cout << endl; } return 0; }
|
module piano(sound, t0,t1,t2,t3,t4,t5,t6,t7,clk);
output wire[7:0] sound;
input t0,t1,t2,t3,t4,t5,t6,t7,clk;
wire [7:0] Chord;
wire [7:0] freq;
wire[3:0] sim,n;
wire [7:0] wave1,wave2,wave3,wave4,wave5,wave6,wave0,wave7;
wire ci0,ci1,ci2,ci3,ci4,ci5;
wire [7:0]clks;
wire [15:0]wavef;
assign Chord[0]=t0;
assign Chord[1]=t1;
assign Chord[2]=t2;
assign Chord[3]=t3;
assign Chord[4]=t4;
assign Chord[5]=t5;
assign Chord[6]=t6;
assign Chord[7]=t7;
divfreq note0(freq,Chord,clk);
assign clks = freq;
rom n0(clks[0],wave0);
rom n1(clks[1],wave1);
rom n2(clks[2],wave2);
rom n3(clks[3],wave3);
rom n4(clks[4],wave4);
rom n5(clks[5],wave5);
rom n6(clks[6],wave6);
rom n7(clks[7],wave7);
assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7;
assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;
assign sound = (sim==0) ? 0:
(sim==1) ? wavef[7:0]:
(sim==2) ? wavef[8:1]:
(sim==3) ? wavef[9:2]:
(sim==4) ? wavef[10:3]:
(sim==5) ? wavef[11:4]:
(sim==6) ? wavef[12:5]:
(sim==7) ? wavef[13:6]:
(sim==8) ? wavef[14:7]:
wavef[15];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long A, B; int N; long long l, r, t, tt, M; cin >> A >> B >> N; for (int i = 0; i < N; i++) { scanf( %I64d%I64d%I64d , &l, &t, &M); long long st = l, ed = l + 1000000; long long H = A + (l - 1) * B; long long D = B, C = t / B; if (t < H) { puts( -1 ); continue; } while (ed - st > 1) { long long md = (st + ed) >> 1; long long E = A + (md - 1) * B; long long L = md - l + 1; long long tot = (H + E) * L / 2; long long tt = max(E, (tot - 1 + M) / M); if (t >= tt) st = md; else ed = md; } long long E = A + (ed - 1) * B; long long L = ed - l + 1; long long tot = (H + E) * L / 2; long long tt = max(E, (tot - 1 + M) / M); if (t >= tt) st++; cout << st << endl; } }
|
#include <bits/stdc++.h> using namespace std; struct seg { int l, r, i; bool operator<(const seg& b) const { return l < b.l; } }; int n, k; seg a[200005]; bool u[400005]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i].l >> a[i].r, a[i].i = i; sort(a, a + n); set<pair<int, int>> pq; for (int i = 0; i < k; i++) pq.insert({0, n + i}); for (int i = 0; i < n; i++) { auto it = pq.lower_bound({a[i].l, -1}); if (it == pq.begin()) { it = --pq.end(); if (a[i].r < it->first) { u[it->second] = 1; pq.erase(it); pq.insert({a[i].r, a[i].i}); } else { u[a[i].i] = 1; } } else { --it; pq.erase(it); pq.insert({a[i].r, a[i].i}); } } cout << count(u, u + n, 1) << n ; for (int i = 0; i < n; i++) if (u[i]) cout << i + 1 << ; cout << n ; }
|
#include <bits/stdc++.h> using namespace std; int n, m, ans; vector<int> v[100010]; int main() { cin >> n >> m; for (int i = 1; i <= m; ++i) { int x, y; scanf( %d%d , &x, &y); v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; ++i) ans += v[i].size() % 2; ans /= 2; for (int i = 1; i <= n; ++i) { if (v[i].size() != 2) continue; int x = v[i][0], y = v[i][1]; if (x == y) { v[x].clear(); ++ans; continue; } v[x][v[x][1] == i] = y; v[y][v[y][1] == i] = x; } cout << ans << << m << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long get(long long r) { return (r + 1) * r / 2; } long long sumto(long long r, int need) { long long pw = 1; long long sum = 0; long long add = 0; for (int len = 1;; ++len) { if (pw * 10 - 1 < r) { long long cnt = pw * 10 - pw; if (need) { sum += add * cnt + get(cnt) * len; add += cnt * len; } else { sum += cnt * len; } } else { long long cnt = r - pw + 1; if (need) { sum += add * cnt + get(cnt) * len; } else { sum += cnt * len; } break; } pw *= 10; } return sum; } int main() { int q; cin >> q; while (q--) { long long k; cin >> k; --k; long long l = 1, r = 1e9; long long res = -1; while (r - l >= 0) { long long mid = (l + r) >> 1; if (sumto(mid, 1) > k) { res = mid; r = mid - 1; } else { l = mid + 1; } } k -= sumto(res - 1, 1); l = 1, r = res; long long num = -1; while (r - l >= 0) { int mid = (l + r) >> 1; if (sumto(mid, 0) > k) { num = mid; r = mid - 1; } else { l = mid + 1; } } cout << to_string(num)[k - sumto(num - 1, 0)] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j, line[35], column[35], var, count; cin >> n; for (i = 1; i <= n; ++i) line[i] = column[i] = 0; for (i = 1; i <= n; ++i) for (j = 1; j <= n; ++j) { cin >> var; line[i] += var; column[j] += var; } count = 0; for (i = 1; i <= n; ++i) for (j = 1; j <= n; ++j) { if (column[i] > line[j]) count++; } cout << count; return 0; }
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm_mc_arithmetic.v
// Title : Multi-cycle arithmetic unit.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`define LM32_MC_STATE_RNG 2:0
`define LM32_MC_STATE_IDLE 3'b000
`define LM32_MC_STATE_MULTIPLY 3'b001
`define LM32_MC_STATE_MODULUS 3'b010
`define LM32_MC_STATE_DIVIDE 3'b011
`define LM32_MC_STATE_SHIFT_LEFT 3'b100
`define LM32_MC_STATE_SHIFT_RIGHT 3'b101
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_mc_arithmetic (
// ----- Inputs -----
clk_i,
rst_i,
stall_d,
kill_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_d,
modulus_d,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply_d,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left_d,
shift_right_d,
sign_extend_d,
`endif
operand_0_d,
operand_1_d,
// ----- Ouputs -----
result_x,
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x,
`endif
stall_request_x
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_d; // Stall instruction in D stage
input kill_x; // Kill instruction in X stage
`ifdef CFG_MC_DIVIDE_ENABLED
input divide_d; // Perform divide
input modulus_d; // Perform modulus
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
input multiply_d; // Perform multiply
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
input shift_left_d; // Perform left shift
input shift_right_d; // Perform right shift
input sign_extend_d; // Whether to sign-extend (arithmetic) or zero-extend (logical)
`endif
input [`LM32_WORD_RNG] operand_0_d;
input [`LM32_WORD_RNG] operand_1_d;
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_WORD_RNG] result_x; // Result of operation
reg [`LM32_WORD_RNG] result_x;
`ifdef CFG_MC_DIVIDE_ENABLED
output divide_by_zero_x; // A divide by zero was attempted
reg divide_by_zero_x;
`endif
output stall_request_x; // Request to stall pipeline from X stage back
wire stall_request_x;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_WORD_RNG] p; // Temporary registers
reg [`LM32_WORD_RNG] a;
reg [`LM32_WORD_RNG] b;
`ifdef CFG_MC_DIVIDE_ENABLED
wire [32:0] t;
`endif
reg [`LM32_MC_STATE_RNG] state; // Current state of FSM
reg [5:0] cycles; // Number of cycles remaining in the operation
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
reg sign_extend_x; // Whether to sign extend of zero extend right shifts
wire fill_value; // Value to fill with for right barrel-shifts
`endif
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Stall pipeline while any operation is being performed
assign stall_request_x = state != `LM32_MC_STATE_IDLE;
`ifdef CFG_MC_DIVIDE_ENABLED
// Subtraction
assign t = {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]} - b;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
// Determine fill value for right shift - Sign bit for arithmetic shift, or zero for logical shift
assign fill_value = (sign_extend_x == `TRUE) & b[`LM32_WORD_WIDTH-1];
`endif
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Perform right shift
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
cycles <= {6{1'b0}};
p <= {`LM32_WORD_WIDTH{1'b0}};
a <= {`LM32_WORD_WIDTH{1'b0}};
b <= {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
sign_extend_x <= 1'b0;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= `FALSE;
`endif
result_x <= {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
else
begin
`ifdef CFG_MC_DIVIDE_ENABLED
divide_by_zero_x <= `FALSE;
`endif
case (state)
`LM32_MC_STATE_IDLE:
begin
if (stall_d == `FALSE)
begin
cycles <= `LM32_WORD_WIDTH;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
`ifdef CFG_MC_DIVIDE_ENABLED
if (divide_d == `TRUE)
state <= `LM32_MC_STATE_DIVIDE;
if (modulus_d == `TRUE)
state <= `LM32_MC_STATE_MODULUS;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
if (multiply_d == `TRUE)
state <= `LM32_MC_STATE_MULTIPLY;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
if (shift_left_d == `TRUE)
begin
state <= `LM32_MC_STATE_SHIFT_LEFT;
sign_extend_x <= sign_extend_d;
cycles <= operand_1_d[4:0];
a <= operand_0_d;
b <= operand_0_d;
end
if (shift_right_d == `TRUE)
begin
state <= `LM32_MC_STATE_SHIFT_RIGHT;
sign_extend_x <= sign_extend_d;
cycles <= operand_1_d[4:0];
a <= operand_0_d;
b <= operand_0_d;
end
`endif
end
end
`ifdef CFG_MC_DIVIDE_ENABLED
`LM32_MC_STATE_DIVIDE:
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
cycles <= cycles - 1'b1;
end
`LM32_MC_STATE_MODULUS:
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b1};
end
else
begin
p <= {p[`LM32_WORD_WIDTH-2:0], a[`LM32_WORD_WIDTH-1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
end
result_x <= p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
begin
// Check for divide by zero
divide_by_zero_x <= b == {`LM32_WORD_WIDTH{1'b0}};
state <= `LM32_MC_STATE_IDLE;
end
cycles <= cycles - 1'b1;
end
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
`LM32_MC_STATE_MULTIPLY:
begin
if (b[0] == 1'b1)
p <= p + a;
b <= {1'b0, b[`LM32_WORD_WIDTH-1:1]};
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= p;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`LM32_MC_STATE_SHIFT_LEFT:
begin
a <= {a[`LM32_WORD_WIDTH-2:0], 1'b0};
result_x <= a;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`LM32_MC_STATE_SHIFT_RIGHT:
begin
b <= {fill_value, b[`LM32_WORD_WIDTH-1:1]};
result_x <= b;
if ((cycles == `LM32_WORD_WIDTH'd0) || (kill_x == `TRUE))
state <= `LM32_MC_STATE_IDLE;
cycles <= cycles - 1'b1;
end
`endif
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long ans1, ans2; long long n, m; cin >> n >> m; ans1 = n * m / 2; ans2 = ans1; if (n * m % 2) ans1++; long long x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; long long white1 = (x2 - x1 + 1) * (y2 - y1 + 1) / 2; long long black1 = white1; if ((x2 - x1 + 1) * (y2 - y1 + 1) % 2) { if (abs(x2 - y2) % 2) black1++; else white1++; } long long x3, y3, x4, y4; cin >> x3 >> y3 >> x4 >> y4; long long white2 = (x4 - x3 + 1) * (y4 - y3 + 1) / 2; long long black2 = white2; if ((x4 - x3 + 1) * (y4 - y3 + 1) % 2) { if (abs(x4 - y3) % 2) black2++; else white2++; } long long x5 = max(x1, x3), y5 = max(y1, y3), x6 = min(x2, x4), y6 = min(y2, y4); long long white = 0, black = 0; if (x5 <= x6 && y5 <= y6) { long long gapx = x6 - x5 + 1; long long gapy = y6 - y5 + 1; white = gapx * gapy / 2; black = white; if (gapx * gapy % 2) { if (abs(x5 - y5) % 2) black++; else white++; } } ans1 -= white; ans2 -= black; white1 -= white; black1 -= black; white2 -= white; black2 -= black; ans1 += black1; ans2 -= black1; ans2 += white2; ans1 -= white2; ans2 += white + black; cout << ans1 << << ans2 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const long long INF = 1e18; struct P { int id; long long dis; friend bool operator<(P a, P b) { return a.dis > b.dis; } }; int n, m, q, x[N], y[N], t[N], l[2][N], id[N], c; long long d[2][N], ans[N], pre[N]; vector<long long> add[N], del[N]; vector<int> g[N]; void dij(int p, int s) { memset(d[p], 0x3f, sizeof(d[p])), d[p][s] = 0; if (p) memset(pre, 0, sizeof(pre)); priority_queue<P> q; q.push((P){s, 0ll}); while (!q.empty()) { int u = q.top().id; long long nd = q.top().dis; q.pop(); if (nd != d[p][u]) continue; for (auto e : g[u]) { int v = x[e] + y[e] - u; long long w = t[e]; if (d[p][u] + w < d[p][v]) q.push((P){v, d[p][v] = d[p][u] + w}), pre[v] = e; } } } void it(int p, int s) { priority_queue<P> q; for (int i = 1; i <= n; i++) if (l[p][i] || i == 1) q.push((P){i, l[p][i]}); while (!q.empty()) { int u = q.top().id; q.pop(); for (auto e : g[u]) if (!id[e]) { int v = x[e] + y[e] - u; long long w = t[e]; if (d[p][u] + w == d[p][v] && l[p][u] < l[p][v]) q.push((P){v, l[p][v] = l[p][u]}); } } } void solve(int i) { if (l[0][x[i]] >= l[1][y[i]]) return; long long val = d[0][x[i]] + t[i] + d[1][y[i]]; add[l[0][x[i]]].push_back(val), del[l[1][y[i]]].push_back(val); } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &x[i], &y[i], &t[i]); g[x[i]].push_back(i), g[y[i]].push_back(i); } dij(0, 1), dij(1, n), memset(l[0], 0x3f, sizeof(l[0])); for (int u = 1; u != n;) { int e = pre[u], v = x[e] + y[e] - u; u = v, l[0][u] = l[1][u] = id[e] = ++c, l[1][u] = -l[1][u]; } l[0][1] = 0, it(0, 1), it(1, n); for (int i = 1; i <= n; i++) l[1][i] = -l[1][i]; for (int i = 1; i <= m; i++) if (!id[i]) solve(i), swap(x[i], y[i]), solve(i); multiset<long long> s; s.insert(INF); for (int i = 0; i < c; i++) { for (auto v : add[i]) s.insert(v); for (auto v : del[i]) s.erase(v); ans[i + 1] = *s.begin(); } while (q--) { int e; long long len; scanf( %d%lld , &e, &len); long long res = len + min(d[0][x[e]] + d[1][y[e]], d[0][y[e]] + d[1][x[e]]); if (len <= t[e] || !id[e]) res = min(res, d[0][n]); else if (id[e]) res = min(res, ans[id[e]]); printf( %lld n , res); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int sum(int a, int b) { int s = a + b; if (s >= mod) s -= mod; return s; } int sub(int a, int b) { int s = a - b; if (s < 0) s += mod; return s; } int mult(int a, int b) { return (1LL * a * b) % mod; } int n, k; int len; const int maxN = (int)1e5 + 10; const int maxK = 105; int dp[maxN][maxK]; int sum_pref[maxN]; int a[maxN]; int f[maxN][maxK]; int all[maxN]; bool can(int l, int r, int color) { return (all[r] - all[l - 1] == f[r][color] - f[l - 1][color]); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); srand(239); cin >> n >> k >> len; for (int i = 1; i <= n; i++) { cin >> a[i]; for (int color = 1; color <= k; color++) { f[i][color] = f[i - 1][color]; f[i][color] += (color == a[i]); } all[i] = all[i - 1] + (a[i] > 0); } if (len == 1) { cout << 0; return 0; } sum_pref[0] = 1; for (int i = 1; i <= n; i++) { for (int color = 1; color <= k; color++) { if (a[i] != -1 && a[i] != color) continue; dp[i][color] = sum_pref[i - 1]; if (i >= len && can(i - len + 1, i, color)) { dp[i][color] = sub(dp[i][color], sub(sum_pref[i - len], dp[i - len][color])); } sum_pref[i] = sum(sum_pref[i], dp[i][color]); } } cout << sum_pref[n]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_4_V
`define SKY130_FD_SC_HD__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_4_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [6:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [6:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module DIGDUG_ROM (
clka,
ena,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [15 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("DIGDUG_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_READ_WIDTH_A(16),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(16),
.C_READ_WIDTH_B(16),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("7"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 10.264701 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(16'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(16'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(16'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdlsrc\qpskhdltest\QPSK_Demodulator_Baseband.v
// Created: 2014-04-21 15:30:34
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Demodulator_Baseband
// Source Path: qpskhdltest/QPSK Demodulator Baseband
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Demodulator_Baseband
(
in0_re,
in0_im,
out0
);
input signed [15:0] in0_re; // sfix16_En15
input signed [15:0] in0_im; // sfix16_En15
output [1:0] out0; // ufix2
wire inphase_lt_zero;
wire inphase_eq_zero;
wire quadrature_lt_zero;
wire quadrature_eq_zero;
wire [3:0] decisionLUTaddr; // ufix4
wire [1:0] DirectLookupTable_1 [0:15]; // ufix2 [16]
wire [1:0] hardDecision; // ufix2
assign inphase_lt_zero = (in0_re < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign inphase_eq_zero = (in0_re == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_lt_zero = (in0_im < 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign quadrature_eq_zero = (in0_im == 16'sb0000000000000000 ? 1'b1 :
1'b0);
assign decisionLUTaddr = {inphase_lt_zero, inphase_eq_zero, quadrature_lt_zero, quadrature_eq_zero};
assign DirectLookupTable_1[0] = 2'b00;
assign DirectLookupTable_1[1] = 2'b00;
assign DirectLookupTable_1[2] = 2'b10;
assign DirectLookupTable_1[3] = 2'b00;
assign DirectLookupTable_1[4] = 2'b01;
assign DirectLookupTable_1[5] = 2'b00;
assign DirectLookupTable_1[6] = 2'b10;
assign DirectLookupTable_1[7] = 2'b00;
assign DirectLookupTable_1[8] = 2'b01;
assign DirectLookupTable_1[9] = 2'b11;
assign DirectLookupTable_1[10] = 2'b11;
assign DirectLookupTable_1[11] = 2'b00;
assign DirectLookupTable_1[12] = 2'b00;
assign DirectLookupTable_1[13] = 2'b00;
assign DirectLookupTable_1[14] = 2'b00;
assign DirectLookupTable_1[15] = 2'b00;
assign hardDecision = DirectLookupTable_1[decisionLUTaddr];
assign out0 = hardDecision;
endmodule // QPSK_Demodulator_Baseband
|
#include <bits/stdc++.h> using namespace std; int n; int a[1005]; int main() { cin >> n; int x; int ans = 0; if (n == 1) { cin >> x; if (x) cout << YES << endl; else cout << NO << endl; return 0; } for (int i = 0; i < n; i++) { cin >> x; ans += x; } if (ans == n - 1) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int arr[200005]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); int now = arr[0], cnt = 1; set<int> sup; stack<int> sdown; sup.insert(now); for (int i = 1; i < n; i++) { if (arr[i] == now) { cnt++; sdown.push(arr[i]); } else { now = arr[i]; sup.insert(now); cnt = 1; } if (cnt >= 3) { cout << NO << endl; return 0; } } cout << YES << endl; cout << sup.size() << endl; bool flag = true; for (auto i = sup.begin(); i != sup.end(); i++) { if (flag) { cout << *i; flag = false; } else cout << << *i; } cout << endl; cout << sdown.size() << endl; flag = true; while (!sdown.empty()) { if (flag) { cout << sdown.top(); flag = false; } else cout << << sdown.top() << endl; sdown.pop(); } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_LP_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_LP_BLACKBOX_V
/**
* udp_dlatch$lP: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$lP (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_LP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O32AI_BEHAVIORAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_BEHAVIORAL_V
|
// Nonstop version of loop
// Always keeps looping when increase == true
// At end is a signal to indicate the next cycle is end
// Use that to signal parent loop to advance.
`define NONSTOP_LOOP(iter, width, init, ready, finish, min, extent)\
reg [width-1:0] iter;\
wire finish;\
always@(posedge clk) begin\
if (rst || init) begin\
iter <= (min);\
end else if(ready) begin\
if (iter != ((extent)-1)) begin\
iter <= iter + 1;\
end else begin\
iter <= (min);\
end\
end else begin\
iter <= iter;\
end\
end\
assign finish = (ready && (iter == (extent) - 1));
// Wrap a nonstop loop to normal loop that loop only once.
// Use done signal to control the non-stop body to stop.
// The init and done behaves like normal loop
`define WRAP_LOOP_ONCE(init, valid, ready, body_finish, body_ready)\
reg valid;\
wire body_ready;\
always@(posedge clk) begin\
if (rst || init) begin\
valid <= 1;\
end else if(body_finish) begin\
valid <= 0;\
end else begin\
valid <= valid;\
end\
end\
assign body_ready = (valid && ready);
// Assign dst as src delayed by specific cycles.
`define DELAY(dst, src, width, delay, not_stall)\
reg [(width)*(delay)-1:0] src``_dly_chain;\
always@(posedge clk) begin\
if(rst) begin\
src``_dly_chain <= 0;\
end else if (not_stall) begin\
src``_dly_chain[(width)-1:0] <= src;\
if((delay) != 1) begin\
src``_dly_chain[(delay)*(width)-1:(width)] <= src``_dly_chain[((delay)-1)*(width)-1:0];\
end\
end else begin\
src``_dly_chain <= src``_dly_chain;\
end\
end\
assign dst = src``_dly_chain[(delay)*(width)-1:((delay)-1)*(width)];
// TVM generate clock signal
`define TVM_DEFINE_TEST_SIGNAL(clk, rst)\
parameter PER = 10;\
reg clk;\
reg rst;\
always begin\
#(PER/2) clk =~ clk;\
end
// Control logic on buffer/RAM read valid.
// This delays the valid signal by one cycle and retain it when write_ready == 0
`define BUFFER_READ_VALID_DELAY(dst, data_valid, write_ready)\
reg dst;\
always@(posedge clk) begin\
if(rst) begin\
dst <= 0;\
end else if (write_ready) begin\
dst <= (data_valid);\
end else begin\
dst <= dst;\
end\
end\
// A cache register that add one cycle lag to the ready signal
// This allows the signal to flow more smoothly
`define CACHE_REG(width, in_data, in_valid, in_ready, out_data, out_valid, out_ready)\
reg [width-1:0] out_data``_state_;\
reg [width-1:0] out_data``_overflow_;\
reg out_valid``_state_;\
reg out_valid``_overflow_;\
always@(posedge clk) begin\
if(rst) begin\
out_valid``_overflow_ <= 0;\
out_valid``_state_ <= 0;\
end else if (out_valid``_overflow_) begin\
if (out_ready) begin\
out_valid``_state_ <= 1;\
out_data``_state_ <= out_data``_overflow_;\
out_valid``_overflow_ <= 0;\
out_data``_overflow_ <= 0;\
end else begin\
out_valid``_state_ <= 1;\
out_data``_state_ <= out_data``_state_;\
out_valid``_overflow_ <= out_valid``_overflow_;\
out_data``_overflow_ <= out_data``_overflow_;\
end\
end else begin\
if (!out_ready && out_valid``_state_) begin\
out_valid``_state_ <= 1;\
out_data``_state_ <= out_data``_state_;\
out_valid``_overflow_ <= in_valid;\
out_data``_overflow_ <= in_data;\
end else begin\
out_valid``_state_ <= in_valid;\
out_data``_state_ <= in_data;\
out_valid``_overflow_ <= out_valid``_overflow_;\
out_data``_overflow_ <= out_data``_overflow_;\
end\
end\
end\ // always@ (posedge clk)
assign in_ready = !out_valid``_overflow_;\
assign out_data = out_data``_state_;\
assign out_valid = out_valid``_state_;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_2_V
`define SKY130_FD_SC_LS__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; template <typename T> inline void read(T &AKNOI) { T x = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } AKNOI = flag * x; } template <typename T> inline void cmin(T &x, T y) { if (y < x) x = y; } template <typename T> inline void cmax(T &x, T y) { if (x < y) x = y; } char s[MAXN], t[MAXN]; int n, m, k[MAXN], len[MAXN]; int tot, ch[MAXN][26], fail[MAXN], ed[MAXN], ff[MAXN]; int q[MAXN], head, tail; vector<int> mtch[MAXN]; void Insert(int id) { int p = 0, l = len[id] = strlen(t + 1); for (int i = 1; i <= l; ++i) { int x = t[i] - a ; if (!ch[p][x]) { ch[p][x] = ++tot; } p = ch[p][x]; } ed[p] = id; } void GetFail() { head = 1, tail = 0; for (int i = 0; i < 26; ++i) { if (ch[0][i]) { q[++tail] = ch[0][i]; } } while (head <= tail) { int u = q[head++]; for (int i = 0; i < 26; ++i) { if (ch[u][i]) { int v = ch[u][i]; fail[v] = ch[fail[u]][i]; ff[v] = (ed[fail[v]] ? fail[v] : ff[fail[v]]); q[++tail] = v; } else { ch[u][i] = ch[fail[u]][i]; } } } } void Run() { int p = 0; for (int i = 1; i <= n; ++i) { p = ch[p][s[i] - a ]; int u = (ed[p] ? p : ff[p]); for (; u; u = ff[u]) { mtch[ed[u]].push_back(i); } } } void init() { scanf( %s , s + 1); n = strlen(s + 1); read(m); for (int i = 1; i <= m; ++i) { read(k[i]); scanf( %s , t + 1); Insert(i); } GetFail(); } void solve() { Run(); for (int i = 1; i <= m; ++i) { if (mtch[i].size() < k[i]) { printf( -1 n ); } else { int ans = n + 1; for (int j = 0, sz = mtch[i].size(); j + k[i] - 1 < sz; ++j) { cmin(ans, mtch[i][j + k[i] - 1] - mtch[i][j]); } printf( %d n , ans + len[i]); } } } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int B = 27397, MOD = 1e9 + 7; const int B1 = 33941, MOD1 = 1e9 + 9; int n, q; struct Node { int nxt[11]; long long sum[11]; Node() { for (int i = 0; i < 10; ++i) nxt[i] = i; memset(sum, 0, sizeof sum); } }; class Tournament { private: int offset, lo, hi, x, y; int nxt_left[11], nxt_right[11]; long long new_sum[11]; vector<Node> tree; void merge(int node) { for (int i = 0; i < 10; ++i) tree[node].sum[i] = tree[2 * node].sum[i] + tree[2 * node + 1].sum[i]; } void propagate(int node) { if (node < offset) { for (int i = 0; i < 10; ++i) { nxt_left[i] = tree[node].nxt[tree[2 * node].nxt[i]]; nxt_right[i] = tree[node].nxt[tree[2 * node + 1].nxt[i]]; } for (int i = 0; i < 10; ++i) { tree[2 * node].nxt[i] = nxt_left[i]; tree[2 * node + 1].nxt[i] = nxt_right[i]; } } memset(new_sum, 0, sizeof new_sum); for (int i = 0; i < 10; ++i) new_sum[tree[node].nxt[i]] += tree[node].sum[i]; for (int i = 0; i < 10; ++i) { tree[node].sum[i] = new_sum[i]; tree[node].nxt[i] = i; } } void update(int node, int from, int to) { propagate(node); if (to <= lo || hi <= from) return; if (from >= lo && to <= hi) { tree[node].nxt[x] = y; propagate(node); return; } update(2 * node, from, (from + to) / 2); update(2 * node + 1, (from + to) / 2, to); merge(node); } long long query(int node, int from, int to) { propagate(node); if (to <= lo || hi <= from) return 0; if (from >= lo && to <= hi) { long long ret = 0; for (int i = 0; i < 10; ++i) ret += (long long)i * tree[node].sum[i]; return ret; } long long left = query(2 * node, from, (from + to) / 2); long long right = query(2 * node + 1, (from + to) / 2, to); return left + right; } public: Tournament(int n) { for (offset = 1; offset <= n; offset <<= 1) ; tree.resize(2 * offset); } void insert(int i, int val) { i += offset; int coef = 1; while (val > 0) { tree[i].sum[val % 10] += (long long)coef; coef *= 10; val /= 10; } for (i >>= 1; i > 0; i >>= 1) merge(i); } void update(int l, int r, int _x, int _y) { lo = l; hi = r; x = _x; y = _y; update(1, 0, offset); } long long query(int l, int r) { lo = l; hi = r; return query(1, 0, offset); } }; int main(void) { scanf( %d%d , &n, &q); Tournament T(n); for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); T.insert(i, x); } for (int i = 0; i < q; ++i) { int t; scanf( %d , &t); if (t == 1) { int l, r, x, y; scanf( %d%d%d%d , &l, &r, &x, &y); --l; if (x == y) continue; T.update(l, r, x, y); continue; } int l, r; scanf( %d%d , &l, &r); --l; printf( %lld n , T.query(l, r)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> ans(n); int a1, a2, a3; cout << ? 1 2 << endl; fflush(stdout); cin >> a1; cout << ? 1 3 << endl; fflush(stdout); cin >> a2; cout << ? 2 3 << endl; fflush(stdout); cin >> a3; int t = (a1 + a2 - a3) / 2; ans[0] = t; ans[2] = a2 - t; ans[1] = a3 - ans[2]; for (int i = 3; i < n; i++) { int now = 0; cout << ? 1 << i + 1 << endl; fflush(stdout); cin >> now; ans[i] = now - t; } cout << ! ; for (int i = 0; i < n; i++) { cout << ans[i] << ; } return 0; }
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/rainier/LUT6_2.v,v 1.4 2007/06/19 19:47:31 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.18)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 6-input Look-Up-Table with Two Outputs
// /___/ /\ Filename : LUT6_2.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 08/08/06 - Initial version.
// 06/04/07 - Change timescale form 100ps/10ps to 1ps/1ps.
// Add wire definition.
// 06/19/07 - Add LOC parameter (CR 441956).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
input I0, I1, I2, I3, I4, I5;
output O5, O6;
reg [63:0] init_reg = INIT;
reg [31:0] init_l, init_h;
reg O_l, O_h, tmp;
reg O5_o, O6_o;
wire I0_i, I1_i, I2_i, I3_i, I4_i, I5_i;
buf bo5 (O5, O5_o);
buf bo6 (O6, O6_o);
buf bi0 (I0_i, I0);
buf bi1 (I1_i, I1);
buf bi2 (I2_i, I2);
buf bi3 (I3_i, I3);
buf bi4 (I4_i, I4);
buf bi5 (I5_i, I5);
initial begin
init_l = init_reg[31:0];
init_h = init_reg[63:32];
end
always @(I5_i or O_l or O_h) begin
O5_o = O_l;
if (I5_i == 1)
O6_o = O_h;
else if (I5_i == 0)
O6_o = O_l;
else begin
if (O_h == 0 && O_l == 0)
O6_o = 1'b0;
else if (O_h == 1 && O_l == 1)
O6_o = 1'b1;
else
O6_o = 1'bx;
end
end
always @( I4_i or I3_i or I2_i or I1_i or I0_i ) begin
tmp = I0_i ^ I1_i ^ I2_i ^ I3_i ^ I4_i;
if ( tmp == 0 || tmp == 1) begin
O_l = init_l[{I4_i, I3_i, I2_i, I1_i, I0_i}];
O_h = init_h[{I4_i, I3_i, I2_i, I1_i, I0_i}];
end
else begin
O_l = lut4_mux4 (
{ lut6_mux8 ( init_l[31:24], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[23:16], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[15:8], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_l[7:0], {I2_i, I1_i, I0_i}) }, { I4_i, I3_i});
O_h = lut4_mux4 (
{ lut6_mux8 ( init_h[31:24], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[23:16], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[15:8], {I2_i, I1_i, I0_i}),
lut6_mux8 ( init_h[7:0], {I2_i, I1_i, I0_i}) }, { I4_i, I3_i});
end
end
specify
(I0 => O5) = (0:0:0, 0:0:0);
(I1 => O5) = (0:0:0, 0:0:0);
(I2 => O5) = (0:0:0, 0:0:0);
(I3 => O5) = (0:0:0, 0:0:0);
(I4 => O5) = (0:0:0, 0:0:0);
(I5 => O5) = (0:0:0, 0:0:0);
(I0 => O6) = (0:0:0, 0:0:0);
(I1 => O6) = (0:0:0, 0:0:0);
(I2 => O6) = (0:0:0, 0:0:0);
(I3 => O6) = (0:0:0, 0:0:0);
(I4 => O6) = (0:0:0, 0:0:0);
(I5 => O6) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
function lut4_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut4_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) )
lut4_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut4_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut4_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut4_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut4_mux4 = d[1];
else
lut4_mux4 = 1'bx;
end
endfunction
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int n, m, w, h; set<int> Set[2]; set<int>::iterator iter; priority_queue<int> qu[2]; int vis[2][200010], point[2][200010]; char s[10]; int main() { int i, j, k, l, r, p, a, b; long long ans; scanf( %d%d%d , &w, &h, &k); Set[0].insert(0); Set[0].insert(h); Set[1].insert(0); Set[1].insert(w); point[0][h] = 0; point[1][w] = 0; qu[0].push(h); qu[1].push(w); for (i = 1; i <= k; i++) { scanf( %s%d , s, &p); if (s[0] == H ) { iter = Set[0].lower_bound(p); r = *iter; l = point[0][r]; vis[0][r - l]++; qu[0].push(r - p); qu[0].push(p - l); point[0][r] = p; point[0][p] = l; Set[0].insert(p); } else { iter = Set[1].lower_bound(p); r = *iter; l = point[1][r]; vis[1][r - l]++; qu[1].push(r - p); qu[1].push(p - l); point[1][r] = p; point[1][p] = l; Set[1].insert(p); } while (true) { a = qu[0].top(); if (vis[0][a] == 0) break; vis[0][a]--; qu[0].pop(); } while (true) { b = qu[1].top(); if (vis[1][b] == 0) break; vis[1][b]--; qu[1].pop(); } ans = (long long)a * (long long)b; printf( %I64d n , ans); } }
|
// unsaved.v
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module unsaved (
input wire clk_clk, // clk.clk
input wire [4:0] pc_address, // pc.address
input wire pc_debugaccess, // .debugaccess
input wire pc_clken, // .clken
input wire pc_chipselect, // .chipselect
input wire pc_write, // .write
output wire [31:0] pc_readdata, // .readdata
input wire [31:0] pc_writedata, // .writedata
input wire [3:0] pc_byteenable, // .byteenable
input wire reset_reset, // reset.reset
input wire reset_reset_req // .reset_req
);
unsaved_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (pc_address), // s1.address
.debugaccess (pc_debugaccess), // .debugaccess
.clken (pc_clken), // .clken
.chipselect (pc_chipselect), // .chipselect
.write (pc_write), // .write
.readdata (pc_readdata), // .readdata
.writedata (pc_writedata), // .writedata
.byteenable (pc_byteenable), // .byteenable
.reset (reset_reset), // reset1.reset
.reset_req (reset_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
`define SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a, b, c; int main() { scanf( %d %d %d n , &a, &b, &c); if (a == b && c == 0) printf( YES n ); else if ((a != b && c == 0) || (a > b && c > 0) || (a < b && c < 0)) printf( NO n ); else { if ((b - a) % c == 0) printf( YES n ); else printf( NO n ); } return 0; }
|
// ----------------------------------------------------------------------
// HLS HDL: Verilog Netlister
// HLS Version: 2011a.126 Production Release
// HLS Date: Wed Aug 8 00:52:07 PDT 2012
//
// Generated by: fyq14@EEWS104A-002
// Generated date: Tue Mar 03 15:18:49 2015
// ----------------------------------------------------------------------
//
// ------------------------------------------------------------------
// Design Unit: dot_product_core
// ------------------------------------------------------------------
module dot_product_core (
clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
);
input clk;
input en;
input arst_n;
input [7:0] input_a_rsc_mgc_in_wire_d;
input [7:0] input_b_rsc_mgc_in_wire_d;
output [7:0] output_rsc_mgc_out_stdreg_d;
reg [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations
reg exit_MAC_lpi;
reg [7:0] acc_sva_1;
reg [2:0] i_1_sva_1;
wire [2:0] MAC_acc_itm;
wire [3:0] nl_MAC_acc_itm;
wire [7:0] acc_sva_2;
wire [8:0] nl_acc_sva_2;
wire [2:0] i_1_sva_2;
wire [3:0] nl_i_1_sva_2;
// Interconnect Declarations for Component Instantiations
assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
* input_b_rsc_mgc_in_wire_d);
assign acc_sva_2 = nl_acc_sva_2[7:0];
assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
assign i_1_sva_2 = nl_i_1_sva_2[2:0];
assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11;
assign MAC_acc_itm = nl_MAC_acc_itm[2:0];
always @(posedge clk or negedge arst_n) begin
if ( ~ arst_n ) begin
output_rsc_mgc_out_stdreg_d <= 8'b0;
acc_sva_1 <= 8'b0;
i_1_sva_1 <= 3'b0;
exit_MAC_lpi <= 1'b1;
end
else begin
if ( en ) begin
output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d},
MAC_acc_itm[2]);
acc_sva_1 <= acc_sva_2;
i_1_sva_1 <= i_1_sva_2;
exit_MAC_lpi <= ~ (MAC_acc_itm[2]);
end
end
end
function [7:0] signext_8_1;
input [0:0] vector;
begin
signext_8_1= {{7{vector[0]}}, vector};
end
endfunction
function [2:0] signext_3_1;
input [0:0] vector;
begin
signext_3_1= {{2{vector[0]}}, vector};
end
endfunction
function [7:0] MUX_v_8_2_2;
input [15:0] inputs;
input [0:0] sel;
reg [7:0] result;
begin
case (sel)
1'b0 : begin
result = inputs[15:8];
end
1'b1 : begin
result = inputs[7:0];
end
default : begin
result = inputs[15:8];
end
endcase
MUX_v_8_2_2 = result;
end
endfunction
function signed [7:0] conv_s2s_16_8 ;
input signed [15:0] vector ;
begin
conv_s2s_16_8 = vector[7:0];
end
endfunction
endmodule
// ------------------------------------------------------------------
// Design Unit: dot_product
// Generated from file(s):
// 3) //icnas3.cc.ic.ac.uk/fyq14/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
// ------------------------------------------------------------------
module dot_product (
input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
);
input [7:0] input_a_rsc_z;
input [7:0] input_b_rsc_z;
output [7:0] output_rsc_z;
input clk;
input en;
input arst_n;
// Interconnect Declarations
wire [7:0] input_a_rsc_mgc_in_wire_d;
wire [7:0] input_b_rsc_mgc_in_wire_d;
wire [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations for Component Instantiations
mgc_in_wire #(.rscid(1),
.width(8)) input_a_rsc_mgc_in_wire (
.d(input_a_rsc_mgc_in_wire_d),
.z(input_a_rsc_z)
);
mgc_in_wire #(.rscid(2),
.width(8)) input_b_rsc_mgc_in_wire (
.d(input_b_rsc_mgc_in_wire_d),
.z(input_b_rsc_z)
);
mgc_out_stdreg #(.rscid(3),
.width(8)) output_rsc_mgc_out_stdreg (
.d(output_rsc_mgc_out_stdreg_d),
.z(output_rsc_z)
);
dot_product_core dot_product_core_inst (
.clk(clk),
.en(en),
.arst_n(arst_n),
.input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
.input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
.output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n < 3) cout << -1; else for (int i = n; i > 0; --i) { cout << i << ; } return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 27443 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w513,
w128,
w385,
w16416,
w16801,
w6160,
w6159,
w33602,
w27443;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w16416 = w513 << 5;
assign w16801 = w385 + w16416;
assign w27443 = w33602 - w6159;
assign w33602 = w16801 << 1;
assign w385 = w513 - w128;
assign w512 = w1 << 9;
assign w513 = w1 + w512;
assign w6159 = w6160 - w1;
assign w6160 = w385 << 4;
assign o_data0 = w27443;
//multiplier_block area estimate = 9154.25268245589;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline bool smin(T &a, const T &b) { return b < a ? a = b, 1 : 0; } template <typename T> inline bool smax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } const long long N = 1e5 + 100, lg = 22; long long n, k, add[N], h[N]; vector<pair<long long, long long> > adj[N]; long long par[N][lg]; void dfs(long long v = 1, long long p = -1, long long dep = 0) { if (v != 1) { par[v][0] = p; for (long long i = 1; i < lg; i++) par[v][i] = par[par[v][i - 1]][i - 1]; } else { for (long long i = 0; i < lg; i++) par[v][i] = v; } h[v] = dep; for (auto u : adj[v]) if (u.first != p) dfs(u.first, v, dep + 1); } long long getPar(long long v, long long k) { for (long long i = lg - 1; i >= 0; i--) if (k >> i & 1) v = par[v][i]; return v; } long long lca(long long u, long long v) { if (h[u] > h[v]) swap(u, v); v = getPar(v, h[v] - h[u]); if (u == v) return v; for (long long i = lg - 1; i >= 0; i--) { if (par[u][i] != par[v][i]) u = par[u][i], v = par[v][i]; } return par[v][0]; } long long ans[N]; long long calc(long long v = 1, long long p = -1, long long want = -1) { long long res = add[v]; for (auto u : adj[v]) { if (u.first == p) continue; res += calc(u.first, v, u.second); } if (want != -1) ans[want] = res; return res; } int32_t main() { cin >> n; for (long long i = 0; i < n - 1; i++) { long long u, v; cin >> u >> v; adj[v].push_back({u, i}), adj[u].push_back({v, i}); } dfs(); cin >> k; while (k--) { long long u, v; cin >> u >> v; long long l = lca(u, v); add[u]++, add[v]++, add[l] -= 2; }; calc(); for (long long i = 0; i < n - 1; i++) cout << ans[i] << ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int a[100001]; stack<int> st; int main() { ios::sync_with_stdio(0); int n; cin >> n; long long int sum = 0; for (int i = 0; i < n; i++) cin >> a[i]; sum += a[0]; for (int i = 1; i < n; i++) sum += max(a[i] - a[i - 1], 0); cout << sum << n ; for (int i = 0; i < a[0]; i++) st.push(0); for (int i = 1; i < n; i++) { if (a[i] - a[i - 1] > 0) { for (int j = 0; j < a[i] - a[i - 1]; j++) st.push(i); } else if (st.size() != 0) { int num = abs(a[i] - a[i - 1]); for (int j = 0; j < num; j++) { int inde = st.top(); inde++; st.pop(); cout << inde << << i << n ; } } } for (int i = 0; i < a[n - 1]; i++) { if (st.size() != 0) { cout << st.top() + 1 << << n << n ; st.pop(); } } }
|
module PLLE2_BASE (/*AUTOARG*/
// Outputs
LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
CLKFBOUT,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
parameter BANDWIDTH = 0;
parameter CLKFBOUT_MULT = 0;
parameter CLKFBOUT_PHASE = 0;
parameter CLKIN1_PERIOD = 0;
parameter CLKOUT0_DIVIDE = 0;
parameter CLKOUT0_DUTY_CYCLE = 0;
parameter CLKOUT0_PHASE = 0;
parameter CLKOUT1_DIVIDE = 0;
parameter CLKOUT1_DUTY_CYCLE = 0;
parameter CLKOUT1_PHASE = 0;
parameter CLKOUT2_DIVIDE = 0;
parameter CLKOUT2_DUTY_CYCLE = 0;
parameter CLKOUT2_PHASE = 0;
parameter CLKOUT3_DIVIDE = 0;
parameter CLKOUT3_DUTY_CYCLE = 0;
parameter CLKOUT3_PHASE = 0;
parameter CLKOUT4_DIVIDE = 0;
parameter CLKOUT4_DUTY_CYCLE = 0;
parameter CLKOUT4_PHASE = 0;
parameter CLKOUT5_DIVIDE = 0;
parameter CLKOUT5_DUTY_CYCLE = 0;
parameter CLKOUT5_PHASE = 0;
parameter DIVCLK_DIVIDE = 0;
parameter REF_JITTER1 = 0;
parameter STARTUP_WAIT = 0;
parameter IOSTANDARD = 0;
//inputs
input CLKIN1;
input RST;
input PWRDWN;
input CLKFBIN;
//outputs
output LOCKED;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
//Not a correct model
assign CLKFBOUT=CLKIN1;
assign LOCKED=1'b0;
assign CLKOUT0=CLKIN1;
assign CLKOUT1=CLKIN1;
assign CLKOUT2=CLKIN1;
assign CLKOUT3=CLKIN1;
assign CLKOUT4=CLKIN1;
assign CLKOUT5=CLKIN1;
assign CLKFBOUT=CLKIN1;
endmodule // PLLE2_BASE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_TB_V
`define SKY130_FD_SC_LP__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long modpow(long long a, long long x) { long long tmp = x; long long val = a; long long ret = 1LL; while (tmp > 0) { if (tmp % 2 == 1) ret = ret * val % mod; val = val * val % mod; tmp /= 2; } return ret; } long long modinv(long long a) { return modpow(a, mod - 2); } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; vector<vector<long long>> G(1 << n, vector<long long>(n, 1)); for (int i = 0; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if (((i >> j) & 1) == 0) continue; for (int k = 0; k < n; k++) { G[i][k] = G[i][k] * a[j] % mod * modinv(a[j] + a[k]) % mod; } } } long long ans = 0LL; vector<long long> P(1 << n); for (int i = 1; i < (1 << n); i++) { long long cnt = __builtin_popcount(i); long long P_tmp = 1LL; for (int j = i; j > 0; j = ((j - 1) & i)) { if (j == i) continue; long long G_tmp0 = 1LL; for (int k = 0; k < n; k++) { if (((j >> k) & 1) == 1) continue; if (((i >> k) & 1) == 0) continue; G_tmp0 = (G_tmp0 * G[j][k]) % mod; } P_tmp = (P_tmp - P[j] * G_tmp0 % mod + mod) % mod; } long long G_tmp1 = 1LL; for (int k = 0; k < n; k++) { if (((i >> k) & 1) == 1) continue; G_tmp1 = (G_tmp1 * G[i][k]) % mod; } ans = (ans + cnt * P_tmp % mod * G_tmp1) % mod; P[i] = P_tmp; } cout << ans << n ; return 0; }
|
module control_div( clk , rst , start , MSB , z , INIT , SH , DEC , LDA , DONE, DV0 );
input clk;
input rst;
input start;
input MSB;
input z;
output reg INIT;
output reg DV0;
output reg SH;
output reg DEC;
output reg LDA;
output reg DONE;
parameter START = 3'b000;
parameter SHIFT_DEC = 3'b001;
parameter CHECK = 3'b010;
parameter ADD = 3'b011;
parameter LOAD = 3'b101; //agregado
parameter END1 = 3'b100;
reg [2:0] state;
initial begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
reg [3:0] count;
always @(posedge clk) begin
if (rst) begin
state = START;
end else begin
case(state)
START: begin
count=0;
if(start)
state = SHIFT_DEC;
else
state = START;
end
SHIFT_DEC:
state = CHECK;
CHECK:
if(z)
state = END1;
else begin
if (MSB==0)
state = ADD;
else
state = SHIFT_DEC;
end
ADD: state=LOAD;
LOAD:
if(z)
state = END1;
else
state = SHIFT_DEC;
END1:begin
count = count + 1;
state = (count>9) ? START : END1 ; // hace falta de 10 ciclos de reloj, para que lea el done y luego cargue el resultado
end
default: state = START;
endcase
end
end
always @(state) begin
case(state)
START:begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
SHIFT_DEC:begin
INIT=0;
DV0=DV0;
SH=1;
DEC=1;
LDA=0;
DONE=0;
end
CHECK:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
ADD:begin
INIT=0;
DV0=1; // primero suma
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
LOAD:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=1; // ahora carga el resultado
DONE=0;
end
END1:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=1;
end
default:begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
endcase
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.