text
stringlengths 59
71.4k
|
|---|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:38:23 05/10/2015
// Design Name:
// Module Name: sbox1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox1(
Bin,
BSout
);
input [6:1] Bin;
output reg [4:1] BSout;
wire [6:1] offset;
assign offset = {Bin[6], Bin[1], Bin[5 : 2]};
always @(offset)
begin
case (offset)
6'b000000: BSout <= 4'd14;
6'b000001: BSout <= 4'd4;
6'b000010: BSout <= 4'd13;
6'b000011: BSout <= 4'd1;
6'b000100: BSout <= 4'd2;
6'b000101: BSout <= 4'd15;
6'b000110: BSout <= 4'd11;
6'b000111: BSout <= 4'd8;
6'b001000: BSout <= 4'd3;
6'b001001: BSout <= 4'd10;
6'b001010: BSout <= 4'd6;
6'b001011: BSout <= 4'd12;
6'b001100: BSout <= 4'd5;
6'b001101: BSout <= 4'd9;
6'b001110: BSout <= 4'd0;
6'b001111: BSout <= 4'd7;
6'b010000: BSout <= 4'd0;
6'b010001: BSout <= 4'd15;
6'b010010: BSout <= 4'd7;
6'b010011: BSout <= 4'd4;
6'b010100: BSout <= 4'd14;
6'b010101: BSout <= 4'd2;
6'b010110: BSout <= 4'd13;
6'b010111: BSout <= 4'd1;
6'b011000: BSout <= 4'd10;
6'b011001: BSout <= 4'd6;
6'b011010: BSout <= 4'd12;
6'b011011: BSout <= 4'd11;
6'b011100: BSout <= 4'd9;
6'b011101: BSout <= 4'd5;
6'b011110: BSout <= 4'd3;
6'b011111: BSout <= 4'd8;
6'b100000: BSout <= 4'd4;
6'b100001: BSout <= 4'd1;
6'b100010: BSout <= 4'd14;
6'b100011: BSout <= 4'd8;
6'b100100: BSout <= 4'd13;
6'b100101: BSout <= 4'd6;
6'b100110: BSout <= 4'd2;
6'b100111: BSout <= 4'd11;
6'b101000: BSout <= 4'd15;
6'b101001: BSout <= 4'd12;
6'b101010: BSout <= 4'd9;
6'b101011: BSout <= 4'd7;
6'b101100: BSout <= 4'd3;
6'b101101: BSout <= 4'd10;
6'b101110: BSout <= 4'd5;
6'b101111: BSout <= 4'd0;
6'b110000: BSout <= 4'd15;
6'b110001: BSout <= 4'd12;
6'b110010: BSout <= 4'd8;
6'b110011: BSout <= 4'd2;
6'b110100: BSout <= 4'd4;
6'b110101: BSout <= 4'd9;
6'b110110: BSout <= 4'd1;
6'b110111: BSout <= 4'd7;
6'b111000: BSout <= 4'd5;
6'b111001: BSout <= 4'd11;
6'b111010: BSout <= 4'd3;
6'b111011: BSout <= 4'd14;
6'b111100: BSout <= 4'd10;
6'b111101: BSout <= 4'd0;
6'b111110: BSout <= 4'd6;
6'b111111: BSout <= 4'd13;
default: BSout <= 4'd0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int test_time, x = 0; cin >> test_time; for (int i = 0; i < test_time; ++i) { string temp; cin >> temp; for (int j = 0; j < temp.length(); ++j) { if (temp[j] == - ) { x--; break; } else if (temp[j] == + ) { x++; break; } } } cout << x; return 0; }
|
#include <bits/stdc++.h> using namespace std; void fastio() { cin.tie(nullptr); cin.sync_with_stdio(false); } using LL = long long; using LD = long double; const LL MOD = 1e9 + 7; const LL INF = LLONG_MAX; const LL N = 2e5 + 1; int main() { fastio(); LL n; cin >> n; vector<LL> a(n); for (auto &e : a) { cin >> e; } vector<LL> ans(n, 0); sort(a.begin(), a.end(), greater<LL>()); LL p = 0; for (LL i = 0; i < n; i += 2) { ans[i] = a[p++]; } for (LL i = 0; i < n; ++i) { if (ans[i] == 0) { ans[i] = a[p++]; } } cout << (n - 1) / 2 << n ; for (auto &e : ans) { cout << e << ; } cout << n ; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; vector<int> G[maxn], a, b; int n, m, flag; int col[maxn]; bool bfs(int s) { queue<int> p; p.push(s); col[s] = 1; while (!p.empty()) { int from = p.front(); p.pop(); int len = G[from].size(); for (int i = 0; i < len; ++i) { int v = G[from][i]; if (col[v] == -1) { p.push(v); col[v] = !col[from]; } if (col[from] == col[v]) return false; } } return true; } int main() { scanf( %d%d , &n, &m); a.clear(); b.clear(); for (int i = 0; i <= n; ++i) G[i].clear(); for (int i = 0; i < m; ++i) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } flag = 0; memset(col, -1, sizeof(col)); for (int i = 1; i <= n; i++) if (col[i] == -1 && !bfs(i)) { flag = true; break; } if (flag) { puts( -1 ); } else { for (int i = 1; i <= n; ++i) { if (G[i].size() == 0) col[i] = -1; if (col[i] == 0) { a.push_back(i); } else if (col[i] == 1) { b.push_back(i); } } int len = a.size(); printf( %d n , len); for (int i = 0; i < len; ++i) { if (i) printf( ); printf( %d , a[i]); } len = b.size(); printf( n%d n , len); for (int i = 0; i < len; ++i) { if (i) printf( ); printf( %d , b[i]); } puts( ); } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_pio_1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> const int N = 1e6 + 5; using namespace std; int n, k, a[N], cnt[N], Min = N; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; Min = min(Min, a[i]); cnt[a[i]]++; } for (int i = 1; i < N; i++) cnt[i] += cnt[i - 1]; for (int i = Min; i > k; i--) { bool ck = 0; int j; for (j = i; j < N; j += i) { if (cnt[j - 1] - cnt[j - i + k]) { ck = 1; break; } } if (j - i + k < N && cnt[N - 1] - cnt[j - i + k]) ck = 1; if (!ck) return cout << i, 0; } cout << min(Min, k) << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_BEHAVIORAL_PP_V
/**
* sleep_pargate_plv: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
// Module ports
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
// Local signals
wire vgnd ;
wire pwrgood_pp0_out_VIRTPWR;
// Name Output Other arguments
pulldown pulldown0 (vgnd );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_VIRTPWR, VPWR, VPWR, vgnd );
bufif0 bufif00 (VIRTPWR , pwrgood_pp0_out_VIRTPWR, SLEEP);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_BEHAVIORAL_PP_V
|
module DriveOutput (
input clk,
input store_strb,
input feedfwd_en,
input use_strobes,
input [9:0] start_proc,
input [9:0] end_proc,
input [4:0] Ldelay,
input [1:0] opMode, //0 = sample-by-sample, 1 = constant DAC, 2 = Pulse mean removal //
input signed [12:0] constDac_val,
//input signed [29:0] din,
input signed [24:0] din,
input signed [6:0] gain,
input DACclkPhase,
input signed [6:0] IIRtapWeight,
//input IIRbypass,
//output reg signed [12:0] dout = 13'd0,
//output reg DAC_en = 1'b0
(* IOB = "true" *) output reg signed [12:0] dout = 13'd0, //For the sake of Iverilog!!
(* IOB = "true" *) output reg DAC_en = 1'b0 //ditto !
//(* IOB = "true" *) output reg signed [12:0] dout_copy = 13'd0, //For the sake of Iverilog!!
//(* IOB = "true" *) output reg DAC_en_copy = 1'b0 //ditto !
);
//parameter offset_delay = 4'd8; //minimum latency 5 cycles with respect to store_strb in FF modules (2 from LUT & mult, 1 gain, 2 Ldelay)
parameter offset_delay = 4'd7; //with respect to store_strb at Ldelay entrance (5 from "loop' module, 2 from gain, 1 from RAM_strobes, -2 from internal)
//7 is to bring the latency down by one cycle - should be 5 from 'loop' + 2 from gain + 1 from P1_strobe (then minus 1 from the register on opgate)
// gain stage, delay, combi o/p block, o/p filtering, decimate and put out.
//reg signed [29:0] dinReg = 30'sd0;
//reg signed [24:0] dinReg = 25'sd0;
//reg signed [6:0] gainReg = 7'sd0;
(* shreg_extract = "no" *) reg signed [35:0] gain_mult = 36'sd0, gainMult_out = 36'sd0;
//reg signed [31:0] gain_mult = 32'sd0;//, gainMult_out = 32'sd0;
(* shreg_extract = "no" *) reg signed [12:0] amp_drive = 13'sd0;
//wire signed [12:0] amp_drive;
wire signed [12:0] amp_drive_del;
always @(posedge clk) begin
//dinReg <= din;
//gainReg <= gain;
//gain_mult <= dinReg * gainReg;
gain_mult <= din * gain;
gainMult_out <= gain_mult;
end
//ShiftReg #(32) latencyDelay (clk, gainMult_out[35:23], Ldelay, amp_drive_del);
ShiftReg #(32) latencyDelay (clk, gainMult_out[30:18], Ldelay, amp_drive_del);
//ShiftReg #(32) latencyDelay (clk, gain_mult[30:18], Ldelay, amp_drive_del);
wire storeStrbDel;
wire [5:0] strbDel;
assign strbDel = Ldelay + offset_delay;
//Delay the store strobe by required amount
StrbShifter #(64) StoreStrbDel (clk, store_strb, strbDel, storeStrbDel);
//Filter goes here ... umm, no just before DACs
//Form output gate
(* shreg_extract = "no" *) reg [9:0] opGate_ctr = 10'd0;
//wire [10:0] totalDelStart, totalDelEnd;
(* shreg_extract = "no" *) reg opGate = 1'b0;
//assign DACgate = offset_delay + Ldelay; //offset version of store strobe
//assign totalDelStart = offset_delay + Ldelay + start_proc;
//assign totalDelEnd = offset_delay + Ldelay + end_proc;
//sequential block for opGate
always @(posedge clk) begin
opGate_ctr <= (storeStrbDel) ? opGate_ctr + 1'b1 : 11'd0;
if (storeStrbDel) begin
//(* full_case, parallel_case *)
case (opGate_ctr)
//totalDelStart: opGate <= 1'b1;
//totalDelEnd: opGate <= 1'b0;
start_proc: opGate <= 1'b1;
end_proc: opGate <= 1'b0;
default: opGate <= opGate;
endcase
end else begin
opGate <= 1'b0;
end
end
//combinatorial block for opGate
/*always @(posedge clk) opGate_ctr <= (storeStrbDel) ? opGate_ctr + 1'b1 : 11'd0;
always @(*) begin
if (storeStrbDel) begin
(* full_case, parallel_case *)
case (opGate_ctr)
//totalDelStart: opGate <= 1'b1;
//totalDelEnd: opGate <= 1'b0;
start_proc: opGate = 1'b1;
end_proc: opGate = 1'b0;
//default: opGate = opGate;
endcase
end else opGate = 1'b0;
end*/
//Combi o/p block
reg feedfwd_en_a = 0, feedfwd_en_b = 0; //PIPELINE REGISTERS
reg signed [12:0] amp_drive_b = 13'sd0; //PIPELINE REGISTER
always @(posedge clk) begin
feedfwd_en_a <= feedfwd_en;
feedfwd_en_b <= feedfwd_en_a;
amp_drive_b <= amp_drive;
end
always @(*) begin
//if (~storeStrbDel) amp_drive = 13'd0; //FF_en condition not necessary - 09/10/14
//if (~storeStrbDel || ~feedfwd_en_b) amp_drive = 13'd0;
//if (~storeStrbDel || ~feedfwd_en) amp_drive = 13'd0;
//else if (opGate || ~use_strobes)
if (storeStrbDel && (opGate || ~use_strobes))
(* full_case, parallel_case *) //recoded 09/10/14
case (opMode) //Need to include saturation detection here, this will be evident from the filter output - could just look for overflows!
2'd0: amp_drive = amp_drive_del;
2'd1: amp_drive = constDac_val;
default: amp_drive = 13'd0;
endcase
else amp_drive = 13'd0;
end
// Filter here now - input is amp_drive
wire signed [12:0] amp_drive_AD, amp_drive_out;
antiDroopIIR #(16) antiDroopIIR_DAC(
.clk(clk),
.trig(store_strb),
//.din(amp_drive),
.din(amp_drive_b),
.tapWeight(IIRtapWeight),
.accClr_en(1'b1),
.oflowClr(),
.oflowDetect(),
.dout(amp_drive_AD)
);
//assign amp_drive_out = (~IIRbypass) ? amp_drive_b : amp_drive_AD;
assign amp_drive_out = amp_drive_AD;
//Decimate and put out
(* shreg_extract = "no" *) reg clk_tog = 1'b0; //1-bit toggle
(* shreg_extract = "no" *) reg storeStrbDel_a = 1'b0, storeStrbDel_b = 1'b0, storeStrbDel_c = 1'b0, storeStrbDel_d = 1'b0, storeStrbDel_e = 1'b0;
wire clearDAC;
wire output_en;
assign clearDAC = storeStrbDel_e & ~storeStrbDel_d; //DAC must be cleared at least one cycle after the storeStrDeb goes low to avoi doubloe pulsing the DAC clk
//assign output_en = (~IIRbypass) ? storeStrbDel_a : storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
assign output_en = storeStrbDel_c; // Compensate with the three cycle delay through the filter or delay of 1 without filter
always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
storeStrbDel_c <= storeStrbDel_b;
storeStrbDel_d <= storeStrbDel_c;
storeStrbDel_e <= storeStrbDel_d;
if (clearDAC && feedfwd_en_b) begin
//if (clearDAC && feedfwd_en) begin
//dout <= dout; //seems a bit dangerous to assume that the amp_drive will be cancelled at the correct time!
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b1;
//DAC_en_copy <= 1'b1;
clk_tog <= clk_tog;
//end else if (storeStrbDel && feedfwd_en_b) begin
//end else if (storeStrbDel && feedfwd_en) begin
end else if (output_en && feedfwd_en_b) begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
//DAC_en_copy <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive_out;
//dout_copy <= (clk_tog) ? dout : amp_drive_out;
end else begin
dout <= 13'd0;
//dout_copy <= 13'd0;
DAC_en <= 1'b0;
//DAC_en_copy <= 1'b0;
clk_tog <= 1'b0;
end
end
/*always @(posedge clk) begin
storeStrbDel_a <= storeStrbDel;
storeStrbDel_b <= storeStrbDel_a;
if (clearDAC) begin
dout <= dout;
DAC_en <= 1'b1;
clk_tog <= clk_tog;
end else if (~storeStrbDel) begin
dout <= 13'd0;
DAC_en <= 1'b0;
clk_tog <= 1'b0;
end else begin
clk_tog <= ~clk_tog;
DAC_en <= clk_tog ^ DACclkPhase;
dout <= (clk_tog) ? dout : amp_drive;
end
end*/
endmodule
|
#include <bits/stdc++.h> int32_t gcd(int32_t a, int32_t b) { if (b == 0) return a; return gcd(b, a % b); } int32_t mpf(int32_t n, std::vector<int32_t>& primes) { for (int32_t i = 0; i < primes.size(); i++) if (n % primes[i] == 0) return primes[i]; return 1; } int main() { int32_t num_tests; std::cin >> num_tests; for (int32_t t = 0; t < num_tests; t++) { int32_t n; std::cin >> n; int32_t n2 = n; std::vector<int32_t> primes; std::map<int32_t, int32_t> powers; for (int32_t i = 2; i * i <= n2; i++) if (n2 % i == 0) { primes.push_back(i); while (n2 % i == 0) { powers[i]++; n2 /= i; } } if (n2 != 1) { primes.push_back(n2); powers[n2]++; } std::map<int32_t, std::vector<int32_t> > mpf2; for (int32_t i = 1; i * i <= n; i++) { if (n % i == 0) { mpf2[mpf(i, primes)].push_back(i); if (i * i != n) mpf2[mpf(n / i, primes)].push_back(n / i); } } mpf2.erase(1); std::vector<int32_t> answer; std::unordered_set<int32_t> used; for (int32_t i = 0; i < primes.size(); i++) { int32_t next = primes.size() != 1 ? primes[i] * primes[(i + 1) % primes.size()] : -1; for (int32_t j = 0; j < mpf2[primes[i]].size(); j++) if (mpf2[primes[i]][j] != next && used.find(mpf2[primes[i]][j]) == used.end()) { used.insert(mpf2[primes[i]][j]); answer.push_back(mpf2[primes[i]][j]); } if (primes.size() != 1 && used.find(next) == used.end()) { answer.push_back(next); used.insert(next); } } for (int32_t j = 0; j < answer.size(); j++) std::cout << answer[j] << ; std::cout << n ; int32_t actions = 0; for (int32_t j = 0; j < answer.size(); j++) { if (gcd(answer[j], answer[(j + 1) % answer.size()]) == 1) actions++; } std::cout << actions << n ; } return 0; }
|
`include "elink_constants.vh"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, rx_active, erx_nreset, erx_io_nreset,
// Inputs
sys_nreset, soft_reset, tx_active, sys_clk, rx_clkin
);
//Frequency Settings (Mhz)
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; // 270;
parameter PLL_VCO_MULT = 4; // RX
parameter TARGET = `CFG_TARGET; // "XILINX", "ALTERA" etc
parameter PLATFORM = `CFG_PLATFORM;
//Override reset counter size for simulation
`ifdef TARGET_SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000 / FREQ_RXCLK; //? Why is the period needed here?
localparam integer IREF_DIVIDE = PLL_VCO_MULT * FREQ_RXCLK / FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
//Input clock, reset, config interface
input sys_nreset; // active low system reset (hw)
input soft_reset; // rx enable signal (sw)
input tx_active; // tx active input
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Reset
output rx_active; // rx active
output erx_nreset; // reset for rx core logic
output erx_io_nreset; // io reset (synced to high speed clock)
//############
//# WIRES
//############
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk;
//pll outputs
wire rx_lclk_pll;
wire rx_lclk_div4_pll;
wire idelay_ref_clk_pll;
//PLL
wire rx_lclk_fb;
wire rx_nreset_in;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
wire pll_locked_sync;
reg [2:0] reset_state;
wire pll_reset;
reg rx_nreset;
wire pll_locked;
//Reset
assign rx_nreset_in = sys_nreset & tx_active;
//wrap around counter that generates a 1 cycle heartbeat
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
`define RX_RESET_ALL 3'b000
`define RX_START_PLL 3'b001
`define RX_ACTIVE 3'b010
//Reset sequence state machine
always @ (posedge sys_clk or negedge rx_nreset_in)
if(!rx_nreset_in)
reset_state[2:0] <= `RX_RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RX_RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `RX_START_PLL;
`RX_START_PLL :
if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `RX_ACTIVE;
`RX_ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RX_RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0])
assign pll_reset = (reset_state[2:0]==`RX_RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RX_RESET_ALL);
//Reset for RX (pipeline to improve timing)
always @ (posedge sys_clk)
rx_nreset <= ~(reset_state[2:0] != `RX_ACTIVE);
//active indicator
assign rx_active = (reset_state[2:0] == `RX_ACTIVE);
//#############################
//#RESET SYNCING
//#############################
oh_rsync rsync_io (// Outputs
.nrst_out (erx_io_nreset),
// Inputs
.clk (rx_lclk),
.nrst_in (rx_nreset)
);
oh_rsync rsync_core (// Outputs
.nrst_out (erx_nreset),
// Inputs
.clk (rx_lclk_div4),
.nrst_in (rx_nreset)
);
generate
if(TARGET=="XILINX")
begin
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb),
.CLKFBOUT(rx_lclk_fb),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),//??
.DO(), //??
.LOCKED(pll_locked)
);
//Clock network
BUFG i_lclk_bufg (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG i_lclk_div4_bufg (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //(300Mhz/4)
BUFG i_idelay_bufg (.I(idelay_ref_clk_pll),.O(idelay_ref_clk));//idelay ctrl clock
//two clock synchronizer for lock signal
oh_dsync dsync (.dout (pll_locked_sync),
.clk (sys_clk),
.nreset (1'b1),
.din (pll_locked)
);
//###########################
// Idelay controller
//###########################
//generate
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
`define IDELAYCTRL_WONT_SYNTHESIZE
`ifdef IDELAYCTRL_WONT_SYNTHESIZE
assign idelay_ready = 'b1;
`else
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL
#(
.SIM_DEVICE("ULTRASCALE_PLUS_ES2")
) idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset)
);
`endif
end // block: ultrascale
else // PLATFORM="ZYNQ"
begin: zynq
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
end // block: zynq
//endgenerate
end // if (TARGET=="XILINX")
endgenerate
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrtp (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_PP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_maca_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_maca_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa, rclk,
scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_out_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_2_V
`define SKY130_FD_SC_LS__O32A_2_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32a_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_2_V
|
#include <bits/stdc++.h> using namespace std; const int dir[4][2] = {1, 0, 0, 1, -1, 0, 0, -1}; const int N = 1e6 + 10; const int mod = 1e9 + 7; const double pi = acos(-1); const double eps = 1e-8; const long long INF = 2e10; template <class T> void _print(T arg) { cout << arg << ; } template <class... Args> void log(Args... args) { int arr[] = {(_print(args), 0)...}; cout << endl; } long long a[N], b[N]; int n, m, k; int main() { ios::sync_with_stdio(0); cin >> n >> k; for (int i = 0; i <= n; ++i) { cin >> a[i]; b[i] = a[i]; } for (int i = 0; i < n; ++i) { a[i + 1] += a[i] / 2; a[i] %= 2; } int pos; for (int i = 0; i <= n; ++i) { if (a[i]) { pos = i; break; } } int res = 0; long long tmp = 0; for (int i = n; i >= 0; --i) { tmp = tmp * 2 + a[i]; if (abs(tmp) > INF) break; if (i <= pos) { long long x = abs(tmp - b[i]); if (i == n & x == 0) continue; res += (x <= k); } } cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char s[55], t[55], i = 0, j = 0; scanf( %s , s); scanf( %s , t); while (t[i] != 0 ) { if (t[i] == s[j]) j++; i++; if (j >= strlen(s)) break; } cout << j + 1; return 0; }
|
#include <bits/stdc++.h> using namespace std; int pot(int x, int y) { if (y == 0) { return 1; } else { return x * pot(x, y - 1); } } int bin(int x, int y) { if ((x == 0 && y != 0) || (y == 0 && x != 0)) { return 1; } else { return bin(x, y - 1) + bin(x - 1, y); } } void strlwr(string& s) { for (int i = 0; (unsigned)i < s.size(); i++) { if (s[i] >= A && s[i] <= Z ) { s[i] += 32; } } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int a[26] = {}; int n; string s; cin >> s; n = s.size(); for (int i = 0; i < n; i++) { a[s[i] - a ]++; } int k = 25; for (int i = 0; i < n; i++) { while (a[k] == 0 && k > 0) { k--; } if (s[i] - a < k) { a[s[i] - a ]--; } if (s[i] - a == k) { a[s[i] - a ]--; cout << s[i]; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; ifstream in( in.txt ); ofstream out( out.txt ); long long a[1000006], b[1000006]; long long fortza(long long n, long long put) { if (!put) return 1; if (put == 1) return n; if (put & 1) return (fortza((n * n) % 998244353, put / 2) * n) % 998244353; return fortza((n * n) % 998244353, put / 2) % 998244353; } int main() { long long n, k, i, j, x; cin >> n; for (i = 1; i <= n; ++i) { cin >> k; for (j = 1; j <= k; ++j) { cin >> x; b[x] = (b[x] + fortza((k * n) % 998244353, 998244353 - 2)) % 998244353; ++a[x]; } } n = fortza(n, 998244353 - 2); for (i = 1, x = 0; i <= 1000006 - 6; ++i) x = (x + (a[i] * ((n * b[i]) % 998244353)) % 998244353) % 998244353; cout << x; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2000000005; const long long INFLL = 1000000000000000009; const long long MOD = 1000000007; long long W[1005][1005], N, M, K; int main() { for (int i = (1); i <= (1000); i++) W[i][0] = 1; for (int j = (1); j <= (1000); j++) { long long s = 0; for (int i = (3); i <= (1000); i++) { s = (s + W[i - 2][j - 1]) % MOD; W[i][j] = (W[i - 1][j] + s) % MOD; } } cin >> N >> M >> K; cout << (W[N][K] * W[M][K]) % MOD; }
|
module AND(in1,in2,out);//and operator
input [31:0] in1;
input [31:0] in2;
output [31:0] out;
and A0(out[0],in1[0],in2[0]);
and A1(out[1],in1[1],in2[1]);
and A2(out[2],in1[2],in2[2]);
and A3(out[3],in1[3],in2[3]);
and A4(out[4],in1[4],in2[4]);
and A5(out[5],in1[5],in2[5]);
and A6(out[6],in1[6],in2[6]);
and A7(out[7],in1[7],in2[7]);
and A8(out[8],in1[8],in2[8]);
and A9(out[9],in1[9],in2[9]);
and A10(out[10],in1[10],in2[10]);
and A11(out[11],in1[11],in2[11]);
and A12(out[12],in1[12],in2[12]);
and A13(out[13],in1[13],in2[13]);
and A14(out[14],in1[14],in2[14]);
and A15(out[15],in1[15],in2[15]);
and A16(out[16],in1[16],in2[16]);
and A17(out[17],in1[17],in2[17]);
and A18(out[18],in1[18],in2[18]);
and A19(out[19],in1[19],in2[19]);
and A20(out[20],in1[20],in2[20]);
and A21(out[21],in1[21],in2[21]);
and A22(out[22],in1[22],in2[22]);
and A23(out[23],in1[23],in2[23]);
and A24(out[24],in1[24],in2[24]);
and A25(out[25],in1[25],in2[25]);
and A26(out[26],in1[26],in2[26]);
and A27(out[27],in1[27],in2[27]);
and A28(out[28],in1[28],in2[28]);
and A29(out[29],in1[29],in2[29]);
and A30(out[30],in1[30],in2[30]);
and A31(out[31],in1[31],in2[31]);
endmodule
module OR(in1,in2,out);//or operation
input [31:0] in1;
input [31:0] in2;
output [31:0] out;
or o0(out[0],in1[0],in2[0]);
or o1(out[1],in1[1],in2[1]);
or o2(out[2],in1[2],in2[2]);
or o3(out[3],in1[3],in2[3]);
or o4(out[4],in1[4],in2[4]);
or o5(out[5],in1[5],in2[5]);
or o6(out[6],in1[6],in2[6]);
or o7(out[7],in1[7],in2[7]);
or o8(out[8],in1[8],in2[8]);
or o9(out[9],in1[9],in2[9]);
or o10(out[10],in1[10],in2[10]);
or o11(out[11],in1[11],in2[11]);
or o12(out[12],in1[12],in2[12]);
or o13(out[13],in1[13],in2[13]);
or o14(out[14],in1[14],in2[14]);
or o15(out[15],in1[15],in2[15]);
or o16(out[16],in1[16],in2[16]);
or o17(out[17],in1[17],in2[17]);
or o18(out[18],in1[18],in2[18]);
or o19(out[19],in1[19],in2[19]);
or o20(out[20],in1[20],in2[20]);
or o21(out[21],in1[21],in2[21]);
or o22(out[22],in1[22],in2[22]);
or o23(out[23],in1[23],in2[23]);
or o24(out[24],in1[24],in2[24]);
or o25(out[25],in1[25],in2[25]);
or o26(out[26],in1[26],in2[26]);
or o27(out[27],in1[27],in2[27]);
or o28(out[28],in1[28],in2[28]);
or o29(out[29],in1[29],in2[29]);
or o30(out[30],in1[30],in2[30]);
or o31(out[31],in1[31],in2[31]);
endmodule
|
// file: dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____10.000______0.000______50.0_____2200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "dcm,clk_wiz_v3_6,{component_name=dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module dcm
(// Clock in ports
input CLK_IN,
// Clock out ports
output CLK_OUT
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
//wire locked_int;
//wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (10.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (),
.STATUS (),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, plen; char p[200], ar[200]; char res[200]; int preone[200]; bool pos, found; bool is_start(int ind) { if (plen + ind > n) return false; for (int l = 0; l < plen; l++) if (p[l] != res[l + ind]) return false; return true; } bool back(int ind) { if (ind < 0) { return true; } if (res[ind] != -1) { if (ar[ind] == 0 && is_start(ind)) return false; return back(ind - 1); } for (int i = 0; i < k; i++) { res[ind] = a + i; if (!is_start(ind)) if (back(ind - 1)) return true; } return false; } int main() { cin >> n >> k; cin >> p; cin >> ar; plen = strlen(p); for (int i = n - plen + 1; i < n; i++) { ar[i] = 0 ; } memset(res, -1, sizeof(res)); pos = true; for (int i = 0; i < n && pos; i++) { if (ar[i] == 1 ) { for (int j = 0; j < plen && pos; j++) { if (res[i + j] != -1 && res[i + j] != p[j]) pos = false; else res[i + j] = p[j]; } } } if (pos && back(n)) { for (int i = 0; i < n; i++) cout << res[i]; } else cout << No solution ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } template <class T> inline T lcm(T a, T b) { a = abs(a); b = abs(b); return (a / gcd(a, b)) * b; } template <class T, class X> inline bool getbit(T a, X i) { T t = 1; return ((a & (t << i)) > 0); } template <class T, class X> inline T setbit(T a, X i) { T t = 1; return (a | (t << i)); } template <class T, class X> inline T resetbit(T a, X i) { T t = 1; return (a & (~(t << i))); } inline long long power(long long a, long long b) { long long multiply = 1; for (int i = (0); i < (b); i++) { multiply *= a; } return multiply; } vector<int> v[102]; int main() { int n, m, x; int first = 0, second = 0; cin >> n; for (int i = (0); i < (n); i++) { cin >> m; for (int j = (0); j < (m); j++) { cin >> x; v[i].push_back(x); } } vector<int> rest; for (int i = (0); i < (n); i++) { if (v[i].size() % 2 == 0) { for (int j = (0); j < (v[i].size() / 2); j++) first += v[i][j]; for (int j = (v[i].size() / 2); j < (v[i].size()); j++) second += v[i][j]; } else { for (int j = (0); j < (v[i].size() / 2); j++) first += v[i][j]; for (int j = (v[i].size() / 2 + 1); j < (v[i].size()); j++) second += v[i][j]; } } for (int j = (0); j < (n); j++) { if (v[j].size() % 2 == 0) continue; rest.push_back(v[j][v[j].size() / 2]); } sort(rest.begin(), rest.end(), greater<int>()); for (int j = (0); j < (rest.size()); j++) { if (j % 2 == 0) first += rest[j]; else second += rest[j]; } cout << first << << second << endl; return 0; }
|
/*
* DSI Shield
* Copyright (C) 2013-2014 twl <>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* video_mixer.v - asynchronous video overlay. Overlays framebuffer
image over HDMI input, outputs data for the DSI core. Work in progress. */
`timescale 1ns/1ps
module video_mixer
(
input clk_sys_i,
input clk_dvi_i,
input rst_n_i,
output fb_almost_full_o,
input fb_wr_i,
input [47:0] fb_pixel_i,
input fb_vsync_i,
output fb_next_frame_o,
input dvi_de_i,
input dvi_hsync_i,
input dvi_vsync_i,
input [47:0] dvi_pixel_i,
input dvi_link_up_i,
input dvi_valid_i,
input dsif_almost_full_i,
output dsif_wr_o,
output [47:0] dsif_pix_o,
output reg dsif_vsync_o,
input dsif_next_frame_i,
output [7:0] mixer_ctl_o,
input [7:0] mixer_ctl_i
);
`define DVI_WAIT_VBLANK 0
`define DVI_WAIT_LINK 1
`define DVI_WAIT_ACTIVE 2
`define DVI_ACTIVE 3
reg [2:0] dvi_state;
reg dvi_visible_start;
reg dvi_vsync_d, dvi_frame_p;
reg dvi_fifo_mask;
wire rst_n_dvi = 1;
always@(posedge clk_dvi_i)
begin
if (!rst_n_dvi || !dvi_link_up_i) begin
dvi_state <= `DVI_WAIT_LINK;
dvi_visible_start <= 0;
dvi_vsync_d <= 0;
dvi_frame_p <= 0;
dvi_fifo_mask <= 0;
end else begin
dvi_vsync_d <= dvi_vsync_i;
case (dvi_state)
`DVI_WAIT_LINK:
begin
dvi_frame_p <= 0;
dvi_state<=`DVI_WAIT_VBLANK;
end
`DVI_WAIT_VBLANK:
begin
// vsync going low
if(!dvi_de_i && !dvi_vsync_i && dvi_vsync_d)
begin
dvi_fifo_mask <=1;
dvi_frame_p <= 1;
dvi_state <= `DVI_WAIT_ACTIVE;
end else
dvi_frame_p <= 0;
end // case: `DVI_WAIT_VBLANK
`DVI_WAIT_ACTIVE:
if(dvi_de_i)
dvi_state <= `DVI_ACTIVE;
`DVI_ACTIVE:
begin
if( dvi_vsync_i && !dvi_de_i )
dvi_state <= `DVI_WAIT_VBLANK;
end
endcase // case (dvi_state)
end
end
wire dvi_rd, dvi_empty;
wire [47:0] dvi_pixel, fb_pixel;
wire overlay_enable, fbuf_purge;
generic_async_fifo
#(
.g_size(512),
.g_data_width(48),
.g_almost_empty_threshold(10),
.g_almost_full_threshold(510)
)
U_DVI_ElasticBuffer
(
.rst_n_i(dvi_link_up_i & rst_n_i & overlay_enable & ~dvi_vsync_i),
.clk_wr_i(clk_dvi_i),
.clk_rd_i(clk_sys_i),
.wr_full_o(wr_full),
.d_i(dvi_pixel_i),
.we_i(dvi_valid_i & dvi_fifo_mask),
.rd_i(dvi_rd),
.rd_empty_o(dvi_empty),
.q_o(dvi_pixel)
);
generic_sync_fifo
#(
.g_size(128),
.g_data_width(48),
.g_almost_empty_threshold(1),
.g_almost_full_threshold(100),
.g_with_almost_full(1)
)
U_FB_ElasticBuffer
(
.rst_n_i(rst_n_i & ~fbuf_purge),
.clk_i(clk_sys_i),
.almost_full_o(fb_almost_full_ebuf),
.d_i(fb_pixel_i),
.we_i(fb_wr_i),
.rd_i(dvi_rd & ~dsif_almost_full_i),
.empty_o(),
.q_o(fb_pixel)
);
`define ST_IDLE 0
`define ST_WAIT_DVI 1
`define ST_PUSH 2
`define ST_WAIT_ACTIVE 3
`define ST_PREFILL 4
reg [2:0] vid_state;
reg [2:0] dvi_frame_p_sync;
wire dvi_frame_p_sys;
always@(posedge clk_sys_i)
dvi_frame_p_sync <= { dvi_frame_p_sync[1:0], dvi_frame_p };
assign dvi_frame_p_sys = dvi_frame_p_sync[1] & ~dvi_frame_p_sync[2];
reg [10:0] count;
reg dsif_wr_reg;
always@(posedge clk_sys_i) begin
if(!rst_n_i || !overlay_enable) begin
vid_state <= `ST_IDLE;
dsif_vsync_o <= 1;
end else begin
case (vid_state)
`ST_IDLE: if(dsif_next_frame_i) begin
vid_state <= `ST_WAIT_DVI;
dsif_vsync_o <= 0;
end
`ST_WAIT_DVI:
if(dvi_frame_p_sys) begin
vid_state <= `ST_WAIT_ACTIVE;
dsif_vsync_o <= 1;
count <= 0;
end
`ST_WAIT_ACTIVE:
if(!dsif_next_frame_i)
begin
dsif_vsync_o <= 0;
vid_state <= `ST_PUSH;
end
`ST_PUSH:
begin
dsif_vsync_o <= 0;
if(dsif_next_frame_i)
vid_state <= `ST_WAIT_DVI;
end
endcase // case (vid_state)
end // else: !if(!rst_n_i || !r_enable)
end // always@ (posedge clk_sys_i)
reg gb_even;
reg [23:0] dsif_pix_hi;
reg dsif_wr = 0;
reg [4:0] rst_dly;
always@(posedge clk_sys_i)
if(!rst_n_i)
rst_dly <= 10;
else if (rst_dly)
rst_dly <= rst_dly -1;
assign dvi_rd = (!dvi_empty) && (vid_state != `ST_IDLE) && (vid_state != `ST_WAIT_DVI);
reg dvi_rd_d0;
always@(posedge clk_sys_i)
if(!rst_n_i)
dvi_rd_d0 <= 0;
else
dvi_rd_d0 <= dvi_rd;
reg [47:0] dsif_pix_reg;
// color key
always@(posedge clk_sys_i)
begin
// no color key for the moment
// if(fb_pixel[47:24] == 'h0000f8)
dsif_pix_reg [47:24] <= dvi_pixel[47:24];
// else
// dsif_pix_reg [47:24] <= fb_pixel[47:24];
// if(fb_pixel[23:0] == 'h0000f8)
dsif_pix_reg [23:0] <= dvi_pixel[23:0];
// else
// dsif_pix_reg [23:0] <= fb_pixel[23:0];
dsif_wr_reg <= dvi_rd_d0;
end
assign dsif_pix_o = overlay_enable ? dsif_pix_reg : fb_pixel_i;
assign dsif_wr_o = overlay_enable ? dsif_wr_reg : fb_wr_i;
assign fb_next_frame_o = overlay_enable ? (vid_state == `ST_WAIT_DVI) : dsif_next_frame_i;
assign fb_almost_full_o = overlay_enable ? fb_almost_full_ebuf : dsif_almost_full_i;
assign overlay_enable = mixer_ctl_i[0];
assign fbuf_purge = mixer_ctl_i[1];
assign mixer_ctl_o[0] = dvi_link_up_i;
assign mixer_ctl_o[1] = dvi_vsync_i;
endmodule // video_mixer
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_arb_mux_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_arb_mux_4.lxt");
$dumpvars(0, test_axis_arb_mux_4);
end
axis_arb_mux_4 #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module dspengine_16to8
#(parameter BASE = 0,
parameter BUF_SIZE = 9)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
output access_we,
output access_stb,
input access_ok,
output access_done,
output access_skip_read,
output [BUF_SIZE-1:0] access_adr,
input [BUF_SIZE-1:0] access_len,
output [35:0] access_dat_o,
input [35:0] access_dat_i
);
wire convert;
setting_reg #(.my_addr(BASE),.width(1)) sr_16to8
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(convert),.changed());
reg [2:0] dsp_state;
localparam DSP_IDLE = 0;
localparam DSP_PARSE_HEADER = 1;
localparam DSP_CONVERT = 2;
localparam DSP_CONVERT_DRAIN_PIPE = 3;
localparam DSP_READ_TRAILER = 4;
localparam DSP_WRITE_TRAILER = 5;
localparam DSP_WRITE_HEADER = 6;
localparam DSP_DONE = 7;
// Parse VITA header
wire is_if_data = (access_dat_i[31:29] == 3'b000);
wire has_streamid = access_dat_i[28];
wire has_classid = access_dat_i[27];
wire has_trailer = access_dat_i[26];
// 25:24 reserved, aka SOB/EOB
wire has_secs = |access_dat_i[23:22];
wire has_tics = |access_dat_i[21:20];
wire [3:0] hdr_length = 1 + has_streamid + has_classid + has_classid + has_secs + has_tics + has_tics;
wire [35:0] prod_i, prod_q;
wire [15:0] scaled_i, scaled_q;
wire [7:0] i8, q8;
reg [7:0] i8_reg, q8_reg;
wire stb_read, stb_clip, val_read, val_clip;
wire stb_out, stb_reg;
reg even;
reg [BUF_SIZE-1:0] read_adr, write_adr;
reg has_trailer_reg;
wire last = (read_adr + 1) == (access_len - has_trailer_reg);
wire last_o, even_o;
wire stb_write = stb_out & (even_o | last_o);
wire send_to_pipe = ~stb_write & (dsp_state == DSP_CONVERT);
reg [31:0] new_header, new_trailer, trailer_mask;
reg [15:0] length;
reg wait_for_trailer;
always @(posedge clk)
if(reset | clear)
dsp_state <= DSP_IDLE;
else
case(dsp_state)
DSP_IDLE :
begin
read_adr <= 0;
write_adr <= 0;
even <= 0;
if(access_ok)
dsp_state <= DSP_PARSE_HEADER;
end
DSP_PARSE_HEADER :
begin
has_trailer_reg <= has_trailer;
new_header[31:16] <= access_dat_i[31:16];
new_header[15:0] <= access_len;
length <= access_len;
if(is_if_data & convert)
begin
read_adr <= hdr_length;
write_adr <= hdr_length;
dsp_state <= DSP_CONVERT;
end
else
dsp_state <= DSP_WRITE_HEADER;
end
DSP_CONVERT:
begin
new_header[26] <= 1'b1; // all converted packets have a trailer
if(stb_write)
write_adr <= write_adr + 1;
else if(stb_read) // should always be 1 if we are here
begin
read_adr <= read_adr + 1;
even <= ~even;
if(last)
begin
dsp_state <= DSP_CONVERT_DRAIN_PIPE;
if(~even)
trailer_mask <= 32'h00400400;
else
trailer_mask <= 32'h00400000;
end
end
end
DSP_CONVERT_DRAIN_PIPE :
if(stb_write)
begin
write_adr <= write_adr + 1;
if(last_o)
if(has_trailer_reg)
begin
dsp_state <= DSP_READ_TRAILER;
wait_for_trailer <= 0;
end
else
begin
dsp_state <= DSP_WRITE_TRAILER;
new_trailer <= trailer_mask;
end
end
DSP_READ_TRAILER :
begin
wait_for_trailer <= 1;
if(wait_for_trailer)
dsp_state <= DSP_WRITE_TRAILER;
new_trailer <= access_dat_i[31:0] | trailer_mask;
end
DSP_WRITE_TRAILER :
begin
dsp_state <= DSP_WRITE_HEADER;
write_adr <= 0;
new_header[15:0] <= write_adr + 1;
end
DSP_WRITE_HEADER :
dsp_state <= DSP_DONE;
DSP_DONE :
begin
read_adr <= 0;
write_adr <= 0;
dsp_state <= DSP_IDLE;
end
endcase // case (dsp_state)
assign access_skip_read = 0;
assign access_done = (dsp_state == DSP_DONE);
assign access_stb = 1;
assign access_we = (dsp_state == DSP_WRITE_HEADER) |
(dsp_state == DSP_WRITE_TRAILER) |
stb_write;
assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } :
(dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
(last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } :
{4'h0, i8_reg, q8_reg, i8, q8 };
assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr;
// DSP Pipeline
wire [15:0] i16 = access_dat_i[31:16];
wire [15:0] q16 = access_dat_i[15:0];
pipectrl #(.STAGES(2), .TAGWIDTH(2)) pipectrl
(.clk(clk), .reset(reset),
.src_rdy_i(send_to_pipe), .dst_rdy_o(), // dst_rdy_o will always be 1 since dst_rdy_i is 1, below
.src_rdy_o(stb_out), .dst_rdy_i(1), // always accept output of chain
.strobes({stb_clip,stb_read}), .valids({val_clip,val_read}),
.tag_i({last,even}), .tag_o({last_o,even_o}));
always @(posedge clk)
if(stb_out & ~even_o)
{i8_reg,q8_reg} <= {i8,q8};
clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_i
(.clk(clk), .in(i16), .out(i8), .strobe_in(stb_clip), .strobe_out());
clip_reg #(.bits_in(16),.bits_out(8),.STROBED(1)) clip_q
(.clk(clk), .in(q16), .out(q8), .strobe_in(stb_clip), .strobe_out());
endmodule // dspengine_16to8
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T Min(T x, T y) { return x < y ? x : y; } template <class T> inline T Max(T x, T y) { return x > y ? x : y; } bool MOP1; long long T, n, res; long long head[(105)], nxt[(105)], to[(105)], line; void add(long long x, long long y) { nxt[++line] = head[x], to[line] = y, head[x] = line; } struct node { string name; long long lei, X, Y; long long tot, mx; long long sz, bo, sp; long long x() { if (lei == 2) return sz ? tot + bo * 2 + (sz - 1) * sp : 0; if (lei == 3) return sz ? mx + bo * 2 : 0; } long long y() { if (lei == 2) return sz ? mx + bo * 2 : 0; if (lei == 3) return sz ? tot + bo * 2 + (sz - 1) * sp : 0; } void add(node now) { sz++; if (lei == 2) { tot += now.X; mx = Max(mx, now.Y); } else if (lei == 3) { tot += now.Y; mx = Max(mx, now.X); } } bool operator<(const node &a) const { return name < a.name; } } A[(105)]; long long read(string k) { long long res = 0; for (long long i = 0; i < k.size(); i++) res = (res << 1) + (res << 3) + (k[i] ^ 48); return res; } map<string, long long> mp; string str; long long a, b; bool mark[(105)]; void dfs(long long x) { mark[x] = 1; for (long long i = head[x]; i; i = nxt[i]) { long long y = to[i]; if (!mark[y]) dfs(y), mark[y] = 1; A[x].add(A[y]); } if (A[x].lei != 1) { A[x].X = A[x].x(); A[x].Y = A[x].y(); } return; } bool MOP2; signed main() { scanf( %d , &T); while (T--) { cin >> str; if (str[0] == W ) { getchar(); getline(cin, str, ( ); mp[str] = ++n; A[n].lei = 1; A[n].name = str; scanf( %d,%d) , &A[n].X, &A[n].Y); } else if (str[0] == H ) { cin >> str; mp[str] = ++n; A[n].name = str; A[n].lei = 2; } else if (str[0] == V ) { cin >> str; mp[str] = ++n; A[n].name = str; A[n].lei = 3; } else { res = str.find( . ); a = mp[str.substr(0, res)]; if (str[res + 1] == s ) { long long now = str.find( ( ) + 1; long long tmp = read(str.substr(now, str.size() - now - 1)); if (str[res + 5] == b ) { A[a].bo = tmp; } else if (str[res + 5] == s ) { A[a].sp = tmp; } } else { b = mp[str.substr(res + 6, str.size() - res - 7)]; add(a, b); } } } for (long long i = 1; i <= n; i++) if (!mark[i]) dfs(i); sort(A + 1, A + 1 + n); for (long long i = 1; i <= n; i++) cout << A[i].name << << A[i].X << << A[i].Y << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; struct node { long long x, y; int id; bool operator<(const node& b) const { if (y != b.y) return y < b.y; else return x < b.x; } } a[210000], b[210000], c, d[210000]; vector<node> q; int n, num, last; int ans[210000]; set<node> s; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i].x >> a[i].y, a[i].id = i, d[i] = a[i]; sort(a + 1, a + 1 + n); for (int i = n; i >= 1; i--) if (a[i].x > last) last = a[i].x, b[++num] = a[i]; reverse(b + 1, b + 1 + num); for (int i = 1; i <= num; i++) { while (q.size() > 1) { node c = q[q.size() - 1], d = q[q.size() - 2]; if ((c.y - d.y) * d.x * b[i].y * (c.x - b[i].x) < (b[i].y - c.y) * b[i].x * d.y * (d.x - c.x)) q.pop_back(); else break; } q.push_back(b[i]); } num = 0; for (int i = 0; i < q.size(); i++) s.insert(q[i]); for (int i = 1; i <= n; i++) if (s.count(d[i])) printf( %d , i); return 0; }
|
#include <bits/stdc++.h> using namespace std; int sol(const vector<long long>& a, int n, int m, long long t) { long long s = 0; for (int i = 0; i < m; i++) s += a[i]; int ans = 0; for (int i = 0; i <= n && s * i <= t; i++) { int cnt = (m + 1) * i; long long r = t - s * i; for (int j = 0; j < m && r >= a[j]; j++) { int c = min(r / a[j], (long long)(n - i)); r -= a[j] * c; cnt += c; } ans = max(ans, cnt); } return ans; } int main() { int n, m; long long t; scanf( %d%d%lld , &n, &m, &t); vector<long long> a(m); for (int i = 0; i < m; i++) scanf( %lld , &a[i]); sort(a.begin(), a.end()); printf( %d n , sol(a, n, m, t)); }
|
`default_nettype none
`timescale 1ns/1ns
module tb_dly();
wire clk, reset;
clock clock(clk, reset);
reg in;
wire start;
wire out50ns, out70ns, out100ns, out150ns;
wire out200ns, out250ns, out400ns, out800ns;
dly50ns dstart(clk, ~reset, in, start);
dly50ns d50ns(clk, ~reset, start, out50ns);
dly70ns d70ns(clk, ~reset, start, out70ns);
dly100ns d100ns(clk, ~reset, start, out100ns);
dly150ns d150ns(clk, ~reset, start, out150ns);
dly200ns d200ns(clk, ~reset, start, out200ns);
dly250ns d250ns(clk, ~reset, start, out250ns);
dly400ns d400ns(clk, ~reset, start, out400ns);
dly800ns d800ns(clk, ~reset, start, out800ns);
wire out1us, out1_5us, out2us, out100us;
wire lv1us, lv1_5us, lv2us, lv100us;
ldly1us d1us(clk, ~reset, start, out1us, lv1us);
ldly1_5us d1_5us(clk, ~reset, start, out1_5us, lv1_5us);
ldly2us d2us(clk, ~reset, start, out2us, lv2us);
ldly100us d100us(clk, ~reset, start, out100us, lv100us);
wire driveedge;
edgedet drive(clk, reset, iot_drive, driveedge);
wire iot_t2, iot_t3, iot_t3a, iot_t4;
wire iot_init_setup, iot_final_setup, iot_reset, iot_restart;
ldly1us iot_dly1(clk, ~reset, start, iot_t2, iot_init_setup);
ldly1_5us iot_dly2(clk, ~reset,
iot_t2,
iot_t3a,
iot_final_setup);
ldly2us iot_dly3(clk, ~reset,
iot_t3a,
iot_t4,
iot_reset);
ldly1us iot_dly4(clk, ~reset,
iot_t2,
iot_t3,
iot_restart);
wire iot_drive = iot_init_setup | iot_final_setup | iot_t2;
initial begin
$dumpfile("dump.vcd");
$dumpvars();
in = 0;
#110;
in = 1;
#20;
in = 0;
end
initial begin
#40000;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, c, a[100005], sign[100005]; bool sign_ch[100005]; int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; sign[n] = 1; c = a[n]; for (int i = n - 1; i >= 1; i--) { if (c >= a[i]) { c -= a[i]; sign[i] = -1; } else { c = a[i] - c; sign[i] = 1; sign_ch[i + 1] = true; } } int flip = 0; for (int i = 1; i <= n; i++) { if (sign_ch[i] == true) flip = !flip; char ch; ch = sign[i] == 1 ? + : - ; if (flip) ch = ch == + ? - : + ; putchar(ch); } putchar( n ); return 0; }
|
module t;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire w11; // From bp3 of FswBypassArbiter.v
wire w12; // From bp3 of FswBypassArbiter.v
// End of automatics
/*AUTOREG*/
wand w0;
wor w1;
tri0 w2;
tri1 w3;
triand w4;
trior w5;
trireg w6;
tri w7;
wire w8;
supply0 w9;
supply1 w10;
FswBypassArbiter bp3 (/*AUTOINST*/
// Outputs
.w0 (w0),
.w1 (w1),
.w2 (w2),
.w3 (w3),
.w4 (w4),
.w5 (w5),
.w6 (w6),
.w7 (w7),
.w8 (w8),
.w9 (w9),
.w10 (w10),
.w11 (w11),
.w12 (w12));
endmodule
module FswBypassArbiter (/*AUTOARG*/
// Outputs
w0, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12
) ;
output w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
endmodule
|
//
// Copyright (c) 2014 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "nova_defs.v"
module nova_io(pclk, prst,
io_inst, io_op, io_result, io_skip, io_busy, io_pulse,
bs_stb, bs_we, bs_adr, bs_dout, bs_din);
input pclk;
input prst;
input [0:15] io_inst;
input [0:15] io_op;
output reg [0:15] io_result;
output reg io_skip;
output io_busy;
input io_pulse;
output reg bs_stb;
output reg bs_we;
output reg [0:7] bs_adr;
output reg [0:15] bs_dout;
input [0:15] bs_din;
// Decode
wire [0:1] inst_acc;
wire [0:2] inst_transfer;
wire [0:1] inst_control;
wire [0:5] inst_device;
assign inst_acc = io_inst[`NOVA_IO_ACC];
assign inst_transfer = io_inst[`NOVA_IO_TRANSFER];
assign inst_control = io_inst[`NOVA_IO_CONTROL];
assign inst_device = io_inst[`NOVA_IO_DEVICE];
wire [0:1] w_register;
assign w_register = (inst_transfer == `NOVA_IO_TRANSFER_DIA |
inst_transfer == `NOVA_IO_TRANSFER_DOA) ? 2'b01 :
(inst_transfer == `NOVA_IO_TRANSFER_DIB |
inst_transfer == `NOVA_IO_TRANSFER_DOB) ? 2'b10 :
(inst_transfer == `NOVA_IO_TRANSFER_DIC |
inst_transfer == `NOVA_IO_TRANSFER_DOC) ? 2'b11 :
(inst_transfer == `NOVA_IO_TRANSFER_SKP |
inst_transfer == `NOVA_IO_TRANSFER_NIO) ? 2'b00 :
2'bxx;
reg [0:2] r_state;
reg [0:2] r_state_next;
localparam SIDLE = 3'b000;
localparam SWAIT = 3'b001;
localparam SREAD = 3'b010;
localparam SSKIP = 3'b011;
localparam SCNTR = 3'b100;
assign io_busy = (|r_state) | io_pulse;
always @(posedge pclk) begin
if(prst) begin
io_result <= 16'h0000;
io_skip <= 1'b0;
//io_busy <= 1'b0;
bs_stb <= 1'b0;
bs_we <= 1'b0;
bs_adr <= 8'h00;
bs_dout <= 16'h0000;
r_state <= SIDLE;
r_state_next <= SIDLE;
end
else begin
case(r_state)
SIDLE:
begin
if(io_pulse) begin
io_skip <= 1'b0;
bs_adr <= {inst_device, w_register};
if(io_inst[0:2] == 3'b011) begin
if(inst_transfer == `NOVA_IO_TRANSFER_DIA |
inst_transfer == `NOVA_IO_TRANSFER_DIB |
inst_transfer == `NOVA_IO_TRANSFER_DIC) begin
bs_stb <= 1'b1;
bs_we <= 1'b0;
r_state <= SWAIT;
r_state_next <= SREAD;
end
else if(inst_transfer == `NOVA_IO_TRANSFER_DOA |
inst_transfer == `NOVA_IO_TRANSFER_DOB |
inst_transfer == `NOVA_IO_TRANSFER_DOC |
inst_transfer == `NOVA_IO_TRANSFER_NIO) begin
bs_stb <= 1'b1;
bs_we <= 1'b1;
bs_dout <= io_op;
if(|inst_control &
inst_transfer != `NOVA_IO_TRANSFER_NIO) begin
r_state <= SCNTR;
end
else begin
r_state <= SWAIT;
r_state_next <= SIDLE;
end
end // if (inst_transfer == `NOVA_IO_TRANSFER_DOA |...
else if(inst_transfer == `NOVA_IO_TRANSFER_SKP) begin
bs_stb <= 1'b1;
bs_we <= 1'b0;
r_state <= SWAIT;
r_state_next <= SSKIP;
end
end // if (io_inst[0:2] == 3'b011)
end
end // case: SIDLE
SREAD: begin
// TODO handle io errors (maybe?)
io_result <= bs_din;
if(|inst_control) begin
bs_we <= 1'b1;
bs_stb <= 1'b1;
bs_adr <= {inst_device, 2'b00};
bs_dout <= {14'h00, inst_control};
r_state <= SWAIT;
r_state_next <= SIDLE;
end
else
r_state <= SIDLE;
end
SCNTR:
begin
bs_adr <= {inst_device, 2'b00};
bs_dout <= {14'h00, inst_control};
bs_we <= 1'b1;
r_state <= SWAIT;
r_state_next <= SIDLE;
end
SWAIT:
begin
bs_stb <= 1'b0;
r_state <= r_state_next;
end
SSKIP:
begin
case(inst_control)
2'b00:
io_skip <= bs_din[0];
2'b01:
io_skip <= ~bs_din[0];
2'b10:
io_skip <= bs_din[1];
2'b11:
io_skip <= ~bs_din[1];
endcase // case (inst_control)
r_state <= SIDLE;
end
endcase // case (r_state)
end
end
endmodule // nova_io
|
#include <bits/stdc++.h> using namespace std; int N; int P[101010]; int V[101010]; vector<int> E[101010]; double T[101010]; void dfs(int cur, double tim) { tim += 1; T[cur] = tim; for (auto& r : E[cur]) { double el = (V[cur] - 1 - V[r]) * 0.5; dfs(r, tim + el); } } void solve() { int i, j, k, l, r, x, y; string s; cin >> N; for (i = 1; i < N; i++) cin >> P[i], P[i]--, E[P[i]].push_back(i); for (i = N - 1; i >= 0; i--) { V[i]++; if (i) V[P[i]] += V[i]; } dfs(0, 0); for (i = 0; i < (N); i++) (void)printf( %lf%c , T[i], (i == N - 1) ? n : ); } int main(int argc, char** argv) { string s; int i; if (argc == 1) ios::sync_with_stdio(false), cin.tie(0); for (i = 0; i < (argc - 1); i++) s += argv[i + 1], s += n ; for (i = 0; i < (s.size()); i++) ungetc(s[s.size() - 1 - i], stdin); solve(); return 0; }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Bus Controller (MBC) Power Gate Header (Active High)
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module mbc_header
(
//**************************************
//Power Domain
//Input - Always On
//Output - MBUS Bus Controller Domain
//**************************************
//Signals
//Input
SLEEP
//Output
);
input SLEEP; //Active High
always @(SLEEP) begin
if (SLEEP) begin
$write("%c[1;34m",27);
$display("***********************************************");
$display("*********MBUS CONTROLLER IS POWER GATED********");
$display("*********AT TIME:", $time);
$display("***********************************************");
$write("%c[0m",27);
end
else begin
$write("%c[1;34m",27);
$display("***********************************************");
$display("********MBUS CONTROLLER IS POWER UNGATED*******");
$display("*********AT TIME:", $time);
$display("***********************************************");
$write("%c[0m",27);
end
end // always @ (SLEEP)
endmodule // mbc_header
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_1_V
`define SKY130_FD_SC_LS__A2111OI_1_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); long long n; cin >> n; string s; cin >> s; for (long long i = 0; i < n - 1; i++) { if (s[i] > s[i + 1]) { cout << YES << endl; cout << i + 1 << << i + 2 << endl; return 0; } } cout << NO << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_TB_V
/**
* udp_dff$P_pp$PG: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_p_pp_pg.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$P_pp$PG dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_TB_V
|
#include <bits/stdc++.h> using namespace std; int read(int &x) { return scanf( %d , &x); } int read(long long &x) { return scanf( %lld , &x); } int read(double &x) { return scanf( %lf , &x); } int read(int &x, int &y) { return scanf( %d%d , &x, &y); } int read(long long &x, long long &y) { return scanf( %lld%lld , &x, &y); } int read(double &x, double &y) { return scanf( %lf%lf , &x, &y); } int read(int &x, int &y, int &z) { return scanf( %d%d%d , &x, &y, &z); } int read(long long &x, long long &y, long long &z) { return scanf( %lld%lld%lld , &x, &y, &z); } int read(double &x, double &y, double &z) { return scanf( %lf%lf%lf , &x, &y, &z); } long long qpow(long long a, long long b, long long mod) { if (a == 0) return 0; long long ans = 1; a %= mod; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans % mod; } long long inv(long long x, long long mod) { return qpow(x, mod - 2, mod); } int dir[4][2] = {0, 1, 0, -1, 1, 0, -1, 0}; int mon[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const int N = 5e5 + 5; struct DSU { int f[N]; void init(int n) { for (int i = 0; i <= n; i++) f[i] = i; } int fa(int x) { return f[x] == x ? x : f[x] = fa(f[x]); } void join(int x, int y) { x = fa(x); y = fa(y); if (x != y) f[x] = y; } }; struct CombMath { long long C[2005][2005]; void init(int n) { for (int i = 0; i <= n; i++) C[i][0] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } }; struct _2sat { vector<int> G[N << 1]; int dfn[N << 1], low[N << 1], stk[N << 1], color[N << 1]; int t, tp, scc; bool vis[N << 1]; void init(int n) { for (int i = 0; i <= 2 * n; i++) G[i].clear(); for (int i = 0; i <= n * 2; i++) dfn[i] = low[i] = color[i] = vis[i] = 0; t = tp = scc = 0; } void add(int x, int xv, int y, int yv) { x = x * 2 + xv; y = y * 2 + yv; G[x ^ 1].push_back(y); G[y ^ 1].push_back(x); } void addmaodun(int x, int xv, int y, int yv) { x = x * 2 + (xv ^ 1); y = y * 2 + (yv ^ 1); G[x ^ 1].push_back(y); G[y ^ 1].push_back(x); } void tarjan(int x) { dfn[x] = low[x] = ++t; stk[++tp] = x; vis[x] = 1; for (auto v : G[x]) { if (!dfn[v]) { tarjan(v); low[x] = min(low[x], low[v]); } else if (vis[v]) low[x] = min(low[x], dfn[v]); } if (low[x] == dfn[x]) { color[x] = ++scc; vis[x] = 0; while (stk[tp] != x) { color[stk[tp]] = scc; vis[stk[tp--]] = 0; } tp--; } } void work(int n) { for (int i = 0; i < 2 * n; i++) if (!dfn[i]) tarjan(i); for (int i = 0; i < n; i++) if (color[i * 2] == color[i * 2 + 1]) { puts( -1 ); return; } vector<int> row, col; for (int i = 0; i < n / 2; i++) { if (color[i * 2] < color[i * 2 + 1]) { continue; } else { row.push_back(i); } } for (int i = n / 2; i < n; i++) { if (color[i * 2] < color[i * 2 + 1]) { continue; } else { col.push_back(i - n / 2); } } int sz = row.size() + col.size(); printf( %d n , sz); for (auto it : row) printf( row %d n , it); for (auto it : col) printf( col %d n , it); } } twosat; char s[N]; int a[2005]; int g[2005][2005]; signed main() { int n; read(n); getchar(); for (int k = 1; k <= 2; k++) { for (int i = 1; i <= n; i++) { gets(s + 1); for (int j = 1; j <= n; j++) { g[i][j] ^= (s[j] - 0 ); } } } twosat.init(2 * n); gets(s + 1); for (int i = 1; i <= n; i++) a[i] = s[i] - 0 ; bool ok = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int n1 = a[i], n2 = a[j]; int ii = i - 1, jj = j + n - 1; if (g[i][j] == 1) { if (n1 == 1 and n2 == 1) { twosat.G[ii * 2].push_back(jj * 2 + 1); twosat.G[jj * 2].push_back(ii * 2 + 1); twosat.G[ii * 2 + 1].push_back(jj * 2); twosat.G[jj * 2 + 1].push_back(ii * 2); } else if (n2 == 1) { twosat.G[ii * 2].push_back(ii * 2 + 1); } else if (n1 == 1) { twosat.G[jj * 2].push_back(jj * 2 + 1); } else { ok = 0; } } else { if (n1 == 1 and n2 == 1) { twosat.G[ii * 2].push_back(jj * 2); twosat.G[ii * 2 + 1].push_back(jj * 2 + 1); twosat.G[jj * 2].push_back(ii * 2); twosat.G[jj * 2 + 1].push_back(ii * 2 + 1); } else if (n2 == 1) { twosat.G[ii * 2 + 1].push_back(ii * 2); } else if (n1 == 1) { twosat.G[jj * 2 + 1].push_back(jj * 2); } else { continue; } } } } if (!ok) puts( -1 ); else { twosat.work(n * 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long x[200001], y[200001], dp[200001], n; bool s[200001]; long long find_upper_bound(long long l, long long r, long long value) { long long mid, index = 1; while (l <= r) { mid = l + (r - l) / 2; if (x[mid] >= value) { index = mid; r = mid - 1; } else l = mid + 1; } return index; } int main() { int t; t = 1; while (t--) { dp[0] = 0; cin >> n; for (int i = 1; i <= n; i++) cin >> x[i] >> y[i] >> s[i]; long long ans = (x[n] + 1) % 998244353, temp; for (int i = 1; i <= n; i++) { temp = find_upper_bound(1, i, y[i]); dp[i] = x[i] - y[i]; if (temp != i) dp[i] = (dp[i] + (dp[i - 1] - dp[temp - 1] + 998244353) % 998244353) % 998244353; if (s[i]) ans = (ans + dp[i]) % 998244353; dp[i] = (dp[i] + dp[i - 1]) % 998244353; } cout << ans << endl; } }
|
// DSP48E1
// [1] 7 Series DSP48E1 User Guide UG479 (v1.9) September 27, 2016
// Figure 2-8 and Table 2-6 shows details
`include "bin_mux/bin_mux.sim.v"
`include "b1reg_mux/b1reg_mux.sim.v"
`include "b2reg_mux/b2reg_mux.sim.v"
`include "bc_mux/bc_mux.sim.v"
`include "bmult_mux/bmult_mux.sim.v"
`include "../nreg/nreg.sim.v"
module DUAL_B_REG
(
B, BCIN, INMODE,
BCOUT, XMUX, BMULT,
CEB1, CEB2, RSTB, CLK
);
// input mux
// DIRECT: use B port
// CASCADE: use BCIN port
parameter B_INPUT = "DIRECT";
// Number of registers in pipeline
parameter BREG = 1;
// Number of registers in BC pipeline
// BREG = 0: BCASCREG must be 0
// BREG = 1: BCASCREG must be 1
// BREG = 2: BCASCREG can be 1 or 2
parameter BCASCREG = 1;
input wire [17:0] B;
input wire [17:0] BCIN;
input wire [4:0] INMODE;
output wire [17:0] BCOUT;
output wire [17:0] XMUX;
output wire [17:0] BMULT;
input wire CEB1;
input wire CEB2;
input wire RSTB;
input wire CLK;
wire [17:0] B1IN;
wire [17:0] B1OUT;
wire [17:0] B2IN;
wire [17:0] B2OUT;
BIN_MUX #(.S(B_INPUT == "CASCADE")) bin_mux (.B(B), .BCIN(BCIN), .O(B1IN));
B1REG_MUX #(.S(BREG>1)) b1_mux (.BYPASS(B1IN), .REG(B1OUT), .O(B2IN));
B2REG_MUX #(.S(BREG>0)) b2_mux (.BYPASS(B2IN), .REG(B2OUT), .O(XMUX));
// If 0, then both reg muxes are in bypass, so use B2_MUX output
// If 1, then use B1 register output (this works for BREG=1 or 2
// If 2, then both reg muxes are not in bypass so use B2_MUX output
BC_MUX #(.S(BCASCREG == 1)) bc_mux (.B1REG(B1OUT), .B2(XMUX), .O(BCOUT));
NREG #(.NBITS(18)) b1 (.D(B1IN), .Q(B1OUT), .CLK(CLK), .CE(CEB1), .RESET(RSTB));
NREG #(.NBITS(18)) b2 (.D(B2IN), .Q(B2OUT), .CLK(CLK), .CE(CEB2), .RESET(RSTB));
BMULT_MUX bmultmux (.B2(XMUX), .B1REG(B1OUT), .S(INMODE[4]), .O(BMULT));
endmodule // DUALB_REG
|
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:46:56 04/06/2015
// Design Name: division
// Module Name: S:/a/asw011/public/PrimeFactorization/testDivision.v
// Project Name: PrimeFactorization
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: division
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDivision;
// Inputs
reg [0:31] n;
reg [0:15] d;
reg clk;
reg reset;
// Outputs
wire [0:31] q;
wire isFactor;
wire isDone;
// Instantiate the Unit Under Test (UUT)
division uut (
.n(n),
.d(d),
.clk(clk),
.reset(reset),
.q(q),
.isFactor(isFactor),
.isDone(isDone)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs\
reset = 0;
clk = 0;
n = 100;
d = 11;
#150;
n = 100;
d = 10;
reset = 1;
#10;
reset = 0;
#150;
n = 27;
d = 3;
reset = 1;
#10;
reset = 0;
#150;
n = 84;
d = 40;
reset = 1;
#10;
reset = 0;
#150;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_SYMBOL_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd1 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O221A_PP_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o221a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int N = 1e5 + 10, M = 1024; int a[N], cnt[N], n, k, x; int main() { scanf( %d %d %d , &n, &k, &x); int ai; for (int i = 1; i <= n; i++) { scanf( %d , &ai); a[ai]++; } for (int ca = 1; ca <= k; ca++) { int tot = 0, y; for (int i = 0; i <= M; i++) { if (tot & 1) cnt[i] = a[i] >> 1; else cnt[i] = (a[i] + 1) >> 1; tot += a[i]; } for (int i = 0; i <= M; i++) a[i] -= cnt[i], a[i ^ x] += cnt[i]; } for (int i = M; i >= 0; i--) if (a[i]) { printf( %d , i); break; } for (int i = 0; i <= M; i++) if (a[i]) { printf( %d n , i); break; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; bool flag = false; cin >> s; stringstream ss(s); char arr[2 * n]; int min0 = 10; int max0 = 0; int min1 = 10; int max1 = 0; for (int i = 0; i < 2 * n; i++) { arr[i] = s.at(i); if (i < n) { if (min0 > (int)arr[i] - 48) { min0 = (int)arr[i] - 48; } if (max0 < (int)arr[i] - 48) { max0 = (int)arr[i] - 48; } } else { if (min1 > (int)arr[i] - 48) { min1 = (int)arr[i] - 48; } if (max1 < (int)arr[i] - 48) { max1 = (int)arr[i] - 48; } } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if ((int)arr[i] - 48 > (int)arr[j] - 48) { char temp = arr[i]; arr[i] = arr[j]; arr[j] = temp; } if ((int)arr[i + n] - 48 > (int)arr[j + n] - 48) { char temp = arr[i + n]; arr[i + n] = arr[j + n]; arr[j + n] = temp; } } } if (min0 < min1) { for (int i = 0; i < n; i++) { if (int(arr[i]) >= int(arr[i + n])) { flag = true; break; } } } else { for (int i = 0; i < n; i++) { if (int(arr[i]) <= int(arr[i + n])) { flag = true; break; } } } if (flag) { cout << NO << endl; } else { cout << YES << endl; } return 0; }
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Based on PR#564 */
module main( );
parameter [7:0] forwards = 8'b11110001;
parameter [0:7] backwards = 8'b10001111;
integer i;
initial begin
for (i = 0 ; i < 8 ; i = i + 1) begin
$write("forwards[%0d] === %b, ", i, forwards[i]);
$display("backwards[%0d] === %b", i, backwards[i]);
if (forwards[i] !== backwards[i]) begin
$display("FAILED -- forwards[%0d] !== backwards[%0d]", i, i);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_4_V
`define SKY130_FD_SC_LP__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 5000 + 5, mod = 1000 * 1000 * 1000 + 7; long long dp[N][N], ps[N]; int main() { long long n, a, b, k; cin >> n >> a >> b >> k; a--, b--; for (int i = 0; i < n; i++) { dp[0][i] = 1; } dp[0][b] = 0; for (int i = 0; i < n; i++) { ps[i + 1] = ps[i] + dp[0][i]; ps[i + 1] %= mod; } for (int i = 1; i <= k; i++) { for (int j = 0; j < n; j++) { if (j < b) { dp[i][j] = (ps[b] - ps[j + 1]) + (ps[j] - ps[max(0 * 1ll, j - (b - j) + 1)]); dp[i][j] += 2 * mod; dp[i][j] %= mod; } else { dp[i][j] = (ps[j] - ps[b + 1]) + (ps[min(n, j + (j - b))] - ps[j + 1]); dp[i][j] += 2 * mod; dp[i][j] %= mod; } } ps[0] = 0; for (int j = 0; j < n; j++) { ps[j + 1] = ps[j] + dp[i][j]; ps[j + 1] += 2 * mod; ps[j + 1] %= mod; } } cout << dp[k][a] % mod; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a, b; cin >> a >> b; if (a == b) { cout << infinity << n ; return 0; } if (a < b) { cout << 0 << n ; return 0; } long long ans = 0; long long n = a - b; for (long long i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (i == n / i) { if (i > b) ans++; } else { if (i > b) ans++; if (n / i > b) ans++; } } } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; string s; cin >> n; cin >> s; int l = 0, r = n - 1, x = 0, y = 0; while (s[l] == < ) { l++; x++; } while (s[r] == > ) { r--; y++; } cout << min(x, y) << endl; ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long k, x; long long a[200010]; int main() { int n; while (cin >> n >> k >> x) { int negative = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] < 0) ++negative; } if (negative % 2 == 0) { int minId = 0; for (int i = 1; i < n; i++) { if (abs(a[i]) < abs(a[minId])) minId = i; } long long num = abs(a[minId]) / x + 1; if (a[minId] >= 0) a[minId] -= min(num, k) * x; else a[minId] += min(num, k) * x; k = max(k - num, 0LL); } priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > que; for (int i = 0; i < n; i++) { que.push(make_pair(abs(a[i]), i)); } while (k--) { pair<int, int> cur = que.top(); que.pop(); int id = cur.second; if (a[id] >= 0) a[id] += x; else a[id] -= x; que.push(make_pair(abs(a[id]), id)); } for (int i = 0; i < n; i++) { if (i != n - 1) cout << a[i] << ; else cout << a[i] << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, n; long long power(long long b, long long p) { if (p == 0) return 1; long long ret = power(b, p / 2); ret *= ret; if (p & 1) ret *= b; return ret; } long long check(long long x) { return a * power(x, n); } int main() { cin >> a >> b >> n; if (b == 0) { cout << 0 << n ; return 0; } if (a == 0) { cout << No solution << n ; return 0; } if (b % a) { cout << No solution << n ; return 0; } long long x = pow(abs(b / a), 1.0 / n) + 0.5; if (check(x) != b) x *= -1; if (check(x) != b) { cout << No solution << n ; return 0; } cout << x << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class node> struct link_cut_tree { bool connected(node* u, node* v) { return lca(u, v) != NULL; } int depth(node* u) { access(u); return get_sz(u->ch[0]); } node* get_root(node* u) { access(u); while (u->ch[0]) u = u->ch[0], u->push(); return access(u), u; } node* ancestor(node* u, int k) { k = depth(u) - k; assert(k >= 0); for (;; u->push()) { int sz = get_sz(u->ch[0]); if (sz == k) return access(u), u; if (sz < k) k -= sz + 1, u = u->ch[1]; else u = u->ch[0]; } assert(0); } node* lca(node* u, node* v) { if (u == v) return u; access(u); access(v); if (!u->p) return NULL; u->splay(); return u->p ?: u; } void link(node* u, node* v) { make_root(v); access(u); set_link(v, u, 0); v->update(); } void cut(node* u) { access(u); u->ch[0]->p = NULL; u->ch[0] = NULL; u->update(); } void cut(node* u, node* v) { cut(depth(u) > depth(v) ? u : v); } void make_root(node* u) { access(u); u->reverse(); access(u); assert(!u->ch[0] && !u->ch[1]); } void access(node* u) { for (node *v = u, *pre = NULL; v; v = v->p) { v->splay(); if (pre) v->update_vsub(pre, false); if (v->ch[1]) v->update_vsub(v->ch[1], true); v->ch[1] = pre; v->update(); pre = v; } u->splay(); assert(!u->ch[1]); } node* operator[](int i) { return &data[i]; } int operator[](node* i) { return i - &data[0]; } vector<node> data; link_cut_tree(int n) : data(n) {} }; template <typename pnode> struct splay_tree { pnode ch[2], p; splay_tree() { ch[0] = ch[1] = p = NULL; } int dir() { if (!p) return -2; if (p->ch[0] == this) return 0; if (p->ch[1] == this) return 1; return -1; } bool is_root() { return dir() < 0; } friend void set_link(pnode u, pnode v, int d) { if (v) v->p = u; if (d >= 0) u->ch[d] = v; } void rotate() { assert(!is_root()); int x = dir(); pnode g = p; set_link(g->p, static_cast<pnode>(this), g->dir()); set_link(g, ch[x ^ 1], x); set_link(static_cast<pnode>(this), g, x ^ 1); g->update(); } void splay() { const pnode& self = static_cast<pnode>(this); while (!is_root() && !p->is_root()) { p->p->push(), p->push(), self->push(); dir() == p->dir() ? p->rotate() : self->rotate(); self->rotate(); } if (!is_root()) p->push(), self->push(), self->rotate(); self->push(); self->update(); } }; template <typename pnode, class splay_tree_vchs> struct splay_tree_lct : splay_tree<pnode> { splay_tree_vchs vnode; using splay_tree<pnode>::ch; bool rev; splay_tree_vchs* root; splay_tree_lct() : splay_tree<pnode>() { root = NULL; rev = 0; } void update() {} void push() { if (rev) { if (ch[0]) ch[0]->reverse(); if (ch[1]) ch[1]->reverse(); rev = 0; } } void rotate() { swap(vnode, this->p->vnode); splay_tree<pnode>::rotate(); } void splay() { auto v = &vnode; bool r = !v->key; splay_tree<pnode>::splay(); if (r && v->key) { if (v->p) v->p->ch[v->p->ch[1] == &v->key->vnode] = v; if (v->ch[0]) v->ch[0]->p = v; if (v->ch[1]) v->ch[1]->p = v; v->key = static_cast<pnode>(this); } } void reverse() { rev ^= 1; swap(ch[0], ch[1]); } void update_vsub(pnode v, bool add) { auto& u = root; if (add) { v->vnode = splay_tree_vchs(v); if (!u) { u = &v->vnode; return; } while (u->ch[1]) u = u->ch[1]; u->ch[1] = &v->vnode; u->ch[1]->p = u; u = u->ch[1]; u->splay(); } else { auto x = &v->vnode; x->splay(); if (!x->ch[0]) { u = x->ch[1]; } else if (!x->ch[1]) { u = x->ch[0]; } else { u = x->ch[0]; u->p = NULL; while (u->ch[1]) u = u->ch[1]; u->ch[1] = x->ch[1]; x->ch[1]->p = u; u->splay(); } if (u) u->p = NULL; x->key = NULL; } } }; const int inf = -1e8; template <typename pnode> struct splay_tree_vchs : splay_tree<splay_tree_vchs<pnode>*> { using splay_tree<splay_tree_vchs<pnode>*>::ch; pnode key; int x; array<int, 4> y; splay_tree_vchs(){}; splay_tree_vchs(const pnode& key) : splay_tree<splay_tree_vchs<pnode>*>(), key(key) { build(); } void build() { x = key->x; y[0] = key->pp[0]; y[1] = 0; y[2] = key->pp[1]; y[3] = inf; } void update() { build(); for (int c = 0; c < 2; ++c) if (ch[c]) { x = max(x, ch[c]->x); for (int i = 0; i < 4; i += 2) { if (ch[c]->y[i] > y[i]) { y[i + 1] = y[i]; y[i] = ch[c]->y[i]; if (ch[c]->y[i + 1] > y[i + 1]) y[i + 1] = ch[c]->y[i + 1]; } else if (ch[c]->y[i] > y[i + 1]) y[i + 1] = ch[c]->y[i]; } } } void push() {} }; const array<int, 4> ainf = {0, inf, 0, inf}; struct node : splay_tree_lct<node*, splay_tree_vchs<node*>> { bool val, len, sval; int slen; int x; array<int, 4> pp; node() : splay_tree_lct() { val = len = sval = 0; slen = x = 0; pp = ainf; } void update() { splay_tree_lct::update(); x = 0; sval = val; slen = len; array<int, 4> up = ainf, dw = ainf; array<int, 2> v1 = {0, inf}, v2 = v1; bool upsval = val; int upslen = len; bool dwsval = val; int dwslen = len; if (ch[0]) { x = max(x, ch[0]->x); up = ch[0]->pp; sval ^= ch[0]->sval; slen += ch[0]->slen; upsval ^= ch[0]->sval; upslen += ch[0]->slen; } if (ch[1]) { x = max(x, ch[1]->x); dw = ch[1]->pp; sval ^= ch[1]->sval; slen += ch[1]->slen; dwsval ^= ch[1]->sval; dwslen += ch[1]->slen; } if (root) { x = max(x, root->x); v1[0] = root->y[0]; v1[1] = root->y[2]; v2[0] = root->y[1]; v2[1] = root->y[3]; } pp[0] = up[0], pp[1] = up[1]; pp[2] = dw[2], pp[3] = dw[3]; for (int i = 0; i < 2; ++i) { x = max(x, len + max({up[2 + i] + dw[i ^ val], up[2 + i] + v1[i ^ val], dw[i] + v1[i ^ val], v1[i] + v2[i ^ val]})); pp[i ^ upsval] = max(pp[i ^ upsval], upslen + max(dw[i], v1[i])); pp[2 + (i ^ dwsval)] = max(pp[2 + (i ^ dwsval)], dwslen + max(up[2 + i], v1[i])); } } void push() { splay_tree_lct::push(); } void reverse() { splay_tree_lct::reverse(); swap(pp[0], pp[2]); swap(pp[1], pp[3]); } }; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n; cin >> n; link_cut_tree<node> lct(2 * n); vector<vector<tuple<int, bool, int>>> adj(n); for (int i = 1, u, v, w; i < n; ++i) { cin >> u >> v >> w; --u, --v; adj[u].push_back({v, w, i}); adj[v].push_back({u, w, i}); } function<void(int, int)> dfs = [&](int u, int p) { for (auto [v, w, i] : adj[u]) if (v != p) { dfs(v, u); lct[n + i]->val = w; lct[n + i]->len = true; lct[n + i]->update(); lct.link(lct[u], lct[n + i]); lct.link(lct[n + i], lct[v]); } }; dfs(0, -1); int q; cin >> q; for (int i = 0, u; i < q; ++i) { cin >> u; lct.access(lct[n + u]); lct[n + u]->val ^= 1; lct[n + u]->update(); cout << lct[n + u]->x << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; int n, q; long long int m; vector<long long int> mods; long long int w[N]; long long int phi(long long int x) { long long int ans = x; for (long long int i = 2; i * i <= x; i++) { if (x % i == 0) { ans -= ans / i; while (x % i == 0) { x /= i; } } } if (x > 1) { ans -= ans / x; } return ans; } long long int magic(long long int x, long long int mod) { if (x < 50) { return x; } return 32 + (x - 32) % mod; } long long int fexp(long long int base, long long int e, long long int mod) { long long int ans = 1; while (e > 0) { if (e & 1) { ans = magic(ans * base, mod); } base = magic(base * base, mod); e >>= 1; } return ans; } long long int go(int l, int r, int on) { if (r == l) { return magic(w[l], mods[on]); } if (mods[on] == 1) { return magic(w[l], mods[on]); } long long int e = go(l + 1, r, on + 1); return fexp(w[l], e, mods[on]); } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m; mods.push_back(m); while (mods.back() != 1) { mods.push_back(phi(mods.back())); } for (int i = 0; i < n; i++) { cin >> w[i]; } cin >> q; while (q--) { int l, r; cin >> l >> r; l--; r--; cout << go(l, r, 0) % mods[0] << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int binExp(long long int x, long long int n, long long int m) { long long int res = 1; while (n) { if (n & 1) res = (res * x) % m; x = (x * x) % m; n >>= 1; } return res; } long long int modInv(long long int i, long long int m) { return binExp(i, m - 2, m); } long long int add(long long int a, long long int b) { long long int res = a + b; if (res >= 1000000007) res -= 1000000007; if (res < 0) res += 1000000007; return res; } long long int mul(long long int a, long long int b) { long long int res = (a) * (b); res %= 1000000007; if (res < 0) res += 1000000007; return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t, t1 = 1; cin >> t; while (t--) { string str; cin >> str; int odd = 0, even = 0, oddq = 0, evenq = 0, oddt = 0, event = 0, ans = 0; for (int i = 0; i < 10; i++) { if (i % 2 != 0) { event++; if (str[i] == 1 ) { even++; } if (str[i] == ? ) { evenq++; } int oddrem = 5 - oddt; int evenrem = 5 - event; if ((odd + oddq - even) > evenrem) { ans = i + 1; break; } if ((even + evenq - odd) > oddrem) { ans = i + 1; break; } } else { oddt++; if (str[i] == 1 ) { odd++; } if (str[i] == ? ) { oddq++; } int oddrem = 5 - oddt; int evenrem = 5 - event; if ((odd + oddq - even) > evenrem) { ans = i + 1; break; } if ((even + evenq - odd) > oddrem) { ans = i + 1; break; } } } if (ans == 0) { cout << 10 << endl; continue; } cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O32A_PP_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; pair<pair<int, int>, int> a[100100]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; a[i].first.first = x; } for (int i = 1; i <= n; i++) { int x; cin >> x; a[i].first.second = x; a[i].second = i; } sort(a + 1, a + n + 1); reverse(a + 1, a + n + 1); cout << (n / 2) + 1 << endl; cout << a[1].second << ; for (int i = 2; i <= n; i += 2) { if (i == n) cout << a[i].second; else { int x = a[i].second; if (a[i + 1].first.second > a[i].first.second) x = a[i + 1].second; cout << x << ; } } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "NIOS_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__diode (
DIODE
);
// Module ports
input DIODE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DIODE_BEHAVIORAL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_aea_e
//
// Generated
// by: wig
// on: Wed Aug 18 12:44:01 2004
// cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../constant.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_aea_e.v,v 1.2 2004/08/18 10:47:11 wig Exp $
// $Date: 2004/08/18 10:47:11 $
// $Log: inst_aea_e.v,v $
// Revision 1.2 2004/08/18 10:47:11 wig
// reworked some testcases
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
//
// Generator: mix_0.pl Revision: 1.32 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_aea_e
//
// No `defines in this module
module inst_aea_e
//
// Generated module inst_aea
//
(
bus20040728_altop_i,
bus20040728_top_i
);
// Generated Module Inputs:
input [7:0] bus20040728_altop_i;
input [7:0] bus20040728_top_i;
// Generated Wires:
wire [7:0] bus20040728_altop_i;
wire [7:0] bus20040728_top_i;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_aea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include<bits/stdc++.h> using namespace std; const int N = 2000 + 10; int n; bool flag[N]; bool Query(int l1, int r1, int l2, int r2) { printf( ? %d %d n , r1 - l1 + 1, r2 - l2 + 1); for (int i = l1; i <= r1; i++) printf( %d%c , i, n [i == r1]); for (int i = l2; i <= r2; i++) printf( %d%c , i, n [i == r2]); fflush(stdout); int res; scanf( %d , &res); return res; } void Solve() { scanf( %d , &n); for (int i = 1; i <= n; i++) flag[i] = 0; for (int i = 2; i <= n; i++) { if (Query(1, i - 1, i, i)) { // printf( i = %d n , i); flag[i] = 1; for (int j = i + 1; j <= n; j++) { if (Query(i, i, j, j)) { flag[j] = 1; } } int L = 1, R = i - 1, ans = 0; while (L <= R) { // printf( L = %d, R = %d n , L, R); int M = (L + R) >> 1; if (Query(1, M, i, i)) R = M - 1, ans = M; else L = M + 1; } // printf( ans = %d n , ans); flag[ans] = 1; break; } } // puts( ans ); // for (int i = 1; i <= n; i++) { // } vector <int> ans; for (int i = 1; i <= n; i++) { if (!flag[i]) { ans.push_back(i); } } printf( ! %d n , ans.size()); for (auto x : ans) { printf( %d , x); } puts( ); fflush(stdout); } int main(){ srand(time(0)); #ifndef ONLINE_JUDGE // freopen( data.in , r , stdin); // freopen( tst.out , w , stdout); clock_t st = clock(); #endif int T = 1; scanf( %d , &T); while (T--) { Solve(); } #ifndef ONLINE_JUDGE clock_t ed = clock(); printf( time : %.6lfs n , 1.0 * (ed - st) / CLOCKS_PER_SEC); #endif return 0; }
|
// cog_alu
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style
module cog_alu
(
input [5:0] i,
input [31:0] s,
input [31:0] d,
input [8:0] p,
input run,
input ci,
input zi,
input [31:0] bus_q,
input bus_c,
output wr,
output [31:0] r,
output co,
output zo
);
// rotation instructions
wire [31:0] dr = { d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7],
d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15],
d[16], d[17], d[18], d[19], d[20], d[21], d[22], d[23],
d[24], d[25], d[26], d[27], d[28], d[29], d[30], d[31] };
wire [255:0] ri = { 32'b0, // rev
{32{d[31]}}, // sar
{32{ci}}, // rcl
{32{ci}}, // rcr
32'b0, // shl
32'b0, // shr
dr[31:0], // rol
d[31:0] }; // ror
wire [63:0] rot = {ri[i[2:0]*32 +: 32], i[0] ? dr : d} >> s[4:0];
wire [31:0] rotr = { rot[0], rot[1], rot[2], rot[3], rot[4], rot[5], rot[6], rot[7],
rot[8], rot[9], rot[10], rot[11], rot[12], rot[13], rot[14], rot[15],
rot[16], rot[17], rot[18], rot[19], rot[20], rot[21], rot[22], rot[23],
rot[24], rot[25], rot[26], rot[27], rot[28], rot[29], rot[30], rot[31] };
wire [31:0] rot_r = ~&i[2:1] && i[0] ? rotr : rot[31:0];
wire rot_c = ~&i[2:1] && i[0] ? dr[0] : d[0];
// mins/maxs/min/max/movs/movd/movi/jmpret/and/andn/or/xor/muxc/muxnc/muxz/muxnz
wire [1:0] log_s = i[2] ? {(i[1] ? zi : ci) ^ i[0], 1'b0} // muxc/muxnc/muxz/muxnz
: {i[1], ~^i[1:0]}; // and/andn/or/xor
wire [127:0] log_x = { d ^ s, // 11 = xor
d | s, // 10 = or mux 1
d & s, // 01 = and
d & ~s }; // 00 = andn mux 0
wire [127:0] mov_x = { d[31:9], p, // jmpret
s[8:0], d[22:0], // movi
d[31:18], s[8:0], d[8:0], // movd
d[31:9], s[8:0] }; // movs
wire [31:0] log_r = i[3] ? log_x[log_s*32 +: 32] // and/andn/or/xor/muxc/muxnc/muxz/muxnz
: i[2] ? mov_x[i[1:0]*32 +: 32] // movs/movd/movi/jmpret
: s; // mins/maxs/min/max
wire log_c = ^log_r; // c is parity of result
// add/sub instructions
wire [3:0] ads = {zi, ci, s[31], 1'b0};
wire add_sub = i[5:4] == 2'b10 ? ads[i[2:1]] ^ i[0] // add/sub/addabs/subabs/sumc/sumnc/sumz/sumnz/mov/neg/abs/absneg/negc/negnc/negz/negnz
: i[5:0] == 6'b110010 || // addx
i[5:0] == 6'b110100 || // adds
i[5:0] == 6'b110110 || // addsx
i[5:2] == 4'b1111 ? 1'b0 // waitcnt
: 1'b1; // other subs
wire add_ci = i[5:3] == 3'b110 && (i[2:0] == 3'b001 || i[1]) && ci || // cmpsx/addx/subx/addsx/subsx
i[4:3] == 2'b11 && i[1:0] == 2'b01; // djnz
wire [31:0] add_d = i[4:3] == 2'b01 ? 32'b0 : d; // mov/neg/abs/absneg/negc/negnc/negz/negnz
wire [31:0] add_s = i[4:0] == 5'b11001 || i[4:1] == 4'b1101 ? 32'hFFFFFFFF // djnz/tjnz/tjz
: add_sub ? ~s // subs
: s; // adds
wire [34:0] add_x = {1'b0, add_d[31], 1'b1, add_d[30:0], 1'b1} +
{1'b0, add_s[31], 1'b0, add_s[30:0], add_ci ^ add_sub};
wire [31:0] add_r = {add_x[33], add_x[31:1]};
wire add_co = add_x[34];
wire add_cm = !add_x[32];
wire add_cs = add_co ^ add_d[31] ^ add_s[31];
wire add_c = i[5:0] == 6'b111000 ? add_co // cmpsub
: i[5:3] == 3'b101 ? s[31] // source msb
: i[5] && i[3:2] == 2'b01 ? add_co ^ add_cm // overflow
: i[4:1] == 4'b1000 ? add_cs // signed
: add_co ^ add_sub; // unsigned
// write-cancel instructions
assign wr = i[5:2] == 4'b0100 ? i[0] ^ (i[1] ? !add_co : add_cs) // mins/maxs/min/max
: i[5:0] == 6'b111000 ? add_co // cmpsub
: 1'b1; // others
// r, c, z results
assign r = i[5] ? add_r
: i[4] ? log_r
: i[3] ? rot_r
: run || ~&p[8:4] ? bus_q
: 32'b0; // write 0's to last 16 registers during load;
assign co = i[5:3] == 3'b000 ? bus_c
: i[5:3] == 3'b001 ? rot_c
: i[5:3] == 3'b011 ? log_c
: add_c;
assign zo = ~|r && (zi || !(i[5:3] == 3'b110 && (i[2:0] == 3'b001 || i[1]))); // addx/subx/cmpx/addsx/subsx/cmpsx logically AND the old z
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if (k > (n % 2 == 0 ? n * n / 2 : (n * n + 1) / 2)) { cout << NO << endl; return 0; } cout << YES << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (k && (i + j) % 2 == 0) { cout << L ; k--; } else { cout << S ; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int n, k, s; vector<long long int> v, ans; void build(const int &last, const int &i, const int &k, const bool &increasing) { if (!k) return; else if (last != v[i] and int(v.size()) - i == k) ans.push_back(v[i]), build(v[i], i + 1, k - 1, increasing); else if (last == v[i]) build(last, i + 1, k, increasing ^ 1); else ans.push_back(last + (increasing ? 1 : -1)), build(last + (increasing ? 1 : -1), i, k - 1, increasing); } int main() { scanf( %lld %lld %lld , &n, &k, &s); if (k * (n - 1) < s or k > s) return printf( %s n , NO ), 0; for (int i = 0; i < k and s > n - 1; ++i, s -= (n - 1)) v.push_back((i & 1) ? 1 : n); if (int(v.size()) & 1) v.push_back(n - s); else v.push_back(1 + s); build(1, 0, k, 1); printf( %s n , YES ); for (int i = 0; i < int(ans.size()); ++i) printf( %lld%c , ans[i], (i == int(ans.size()) - 1) ? n : ); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct point { long double x, y; }; point a1, a2, a3, a4, b1, b2, b3, b4, c; int l, r, u, d; bool corner(point b) { if (b.x <= r && b.x >= l && b.y <= u && b.y >= d) return true; else return false; } pair<long double, long double> line(point a, point b) { long double m, c; m = ((long double)b.y - a.y) / ((long double)b.x - a.x); c = a.y - m * a.x; return {m, c}; } point foot(pair<long double, long double> line) { point p; p.x = (line.first * (c.y + line.second) + c.x) / (1 + line.first * line.first); p.y = line.first * p.x + line.second; return p; } bool inside(point p, pair<long double, long double> l1, pair<long double, long double> l2) { int k = l1.first / l2.first; if (k == -1) { l1.first *= -1; l1.second *= -1; } if ((p.x * l1.first + l1.second - p.y) * (p.x * l2.first + l2.second - p.y) <= 0) return true; return false; } int main() { ios::sync_with_stdio(0); cin >> a1.x >> a1.y >> a2.x >> a2.y >> a3.x >> a3.y >> a4.x >> a4.y; c.x = (a1.x + a2.x + a3.x + a4.x) / 4; c.y = (a1.y + a2.y + a3.y + a4.y) / 4; l = min(min(a1.x, a2.x), a3.x); r = max(max(a1.x, a2.x), a3.x); d = min(min(a1.y, a2.y), a3.y); u = max(max(a1.y, a2.y), a3.y); cin >> b1.x >> b1.y >> b2.x >> b2.y >> b3.x >> b3.y >> b4.x >> b4.y; int flag = 0; if (corner(b1) || corner(b2) || corner(b3) || corner(b4)) flag = 1; pair<long double, long double> l1, l2, l3, l4; l1 = line(b1, b2); l2 = line(b2, b3); l3 = line(b3, b4); l4 = line(b4, b1); long double d = (r - l) / 2 * sqrt((long double)2); if ((inside(a1, l1, l3) && inside(a1, l2, l4)) || (inside(a2, l1, l3) && inside(a2, l2, l4)) || (inside(a3, l1, l3) && inside(a3, l2, l4)) || (inside(a4, l1, l3) && inside(a4, l2, l4)) || (inside(c, l1, l3) && inside(c, l2, l4))) flag = 1; if (flag) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, k, h = 0; cin >> n >> k; vector<int> v; for (int i = 0; i < n; i++) v.push_back(i); for (int ki = 1; ki <= k; ki++) { int x; cin >> x; x = x - (x / (n)) * (n); int d = (h + x) % n; h = d; if (d == n - 1) h = 0; n--; cout << v[d] + 1 << ; vector<int> tmp; for (int i = 0; i < v.size(); i++) if (i != d) tmp.push_back(v[i]); v = tmp; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_2_V
`define SKY130_FD_SC_LS__O2111AI_2_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111ai_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_2_V
|
#include <bits/stdc++.h> char str[100005], ans[100005]; int out[100005]; struct Edge { int link[400005], next[400005], son[400005], l; void clear() { l = 0; memset(son, 0, sizeof(son)); } void addedge(int x, int y) { link[++l] = y; next[l] = son[x]; son[x] = l; } }; Edge e; int top = 0; int main() { scanf( %s , str); int l = strlen(str); for (int i = l - 1; i >= 0; --i) e.addedge(str[i], i); for (char c = z ; c >= a ; --c) for (int p = e.son[c]; p; p = e.next[p]) if (top == 0 || e.link[p] > out[top]) out[++top] = e.link[p]; for (int i = 1; i <= top; ++i) ans[i - 1] = str[out[i]]; printf( %s n , ans); return 0; }
|
#include <algorithm> #include <iostream> #include <map> #include <vector> using namespace std; using LL = long long; #define mk make_pair const int MAX_N = 3E5 + 100; const int MAX_LOG_N = 18 + 1; int n, m; vector<int> G[MAX_N]; //================================= int log2Static[MAX_N]; void log2Init(int n) { int w = 1, j = 0; while (w <= n) { for (int i = w; i < 2 * w && i <= n; ++i) log2Static[i] = j; w *= 2; j += 1; } } int dep[MAX_N]; int anster[MAX_N][MAX_LOG_N]; void getAnster(int u, int fat) { dep[u] = dep[fat] + 1; anster[u][0] = fat; for (int i = 1; i <= log2Static[dep[u]]; ++i) { anster[u][i] = anster[anster[u][i - 1]][i - 1]; } for (int v : G[u]) { if (fat == v) continue; getAnster(v, u); } } int getLCA(int u, int v) { if (dep[u] < dep[v]) swap(u, v); while (dep[u] > dep[v]) { u = anster[u][log2Static[dep[u] - dep[v]]]; } if (u == v) return u; for (int i = log2Static[dep[u]]; i >= 0;) { if (anster[u][i] == anster[v][i]) { i -= 1; } else { u = anster[u][i]; v = anster[v][i]; } } return anster[u][0]; } //================================= class Path { public: int c, ui, vi; }; int curSon[MAX_N]; LL pathCnt[MAX_N]; Path path[MAX_N]; vector<int> lcaPath[MAX_N]; vector<int> sidePath[MAX_N]; LL ans; void dfs(int u, int fat) { for (int i : sidePath[u]) { if (!path[i].ui) path[i].ui = curSon[path[i].c]; else path[i].vi = curSon[path[i].c]; } for (int v : G[u]) { if (fat == v) continue; curSon[u] = v; dfs(v, u); pathCnt[u] += pathCnt[v]; } pathCnt[u] -= lcaPath[u].size(); LL tmp1 = 0; map<pair<int, int>, LL> tmp2; for (int i : lcaPath[u]) { int tmp = 0; tmp += pathCnt[path[i].ui] ? pathCnt[path[i].ui] - 1 : 0; tmp += pathCnt[path[i].vi] ? pathCnt[path[i].vi] - 1 : 0; tmp1 += pathCnt[u] - tmp - 1; //处理双重边情况 if (path[i].ui && path[i].vi) { tmp2[mk(path[i].ui, path[i].vi)] += 1; } } for (auto it : tmp2) { tmp1 += it.second * (it.second - 1); } //特殊处理 for (int i : lcaPath[u]) { if (path[i].ui) pathCnt[path[i].ui] -= 1; if (path[i].vi) pathCnt[path[i].vi] -= 1; } pathCnt[u] -= lcaPath[u].size(); //仅统计向上路径的 for (int i : lcaPath[u]) { tmp1 += pathCnt[u] - pathCnt[path[i].ui] - pathCnt[path[i].vi]; } ans += tmp1 / 2; } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } log2Init(n); getAnster(1, 0); // init cin >> m; for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; pathCnt[u] += 1; pathCnt[v] += 1; path[i].c = getLCA(u, v); if (path[i].c == u) u = 0; if (path[i].c == v) v = 0; if (u > v) swap(u, v); lcaPath[path[i].c].push_back(i); if (u) sidePath[u].push_back(i); if (v) sidePath[v].push_back(i); } dfs(1, 0); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; int a[maxn]; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); if (n > min(m, k)) printf( No n ); else printf( Yes n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; const int N = 100005; int n, m, k; vector<int> adj[N]; int cnt[N]; int mark[N]; int pass; int aux[N]; bool ta[N]; bool clique(int x) { pass++; mark[x] = pass; int id = 0; for (int i : adj[x]) if (!ta[i]) { mark[i] = pass; aux[id++] = i; } for (int i = 0; i < id; i++) { for (int j = i + 1; j < id; j++) { if (!binary_search(adj[aux[i]].begin(), adj[aux[i]].end(), aux[j])) return 0; } } return 1; } int main() { int t; scanf( %d , &t); while (t--) { scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { adj[i].clear(); cnt[i] = 0; ta[i] = 0; } for (int i = 0; i < m; i++) { int a, b; scanf( %d %d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); cnt[b]++; cnt[a]++; } for (int i = 1; i <= n; i++) { sort(adj[i].begin(), adj[i].end()); } priority_queue<ii> pq; for (int i = 1; i <= n; i++) { pq.push({-cnt[i], i}); } bool ok = 0; while (1) { if (pq.empty()) break; int c, x; tie(c, x) = pq.top(); c = -c; if (c != cnt[x]) { pq.pop(); continue; } if (c >= k) { vector<int> ans; while (!pq.empty()) { int c, x; tie(c, x) = pq.top(); c = -c; pq.pop(); if (c != cnt[x]) { continue; } ans.push_back(x); } printf( 1 %d n , (int)ans.size()); for (int i : ans) { printf( %d , i); } printf( n ); ok = 1; break; } pq.pop(); if (c == k - 1) { if (clique(x)) { printf( 2 n ); printf( %d , x); for (int i : adj[x]) if (!ta[i]) { printf( %d , i); } printf( n ); ok = 1; break; } } cnt[x] = 0; ta[x] = 1; for (int i : adj[x]) if (cnt[i]) { cnt[i]--; pq.push({-cnt[i], i}); } } if (!ok) { printf( -1 n ); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int tree[2000005] = {0}, num[500005] = {0}, dp[500005] = {1}; void modify(int index, int l, int r, int ql, int qr, int v) { if (ql <= l && qr >= r) { tree[index] = v; return; } int mid = (l + r) >> 1; if (ql <= mid && qr >= l) modify(index << 1, l, mid, ql, qr, v); if (ql <= r && qr >= mid + 1) modify(index << 1 | 1, mid + 1, r, ql, qr, v); tree[index] = max(tree[index << 1], tree[index << 1 | 1]); } int query(int index, int l, int r, int ql, int qr) { if (ql <= l && qr >= r) return tree[index]; int mid = (l + r) >> 1, ans = 0; if (ql <= mid && qr >= l) ans = max(ans, query(index << 1, l, mid, ql, qr)); if (ql <= r && qr >= mid + 1) ans = max(ans, query(index << 1 | 1, mid + 1, r, ql, qr)); return ans; } int main() { int i, n, k, d, index = 0; scanf( %d%d%d , &n, &k, &d); for (i = 1; i <= n; i++) scanf( %d , &num[i]); sort(num + 1, num + n + 1); modify(1, 0, n, 0, 0, 1); for (i = 1; i <= n; i++) { while (num[i] > num[index] + d) index++; if (i - k >= index - 1) dp[i] = query(1, 0, n, index - 1, i - k); else dp[i] = 0; modify(1, 0, n, i, i, dp[i]); } if (dp[n]) puts( YES ); else puts( NO ); }
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module decodes video streams from the Terasic CCD cameras. *
* *
******************************************************************************/
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41AI_4_V
`define SKY130_FD_SC_HS__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41AI_4_V
|
#include <bits/stdc++.h> using namespace std; map<pair<long long, long long>, long long> mp; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; for (long long i = 0; i < m; i++) { long long a, b; cin >> a >> b; a--; b--; mp[{a, b}] = 1; mp[{b, a}] = 1; } if (n < 7) { cout << m << endl; } else { long long ans = m; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { long long ctr = 0; for (long long k = 0; k < n; k++) { if (mp[{i, k}] == 1 and mp[{j, k}]) { ctr++; } } ans = min(ans, ctr); } } cout << m - ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1 << 28; const long long LINF = 1ll << 61; inline long long getnum() { register long long r = 0; register bool ng = 0; register char c; c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); if (c == - ) ng = 1, c = getchar(); while (c != && c != n ) r = r * 10 + c - 0 , c = getchar(); if (ng) r = -r; return r; } template <class T> inline void putnum(T x) { if (x < 0) putchar( - ), x = -x; register short a[20] = {}, sz = 0; while (x > 0) a[sz++] = x % 10, x /= 10; if (sz == 0) putchar( 0 ); for (int i = sz - 1; i >= 0; i--) putchar( 0 + a[i]); } inline void putsp() { putchar( ); } inline void putendl() { putchar( n ); } inline char mygetchar() { register char c = getchar(); while (c == || c == n ) c = getchar(); return c; } const int dx[] = {1, -1, 0, 0}; const int dy[] = {0, 0, 1, -1}; const int maxn = 1700; int w, h, c[maxn][maxn], ans[12345]; bool g[maxn][maxn], ng[2][maxn][maxn], vis[maxn][maxn], p; void color(int x, int y, int id) { c[x][y] = id; for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (nx > 0 && nx <= w && ny > 0 && ny <= h && g[nx][ny] && c[nx][ny] == 0) { color(nx, ny, id); } } } void dfs(int x, int y) { vis[x][y] = 1; for (int i = 0; i < 4; i++) { int nx = x + dx[i], ny = y + dy[i]; if (nx > 0 && nx <= w && ny > 0 && ny <= h && g[nx][ny] && !vis[nx][ny]) { dfs(nx, ny); } } } void getsmaller() { p ^= 1; for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { ng[p][i][j] = ng[p ^ 1][i][j]; for (int k = 0; k < 4; k++) { if (!ng[p ^ 1][i + dx[k]][j + dy[k]]) { ng[p][i][j] = 0; } } } } } void getbigger() { p ^= 1; for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { ng[p][i][j] = ng[p ^ 1][i][j]; for (int k = 0; k < 4; k++) { if (ng[p ^ 1][i + dx[k]][j + dy[k]]) { ng[p][i][j] = 1; } } } } } void see() { for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { putnum(g[i][j] & (!vis[i][j])), putsp(); } putendl(); } putendl(); } int main() { w = getnum(), h = getnum(); for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { g[i][j] = getnum(); } } int id = 0; for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { if (g[i][j] && c[i][j] == 0) { id++; color(i, j, id); } } } for (int i = 1; i <= w; i++) for (int j = 1; j <= h; j++) ng[p][i][j] = g[i][j]; getsmaller(); getsmaller(); getsmaller(); getbigger(); getbigger(); getbigger(); getbigger(); getbigger(); for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { g[i][j] &= !ng[p][i][j]; } } for (int i = 1; i <= w; i++) for (int j = 1; j <= h; j++) ng[p][i][j] = g[i][j]; getsmaller(); getbigger(); for (int i = 1; i <= w; i++) for (int j = 1; j <= h; j++) g[i][j] = ng[p][i][j]; for (int i = 1; i <= w; i++) { for (int j = 1; j <= h; j++) { if (g[i][j] && !vis[i][j]) { ans[c[i][j]]++; dfs(i, j); } } } sort(ans + 1, ans + id + 1); putnum(id), putsp(), putendl(); for (int i = 1; i <= id; i++) putnum(ans[i]), putsp(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int max_n = 1000, max_k = 100; int dp[max_n][max_k]; int p[max_n + 5]; int main() { int n, k, mod; cin >> n >> k >> mod; p[0] = 10 % k; for (int i = 0; i < n; i++) p[i + 1] = p[i] * 10 % k; memset(dp, 0, sizeof dp); for (int dig = 1; dig < 10; dig++) dp[0][dig % k] = (1 + dp[0][dig % k]) % mod; for (int i = 0; i < n - 1; i++) for (int dig = (i + 1 == n - 1); dig < 10; dig++) { if (dig) { int newr = dig * p[i] % k; dp[i + 1][newr] = (1 + dp[i + 1][newr]) % mod; } for (int r = 0; r < k; r++) { int newr = r ? (dig * p[i] + r) % k : 0; dp[i + 1][newr] = (dp[i][r] + dp[i + 1][newr]) % mod; } } cout << dp[n - 1][0] << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
string s;
integer cyc = 0;
// Check constification
initial begin
s="1234"; `checkh(s.len(),4);
s="ab7CD"; `checks(s.toupper(), "AB7CD");
s="ab7CD"; `checks(s.tolower(), "ab7cd");
s="1234"; s.putc(-1, "z"); `checks(s, "1234");
s="1234"; s.putc(4, "z"); `checks(s, "1234");
s="1234"; s.putc(2, 0); `checks(s, "1234");
s="1234"; s.putc(2, "z"); `checks(s, "12z4");
s="1234"; `checkh(s.getc(-1), 0);
s="1234"; `checkh(s.getc(4), 0);
s="1234"; `checkh(s.getc(2), "3");
s="b"; if (s.compare("a") <= 0) $stop;
s="b"; if (s.compare("b") != 0) $stop;
s="b"; if (s.compare("c") >= 0) $stop;
s="b"; if (s.compare("A") <= 0) $stop;
s="b"; if (s.compare("B") <= 0) $stop;
s="b"; if (s.compare("C") <= 0) $stop;
s="B"; if (s.compare("a") >= 0) $stop;
s="B"; if (s.compare("b") >= 0) $stop;
s="B"; if (s.compare("c") >= 0) $stop;
s="b"; if (s.icompare("A") < 0) $stop;
s="b"; if (s.icompare("B") != 0) $stop;
s="b"; if (s.icompare("C") >= 0) $stop;
s="abcd"; `checks(s.substr(-1,1), "");
s="abcd"; `checks(s.substr(1,0), "");
s="abcd"; `checks(s.substr(1,4), "");
s="abcd"; `checks(s.substr(2,3), "cd");
s="101"; `checkh(s.atoi(), 'd101);
s="101"; `checkh(s.atohex(), 'h101);
s="101"; `checkh(s.atooct(), 'o101);
s="101"; `checkh(s.atobin(), 'b101);
s="1.23"; `checkg(s.atoreal(), 1.23);
s.itoa(123); `checks(s, "123");
s.hextoa(123); `checks(s, "7b");
s.octtoa(123); `checks(s, "173");
s.bintoa(123); `checks(s, "");
s.realtoa(1.23); `checks(s, "1.23");
s = "bAr";
s = s.toupper; `checks(s, "BAR");
s = s.tolower; `checks(s, "bar");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
s = "1234";
end
else if (cyc==1) begin
`checkh(s.len(),4);
end
else if (cyc==2) begin
s.putc(-1, "z");
end
else if (cyc==3) begin
`checks(s, "1234");
s.putc(4, "z");
end
else if (cyc==4) begin
`checks(s, "1234");
s.putc(2, 0);
end
else if (cyc==5) begin
`checks(s, "1234");
s.putc(2, "z");
end
else if (cyc==6) begin
`checks(s, "12z4");
end
else if (cyc==7) begin
`checkh(s.getc(-1), 0);
`checkh(s.getc(4), 0);
`checkh(s.getc(2), "z");
s="ab3CD";
end
else if (cyc==8) begin
`checks(s.toupper(), "AB3CD");
`checks(s.tolower(), "ab3cd");
s="b";
end
else if (cyc==9) begin
if (s.compare("a") <= 0) $stop;
if (s.compare("b") != 0) $stop;
if (s.compare("c") >= 0) $stop;
if (s.compare("A") <= 0) $stop;
if (s.compare("B") <= 0) $stop;
if (s.compare("C") <= 0) $stop;
if (s.icompare("A") < 0) $stop;
if (s.icompare("B") != 0) $stop;
if (s.icompare("C") >= 0) $stop;
s="abcd";
end
else if (cyc==10) begin
`checks(s.substr(-1,1), "");
`checks(s.substr(1,0), "");
`checks(s.substr(1,4), "");
`checks(s.substr(2,3), "cd");
s="101";
end
else if (cyc==11) begin
`checkh(s.atoi(), 'd101);
`checkh(s.atohex(), 'h101);
`checkh(s.atooct(), 'o101);
`checkh(s.atobin(), 'b101);
s="1.23";
end
else if (cyc==12) begin
`checkg(s.atoreal(), 1.23);
end
else if (cyc==13) begin
s.itoa(123);
end
else if (cyc==14) begin
`checks(s, "123");
s.hextoa(123);
end
else if (cyc==15) begin
`checks(s, "7b");
s.octtoa(123);
end
else if (cyc==16) begin
`checks(s, "173");
s.bintoa(123);
end
else if (cyc==17) begin
`checks(s, "");
s.realtoa(1.23);
end
else if (cyc==18) begin
`checks(s, "1.23");
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int t, n; char s[505050]; int a[1 << 20], b[1 << 20]; const int L = 20, FN = (1 << L); int rev[FN]; const long double pi = 3.1415926535897932384626433832795028841971l; const long double two_pi = pi * 2; struct cp { long double x, y; cp() {} cp(long double _x) : x(_x), y(0) {} cp(long double _x, long double _y) : x(_x), y(_y) {} inline cp operator+(const cp &p) const { return cp(x + p.x, y + p.y); } inline cp operator-(const cp &p) const { return cp(x - p.x, y - p.y); } inline cp operator*(const cp &p) const { return cp(x * p.x - y * p.y, x * p.y + y * p.x); } inline cp operator!() const { return cp(x, -y); } } nw[FN + 1], f[FN], g[FN], h[FN]; void init() { rev[0] = 0; for (int i = 1; i < FN; i++) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (L - 1)); nw[0] = nw[FN] = cp(1, 0); for (int i = 1; i <= (FN >> 1); i++) nw[i] = cp(cos(i * two_pi / FN), sin(i * two_pi / FN)); for (int i = (FN >> 1) + 1; i < FN; i++) nw[i] = !nw[FN - i]; } void dft(cp *a, int n, int fg) { int d = __builtin_ctz(FN / n); for (int i = 0; i < n; i++) if (i < (rev[i] >> d)) swap(a[i], a[rev[i] >> d]); for (int size = 2; size <= n; size <<= 1) { int step = FN / size; if (fg) step = -step; for (int i = 0; i < n; i += size) { cp *u = a + i, *v = a + (i + (size >> 1)), *w = fg ? nw + FN : nw; for (int k = (size >> 1); k--;) { cp tmp = (*v) * (*w); *v = *u - tmp, *u = *u + tmp; u++, v++, w += step; } } } if (fg) for (int i = 0; i < n; i++) a[i].x /= n, a[i].y /= n; } void func(int *a, int *b, int *c, int n) { for (int i = 0; i < n; i++) { f[i] = cp((long double)a[i]); g[i] = cp((long double)b[i]); } dft(f, n, 0); dft(g, n, 0); for (int i = 0; i < n; i++) h[i] = f[i] * g[i]; dft(h, n, 1); for (int i = 0; i < n; i++) c[i] = int(h[i].x + 0.5); } bool chk(int d) { for (int i = d; i < n; i += d) if (a[n + i] || a[n - i]) return false; return true; } int ans[505050]; int main() { init(); scanf( %d , &t); while (t--) { scanf( %d%s , &n, s); int m = 1 << (33 - __builtin_clz(n - 1)); assert(m >= 2 * n); for (int i = 0; i < m; i++) a[i] = b[i] = 0; for (int i = 0; i < n; i++) { if (s[i] == V ) a[i] = 1; else if (s[i] == K ) b[n - i] = 1; } func(a, b, a, m); int cnt = 0; for (int i = 1; i <= n; i++) ans[i] = chk(i), cnt += ans[i]; cout << cnt << endl; for (int i = 1; i <= n; i++) if (ans[i]) printf( %d , i); puts( ); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Test:
tri t;
bufif1 (t, crc[1], cyc[1:0]==2'b00);
bufif1 (t, crc[2], cyc[1:0]==2'b10);
tri0 t0;
bufif1 (t0, crc[1], cyc[1:0]==2'b00);
bufif1 (t0, crc[2], cyc[1:0]==2'b10);
tri1 t1;
bufif1 (t1, crc[1], cyc[1:0]==2'b00);
bufif1 (t1, crc[2], cyc[1:0]==2'b10);
tri t2;
t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t2, crc[2], cyc[1:0]==2'b10);
tri t3;
t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00));
bufif1 (t3, crc[2], cyc[1:0]==2'b10);
wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h04f91df71371e950
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t_tri2 (/*AUTOARG*/
// Outputs
t2,
// Inputs
d, oe
);
output t2;
input d;
input oe;
tri1 t2;
bufif1 (t2, d, oe);
endmodule
module t_tri3 (/*AUTOARG*/
// Outputs
t3,
// Inputs
d, oe
);
output tri1 t3;
input d;
input oe;
bufif1 (t3, d, oe);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; template <class T> using vec = std::vector<T>; bool __hack = std::ios::sync_with_stdio(false); auto __hack1 = cin.tie(nullptr); struct Input { Input(istream &in) : in(&in) {} template <class T> T next() const { T x; *in >> x; return x; } int ni() const { return next<int>(); } istream *in; }; Input in(cin); class Output { private: ostream *out; template <typename T> void printSingle(const T &value) { *out << value; } public: Output(ostream &out) : out(&out) {} inline void setPrecision(int d) { *out << fixed << setprecision(d); } inline void print() {} template <typename T, typename... Ts> inline void print(const T &f, const Ts &...args) { printSingle(f); if (sizeof...(args) != 0) { *out << ; print(args...); } } template <typename... Ts> inline void println(const Ts &...args) { print(args...); (*out) << n ; } template <typename... Ts> inline void operator()(const Ts &...args) { println(args...); } }; Output out(cout); namespace template_util { constexpr int bytecount(uint64_t x) { return x ? 1 + bytecount(x >> 8) : 0; } template <int N> struct bytetype {}; template <uint64_t N> struct minimal_uint : bytetype<bytecount(N)> {}; } // namespace template_util double EPS = 1e-10; bool doubleEqual(double a, double b) { return fabs(a - b) < EPS; } void solveOne() { auto n = in.ni(); auto len = in.ni(); vec<int> a(n + 2); a[0] = 0; a[n + 1] = len; for (int i = (1); i <= (n); ++i) a[i] = in.ni(); int i = 0, j = n + 1; double t = 0; int s1 = 1, s2 = 1; double x1 = 0, x2 = len; out.setPrecision(15); while (i + 1 < j) { double d1 = a[i + 1] - x1; double t1 = d1 / s1; double d2 = x2 - a[j - 1]; double t2 = d2 / s2; if (doubleEqual(t1, t2)) { t += t1; ++s1; ++s2; ++i; --j; x1 = a[i]; x2 = a[j]; if (i == j) { out(t); return; } } else if (t1 < t2) { t += t1; ++s1; ++i; x1 = a[i]; x2 -= t1 * s2; } else { t += t2; ++s2; --j; x2 = a[j]; x1 += t2 * s1; } } double d = x2 - x1; double s = s1 + s2; t += d / s; out(t); } void solve(istream &inStream, ostream &outStream) { in = Input(inStream); out = Output(outStream); auto tests = in.ni(); while (tests--) { solveOne(); } } int main() { solve(cin, cout); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string str[n]; for (int i = 0; i < n; i++) cin >> str[i]; int brr[m]; for (int i = 0; i < m; i++) cin >> brr[i]; int count = 0; for (int i = 0; i < m; i++) { int arr[5] = {0}; for (int j = 0; j < n; j++) { arr[str[j][i] - A ]++; } int k = *max_element(arr, arr + 5); count += k * brr[i]; } cout << count; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void printArray(T arr, int l) { for (int i = 0; i < l; i++) cout << arr[i] << ; cout << endl; } int main(void) { int n, k; cin >> n >> k; vector<int> floors; for (int i = 0; i < n; i++) { int temp; cin >> temp; floors.push_back(temp); } sort(floors.begin(), floors.end(), greater<int>()); int done = 0; long long int cost = 0; while (done < n) { cost += 2 * (floors[done] - 1); done += k; } cout << cost << endl; return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:39 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_stub.v
// Design : system_clk_wiz_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_1_0(clk_out1, clk_out2, clk_out3, clk_out4, resetn,
locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,resetn,locked,clk_in1" */;
output clk_out1;
output clk_out2;
output clk_out3;
output clk_out4;
input resetn;
output locked;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; class matrix { public: int row, col; std::vector<std::vector<int>> num; matrix(int row, int col, int defaultValue = 0) { this->num = std::vector<std::vector<int>>(row, std::vector<int>(col, defaultValue)); this->row = row; this->col = col; } matrix(std::vector<std::vector<int>> num) { this->num = num; this->row = this->num.size(); this->col = this->num[0].size(); } matrix operator*(matrix &another) { if (this->col != another.row) { printf( Wrong size: %d*%d X %d*%d n , this->row, this->col, another.row, another.col); throw Wrong size ; } matrix newone(this->row, another.col); for (int r = 0; r < newone.row; r++) { for (int c = 0; c < newone.col; c++) { for (int k = 0; k < this->col; k++) { newone.num[r][c] += 1ll * this->num[r][k] * another.num[k][c] % (mod - 1); newone.num[r][c] %= mod - 1; } } } return newone; } matrix operator^(long long x) { if (x == 0) { printf( Not implemented yet. n ); throw Not implemented ; } else if (x == 1) { return *this; } else { matrix halfpower = (*this) ^ (x / 2); if (x % 2 == 0) return halfpower * halfpower; else return halfpower * halfpower * (*this); } } }; std::vector<int> primeDecomposition(int x) { std::vector<int> answer; for (int i = 2; i * i <= x; i++) { if (x % i == 0) { answer.push_back(i); while (x % i == 0) x /= i; } } if (x > 1) answer.push_back(x); return answer; } int power(int a, long long b) { if (b == 0) return 1; int half = power(a, b / 2); if (b % 2 == 0) return 1ll * half * half % mod; else return 1ll * half * half % mod * a % mod; } int main() { long long n; int f[4], c, answer(1); scanf( %lld%d%d%d%d , &n, &f[1], &f[2], &f[3], &c); matrix baseMatrix({{1, 1, 1}, {1, 0, 0}, {0, 1, 0}}); baseMatrix = baseMatrix ^ (n - 3); std::set<int> primeSet; for (int t : primeDecomposition(c)) primeSet.insert(t); for (int i = 1; i <= 3; i++) for (int t : primeDecomposition(f[i])) primeSet.insert(t); for (int t : primeSet) { matrix countMatrix(3, 1); for (int i = 0; i < 3; i++) { for (int k = f[i + 1]; k % t == 0; k /= t) countMatrix.num[3 - i - 1][0]++; for (int k = c; k % t == 0; k /= t) countMatrix.num[3 - i - 1][0] += i + 1; } countMatrix = baseMatrix * countMatrix; answer = 1ll * answer * power(t, countMatrix.num[0][0]) % mod; } answer = 1ll * answer * power(power(c, mod - 2), n) % mod; printf( %d n , answer); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { char dir; cin >> dir; string m; cin >> m; string kboard = qwertyuiopasdfghjkl;zxcvbnm,./ ; if (dir == R ) { for (int i = 0; i < m.length(); i++) { int index = kboard.find(m[i]); cout << kboard[index - 1]; } cout << endl; } else { for (int i = 0; i < m.length(); i++) { int index = kboard.find(m[i]); cout << kboard[index + 1]; } cout << endl; } return 0; }
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_instance_index = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_ir_width = 2,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_mfg_id = 70,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_action = "",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_n_scan = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_total_length = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_type_id = 34,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_FUNCTIONAL_PP_V
|
`timescale 1ps/1ps
module tb_gcd8;
parameter DELAY = 1;
parameter NUM_DATA = 6;
parameter [7:0] x_data [0:NUM_DATA-1] = {13, 5, 12, 16, 1, 4};
parameter [7:0] y_data [0:NUM_DATA-1] = {5, 13, 16, 12, 4, 1};
integer counter;
reg activate_0r; wire activate_0a;
reg x_0a; wire x_0r; reg [7:0] x_0d;
reg y_0a; wire y_0r; reg [7:0] y_0d;
reg z_0a; wire z_0r; wire [7:0] z_0d;
reg initialise;
Balsa_gcd8 (
.activate_0r(activate_0r), .activate_0a(activate_0a),
.x_0a(x_0a), .x_0r(x_0r), .x_0d(x_0d),
.y_0a(y_0a), .y_0r(y_0r), .y_0d(y_0d),
.z_0a(z_0a), .z_0r(z_0r), .z_0d(z_0d),
.initialise(initialise)
);
always@(posedge z_0r) begin
if (activate_0r) begin
$display("gcd(%d, %d) = %d", x_0d, y_0d, z_0d);
end
end
always@(x_0r) begin
if (x_0r) begin
#DELAY x_0d = x_data[counter];
end
#DELAY x_0a = x_0r;
end
always@(y_0r) begin
if (y_0r) begin
#DELAY y_0d = y_data[counter];
end
#DELAY y_0a = y_0r;
end
always@(z_0r) begin
#DELAY
z_0a = z_0r;
if (activate_0r && !z_0r) begin
counter = counter + 1;
if (counter >= NUM_DATA) begin
$finish;
end
end
end
initial begin
counter = 0;
x_0d = 0;
y_0d = 0;
x_0a = 0;
y_0a = 0;
z_0a = 0;
activate_0r = 0;
initialise = 1;
#DELAY initialise = 0;
#DELAY activate_0r = 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_TB_V
`define SKY130_FD_SC_HS__EDFXTP_TB_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxtp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 DE = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 DE = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 DE = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 DE = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__edfxtp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_TB_V
|
#include <bits/stdc++.h> using namespace std; void Read(int &p) { p = 0; char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) ; for (; c >= 0 && c <= 9 ; c = getchar()) p = p * 10 + c - 0 ; } int n, k; struct Node { long long siz; int mxx[12], mnn[12]; bool operator<(const Node &b) const { for (int i = 1; i <= k; i++) if (mxx[i] > b.mnn[i]) return 0; return 1; } } S; set<Node> M; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) { S.siz = 1; for (int j = 1; j <= k; j++) { int x; Read(x); S.mnn[j] = S.mxx[j] = x; } set<Node>::iterator it = M.find(S); while (it != M.end()) { S.siz += it->siz; for (int j = 1; j <= k; j++) { S.mxx[j] = max(S.mxx[j], it->mxx[j]); S.mnn[j] = min(S.mnn[j], it->mnn[j]); } M.erase(it); it = M.find(S); } M.insert(S); printf( %lld n , M.rbegin()->siz); } }
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; int x[N], y[N], c[N], k[N], f[N]; int s[N], st, tu[N], tv[N]; struct node { int u, v; long long s; bool operator<(const node &p) const { return s < p.s; } } d[N * N + N]; int dis(int a, int b) { return abs(x[a] - x[b]) + abs(y[a] - y[b]); } int fd(int x) { if (f[x] == x) return x; return f[x] = fd(f[x]); } void mg(int x, int y) { int fa = fd(x), fb = fd(y); f[fa] = fb; } int main() { int n, p = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); for (int i = 1; i <= n; i++) { scanf( %d , &c[i]); f[i] = i; d[++p].s = c[i]; d[p].u = i; d[p].v = n + 1; } for (int i = 1; i <= n; i++) scanf( %d , &k[i]); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) d[++p].s = 1ll * dis(i, j) * (k[i] + k[j]), d[p].u = i, d[p].v = j; sort(d + 1, d + p + 1); int cnt = 0; long long ans = 0; for (int i = 1; i <= p; i++) { if (fd(d[i].u) == fd(d[i].v)) continue; if (d[i].v == n + 1) s[++s[0]] = d[i].u; else { st++; tu[st] = d[i].u; tv[st] = d[i].v; } mg(d[i].u, d[i].v); ans += d[i].s; cnt++; if (cnt == n) break; } printf( %lld n , ans); printf( %d n , s[0]); for (int i = 1; i <= s[0]; i++) printf( %d , s[i]); puts( ); printf( %d n , st); for (int i = 1; i <= st; i++) printf( %d %d n , tu[i], tv[i]); return 0; }
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; char str[1000010]; long long cntu[1000010]; long long cntd[1000010]; long long sumu[1000010]; long long sumd[1000010]; long long CNTU; long long CNTD; int main() { scanf( %I64d%s , &n, str + 1); for (long long i = 1; i <= n; i++) { cntu[i] = cntu[i - 1]; cntd[i] = cntd[i - 1]; sumu[i] = sumu[i - 1]; sumd[i] = sumd[i - 1]; if (str[i] == U ) { CNTU++; cntu[i]++; sumu[i] += i; } else { CNTD++; cntd[i]++; sumd[i] += i; } } for (long long i = 1; i <= n; i++) if (str[i] == U ) { if (cntu[i - 1] >= CNTD - cntd[i]) { long long k = upper_bound(cntu + 1, cntu + n + 1, cntu[i - 1] - CNTD + cntd[i]) - cntu; printf( %I64d , (-(sumu[i - 1] - sumu[k - 1]) + (sumd[n] - sumd[i])) * 2 + n - i + 1); } else { long long k = lower_bound(cntd + 1, cntd + n + 1, cntd[i] + cntu[i - 1] + 1) - cntd; printf( %I64d , (-sumu[i - 1] + (sumd[k] - sumd[i]) - i) * 2 + i); } } else { if (cntu[i - 1] <= CNTD - cntd[i]) { long long k = lower_bound(cntd + i, cntd + n + 1, cntd[i] + cntu[i - 1]) - cntd; printf( %I64d , (-sumu[i - 1] + (sumd[k] - sumd[i])) * 2 + i); } else { long long k = upper_bound(cntu + 1, cntu + n + 1, cntu[i - 1] - CNTD + cntd[i] - 1) - cntu; printf( %I64d , (i - (sumu[i - 1] - sumu[k - 1]) + (sumd[n] - sumd[i])) * 2 + n - i + 1); } } return 0; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.