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#include <bits/stdc++.h> using namespace std; long long int n, k, p[100005]; long long int dp[100005]; long long int f(long long int s) { if (dp[s] != -1) return dp[s]; if (p[s] == 0) { long long int lo = max(0LL, s - k - 1); long long int hi = min(n, s + k); return dp[s] = max(0LL, hi - lo); } long long int lo = max(p[s] + k, max(0LL, s - k - 1)); long long int hi = min(n, s + k); dp[s] = f(p[s]) + max(0LL, hi - lo); return dp[s]; } int main() { cin >> n >> k; for (long long int i = 1; i <= n; i++) cin >> p[i]; memset(dp, -1, sizeof(dp)); for (long long int i = 1; i <= n; i++) if (dp[i] == -1) f(i); for (long long int i = 1; i <= n; i++) cout << dp[i] << ; }
|
#include <bits/stdc++.h> using namespace std; const int L = 1000 + 10; int b[L]; int w, m, l = 0; int main() { cin >> w >> m; if (w > 3) while (m) { int q = m % w; m /= w; if (q > 1 && q < w - 1) { cout << NO << endl; return 0; } if (q == w - 1) m++; } cout << YES << endl; return 0; }
|
module signalinput(
input [1:0] testmode, // 00, 01, 10, 11 分别代表4种频率,
// 分别为 3125, 250, 50, 12500Hz, 使用 SW1~SW0 来控制
input sysclk, // 系统时钟100M
output sigin1 // 输出待测信号
);
reg [20:0] state;
reg [20:0] divide;
reg sigin;
assign sigin1 = sigin;
initial
begin
sigin = 0;
state = 21'b000000000000000000000;
divide = 21'b0_0000_0111_1101_0000_0000;
end
always @(testmode)
begin
case(testmode[1:0])
2'b00: divide = 21'b0_0000_0111_1101_0000_0000; // 3125Hz, 分频比为32000
2'b01: divide = 21'b0_0000_0011_1110_1000_0000; // 6250Hz, 分频比为16000
2'b10: divide = 21'b1_1110_1000_0100_1000_0000; // 50Hz, 分频比为2000000
2'b11: divide = 21'b0_0000_0001_1111_0100_0000; // 12500Hz, 分频比为8000
endcase
end
always @(posedge sysclk) // 按divide分频
begin
if(state == 0)
sigin = ~sigin;
state = state + 21'd2;
if(state == divide)
state = 0;
end
endmodule
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#include <bits/stdc++.h> using namespace ::std; const long double PI = acos(-1); const long long MOD = 1000000000 + 7; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long add(long long a, long long b, long long m = MOD) { if (a >= m) a %= m; if (b >= m) b %= m; if (a < 0) a += m; if (b < 0) b += m; long long res = a + b; if (res >= m or res <= -m) res %= m; if (res < 0) res += m; return res; } long long mul(long long a, long long b, long long m = MOD) { if (a >= m) a %= m; if (b >= m) b %= m; if (a < 0) a += m; if (b < 0) b += m; long long res = a * b; if (res >= m or res <= -m) res %= m; if (res < 0) res += m; return res; } long long pow_mod(long long a, long long b, long long m = MOD) { long long res = 1LL; a = a % m; while (b) { if (b & 1) res = mul(res, a, m); b >>= 1; a = mul(a, a, m); } return res; } long long fastexp(long long a, long long b) { long long res = 1LL; while (b) { if (b & 1) res = res * a; b >>= 1; a *= a; } return res; } int gcdExtendido(int a, int b, int *x, int *y) { if (a == 0) { *x = 0; *y = 1; return b; } int x1, y1; int gcd = gcdExtendido(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } int modInverso(int a, int m) { int x, y; int g = gcdExtendido(a, m, &x, &y); if (g != 1) return -1; else return (x % m + m) % m; } const int N = 300000 + 5; const int L = 30; const int SUML = 300000 * 30 + 5; const int E = 2; int n; int a[N]; int nodes = 1; int frec[SUML]; int trie[SUML][E]; void insert(int x) { int pos = 0; for (int i = L - 1; i >= 0; i--) { int nxt = (x >> i) & 1; if (trie[pos][nxt] == 0) { trie[pos][nxt] = nodes++; } pos = trie[pos][nxt]; frec[pos] += 1; } } void erase(int val) { int pos = 0; for (int i = L - 1; i >= 0; i--) { int nxt = (val >> i) & 1; pos = trie[pos][nxt]; frec[pos] -= 1; } } int getMin(int x) { int ans = 0; int pos = 0; for (int i = L - 1; i >= 0; i--) { int have = (x >> i) & 1; int nxt = have; if (frec[trie[pos][nxt]] == 0) nxt ^= 1; ans |= (nxt ^ have) << i; pos = trie[pos][nxt]; } return ans; } int main() { scanf( %d , &(n)); for (int i = 1; i <= n; i++) scanf( %d , &(a[i])); for (int i = 1; i <= n; i++) { int x; scanf( %d , &(x)); insert(x); } for (int i = 1; i <= n; i++) { int cur = getMin(a[i]); erase(cur ^ a[i]); printf( %d%c , cur, n [i == n]); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int Maxl = 26; const int Maxn = 30005; const int Maxstr = 200005; const int Inf = 2000000007; char str[Maxstr]; int t; int n, m, k; int freq[Maxl]; bool dp[Maxn]; int res; int main() { scanf( %d , &t); while (t--) { scanf( %d %d %d , &n, &m, &k); scanf( %s , str); fill(freq, freq + Maxl, 0); for (int i = 0; i < k; i++) freq[str[i] - A ]++; res = Inf; int mx = max(n, m); for (int i = 0; i < Maxl; i++) { int tot = 0; for (int j = 0; j < Maxl; j++) if (j != i) tot += freq[j]; int mn = tot; fill(dp, dp + mx + 1, false); dp[0] = true; for (int j = 0; j < Maxl; j++) if (j != i) for (int l = mx; l >= 0; l--) if (dp[l]) if (l + freq[j] > mx) mn = min(mn, l + freq[j]); else dp[l + freq[j]] = true; for (int l = 0; l <= mx; l++) if (dp[l]) { int a = l, b = tot - l; int mya = max(0, n - a), myb = max(0, m - b); if (mya + myb <= freq[i]) res = min(res, mya * myb); mya = max(0, n - b), myb = max(0, m - a); if (mya + myb <= freq[i]) res = min(res, mya * myb); } int a = mn, b = tot - mn; int mya = max(0, n - a), myb = max(0, m - b); if (mya + myb <= freq[i]) res = min(res, mya * myb); mya = max(0, n - b), myb = max(0, m - a); if (mya + myb <= freq[i]) res = min(res, mya * myb); } printf( %d n , res); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND4_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_SYMBOL_V
|
// ==========================================================================
// CRC Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// ==========================================================================
module sd_crc_7(BITVAL, ENABLE, BITSTRB, CLEAR, CRC);
input BITVAL; // Next input bit
input ENABLE; // Enable calculation
input BITSTRB; // Current bit valid (Clock)
input CLEAR; // Init CRC value
output [6:0] CRC; // Current output CRC value
reg [6:0] CRC; // We need output registers
wire inv;
assign inv = BITVAL ^ CRC[6]; // XOR required?
always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC <= 0; // Init before calculation
end
else begin
if (ENABLE == 1) begin
CRC[6] <= CRC[5];
CRC[5] <= CRC[4];
CRC[4] <= CRC[3];
CRC[3] <= CRC[2] ^ inv;
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int NMax = 100005; const int sqrNMax = 330; int N; int Nb[NMax][sqrNMax + 5]; int A[NMax], B[sqrNMax + 5][2 * sqrNMax + 5], Start[sqrNMax + 5], Block[NMax], totalB, Size[sqrNMax + 5]; void Read() { scanf( %d , &N); for (int i = 1; i <= N; i++) scanf( %d , &A[i]); } void buildB() { int currentBlock = 1, cnt = 0; Start[1] = 1; for (int i = 1; i <= N; i++) { ++cnt; if (cnt == sqrNMax) { ++currentBlock; Start[currentBlock] = i; cnt = 1; } ++Size[currentBlock]; B[currentBlock][cnt] = A[i]; Nb[A[i]][currentBlock]++; Block[i] = currentBlock; } totalB = currentBlock; } int findBlock(int pos) { int sum = 0; for (int i = 1; i <= totalB; i++) { if (sum + Size[i] >= pos) { Start[i] = sum + 1; return i; } sum += Size[i]; } } int deleteElem(int block, int pos) { int p = pos - Start[block] + 1; int res = B[block][p]; Nb[res][block]--; for (int j = p; j < Size[block]; j++) swap(B[block][j], B[block][j + 1]); --Size[block]; return res; } void addElem(int block, int pos, int val) { int p = pos - Start[block] + 1; Nb[val][block]++; B[block][++Size[block]] = val; for (int j = Size[block] - 1; j >= p; j--) swap(B[block][j], B[block][j + 1]); } void makeCircularPerm(int left, int right) { int b = findBlock(right); int val = deleteElem(b, right); b = findBlock(left); addElem(b, left, val); } void buildA() { int cnt = 0; for (int i = 1; i <= totalB; i++) { for (int j = 1; j <= Size[i]; j++) A[++cnt] = B[i][j]; } } void initialize() { for (int i = 1; i <= totalB; i++) { for (int j = 1; j <= Size[i]; j++) Nb[B[i][j]][i] = 0; Size[i] = 0; Start[i] = 0; } } inline int decode(int nb, int lastans) { return (nb + lastans - 1) % N + 1; } int Query(int left, int right, int val) { int ans = 0, b = findBlock(left), b2 = findBlock(right); for (int i = b + 1; i < b2; i++) ans += Nb[val][i]; int l = left - Start[b] + 1, r = right - Start[b2] + 1; if (b == b2) { for (int j = l; j <= r; j++) if (B[b][j] == val) ++ans; return ans; } for (int j = l; j <= Size[b]; j++) if (B[b][j] == val) ans++; for (int j = 1; j <= r; j++) if (B[b2][j] == val) ++ans; return ans; } void Solve() { int Q; scanf( %d , &Q); buildB(); int lastans = 0, cntQ = 0; for (int i = 1; i <= Q; i++) { int type, l, r, k; scanf( %d%d%d , &type, &l, &r); l = decode(l, lastans); r = decode(r, lastans); if (l > r) swap(l, r); if (type == 1) { ++cntQ; makeCircularPerm(l, r); if (cntQ == sqrNMax) { cntQ = 0; buildA(); initialize(); buildB(); } } else { scanf( %d , &k); k = decode(k, lastans); lastans = Query(l, r, k); printf( %d n , lastans); } } } int main() { Read(); Solve(); return 0; }
|
#include <bits/stdc++.h> namespace solution {} namespace solution { class ISolution { public: virtual void init(){}; virtual bool input() { return false; }; virtual void output(){}; virtual int run() = 0; }; } // namespace solution namespace solution { using namespace std; const long long MOD = 1000000000LL; const int SIZE = 2 * 100000 + 11; const int QUERY_SIZE = 2 * 100000 + 11; int n, m; long long A[SIZE]; long long F[SIZE]; void query_1() { int x, v; cin >> x >> v; A[x] = v; } void query_2() { int l, r; cin >> l >> r; int len = r - l + 1; long long sum = 0; for (int i = 0; i < len; ++i) sum = (sum + F[i] * A[l + i]) % MOD; cout << sum << endl; } void solve() { F[0] = F[1] = 1; for (int i = 2; i < SIZE; ++i) F[i] = (F[i - 1] + F[i - 2]) % MOD; for (int i = 0; i < m; ++i) { int t; cin >> t; if (t == 1) { query_1(); } else if (t == 2) { query_2(); } } } class Solution : public ISolution { public: bool input() { if (!(cin >> n >> m)) return false; for (int i = 0; i < n; ++i) cin >> A[i + 1]; return true; } int run() { while (init(), input()) { solve(); output(); } return 0; } }; } // namespace solution int main() { return solution::Solution().run(); }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 23:23:50 04/27/2016
// Design Name:
// Module Name: Search_8Comparators
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Search_8Comparators(
input clock,
input reset,
input [1023:0] data,
input [63:0] key,
output reg match
);
// Use the counter to determine which bits of data to use.
reg [7:0] counter;
// Track the data needed for each comparator.
reg [63:0] data1, data2, data3, data4, data5, data6, data7, data8;
// Track each match output for each comparator.
wire match1, match2, match3, match4, match5, match6, match7, match8;
Comparator c1
(
.data(data1),
.key(key),
.match(match1)
);
Comparator c2
(
.data(data2),
.key(key),
.match(match2)
);
Comparator c3
(
.data(data3),
.key(key),
.match(match3)
);
Comparator c4
(
.data(data4),
.key(key),
.match(match4)
);
Comparator c5
(
.data(data5),
.key(key),
.match(match5)
);
Comparator c6
(
.data(data6),
.key(key),
.match(match6)
);
Comparator c7
(
.data(data7),
.key(key),
.match(match7)
);
Comparator c8
(
.data(data8),
.key(key),
.match(match8)
);
// Sequential Logic
always @(posedge clock, posedge reset)
begin
// If reset, reset every variable to their defaults.
if (reset)
begin
counter <= 0;
match <= 0;
end
// Otherwise, calculate the desired values.
else
begin
// If the last count is reached, then reset the counter.
// Equation: last count = (data_size - comparator_size) / num_of_comparators
if (counter == 120)
counter <= 0;
// Otherwise, increment the counter.
else
counter <= counter + 1;
// If the comparators yield matches for any of the current searches,
// then set the overall match to 1.
if (match1 || match2 || match3 || match4)
match <= 1;
// Otherwise, set it to 0.
else
match <= 0;
end
end
always @*
begin
if (counter == 120)
begin
data1 = data[1023-4*counter-:64];
data2 = data[1023-4*counter-:64];
data3 = data[1023-4*counter-:64];
data4 = data[1023-4*counter-:64];
data5 = data[1023-4*counter-:64];
data6 = data[1023-4*counter-:64];
data7 = data[1023-4*counter-:64];
data8 = data[1023-4*counter-:64];
end
else
begin
data1 = data[1023-4*counter-:64];
data2 = data[1022-4*counter-:64];
data3 = data[1021-4*counter-:64];
data4 = data[1020-4*counter-:64];
data5 = data[1019-4*counter-:64];
data6 = data[1018-4*counter-:64];
data7 = data[1017-4*counter-:64];
data8 = data[1016-4*counter-:64];
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of vgch_suba
//
// Generated
// by: wig
// on: Fri Jul 7 06:44:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: vgch_suba.v,v 1.2 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: vgch_suba.v,v $
// Revision 1.2 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of vgch_suba
//
// No user `defines in this module
module vgch_suba
//
// Generated Module vgch_suba_i
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for cgu_i
cgu cgu_i (
);
// End of Generated Instance Port Map for cgu_i
// Generated Instance Port Map for tmu_i
tmu tmu_i (
);
// End of Generated Instance Port Map for tmu_i
endmodule
//
// End of Generated Module rtl of vgch_suba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_SYMBOL_V
`define SKY130_FD_SC_HD__O2111AI_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_stub.v
// Design : RAT_Mux2x1_10_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Mux2x1_10,Vivado 2016.4" *)
module RAT_Mux2x1_10_0_0(A, B, SEL, X)
/* synthesis syn_black_box black_box_pad_pin="A[9:0],B[9:0],SEL,X[9:0]" */;
input [9:0]A;
input [9:0]B;
input SEL;
output [9:0]X;
endmodule
|
#include <bits/stdc++.h> int main() { std::ios_base::sync_with_stdio(false); std::string s; std::cin >> s; int n = s.length(); std::vector<int> prefix_fun(n, 0); for (int i = 1; i < n; i++) { int j = prefix_fun[i - 1]; while (j > 0 && s[i] != s[j]) { j = prefix_fun[j - 1]; } if (s[i] == s[j]) { j++; } prefix_fun[i] = j; } if (prefix_fun[n - 1] == 0) { std::cout << Just a legend ; return 0; } for (int i = 1; i < n - 1; i++) { if (prefix_fun[i] == prefix_fun[n - 1]) { std::cout << s.substr(0, prefix_fun[i]); return 0; } } int j = prefix_fun[prefix_fun[n - 1] - 1]; if (j == 0) { std::cout << Just a legend ; return 0; } std::cout << s.substr(0, j); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void rread(T& num) { num = 0; T f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) num = num * 10 + ch - 0 , ch = getchar(); num *= f; } const int maxn = 1e5 + 5, maxpow = 9; const long long inf = 1e18; int n, m; long long a[maxn]; vector<long long> bin; inline void Prework() { long long now = 1; for (int(i) = (0); (i) < (maxpow); (i)++) bin.push_back(now), now *= 42; } inline long long GetToNxt(long long x) { int tmp = lower_bound(bin.begin(), bin.end(), x) - bin.begin(); if (tmp == maxpow) return inf; return bin[tmp] - x; } int root; namespace Treap { int ndtot; struct TreapNode { int l, r, len, sz; long long val, tonxt, mini, tag; } T[maxn]; vector<int> pool; inline int NewNode(long long val, int len) { int x; if (((pool).size())) x = pool.back(), pool.pop_back(); else x = ++ndtot; (T[(x)].l) = (T[(x)].r) = (T[(x)].tag) = 0; (T[(x)].val) = val; (T[(x)].sz) = (T[(x)].len) = len; (T[(x)].tonxt) = (T[(x)].mini) = GetToNxt(val); return x; } inline void Update(int x) { (T[(x)].sz) = (T[(x)].len) + (T[((T[(x)].l))].sz) + (T[((T[(x)].r))].sz); (T[(x)].mini) = min((T[(x)].tonxt), min((T[((T[(x)].l))].mini), (T[((T[(x)].r))].mini))); } inline int Build(int l, int r) { if (l > r) return 0; int x = NewNode(a[((l + r) >> 1)], 1); (T[(x)].l) = Build(l, ((l + r) >> 1) - 1); (T[(x)].r) = Build(((l + r) >> 1) + 1, r); Update(x); return x; } inline void AddVal(int x, long long num) { if (!x) return; (T[(x)].tag) += num; (T[(x)].val) += num; (T[(x)].tonxt) -= num; (T[(x)].mini) -= num; } inline void PushDown(int x) { if (!x || !(T[(x)].tag)) return; AddVal((T[(x)].l), (T[(x)].tag)); AddVal((T[(x)].r), (T[(x)].tag)); (T[(x)].tag) = 0; } inline int Rnd(int x, int y) { return rand() % ((T[(x)].sz) + (T[(y)].sz)) < (T[(x)].sz); } inline int Merge(int x, int y) { if (!x || !y) return x + y; PushDown(x); PushDown(y); if (Rnd(x, y)) { (T[(x)].r) = Merge((T[(x)].r), y); Update(x); return x; } else { (T[(y)].l) = Merge(x, (T[(y)].l)); Update(y); return y; } } inline pair<int, int> Split(int x, int len) { if (!x) return make_pair(0, 0); PushDown(x); if ((T[((T[(x)].l))].sz) >= len) { pair<int, int> y = Split((T[(x)].l), len); (T[(x)].l) = y.second; Update(x); return make_pair(y.first, x); } len -= (T[((T[(x)].l))].sz); if (len < (T[(x)].len)) { int x1 = NewNode((T[(x)].val), len), x2 = NewNode((T[(x)].val), (T[(x)].len) - len); (T[(x1)].l) = (T[(x)].l); (T[(x2)].r) = (T[(x)].r); Update(x1); Update(x2); pool.push_back(x); return make_pair(x1, x2); } len -= (T[(x)].len); pair<int, int> z = Split((T[(x)].r), len); (T[(x)].r) = z.first; Update(x); return make_pair(x, z.second); } inline long long QueryVal(int x) { long long res; pair<int, int> b = Split(root, x), a = Split(b.first, x - 1); res = (T[(a.second)].val); b.first = Merge(a.first, a.second); root = Merge(b.first, b.second); return res; } inline void Recycle(int x) { if (!x) return; Recycle((T[(x)].l)); pool.push_back(x); Recycle((T[(x)].r)); } inline void SetVal(int l, int r, long long val) { pair<int, int> b = Split(root, r), a = Split(b.first, l - 1); Recycle(a.second); int x = NewNode(val, r - l + 1); b.first = Merge(a.first, x); root = Merge(b.first, b.second); } inline void FixMini(int x) { if (!x) return; PushDown(x); if ((T[(x)].tonxt) == (T[(x)].mini)) { (T[(x)].tonxt) = GetToNxt((T[(x)].val)); Update(x); return; } if ((T[((T[(x)].l))].mini) < (T[((T[(x)].r))].mini)) FixMini((T[(x)].l)); else FixMini((T[(x)].r)); Update(x); } inline void Print(int x) { if (!x) return; Print((T[(x)].l)); cerr << (T[(x)].val) << ( << (T[(x)].tonxt) << ) ; Print((T[(x)].r)); } inline void AddVal(int l, int r, long long x) { pair<int, int> b = Split(root, r), a = Split(b.first, l - 1); AddVal(a.second, x); while (1) { while ((T[(a.second)].mini) < 0) FixMini(a.second); if ((T[(a.second)].mini) > 0) break; AddVal(a.second, x); } b.first = Merge(a.first, a.second); root = Merge(b.first, b.second); } inline void Init() { (T[(0)].mini) = inf; } } // namespace Treap inline void judge() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } int main() { Prework(); Treap::Init(); rread(n); rread(m); for (int(i) = (1); (i) <= (n); (i)++) rread(a[i]); root = Treap::Build(1, n); while (m--) { int opt; rread(opt); if (opt == 1) { int x; rread(x); printf( %lld n , Treap::QueryVal(x)); } else if (opt == 2) { int l, r; long long x; rread(l); rread(r); rread(x); Treap::SetVal(l, r, x); } else if (opt == 3) { int l, r; long long x; rread(l); rread(r); rread(x); Treap::AddVal(l, r, x); } } return 0; }
|
/* verilator lint_off WIDTH */
module emesh_monitor(/*AUTOARG*/
// Inputs
clk, reset, itrace, etime, emesh_access, emesh_packet, emesh_wait
);
parameter AW = 32;
parameter DW = 32;
parameter NAME = "cpu";
parameter PW = 104;
//BASIC INTERFACE
input clk;
input reset;
input itrace;
input [31:0] etime;
//MESH TRANSCTION
input emesh_access;
input [PW-1:0] emesh_packet;
input emesh_wait;
//core name for trace
reg [63:0] name=NAME;
reg [31:0] ftrace;
initial
begin
ftrace = $fopen({NAME,".trace"}, "w");
end
always @ (posedge clk)
if(itrace & ~reset & emesh_access & ~emesh_wait)
begin
//$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
$fwrite(ftrace, "%h_%h_%h_%h\n",emesh_packet[103:72], emesh_packet[71:40],emesh_packet[39:8],
{emesh_packet[7:4],emesh_packet[3:2],emesh_packet[1],emesh_access});
end
endmodule // emesh_monitor
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/30/2017 01:18:01 AM
// Design Name:
// Module Name: top_new
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_new#(parameter WIDTH=170, //% @param Width of data input and output
parameter CNT_WIDTH=8, //% @param WIDTH must be no greater than 2**CNT_WIDTH
parameter DIV_WIDTH=6, //% @param width of division factor.
parameter SHIFT_DIRECTION=1, //% @param 1: MSB out first, 0: LSB out first
parameter READ_TRIG_SRC=0, //% @param 0:start act as trig, 1: load_sr act as trig
parameter READ_DELAY=0 //% @param state machine delay period
)(
input clk_in, //% clock input is synchronised with input signals control clock.
input rst, //% module reset
//input start, //% start signal
input [WIDTH-1:0] din, //% 170-bit data input to config shift register
input data_in_p, //% data from shift register
input data_in_n, //% data from shift register
input [DIV_WIDTH-1:0] div, //% division factor 2**div
input pulse_in,
output clk, //% sub modules' control clock
output clk_sr_p, //% control clock send to shift register
output clk_sr_n, //% control clock send to shift register
output data_out_p, //% data send to shift register
output data_out_n, //% data send to shift register
output load_sr_p, //% load signal send to shift register
output load_sr_n, //% load signal send to shift register
output valid, //% valid is asserted when 170-bit dout is on the output port
output [WIDTH-1:0] dout
);
wire start;
Top_SR top_sr_inst(
.clk_in(clk_in), //% clock input is synchronised with input signals control clock.
.rst(rst), //% module reset
.start(start), //% start signal
.din(din), //% 170-bit data input to config shift register
.data_in_p(data_in_p), //% data from shift register
.data_in_n(data_in_n), //% data from shift register
.div(div), //% division factor 2**div
.clk(clk), //% sub modules' control clock
.clk_sr_p(clk_sr_p), //% control clock send to shift register
.clk_sr_n(clk_sr_n), //% control clock send to shift register
.data_out_p(data_out_p), //% data send to shift register
.data_out_n(data_out_n), //% data send to shift register
.load_sr_p(load_sr_p), //% load signal send to shift register
.load_sr_n(load_sr_n), //% load signal send to shift register
.valid(valid), //% valid is asserted when 170-bit dout is on the output port
.dout(dout)
);
pulse_synchronise pulse_synchronise_inst(
.pulse_in(pulse_in), //% input pulse
.clk_in(clk_in), //% pulse_in control clock
.clk_out(clk), //% pulse_out control clock
.rst(rst), //% module reset
.pulse_out(start)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; const int MAXN = 500000; int A[MAXN + 10]; int main() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &A[i]); A[n + 1] = INT_MAX; A[0] = INT_MIN; sort(A + 1, A + n + 1); int l = 1, r = n; for (l = 2; l <= n && A[l] == A[l - 1]; l++) ; l--; int days = k; while (l <= n) { long long d = l * (long long)(A[l + 1] - A[l]); if (d <= days) { days -= d; A[l] = A[l + 1]; while (l <= n && A[l] == A[l + 1]) l++; } else { long long m = days / l, M = days % l, v = A[l] + m; for (int i = 1; i <= l; i++) A[i] = v; for (int i = 0; i < M; i++) A[l - i] = v + 1LL; break; } } for (r = n - 1; r > 0 && A[r] == A[r + 1]; r--) ; r++; days = k; while (r > 0) { long long d = (n - r + 1) * ((long long)A[r] - (long long)A[r - 1]); if (d <= days) { days -= d; A[r] = A[r - 1]; while (r > 0 && A[r] == A[r - 1]) r--; } else { long long m = days / (n - r + 1), M = days % (n - r + 1), v = A[r] - m; for (int i = r; i <= n; i++) A[i] = v; for (int i = 0; i < M; i++) A[r + i] = v - 1LL; break; } } printf( %d n , A[n] - A[1]); return 0; }
|
//altera message_off 10230
module alt_mem_ddrx_list
# (
// module parameter port list
parameter
CTL_LIST_WIDTH = 3, // number of dram commands that can be tracked at a time
CTL_LIST_DEPTH = 8,
CTL_LIST_INIT_VALUE_TYPE = "INCR", // INCR, ZERO
CTL_LIST_INIT_VALID = "VALID" // VALID, INVALID
)
(
// port list
ctl_clk,
ctl_reset_n,
// pop free list
list_get_entry_valid,
list_get_entry_ready,
list_get_entry_id,
list_get_entry_id_vector,
// push free list
list_put_entry_valid,
list_put_entry_ready,
list_put_entry_id
);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free list
input list_get_entry_ready;
output list_get_entry_valid;
output [CTL_LIST_WIDTH-1:0] list_get_entry_id;
output [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
// push free list
output list_put_entry_ready;
input list_put_entry_valid;
input [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// port type declaration
// -----------------------------
reg list_get_entry_valid;
wire list_get_entry_ready;
reg [CTL_LIST_WIDTH-1:0] list_get_entry_id;
reg [CTL_LIST_DEPTH-1:0] list_get_entry_id_vector;
wire list_put_entry_valid;
reg list_put_entry_ready;
wire [CTL_LIST_WIDTH-1:0] list_put_entry_id;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_LIST_WIDTH-1:0] list [CTL_LIST_DEPTH-1:0];
reg list_v [CTL_LIST_DEPTH-1:0];
reg [CTL_LIST_DEPTH-1:0] list_vector;
wire list_get = list_get_entry_valid & list_get_entry_ready;
wire list_put = list_put_entry_valid & list_put_entry_ready;
// -----------------------------
// module definition
// -----------------------------
// generate interface signals
always @ (*)
begin
// connect interface signals to list head & tail
list_get_entry_valid = list_v[0];
list_get_entry_id = list[0];
list_get_entry_id_vector = list_vector;
list_put_entry_ready = ~list_v[CTL_LIST_DEPTH-1];
end
// list put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
// initialize every entry
if (CTL_LIST_INIT_VALUE_TYPE == "INCR")
begin
list [i] <= i;
end
else
begin
list [i] <= {CTL_LIST_WIDTH{1'b0}};
end
if (CTL_LIST_INIT_VALID == "VALID")
begin
list_v [i] <= 1'b1;
end
else
begin
list_v [i] <= 1'b0;
end
end
list_vector <= {CTL_LIST_DEPTH{1'b0}};
end
else
begin
// get request code must be above put request code
if (list_get)
begin
// on a get request, list is shifted to move next entry to head
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
list_v [i-1] <= list_v [i];
list [i-1] <= list [i];
end
list_v [CTL_LIST_DEPTH-1] <= 0;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
if (list_put)
begin
// on a put request, next empty list entry is written
if (~list_get)
begin
// put request only
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if ( list_v[i-1] & ~list_v[i])
begin
list_v [i] <= 1'b1;
list [i] <= list_put_entry_id;
end
end
if (~list_v[0])
begin
list_v [0] <= 1'b1;
list [0] <= list_put_entry_id;
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_LIST_DEPTH; i = i + 1'b1)
begin
if (list_v[i-1] & ~list_v[i])
begin
list_v [i-1] <= 1'b1;
list [i-1] <= list_put_entry_id;
end
end
// if (~list_v[0])
// begin
// $display("error - list underflow");
// end
for (i = 0; i < CTL_LIST_DEPTH;i = i + 1'b1)
begin
if (list_v[0] & ~list_v[1])
begin
if (i == list_put_entry_id)
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
else
begin
if (i == list [1])
begin
list_vector [i] <= 1'b1;
end
else
begin
list_vector [i] <= 1'b0;
end
end
end
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cluster_header_ctu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The cluster header is instatiated as a hard macro.
// This model is for simulation only.
`include "sys.h"
module cluster_header_ctu (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si; // scan ports for reset flop repeaters
input se;
output so;
wire pre_sync_enable;
wire sync_enable;
wire cluster_grst_l;
wire dbginit_l;
wire rst_sync_so;
bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
.so(),
.q (pre_sync_enable),
.ck (gclk),
.d (cluster_cken),
.sd(1'b0),
.se(1'b0)
);
bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch
.so (sync_enable),
.ck (gclk),
.sd (pre_sync_enable)
);
// NOTE! Pound delay in the below statement is meant to provide 10 ps
// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
// and sync pulses to be modelled accurately. gclk and rclk need to have
// at least one simulator timestep separation to allow the flop->flop
// synchronizer to work correctly.
reg rclk_reg;
always @(gclk) rclk_reg = #10 gclk;
assign rclk = rclk_reg;
synchronizer_asr rst_repeater (
.sync_out(cluster_grst_l),
.so(rst_sync_so),
.async_in(grst_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(arst_l),
.si(si),
.se(se)
);
synchronizer_asr dbginit_repeater (
.sync_out(dbginit_l),
.so(so),
.async_in(gdbginit_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(adbginit_l),
.si(rst_sync_so),
.se(se)
);
endmodule // cluster_header
|
#include <bits/stdc++.h> using namespace std; map<vector<long long>, long long> mp; int main() { long long n; cin >> n; long long a[] = {2, 3, 5, 7}; vector<long long> t; for (long long mask = 1; mask < (1 << 4); mask++) { t.clear(); for (long long j = 0; j < 4; j++) { if (mask & (1 << j)) t.push_back(a[j]); } sort(t.begin(), t.end()); long long y = 1; for (auto v : t) y *= v; mp[t] += n / y; } for (auto x : mp) { if (x.first.size() % 2) { n -= x.second; continue; } n += x.second; } cout << n << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(long long a) { write(a); puts( ); } inline void wri(long long a) { write(a); putchar( ); } inline unsigned long long rnd() { return ((unsigned long long)rand() << 30 ^ rand()) << 4 | rand() % 4; } const int N = 150005; long double l[N], r[N]; struct data { long long p, t, id; } a[N], b[N]; int n; long long T; bool cmp(data a, data b) { return a.p < b.p; } bool cmpt(data a, data b) { long long A = (long long)a.t * b.p, B = (long long)b.t * a.p; return A == B ? a.p < b.p : A < B; } bool check(long double c) { long long sum = 0; for (int i = 1, j; i <= n; i = j) { j = i + 1; while (j <= n && a[j].t * a[i].p == a[i].t * a[j].p) j++; for (int k = (int)(i); k <= (int)(j - 1); k++) r[a[k].id] = (1 - c * (sum + a[k].t) / T) * a[k].p; for (int k = (int)(i); k <= (int)(j - 1); k++) sum += a[k].t; for (int k = (int)(i); k <= (int)(j - 1); k++) l[a[k].id] = (1 - c * sum / T) * a[k].p; } int dq = n; long double mn = 1e100; for (int i = (int)(n); i >= (int)(1); i--) { while (b[dq].p > b[i].p) { mn = min(mn, l[b[dq--].id]); } if (mn <= r[b[i].id]) return 0; } return 1; } int main() { n = read(); for (int i = (int)(1); i <= (int)(n); i++) a[a[i].id = i].p = read(); for (int i = (int)(1); i <= (int)(n); i++) T += (a[i].t = read()); for (int i = (int)(1); i <= (int)(n); i++) b[i] = a[i]; sort(a + 1, a + n + 1, cmpt); sort(b + 1, b + n + 1, cmp); long double l = 0, r = 1; for (int i = (int)(1); i <= (int)(80); i++) { long double mid = (l + r) / 2; if (check(mid)) l = mid; else r = mid; } printf( %.10f , (double)l); }
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//Code By CXY07 #include<bits/stdc++.h> using namespace std; //#define FILE //#define int long long #define debug(x) cout << #x << = << x << endl #define file(FILENAME) freopen(FILENAME .in , r , stdin), freopen(FILENAME .out , w , stdout) #define LINE() cout << LINE = << __LINE__ << endl #define LL long long #define ull unsigned long long #define pii pair<int,int> #define mp make_pair #define pb push_back #define fst first #define scd second #define inv(x) qpow((x),mod - 2) #define lowbit(x) ((x) & (-(x))) #define abs(x) ((x) < 0 ? (-(x)) : (x)) #define randint(l, r) (rand() % ((r) - (l) + 1) + (l)) #define vec vector const int MAXN = 1e6 + 10; const int INF = 2e9; const double PI = acos(-1); const double eps = 1e-6; //const int mod = 1e9 + 7; //const int mod = 998244353; //const int G = 3; //const int base = 131; int T, n, m; int _L[MAXN], _R[MAXN]; int *L = _L + (int)5e5, *R = _R + (int)5e5; char s[MAXN]; template<typename T> inline bool read(T &a) { a = 0; char c = getchar(); int f = 1; while(c < 0 || c > 9 ) {if(c == - ) f = -1; c = getchar();} while(c >= 0 && c <= 9 ) {a = a * 10 + (c ^ 48); c = getchar();} a *= f; return 1; } template<typename A, typename ...B> inline bool read(A &x, B &...y) {return read(x) && read(y...);} void solve() { scanf( %s , s + 1); n = strlen(s + 1); for(int i = -n; i <= n; ++i) L[i] = R[i] = 0; int now = 0; for(int i = 1; i <= n; ++i) { if(s[i] == 1 ) R[now++]++; else L[now--]++; } now = 0; for(int i = 1; i <= n; ++i) { if(L[now] && (!R[now] || R[now - 1])) L[now--]--, putchar( 0 ); else R[now++]--, putchar( 1 ); } putchar( n ); } signed main () { #ifdef FILE freopen( .in , r ,stdin); freopen( .out , w ,stdout); #endif read(T); while(T--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; void pause() {} bool sortbysecdesc(const pair<int, int> &a, const pair<int, int> &b) { return a.second > b.second; } int rec(int n, int i, int a[], int c) { c++; if (n == i) return c; rec(a[n - 1], i, a, c); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, a[1005], c = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = n - 1; i >= 0; i--) { c++; if (c == a[i]) { cout << c; break; } else if (c > a[i]) { cout << c - 1; break; } } cout << n ; } pause(); }
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/*
* Copyright (c) 2012, Stefan Kristiansson <>
* All rights reserved.
*
* Based on vga_fifo_dc.v in Richard Herveille's VGA/LCD core
* Copyright (C) 2001 Richard Herveille <>
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module dual_clock_fifo #(
parameter ADDR_WIDTH = 3,
parameter DATA_WIDTH = 32
)
(
input wire wr_rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_rst_i,
input wire rd_clk_i,
input wire rd_en_i,
output reg [DATA_WIDTH-1:0] rd_data_o,
output reg full_o,
output reg empty_o
);
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] wr_addr_gray;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] rd_addr_gray;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
function [ADDR_WIDTH-1:0] gray_conv;
input [ADDR_WIDTH-1:0] in;
begin
gray_conv = {in[ADDR_WIDTH-1],
in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
end
endfunction
always @(posedge wr_clk_i) begin
if (wr_rst_i) begin
wr_addr <= 0;
wr_addr_gray <= 0;
end else if (wr_en_i) begin
wr_addr <= wr_addr + 1'b1;
wr_addr_gray <= gray_conv(wr_addr + 1'b1);
end
end
// synchronize read address to write clock domain
always @(posedge wr_clk_i) begin
rd_addr_gray_wr <= rd_addr_gray;
rd_addr_gray_wr_r <= rd_addr_gray_wr;
end
always @(posedge wr_clk_i)
if (wr_rst_i)
full_o <= 0;
else if (wr_en_i)
full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
else
full_o <= full_o & (gray_conv(wr_addr + 1'b1) == rd_addr_gray_wr_r);
always @(posedge rd_clk_i) begin
if (rd_rst_i) begin
rd_addr <= 0;
rd_addr_gray <= 0;
end else if (rd_en_i) begin
rd_addr <= rd_addr + 1'b1;
rd_addr_gray <= gray_conv(rd_addr + 1'b1);
end
end
// synchronize write address to read clock domain
always @(posedge rd_clk_i) begin
wr_addr_gray_rd <= wr_addr_gray;
wr_addr_gray_rd_r <= wr_addr_gray_rd;
end
always @(posedge rd_clk_i)
if (rd_rst_i)
empty_o <= 1'b1;
else if (rd_en_i)
empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
else
empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
// generate dual clocked memory
reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
always @(posedge rd_clk_i)
if (rd_en_i)
rd_data_o <= mem[rd_addr];
always @(posedge wr_clk_i)
if (wr_en_i)
mem[wr_addr] <= wr_data_i;
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7; int n, m, a[maxn]; map<int, int> mp, rmp; int main() { scanf( %d%d , &n, &m); int id; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] == m) id = i; } int cnt = 0; for (int i = id; i >= 1; i--) { if (a[i] < m) cnt++; else if (a[i] > m) cnt--; mp[cnt]++; } long long ans = 0; cnt = 0; for (int i = id; i <= n; i++) { if (a[i] < m) cnt++; else if (a[i] > m) cnt--; ans += 1LL * mp[-cnt] + 1LL * mp[-cnt - 1]; } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; struct comp { bool operator()(const vector<int>& lhs, const vector<int>& rhs) const { return lhs.size() > rhs.size(); } }; struct comps { bool operator()(const string& lhs, const string& rhs) const { return lhs > rhs; } }; bool ff(pair<int, int> a, pair<int, int> b) { return a.first < b.first; } double dis(double x1, double y1, double x2, double y2) { return sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); } int gcd(long long unsigned int a, long long unsigned int b) { return (b == 0) ? a : gcd(b, a % b); } int comb(int a, int b) { if (a == 0) return 1; if (a < b) return 1; if (a == b) return 1; if (b == 1) return a; if (b == 0) return 1; long long unsigned int aa = 1, bb = 1; for (int i = b; i > 0; i--, a--) { aa *= a; bb *= i; int gc = gcd(aa, bb); if (gc > 1) { aa /= gc; bb /= gc; } } return aa % 1000000007; } bool isprime(long long unsigned int n) { for (int i = 2; i <= sqrt(n); i++) if (n % i == 0) return false; return true; } bool f(pair<int, int> p1, pair<int, int> p2) { if (p1.first < p2.first) return true; else if ((p1.first == p2.first) && (p1.second > p2.second)) return true; else return false; } int t[100005]; int x[100005]; int v[100005]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) cin >> t[i] >> x[i]; int i = 0; int nn = n; int kalkis = 0; int delay = 0; while (n > 0) { int p = (n >= m) ? m : n; n -= p; kalkis = (t[i + p - 1] > (kalkis + delay)) ? t[i + p - 1] : (kalkis + delay); map<int, int> mapp; map<int, vector<int> > duranlar; for (int j = i; j < i + p; j++) { mapp[x[j]]++; duranlar[x[j]].push_back(j); } map<int, int>::iterator it; delay = 0; for (it = mapp.begin(); it != mapp.end(); it++) { for (int k = 0; k < duranlar[it->first].size(); k++) { v[duranlar[it->first][k]] = kalkis + delay + (it->first); } delay += 1 + (it->second) / 2; } it--; delay += 2 * (it->first); i += p; } for (int i = 0; i < nn; i++) cout << v[i] << ; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_1_V
`define SKY130_FD_SC_MS__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_1_V
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e6; const int inf = 1e6; int n, m; int a[maxn + 5], b[maxn + 5]; int tag[maxn << 2], mx[maxn << 2]; void seta(int p, int d) { tag[p] += d; mx[p] += d; } void push(int p) { seta(p + p, tag[p]); seta(p + p + 1, tag[p]); tag[p] = 0; } void modify(int p, int l, int r, int ql, int qr, int d) { if (l == ql && r == qr) { seta(p, d); return; } push(p); int mid = (l + r) >> 1; if (qr <= mid) modify(p + p, l, mid, ql, qr, d); else if (mid < ql) modify(p + p + 1, mid + 1, r, ql, qr, d); else modify(p + p, l, mid, ql, mid, d), modify(p + p + 1, mid + 1, r, mid + 1, qr, d); mx[p] = max(mx[p + p], mx[p + p + 1]); } int query(int p, int l, int r) { if (l == r) return l; push(p); int mid = (l + r) >> 1; if (mx[p + p + 1] > 0) return query(p + p + 1, mid + 1, r); else return query(p + p, l, mid); } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); modify(1, 1, inf, 1, a[i], 1); } for (int i = 1; i <= m; i++) { scanf( %d , &b[i]); modify(1, 1, inf, 1, b[i], -1); } int q; scanf( %d , &q); while (q--) { int op, i, x; scanf( %d %d %d , &op, &i, &x); if (op == 1) { modify(1, 1, inf, 1, a[i], -1); a[i] = x; modify(1, 1, inf, 1, a[i], 1); } else { modify(1, 1, inf, 1, b[i], 1); b[i] = x; modify(1, 1, inf, 1, b[i], -1); } if (mx[1] <= 0) printf( %d n , -1); else printf( %d n , query(1, 1, inf)); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int base = 1000 * 1000 * 1000, inf = 1000 * 1000 * 1000; int buf = 0; long long gcd(long long a, long long b) { while (b) b ^= a ^= b ^= a %= b; return a; } int p[10], e[10][10]; string a[10]; int main() { int n, k, ans = inf; cin >> n >> k; for (int(i) = (1); (i) <= (n); ++(i)) { cin >> a[i]; for (int(j) = 0; (j) < (a[i].length()); ++(j)) e[i][j + 1] = a[i][j] - 0 ; } for (int(i) = (1); (i) <= (k); ++(i)) p[i] = i; bool ok = true; for (;;) { if (!ok) break; int MAX = -inf, MIN = inf; for (int(i) = (1); (i) <= (n); ++(i)) { int w[10]; long long buf = 0; for (int(j) = (1); (j) <= (k); ++(j)) { w[j] = e[i][p[j]]; long long y = 1; for (int(qq) = 0; (qq) < (k - j); ++(qq)) y *= 10; buf += w[j] * y; } if (buf > MAX) MAX = buf; if (buf < MIN) MIN = buf; } if (ans > MAX - MIN) ans = MAX - MIN; ok = false; for (int i = k - 1; i >= 1; i--) { if (p[i] < p[i + 1]) { int mn = -1; for (int(j) = (i + 1); (j) <= (k); ++(j)) if (mn == -1 || p[j] > p[i] && p[j] < p[mn]) mn = j; swap(p[i], p[mn]); reverse(p + i + 1, p + k + 1); ok = true; break; } } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; char buf[25]; struct node { long long x, y; bool operator<(node tp) const { if (x != tp.x) return x < tp.x; return y < tp.y; } }; map<long long, long long> h1, h2; map<node, long long> t, q; const long long inf = 1e17; const long long maxn = 200010; long long L1[maxn], R1[maxn], l1[maxn], r1[maxn], s1[maxn], a[maxn]; long long L2[maxn], R2[maxn], l2[maxn], r2[maxn], s2[maxn]; long long n, m, sum1, sum2; long long ans; long long read() { long long x = 0, f = 0; char ch; do { ch = getchar(); if (ch == - ) f = 1; } while (ch < 0 || ch > 9 ); while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return f ? -x : x; } void write(long long x) { if (x < 0) { putchar( - ); x = -x; } if (!x) { putchar( 0 ); return; } long long cnt = 0; while (x) { buf[++cnt] = 0 + x % 10; x /= 10; } for (long long i = cnt; i >= 1; --i) putchar(buf[i]); } signed main() { srand(19267180); n = read(); m = read(); for (long long i = 1; i <= n; ++i) { h1[i] = (1ll * rand() * rand() * rand() * rand() % inf + inf) % inf; h2[i] = (1ll * rand() * rand() * rand() * rand() % inf + inf) % inf; sum1 = h1[i] ^ sum1; sum2 = h2[i] ^ sum2; } for (long long i = 1; i <= n; ++i) { long long l = read(), r = read(); ++a[l]; --a[r + 1]; s1[l] ^= h1[i]; s1[r + 1] ^= h1[i]; L1[l - 1] ^= h1[i]; R1[r + 1] ^= h1[i]; s2[l] ^= h2[i]; s2[r + 1] ^= h2[i]; L2[l - 1] ^= h2[i]; R2[r + 1] ^= h2[i]; } for (long long i = m - 1; i >= 1; --i) L1[i] ^= L1[i + 1], L2[i] ^= L2[i + 1]; for (long long i = 2; i <= m; ++i) { R1[i] ^= R1[i - 1], s1[i] ^= s1[i - 1]; R2[i] ^= R2[i - 1], s2[i] ^= s2[i - 1]; } for (long long i = 2; i <= m; ++i) s1[i] ^= s1[i - 1], s2[i] ^= s2[i - 1]; for (long long i = 1; i <= m; ++i) { l1[i] = s1[i - 1] ^ R1[i], r1[i] = s1[i] ^ L1[i]; l2[i] = s2[i - 1] ^ R2[i], r2[i] = s2[i] ^ L2[i]; } for (long long i = m; i >= 1; --i) { t[(node){r1[i], r2[i]}] += 1; q[(node){r1[i], r2[i]}] += i; long long x_1 = sum1 ^ l1[i], x_2 = sum2 ^ l2[i]; ans += q[(node){x_1, x_2}] - 1ll * t[(node){x_1, x_2}] * (i - 1); } for (long long i = 1; i <= m; ++i) a[i] += a[i - 1]; long long x = 0; for (long long i = 1; i <= m; ++i) { if (a[i] == 0) ++x; else x = 0; if (x) if (i == m || a[i + 1] != 0) for (long long j = 1; j <= x; ++j) ans -= 1ll * j * (x - j + 1); } write(ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long p; map<long long, int> m[123]; int main() { int characters_value[26]; long long i; for (i = 0; i < 26; i++) cin >> characters_value[i]; string s; cin >> s; long long ans = 0; for (i = 0; i < s.size(); i++) { ans += m[s[i]][p]; p += characters_value[s[i] - a ]; m[s[i]][p]++; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; const int INF = int(1e9); long long n, m; pair<long long, long long> p = make_pair(0, 0); long long b[222222]; long long c[222222]; long long ans; map<long long, long long> mp; int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; mp[x]++; } cin >> m; for (int i = 1; i <= m; i++) cin >> b[i]; for (int i = 1; i <= m; i++) cin >> c[i]; for (int i = 1; i <= m; i++) if (p <= make_pair(mp[b[i]], mp[c[i]])) ans = i, p = make_pair(mp[b[i]], mp[c[i]]); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int on[100005]; int prime[100005], cnt = 0; void ola() { for (int i = 2; i <= 100005; i++) { if (!on[i]) prime[cnt++] = i; for (int j = 0; j < cnt && i * prime[j] <= 100005; j++) { on[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } } int main() { int n, flag = 0; cin >> n; ola(); for (int i = 2; i <= n + 1; i++) { if (on[i] == 1) { on[i] = 2; flag = 1; } else on[i] = 1; } if (flag == 1) cout << 2 << endl; else cout << 1 << endl; for (int i = 2; i <= n; i++) cout << on[i] << ; cout << on[n + 1] << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:06 08/03/2009
// Design Name:
// Module Name: ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MCtrl(input clk,
input reset,
input [31:0] Inst_in,
input zero,
input overflow,
input MIO_ready,
output reg MemRead,
output reg MemWrite,
output [2:0]ALU_operation,
output [4:0]state_out,
output reg CPU_MIO,
output reg IorD,
output reg IRWrite,
output reg [1:0]RegDst,
output reg RegWrite,
output reg [1:0]MemtoReg,
output reg ALUSrcA,
output reg [1:0]ALUSrcB,
output reg [1:0]PCSource,
output reg PCWrite,
output reg PCWriteCond,
output reg Branch
);
reg [3:0] state, Q;
reg [1:0] ALUop;
wire[3:0] D;
parameter IF = 4'b0000, ID = 4'b0001, Mem_Ex = 4'b0010, Mem_RD = 4'b0011, LW_WB = 4'b0100,
Mem_W = 4'b0101, R_Exc = 4'b0110, R_WB = 4'b0111, Beq_Exc= 4'b1000, J = 4'b1001,
Error = 4'b1111;
`define Datapath_signals {PCWrite, PCWriteCond,IorD, MemRead, MemWrite,IRWrite, MemtoReg, PCSource, ALUSrcA, ALUSrcB, RegWrite, RegDst, Branch, ALUop, CPU_MIO}
parameter value0 = 20'b10010100000010000000, value1 = 20'b00000000000110000000,
value2 = 20'b00000000001100000000, value3 = 20'b00110000000000000001,
value4 = 20'b00000001000001000000, value5 = 20'b00101000000000000001,
value6 = 20'b00000000001000000100, value7 = 20'b00000000000001010000,
value8 = 20'b01000000011000001010, value9 = 20'b10000000100000000000;
parameter AND=3'b000, OR=3'b001, ADD=3'b010, SUB=3'b110, NOR=3'b100, SLT=3'b111, XOR=3'b011, SRL=3'b101;
assign state_out={1'b0,Q};
wire [5:0] OP = Inst_in[31:26];
//
wire s0 = ~|Q; //if Q=0000 then s0 = 1
wire s1 = ~Q[3] && ~Q[2] && ~Q[1] && Q[0] ; //if Q=0001 then s1 = 1
wire s2 = ~Q[3] && ~Q[2] && Q[1] && ~Q[0] ; //if Q=0010 then s2 = 1
wire s3 = ~Q[3] && ~Q[2] && Q[1] && Q[0] ; //if Q=0011 then s3 = 1
wire s4 = ~Q[3] && Q[2] && ~Q[1] && ~Q[0] ; //if Q=0100 then s4 = 1
wire s5 = ~Q[3] && Q[2] && ~Q[1] && Q[0] ; //if Q=0101 then s5 = 1
wire s6 = ~Q[3] && Q[2] && Q[1] && ~Q[0] ; //if Q=0110 then s6 = 1
wire s7 = ~Q[3] && Q[2] && Q[1] && Q[0] ; //if Q=0111 then s7 = 1
wire s8 = Q[3] && ~Q[2] && ~Q[1] && ~Q[0] ; //if Q=1000 then s8 = 1
wire s9 = Q[3] && ~Q[2] && ~Q[1] && Q[0] ; //if Q=1001 then s9 = 1
wire Rtype = ~|OP;
wire LS = (OP == 6'b10x011) ? 1 : 0;
wire IBeq = (OP == 6'b000100) ? 1 : 0;
wire Jump = (OP == 6'b000010) ? 1 : 0;
wire Load = (OP == 6'b100011) ? 1 : 0;
wire Store = (OP == 6'b101011) ? 1 : 0;
assign D[3] = s1 && (IBeq || Jump);
assign D[2] = s1 && Rtype || s2 && Store || s3 && Load || s6 && Rtype;
assign D[1] = s1 && (LS || Rtype) || s2 && Load || s6 && Rtype;
assign D[0] = s0 || s1 && Jump || s2 && Load || s2 && Store || s6 && Rtype;
always @ (posedge clk or posedge reset)
if (reset==1) Q <= IF;
else Q <= D;
always @ * begin
case(Q) //state
IF: `Datapath_signals = value0;
ID: `Datapath_signals = value1;
Mem_Ex: `Datapath_signals = value2;
Mem_RD: `Datapath_signals = value3;
LW_WB: `Datapath_signals = value4;
Mem_W: `Datapath_signals = value5;
R_Exc: `Datapath_signals = value6;
R_WB: `Datapath_signals = value7;
Beq_Exc: `Datapath_signals = value8;
J: `Datapath_signals = value9;
default: `Datapath_signals = value0;
endcase
end
//ALU Decoder
ALU_Decoder ALU_D(.ALUop(ALUop),
.Fun(Inst_in[5:0]),
.ALU_Control(ALU_operation)
);
/* always @ * begin
case(ALUop)
2'b00: ALU_operation = 3'b010; //add¼ÆËãµØÖ·
2'b01: ALU_operation = 3'b110; //sub±È½ÏÌõ¼þ
2'b10:
case (Inst_in[5:0])
6'b100000: ALU_operation = ADD;
6'b100010: ALU_operation = SUB;
6'b100100: ALU_operation = AND;
6'b100101: ALU_operation = OR;
6'b100111: ALU_operation = NOR;
6'b101010: ALU_operation = SLT;
6'b000010: ALU_operation = SRL; //shfit 1bit right
6'b000000: ALU_operation = XOR;
default: ALU_operation = ADD;
endcase
2'b11: ALU_operation = 3'b111; //slti
endcase
end
*/
/* always @ (posedge clk or posedge reset)
if (reset==1) begin
state <= IF;
end
else
case (state)
IF: begin
if(MIO_ready)begin state <= ID; end
else begin state <= IF;end
end
ID: begin
case (Inst_in[31:26])
6'b000000:begin state <= R_Exc; end //R-type OP
6'b100011:begin state <= Mem_Ex; end //Lw
6'b101011:begin state <= Mem_Ex; end //Sw
6'b000010:begin state <= J; end //Jump
6'b000100:begin state <= Beq_Exc; end //Beq
default: begin state <= Error; end
endcase
end //end ID
Mem_Ex:begin
if(Inst_in[31:26]==6'b100011)begin
state <= Mem_RD; end
else if(Inst_in[31:26]==6'b101011)begin
state <= Mem_W; end
end
Mem_RD:begin
if(MIO_ready)begin
state <= LW_WB; end
else begin
state <=Mem_RD; end
end
Mem_W:begin
if(MIO_ready)begin
state <= IF; end
else begin
state <= Mem_W; end
end
LW_WB:begin
state <=IF; end
R_Exc:begin
state <= R_WB; end
R_WB:begin
state <= IF; end
Beq_Exc:begin
state <= IF; end
J:begin
state <= IF; end
Error: state <= Error;
default: begin
state <= Error; end
endcase
*/
endmodule
|
// nios_system_nios2_qsys_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.03.15:20:15
`timescale 1 ps / 1 ps
module nios_system_nios2_qsys_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [18:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [18:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_system_nios2_qsys_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
`include "system.vh"
module harness();
parameter CYCLE = 100,
Tsetup = 15,
Thold = 5;
// -- Señales de interconexion ----------------------------------- >>>>>
reg clk;
reg reset;
// -- input port --------------------------------------------- >>>>>
wire credit_out_dout;
wire [`CHANNEL_WIDTH-1:0] input_channel_din;
// -- output port -------------------------------------------- >>>>>
wire credit_in_din;
wire [`CHANNEL_WIDTH-1:0] output_channel_dout;
// -- interfaz :: processing node ---------------------------- >>>>>
wire start_strobe;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordA;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordB;
wire done_strobe;
wire active_test_engine;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordC;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordD;
// -- DUT -------------------------------------------------------- >>>>>
test_engine_network_interface DUT
(
.clk (clk),
.reset (reset),
// -- input port ----------------------------------------- >>>>>
.credit_out_dout (credit_out_dout),
.input_channel_din (input_channel_din),
// -- output port ---------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout),
// -- interfaz :: processing node ------------------------ >>>>>
.start_strobe_dout (start_strobe),
.wordA_dout (wordA),
.wordB_dout (wordB),
.done_strobe_din (done_strobe),
.active_test_engine_din (active_test_engine),
.wordC_din (wordC),
.wordD_din (wordD)
);
// -- PE dummy --------------------------------------------------- >>>>>
test_engine_dummy
#(
.Thold(Thold)
)
test_engine_dummy
(
.clk(clk),
// -- inputs --------------------------------------------- >>>>>
.start_strobe_din(start_strobe),
.wordA_din(wordA),
.wordB_din(wordB),
// -- outputs -------------------------------------------- >>>>>
.done_strobe_dout(done_strobe),
.active_test_engine_dout(active_test_engine),
.wordC_dout(wordC),
.wordD_dout(wordD)
);
// -- Canal IO ----------------------------------------------- >>>>>
source
#(
.Thold(Thold),
.CREDITS(1)
)
input_channel
(
.clk (clk),
.credit_in (credit_out_dout),
.channel_out(input_channel_din)
);
sink
#(
.Thold(Thold)
)
output_channel
(
.clk (clk),
.channel_in (output_channel_dout),
.credit_out (credit_in_din)
);
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule // harness
|
// megafunction wizard: %LPM_CLSHIFT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_CLSHIFT
// ============================================================
// File Name: SHIFT.v
// Megafunction Name(s):
// LPM_CLSHIFT
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module SHIFT (
data,
direction,
distance,
result);
input [15:0] data;
input direction;
input [3:0] distance;
output [15:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
// Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "16"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: lpm_widthdist NUMERIC "4"
// Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: port_direction NUMERIC "2"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL "direction"
// Retrieval info: USED_PORT: distance 0 0 4 0 INPUT NODEFVAL "distance[3..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
// Retrieval info: CONNECT: @distance 0 0 4 0 distance 0 0 4 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SHIFT_bb.v TRUE
|
//================code===================// //#define TLE #ifdef TLE #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #endif #include <bits/stdc++.h> #include <unordered_map> #include <unordered_set> #include <random> #include <ctime> #define ci(t) cin>>t #define co(t) cout<<t #define LL long long #define ld long double #define fa(i,a,b) for(LL i=(a);i<(LL)(b);++i) #define fd(i,a,b) for(LL i=(a);i>(LL)(b);--i) #define setp pair<pair<int,int>,int> #define setl pair<LL,LL> #define M_PI 3.14159265358979323846 #define micro 0.000001 using namespace std; #ifdef OHSOLUTION #define ce(t) cerr<<t #define AT cerr << n=================ANS================= n #define AE cerr << n===================================== n LL gcd(LL a, LL b) { return a % b ? gcd(b, a % b) : b; } LL lcm(LL a, LL b) { return (a * b) / gcd(a, b); } #else #define AT #define AE #define ce(t) #define __popcnt __builtin_popcount #define gcd __gcd #define lcm __lcm #endif pair <int, int> vu[9] = { {0,1},{1,0},{0,-1} ,{-1,0},{0,0},{1,1}, {-1,1} , {1,-1},{-1,-1} }; //RDLU EWSN template<typename T, typename U> void ckmax(T& a, U b) { a = a < b ? b : a; } template<typename T, typename U> void ckmin(T& a, U b) { a = a > b ? b : a; } struct gcmp { bool operator()(LL a, LL b) { return a < b; } bool operator()(setl a, setl b) { return a.second < b.second; } }; struct lcmp { bool operator()(LL a, LL b) { return a > b; } bool operator()(setl a, setl b) { return a.second > b.second; } }; const int max_v = 2e5 + 7; const int INF = 1e9 + 7; const LL LNF = (LL)1e18 + 7ll; const LL mod = 1e9 + 7; int v, e; vector <setl> adj[max_v]; LL dist[max_v][57]; bool vist[max_v][57]; struct node { LL first, second; LL cost; }; struct cmp { bool operator()(const node& x, const node& b) { return x.second > b.second; } }; int main() { #ifdef OHSOLUTION freopen( input.txt , r , stdin); #endif ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ci(v >> e); fa(i, 0, e) { int x, y, cost; ci(x >> y >> cost), --x, --y; adj[x].push_back({ y,cost }); adj[y].push_back({ x,cost }); } priority_queue<node, vector<node>, cmp> pq; fa(i, 0, v) fa(j, 0, 51) dist[i][j] = INF; dist[0][0] = 0; pq.push({ 0,0 ,0}); while (!pq.empty()) { node cur; do { cur = pq.top(); pq.pop(); } while (!pq.empty() && vist[cur.first][cur.cost]); if (vist[cur.first][cur.cost]) break; vist[cur.first][cur.cost] = 1; if (cur.cost) { for (auto x : adj[cur.first]) { if (dist[x.first][0] > dist[cur.first][cur.cost] + (cur.cost + x.second) * (cur.cost + x.second)) { dist[x.first][0] = dist[cur.first][cur.cost] + (cur.cost + x.second) * (cur.cost + x.second); pq.push({ x.first,dist[x.first][0],0 }); } } } else { for (auto x : adj[cur.first]) { if (dist[x.first][x.second] > dist[cur.first][cur.cost]) { dist[x.first][x.second] = dist[cur.first][cur.cost]; pq.push({ x.first,dist[x.first][x.second],x.second }); } } } } fa(i, 0, v) dist[i][0] == INF ? co(-1 << ) : co(dist[i][0] << ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {-1, 0, 0, 1}; int dy[] = {0, -1, 1, 0}; int dx1[] = {-1, -1, -1, 0, 0, 0, 1, 1, 1}; int dy1[] = {-1, 0, 1, -1, 0, 1, -1, 0, 1}; const double eps = 1e-9; const int inf = 2000000000; const long long int infLL = 9000000000000000000; const long long int MOD = 1e+7; const double PI = 3.141592653589793238462643383279; int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; int ans = 2 * n - m + 1; for (long long int i = 0; i < m; i++) { int k; cin >> k; for (long long int j = 0; j < k; j++) { int a; cin >> a; if (a == j + 1) ans -= 2; } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, now; int a[3005], b[3005]; int vis[3005], f[3005], c[3005]; int ok[3005]; int findcir(int *a, int n) { int ret = 0; for (int i = 1; i <= n; i++) b[a[i]] = i; memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) { if (vis[i]) continue; int j; ret++; for (j = i; !vis[j]; j = b[j]) { f[j] = ret; vis[j] = 1; c[ret]++; } } return ret; } void Swap(int x) { if (!x) return; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (f[i] == f[j]) { printf( %d %d , i, j); x--; if (!x) return; swap(a[i], a[j]); findcir(a, n); } } void move(int x) { if (!x) return; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (f[i] != f[j]) { printf( %d %d , i, j); x--; if (!x) return; swap(a[i], a[j]); findcir(a, n); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); now = findcir(a, n); now = n - now; scanf( %d , &m); printf( %d n , abs(now - m)); if (now > m) { Swap(now - m); } else move(m - now); return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_zero_one_hot (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ZERO_ONE_HOT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/ovl_zero_one_hot_logic.v"
`endif
`ifdef OVL_SVA
`include "./sva05/ovl_zero_one_hot_logic.sv"
`endif
`ifdef OVL_PSL
`include "./psl05/assert_zero_one_hot_psl_logic.v"
`else
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endmodule // ovl_zero_one_hot
`endif
|
// part of NeoGS project
//
// (c) NedoPC 2007-2008
//
// modelling is in tb_dma1.*
// look also at dma_access.png
module dma_access(
input clk,
input rst_n,
input dma_req, // DMA request
input [21:0] dma_addr, // DMA address (2mb)
input dma_rnw, // DMA READ/nWRITE
input [7:0] dma_wd, // DMA data to write
output reg [7:0] dma_rd, // DMA data just read
output reg dma_busynready, // DMA BUSY/nREADY
output reg dma_ack, // positive pulse as dma_busynready goes high
output reg dma_end, // positive pulse as dma_busynready goes low
output wire mem_dma_bus, // DMA taking over the bus
output wire [21:0] mem_dma_addr, // DMA address going to the bus
output wire [7:0] mem_dma_wd, // DMA data going to the bus
input [7:0] mem_dma_rd, // DMA data going from the bus
output wire mem_dma_rnw, // DMA bus direction (1=read, 0=write)
output reg mem_dma_oe, // DMA read strobe going to the bus
output reg mem_dma_we, // DMA write pulse going to the bus
output reg busrq_n, // CPU signals
input busak_n // control
);
reg dma_bus;
reg [21:0] int_dma_addr;
reg int_dma_rnw;
reg [7:0] int_dma_wd;
wire [7:0] int_dma_rd;
assign mem_dma_bus = dma_bus;
assign mem_dma_addr = int_dma_addr;
assign mem_dma_wd = int_dma_wd;
assign mem_dma_rnw = int_dma_rnw;
assign int_dma_rd = mem_dma_rd;
localparam IDLE = 0;
localparam START = 1;
localparam WACK = 2;
localparam READ1 = 3;
localparam READ2 = 4;
localparam WRITE1 = 5;
localparam WRITE2 = 6;
reg [3:0] state;
reg [3:0] next_state;
// for simulation purposes
initial
begin
state <= IDLE;
busrq_n <= 1'b1;
mem_dma_oe <= 1'b1;
mem_dma_we <= 1'b1;
end
// FSM
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
state <= IDLE;
else
state <= next_state;
end
always @*
begin
case( state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
if( dma_req==1'b1 )
next_state <= START;
else
next_state <= IDLE;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
next_state <= WACK;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
if( busak_n == 1'b1 ) ///// ACHTUNG WARNING!!! probably use here registered busak?
next_state <= WACK;
else // busak_n == 1'b0
begin
if( int_dma_rnw == 1'b1 ) // read
next_state <= READ1;
else // int_dma_rnw == 1'b0 - write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
next_state <= READ2;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
next_state <= WRITE2;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
if( dma_req == 1'b0 )
next_state <= IDLE;
else // dma_req == 1'b1
begin
if( dma_rnw == 1'b1 ) // next is read
next_state <= READ1;
else // dma_rnw == 1'b0 - next is write
next_state <= WRITE1;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
begin
busrq_n <= 1'b1;
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b0;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
else case( next_state )
//////////////////////////////////////////////////////////////////////////////////////////
IDLE:
begin
dma_end <= 1'b0;
busrq_n <= 1'b1;
dma_bus <= 1'b0;
mem_dma_oe <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
START:
begin
// dma_bus <= 1'b0; // if rst=0>1 and dma_ack=1 --> ??? is this really needed?
busrq_n <= 1'b0;
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
int_dma_rnw <= dma_rnw;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WACK:
begin
dma_ack <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////////////////////
READ1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b0;
if( dma_busynready == 1'b0 ) // if we are here from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b1;
int_dma_addr <= dma_addr;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
READ2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
dma_rd <= int_dma_rd;
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE1:
begin
dma_bus <= 1'b1; // take over the bus
mem_dma_oe <= 1'b1;
if( dma_busynready == 1'b0 ) // from READ2 or WRITE2
begin
dma_busynready <= 1'b1;
dma_ack <= 1'b1;
dma_end <= 1'b0;
int_dma_rnw <= 1'b0;
int_dma_addr <= dma_addr;
int_dma_wd <= dma_wd;
end
end
//////////////////////////////////////////////////////////////////////////////////////////
WRITE2:
begin
dma_busynready <= 1'b0;
dma_ack <= 1'b0;
dma_end <= 1'b1;
end
//////////////////////////////////////////////////////////////////////////////////////////
endcase
end
// mem_dma_we generator
always @(negedge clk,negedge rst_n)
begin
if( !rst_n )
mem_dma_we <= 1'b1;
else
begin
if( dma_bus )
begin
if( !int_dma_rnw )
mem_dma_we <= ~mem_dma_we;
end
else
mem_dma_we <= 1'b1;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_dram_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module cmp_dram_mon(/*AUTOARG*/
// Inputs
clk, dram_pad0_cs_l, dram_pad1_cs_l, dram_pad2_cs_l,
dram_pad3_cs_l, rst_l
);
input clk;
input [1:0] dram_pad0_cs_l;
input [1:0] dram_pad1_cs_l;
input [1:0] dram_pad2_cs_l;
input [1:0] dram_pad3_cs_l;
input rst_l;
reg[2:0] count00, count01, count10, count11, count20, count21, count30, count31;
reg tr00, tr01, tr10, tr11, tr20, tr21, tr30, tr31;
initial begin
count00 = 0;count01 = 0;
count10 = 0;count11 = 0;
count20 = 0;count21 = 0;
count30 = 0;count31 = 0;
tr00 = 0;tr01 = 0;
tr10 = 0;tr11 = 0;
tr20 = 0;tr21 = 0;
tr30 = 0;tr31 = 0;
end
`ifdef GATE_SIM_DRAM
`else
dram_mon dram_mon0( .clk (clk), .rst_l (rst_l));
always @(negedge clk)
begin
if(rst_l)begin
if(`DRAM_PATH0.que_pos == 5'h0a)begin
#2
if((dram_pad0_cs_l[0] == 0) & (dram_pad0_cs_l[1] == 0))begin
$display("%0d Error: pad0 cs0 and cs1 turn on the same time", $time);
`MONITOR_PATH.fail("cs0 and cs1 turn on the same time");
end
if(dram_pad0_cs_l[0] == 0)begin
if(tr01 && (count01 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs0 turn on early");
end
tr00 = 1;tr01 = 0;count00 = 0;
end
if(dram_pad0_cs_l[1] == 0)begin
if(tr00 && (count00 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs1 turn on early");
end
tr01 = 1;tr00 = 0;count01 = 0;
end // if (dram_pad0_cs_l[1] == 0)
end // if (que_pos0 == 5'h0a)
if(`DRAM_PATH1.que_pos == 5'h0a)begin
#2
if((dram_pad1_cs_l[0] == 0) & (dram_pad1_cs_l[1] == 0))begin
$display("%0d Error: pad1 cs0 and cs1 turn on the same time", $time);
`MONITOR_PATH.fail("cs0 and cs1 turn on the same time");
end
if(dram_pad1_cs_l[0] == 0)begin
if(tr11 && (count11 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs0 turn on early");
end
tr10 = 1;tr11 = 0;count10 = 0;
end
if(dram_pad1_cs_l[1] == 0)begin
if(tr10 && (count10 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs1 turn on early");
end
tr11 = 1;tr10 = 0;count11 = 0;
end
end // if (que_pos1 == 5'h0a)
if(`DRAM_PATH2.que_pos == 5'h0a)begin
#2
if((dram_pad2_cs_l[0] == 0) & (dram_pad2_cs_l[1] == 0))begin
$display("%0d Error: pad2 cs0 and cs1 turn on the same time", $time);
`MONITOR_PATH.fail("cs0 and cs1 turn on the same time");
end
if(dram_pad2_cs_l[0] == 0)begin
if(tr21 && (count21 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs0 turn on early");
end
tr20 = 1;tr21 = 0;count20 = 0;
end
if(dram_pad2_cs_l[1] == 0)begin
if(tr20 && (count20 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs1 turn on early");
end
tr21 = 1;tr20 = 0;count21 = 0;
end // if (dram_pad0_cs_l[1])
end // if (que_pos2 == 5'h0a)
if(`DRAM_PATH3.que_pos == 5'h0a)begin
#2
if((dram_pad3_cs_l[0] == 0) & (dram_pad3_cs_l[1] == 0))begin
$display("%0d Error: pad3 cs0 and cs1 turn on the same time", $time);
`MONITOR_PATH.fail("cs0 and cs1 turn on the same time");
end
if(dram_pad3_cs_l[0] == 0)begin
if(tr31 && (count31 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs0 turn on early");
end
tr30 = 1;tr31 = 0;count30 = 0;
end
if(dram_pad3_cs_l[1] == 0)begin
if(tr30 && (count30 < 6))begin
$display("%0d Error: dram pad0 chip enable turn on early", $time);
`MONITOR_PATH.fail("Dram chip cs1 turn on early");
end
tr31 = 1;tr30 = 0;count31 = 0;
end // if (dram_pad0_cs_l[1])
end // if (que_pos3 == 5'h0a)
if(tr00)count00 = count00 + 1;
if(tr01)count01 = count01 + 1;
if(tr10)count10 = count10 + 1;
if(tr11)count11 = count11 + 1;
if(tr20)count20 = count20 + 1;
if(tr21)count21 = count21 + 1;
if(tr30)count30 = count30 + 1;
if(tr31)count31 = count31 + 1;
if(count00 == 6)tr00 = 0;
if(count01 == 6)tr01 = 0;
if(count10 == 6)tr10 = 0;
if(count11 == 6)tr11 = 0;
if(count20 == 6)tr20 = 0;
if(count21 == 6)tr21 = 0;
if(count30 == 6)tr30 = 0;
if(count31 == 6)tr31 = 0;
end
end // always @ (negedge clk)
`endif // ifdef GATE_SIM_DRAM
endmodule
|
// `include "define.v"
module ForwardControl (
input rst,
input[`RegAddrWidth-1:0] reg_data_1_addr_ID,
input[`RegAddrWidth-1:0] reg_data_2_addr_ID,
input[`RegAddrWidth-1:0] reg_data_1_addr_EX,
input[`RegAddrWidth-1:0] reg_data_2_addr_EX,
input[`RegAddrWidth-1:0] target_EX,
input WriteReg_EX,
input[`RegAddrWidth-1:0] reg_data_2_addr_MEM,
input[`RegAddrWidth-1:0] target_MEM,
input WriteReg_MEM,
input MemOrAlu_MEM,
input we_hi_MEM,
input we_lo_MEM,
input[`RegAddrWidth-1:0] target_WB,
input WriteReg_WB,
input we_hi_WB,
input we_lo_WB,
output reg[1:0] FWA,
output reg[1:0] FWB,
output reg[1:0] FWhi,
output reg[1:0] FWlo,
output reg FWLS,
output reg[1:0] FW_br_A,
output reg[1:0] FW_br_B
);
always @(*) begin : proc_forwarding
if (rst == ~`RstEnable) begin
// branch srcA
if ((reg_data_1_addr_ID == target_EX) &&
(WriteReg_EX == `WriteEnable) &&
(target_EX != 0)) begin
FW_br_A <= `FW_br_EX_ALU;
end
else if ((reg_data_1_addr_ID == target_MEM) &&
(WriteReg_MEM == `WriteEnable) &&
(target_MEM != 0)) begin
case (MemOrAlu_MEM)
`ALU : FW_br_A <= `FW_br_MEM_ALU;
`Mem : FW_br_A <= `FW_br_MEM_MEM;
default : begin
end
endcase
end
else begin
FW_br_A <= `FW_br_Origin;
end
// branch srcB
if ((reg_data_2_addr_ID == target_EX) &&
(WriteReg_EX == `WriteEnable) &&
(target_EX != 0)) begin
FW_br_B <= `FW_br_EX_ALU;
end
else if ((reg_data_2_addr_ID == target_MEM) &&
(WriteReg_MEM == `WriteEnable) &&
(target_MEM != 0)) begin
case (MemOrAlu_MEM)
`ALU : FW_br_B <= `FW_br_MEM_ALU;
`Mem : FW_br_B <= `FW_br_MEM_MEM;
default : begin
end
endcase
end
else begin
FW_br_B <= `FW_br_Origin;
end
// stage EX reg_data_1
if ((reg_data_1_addr_EX == target_MEM) &&
(WriteReg_MEM == `WriteEnable) &&
(target_MEM != 0)) begin
FWA <= `FWMem;
end
else if ((reg_data_1_addr_EX == target_WB) &&
(WriteReg_WB == `WriteEnable) &&
(target_WB != 0)) begin
FWA <= `FWWB;
end
else begin
FWA <= `FWOrigin;
end
// stage EX reg_data_2
if ((reg_data_2_addr_EX == target_MEM) &&
(WriteReg_MEM == `WriteEnable) &&
(target_MEM != 0)) begin
FWB <= `FWMem;
end
else if ((reg_data_2_addr_EX == target_WB) &&
(WriteReg_WB == `WriteEnable) &&
(target_WB != 0)) begin
FWB <= `FWWB;
end
else begin
FWB <= `FWOrigin;
end
// stage EX hi
if (we_hi_MEM == `WriteEnable) begin
FWhi <= `FWMem;
end
else if (we_hi_WB == `WriteEnable) begin
FWhi <= `FWWB;
end
else begin
FWhi <= `FWOrigin;
end
// stage EX lo
if (we_lo_MEM == `WriteEnable) begin
FWlo <= `FWMem;
end
else if (we_lo_WB == `WriteEnable) begin
FWlo <= `FWWB;
end
else begin
FWlo <= `FWOrigin;
end
// stage MEM SW
if ((reg_data_2_addr_MEM == target_WB) &&
(WriteReg_WB == `WriteEnable) &&
(target_WB != 0)) begin
FWLS <= `FW_LS_WB;
end
else begin
FWLS <= `FW_LS_Origin;
end
end
else begin
FWA <= 0;
FWB <= 0;
FWhi <= 0;
FWlo <= 0;
FWLS <= 0;
FW_br_A <= 0;
FW_br_B <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:59:52 03/09/2015
// Design Name:
// Module Name: Register_Group
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register_Group(
output [15 : 0] data_out_A,
output [15 : 0] data_out_B,
input write,
input [3 : 0] address,
input [7 : 0] output_AB,
input [15 : 0] data_in
);
reg [15 : 0] register [15 : 0]; // R0 for zero, R1~R7 are normal reg, R2 for RA, R15 for SP, R14 for T, R13 for IH
initial
begin
register[0] <= 0;
end
assign data_out_A = register[output_AB[7 : 4]];
assign data_out_B = register[output_AB[3 : 0]];
always @(posedge write) // R0 for zero, so write != 0 means pipeline needs to WB
begin
if (address != 0)
begin
register[address] <= data_in;
end
// register[0] = 0;
end
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
/*
* UART interface
*/
input wire rxd,
output wire txd,
/*
* Status
*/
output wire tx_busy,
output wire rx_busy,
output wire rx_overrun_error,
output wire rx_frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
uart_tx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(tx_busy),
// configuration
.prescale(prescale)
);
uart_rx #(
.DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.busy(rx_busy),
.overrun_error(rx_overrun_error),
.frame_error(rx_frame_error),
// configuration
.prescale(prescale)
);
endmodule
|
`define bsg_xnor_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_XNR2D1BWP_b``bits xnor_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_xnor #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_xnor_macro(34) else
`bsg_xnor_macro(33) else
`bsg_xnor_macro(32) else
`bsg_xnor_macro(31) else
`bsg_xnor_macro(30) else
`bsg_xnor_macro(29) else
`bsg_xnor_macro(28) else
`bsg_xnor_macro(27) else
`bsg_xnor_macro(26) else
`bsg_xnor_macro(25) else
`bsg_xnor_macro(24) else
`bsg_xnor_macro(23) else
`bsg_xnor_macro(22) else
`bsg_xnor_macro(21) else
`bsg_xnor_macro(20) else
`bsg_xnor_macro(19) else
`bsg_xnor_macro(18) else
`bsg_xnor_macro(17) else
`bsg_xnor_macro(16) else
`bsg_xnor_macro(15) else
`bsg_xnor_macro(14) else
`bsg_xnor_macro(13) else
`bsg_xnor_macro(12) else
`bsg_xnor_macro(11) else
`bsg_xnor_macro(10) else
`bsg_xnor_macro(9) else
`bsg_xnor_macro(8) else
`bsg_xnor_macro(7) else
`bsg_xnor_macro(6) else
`bsg_xnor_macro(5) else
`bsg_xnor_macro(4) else
`bsg_xnor_macro(3) else
`bsg_xnor_macro(2) else
`bsg_xnor_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i ^ b_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_xnor)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:55:51 07/09/2015
// Design Name:
// Module Name: Component_encoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Component_encoder
( input [7:0] Data,
input C0,
input C1,
input DE,
input PixClk,
output [9:0] OutEncoded
);
integer Cnt;
integer NewCnt;
reg [8:0] q_m;
integer N1_Data;
integer N1_qm;
integer N0_qm;
reg [9:0] Encoded;
initial
begin
Cnt = 0;
NewCnt = 0;
end
assign OutEncoded = Encoded;
always @(posedge PixClk)
begin
N1_Data = Data[0] + Data[1] + Data[2] + Data[3] + Data[4] + Data[5] + Data[6] + Data[7];
if ((N1_Data > 4) || ((N1_Data == 4) && (Data[0] == 0)))
begin
q_m[0] = Data[0];
q_m[1] = ~(q_m[0] ^ Data[1]);
q_m[2] = ~(q_m[1] ^ Data[2]);
q_m[3] = ~(q_m[2] ^ Data[3]);
q_m[4] = ~(q_m[3] ^ Data[4]);
q_m[5] = ~(q_m[4] ^ Data[5]);
q_m[6] = ~(q_m[5] ^ Data[6]);
q_m[7] = ~(q_m[6] ^ Data[7]);
q_m[8] = 0;
end
else
begin
q_m[0] = Data[0];
q_m[1] = q_m[0] ^ Data[1];
q_m[2] = q_m[1] ^ Data[2];
q_m[3] = q_m[2] ^ Data[3];
q_m[4] = q_m[3] ^ Data[4];
q_m[5] = q_m[4] ^ Data[5];
q_m[6] = q_m[5] ^ Data[6];
q_m[7] = q_m[6] ^ Data[7];
q_m[8] = 1;
end
N1_qm = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7];
N0_qm = 8 - N1_qm;
if (DE == 1)
begin
if ((Cnt == 0) || (N1_qm == 4))
begin
if (q_m[8] == 0)
begin
Encoded[9] = 1;
Encoded[8] = 0;
Encoded[7:0] = ~q_m[7:0];
NewCnt = Cnt + N0_qm - N1_qm;
end
else
begin
Encoded[9] = 0;
Encoded[8] = 1;
Encoded[7:0] = q_m[7:0];
NewCnt = Cnt + N1_qm - N0_qm;
end
end
else
begin
if (((Cnt > 0) && (N1_qm > 4)) || ((Cnt < 0) && (N1_qm < 4)))
begin
if (q_m[8] == 0)
begin
Encoded[9] = 1;
Encoded[8] = 0;
Encoded[7:0] = ~q_m[7:0];
NewCnt = Cnt + N0_qm - N1_qm;
end
else
begin
Encoded[9] = 1;
Encoded[8] = 1;
Encoded[7:0] = ~q_m[7:0];
NewCnt = Cnt + N0_qm - N1_qm + 2;
end
end
else
begin
if (q_m[8] == 0)
begin
Encoded[9] = 0;
Encoded[8] = 0;
Encoded[7:0] = q_m[7:0];
NewCnt = Cnt + N1_qm - N0_qm - 2;
end
else
begin
Encoded[9] = 0;
Encoded[8] = 1;
Encoded[7:0] = q_m[7:0];
NewCnt = Cnt + N1_qm - N0_qm;
end
end
end
end
else
begin
NewCnt = 0;
case({C0,C1})
2'b10: Encoded = 10'b0010101011;
2'b01: Encoded = 10'b0101010100;
2'b11: Encoded = 10'b1010101011;
default: Encoded = 10'b1101010100;
endcase
end
end
always @(negedge PixClk)
begin
Cnt = NewCnt;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int in() { int32_t x; scanf( %d , &x); return x; } inline long long lin() { long long x; scanf( %lld , &x); return x; } inline string get() { char ch[2000010]; scanf( %s , ch); return ch; } const int MAX_LG = 21; const int maxn = 2e3 + 10; const int maxm = 1e5 + 10; const int base = 29; const int mod = 1e9 + 7; const int INF = 1e9 + 100; const int SQ = 317; int Cmp; int mark[maxn]; int v[maxm], u[maxm], deg[maxn], has[maxn][maxn], e[maxm]; int vc[5]; inline void dfs(int node, int id) { int edgeid = has[node][vc[id]] - 1; if (edgeid < 0) return; int nxt = v[edgeid] == node ? u[edgeid] : v[edgeid]; has[node][vc[id]] = 0; has[nxt][vc[id]] = 0; dfs(nxt, id ^ 1); has[node][vc[id ^ 1]] = edgeid + 1; has[nxt][vc[id ^ 1]] = edgeid + 1; e[edgeid] = vc[id ^ 1]; } int res; int32_t main() { int a = in(), b = in(), m = in(); for (int i = 0; i < m; i++) { v[i] = in(), u[i] = in() + a; deg[v[i]]++; deg[u[i]]++; res = max(res, max(deg[v[i]], deg[u[i]])); } for (int i = 0; i < m; i++) { bool fl = false; for (int col = 1; col <= res; col++) { if (has[v[i]][col] == 0 && has[u[i]][col] == 0 && col <= res) { has[v[i]][col] = has[u[i]][col] = i + 1; e[i] = col; fl = true; break; } } if (!fl) { Cmp++; for (int col = 1; col <= res; col++) { if (has[v[i]][col] && !has[u[i]][col]) vc[0] = col; if (has[v[i]][col] == 0 && has[u[i]][col]) vc[1] = col; } dfs(v[i], 0); has[v[i]][vc[0]] = has[u[i]][vc[0]] = i + 1; e[i] = vc[0]; } } cout << res << n ; for (int i = 0; i < m; i++) cout << e[i] << ; }
|
#include <bits/stdc++.h> using namespace std; int nod(int a, int b) { while (a && b) { int c = a % b; a = b; b = c; } return a | b; } int Abs(int a) { return a >= 0 ? a : -a; } int main() { int n, m; cin >> n >> m; vector<vector<int> > e(n); for (int i = 0; i < m; ++i) { int a, b; scanf( %d%d , &a, &b); a--; b--; e[a].push_back(b); } vector<int> d(n, -1); queue<int> q; q.push(0); d[0] = 0; int r = 0; while (!q.empty()) { int i = q.front(); q.pop(); int dd = d[i] + 1; for (int j = 0; j < (int)e[i].size(); ++j) { int a = e[i][j]; if (d[a] >= 0) r = nod(r, Abs(d[a] - dd)); else { q.push(a); d[a] = dd; } } } int c = 0; for (int i = 0; i < n; ++i) if (d[i] >= 0 && d[i] % r == 0) c++; printf( %d n%d n , r, c); for (int i = 0; i < n; ++i) if (d[i] >= 0 && d[i] % r == 0) printf( %d , i + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x7fffffff; inline int reint() { int d; scanf( %d , &d); return d; } inline long relong() { long l; scanf( %ld , &l); return l; } inline char rechar() { scanf( ); return getchar(); } inline double redouble() { double d; scanf( %lf , &d); return d; } inline string restring() { string s; cin >> s; return s; } int mask(int a) { char str[10]; sprintf(str, %d , a); char ans[10]; int j = 0; for (int i = (0); i < (strlen(str)); i++) { if (str[i] == 4 || str[i] == 7 ) { ans[j++] = str[i]; } } int res = 0; for (int i = (0); i < (j); i++) { res += ans[i] - 0 ; if (i != j - 1) { res *= 10; } } return res; } int c, b; int main(void) { cin >> c >> b; c++; while (mask(c) != b) { c++; } cout << c << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<long long> a(n); long long i, j; for (i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { if (a[i] == 0) continue; if (a[j] % a[i] == 0) { a[j] = 0; } } } long long cnt = 0; for (i = 0; i < n; i++) if (a[i] > 0) cnt++; cout << cnt << endl; return 0; }
|
`include "defines.v"
`include "injector.v"
`include "ejector.v"
module nodeRouter
#(parameter addr = 4'b0010)
(
input `control_w port0_ci,
input `control_w port1_ci,
input `control_w portl0_ci,
input `control_w portl1_ci,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_co,
output `control_w port1_co,
output `control_w portl0_co,
output `control_w portl1_co
);
// Config
wire `addrx_w addrx, max_addrx;
wire `addry_w addry, max_addry;
assign addrx = addr[`addrx_f]; // This nodes x address
assign addry = addr[`addry_f]; // This nodes y address
assign max_addrx = `addrx_max;
assign max_addry = `addry_max;
// inputs
wire `control_w port0_c_0, port1_c_0, portl0_c_0, portl1_c_0;
assign port0_c_0 = (rst) ? `control_n'd0 : port0_ci;
assign port1_c_0 = (rst) ? `control_n'd0 : port1_ci;
assign portl0_c_0 = (rst) ? `control_n'd0 : portl0_ci;
assign portl1_c_0 = (rst) ? `control_n'd0 : portl1_ci;
/************* STAGE 1 *************/
reg `control_w port0_c_0_r, port1_c_0_r, portl0_c_0_r, portl1_c_0_r;
always @(posedge clk) begin
port0_c_0_r <= port0_c_0;
port1_c_0_r <= port1_c_0;
portl0_c_0_r <= portl0_c_0;
portl1_c_0_r <= portl1_c_0;
end
wire `steer_w port0_c_1, port1_c_1;
ejector ej(
.addr(addr),
.c0(port0_c_0_r),
.c1(port1_c_0_r),
.c0_o(port0_c_1),
.c1_o(port1_c_1),
.c_ej0(portl0_co),
.c_ej1(portl1_co));
injector ij(
.c0(port0_c_1),
.c1(port1_c_1),
.c0_o(port0_co),
.c1_o(port1_co),
.c_in0(portl0_ci),
.c_in1(portl1_ci),
.ack0(portl0_ack),
.ack1(portl1_ack));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[100005]; double dfs(int i, int ult) { double ans = 0; int c = g[i].size() - (i != 1); for (int j = 0; j < g[i].size(); j++) { if (g[i][j] != ult) { ans += (dfs(g[i][j], i) + 1.0) / c; } } return ans; } int main() { int n; scanf( %d , &n); for (int i = 1; i < n; i++) { int a, b; scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } printf( %.15lf n , dfs(1, 0)); }
|
#include <bits/stdc++.h> using namespace std; long long n, t; std::vector<pair<long long, long long> > v; long long dp[(1 << 15) + 5][226][4]; long long solve(long long x, long long y, long long z) { if (x == 0) return 1; if (x < 0) return 0; if (dp[y][x][z] != -1) return dp[y][x][z]; long long ans = 0; for (long long i = 0; i < n; i++) { if (v[i].second != z and (y & (1 << i))) { ans = (ans + (solve(x - v[i].first, y - (1 << i), v[i].second)) % 1000000007) % 1000000007; } } dp[y][x][z] = ans; return dp[y][x][z] % 1000000007; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> t; long long t1, t2; for (long long i = 0; i < (1 << 15) + 5; i++) for (long long j = 0; j < 226; j++) for (long long k = 0; k < 4; k++) dp[i][j][k] = -1; for (long long i = 0; i < n; i++) { cin >> t1 >> t2; v.push_back(make_pair(t1, t2)); } cout << solve(t, (1 << n) - 1, 0); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_tmu2();
parameter fml_depth = 26;
parameter wbm_depth = 26;
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [31:0] wbm_adr_o;
wire [2:0] wbm_cti_o;
wire wbm_cyc_o;
wire wbm_stb_o;
reg wbm_ack_i;
reg [31:0] wbm_dat_i;
wire [fml_depth-1:0] fmlr_adr;
wire fmlr_stb;
reg fmlr_ack;
reg [63:0] fmlr_di;
wire [fml_depth-1:0] fmldr_adr;
wire fmldr_stb;
reg fmldr_ack;
reg [63:0] fmldr_di;
wire [fml_depth-1:0] fmlw_adr;
wire fmlw_stb;
reg fmlw_ack;
wire [7:0] fmlw_sel;
wire [63:0] fmlw_do;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
tmu2 #(
.fml_depth(fml_depth),
.texel_cache_depth(13)
) dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.irq(irq),
.wbm_adr_o(wbm_adr_o),
.wbm_cti_o(wbm_cti_o),
.wbm_cyc_o(wbm_cyc_o),
.wbm_stb_o(wbm_stb_o),
.wbm_ack_i(wbm_ack_i),
.wbm_dat_i(wbm_dat_i),
.fmlr_adr(fmlr_adr),
.fmlr_stb(fmlr_stb),
.fmlr_ack(fmlr_ack),
.fmlr_di(fmlr_di),
.fmldr_adr(fmldr_adr),
.fmldr_stb(fmldr_stb),
.fmldr_ack(fmldr_ack),
.fmldr_di(fmldr_di),
.fmlw_adr(fmlw_adr),
.fmlw_stb(fmlw_stb),
.fmlw_ack(fmlw_ack),
.fmlw_sel(fmlw_sel),
.fmlw_do(fmlw_do)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
`define TEST_COPY
/* Handle WB master for texture coordinates reads */
reg [6:0] x;
reg [6:0] y;
always @(posedge sys_clk) begin
if(wbm_stb_o & ~wbm_ack_i) begin
x = wbm_adr_o[9:3];
y = wbm_adr_o[16:10];
`ifdef TEST_COPY
if(wbm_adr_o[2])
wbm_dat_i = y*16*64;
else
wbm_dat_i = x*16*64;
`endif
`ifdef TEST_ZOOMIN
if(wbm_adr_o[2])
wbm_dat_i = y*10*64;
else
wbm_dat_i = x*10*64;
`endif
`ifdef TEST_ZOOMOUT
if(wbm_adr_o[2])
wbm_dat_i = y*40*64;
else
wbm_dat_i = x*40*64;
`endif
`ifdef TEST_ROTOZOOM
// 73*cos(pi/8) ~ 67
// 73*sin(pi/8) ~ 28
if(wbm_adr_o[2])
wbm_dat_i = (x*16-256)*28 + (y*16-256)*67 + 256*64;
else
wbm_dat_i = (x*16-256)*67 - (y*16-256)*28 + 256*64;
`endif
$display("Vertex read: %d,%d (y:%b)", x, y, wbm_adr_o[2]);
wbm_ack_i = 1'b1;
end else
wbm_ack_i = 1'b0;
end
/* Handle FML master for pixel reads */
task handle_read;
input img;
input [fml_depth-1:0] addr;
integer read_addr2;
integer x;
integer y;
reg [15:0] p1; /* work around bugs/problems if we assign */
reg [15:0] p2; /* directly to fmlr_di[xx:xx] in $image_get... */
reg [15:0] p3;
reg [15:0] p4;
begin
read_addr2 = addr[20:0]/2;
x = read_addr2 % 512;
y = read_addr2 / 512;
$image_get(img, x + 0, y, p1);
$image_get(img, x + 1, y, p2);
$image_get(img, x + 2, y, p3);
$image_get(img, x + 3, y, p4);
if(img != 0)
fmldr_di = {p1, p2, p3, p4};
else
fmlr_di = {p1, p2, p3, p4};
end
endtask
/* Texture */
integer read_burstcount;
integer read_addr;
initial read_burstcount = 0;
always @(posedge sys_clk) begin
fmlr_ack = 1'b0;
if(read_burstcount == 0) begin
if(fmlr_stb & (($random % 5) == 0)) begin
read_burstcount = 1;
read_addr = fmlr_adr;
handle_read(0, read_addr);
//$display("Starting FML burst READ at address %x, data=%x", read_addr, fmlr_di);
fmlr_ack = 1'b1;
end
end else begin
read_addr = read_addr + 8;
read_burstcount = read_burstcount + 1;
handle_read(0, read_addr);
//$display("Continuing FML burst READ at address %x, data=%x", read_addr, fmlr_di);
if(read_burstcount == 4)
read_burstcount = 0;
end
end
/* Destination */
integer dread_burstcount;
integer dread_addr;
initial dread_burstcount = 0;
always @(posedge sys_clk) begin
fmldr_ack = 1'b0;
if(dread_burstcount == 0) begin
if(fmldr_stb & (($random % 5) == 0)) begin
dread_burstcount = 1;
dread_addr = fmldr_adr;
handle_read(1, dread_addr);
//$display("Starting FML burst read at address %x, data=%x [dest]", dread_addr, fmldr_di);
fmldr_ack = 1'b1;
end
end else begin
dread_addr = dread_addr + 8;
dread_burstcount = dread_burstcount + 1;
handle_read(1, dread_addr);
//$display("Continuing FML burst read at address %x, data=%x [dest]", dread_addr, fmldr_di);
if(dread_burstcount == 4)
dread_burstcount = 0;
end
end
/* Handle FML master for pixel writes */
integer write_burstcount;
integer write_addr;
task handle_write;
integer write_addr2;
integer x;
integer y;
begin
write_addr2 = write_addr[20:0]/2;
x = write_addr2 % 512;
y = write_addr2 / 512;
if(fmlw_sel[7])
$image_set(1, x + 0, y, fmlw_do[63:48]);
if(fmlw_sel[5])
$image_set(1, x + 1, y, fmlw_do[47:32]);
if(fmlw_sel[3])
$image_set(1, x + 2, y, fmlw_do[31:16]);
if(fmlw_sel[1])
$image_set(1, x + 3, y, fmlw_do[15:0]);
end
endtask
initial write_burstcount = 0;
always @(posedge sys_clk) begin
fmlw_ack = 1'b0;
if(write_burstcount == 0) begin
if(fmlw_stb & (($random % 5) == 0)) begin
write_burstcount = 1;
write_addr = fmlw_adr;
//$display("Starting FML burst WRITE at address %x data=%x mask=%b", write_addr, fmlw_do, fmlw_sel);
handle_write;
fmlw_ack = 1'b1;
end
end else begin
write_addr = write_addr + 8;
write_burstcount = write_burstcount + 1;
//$display("Continuing FML burst WRITE at address %x data=%x mask=%b", write_addr, fmlw_do, fmlw_sel);
handle_write;
if(write_burstcount == 4)
write_burstcount = 0;
end
end
always begin
$display("Opening input picture...");
$image_open;
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fmlr_di = 64'd0;
fmlr_ack = 1'b0;
fmldr_di = 64'd0;
fmldr_ack = 1'b0;
fmlw_ack = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
/* Setup */
$display("Configuring TMU...");
csrwrite(32'h2C, 32'h01000000); /* dst framebuffer */
csrwrite(32'h04, 32); /* hmeshlast */
csrwrite(32'h08, 32); /* vmeshlast */
csrwrite(32'h1C, 512); /* texhres */
csrwrite(32'h20, 512); /* texvres */
csrwrite(32'h30, 512); /* dsthres */
csrwrite(32'h34, 512); /* dstvres */
csrwrite(32'h40, 16); /* squarew */
csrwrite(32'h44, 16); /* squareh */
csrwrite(32'h24, 32'h7fff); /* hmask, enable 512x512 wrapping */
csrwrite(32'h28, 32'h7fff); /* vmask */
csrwrite(32'h48, 63); /* alpha */
/* Start */
$display("Starting TMU...");
csrwrite(32'h00, 32'd1);
@(posedge irq);
$display("Received DONE IRQ from TMU!");
$display("Writing output picture...");
$image_close;
$display("All done!");
$finish;
end
endmodule
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Data cache LRU implementation
Copyright (C) 2012 Stefan Wallentowitz <>
******************************************************************************/
// This is the least-recently-used (LRU) calculation module. It
// essentially has two types of input and output. First, the history
// information needs to be evaluated to calculate the LRU value.
// Second, the current access and the LRU are one hot values of the
// ways.
//
// This module is pure combinational. All registering is done outside
// this module. The following parameter exists:
//
// * NUMWAYS: Number of ways (must be greater than 1)
//
// The following ports exist:
//
// * current: The current LRU history
// * update: The new LRU history after access
//
// * access: 0 if no access or one-hot of the way that accesses
// * lru_pre: LRU before the access (one hot of ways)
// * lru_post: LRU after the access (one hot of ways)
//
// The latter three have the width of NUMWAYS apparently. The first
// three are more complicated as this is an optimized way of storing
// the history information, which will be shortly described in the
// following.
//
// A naive approach to store the history of the access is to store the
// relative "age" of each element in a vector, for example for four
// ways:
//
// 0: 1 1: 3 2: 1 3:0
//
// This needs 4x2 bits, but more important it also needs a set of
// comparators and adders. This can become increasingly complex when
// using a higher number of cache ways with an impact on area and
// timing.
//
// Similarly, it is possible to store a "stack" of the access and
// reorder this stack on an access. But the problems are similar, it
// needs comparators etc.
//
// A neat approach is to store the history efficiently coded, while
// also easing the calculation. This approach stores the information
// whether each entry is older than the others. For example for the
// four-way example (x<y means x is older than y):
//
// |0<1|0<2|0<3|1<0|1<2|1<3|2<0|2<1|2<3|3<0|3<1|3<2|
//
// This is redundant as two entries can never be equally old meaning
// x<y == !y<x, leading to a simpler version
//
// |0<1|0<2|0<3|1<2|1<3|2<3|
//
// The calculations on this vector are much simpler and it is
// therefore used by this module.
//
// The width of this vector is the triangular number of (NUMWAYS-1),
// specifically:
// WIDTH=NUMWAYS*(NUMWAYS-1)/2.
//
// The details of the algorithms are described below. The designer
// just needs to apply current history vector and the access and gets
// the updated history and the LRU before and after the access.
//
// Instantiation example:
// mor1kx_dcache_lru
// (.NUMWAYS(4))
// u_lru(.current (current_history[((NUMWAYS*(NUMWAYS-1))>>1)-1:0])),
// .update (updated_history[((NUMWAYS*(NUMWAYS-1))>>1)-1:0])),
// .access (access[NUMWAYS-1:0]),
// .lru_pre (lru_pre[NUMWAYS-1:0]),
// .lru_post (lru_post[NUMWAYS-1:0]));
module mor1kx_cache_lru(/*AUTOARG*/
// Outputs
update, lru_pre, lru_post,
// Inputs
current, access
);
parameter NUMWAYS = 2;
// Triangular number
localparam WIDTH = NUMWAYS*(NUMWAYS-1) >> 1;
input [WIDTH-1:0] current;
output reg [WIDTH-1:0] update;
input [NUMWAYS-1:0] access;
output reg [NUMWAYS-1:0] lru_pre;
output reg [NUMWAYS-1:0] lru_post;
reg [NUMWAYS-1:0] expand [0:NUMWAYS-1];
integer i, j;
integer offset;
//
// < 0 1 2 3
// 0 1 (0<1) (0<2) (0<3)
// 1 (1<0) 1 (1<2) (1<3)
// 2 (2<0) (2<1) 1 (2<3)
// 3 (3<0) (3<1) (3<2) 1
//
// As two entries can never be equally old (needs to be avoided on
// the outside) this is equivalent to:
//
// < 0 1 2 3
// 0 1 (0<1) (0<2) (0<3)
// 1 !(0<1) 1 (1<2) (1<3)
// 2 !(0<2) !(1<2) 1 (2<3)
// 3 !(0<3) !(1<3) !(2<3) 1
//
// The lower half below the diagonal is the inverted mirror of the
// upper half. The number of entries in each half is of course
// equal to the width of our LRU vector and the upper half is
// filled with the values from the vector.
//
// The algorithm works as follows:
//
// 1. Fill the matrix (expand) with the values. The entry (i,i) is
// statically one.
//
// 2. The LRU_pre vector is the vector of the ANDs of the each row.
//
// 3. Update the values with the access vector (if any) in the
// following way: If access[i] is set, the values in row i are
// set to 0. Similarly, the values in column i are set to 1.
//
// 4. The update vector of the lru history is then generated by
// copying the upper half of the matrix back.
//
// 5. The LRU_post vector is the vector of the ANDs of each row.
//
// In the following an example will be used to demonstrate the algorithm:
//
// NUMWAYS = 4
// current = 6'b110100;
// access = 4'b0010;
//
// This current history is:
//
// 0<1 0<2 0<3 1<2 1<3 2<3
// 0 0 1 0 1 1
//
// and way 2 is accessed.
//
// The history of accesses is 3>0>1>2 and the expected result is an
// update to 2>3>0>1 with LRU_pre=2 and LRU_post=1
always @(*) begin : comb
// The offset is used to transfer the flat history vector into
// the upper half of the
offset = 0;
// 1. Fill the matrix (expand) with the values. The entry (i,i) is
// statically one.
for (i = 0; i < NUMWAYS; i = i + 1) begin
expand[i][i] = 1'b1;
for (j = i + 1; j < NUMWAYS; j = j + 1) begin
expand[i][j] = current[offset+j-i-1];
end
for (j = 0; j < i; j = j + 1) begin
expand[i][j] = !expand[j][i];
end
offset = offset + NUMWAYS - i - 1;
end // for (i = 0; i < NUMWAYS; i = i + 1)
// For the example expand is now:
// < 0 1 2 3 0 1 2 3
// 0 1 (0<1) (0<2) (0<3) 0 1 0 0 1
// 1 (1<0) 1 (1<2) (1<3) => 1 1 1 0 1
// 2 (2<0) (2<1) 1 (2<3) 2 1 1 1 1
// 3 (3<0) (3<1) (3<2) 1 3 0 0 0 1
// 2. The LRU_pre vector is the vector of the ANDs of the each
// row.
for (i = 0; i < NUMWAYS; i = i + 1) begin
lru_pre[i] = &expand[i];
end
// We derive why this is the case for the example here:
// lru_pre[2] is high when the following condition holds:
//
// (2<0) & (2<1) & (2<3).
//
// Applying the negation transform we get:
//
// !(0<2) & !(1<2) & (2<3)
//
// and this is exactly row [2], so that here
//
// lru_pre[2] = &expand[2] = 1'b1;
//
// At this point you can also see why we initialize the diagonal
// with 1.
// 3. Update the values with the access vector (if any) in the
// following way: If access[i] is set, the values in row i
// are set to 0. Similarly, the values in column i are set
// to 1.
for (i = 0; i < NUMWAYS; i = i + 1) begin
if (access[i]) begin
for (j = 0; j < NUMWAYS; j = j + 1) begin
if (i != j) begin
expand[i][j] = 1'b0;
end
end
for (j = 0; j < NUMWAYS; j = j + 1) begin
if (i != j) begin
expand[j][i] = 1'b1;
end
end
end
end // for (i = 0; i < NUMWAYS; i = i + 1)
// Again this becomes obvious when you see what we do here.
// Accessing way 2 leads means now
//
// (0<2) = (1<2) = (3<2) = 1, and
// (2<0) = (2<1) = (2<3) = 0
//
// The matrix changes accordingly
//
// 0 1 2 3 0 1 2 3
// 0 1 0 0 1 0 1 0 1 1
// 1 1 1 0 1 => 1 1 1 1 1
// 2 1 1 1 1 2 0 0 1 0
// 3 0 0 0 1 3 0 0 1 1
// 4. The update vector of the lru history is then generated by
// copying the upper half of the matrix back.
offset = 0;
for (i = 0; i < NUMWAYS; i = i + 1) begin
for (j = i + 1; j < NUMWAYS; j = j + 1) begin
update[offset+j-i-1] = expand[i][j];
end
offset = offset + NUMWAYS - i - 1;
end
// This is the opposite operation of step 1 and is clear now.
// Update becomes:
//
// update = 6'b011110
//
// This is translated to
//
// 0<1 0<2 0<3 1<2 1<3 2<3
// 0 1 1 1 1 0
//
// which is: 2>3>0>1, which is what we expected.
// 5. The LRU_post vector is the vector of the ANDs of each row.
for (i = 0; i < NUMWAYS; i = i + 1) begin
lru_post[i] = &expand[i];
end
// This final step is equal to step 2 and also clear now.
//
// lru_post[1] = &expand[1] = 1'b1;
//
// lru_post = 4'b0010 is what we expected.
end
endmodule // mor1kx_dcache_lru
|
#include <bits/stdc++.h> using namespace std; char q[7][50] = { Anka , Chapay , Cleo , Troll , Dracul , Snowy , Hexadecimal }; map<string, int> h; int a[3], u[7], v[3], w[7], r, rb, m[7][7]; void upd() { int i, mx, mn, j, k; for (i = 0; i < 3; v[i] = 0, i++) ; for (i = 0; i < 7; v[u[i]]++, i++) ; for (i = 0; i < 3; i++) if (!v[i]) return; for (i = 0; i < 7; w[i] = a[u[i]] / v[u[i]], i++) ; for (mx = w[0], mn = w[0], i = 1; i<7; mx = w[i]> mx ? w[i] : mx, mn = w[i] < mn ? w[i] : mn, i++) ; for (k = 0, i = 0; i < 7; i++) for (j = 0; j < 7; k += m[i][j] && u[i] == u[j], j++) ; if (mx - mn < r || (mx - mn == r && k > rb)) { r = mx - mn; rb = k; } } void rec(int i) { if (i == 7) upd(); else for (u[i] = 0; u[i] < 3; rec(i + 1), u[i]++) ; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0), cerr << ; int i, j, t; char s[100]; for (i = 0; i < 7; h[q[i]] = i, i++) ; for (cin >> t; t--;) { cin >> s; i = h[s]; cin >> s >> s; j = h[s]; m[i][j] = 1; } for (i = 0; i < 3; cin >> a[i], i++) ; r = 2000000010; rec(0); cout << r << << rb << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [11:0] in_a;
reg [31:0] sel;
wire [2:0] out_x;
extractor #(4,3) extractor (
// Outputs
.out (out_x),
// Inputs
.in (in_a),
.sel (sel));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x %x\n", cyc, in_a, sel, out_x);
if (cyc==1) begin
in_a <= 12'b001_101_111_010;
sel <= 32'd0;
end
if (cyc==2) begin
sel <= 32'd1;
if (out_x != 3'b010) $stop;
end
if (cyc==3) begin
sel <= 32'd2;
if (out_x != 3'b111) $stop;
end
if (cyc==4) begin
sel <= 32'd3;
if (out_x != 3'b101) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module extractor (/*AUTOARG*/
// Outputs
out,
// Inputs
in, sel
);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=2;
input [IN_WIDTH*OUT_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
input [31:0] sel;
wire [OUT_WIDTH-1:0] out = selector(in,sel);
function [OUT_WIDTH-1:0] selector;
input [IN_WIDTH*OUT_WIDTH-1:0] inv;
input [31:0] selv;
integer i;
begin
selector = 0;
for (i=0; i<OUT_WIDTH; i=i+1) begin
selector[i] = inv[selv*OUT_WIDTH+i];
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 5e5 + 100, INF = 1e9; int N, M, X[MX], cnt; map<int, int> mp; struct Seg { int z; int l, r; Seg *L, *R; void update(int x) { z = min(z, x); } void pushdown() { L->update(z), R->update(z); } void init(int a, int b); void Min(int a, int b, int x); int ask(int a); } T[MX << 1], *Cnt = T; Seg* New() { return ++Cnt; } void Seg::init(int a, int b) { l = a, r = b, z = INF; if (l == r) return; int m = (l + r) >> 1; L = New(), L->init(l, m); R = New(), R->init(m + 1, r); } void Seg::Min(int a, int b, int x) { if (a <= l && r <= b) { update(x); return; } pushdown(); if (a <= L->r) L->Min(a, b, x); if (b >= R->l) R->Min(a, b, x); } int Seg::ask(int a) { if (l == r) return z; pushdown(); if (a <= L->r) return L->ask(a); else return R->ask(a); } struct Query { int id, l, nx; } Q[MX]; int H[MX], qc; void add(int id, int l, int r) { Q[++qc].id = id, Q[qc].l = l, Q[qc].nx = H[r], H[r] = qc; } int ans[MX]; int A[MX]; void Solve() { for (int i = (1); i <= (N); ++i) { int c = X[i]; if (A[c]) { int delta = i - A[c]; T->Min(1, A[c], delta); } A[c] = i; for (int j = H[i]; j; j = Q[j].nx) ans[Q[j].id] = T->ask(Q[j].l); } } int main() { scanf( %d%d , &N, &M); int x; for (int i = (1); i <= (N); ++i) { scanf( %d , &x); if (!mp.count(x)) mp[x] = ++cnt; X[i] = mp[x]; } T->init(1, N); int l, r; for (int i = (1); i <= (M); ++i) { scanf( %d%d , &l, &r); add(i, l, r); } Solve(); for (int i = (1); i <= (M); ++i) printf( %d n , (ans[i] == INF ? -1 : ans[i])); return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck the_ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk the_ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_instance_index = 0,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_ir_width = 2,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_mfg_id = 110,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_action = "",
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_n_scan = 0,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_total_length = 0,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_type_id = 135,
// ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
module cla_adder(
input [31:0] A,
input [31:0] B,
input Cin,
output [31:0] Sum,
output Cout
);
wire [31:0] a_plus_b_cin_0;
wire [31:0] a_plus_b_cin_1;
full_adder fa_00_cin_0
full_adder fa_01_cin_0
full_adder fa_02_cin_0
full_adder fa_03_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_00_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
full_adder fa_0_cin_0
endmodule
|
/**
* bsg_cache_decode.v
*
*/
`include "bsg_defines.v"
module bsg_cache_decode
import bsg_cache_pkg::*;
(
input bsg_cache_opcode_e opcode_i
, output bsg_cache_decode_s decode_o
);
always_comb begin
case (opcode_i)
// double
AMOSWAP_D, AMOADD_D, AMOAND_D, AMOOR_D, AMOXOR_D,
AMOMIN_D, AMOMAX_D, AMOMINU_D, AMOMAXU_D,
LD, SD, LDU: decode_o.data_size_op = 2'b11;
// word
AMOSWAP_W, AMOADD_W, AMOAND_W, AMOOR_W, AMOXOR_W,
AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W,
LW, SW, LWU: decode_o.data_size_op = 2'b10;
// half
LH, SH, LHU: decode_o.data_size_op = 2'b01;
// byte
LB, SB, LBU: decode_o.data_size_op = 2'b00;
default: decode_o.data_size_op = 2'b00;
endcase
end
assign decode_o.mask_op = (opcode_i == LM) | (opcode_i == SM);
assign decode_o.sigext_op = (opcode_i == LB)
|| (opcode_i == LH)
|| (opcode_i == LW)
|| (opcode_i == LD)
|| decode_o.atomic_op;
assign decode_o.ld_op = (opcode_i == LB)
|| (opcode_i == LH)
|| (opcode_i == LW)
|| (opcode_i == LD)
|| (opcode_i == LBU)
|| (opcode_i == LHU)
|| (opcode_i == LWU)
|| (opcode_i == LDU)
|| (opcode_i == LM);
assign decode_o.st_op = (opcode_i == SB)
|| (opcode_i == SH)
|| (opcode_i == SW)
|| (opcode_i == SD)
|| (opcode_i == SM);
assign decode_o.tagst_op = (opcode_i == TAGST);
assign decode_o.tagfl_op = (opcode_i == TAGFL);
assign decode_o.taglv_op = (opcode_i == TAGLV);
assign decode_o.tagla_op = (opcode_i == TAGLA);
assign decode_o.afl_op = (opcode_i == AFL);
assign decode_o.aflinv_op = (opcode_i == AFLINV);
assign decode_o.ainv_op = (opcode_i == AINV);
assign decode_o.alock_op = (opcode_i == ALOCK);
assign decode_o.aunlock_op = (opcode_i == AUNLOCK);
assign decode_o.tag_read_op = ~decode_o.tagst_op;
// atomic extension
always_comb begin
decode_o.atomic_op = 1'b1;
// These subopcodes are intended to match the low 4 bits of the
// corresponding bsg_cache_pkt opcode, to simplify decoding
unique case (opcode_i)
AMOSWAP_W, AMOSWAP_D: decode_o.amo_subop = e_cache_amo_swap;
AMOADD_W, AMOADD_D: decode_o.amo_subop = e_cache_amo_add;
AMOXOR_W, AMOXOR_D: decode_o.amo_subop = e_cache_amo_xor;
AMOAND_W, AMOAND_D: decode_o.amo_subop = e_cache_amo_and;
AMOOR_W, AMOOR_D: decode_o.amo_subop = e_cache_amo_or;
AMOMIN_W, AMOMIN_D: decode_o.amo_subop = e_cache_amo_min;
AMOMAX_W, AMOMAX_D: decode_o.amo_subop = e_cache_amo_max;
AMOMINU_W, AMOMINU_D: decode_o.amo_subop = e_cache_amo_minu;
AMOMAXU_W, AMOMAXU_D: decode_o.amo_subop = e_cache_amo_maxu;
default: begin
decode_o.atomic_op = 1'b0;
decode_o.amo_subop = e_cache_amo_swap;
end
endcase
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_manager_0_1,frequency_analyzer_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=10,PIXEL0_INDEX=63,PIXEL1_INDEX=511,PIXEL2_INDEX=1000,PIXEL0_FREQUENCY0=5000,PIXEL0_FREQUENCY1=10000,PIXEL1_FREQUENCY0=15000,PIXEL1_FREQUENCY1=20000,PIXEL2_FREQUENCY0=40000,PIXEL2_FREQ\
UENCY1=50000,FREQUENCY_DEVIATION=20,CLOCK_FREQUENCY=100000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [9 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [9 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(10),
.PIXEL0_INDEX(63),
.PIXEL1_INDEX(511),
.PIXEL2_INDEX(1000),
.PIXEL0_FREQUENCY0(5000),
.PIXEL0_FREQUENCY1(10000),
.PIXEL1_FREQUENCY0(15000),
.PIXEL1_FREQUENCY1(20000),
.PIXEL2_FREQUENCY0(40000),
.PIXEL2_FREQUENCY1(50000),
.FREQUENCY_DEVIATION(20),
.CLOCK_FREQUENCY(100000000)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int a[1000000]; struct cr { int l; int r; int d; } op[1000000]; long long int kt[1000000]; long long int ktt[1000000]; long long int fiop[1000000]; long long int vp[1000000]; long long int vpp[1000000]; long long int mba[1000000]; int main() { int n, m, k, b, c, i, j; long long int uv; cin >> n >> m >> k; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (i = 1; i <= m; i++) { cin >> op[i].l >> op[i].r >> op[i].d; } for (i = 0; i < k; i++) { cin >> b >> c; kt[b]++; ktt[c]--; } b = 0; for (i = 1; i <= m; i++) { b += kt[i]; fiop[i] += b; b += ktt[i]; } uv = 0; for (i = 1; i <= m; i++) { uv = (op[i].d * fiop[i]); vp[op[i].l] += uv; vpp[op[i].r] -= uv; } uv = 0; for (i = 0; i <= 100010; i++) { uv += vp[i]; mba[i] += uv; uv += vpp[i]; } for (i = 1; i <= n; i++) { a[i] += mba[i]; cout << a[i] << ; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int T; long long a, b, c; for (scanf( %d , &T); T; T--) { cin >> a >> b >> c; if (a >= c) { printf( -1 ); } else printf( 1 ); if (a * b > c) printf( %I64d n , b); else printf( -1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void readi(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readll(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readc(char &x) { char c; while ((c = getchar()) == ) ; x = c; } void writes(string s) { puts(s.c_str()); } void writeln() { writes( ); } void writei(int x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } void writell(long long x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } long long n, m, li, ns, i, j, k, l, mod = 1e9 + 7, x, y, dp[123456][12][3], vis[123456]; vector<long long> e[123456]; void dfs(int x, int fa) { long long i; if (vis[x]) return; vis[x] = 1; dp[x][0][2] = ns - 1; dp[x][1][1] = 1; dp[x][0][0] = m - ns; for (i = 0; i < e[x].size(); i++) { if (e[x][i] == fa) continue; dfs(e[x][i], x); for (j = li; ~j; j--) { long long mem[3] = {0, 0, 0}; for (k = 0; k <= j; k++) { (mem[0] += (dp[x][j - k][0] * (dp[e[x][i]][k][0] + dp[e[x][i]][k][2]))) %= mod; (mem[1] += (dp[x][j - k][1] * (dp[e[x][i]][k][2]))) %= mod; (mem[2] += (dp[x][j - k][2] * (dp[e[x][i]][k][0] + dp[e[x][i]][k][1] + dp[e[x][i]][k][2]))) %= mod; } for (k = 0; k < 3; k++) dp[x][j][k] = mem[k]; } } } int main() { readll(n); readll(m); for (i = 1; i < n; i++) { readll(x); readll(y); e[x].push_back(y); e[y].push_back(x); } readll(ns); readll(li); dfs(1, 0); long long res = 0; for (i = 0; i <= li; i++) (res += dp[1][i][0] + dp[1][i][1] + dp[1][i][2]) %= mod; writell(res); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int l = s.length(); cout << 4 << endl; cout << R << l - 1 << endl; cout << L << 2 << endl; cout << L << l + 1 << endl; cout << L << 2 << endl; return 0; }
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module displaysigned();
reg signed [7:0] foo;
reg [7:0] bar;
initial begin
foo = -8'sd2;
bar = foo;
$display("foo=%0d bar=%0d $signed(bar)=%0d",
foo, bar, $signed(bar));
$finish;
end
endmodule
|
/***************************************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* Retrived from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html *
***************************************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1024; int dp[N]; int n, k; vector<int> ans; int f(int i) { if (i >= n) return 0; if (i + k >= n) return 1e9; if (dp[i] != -1) return dp[i]; return dp[i] = f(i + 2 * k + 1) + 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; memset(dp, -1, sizeof dp); int r = 1e9, best = -1; for (int i = 0, ThxDem = k + 1; i < ThxDem; ++i) if (r > f(i + k + 1) + 1) { r = f(i + k + 1) + 1; best = i; } while (best < n) { ans.push_back(best + 1); best += 2 * k + 1; } assert(((int)(ans).size()) == r); cout << r << n ; for (int x : ans) cout << x << ; cout << n ; }
|
module fifo_128_8(
input wire i_clk,
input wire i_rst_n,
input wire i_slv_valid,
output wire o_slv_rdy,
input wire [63:0] i_slv_data,
output reg [7:0] o_mst_data,
output wire o_mst_valid,
input i_mst_rdy
);
reg [63:0] mem [0:15];
reg [3:0] wr_addr;
reg [6:0] rd_addr;
reg [7:0] data_count;
assign o_mst_valid = (data_count > 0) ? 1'b1 : 1'b0;
assign o_slv_rdy = (data_count < 120) ? 1'b1 : 1'b0;
assign valid_wr = i_slv_valid & o_slv_rdy;
assign valid_rd = o_mst_valid & i_mst_rdy;
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
wr_addr <= 0;
end
else
begin
if(valid_wr)
begin
mem[wr_addr] <= i_slv_data;
wr_addr <= wr_addr + 1;
end
end
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
rd_addr <= 0;
end
else
begin
if(valid_rd)
begin
rd_addr <= rd_addr + 1'b1;
end
end
end
always@(*)
begin
case(rd_addr[2:0])
0:begin
o_mst_data <= mem[rd_addr[6:3]][7:0];
end
1:begin
o_mst_data <= mem[rd_addr[6:3]][15:8];
end
2:begin
o_mst_data <= mem[rd_addr[6:3]][23:16];
end
3:begin
o_mst_data <= mem[rd_addr[6:3]][31:24];
end
4:begin
o_mst_data <= mem[rd_addr[6:3]][39:32];
end
5:begin
o_mst_data <= mem[rd_addr[6:3]][47:40];
end
6:begin
o_mst_data <= mem[rd_addr[6:3]][55:48];
end
7:begin
o_mst_data <= mem[rd_addr[6:3]][63:56];
end
endcase
end
always @(posedge i_clk)
begin
if(!i_rst_n)
begin
data_count <= 0;
end
else
begin
if(valid_wr & !valid_rd)
data_count <= data_count + 8;
else if(!valid_wr & valid_rd)
data_count <= data_count - 1'b1;
else if(valid_wr & valid_rd)
data_count <= data_count + 7;
end
end
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// --
// TLB management unit for the ZAP processor. The TLB units use single cycle --
// clearing memories since TLBs are shallow. --
// --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_tlb #(
parameter LPAGE_TLB_ENTRIES = 8,
parameter SPAGE_TLB_ENTRIES = 8,
parameter SECTION_TLB_ENTRIES = 8,
parameter FPAGE_TLB_ENTRIES = 8
) (
// Clock and reset.
input wire i_clk,
input wire i_reset,
// From cache FSM (processor)
input wire [31:0] i_address,
input wire [31:0] i_address_nxt,
input wire i_rd,
input wire i_wr,
// CPSR, SR, DAC register.
input wire [31:0] i_cpsr,
input wire [1:0] i_sr,
input wire [31:0] i_dac_reg,
input wire [31:0] i_baddr,
// From CP15.
input wire i_mmu_en,
input wire i_inv,
// To cache FSM.
output wire [31:0] o_phy_addr,
output wire [7:0] o_fsr,
output wire [31:0] o_far,
output wire o_fault,
output wire o_cacheable,
output wire o_busy,
// Wishbone memory interface - Needs to go through some OR gates.
output wire o_wb_stb_nxt,
output wire o_wb_cyc_nxt,
output wire [31:0] o_wb_adr_nxt,
output wire o_wb_wen_nxt,
output wire [3:0] o_wb_sel_nxt,
input wire [31:0] i_wb_dat,
output wire [31:0] o_wb_dat_nxt,
input wire i_wb_ack
);
// ----------------------------------------------------------------------------
assign o_wb_dat_nxt = 32'd0;
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
wire [`SECTION_TLB_WDT-1:0] setlb_wdata, setlb_rdata;
wire [`LPAGE_TLB_WDT-1:0] lptlb_wdata, lptlb_rdata;
wire [`SPAGE_TLB_WDT-1:0] sptlb_wdata, sptlb_rdata;
wire [`FPAGE_TLB_WDT-1:0] fptlb_wdata, fptlb_rdata;
wire sptlb_wen, lptlb_wen, setlb_wen;
wire sptlb_ren, lptlb_ren, setlb_ren;
wire fptlb_ren, fptlb_wen;
wire walk;
wire [7:0] fsr;
wire [31:0] far;
wire cacheable;
wire [31:0] phy_addr;
wire [31:0] tlb_address;
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`SECTION_TLB_WDT), .DEPTH(SECTION_TLB_ENTRIES))
u_section_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (setlb_wdata),
.i_wen (setlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__SECTION_INDEX]),
.i_waddr (tlb_address[`VA__SECTION_INDEX]),
.o_rdata (setlb_rdata),
.o_rdav (setlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`LPAGE_TLB_WDT), .DEPTH(LPAGE_TLB_ENTRIES))
u_lpage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (lptlb_wdata),
.i_wen (lptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__LPAGE_INDEX]),
.i_waddr (tlb_address[`VA__LPAGE_INDEX]),
.o_rdata (lptlb_rdata),
.o_rdav (lptlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`SPAGE_TLB_WDT), .DEPTH(SPAGE_TLB_ENTRIES))
u_spage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (sptlb_wdata),
.i_wen (sptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__SPAGE_INDEX]),
.i_waddr (tlb_address[`VA__SPAGE_INDEX]),
.o_rdata (sptlb_rdata),
.o_rdav (sptlb_ren)
);
// ----------------------------------------------------------------------------
zap_mem_inv_block #(.WIDTH(`FPAGE_TLB_WDT), .DEPTH(FPAGE_TLB_ENTRIES))
u_fpage_tlb (
.i_clk (i_clk),
.i_reset (i_reset),
.i_wdata (fptlb_wdata),
.i_wen (fptlb_wen),
.i_ren (1'd1),
.i_inv (i_inv | !i_mmu_en),
.i_raddr (i_address_nxt[`VA__FPAGE_INDEX]),
.i_waddr (tlb_address[`VA__FPAGE_INDEX]),
.o_rdata (fptlb_rdata),
.o_rdav (fptlb_ren)
);
// ----------------------------------------------------------------------------
zap_tlb_check #(
.LPAGE_TLB_ENTRIES(LPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES(SPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES(FPAGE_TLB_ENTRIES)
)
u_zap_tlb_check (
.i_mmu_en (i_mmu_en),
.i_va (i_address),
.i_rd (i_rd),
.i_wr (i_wr),
.i_cpsr (i_cpsr),
.i_sr (i_sr),
.i_dac_reg (i_dac_reg),
.i_sptlb_rdata (sptlb_rdata),
.i_sptlb_rdav (sptlb_ren),
.i_lptlb_rdata (lptlb_rdata),
.i_lptlb_rdav (lptlb_ren),
.i_setlb_rdata (setlb_rdata),
.i_setlb_rdav (setlb_ren),
.i_fptlb_rdata (fptlb_rdata),
.i_fptlb_rdav (fptlb_ren),
.o_walk (walk),
.o_fsr (fsr),
.o_far (far),
.o_cacheable (cacheable),
.o_phy_addr (phy_addr)
);
// ----------------------------------------------------------------------------
zap_tlb_fsm #(
.LPAGE_TLB_ENTRIES (LPAGE_TLB_ENTRIES),
.SPAGE_TLB_ENTRIES (SPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES (SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES (FPAGE_TLB_ENTRIES)
) u_zap_tlb_fsm (
.o_unused_ok (), // UNCONNECTED. For lint.
.i_clk (i_clk),
.i_reset (i_reset),
.i_mmu_en (i_mmu_en),
.i_baddr (i_baddr),
.i_address (i_address),
.i_walk (walk),
.i_fsr (fsr),
.i_far (far),
.i_cacheable (cacheable),
.i_phy_addr (phy_addr),
.o_fsr (o_fsr),
.o_far (o_far),
.o_fault (o_fault),
.o_phy_addr (o_phy_addr),
.o_cacheable (o_cacheable),
.o_busy (o_busy),
.o_setlb_wdata (setlb_wdata),
.o_setlb_wen (setlb_wen),
.o_sptlb_wdata (sptlb_wdata),
.o_sptlb_wen (sptlb_wen),
.o_lptlb_wdata (lptlb_wdata),
.o_lptlb_wen (lptlb_wen),
.o_fptlb_wdata (fptlb_wdata),
.o_fptlb_wen (fptlb_wen),
.o_address (tlb_address),
.o_wb_cyc (),
.o_wb_stb (),
.o_wb_wen (o_wb_wen_nxt),
.o_wb_sel (),
.o_wb_adr (),
.i_wb_dat (i_wb_dat),
.i_wb_ack (i_wb_ack),
.o_wb_sel_nxt (o_wb_sel_nxt),
.o_wb_cyc_nxt (o_wb_cyc_nxt),
.o_wb_stb_nxt (o_wb_stb_nxt),
.o_wb_adr_nxt (o_wb_adr_nxt)
);
// ----------------------------------------------------------------------------
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const long long INF(0x3f3f3f3f3f3f3f3fll); const long long inf(0x3f3f3f3f); template <typename T> void read(T &res) { bool flag = false; char ch; while (!isdigit(ch = getchar())) (ch == - ) && (flag = true); for (res = ch - 48; isdigit(ch = getchar()); res = (res << 1) + (res << 3) + ch - 48) ; flag && (res = -res); } template <typename T> void Out(T x) { if (x < 0) putchar( - ), x = -x; if (x > 9) Out(x / 10); putchar(x % 10 + 0 ); } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long lcm(long long a, long long b) { return a * b / gcd(a, b); } long long pow_mod(long long x, long long n, long long mod) { long long res = 1; while (n) { if (n & 1) res = res * x % mod; x = x * x % mod; n >>= 1; } return res; } long long fact_pow(long long n, long long p) { long long res = 0; while (n) { n /= p; res += n; } return res; } long long mult(long long a, long long b, long long p) { a %= p; b %= p; long long r = 0, v = a; while (b) { if (b & 1) { r += v; if (r > p) r -= p; } v <<= 1; if (v > p) v -= p; b >>= 1; } return r; } long long quick_pow(long long a, long long b, long long p) { long long r = 1, v = a % p; while (b) { if (b & 1) r = mult(r, v, p); v = mult(v, v, p); b >>= 1; } return r; } bool CH(long long a, long long n, long long x, long long t) { long long r = quick_pow(a, x, n); long long z = r; for (long long i = 1; i <= t; i++) { r = mult(r, r, n); if (r == 1 && z != 1 && z != n - 1) return true; z = r; } return r != 1; } bool Miller_Rabin(long long n) { if (n < 2) return false; if (n == 2) return true; if (!(n & 1)) return false; long long x = n - 1, t = 0; while (!(x & 1)) { x >>= 1; t++; } srand(time(NULL)); long long o = 8; for (long long i = 0; i < o; i++) { long long a = rand() % (n - 1) + 1; if (CH(a, n, x, t)) return false; } return true; } void exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return; } exgcd(b, a % b, x, y); long long t = x; x = y, y = t - (a / b) * y; } long long inv(long long a, long long b) { long long x, y; return exgcd(a, b, x, y), (x % b + b) % b; } long long crt(long long x, long long p, long long mod) { return inv(p / mod, mod) * (p / mod) * x; } long long fac(long long x, long long a, long long b) { if (!x) return 1; long long ans = 1; for (long long i = 1; i <= b; i++) if (i % a) ans *= i, ans %= b; ans = pow_mod(ans, x / b, b); for (long long i = 1; i <= x % b; i++) if (i % a) ans *= i, ans %= b; return ans * fac(x / a, a, b) % b; } long long C(long long n, long long m, long long a, long long b) { long long N = fac(n, a, b), M = fac(m, a, b), Z = fac(n - m, a, b), sum = 0, i; for (i = n; i; i = i / a) sum += i / a; for (i = m; i; i = i / a) sum -= i / a; for (i = n - m; i; i = i / a) sum -= i / a; return N * pow_mod(a, sum, b) % b * inv(M, b) % b * inv(Z, b) % b; } long long exlucas(long long n, long long m, long long p) { long long t = p, ans = 0, i; for (i = 2; i * i <= p; i++) { long long k = 1; while (t % i == 0) { k *= i, t /= i; } ans += crt(C(n, m, i, k), p, k), ans %= p; } if (t > 1) ans += crt(C(n, m, t, t), p, t), ans %= p; return ans % p; } const long long N = 3e5 + 10; signed main() { std::ios::sync_with_stdio(false); long long t; cin >> t; while (t--) { long long n; cin >> n; cout << n << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 2e9; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline bool isPrime(long long x) { if (x <= 1) return 0; if (x <= 3) return 1; if (!(x % 2) || !(x % 3)) return 0; long long s = sqrt(1.0 * x) + EPS; for (long long i = 5; i <= s; i += 6) { if (!(x % i) || !(x % (i + 2))) return 0; } return 1; } inline long long fpow(long long n, long long k, long long p = 2e18) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } inline int inv(int a, long long p = 2e18) { return fpow(a, p - 2, p); } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } const int N = 3e5 + 5; long long n, m; long long a[N]; vector<int> adj[N]; void Solve() { cin >> n; vector<pair<int, int> > edges; map<pair<int, int>, int> mp; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); edges.push_back({u, v}); } int cnt = 0; for (int i = 1; i <= n; i++) { if (int((adj[i]).size()) == 1 && !mp.count({i, adj[i][0]})) { mp[{i, adj[i][0]}] = mp[{adj[i][0], i}] = cnt++; } } for (auto p : edges) { int u = p.first; int v = p.second; if (mp.count({u, v})) { cout << mp[{u, v}] << n ; } else { cout << cnt++ << n ; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); int query = 1; int start = 1000 * clock() / CLOCKS_PER_SEC; while (query--) Solve(); cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC - start << ms n ; }
|
#include <bits/stdc++.h> using namespace std; void read(long long a = 0) { freopen( in , r , stdin); if (a) freopen( out , w , stdout); } long long a[100009 * 10], b[100009 * 10]; long long n, m; bool bs(long long num) { bool vis[100009 * 10] = {}; long long space = 0; for (int i = num; i >= 0; i--) { if (a[i] && !vis[a[i]]) { vis[a[i]] = 1; space += b[a[i] - 1]; } else { space--; space = max(space, 0ll); } } for (int i = 1; i <= m; i++) if (!vis[i]) return 0; if (space == 0) return 1; else return 0; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> b[i]; long long lo = 0, hi = n + 1; while (lo < hi) { long long mid = (lo + hi - 1) >> 1; if (bs(mid)) hi = mid; else lo = mid + 1; } if (hi == n + 1) cout << -1 ; else cout << hi + 1; }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_128_49.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_128_49 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [48:0] data;
input rdreq;
input wrreq;
output empty;
output [48:0] q;
output [7:0] usedw;
wire sub_wire0;
wire [48:0] sub_wire1;
wire [7:0] sub_wire2;
wire empty = sub_wire0;
wire [48:0] q = sub_wire1[48:0];
wire [7:0] usedw = sub_wire2[7:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.usedw (sub_wire2),
.almost_empty (),
.almost_full (),
.full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 49,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "49"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "49"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "49"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 49 0 INPUT NODEFVAL "data[48..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 49 0 OUTPUT NODEFVAL "q[48..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 49 0 data 0 0 49 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 49 0 @q 0 0 49 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128_49_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; const int N = 100005; const long double INF = 1e18; const long double PI = acos(-1.0); int n; pair<long long, long long> o, origin, p[N]; long long r_1 = 0; long double r_2 = INF; long long sqDist(pair<long long, long long> a, pair<long long, long long> b) { return (a.first - b.first) * (a.first - b.first) + (a.second - b.second) * (a.second - b.second); } bool isObtuse(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c) { long long ab = sqDist(a, b), bc = sqDist(b, c), ca = sqDist(c, a); return ab + bc <= ca; } long double minDist(pair<long long, long long> a, pair<long long, long long> b) { long double diff_x = b.first - a.first, diff_y = b.second - a.second; if (diff_x == 0 and diff_y == 0) { diff_x = a.first; diff_y = a.second; return diff_x * diff_x + diff_y * diff_y; } long double t = (-a.first * diff_x - a.second * diff_y) / (1.0 * diff_x * diff_x + 1.0 * diff_y * diff_y); if (t < 0) { diff_x = a.first; diff_y = a.second; } else if (t > 1) { diff_x = b.first; diff_y = b.second; } else { diff_x = a.first + t * diff_x; diff_y = a.second + t * diff_y; } return diff_x * diff_x + diff_y * diff_y; } int main() { origin = pair<long long, long long>(0, 0); scanf( %d %lld %lld , &n, &o.first, &o.second); for (int i = 0; i < n; ++i) { scanf( %lld %lld , &p[i].first, &p[i].second); p[i].first -= o.first, p[i].second -= o.second; r_1 = max(r_1, sqDist(p[i], origin)); r_2 = min(r_2, (long double)sqDist(p[i], origin)); } p[n] = p[0]; for (int i = 0; i < n; ++i) { r_2 = min(r_2, minDist(p[i], p[i + 1])); } long double ans = max((long double)0.0, PI * (r_1 - r_2)); printf( %0.16f n , (double)ans); return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V
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#include <bits/stdc++.h> using namespace std; const int N = 600050; long long a[N], dp[N][3]; int main() { int n, x; scanf( %d%d , &n, &x); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } long long ans = 0; for (int i = 1; i <= n; i++) { dp[i][0] = max(dp[i][0], max(dp[i - 1][0], 0ll) + a[i]); dp[i][1] = max(dp[i][1], max(dp[i - 1][0], 0ll) + a[i] * x); dp[i][1] = max(dp[i][1], dp[i - 1][1] + a[i] * x); dp[i][2] = max(dp[i][2], max(dp[i - 1][1], dp[i - 1][2]) + a[i]); ans = max(max(ans, dp[i][0]), max(dp[i][1], dp[i][2])); } printf( %lld n , ans); }
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#include <bits/stdc++.h> using namespace std; int n, a[1005]; long long dp[1005]; long long dpsum[1005]; bool b[1005]; long long ch[1005][1005]; long long gc(int c, int x) { if (x == 0 || c == x) return 1; if (!ch[c][x]) { ch[c][x] = (gc(c - 1, x - 1) + gc(c - 1, x)) % 998244353; } return ch[c][x]; } int getdp(int x) { if (!b[x]) { b[x] = 1; if (a[x] > 0) { for (int i = x + a[x] + 1; i <= n + 1; ++i) { dp[x] = (dp[x] + gc(i - x - 2, a[x] - 1) * (1LL + dpsum[i])) % 998244353; } } } return dp[x]; } int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } long long ans = 0; for (int i = n; i >= 1; --i) { dpsum[i] = dpsum[i + 1] + getdp(i); dpsum[i] %= 998244353; } for (int i = 1; i <= n; ++i) { ans = ans + getdp(i); ans %= 998244353; } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; if (s.size() == 1) { if (s[0] == ? ) printf( a n ); else cout << s << n ; } else { int f = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == s[i + 1] && s[i] != ? ) { f = 1; break; } } if (f == 1) printf( -1 n ); else { char ch = a ; for (int i = 0; i < s.size() - 1; i++) { if (s[i] == ? && i == 0) { for (char c = a ; c <= c ; c++) { if (s[i + 1] != c) { s[i] = c; break; } } } else if (s[i] == ? ) { for (char c = a ; c <= c ; c++) { if (s[i + 1] != c && s[i - 1] != c) { s[i] = c; break; } } } } if (s[s.size() - 1] == ? ) { for (char c = a ; c <= c ; c++) { if (s[s.size() - 2] != c) { s[s.size() - 1] = c; break; } } } cout << s << n ; } } } }
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#include <bits/stdc++.h> using namespace std; long long a = 0, b = 0, f = 0, t = 0, x[101010], s2 = 0, s3 = 0, i = 0, j = 0, p = 0, k = 0; string d1, d2, d3; int main() { cin >> a >> p; for (b = 1; b <= a; b++) { cin >> f; if (f > p) s2 += 2; else s2 += 1; } cout << s2; }
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#include <bits/stdc++.h> using namespace std; string ans = ; set<int> s[26]; map<int, bool> vis; void solve(char a) { ans += a; vis[a - a ] = true; for (auto it : s[a - a ]) { if (!vis[it - a ]) { solve(it); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { string str; cin >> str; int n = str.length(); string alp = abcdefghijklmnopqrstuvwxyz ; if (n == 1) { cout << YES << endl; cout << alp << endl; continue; } for (int i = 0; i < 26; i++) s[i].clear(); vis.clear(); ans = ; for (long long int i = 1; i < n - 1; i++) { s[str[i] - a ].insert(str[i - 1]); s[str[i] - a ].insert(str[i + 1]); } s[str[0] - a ].insert(str[1]); s[str[n - 1] - a ].insert(str[n - 2]); int flag = 0, cnt = 0; char st; for (long long int i = 0; i < 26; i++) { if (s[i].size() > 2) { flag = 1; } else if (s[i].size() == 1) { cnt++; st = alp[i]; } } if (flag or cnt < 2) { cout << NO << endl; continue; } cout << YES << endl; solve(st); for (int i = 0; i < 26; i++) { if (!vis[alp[i] - a ]) ans += alp[i]; } cout << ans << endl; } return 0; }
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/*
* Testbench for Zet processor
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module test_zet;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
wire [19:0] pc;
reg clk;
reg rst;
reg [15:0] io_reg;
reg intr;
// Wishbone master interface - fetch
wire [15:0] wbf_dat_i;
wire [19:1] wbf_adr_o;
wire [ 1:0] wbf_sel_o;
wire wbf_cyc_o;
wire wbf_stb_o;
wire wbf_ack_i;
// Module instantiations
memory2prt mem0 (
.wb1_clk_i (clk),
.wb1_dat_o(wbf_dat_i),
.wb1_adr_i(wbf_adr_o),
.wb1_sel_i(wbf_sel_o),
.wb1_cyc_i(wbf_cyc_o),
.wb1_stb_i(wbf_stb_o),
.wb1_ack_o(wbf_ack_i),
.wb2_clk_i (clk),
.wb2_rst_i (rst),
.wb2_dat_i (dat_o),
.wb2_dat_o (mem_dat_i),
.wb2_adr_i (adr),
.wb2_we_i (we),
.wb2_sel_i (sel),
.wb2_stb_i (stb & !tga),
.wb2_cyc_i (cyc & !tga),
.wb2_ack_o (mem_ack)
);
zet zet (
.clk_i (clk),
.rst_i (rst),
// Wishbone master interface - fetch
.wbf_dat_i(wbf_dat_i),
.wbf_adr_o(wbf_adr_o),
.wbf_sel_o(wbf_sel_o),
.wbf_cyc_o(wbf_cyc_o),
.wbf_stb_o(wbf_stb_o),
.wbf_ack_i(wbf_ack_i),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.intr (1'b0),
.inta (inta),
.iid (4'h0),
.pc (pc)
);
// Assignments
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = inta ? 16'd3 : (tga ? io_dat_i : mem_dat_i);
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
// Behaviour
// IO Stub
always @(posedge clk)
if (adr[15:1]==15'h5b && sel[1] && cyc && stb)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15'h5c & sel[0] && cyc && stb)
io_reg[15:8] <= dat_o[7:0];
always #1.5 clk = ~clk;
initial
begin
intr <= 1'b0;
clk <= 1'b1;
rst <= 1'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
#1000 intr <= 1'b1;
//@(posedge inta)
@(posedge clk) intr <= 1'b0;
end
initial
begin
$readmemh("data.rtlrom", mem0.ram1, 19'h78000);
$readmemh("data.rtlrom", mem0.ram2, 19'h78000);
// $readmemb("../rtl/micro_rom.dat",
// zet.core.micro_data.micro_rom.rom);
end
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T> T sqr(T x) { return x * x; } template <typename T> T abs(T x) { return x < 0 ? -x : x; } template <typename T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } set<vector<int> > s; vector<pair<char, pair<int, int> > > ans; bool rec(vector<int>& a) { if (a.size() == 1) { return a[0] == 24; } if (s.find(a) != s.end()) { return false; } s.insert(a); for (size_t i = 0; i < a.size(); ++i) { for (size_t j = i + 1; j < a.size(); ++j) { vector<int> b = a; int x = a[i], y = a[j]; b.erase(b.begin() + j); b.erase(b.begin() + i); b.push_back(x + y); ans.push_back(make_pair( + , make_pair(x, y))); if (rec(b)) { return true; } b.pop_back(); ans.pop_back(); b.push_back(y - x); ans.push_back(make_pair( - , make_pair(y, x))); if (rec(b)) { return true; } b.pop_back(); ans.pop_back(); b.push_back(x - y); ans.push_back(make_pair( - , make_pair(x, y))); if (rec(b)) { return true; } b.pop_back(); ans.pop_back(); b.push_back(x * y); ans.push_back(make_pair( * , make_pair(x, y))); if (rec(b)) { return true; } b.pop_back(); ans.pop_back(); } } return false; } int main(int, char**) { ios_base::sync_with_stdio(false); int n; cin >> n; if (n < 4) { cout << NO << endl; return 0; } cout << YES << endl; vector<int> a; for (int i = 1; i <= n % 2 + 4; ++i) { a.push_back(i); } rec(a); for (int i = n % 2 + 4; i < n; i += 2) { ans.push_back(make_pair( - , make_pair(i + 2, i + 1))); ans.push_back(make_pair( * , make_pair(24, 1))); } for (size_t i = 0; i < ans.size(); ++i) { int x = ans[i].second.first; int y = ans[i].second.second; int r = -1; switch (ans[i].first) { case - : r = x - y; break; case + : r = x + y; break; case * : r = x * y; break; } cout << x << << ans[i].first << << y << = << r << endl; } fprintf(stderr, Time execute: %.3lf sec n , clock() / (double)CLOCKS_PER_SEC); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5; long long int n, x, y, b, a[3]; int main() { long long int x, y; cin >> x >> y; long long int a = 0; while (true) { if (a % 2 == 0) { if (x >= 2 && y >= 2) { x -= 2; y -= 2; } else { if (x >= 1 && y >= 12) { x--; y -= 12; } else { if (x >= 0 && y >= 22) { y -= 22; } else { break; } } } } else { if (x >= 0 && y >= 22) { y -= 22; } else { if (x >= 1 && y >= 12) { x--; y -= 12; } else { if (x >= 2 && y >= 2) { x -= 2; y -= 2; } else { break; } } } } a++; } if (a % 2 == 1) { cout << Ciel ; return 0; } cout << Hanako ; }
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#include <bits/stdc++.h> using namespace std; const long long N = 100005; string A; void solve() { long long n, mi = 0, pl = 0; cin >> A; A = + + A; n = A.size() - 1; stack<char> s; for (__typeof((n)) i = (1); i <= (n); i++) { if (s.empty()) s.push(A[i]); else if (s.top() == A[i]) s.pop(); else s.push(A[i]); } if (s.empty()) cout << Yes << n ; else cout << No << n ; } signed main() { long long t; ios_base::sync_with_stdio(false); t = 1; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; bool f = 0; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = 1; for (; isdigit(c); c = getchar()) x = x * 10 + (c ^ 48); if (f) x = -x; } template <typename F> inline void write(F x, char ed = n ) { static short st[30]; short tp = 0; if (x < 0) putchar( - ), x = -x; do st[++tp] = x % 10, x /= 10; while (x); while (tp) putchar( 0 | st[tp--]); putchar(ed); } template <typename T> inline void Mx(T &x, T y) { x < y && (x = y); } template <typename T> inline void Mn(T &x, T y) { x > y && (x = y); } const int N = 50005; int a[N], n; long long ask(int l, int r) { cout << ? << l << << r << endl; fflush(stdout); long long t; cin >> t; return t; } int main() { read(n); long long t1 = ask(1, 2), t2 = ask(1, 3), t3 = ask(2, 3); a[3] = t2 - t1, a[2] = t3 - a[3], a[1] = t1 - a[2]; for (int i = 4; i <= n; i++) a[i] = ask(i - 1, i) - a[i - 1]; cout << ! ; for (int i = 1; i <= n; i++) cout << a[i] << ; fflush(stdout); return 0; }
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// precompute lookup table for each digit? #include <iostream> #include <unordered_map> #include <utility> #include <algorithm> using namespace std; #define MP make_pair<int, int> int main() { unordered_map<int, int> lookup[10]; lookup[1].insert(MP(0, 1)); lookup[2].insert(MP(0, 2)); lookup[2].insert(MP(1, 21)); lookup[3].insert(MP(0, 3)); lookup[3].insert(MP(1, 13)); lookup[3].insert(MP(2, 23)); lookup[4].insert(MP(0, 4)); lookup[4].insert(MP(2, 14)); lookup[4].insert(MP(1, 41)); lookup[4].insert(MP(3, 43)); lookup[5].insert(MP(0, 5)); lookup[5].insert(MP(1, 51)); lookup[5].insert(MP(2, 52)); lookup[5].insert(MP(3, 53)); lookup[5].insert(MP(4, 54)); lookup[6].insert(MP(0, 6)); lookup[6].insert(MP(4, 16)); lookup[6].insert(MP(2, 26)); lookup[6].insert(MP(1, 61)); lookup[6].insert(MP(3, 63)); lookup[6].insert(MP(5, 65)); lookup[7].insert(MP(0, 7)); lookup[7].insert(MP(3, 17)); lookup[7].insert(MP(6, 27)); lookup[7].insert(MP(2, 37)); lookup[7].insert(MP(5, 47)); lookup[7].insert(MP(1, 57)); lookup[7].insert(MP(4, 67)); lookup[8].insert(MP(0, 8)); lookup[8].insert(MP(2, 18)); lookup[8].insert(MP(4, 28)); lookup[8].insert(MP(6, 38)); lookup[8].insert(MP(1, 81)); lookup[8].insert(MP(3, 83)); lookup[8].insert(MP(5, 85)); lookup[8].insert(MP(7, 87)); lookup[9].insert(MP(0, 9)); lookup[9].insert(MP(1, 19)); lookup[9].insert(MP(2, 29)); lookup[9].insert(MP(3, 39)); lookup[9].insert(MP(4, 49)); lookup[9].insert(MP(5, 59)); lookup[9].insert(MP(6, 69)); lookup[9].insert(MP(7, 79)); lookup[9].insert(MP(8, 89)); int t; cin >> t; while (t--) { int q, d; cin >> q >> d; for (int i = 0; i < q; ++i) { int x; cin >> x; int mod = x % d; if (lookup[d].at(mod) <= x) cout << YES << endl; else cout << NO << endl; } } }
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#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; long long mod = 1000000007LL; long long mod2 = 998244353LL; long long t, l, r; long long dp[5000005]; long long prm[5000005]; long long pw[5000005]; long long dfs(int x) { if (dp[x] >= 0) return dp[x]; if (x == 1) return dp[x] = 0LL; dp[x] = (long long)x * (long long)(x - 1) / 2LL; dp[x] %= mod; long long i; if (x > 2 && x % 2 == 0) { return dp[x] = (dfs(x / 2) + (2 * (2 - 1) / 2) % mod * (x / 2) % mod) % mod; } int d = prm[x]; if (d < 0) return dp[x]; return dp[x] = (dfs(x / d) + (d * (d - 1) / 2) % mod * (x / d) % mod) % mod; } long long getpw(long long x, long long y) { long long res = 1LL; while (y) { if (y & 1) res = res * x % mod; x = x * x % mod; y /= 2; } return res; } int main() { cin >> t >> l >> r; memset(prm, -1, sizeof(prm)); for (int i = 2; i * i <= r; ++i) { if (prm[i] < 0) { for (int j = 2 * i; j <= r; j += i) { if (prm[j] < 0) prm[j] = i; } } } pw[0] = 1LL; for (int i = 1; i <= r; ++i) { pw[i] = pw[i - 1] * (long long)t % mod; } memset(dp, -1, sizeof(dp)); long long res = 0LL; for (int i = 2; i <= r; ++i) { if (dp[i] < 0) { dfs(i); if (i >= l && i <= r) { long long tmp = dp[i] * pw[i - l] % mod; res = (res + tmp) % mod; } } } cout << res << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_4_V
`define SKY130_FD_SC_LS__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_4_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:53 maverickist
// verification is complete.
//
// Revision 1.2 2005/12/16 06:44:16 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module RMON (
Clk ,
Reset ,
//Tx_RMON
Tx_pkt_type_rmon ,
Tx_pkt_length_rmon ,
Tx_apply_rmon ,
Tx_pkt_err_type_rmon,
//Tx_RMON
Rx_pkt_type_rmon ,
Rx_pkt_length_rmon ,
Rx_apply_rmon ,
Rx_pkt_err_type_rmon,
//CPU
CPU_rd_addr ,
CPU_rd_apply ,
CPU_rd_grant ,
CPU_rd_dout
);
input Clk ;
input Reset ;
//Tx_RMON
input [2:0] Tx_pkt_type_rmon ;
input [15:0] Tx_pkt_length_rmon ;
input Tx_apply_rmon ;
input [2:0] Tx_pkt_err_type_rmon;
//Tx_RMON
input [2:0] Rx_pkt_type_rmon ;
input [15:0] Rx_pkt_length_rmon ;
input Rx_apply_rmon ;
input [2:0] Rx_pkt_err_type_rmon;
//CPU
input [5:0] CPU_rd_addr ;
input CPU_rd_apply ;
output CPU_rd_grant ;
output [31:0] CPU_rd_dout ;
//******************************************************************************
//interface signals
//******************************************************************************
wire Reg_apply_0 ;
wire [4:0] Reg_addr_0 ;
wire [15:0] Reg_data_0 ;
wire Reg_next_0 ;
wire Reg_apply_1 ;
wire [4:0] Reg_addr_1 ;
wire [15:0] Reg_data_1 ;
wire Reg_next_1 ;
wire [5:0] Addra ;
wire [31:0] Dina ;
wire [31:0] Douta ;
wire Wea ;
//******************************************************************************
assign RxAddrb=0;
assign TxAddrb=0;
RMON_addr_gen U_0_Rx_RMON_addr_gen(
.Clk (Clk ),
.Reset (Reset ),
//RMON (//RMON ),
.Pkt_type_rmon (Rx_pkt_type_rmon ),
.Pkt_length_rmon (Rx_pkt_length_rmon ),
.Apply_rmon (Rx_apply_rmon ),
.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
//Rmon_ctrl (//Rron_ctrl ),
.Reg_apply (Reg_apply_0 ),
.Reg_addr (Reg_addr_0 ),
.Reg_data (Reg_data_0 ),
.Reg_next (Reg_next_0 ),
//CPU (//CPU ),
.Reg_drop_apply ( ));
RMON_addr_gen U_0_Tx_RMON_addr_gen(
.Clk (Clk ),
.Reset (Reset ),
//RMON (//RMON ),
.Pkt_type_rmon (Tx_pkt_type_rmon ),
.Pkt_length_rmon (Tx_pkt_length_rmon ),
.Apply_rmon (Tx_apply_rmon ),
.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//Rmon_ctrl (//Rron_ctrl ),
.Reg_apply (Reg_apply_1 ),
.Reg_addr (Reg_addr_1 ),
.Reg_data (Reg_data_1 ),
.Reg_next (Reg_next_1 ),
//CPU (//CPU ),
.Reg_drop_apply ( ));
RMON_CTRL U_RMON_CTRL(
.Clk (Clk ),
.Reset (Reset ),
//RMON_CTRL (//RMON_CTRL ),
.Reg_apply_0 (Reg_apply_0 ),
.Reg_addr_0 (Reg_addr_0 ),
.Reg_data_0 (Reg_data_0 ),
.Reg_next_0 (Reg_next_0 ),
.Reg_apply_1 (Reg_apply_1 ),
.Reg_addr_1 (Reg_addr_1 ),
.Reg_data_1 (Reg_data_1 ),
.Reg_next_1 (Reg_next_1 ),
//dual-port ram (//dual-port ram ),
.Addra (Addra ),
.Dina (Dina ),
.Douta (Douta ),
.Wea (Wea ),
//CPU (//CPU ),
.CPU_rd_addr (CPU_rd_addr ),
.CPU_rd_apply (CPU_rd_apply ),
.CPU_rd_grant (CPU_rd_grant ),
.CPU_rd_dout (CPU_rd_dout )
);
RMON_dpram U_Rx_RMON_dpram(
.Reset (Reset ),
.Clk (Clk ),
//port-a for Rmon (//port-a for Rmon ),
.Addra (Addra ),
.Dina (Dina ),
.Douta ( ),
.Wea (Wea ),
//port-b for CPU (//port-b for CPU ),
.Addrb (Addra ),
.Doutb (Douta ));
endmodule
|
//`define USE_TEST_RAM
module uart_fifo
#(parameter TX_RAM_ADDRESS_BITS = 10,
RX_RAM_ADDRESS_BITS = 10)
(input reset,
input sys_clk,
input tx_wren, // When this goes high, there's new data for the fifo
input [7:0] tx_data,
input tx_accept, // UART signals when it can accepted tx data
input [7:0] rx_data,
input rx_data_ready,
input rx_accept, // User signal describes when it accepted rx data
output reg tx_out_wren, // High to tell UART that there's data. UART responds by pulsing tx_accept
output tx_fifo_full,
output reg tx_fifo_ram_wren, // pulled high to write new data into the fifo ram
output reg [7:0] tx_data_out,
output reg [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_read_address,
output reg [TX_RAM_ADDRESS_BITS-1:0] tx_fifo_ram_write_address,
output reg [7:0] rx_data_out,
output reg [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_read_address,
output reg [RX_RAM_ADDRESS_BITS-1:0] rx_fifo_ram_write_address,
output rx_fifo_full,
output reg rx_fifo_ram_wren,
output reg rx_data_out_ready
);
localparam FIFO_TX_SIZE = 1 << TX_RAM_ADDRESS_BITS;
localparam FIFO_RX_SIZE = 1 << RX_RAM_ADDRESS_BITS;
// Ring buffer content usage...need 1 extra bit for when the buffer is full
reg [TX_RAM_ADDRESS_BITS:0] tx_count;
assign tx_fifo_full = (tx_count == FIFO_TX_SIZE);
reg [RX_RAM_ADDRESS_BITS:0] rx_count;
assign rx_fifo_full = (rx_count == FIFO_RX_SIZE);
localparam TX_IDLE=2'd0, TX_WAIT_MEM=2'd1, TX_WAIT_UART=2'd2;
reg [1:0] tx_state;
wire write_tx_ram = tx_wren && ~tx_fifo_full;
reg rx_data_ready_wait;
wire write_rx_ram = rx_data_ready && ~rx_data_ready_wait && ~rx_fifo_full;
localparam RX_IDLE=2'd0, RX_WAIT_MEM1=2'd1, RX_WAIT_MEM2=2'd2, RX_WAIT_ACCEPT=2'd3;
reg [1:0] rx_state;
////////////////////////////////////////////////////////////////////////////////
// TX protocol
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
tx_fifo_ram_read_address <= {TX_RAM_ADDRESS_BITS{1'b0}};
`ifdef USE_TEST_RAM
tx_count <= FIFO_TX_SIZE;
tx_fifo_ram_write_address <= FIFO_TX_SIZE;
`else
tx_count <= 'b0;
tx_fifo_ram_write_address <= {TX_RAM_ADDRESS_BITS{1'b0}};
`endif
tx_fifo_ram_wren <= 'b0;
tx_data_out <= 8'b0;
tx_out_wren <= 'b0;
tx_state <= TX_IDLE;
end else begin
// Allow a write to memory as long as the fifo isn't full
tx_fifo_ram_wren <= write_tx_ram;
if(write_tx_ram)
tx_data_out <= tx_data;
// write_address will move only after written to it in the last cycle, so tx_fifo_ram_wren is used instead of the write_tx_ram wire
tx_fifo_ram_write_address <= tx_fifo_ram_write_address + (tx_fifo_ram_wren ? 1 : 0);
// tx_count will go down when the UART accepts data, and up when incoming data is received
// this logic allows for both to happen simultaneously:
tx_count <= tx_count + (((tx_state == TX_WAIT_UART) && tx_accept) ? -1 : 0) + ((write_tx_ram) ? 1 : 0);
case(tx_state)
TX_IDLE: begin
// This uses the previous value of tx_count
if((| tx_count) && ~tx_accept) begin
// There's data to send, and rdaddress is already on the line,
// so waiting 1 clock cycle (to make sure RAM is ready) should be good, then flip tx_out_wren high
tx_state <= TX_WAIT_MEM;
end
end
TX_WAIT_MEM: begin
// Byte is on the line, so tell UART it's ready and wait for accept
tx_out_wren <= 1'b1;
tx_state <= TX_WAIT_UART;
end
TX_WAIT_UART: begin
if(tx_accept) begin
tx_out_wren <= 1'b0;
// free up space now that the UART has taken the data
tx_fifo_ram_read_address <= tx_fifo_ram_read_address + 1'b1;
// wait for the UART to be ready again
tx_state <= TX_IDLE;
end
end
default: begin
tx_out_wren <= 1'b0;
tx_state <= TX_IDLE;
end
endcase
end
end
////////////////////////////////////////////////////////////////////////////////
// RX protocol
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
rx_fifo_ram_read_address <= {RX_RAM_ADDRESS_BITS{1'b0}};
rx_fifo_ram_write_address <= {RX_RAM_ADDRESS_BITS{1'b0}};
rx_count <= 'b0;
rx_fifo_ram_wren <= 'b0;
rx_data_out <= 8'b0;
rx_data_out_ready <= 1'b0;
rx_data_ready_wait <= 1'b0;
rx_state <= RX_IDLE;
end else begin
// Allow a write to memory as long as the fifo isn't full but only once when data_ready is high
rx_fifo_ram_wren <= write_rx_ram;
if(write_rx_ram) begin
rx_data_out <= rx_data;
rx_data_ready_wait <= 1'b1;
end else if(~rx_data_ready && rx_data_ready_wait) begin
rx_data_ready_wait <= 1'b0;
end
// write_address will move only after it was written to it in the last cycle, so rx_fifo_ram_wren is used instead of the write_rx_ram wire
rx_fifo_ram_write_address <= rx_fifo_ram_write_address + (rx_fifo_ram_wren ? 1 : 0);
// rx_count will go down when the user accepts data, and up when UART data is received.
// this logic allows for both to happen simultaneously:
rx_count <= rx_count + (((rx_state == RX_WAIT_ACCEPT) && rx_accept) ? -1 : 0) + ((write_rx_ram) ? 1 : 0);
case(rx_state)
RX_IDLE: begin
if((| rx_count) && ~rx_accept) begin
// read address is already on the line this cycle,
// If the data out of q is being registered, another clock cycle
// must occur, so waiting two cycles seems safer
rx_state <= RX_WAIT_MEM1;
end
end
RX_WAIT_MEM1: begin
rx_state <= RX_WAIT_MEM2;
end
RX_WAIT_MEM2: begin
// data is ready, trigger to user
rx_data_out_ready <= 1'b1;
rx_state <= RX_WAIT_ACCEPT;
end
RX_WAIT_ACCEPT: begin
if(rx_accept) begin
rx_data_out_ready <= 1'b0;
rx_fifo_ram_read_address <= rx_fifo_ram_read_address + 1'b1;
rx_state <= RX_IDLE;
end
end
default: begin
rx_data_out_ready <= 1'b0;
rx_state <= RX_IDLE;
end
endcase
end
end
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_signal_breakout (
write_command_data_in, // descriptor from the write FIFO
write_command_data_out, // reformated descriptor to the write master
// breakout of command information
write_address,
write_length,
write_park,
write_end_on_eop,
write_transfer_complete_IRQ_mask,
write_early_termination_IRQ_mask,
write_error_IRQ_mask,
write_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
write_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
// additional control information that needs to go out asynchronously with the command data
write_stop,
write_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] write_command_data_in;
output wire [255:0] write_command_data_out;
output wire [63:0] write_address;
output wire [31:0] write_length;
output wire write_park;
output wire write_end_on_eop;
output wire write_transfer_complete_IRQ_mask;
output wire write_early_termination_IRQ_mask;
output wire [7:0] write_error_IRQ_mask;
output wire [7:0] write_burst_count;
output wire [15:0] write_stride;
output wire [15:0] write_sequence_number;
input write_stop;
input write_sw_reset;
assign write_address[31:0] = write_command_data_in[63:32];
assign write_length = write_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign write_park = write_command_data_in[235];
assign write_end_on_eop = write_command_data_in[236];
assign write_transfer_complete_IRQ_mask = write_command_data_in[238];
assign write_early_termination_IRQ_mask = write_command_data_in[239];
assign write_error_IRQ_mask = write_command_data_in[247:240];
assign write_burst_count = write_command_data_in[127:120];
assign write_stride = write_command_data_in[159:144];
assign write_sequence_number = write_command_data_in[111:96];
assign write_address[63:32] = write_command_data_in[223:192];
end
else
begin
assign write_park = write_command_data_in[107];
assign write_end_on_eop = write_command_data_in[108];
assign write_transfer_complete_IRQ_mask = write_command_data_in[110];
assign write_early_termination_IRQ_mask = write_command_data_in[111];
assign write_error_IRQ_mask = write_command_data_in[119:112];
assign write_burst_count = 8'h00;
assign write_stride = 16'h0000;
assign write_sequence_number = 16'h0000;
assign write_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the write master (MSBs to LSBs)
assign write_command_data_out = {{132{1'b0}}, // zero pad the upper 132 bits
write_address[63:32],
write_stride,
write_burst_count,
write_sw_reset,
write_stop,
1'b0, // used to be the early termination bit so now it's reserved
write_end_on_eop,
write_length,
write_address[31:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { char ch = getchar(); int w = 1, c = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) w = -1; for (; isdigit(ch); ch = getchar()) c = (c << 1) + (c << 3) + (ch ^ 48); return w * c; } const int mod = 1e9 + 7, M = 1e6 + 10; struct node { long long x, y, z; node(long long _ = 1, long long __ = 0, long long ___ = 0) { x = _; y = __; z = ___; } } a[M]; long long b[M]; node operator+(node A, node B) { return node(A.x * B.x % mod, (A.y * B.x + B.y * A.x) % mod, (A.x * B.z + A.z * B.x + 2ll * A.y * B.y) % mod); } int n; int main() { n = read(); for (int i = (1); i <= (n); ++i) { int x = read(); a[x] = a[x] + node(2, x, 1ll * x * x % mod); } for (int len = 1; len <= 100000; len *= 10) { for (int j = (999999); j >= (0); --j) { if ((j / len) % 10) { a[j - len] = a[j - len] + a[j]; } } } for (int i = (0); i <= (999999); ++i) b[i] = a[i].z; for (int len = 1; len <= 100000; len *= 10) { for (int j = (0); j <= (999999); ++j) { if ((j / len) % 10) { b[j - len] += mod - b[j]; b[j - len] %= mod; } } } long long ans = 0; for (int i = (0); i <= (999999); ++i) { ans ^= b[i] * i; } cout << ans << n ; return 0; }
|
// $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2010 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Simulation Library Component
// / / Fujisan PHASER REF
// /__/ /\ Filename : PHASER_REF.v
// \ \ / \
// \__\/\__ \
//
// Revision: Comment:
// 23APR2010 Initial UNI/UNP/SIM from yml
// 02JUL2010 add functionality
// 29SEP2010 update functionality based on rtl
// add width checks
// 28OCT2010 CR580289 ref_clock_input_freq_MHz_min/max < vs <=
// 09NOV2010 CR581863 blocking statements, clock counts to lock.
// 11NOV2010 CR582599 warning in place of LOCK
// 01DEC2010 clean up display of real numbers
// 11JAN2011 586040 correct spelling XIL_TIMING vs XIL_TIMIMG
// 15AUG2011 621681 remove SIM_SPEEDUP make default
// 16APR2012 655365 else missing from delay_LOCKED always block
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PHASER_REF (
LOCKED,
CLKIN,
PWRDWN,
RST
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
parameter [0:0] IS_RST_INVERTED = 1'b0;
`ifdef XIL_TIMING
localparam in_delay = 0;
localparam INCLK_DELAY = 0;
localparam out_delay = 0;
`else
localparam in_delay = 1;
localparam INCLK_DELAY = 0;
localparam out_delay = 10;
`endif
localparam MODULE_NAME = "PHASER_REF";
localparam real REF_CLK_JITTER_MAX = 100.000;
output LOCKED;
input CLKIN;
input PWRDWN;
input RST;
tri0 GSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire delay_CLKIN;
wire delay_PWRDWN;
wire delay_RST;
wire delay_GSR;
reg delay_LOCKED = 1'b1;
real ref_clock_input_period = 11.0;
real ref_clock_input_freq_MHz = 1.68;
real time_last_rising_edge = 1.0;
real last_ref_clock_input_period = 13.0;
real last_ref_clock_input_freq_MHz = 1.69;
integer same_period_count = 0;
integer different_period_count = 0;
integer same_period_count_last = 0;
integer count_clks = 0;
real ref_clock_input_freq_MHz_min = 400.000; // valid min freq in MHz
real ref_clock_input_freq_MHz_max = 1066.000; // valid max freq in MHz
reg IS_PWRDWN_INVERTED_BIN = IS_PWRDWN_INVERTED;
reg IS_RST_INVERTED_BIN = IS_RST_INVERTED;
assign #(out_delay) LOCKED = delay_LOCKED;
assign #(INCLK_DELAY) delay_CLKIN = CLKIN;
assign #(in_delay) delay_PWRDWN = PWRDWN ^ IS_PWRDWN_INVERTED_BIN;
assign #(in_delay) delay_RST = RST ^ IS_RST_INVERTED_BIN;
assign delay_GSR = GSR;
always @(posedge delay_CLKIN)
begin
last_ref_clock_input_period <= ref_clock_input_period;
last_ref_clock_input_freq_MHz <= ref_clock_input_freq_MHz;
same_period_count_last <= same_period_count;
ref_clock_input_period <= $time - time_last_rising_edge;
ref_clock_input_freq_MHz <= 1e6/($time - time_last_rising_edge);
time_last_rising_edge <= $time/1.0;
if ( (delay_RST==0) && (delay_PWRDWN ==0) &&
(ref_clock_input_period - last_ref_clock_input_period <= REF_CLK_JITTER_MAX) &&
(last_ref_clock_input_period - ref_clock_input_period <= REF_CLK_JITTER_MAX) )
begin
if (same_period_count < 6) same_period_count <= same_period_count + 1;
if ( same_period_count >= 3 && same_period_count != same_period_count_last && different_period_count != 0)
begin
different_period_count <= 0; //reset different_period_count
end
end
else // detecting different clock-preiod
begin
different_period_count = different_period_count + 1;
if ( different_period_count >= 1 && same_period_count != 0 )
begin
same_period_count <= 0 ; //reset same_period_count
end
end
end
always @(posedge delay_CLKIN or posedge delay_RST or posedge delay_PWRDWN) begin
if ( delay_RST||delay_PWRDWN)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ((same_period_count >= 1) && (count_clks < 6))
begin
count_clks <= count_clks + 1;
end
else if (different_period_count >= 1)
begin
delay_LOCKED <= 1'b0;
count_clks <= 0;
end
else if ( (count_clks >= 5) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 >= ref_clock_input_freq_MHz_min ) &&
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 <= ref_clock_input_freq_MHz_max ) )
begin
delay_LOCKED <= 1'b1;
end
end
always @(posedge delay_CLKIN)
if ( (count_clks == 5) &&
( ((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 < ref_clock_input_freq_MHz_min) ||
((ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000 > ref_clock_input_freq_MHz_max) ) ) begin
$display("Warning: Invalid average CLKIN frequency detected = %4.3f MHz", (ref_clock_input_freq_MHz + last_ref_clock_input_freq_MHz)/2.000);
$display(" on %s instance %m at time %t ps.", MODULE_NAME, $time);
$display(" The valid CLKIN frequency range is:");
$display(" Minimum = %4.3f MHz", ref_clock_input_freq_MHz_min );
$display(" Maximum = %4.3f MHz", ref_clock_input_freq_MHz_max );
end
`ifdef XIL_TIMING
specify
$period (negedge CLKIN, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // PHASER_REF
`endcelldefine
|
/*
DCPU16 Verilog Implementation
Copyright (C) 2012 Shawn Tan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version. This program is
distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU Lesser General Public
License along with this program. If not, see
<http://www.gnu.org/licenses/>. */
/*
DCPU16 PIPELINE
===============
Consists of the following stages:
- Fetch (FE): fetches instructions from the FBUS.
- Decode (DE): decodes instructions.
- EA A (EA) : calculates EA for A
- EA B (EB) : calculates EA for B
- Load A (LA): loads operand A from ABUS.
- Load B (LB): loads operand B from ABUS.
- Execute (EX): performs the ALU operation.
- Save A (SA): saves operand A to the FBUS.
0| 1| 2| 3| 0| 1| 2| 3| 0| 1| 2| 3
FE|DE|EA|EB|LA|LB|EX|SA
FE|DE|EA|EB|LA|LB|EX|SA
FE|DE|EA|EB|LA|LB|EX|SA
*/
// 775@155
// 692@159
// 685@160
// 603@138
// 573@138
// 508@141
// 502@149
// 712@153
// 679@162
module dcpu16_cpu (/*AUTOARG*/
// Outputs
g_wre, g_stb, g_dto, g_adr, f_wre, f_stb, f_dto, f_adr,
// Inputs
rst, g_dti, g_ack, f_dti, f_ack, clk
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [15:0] f_adr; // From m0 of dcpu16_mbus.v
output [15:0] f_dto; // From x0 of dcpu16_alu.v
output f_stb; // From m0 of dcpu16_mbus.v
output f_wre; // From m0 of dcpu16_mbus.v
output [15:0] g_adr; // From m0 of dcpu16_mbus.v
output [15:0] g_dto; // From x0 of dcpu16_alu.v
output g_stb; // From m0 of dcpu16_mbus.v
output g_wre; // From m0 of dcpu16_mbus.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To c0 of dcpu16_ctl.v, ...
input f_ack; // To c0 of dcpu16_ctl.v, ...
input [15:0] f_dti; // To c0 of dcpu16_ctl.v, ...
input g_ack; // To m0 of dcpu16_mbus.v
input [15:0] g_dti; // To m0 of dcpu16_mbus.v
input rst; // To c0 of dcpu16_ctl.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CC; // From x0 of dcpu16_alu.v
wire bra; // From c0 of dcpu16_ctl.v
wire ena; // From m0 of dcpu16_mbus.v
wire [15:0] ireg; // From c0 of dcpu16_ctl.v
wire [3:0] opc; // From c0 of dcpu16_ctl.v
wire [1:0] pha; // From c0 of dcpu16_ctl.v
wire [15:0] regA; // From m0 of dcpu16_mbus.v
wire [15:0] regB; // From m0 of dcpu16_mbus.v
wire [15:0] regO; // From x0 of dcpu16_alu.v
wire [15:0] regR; // From x0 of dcpu16_alu.v
wire [2:0] rra; // From c0 of dcpu16_ctl.v
wire [15:0] rrd; // From r0 of dcpu16_regs.v
wire [2:0] rwa; // From c0 of dcpu16_ctl.v
wire [15:0] rwd; // From x0 of dcpu16_alu.v
wire rwe; // From c0 of dcpu16_ctl.v
wire wpc; // From m0 of dcpu16_mbus.v
// End of automatics
/*AUTOREG*/
dcpu16_ctl
c0 (/*AUTOINST*/
// Outputs
.ireg (ireg[15:0]),
.pha (pha[1:0]),
.opc (opc[3:0]),
.rra (rra[2:0]),
.rwa (rwa[2:0]),
.rwe (rwe),
.bra (bra),
// Inputs
.CC (CC),
.wpc (wpc),
.f_dti (f_dti[15:0]),
.f_ack (f_ack),
.clk (clk),
.ena (ena),
.rst (rst));
dcpu16_mbus
m0 (/*AUTOINST*/
// Outputs
.g_adr (g_adr[15:0]),
.g_stb (g_stb),
.g_wre (g_wre),
.f_adr (f_adr[15:0]),
.f_stb (f_stb),
.f_wre (f_wre),
.ena (ena),
.wpc (wpc),
.regA (regA[15:0]),
.regB (regB[15:0]),
// Inputs
.g_dti (g_dti[15:0]),
.g_ack (g_ack),
.f_dti (f_dti[15:0]),
.f_ack (f_ack),
.bra (bra),
.CC (CC),
.regR (regR[15:0]),
.rrd (rrd[15:0]),
.ireg (ireg[15:0]),
.regO (regO[15:0]),
.pha (pha[1:0]),
.clk (clk),
.rst (rst));
dcpu16_alu
x0 (/*AUTOINST*/
// Outputs
.f_dto (f_dto[15:0]),
.g_dto (g_dto[15:0]),
.rwd (rwd[15:0]),
.regR (regR[15:0]),
.regO (regO[15:0]),
.CC (CC),
// Inputs
.regA (regA[15:0]),
.regB (regB[15:0]),
.opc (opc[3:0]),
.clk (clk),
.rst (rst),
.ena (ena),
.pha (pha[1:0]));
dcpu16_regs
r0 (/*AUTOINST*/
// Outputs
.rrd (rrd[15:0]),
// Inputs
.rwd (rwd[15:0]),
.rra (rra[2:0]),
.rwa (rwa[2:0]),
.rwe (rwe),
.rst (rst),
.ena (ena),
.clk (clk));
endmodule // dcpu16
|
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