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#include <bits/stdc++.h> using namespace std; const int maxn = (int)(1e5) + 5; int l[maxn], r[maxn]; int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> l[i] >> r[i]; sort(l + 1, l + n + 1); sort(r + 1, r + n + 1); long long ret = n; for (int i = 1; i <= n; ++i) ret += max(l[i], r[i]); cout << ret << endl; return 0; }
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#include <bits/stdc++.h> template <class T1, class T2> inline bool cmin(T1 &a, const T2 &b) { return b < a ? (a = b, true) : false; } template <class T1, class T2> inline bool cmax(T1 &a, const T2 &b) { return a < b ? (a = b, true) : false; } template <class Type> Type read() { Type a; bool b; unsigned char c; while (c = getchar() - 48, (c > 9) & (c != 253)) ; for (a = (b = c == 253) ? 0 : c; (c = getchar() - 48) <= 9; a = a * 10 + c) ; return b ? -a : a; } int (*rd)() = read<int>; const int N = 2e5; std::vector<int> b[N], g[N]; int gcd(int x, int y) { return y ? gcd(y, x % y) : x; } std::pair<int, int> exgcd(int x, int y) { if (y == 0) return {1, 0}; int a, b; std::tie(b, a) = exgcd(y, x % y); return {a, b - x / y * a}; } void gg() { puts( -1 ); exit(0); } long long solve(int n, int m, const std::vector<int> &b, const std::vector<int> &g) { long long ans = -1; std::vector<std::pair<int, int>> pos; int inv = exgcd(n, m).second % n; if (inv < 0) inv += n; for (int i : b) pos.emplace_back((long long)i * inv % n, 0); for (int i : g) pos.emplace_back((long long)i * inv % n, 1); std::sort(pos.begin(), pos.end()); pos.resize(std::unique(pos.begin(), pos.end(), [](std::pair<int, int> p, std::pair<int, int> q) { return p.first == q.first; }) - pos.begin()); int i = pos.back().first; for (auto p : pos) { if ((p.first - 1 + n) % n != i) cmax(ans, (long long)(p.first - i - 1 + n) % n * m + (long long)i * m % n); if (p.second) cmax(ans, (long long)i * m % n); i = p.first; } return ans; } int main() { int n, m, d; long long ans = 0; std::vector<int> glob, glog; n = rd(), m = rd(), d = gcd(n, m); glob.resize(rd()); for (int &i : glob) i = rd(); glog.resize(rd()); for (int &i : glog) i = rd(); if (glob.size() + glog.size() < d) gg(); for (int i : glob) b[i % d].push_back(i / d); for (int i : glog) g[i % d].push_back(i / d); n /= d, m /= d; for (int i = 0; i < d; ++i) { if (b[i].empty() && g[i].empty()) gg(); cmax(ans, std::max(solve(n, m, b[i], g[i]), solve(m, n, g[i], b[i])) * d + i); } printf( %lld n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { char com[200]; char *p; int man = 0; int sum = 0; int i; int word; while (scanf( %c , com) == 1) { i = 1; while ((com[i] = getchar()) != n ) i++; com[i] = 0 ; word = 0; if (com[0] == + ) { man++; continue; } if (com[0] == - ) { man--; continue; } p = strchr(com, : ); p += 1; while (*(p++) != 0 ) { word++; } sum += word * man; } printf( %d , sum); }
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#include <bits/stdc++.h> int main(void) { double a, v, l, d, w, t = 0; scanf( %lf%lf%lf%lf%lf , &a, &v, &l, &d, &w); if (2 * a * d <= w * w || w >= v) { if (l * a * 2 >= v * v) { t += v / a; t += (l - v * v / (2 * a)) / v; } else { t += sqrt(2 * l / a); } } else if (2 * a * d >= 2 * v * v - w * w) { t += v / a; t += (v - w) / a; t += (d - (2 * v * v - w * w) / (2 * a)) / v; if (2 * a * (l - d) > v * v - w * w) { t += (v - w) / a; t += (l - d - (v * v - w * w) / (2 * a)) / v; } else { t += sqrt(2 * (l - d) / a + w * w / (a * a)) - w / a; } } else { t += (sqrt(a * d + w * w / 2) + sqrt(a * d + w * w / 2) - w) / a; if (2 * a * (l - d) > v * v - w * w) { t += (v - w) / a; t += (l - d - (v * v - w * w) / (2 * a)) / v; } else { t += sqrt(2 * (l - d) / a + w * w / (a * a)) - w / a; } } printf( %f n , t); return 0; }
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; using ld = long double; template <class T> using Table = vector<vector<T>>; const ld eps = 1e-9; template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> v) { os << ( << v.first << , << v.second << ) ; return os; } template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << ; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<vector<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const vector<set<T>> &v) { for (int i = 0; i < v.size(); i++) { if (i > 0) { os << endl; } os << v[i]; } return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &v) { int i = 0; for (auto it : v) { if (i > 0) { os << ; } os << it; i++; } return os; } using ll = long long int; pair<int, bool> get_c(const vector<vector<int>> &graph, int N) { vector<int> comes(N); vector<int> colors(N, -1); bool ok = true; queue<int> que; int sum = 0; for (int i = 0; i < N; ++i) { if (!comes[i]) { colors[i] = 0; sum++; que.emplace(i); while (!que.empty()) { int now = que.front(); comes[now] = true; que.pop(); for (auto e : graph[now]) { if (!comes[e]) { que.emplace(e); colors[e] = 1 ^ colors[now]; } if (colors[e] == colors[now]) ok = false; } } } } return make_pair(sum, ok); } ll int_pow(int a, int b) { if (b == 0) return 1; else return a * int_pow(a, b - 1); } int main() { ios::sync_with_stdio(false); int N, M; cin >> N >> M; vector<vector<int>> edges(N); for (int i = 0; i < M; ++i) { int u, v; cin >> u >> v; u--; v--; edges[u].push_back(v); edges[v].push_back(u); } auto p = get_c(edges, N); int C = p.first; bool b_ok = p.second; int isolated_v_cnt = 0; for (int i = 0; i < N; ++i) { if (edges[i].empty()) isolated_v_cnt++; } vector<vector<vector<ll>>> cnts(2, vector<vector<ll>>(2, vector<ll>(2))); cnts[1][0][0] = cnts[0][0][1] = int_pow(2, isolated_v_cnt); cnts[0][1][0] = b_ok ? int_pow(2, C) : 0; cnts[1][1][1] = int_pow(2, N); cnts[1][0][1] = int_pow(2, C); { int K = N / 2; vector<int> yys(1ll << (N - K)); for (int xx = 0; xx < (1ll << K); ++xx) { bool ok = true; vector<int> uses(K); for (int i = 0; i < K; ++i) { uses[i] = (xx & (1ll << i)) != 0; } int yy = 0; for (int i = 0; i < K; ++i) { for (auto e : edges[i]) { if (uses[i]) { if (e < K) { if (uses[i] && uses[e]) ok = false; } else { yy |= (1ll << (e - K)); } } } } if (ok) { yys[yy ^ ((1ll << (N - K)) - 1)]++; } else { } } for (int i = 0; i < (N - K); ++i) { for (int x = 0; x < (1ll << (N - K)); ++x) { if ((x & (1ll << i)) != 0) { yys[x ^ (1ll << i)] += yys[x]; } } } ll answer = 0; for (int yy = 0; yy < (1ll << (N - K)); ++yy) { bool ok = true; vector<int> uses(N - K); for (int i = 0; i < N - K; ++i) { uses[i] = (yy & (1ll << i)) != 0; } for (int i = 0; i < N - K; ++i) { for (auto e : edges[K + i]) { if (e >= K) { if (uses[i] && uses[e - K]) ok = false; } else { } } } if (ok) { answer += yys[yy]; } } cnts[1][1][0] = cnts[0][1][1] = answer; } if (!M) cnts[0][0][0] = (1ll << N); ll answer = 0; answer = cnts[1][1][1] - cnts[1][1][0] - cnts[1][0][1] - cnts[0][1][1] + cnts[1][0][0] + cnts[0][1][0] + cnts[0][0][1] - cnts[0][0][0]; cout << answer << endl; return 0; }
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//Shrey Dubey #include<iostream> #include<string> #include<algorithm> #include<map> #include<unordered_map> #include<vector> #include<set> #include<list> #include<iomanip> #include<queue> #include<stack> #include <math.h> #include<climits> #include<bitset> #include<cstring> #include<numeric> #include<array> using namespace std; typedef long long ll; typedef long double ld; #define YES cout<< YES n #define Yes cout<< Yes n #define NO cout<< NO n #define No cout<< No n #define prDouble(x) cout<<fixed<<setprecision(10)<<x //to print decimal numbers #define pb push_back #define ff first #define sec second #define umap unordered_map #define mp make_pair #define KOBE ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL) #define fo(n) for(ll i = 0; i<n; i++) #define fnd(stl, data) find(stl.begin(), stl.end(), data) #define forn(x,n) for(ll x = 0; x<n; x++) #define imax INT_MAX #define lmax LLONG_MAX #define imin INT_MIN #define lmin LLONG_MIN #define vi vector<int> #define vl vector<ll> #define vp vector<pair<ll,ll> > #define vs vector<string> #define vb vector<bool> #define pr(t) cout<<t<< n #define int long long #define ql queue<ll> #define qp queue<pair<ll,ll> > #define endl n #define nl cout<< n #define re cin >> #define pll pair<ll,ll> #define FOR(a,b) for(ll i = a; i<=b; i++) #define all(x) x.begin(),x.end() #define LG 22 // ll dx[] = {1,0,-1,0}; // ll dy[] = {0,1,0,-1}; ll mod = 1e9 + 7; ll cl(ld a){ if(a>(ll) a){ return (ll)a+1; } else{ return (ll)a; } } ll flr(ld a){ if(a < 0.0){ return (ll) a - 1; } return (ll) a; } ll gcd(ll a, ll b){ if(b == 0) return a; else return gcd(b,a%b); } //code starts here ll n,q; const ll M = 1e5+100; ll nxt[M] = {0}, a[M]; ll dp[LG][M] = {0}; vl fact[M]; void solve(){ re n; re q; fo(n) re a[i+1]; for(ll i = 2; i<M; i++){ if(!fact[i].empty()) continue; for(ll j = i; j<M; j+=i){ nxt[i] = n+1; fact[j].pb(i); } } dp[0][n+1] = n+1; for(ll i = n; i>=1; i--){ dp[0][i] = dp[0][i+1]; for(auto f: fact[a[i]]){ // if(i == 6 && f == 7) pr( here ); dp[0][i] = min(dp[0][i],nxt[f]); nxt[f] = i; } // cout<<i<< () <<dp[0][i]<< n ; } for(ll j = 1; j<20; j++){ for(ll i = 1; i<=n+1; i++){ ll k = dp[j-1][i]; dp[j][i] = dp[j-1][k]; } } while(q--){ ll l,r; re l; re r; ll ans = 0; for(ll i = 19; i>=0; i--){ if(dp[i][l] <= r){ // cout<<l<< () n ; ans += (1<<i); l = dp[i][l]; } } pr(ans+1); } } int32_t main(){ KOBE; ll t; t = 1; // re t; while(t--) solve(); } //common errors // row - n, col - m always and loop var // see the freq of numbers carefully // see if there s array overflow // use map for large inputs // always check for n = 1 condition // check loop starting and end points :( //problem ideas //check piegonhole wherever possible //there might be many instances of limited answers like 0,1,2 only // see suffix and prefix //don t be obsessed with binary search // try to find repeating pattern in matrices
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#include <bits/stdc++.h> using namespace std; signed long long p[1000005] = {0}; void sieve() { p[0] = 1; p[1] = 1; for (signed long long i = 2; i * i <= 1000000; i++) { if (p[i] == 0) { for (signed long long j = 2 * i; j <= 1000000; j = j + i) p[j] = 1; } } } int main() { signed long long n, m, wt; cin >> n >> m; sieve(); for (signed long long i = n - 1; i <= 1000000; i++) { if (p[i] == 0) { wt = i; break; } } cout << wt << << wt << endl; ; for (signed long long i = 1; i < n - 1; i++) cout << i << << i + 1 << << 1 << endl; cout << n - 1 << << n << << wt - (n - 2) << endl; signed long long cnt = n - 1; for (signed long long i = 1; i <= n; i++) { for (signed long long j = i + 2; j <= n; j++) { if (cnt == m) return 0; cout << i << << j << << wt + 5 << endl; cnt++; } } return 0; }
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module SysPLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire sdr_clk,
// interface 'outclk1'
output wire sys_clk,
// interface 'outclk2'
output wire vga_clk,
output wire pit_clk,
// interface 'locked'
output wire locked
);
wire [4:0] sub_wire0;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire5;
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign sdr_clk = sub_wire1;
assign sys_clk = sub_wire2;
assign vga_clk = sub_wire3;
assign pit_clk = sub_wire4;
assign sub_wire5 = refclk;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (locked),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "-2727",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 25000000,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 596529,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
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#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; long long power(long long a, long long b) { if (b == 0) return 1; else if (b == 1) { return a; } else if (b & 1) { return (a % mod * power((a % mod * a % mod) % mod, b / 2)) % mod; } else { return (power((a % mod * a % mod) % mod, b / 2)) % mod; } } void solve() { int n, m, a, b; cin >> n >> m; vector<int> adj[n + 1]; vector<int> deg(n + 1, 0), ans, dis(n + 1, 0), odd, even; for (long long i = 0; i < m; i++) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); deg[a]++; deg[b]++; } queue<pair<int, int> > q; vector<bool> vis(n + 1, false); q.push({1, 0}); vis[1] = 1; while (!q.empty()) { auto it = q.front(); q.pop(); dis[it.first] = it.second; for (int j : adj[it.first]) { if (!vis[j]) { vis[j] = 1; q.push({j, dis[it.first] + 1}); } } } for (int i = 1; i <= n; i++) { if (dis[i] & 1) { odd.push_back(i); } else { even.push_back(i); } } if (odd.size() > even.size()) { cout << even.size() << endl; for (int i = 0; i < even.size(); i++) { cout << even[i] << ; } cout << endl; } else { cout << odd.size() << endl; for (int i = 0; i < odd.size(); i++) { cout << odd[i] << ; } cout << endl; } } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2000010; int main() { int len, cnt; char s, d, st[maxn], word[26]; cin >> len >> cnt; cin >> st; for (int i = 0; i < 26; ++i) { word[i] = a + i; } for (int i = 1; i <= cnt; ++i) { cin >> s >> d; if (s == d) continue; for (int j = 0; j < 26; ++j) { if (word[j] == s) word[j] = d; else if (word[j] == d) word[j] = s; } } for (int i = 0; i < len; ++i) cout << word[st[i] - a ]; cout << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_MS__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ms__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_FUNCTIONAL_V
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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_rx_core #(
parameter ABUSWIDTH = 16,
parameter [1:0] ADC_ID = 0,
parameter [0:0] HEADER_ID = 0
) (
input wire ADC_ENC,
input wire [13:0] ADC_IN,
input wire ADC_SYNC,
input wire ADC_TRIGGER,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 1;
// 0 - soft reset
// 1 - start/status
//TODO:
// - external trigger /rising falling
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000; // CONF_START_WITH_SYNC = TRUE
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 0;
status_regs[6] <= 1;
status_regs[7] <= 0;
status_regs[8] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
wire START;
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_WITH_SYNC;
assign CONF_START_WITH_SYNC = status_regs[2][0];
wire CONF_EN_EX_TRIGGER;
assign CONF_EN_EX_TRIGGER = status_regs[2][1];
wire CONF_SINGLE_DATA;
assign CONF_SINGLE_DATA = status_regs[2][2];
wire [23:0] CONF_DATA_CNT;
assign CONF_DATA_CNT = {status_regs[5], status_regs[4], status_regs[3]};
wire [7:0] CONF_SAMPLE_SKIP = status_regs[6];
wire [7:0] CONF_SAMPEL_DLY = status_regs[7];
reg [7:0] CONF_ERROR_LOST;
assign LOST_ERROR = CONF_ERROR_LOST != 0;
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_ERROR_LOST;
else if(BUS_ADD < 16)
BUS_DATA_OUT <= BUS_STATUS_OUT;
end
end
wire rst_adc_sync;
cdc_reset_sync isync_rst (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(ADC_ENC), .pulse_out(rst_adc_sync));
wire start_adc_sync;
cdc_pulse_sync istart_rst (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(ADC_ENC), .pulse_out(start_adc_sync));
wire adc_sync_pulse;
pulse_gen_rising pulse_adc_sync (.clk_in(ADC_ENC), .in(ADC_SYNC), .out(adc_sync_pulse));
//long reset is needed
reg [7:0] sync_cnt;
always @(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
/*
reg [7:0] align_cnt;
always @(posedge ADC_ENC) begin
if(adc_sync_pulse)
align_cnt <= 0;
else if(align_cnt == (CONF_SAMPLE_SKIP - 1))
align_cnt <= 0;
else
align_cnt <= align_cnt + 1;
end
*/
reg adc_sync_wait;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
adc_sync_wait <= 0;
else if(start_adc_sync)
adc_sync_wait <= 1;
else if (adc_sync_pulse)
adc_sync_wait <= 0;
end
wire start_data_count;
assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
reg [23:0] rec_cnt;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
rec_cnt <= 0;
else if(start_data_count && (rec_cnt > CONF_DATA_CNT || rec_cnt == 0))
rec_cnt <= 1;
else if(rec_cnt != 24'hff_ffff && rec_cnt > 0 && CONF_DATA_CNT != 0)
rec_cnt <= rec_cnt + 1;
end
wire DONE;
assign DONE = rec_cnt > CONF_DATA_CNT;
reg cdc_fifo_write_single;
always @(*) begin
if(CONF_DATA_CNT==0 && rec_cnt>=1) //forever
cdc_fifo_write_single = 1;
else if(rec_cnt>=1 && rec_cnt <= CONF_DATA_CNT) //to CONF_DATA_CNT
cdc_fifo_write_single = 1;
else
cdc_fifo_write_single = 0;
end
reg [13:0] prev_data;
reg prev_sync;
reg prev_ready;
always @(posedge ADC_ENC) begin
if(rst_adc_sync || start_adc_sync)
prev_ready <= 0;
else
prev_ready <= !prev_ready;
end
//
reg [13:0] ADC_IN_DLY, adc_dly_mem;
reg [13:0] dly_mem [255:0];
reg [7:0] dly_addr_read, dly_addr_write;
always @(posedge ADC_ENC)
if(rst_adc_sync)
dly_addr_write <= 0;
else
dly_addr_write <= dly_addr_write + 1;
always @(posedge ADC_ENC)
dly_mem[dly_addr_write] <= ADC_IN;
always @(posedge ADC_ENC)
adc_dly_mem <= dly_mem[dly_addr_read];
always @(*) begin
dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
end
//
always @(posedge ADC_ENC) begin
prev_data <= ADC_IN_DLY;
prev_sync <= ADC_SYNC;
end
wire fifo_full, cdc_fifo_empty, cdc_fifo_write_double;
assign cdc_fifo_write_double = cdc_fifo_write_single && prev_ready; //write every second
wire wfull;
reg cdc_fifo_write;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
CONF_ERROR_LOST <= 0;
else if (CONF_ERROR_LOST!=8'hff && wfull && cdc_fifo_write)
CONF_ERROR_LOST <= CONF_ERROR_LOST +1;
end
reg [31:0] data_to_fifo;
always @(*) begin
if(CONF_SINGLE_DATA)
data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
else
data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
if(CONF_SINGLE_DATA)
cdc_fifo_write = cdc_fifo_write_single;
else
cdc_fifo_write = cdc_fifo_write_double;
end
wire [31:0] cdc_data_out;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(3)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_fifo), //.wdata({ADC_SYNC,2'd0,ADC_SYNC,14'd0,adc_des}),
.winc(cdc_fifo_write),
.wclk(ADC_ENC),
.wrst(RST_LONG),
.rinc(!fifo_full),
.rclk(BUS_CLK),
.rrst(RST_LONG)
);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(1024)
) fifo_i (
.clk(BUS_CLK),
.reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]),
.size()
);
//assign FIFO_DATA[31:30] = 0;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(ADC_ENC), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
/**
* bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc.v
*
* bsg_mem_1rw_sync_mask_write_byte implementation using associative array.
*
* This is for simulating arbitrarily large memories.
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter write_mask_width_lp=(data_width_p>>3)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_p-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output [data_width_p-1:0] data_o
);
for (genvar i = 0; i < write_mask_width_lp; i++) begin: bk
bsg_nonsynth_mem_1rw_sync_assoc #(
.addr_width_p(addr_width_p)
,.width_p(8)
) mem_1rw_sync (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(data_i[(i*8)+:8])
,.addr_i(addr_i)
,.v_i(v_i)
,.w_i(w_i & write_mask_i[i])
,.data_o(data_o[(i*8)+:8])
);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc)
|
/*--------------------------------------------------------------- γγγγγγγγγγγ β§οΌΏβ§ γγγγγ β§οΌΏβ§ γοΌΒ΄<_ο½ οΌγ γγγγ οΌ Β΄_γ`οΌγ/γ βi γγγγοΌγγγοΌΌγ γ |γ| γγγ /γγ /οΏ£οΏ£οΏ£οΏ£/γγ| γ οΌΏ_(__οΎγ€/γ οΌΏ/ .| .|οΌΏοΌΏοΌΏοΌΏ γ γγγοΌΌ/οΌΏοΌΏοΌΏοΌΏ/γοΌuγβ --------------------------------------------------------------*/ #include<bits/stdc++.h> #define IO ios::sync_with_stdio(false);cin.tie(0) #define rep(i,a,b) for(int i=a;i<=b;i++) #define req(i,a,b) for(int i=a;i>=b;i--) #define pb push_back #define fi first #define se second #define PI pair<int,int> #define PII pair<ll,PI> using namespace std; typedef long long ll; const int N=1e5+7; const ll mod=1e9+7; int a[107],b[107],x[107]; PI p[107]; int main() { IO; int t; cin>>t; while(t--){ int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 1; i <= n; ++i) { cin >> b[i]; } int ans = 0; for (int i = 1; i <= n; ++i) { ans += a[i]-b[i]; } if (ans != 0) { cout << -1 << endl; continue; } int sum1 = 0, sum2 =0; for (int i = 1; i <= n; ++i) { x[i] = a[i] - b[i]; if (x[i] > 0) { sum1 += x[i]; } else if(x[i] < 0) { sum2 += x[i]; } } cout << sum1 << endl; while(sum1){ for(int i = 1; i <= n; i++){ if(x[i] < 0){ for(int j = 1; j <= n; j++){ if(x[j] > 0){ cout << j << << i << endl; x[i]++; x[j]--; sum1--; break; } } } } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_PP_BLACKBOX_V
|
// tb200.v - A WCI::OCP test bench with BFM, DUT, and Monitor/Observer
// Copyright (c) 2010 Atomic Rules LLC - ALL RIGHTS RESERVED
//
// This testbench instances three components, and provides them with a common clock and reset
// These three components are connected together with the WCI0_ signal group
// 1. A BFM "Initiator" which initiates WCI cycles
// 2. A DUT "Taget" which completes WCI cycles
// 3. A Monitor/Observer which watches ober the WCI cycles
`timescale 1ns/1ps
module tb200 ();
reg CLK; // System Clock
reg RST_N; // System Reset (active-low)
always begin // Clock generation...
#5; CLK = 1'b0;
#5; CLK = 1'b1;
end
initial begin: initblock
integer i;
localparam resetCycles = 16;
#0 RST_N = 1'b0; $display("[%0d] %m: System Reset Asserted, RST_N=0", $time);
for (i=0;i<resetCycles;i=i+1) @(posedge CLK);
#0 RST_N = 1'b1; $display("[%0d] %m: System Reset Released, RST_N=1", $time);
end
// WCI0_ WCI::OCP Wires to interconnect the BFM, DUT and Monitor...
wire WCI0_Clk = CLK; // Connect system clock to be the clock of the WCI0 M/S/O link
wire WCI0_MReset_n;
wire [2:0] WCI0_MCmd;
wire WCI0_MAddrSpace;
wire [3:0] WCI0_MByteEn;
wire [19:0] WCI0_MAddr;
wire [31:0] WCI0_MData;
wire [1:0] WCI0_SResp;
wire [31:0] WCI0_SData;
wire WCI0_SThreadBusy;
wire [1:0] WCI0_SFlag;
wire [1:0] WCI0_MFlag;
mkWciOcpInitiator bfm ( // Instance the BFM Initiator...
.CLK (CLK),
.RST_N (RST_N),
// .wciM0_Clk (WCI0_Clk),
.RST_N_wciM0 (WCI0_MReset_n), // WCI0_MReset_n is the reset source for this WCI0 link
.wciM0_MCmd (WCI0_MCmd),
.wciM0_MAddrSpace (WCI0_MAddrSpace),
.wciM0_MByteEn (WCI0_MByteEn),
.wciM0_MAddr (WCI0_MAddr),
.wciM0_MData (WCI0_MData),
.wciM0_SResp (WCI0_SResp),
.wciM0_SData (WCI0_SData),
.wciM0_SThreadBusy (WCI0_SThreadBusy),
.wciM0_SFlag (WCI0_SFlag),
.wciM0_MFlag (WCI0_MFlag)
);
mkWciOcpTarget wut ( // Instance the "Worker Under Test" (WUT) target
.wciS0_Clk (WCI0_Clk),
.wciS0_MReset_n (WCI0_MReset_n),
.wciS0_MCmd (WCI0_MCmd),
.wciS0_MAddrSpace (WCI0_MAddrSpace),
.wciS0_MByteEn (WCI0_MByteEn),
.wciS0_MAddr (WCI0_MAddr),
.wciS0_MData (WCI0_MData),
.wciS0_SResp (WCI0_SResp),
.wciS0_SData (WCI0_SData),
.wciS0_SThreadBusy (WCI0_SThreadBusy),
.wciS0_SFlag (WCI0_SFlag),
.wciS0_MFlag (WCI0_MFlag)
);
mkWciOcpMonitor mon ( // Instance the Monitor/Observer...
.CLK (CLK),
.RST_N (RST_N),
.CLK_wci_clk (WCI0_Clk),
.RST_N_wci_rstn (WCI0_MReset_n),
.wciO0_MCmd (WCI0_MCmd),
.wciO0_MAddrSpace (WCI0_MAddrSpace),
.wciO0_MByteEn (WCI0_MByteEn),
.wciO0_MAddr (WCI0_MAddr),
.wciO0_MData (WCI0_MData),
.wciO0_SResp (WCI0_SResp),
.wciO0_SData (WCI0_SData),
.wciO0_SThreadBusy (WCI0_SThreadBusy),
.wciO0_SFlag (WCI0_SFlag),
.wciO0_MFlag (WCI0_MFlag)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 305; const int inf = 0x3f3f3f3f; const double eps = 1e-5; int n, c; int dp[605][N][N], a[N][N]; int max(int a, int b, int c, int d) { return max(max(a, b), max(c, d)); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &a[i][j]); memset(dp, -inf, sizeof(dp)); dp[0][1][1] = a[1][1]; int l = (n - 1) * 2; for (int i = 1; i <= l; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= n; k++) { if (k == j) c = a[j][i + 2 - j]; else c = a[j][i + 2 - j] + a[k][i + 2 - k]; dp[i][j][k] = max(dp[i - 1][j - 1][k - 1], dp[i - 1][j][k - 1], dp[i - 1][j - 1][k], dp[i - 1][j][k]) + c; } } } printf( %d n , dp[l][n][n]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; void file() { freopen( alost.in , r , stdin); freopen( output.txt , w , stdout); } bool ar[10000005]; void sieve() { ar[0] = ar[1] = 1; for (long long i = 2; i * i <= (int)1e7; i++) if (!ar[i]) for (long long j = i * i; j <= (int)1e7; j += i) ar[j] = 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL), cout.tie(NULL); ; sieve(); int n; cin >> n; for (int i = 2; i <= (int)1e7 && n; i++) if (!ar[i]) cout << i << , n--; cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool prime[1500000 + 10]; bool a[1500000 + 10]; int func(int N, int x) { int i, ans = 0; if (x == 2) return 0; if (a[1]) return 1; if (x >= 1500000) return -1; for (i = 2; i <= x - 1; i++) if (prime[i]) if (a[i]) ans++; else return -1; return ans; } int main(void) { int i, j, N, x, tmp; for (i = 2; i < 1500000; i++) prime[i] = true; for (i = 2; i * i < 1500000; i++) if (prime[i]) for (j = i * i; j < 1500000; j += i) prime[j] = false; scanf( %d%d , &N, &x); for ((i) = 0; (i) < (int)(N); (i)++) { scanf( %d , &tmp); if (tmp < 1500000) a[tmp] = true; } int ans = func(N, x); cout << ans << endl; return 0; }
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
phy_ddio_oct_ena,
afi_dqs_en,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
assign phy_ddio_dq_pre_shift = afi_wdata;
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en;
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid;
assign phy_ddio_wrdata_mask_pre_shift = afi_dm;
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
always @(posedge pll_afi_clk)
begin
afi_wdata_r[0] <= afi_wdata;
afi_dqs_en_r[0] <= afi_dqs_en;
afi_wdata_valid_r[0] <= afi_wdata_valid;
afi_dm_r[0] <= afi_dm;
end
for (stage = 1; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
afi_wdata_r[stage] <= afi_wdata_r[stage-1];
afi_dqs_en_r[stage] <= afi_dqs_en_r[stage-1];
afi_wdata_valid_r[stage] <= afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= afi_dm_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
end
endgenerate
wire [AFI_DQS_WIDTH-1:0] oct_ena;
reg [MEM_WRITE_DQS_WIDTH-1:0] dqs_en_reg;
always @(posedge pll_afi_clk)
dqs_en_reg <= phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] = ~phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH];
assign oct_ena[MEM_WRITE_DQS_WIDTH-1:0] = ~(phy_ddio_dqs_en[AFI_DQS_WIDTH-1:MEM_WRITE_DQS_WIDTH] | dqs_en_reg);
assign phy_ddio_oct_ena_pre_shift = oct_ena & ~force_oct_off;
assign phy_ddio_dq = phy_ddio_dq_pre_shift;
assign phy_ddio_wrdata_mask = phy_ddio_wrdata_mask_pre_shift;
assign phy_ddio_wrdata_en = phy_ddio_wrdata_en_pre_shift;
assign phy_ddio_dqs_en = phy_ddio_dqs_en_pre_shift;
assign phy_ddio_oct_ena = phy_ddio_oct_ena_pre_shift;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; long long a[N], b[N]; void add(int l, int r, int val) { if (l > r) return; b[l] += val; b[r + 1] -= val; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) cin >> a[i]; for (int i = 1; i < m; i++) if (a[i - 1] != a[i]) { int x1 = min(a[i - 1], a[i]); int x2 = max(a[i - 1], a[i]); add(1, x1 - 1, x2 - x1); add(x1, x1, x2 - 1); add(x1 + 1, x2 - 1, x2 - x1 - 1); add(x2, x2, x1); add(x2 + 1, n, x2 - x1); } for (int i = 1; i <= n; i++) b[i] += b[i - 1]; for (int i = 1; i <= n; i++) { if (i > 1) cout << ; cout << b[i]; } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_1_V
`define SKY130_FD_SC_LS__DLRBN_1_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbn_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrbn base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
hdmi_iic_rstn,
hdmi_iic_scl,
hdmi_iic_sda,
hdmi_rx_clk,
hdmi_tx_clk,
hdmi_rx_data,
hdmi_tx_data,
hdmiio_int,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
inout hdmi_iic_rstn;
inout hdmi_iic_scl;
inout hdmi_iic_sda;
inout hdmiio_int;
input otg_vbusoc;
// imageon ports
input hdmi_rx_clk;
output hdmi_tx_clk;
input [15:0] hdmi_rx_data;
output [15:0] hdmi_tx_data;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire hdmi_rx_clk;
wire hdmi_tx_clk;
wire hdmi_rx_clk_bufio;
wire [15:0] hdmi_rx_data;
reg [15:0] hdmi_rx_data_in;
reg [15:0] hdmi_tx_data;
always @(posedge hdmi_rx_clk_bufio) begin
hdmi_rx_data_in <= hdmi_rx_data;
hdmi_tx_data <= hdmi_rx_data_in;
end
// instantiations
BUFIO (
.I (hdmi_rx_clk),
.O (hdmi_rx_clk_bufio));
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.C (hdmi_rx_clk_bufio),
.Q (hdmi_tx_clk));
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi (
.dio_t (gpio_t[32]),
.dio_i (gpio_o[32]),
.dio_o (gpio_i[32]),
.dio_p (hdmiio_int));
ad_iobuf #(.DATA_WIDTH(1)) i_gpio_hdmi_iic_rstn (
.dio_t (gpio_t[33]),
.dio_i (gpio_o[33]),
.dio_o (gpio_i[33]),
.dio_p (hdmi_iic_rstn));
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.iic_imageon_scl_io (hdmi_iic_scl),
.iic_imageon_sda_io (hdmi_iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//UART FIFO
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1ns/1ps
/*
A custom FIFO that can take multiple bytes in at a time
*/
module uart_fifo (
clk,
rst,
size,
write_strobe,
write_available,
write_data,
read_strobe,
read_count,
read_data,
overflow,
underflow,
full,
empty
);
//parameters
parameter FIFO_SIZE = 10;
input clk;
input rst;
output wire [31:0] size;
input write_strobe;
output wire [31:0] write_available;
input [7:0] write_data;
input read_strobe;
output reg [31:0] read_count;
output wire [7:0] read_data;
output reg overflow;
output reg underflow;
output full;
output empty;
//Wires, Registers
reg [FIFO_SIZE - 1: 0] in_pointer;
reg [FIFO_SIZE - 1: 0] out_pointer;
dual_port_bram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(FIFO_SIZE),
//`ifdef SIMULATION
// .MEM_FILE("mem_file.txt"),
// .MEM_FILE_LENGTH(8)
//`else
.MEM_FILE("NOTHING"),
.MEM_FILE_LENGTH(0)
//`endif
) mem (
.a_clk(clk),
.a_wr(write_strobe),
.a_addr(in_pointer),
.a_din(write_data),
//.a_dout(),
.b_clk(clk),
.b_wr(1'b0),
.b_addr(out_pointer),
.b_din(8'h0),
.b_dout(read_data)
);
//synthesis attribute ram_style of mem is block
wire [FIFO_SIZE - 1: 0] last;
//Asynchronous Logic
assign size = 1 << FIFO_SIZE;
assign last = (out_pointer - 1);
assign full = (in_pointer == last);
assign empty = (read_count == 0);
assign write_available = size - read_count;
integer i;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
read_count <= 0;
in_pointer <= 0;
out_pointer <= 0;
//`ifdef SIMULATION
// read_count <= 8;
// in_pointer <= 8;
//`endif
overflow <= 0;
underflow <= 0;
end
else begin
overflow <= 0;
underflow <= 0;
if (write_strobe) begin
if (full && !read_strobe) begin
//overflow
$display ("UART CONTROLLER: Overflow condition");
out_pointer <= out_pointer + 1;
overflow <= 1;
end
else begin
//not overflow
if (!read_strobe) begin
read_count <= read_count + 1;
end
end
in_pointer <= in_pointer + 1;
end
if (read_strobe) begin
if (empty) begin
//empty
underflow <= 1;
end
else begin
if (full && write_strobe) begin
//check for that very rare condition where the write strobe and the read strobe is begin used at the same time
//and the FIFO is full
overflow <= 0;
end
else begin
if (!write_strobe) begin
read_count <= read_count - 1;
end
out_pointer <= out_pointer + 1;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y; }; vector<node> answer; int dis[1000005], a[1000005], pre[1000005]; bool prime[1000005]; void getprime() { for (int i = 2; i < 1000005 - 5; i++) { if (!prime[i]) { for (int j = i * 2; j < 1000005 - 5; j += i) { prime[j] = true; } } } int maxx = 2; for (int i = 2; i < 1000005 - 5; i++) { if (prime[i] == false) maxx = i; pre[i] = maxx; } } int main() { getprime(); int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); dis[a[i]] = i; } int t = 0; for (int i = 1; i <= n; i++) { if (a[i] == i) continue; int j = dis[i]; while (j != i) { int k = pre[j - i + 1]; k = j - k + 1; node q; q.x = k, q.y = j; answer.push_back(q); swap(dis[a[j]], dis[a[k]]); swap(a[j], a[k]); j = k; } } printf( %d n , answer.size()); for (int i = 0; i < answer.size(); i++) { printf( %d %d n , answer[i].x, answer[i].y); } }
|
/**
\file "interleave-c.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
Added inverters in prsim to check for proper event interleaving.
$Id: interleave-c.v,v 1.3 2010/04/06 00:08:33 fang Exp $
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ interleave-c.haco-c
$prsim("interleave-c.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$prsim_cmd("timing after");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #6 $finish;
initial
$monitor("@%6.3f: out=%d,%d,%d,%d,%d", $realtime,
out0, out1, out2, out3, out);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:52 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xlconcat_0_0_stub.v
// Design : zqynq_lab_1_design_xlconcat_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(In0, In1, dout)
/* synthesis syn_black_box black_box_pad_pin="In0[0:0],In1[0:0],dout[1:0]" */;
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { scanf( %d%d , &n, &m); while (n--) { int a, b, t, ans; scanf( %d%d%d , &a, &b, &t); if (a == b) { printf( %d n , t); continue; } int d = t / (m - 1); ans = d * (m - 1); if (d % 2 == 0) { if (ans + a - 1 < t) { ans = ans + m - 1 + m - a; if (b < a) ans += a - b; else ans += a - 1 + b - 1; } else { ans += a - 1; if (b > a) ans += b - a; else ans += m - a + m - b; } } else { if (ans + m - a < t) { ans += m - 1 + a - 1; if (b > a) ans += b - a; else ans += m - a + m - b; } else { ans += m - a; if (b < a) ans += a - b; else ans += a - 1 + b - 1; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 5010; const int mod = 1e9 + 7; const long long INF = 1e15; int nex[N]; long long x[N], a[N], b[N], c[N], d[N]; int main() { int n, s, e; while (~scanf( %d%d%d , &n, &s, &e)) { nex[s] = e; for (int i = 1; i <= n; i++) scanf( %I64d , &x[i]); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (int i = 1; i <= n; i++) scanf( %I64d , &b[i]); for (int i = 1l; i <= n; i++) scanf( %I64d , &c[i]); for (int i = 1; i <= n; i++) scanf( %I64d , &d[i]); for (int i = 1; i <= n; i++) { if (i == s || i == e) continue; long long mi = INF, id; for (int j = s; j != e; j = nex[j]) { long long tmpans = 0; int from = j, to = i; if (to < from) tmpans += abs(x[from] - x[to]) + c[from] + b[to]; else tmpans += abs(x[from] - x[to]) + d[from] + a[to]; from = i, to = nex[j]; if (to < from) tmpans += abs(x[from] - x[to]) + c[from] + b[to]; else tmpans += abs(x[from] - x[to]) + d[from] + a[to]; from = j, to = nex[j]; if (to < from) tmpans -= abs(x[from] - x[to]) + c[from] + b[to]; else tmpans -= abs(x[from] - x[to]) + d[from] + a[to]; if (mi > tmpans) { mi = tmpans; id = j; } } int tmpnex = nex[id]; nex[id] = i; nex[i] = tmpnex; } long long ans = 0; for (int i = s; i != e; i = nex[i]) { long long tmpans = 0; int from = i, to = nex[i]; if (to < from) tmpans += abs(x[from] - x[to]) + c[from] + b[to]; else tmpans += abs(x[from] - x[to]) + d[from] + a[to]; ans += tmpans; } printf( %I64d n , ans); } return 0; }
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:45 EST 2016
//
// Method conflict info:
// Method: select
// Conflict-free: select
// Sequenced before: next
//
// Method: next
// Sequenced after: select
// Conflicts: next
//
//
// Ports:
// Name I/O size props
// select O 5
// CLK I 1 clock
// RST_N I 1 reset
// select_requests I 5
// EN_next I 1
//
// Combinational paths from inputs to outputs:
// select_requests -> select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkInputArbiter(CLK,
RST_N,
select_requests,
select,
EN_next);
input CLK;
input RST_N;
// value method select
input [4 : 0] select_requests;
output [4 : 0] select;
// action method next
input EN_next;
// signals for module outputs
wire [4 : 0] select;
// register arb_token
reg [4 : 0] arb_token;
wire [4 : 0] arb_token$D_IN;
wire arb_token$EN;
// remaining internal signals
wire [1 : 0] ab__h1657,
ab__h1672,
ab__h1687,
ab__h1702,
ab__h1717,
ab__h3098,
ab__h3545,
ab__h3938,
ab__h4282,
ab__h4577;
wire NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
ab_BIT_0___h2269,
ab_BIT_0___h2376,
ab_BIT_0___h2483,
ab_BIT_0___h2590,
ab_BIT_0___h3169,
ab_BIT_0___h3305,
ab_BIT_0___h3698,
ab_BIT_0___h4042,
ab_BIT_0___h4337,
arb_token_BIT_0___h2267,
arb_token_BIT_1___h2374,
arb_token_BIT_2___h2481,
arb_token_BIT_3___h2588,
arb_token_BIT_4___h2695;
// value method select
assign select =
{ ab__h1657[1] || ab__h3098[1],
!ab__h1657[1] && !ab__h3098[1] &&
(ab__h1672[1] || ab__h3545[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h1657[1] && !ab__h3098[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// register arb_token
assign arb_token$D_IN = { arb_token[0], arb_token[4:1] } ;
assign arb_token$EN = EN_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h1717));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h2269),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h1702));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h2376),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h1687));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h2483),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h1672));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h2590),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h1657));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h3169),
.gen_grant_carry_r(select_requests[0]),
.gen_grant_carry_p(arb_token_BIT_0___h2267),
.gen_grant_carry(ab__h4577));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h4337),
.gen_grant_carry_r(select_requests[1]),
.gen_grant_carry_p(arb_token_BIT_1___h2374),
.gen_grant_carry(ab__h4282));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h4042),
.gen_grant_carry_r(select_requests[2]),
.gen_grant_carry_p(arb_token_BIT_2___h2481),
.gen_grant_carry(ab__h3938));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h3698),
.gen_grant_carry_r(select_requests[3]),
.gen_grant_carry_p(arb_token_BIT_3___h2588),
.gen_grant_carry(ab__h3545));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h3305),
.gen_grant_carry_r(select_requests[4]),
.gen_grant_carry_p(arb_token_BIT_4___h2695),
.gen_grant_carry(ab__h3098));
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
(ab__h1687[1] || ab__h3938[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h1657[1] && !ab__h3098[1] && !ab__h1672[1] &&
!ab__h3545[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h1687[1] && !ab__h3938[1] && !ab__h1702[1] &&
!ab__h4282[1] &&
(ab__h1717[1] || ab__h4577[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h1672[1] && !ab__h3545[1] && !ab__h1687[1] &&
!ab__h3938[1] &&
(ab__h1702[1] || ab__h4282[1]) ;
assign ab_BIT_0___h2269 = ab__h1717[0] ;
assign ab_BIT_0___h2376 = ab__h1702[0] ;
assign ab_BIT_0___h2483 = ab__h1687[0] ;
assign ab_BIT_0___h2590 = ab__h1672[0] ;
assign ab_BIT_0___h3169 = ab__h1657[0] ;
assign ab_BIT_0___h3305 = ab__h3545[0] ;
assign ab_BIT_0___h3698 = ab__h3938[0] ;
assign ab_BIT_0___h4042 = ab__h4282[0] ;
assign ab_BIT_0___h4337 = ab__h4577[0] ;
assign arb_token_BIT_0___h2267 = arb_token[0] ;
assign arb_token_BIT_1___h2374 = arb_token[1] ;
assign arb_token_BIT_2___h2481 = arb_token[2] ;
assign arb_token_BIT_3___h2588 = arb_token[3] ;
assign arb_token_BIT_4___h2695 = arb_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
arb_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
end
else
begin
if (arb_token$EN) arb_token <= `BSV_ASSIGNMENT_DELAY arb_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
arb_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkInputArbiter
|
#include <bits/stdc++.h> using namespace std; static inline void canhazfast() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } template <typename T> T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <typename T> T extgcd(T a, T b, T &x, T &y) { T x0 = 1, y0 = 0, x1 = 0, y1 = 1; while (b) { T q = a / b; a %= b; swap(a, b); x0 -= q * x1; swap(x0, x1); y0 -= q * y1; swap(y0, y1); } x = x0; y = y0; return a; } static inline int ctz(unsigned x) { return __builtin_ctz(x); } static inline int ctzll(unsigned long long x) { return __builtin_ctzll(x); } static inline int clz(unsigned x) { return __builtin_clz(x); } static inline int clzll(unsigned long long x) { return __builtin_clzll(x); } static inline int popcnt(unsigned x) { return __builtin_popcount(x); } static inline int popcntll(unsigned long long x) { return __builtin_popcountll(x); } static inline int bsr(unsigned x) { return 31 ^ clz(x); } static inline int bsrll(unsigned long long x) { return 63 ^ clzll(x); } struct Node { long long mx, lz; }; Node t[1 << 19]; int a[1 << 18]; long long build(int u, int b, int e, long long s = 0) { if (b + 1 == e) { t[u].mx = a[b] - s; return s + a[b]; } int m = (b + e) / 2, lc = 2 * u, rc = 2 * u + 1; s = build(lc, b, m, s); s = build(rc, m, e, s); t[u].mx = max(t[lc].mx, t[rc].mx); return s; } void push(int u, int sz) { if (!t[u].lz) return; t[u].mx += t[u].lz; if (sz > 1) { t[2 * u].lz += t[u].lz; t[2 * u + 1].lz += t[u].lz; } t[u].lz = 0; } void upd(int u, int b, int e, int pos, int d) { int sz = e - b; if (pos >= e) return push(u, e - b); if (pos < b) return t[u].lz -= d, push(u, sz); if (sz == 1) return t[u].lz += d, push(u, sz); push(u, sz); int m = (b + e) / 2, lc = 2 * u, rc = 2 * u + 1; upd(lc, b, m, pos, d); upd(rc, m, e, pos, d); t[u].mx = max(t[lc].mx, t[rc].mx); } int get(int u, int b, int e) { push(u, e - b); if (t[u].mx < 0) return -2; if (b + 1 == e) return t[u].mx == 0 ? b : -2; int m = (b + e) / 2, lc = 2 * u, rc = 2 * u + 1; int res = get(lc, b, m); if (res < 0) res = get(rc, m, e); return res; } int main() { canhazfast(); int n, q; cin >> n >> q; for (int i = 0; i < n; ++i) cin >> a[i]; build(1, 0, n); for (; q; --q) { int p, x; cin >> p >> x; --p; upd(1, 0, n, p, x - a[p]); a[p] = x; cout << get(1, 0, n) + 1 << n ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/15 23:06:33
// Design Name:
// Module Name: Chip_Decoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Chip_Decoder(
input A9,A8,F,A3,A2,AEN,IORbar,IOWbar,
output reg [3:0] CSbar,
output reg Ebar,DIR
);
reg [1:0] A;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3;
always @(A9 or A8 or AEN or F or IORbar or IOWbar)
begin
if((A9 == 1) & (A8 == 1) & (AEN == 0) & F & (IORbar != IOWbar))
Ebar = 0;
else
Ebar = 1;
if((IORbar == 0) & (IOWbar ==1))
DIR = 0;
else
DIR = 1;
end
always @(A3 or A2)
begin
A = {A3,A2};
case(A)
S0 : CSbar = 4'b1110;
S1 : CSbar = 4'b1101;
S2 : CSbar = 4'b1011;
S3 : CSbar = 4'b0111;
endcase
end
endmodule
|
`timescale 1ns / 1ps
/**
Pipelined CPU
*/
module pipeline ( input wire clk,
input wire rst,
output i_read_en,
output [31:0] i_addr,
input [31:0] i_instr_in,
input wb_done_i,
output wire d_read_en,
output wire d_write_en,
output wire [31:0] d_addr,
output wire [31:0] d_write_data,
input wire [31:0] d_data_in );
/* Interconnect wires*/
wire [1:0] pc_source;
wire pc_write;
wire [31:0] jump_addr;
wire [31:0] branch_addr;
wire [31:0] next_i_addr;
wire [31:0] i_fetched; // fetched instrcution from if
wire if_id_write_en; // write enable for IF/ID pipe reg
wire [31:0] wreg_data; // data to write into regfile
wire [4:0] ex_dst_reg;
wire [5:0] ex_opcode;
wire [4:0] id_rs;
wire [4:0] id_rt;
wire [5:0] id_opcode;
wire ID_EX_wb_reg_write;
wire ID_EX_wb_mem_to_reg;
wire ID_EX_mem_read;
wire ID_EX_mem_write;
wire ID_EX_ex_imm_command;
wire ID_EX_ex_alu_src_b;
wire ID_EX_ex_dst_reg_sel;
wire [1:0] ID_EX_ex_alu_op;
wire [31:0] ID_EX_A;
wire [31:0] ID_EX_B;
wire [31:0] ID_EX_sign_extend_offset;
wire [4:0] ID_EX_rt; // target register
wire [4:0] ID_EX_rd; // destination register
wire [4:0] ID_EX_rs; // source register
wire [5:0] ID_EX_opcode;
wire [31:0] EX_MEM_alu_result;
wire [31:0] EX_MEM_B_value;
wire [4:0] EX_MEM_dst_reg;
wire [5:0] EX_MEM_opcode;
wire EX_MEM_mem_read;
wire EX_MEM_mem_write;
wire EX_MEM_wb_reg_write;
wire EX_MEM_wb_mem_to_reg;
wire [4:0] MEM_WB_dst_reg;
wire MEM_WB_reg_write;
wire MEM_WB_mem_to_reg;
wire [31:0] MEM_WB_mem_out;
wire [31:0] MEM_WB_alu_out;
wire id_rt_is_source;
wire hazard_detected;
// forwarding control signals for muxes
wire [1:0] if_rs_forward_control;
wire [1:0] id_rt_forward_control;
wire [1:0] ex_rs_forward_control;
wire [1:0] ex_rt_forward_control;
if_stage ifetch_inst(
.clk ( clk ),
.rst ( rst ),
.pstop_i(pstop),
.if_id_write_en ( if_id_write_en ),
.pc_write ( pc_write ),
.pc_source ( pc_source ),
.i_read_en ( i_read_en ),
.i_addr ( i_addr ),
.i_instr_in ( i_instr_in),
.jump_addr ( jump_addr ),
.branch_addr ( branch_addr ),
.IF_ID_instruction ( i_fetched ),
.IF_ID_next_i_addr ( next_i_addr ));
hazard_unit hazard_inst(
.clk ( clk ), // isn't needed for now
.rst ( rst ), // isn't needed for now
.ex_dst_reg ( ex_dst_reg ),
.pstop_o(pstop),
.mem_dst_reg ( EX_MEM_dst_reg ),
.id_rs ( id_rs ),
.id_rt ( id_rt ),
.mem_opcode ( EX_MEM_opcode ),
.ex_opcode ( ex_opcode ),
.id_opcode ( id_opcode ),
.id_rt_is_source ( id_rt_is_source ),
.ex_reg_write ( ID_EX_wb_reg_write ),
.mem_reg_write ( EX_MEM_wb_reg_write ),
.pc_write ( pc_write ),
.if_id_write_en ( if_id_write_en ),
.wb_done_i(wb_done_i),
.hazard_detected_o ( hazard_detected ));
forwarding_unit forwarding_inst(
.ex_mem_reg_write (EX_MEM_wb_reg_write),
.mem_wb_reg_write (MEM_WB_reg_write),
.ex_mem_dst_reg (EX_MEM_dst_reg),
.mem_wb_dst_reg (MEM_WB_dst_reg),
.id_ex_rs (ID_EX_rs),
.id_ex_rt (ID_EX_rt),
.if_id_rs (id_rs),
.if_id_rt (id_rt),
.if_rs_forward_control ( if_rs_forward_control ),
.id_rt_forward_control ( id_rt_forward_control ),
.ex_rs_forward_control ( ex_rs_forward_control ),
.ex_rt_forward_control ( ex_rt_forward_control ));
id_stage idecode_inst(
.clk ( clk ),
.rst ( rst ),
.reg_write ( MEM_WB_reg_write ),
.wreg_addr ( MEM_WB_dst_reg ), // write register number
.wreg_data ( wreg_data ), // data to write into regfile
.instruction ( i_fetched ),
.next_i_addr ( next_i_addr ), // instruction fetched, next instruction address
.pstop_i(pstop),
.rs_fwd_sel ( if_rs_forward_control ), // forwarding control signals
.rt_fwd_sel ( id_rt_forward_control ), // forwarding control signals
.mem_fwd_val ( EX_MEM_alu_result ), // forwarded data values from MEM
.wb_fwd_val ( wreg_data ), // forwarded data values from WB
.hazard ( hazard_detected ),
.id_rs( id_rs ),
.id_rt( id_rt ),
.id_opcode( id_opcode ),
.ID_EX_A ( ID_EX_A ),
.ID_EX_B ( ID_EX_B ),
.ID_EX_rt ( ID_EX_rt ),
.ID_EX_rs ( ID_EX_rs ),
.ID_EX_rd ( ID_EX_rd ),
.ID_EX_opcode ( ID_EX_opcode ),
.ID_EX_sign_extend_offset ( ID_EX_sign_extend_offset ),
.ID_EX_wb_reg_write ( ID_EX_wb_reg_write ),
.ID_EX_wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.ID_EX_mem_read ( ID_EX_mem_read ),
.ID_EX_mem_write ( ID_EX_mem_write ),
.ID_EX_ex_imm_command ( ID_EX_ex_imm_command ),
.ID_EX_ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ID_EX_ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ID_EX_ex_alu_op ( ID_EX_ex_alu_op ),
.branch_addr ( branch_addr ),
.jump_addr ( jump_addr ),
.id_rt_is_source ( id_rt_is_source ),
.if_pc_source ( pc_source ));
ex_stage execute_inst(
.clk ( clk ),
.rst ( rst ),
.wb_reg_write ( ID_EX_wb_reg_write ),
.wb_mem_to_reg ( ID_EX_wb_mem_to_reg ),
.mem_read ( ID_EX_mem_read ),
.pstop_i(pstop),
.mem_write ( ID_EX_mem_write ),
.ex_imm_command ( ID_EX_ex_imm_command ),
.ex_alu_src_b ( ID_EX_ex_alu_src_b ),
.ex_dst_reg_sel ( ID_EX_ex_dst_reg_sel ),
.ex_alu_op ( ID_EX_ex_alu_op ),
.A ( ID_EX_A ),
.B ( ID_EX_B ),
.sign_extend_offset ( ID_EX_sign_extend_offset ),
.rt ( ID_EX_rt ), // target register
.rd ( ID_EX_rd ), // destination register
.opcode ( ID_EX_opcode ),
.rs_fwd_sel ( ex_rs_forward_control ), // forwarding muxes control
.rt_fwd_sel ( ex_rt_forward_control ), // forwarding muxes control
.mem_fwd_val ( EX_MEM_alu_result ), // forwarding from MEM
.wb_fwd_val ( wreg_data ), // forwarding from WB
.ex_dst_reg ( ex_dst_reg ),
.ex_opcode ( ex_opcode ),
.EX_MEM_alu_result ( EX_MEM_alu_result ),
.EX_MEM_B_value ( EX_MEM_B_value ),
.EX_MEM_dst_reg ( EX_MEM_dst_reg ),
.EX_MEM_opcode ( EX_MEM_opcode ),
.EX_MEM_mem_read ( EX_MEM_mem_read ),
.EX_MEM_mem_write ( EX_MEM_mem_write ),
.EX_MEM_wb_reg_write ( EX_MEM_wb_reg_write ),
.EX_MEM_wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ));
mem_stage memstage_inst(
.clk ( clk ),
.rst ( rst ),
.mem_read ( EX_MEM_mem_read ),
.mem_write ( EX_MEM_mem_write ),
.alu_result ( EX_MEM_alu_result ),
.B ( EX_MEM_B_value ),
.pstop_i(pstop),
.dst_reg ( EX_MEM_dst_reg ),
.wb_reg_write ( EX_MEM_wb_reg_write ),
.wb_mem_to_reg ( EX_MEM_wb_mem_to_reg ),
.MEM_WB_dst_reg ( MEM_WB_dst_reg ),
.MEM_WB_reg_write ( MEM_WB_reg_write ),
.MEM_WB_mem_to_reg ( MEM_WB_mem_to_reg ),
.MEM_WB_mem_out ( MEM_WB_mem_out ),
.MEM_WB_alu_out ( MEM_WB_alu_out ),
.d_read_en ( d_read_en ),
.d_write_en ( d_write_en ),
.d_addr ( d_addr ),
.d_write_data ( d_write_data ),
.d_data_in ( d_data_in ));
wb_stage wb_inst(
.mem_to_reg ( MEM_WB_mem_to_reg ),
.mem_out ( MEM_WB_mem_out ),
.alu_out ( MEM_WB_alu_out ),
.write_data ( wreg_data ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int max_n = 105; int n; int a[max_n]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); vector<int> V; sort(a, a + n); for (int nb = 1; nb <= n; nb++) { V.clear(); for (int i = 0; i < nb; i++) V.push_back(a[n - i - 1]); bool pos = 1; for (int i = n - nb - 1; i >= 0; i--) { int mx = 0, mj = 0; for (int j = 0; j < nb; j++) if (mx < V[j]) { mx = V[j]; mj = j; } if (mx > 0) { V[mj] = min(V[mj] - 1, a[i]); } else pos = 0; } if (pos) { printf( %d n , nb); return 0; } } return 0; }
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: twiddle_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module twiddle_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [6:0] rdaddress;
input [6:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef SIMULATION
altsyncram_component.init_file = "../../dgn/rtl/altera/twiddle_ram.mif",
`else //for syn
altsyncram_component.init_file = "../rtl/altera/twiddle_ram.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "twiddle_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "twiddle_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 7 0 INPUT NODEFVAL "rdaddress[6..0]"
// Retrieval info: USED_PORT: wraddress 0 0 7 0 INPUT NODEFVAL "wraddress[6..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 7 0 wraddress 0 0 7 0
// Retrieval info: CONNECT: @address_b 0 0 7 0 rdaddress 0 0 7 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twiddle_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int mn[200010 * 4], lazy_value[4 * 200010]; bool lazy[4 * 200010]; void update_node(int idx, int st, int ed, int val) { lazy[idx] = 1; lazy_value[idx] += val; mn[idx] += val; } void update_lazy(int idx, int st, int ed) { if (st == ed) return; int mid = (st + ed) / 2; update_node(2 * idx, st, mid, lazy_value[idx]); update_node(2 * idx + 1, mid + 1, ed, lazy_value[idx]); lazy[idx] = lazy_value[idx] = 0; } void insert(int idx, int st, int ed, int s, int e, int val) { if (st == s && ed == e) { update_node(idx, st, ed, val); return; } if (lazy[idx]) update_lazy(idx, st, ed); int mid = (st + ed) / 2; if (e <= mid) insert(idx * 2, st, mid, s, e, val); else if (s > mid) insert(idx * 2 + 1, mid + 1, ed, s, e, val); else { insert(idx * 2, st, mid, s, mid, val); insert(idx * 2 + 1, mid + 1, ed, mid + 1, e, val); } mn[idx] = min(mn[idx * 2], mn[idx * 2 + 1]); } int query(int idx, int st, int ed, int s, int e) { if (st == s && ed == e) return mn[idx]; if (lazy[idx]) update_lazy(idx, st, ed); int mid = (st + ed) / 2; if (mid >= e) return query(2 * idx, st, mid, s, e); else if (s > mid) return query(2 * idx + 1, mid + 1, ed, s, e); else return min(query(idx * 2, st, mid, s, mid), query(idx * 2 + 1, mid + 1, ed, mid + 1, e)); } int main() { int n, val, i, q, cnt, st, ed; string s_line; cin >> n; for (i = 0; i < n; i++) { cin >> val; insert(1, 0, n - 1, i, i, val); } cin >> q; getchar(); while (q--) { getline(cin, s_line); stringstream ss1; ss1 << s_line; ss1 >> st; ss1 >> ed; cnt = 0; while (ss1 >> val) cnt++; if (cnt) { if (st > ed) { insert(1, 0, n - 1, st, n - 1, val); insert(1, 0, n - 1, 0, ed, val); } else insert(1, 0, n - 1, st, ed, val); } else { if (st > ed) cout << min(query(1, 0, n - 1, st, n - 1), query(1, 0, n - 1, 0, ed)); else cout << query(1, 0, n - 1, st, ed); cout << endl; } } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//deco que pasa de BCD a la salida del display, cada caso es la salida
module bcd_to_display(
input clk,
input rst,
input [3:0] BCD,
output reg[7:0] DISPLAY
);
initial begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
always @ (posedge clk)
begin
if (rst)
begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
else
begin
case (BCD)
4'b0000: DISPLAY = 8'b11111110;// ---- espera
4'b0001: DISPLAY = 8'b11001111;// Piso 1
4'b0010: DISPLAY = 8'b10010010;// Piso 2
4'b0011: DISPLAY = 8'b10000110;// Piso 3
4'b0100: DISPLAY = 8'b11001100;// Piso 4
4'b0101: DISPLAY = 8'b10100100;// Sube
4'b0110: DISPLAY = 8'b10001000;// Abierto
4'b0111: DISPLAY = 8'b10110001;// Cerrado
4'b1000: DISPLAY = 8'b10000000;// Baja
4'b1001: DISPLAY = 8'b10011000;// indica el Piso
default: DISPLAY = 8'b0;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct edge { int v, c, i, d; edge(int v, int c, int i, int d) : v(v), c(c), i(i), d(d) {} }; vector<vector<edge> > g(200005); int n, m, d[200005], f[200005]; int main() { cin >> n >> m; for (int _n = m, i = 0; i < _n; ++i) { int a, b, c; cin >> a >> b >> c; a--; b--; g[a].push_back(edge(b, c, i, 0)); g[b].push_back(edge(a, c, i, 1)); f[a] += c; f[b] += c; } for (int _n = n, i = 0; i < _n; ++i) f[i] /= 2; queue<int> Q; Q.push(0); memset(d, -1, sizeof(d)); while (!Q.empty()) { int u = Q.front(); Q.pop(); for (int _n = int((g[u]).size()), i = 0; i < _n; ++i) { int id = g[u][i].i; if (d[id] == -1) { d[id] = g[u][i].d; int v = g[u][i].v; f[v] -= g[u][i].c; if (f[v] == 0 && v != n - 1) Q.push(v); } } } for (int _n = m, i = 0; i < _n; ++i) cout << d[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e4 + 6; int n, l, r, h[N], b[N], ans[N], S; vector<int> X, Y; int main() { scanf( %d%d%d , &n, &l, &r); for (int i = 1; i <= n; ++i) scanf( %d , h + i), S += h[i]; for (int i = 1; i <= n; ++i) scanf( %d , b + i); int _l = S - r, _r = S - l; for (int i = 1; i <= n; ++i) (b[i] ? Y : X).push_back(h[i]); sort(X.rbegin(), X.rend()), sort(Y.rbegin(), Y.rend()); for (int i = 1; i <= 10000; ++i) ans[i] = -1e9; for (int s : X) for (int i = 10000; i >= s; --i) if (ans[i - s] >= 0) ans[i] = max(ans[i], ans[i - s]); for (int s : Y) for (int i = 10000; i >= s; --i) if (ans[i - s] >= 0) ans[i] = max(ans[i], ans[i - s] + (_l <= i && i <= _r)); printf( %d n , *max_element(ans, ans + 10001)); }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e18; const long long mod = 1e9; long long dp[100005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long i; long long a[n]; set<long long> s; long long c = 0; for (i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); if (i > 0) { if (a[i] != a[i - 1]) { c++; } } } long long d = s.size(); if (d <= k) { cout << 1 << endl; } else { if (k == 1 && (d != k)) { cout << -1 << endl; } else { cout << (((c % (k - 1)) == 0) ? (c / (k - 1)) : (c / (k - 1) + 1)) << endl; } } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] wr_data;
reg wr_en;
wire [31:0] rd_data;
wire [1:0] rd_guards;
wire [1:0] rd_guardsok;
regfile regfile (/*AUTOINST*/
// Outputs
.rd_data (rd_data[31:0]),
.rd_guards (rd_guards[1:0]),
.rd_guardsok (rd_guardsok[1:0]),
// Inputs
.wr_data (wr_data[31:0]),
.wr_en (wr_en),
.clk (clk));
initial wr_en = 0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (!rd_guards[0]) $stop;
if (!rd_guardsok[0]) $stop;
wr_en <= 1'b1;
wr_data <= 32'hfeedf;
end
if (cyc==2) begin
wr_en <= 0;
end
if (cyc==3) begin
wr_en <= 0;
if (rd_data != 32'hfeedf) $stop;
if (rd_guards != 2'b11) $stop;
if (rd_guardsok != 2'b11) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module regfile (
input [31:0] wr_data,
input wr_en,
output reg [31:0] rd_data,
output [1:0] rd_guards /*verilator public*/,
output [1:0] rd_guardsok /*verilator public*/,
input clk
);
always @(posedge clk) begin
if (wr_en)
begin
rd_data <= wr_data;
end
end
// this initial statement will induce correct initialize behavior
// initial rd_guards= { 2'b11 };
assign rd_guards= {
rd_data[0],
1'b1
};
assign rd_guardsok[0] = 1'b1;
assign rd_guardsok[1] = rd_data[0];
endmodule // regfile
|
#include <bits/stdc++.h> const int maxn = 1e2 + 10; const int dis[4][2] = {{0, 1}, {-1, 0}, {0, -1}, {1, 0}}; using namespace std; long long gcd(long long p, long long q) { return q == 0 ? p : gcd(q, p % q); } long long qpow(long long p, long long q) { long long f = 1; while (q) { if (q & 1) f = f * p % 1000000007; p = p * p % 1000000007; q >>= 1; } return f; } int n, m, k, t, q, co[maxn][maxn], c[maxn]; long long dp[maxn][maxn][maxn]; int main() { int i, j; for (i = 0; i <= 100; i++) for (j = 0; j <= 100; j++) for (k = 0; k <= 100; k++) dp[i][j][k] = 1e18; scanf( %d%d%d , &n, &m, &q); for (i = 1; i <= n; i++) scanf( %d , &c[i]); for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) scanf( %d , &co[i][j]); i = 1; if (i == 1) { if (c[i]) dp[1][c[i]][1] = 0; else { for (j = 1; j <= m; j++) dp[1][j][1] = co[1][j]; } } for (i = 2; i <= n; i++) { if (c[i]) { for (j = 1; j <= m; j++) for (k = 1; k <= 100; k++) { if (j == c[i]) dp[i][j][k] = min(dp[i - 1][j][k], dp[i][j][k]); else dp[i][c[i]][k] = min(dp[i - 1][j][k - 1], dp[i][c[i]][k]); } } else { for (j = 1; j <= m; j++) for (k = 1; k <= 100; k++) for (t = 1; t <= m; t++) { dp[i][j][k] = min(dp[i][j][k], t == j ? dp[i - 1][t][k] + co[i][j] : dp[i - 1][t][k - 1] + co[i][j]); } } } long long mi = 1e18; for (i = 1; i <= m; i++) mi = min(dp[n][i][q], mi); printf( %lld n , mi == 1e18 ? -1 : mi); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_2_V
`define SKY130_FD_SC_HD__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_2_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using u64 = uint64_t; using u32 = uint32_t; using pi = pair<int, int>; using pl = pair<ll, ll>; using vi = vector<int>; using vl = vector<ll>; using vvi = vector<vi>; using vpi = vector<pi>; static constexpr int INF = (int)1e9; static constexpr ll INFL = (ll)1e18; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, m; cin >> n >> m; vector<string> s(n), t(m); for (auto& si : s) cin >> si; for (auto& ti : t) cin >> ti; int q, y; cin >> q; while (q--) cin >> y, --y, cout << s[y % n] << t[y % m] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); }; long long t; cin >> t; while (t--) { long long a, b, n, s; cin >> a >> b >> n >> s; bool ans = false; long long f = s / n; s -= min(f, a) * n; if (s <= b) { cout << YES n ; } else { cout << NO n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 2e5 + 5; vector<int> G[M]; int n, A[M], num, ok, res, ans[2][M], C; bool mark[M]; void ma(int a, int b) { if (a == b || mark[a] && mark[b]) return; printf( %d %d n , a, b); ans[0][C] = a; ans[1][C] = b; C++; mark[a] = mark[b] = 1; ma(A[a], A[b]); } int main() { scanf( %d , &n); res = -1; for (int i = 1; i <= n; i++) scanf( %d , A + i); for (int i = 1; i <= n; i++) { int nw = A[i], has = 0; while (!mark[nw]) { has = 1; mark[nw] = 1; G[num].push_back(nw); nw = A[nw]; } if (G[num].size() == 1) ok = A[i]; if (G[num].size() == 2) res = num; if (has) num++; } memset(mark, 0, sizeof(mark)); if (ok) { puts( YES ); for (int i = 1; i <= n; i++) if (i != ok) printf( %d %d n , ok, i); } else if (~res) { for (int i = 0; i < num; i++) if (G[i].size() & 1) { puts( NO ); return 0; } puts( YES ); printf( %d %d n , G[res][0], A[G[res][0]]); for (int i = 0; i < num; i++) if (res != i) ma(G[res][0], G[i][0]); } else puts( NO ); return 0; }
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.eqz2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.eqz2_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; string s[102]; int main() { int n, i, cnt[27], j, k; cin >> n; for (i = 0; i < n; i++) cin >> s[i]; int ans = 0, temp, first, second, x, r; for (i = 1; i <= 26; i++) { for (j = 1; j <= 26; j++) { temp = 0; for (k = 0; k < n; k++) { memset(cnt, 0, sizeof(cnt)); x = 0; for (r = 0; r < s[k].size(); r++) { cnt[(int)s[k][r] - 96]++; } for (r = 1; r <= 26; r++) { if (cnt[r]) x++; } if (x <= 2) { int flag = 0; for (r = 1; r <= 26; r++) { if (cnt[r]) { if (r != i && r != j) flag = 1; } } if (flag == 0) temp += s[k].size(); } } ans = max(ans, temp); } } cout << ans << endl; return 0; }
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_0_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_0_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:35:33 09/12/2015
// Design Name: Truth table implementation of 4:3 encoder.
// Module Name: encoder43table
//////////////////////////////////////////////////////////////////////////////////
module encoder43table(A, B, C, D, Y2, Y1, Y0);
input A, B, C, D;
output reg Y2, Y1, Y0;
always@(A, B, C, D)
case({A, B, C, D})
4'b0000: {Y2, Y1, Y0} = 3'b000;
4'b0001: {Y2, Y1, Y0} = 3'b001;
4'b0010: {Y2, Y1, Y0} = 3'b001;
4'b0011: {Y2, Y1, Y0} = 3'b010;
4'b0100: {Y2, Y1, Y0} = 3'b001;
4'b0101: {Y2, Y1, Y0} = 3'b010;
4'b0110: {Y2, Y1, Y0} = 3'b010;
4'b0111: {Y2, Y1, Y0} = 3'b011;
4'b1000: {Y2, Y1, Y0} = 3'b001;
4'b1001: {Y2, Y1, Y0} = 3'b010;
4'b1010: {Y2, Y1, Y0} = 3'b010;
4'b1011: {Y2, Y1, Y0} = 3'b011;
4'b1100: {Y2, Y1, Y0} = 3'b010;
4'b1101: {Y2, Y1, Y0} = 3'b011;
4'b1110: {Y2, Y1, Y0} = 3'b011;
4'b1111: {Y2, Y1, Y0} = 3'b100;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, Q, ans[100005], t[265000]; vector<int> v[100005]; vector<pair<int, int> > vq[100005]; void build(int k, int l, int r) { t[k] = 1e9; if (l == r) return; int mid = (l + r) / 2; build(k * 2, l, mid); build(k * 2 + 1, mid + 1, r); } void pushdown(int k) { t[k * 2] = min(t[k * 2], t[k]); t[k * 2 + 1] = min(t[k * 2 + 1], t[k]); } void change(int k, int l, int r, int x, int y, int v) { if (t[k] <= v) return; if (l == x && r == y) { t[k] = v; return; } int mid = (l + r) / 2; pushdown(k); if (y <= mid) change(k * 2, l, mid, x, y, v); else if (x > mid) change(k * 2 + 1, mid + 1, r, x, y, v); else change(k * 2, l, mid, x, mid, v), change(k * 2 + 1, mid + 1, r, mid + 1, y, v); t[k] = max(t[k * 2], t[k * 2 + 1]); } int ask(int k, int l, int r, int p, int v) { if (t[k] <= v) return -1; if (p <= l) { for (; l < r;) { int mid = (l + r) / 2; pushdown(k); k *= 2; if (t[k] > v) r = mid; else l = mid + 1, k++; } return l; } int mid = (l + r) / 2; int tmp = -1; if (p <= mid) tmp = ask(k * 2, l, mid, p, v); if (tmp != -1) return tmp; return ask(k * 2 + 1, mid + 1, r, p, v); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); if (x < y) v[x].push_back(y); } scanf( %d , &Q); for (int i = 1; i <= Q; i++) { int x, y; scanf( %d%d , &x, &y); vq[x].push_back(make_pair(y, i)); } build(1, 1, n); for (int i = n; i; i--) { for (int j = 0; j < v[i].size(); j++) change(1, 1, n, i, v[i][j] - 1, v[i][j]); for (int j = 0; j < vq[i].size(); j++) ans[vq[i][j].second] = ask(1, 1, n, i, vq[i][j].first); } for (int i = 1; i <= Q; i++) printf( %d n , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; int t, n, m, k, a, b, ans; int maxl = 1e9; int num[300005]; int main() { scanf( %d , &t); while (t--) { scanf( %d%d%d , &n, &m, &k); if (m <= k) k = m - 1; a = n - m + 1; b = n - k; for (int i = 1; i <= n; i++) { scanf( %d , &num[i]); } ans = 0; for (int i = 1; i <= n; i++) { if (i + b - 1 > n) break; int ansl = maxl; for (int j = i; j <= i + b - 1; j++) { if (j + a - 1 > i + b - 1) break; ansl = min(ansl, max(num[j], num[j + a - 1])); } ans = max(ans, ansl); } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> class MapValue { public: std::string configuration; int s1; MapValue() {} MapValue(std::string configuration, int s1) : configuration(configuration), s1(s1) {} }; class PairHash { public: std::size_t operator()(const std::pair<int, int> &p) const { return std::hash<int>()(p.first) ^ std::hash<int>()(p.second); } }; std::unordered_map<std::pair<int, int>, MapValue, PairHash> my_map; int A[100], B[100], C[100], q_rez = -0x3f3f3f3f; std::string rrr = Impossible ; void back(int s1, int s2, int s3, int k, int max, std::string ss) { if (k == max + 1) { my_map.emplace(std::make_pair(s2 - s1, s3 - s2), MapValue(ss, s1)); return; } s1 += A[k]; s2 += B[k]; back(s1, s2, s3, k + 1, max, ss + LM n ); s1 -= A[k]; s3 += C[k]; back(s1, s2, s3, k + 1, max, ss + MW n ); s2 -= B[k]; s1 += A[k]; back(s1, s2, s3, k + 1, max, ss + LW n ); } void back2(int s1, int s2, int s3, int k, int max, std::string ss) { if (k == max + 1) { std::string result; auto it = my_map.find(std::make_pair(s1 - s2, s2 - s3)); if (it != my_map.end()) { int q = s1 + it->second.s1; if (q > q_rez) { rrr = it->second.configuration + ss; q_rez = q; } } return; } s1 += A[k]; s2 += B[k]; back2(s1, s2, s3, k + 1, max, ss + LM n ); s1 -= A[k]; s3 += C[k]; back2(s1, s2, s3, k + 1, max, ss + MW n ); s2 -= B[k]; s1 += A[k]; back2(s1, s2, s3, k + 1, max, ss + LW n ); } int main() { int N; std::cin >> N; for (int i = 1; i <= N; i++) { std::cin >> A[i] >> B[i] >> C[i]; } std::string ss = ; back(0, 0, 0, 1, N / 2, ss); ss = ; back2(0, 0, 0, N / 2 + 1, N, ss); std::cout << rrr; }
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: uart_fifo_dual_port_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module uart_fifo_dual_port_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [9:0] rdaddress;
input [9:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL "rdaddress[9..0]"
// Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL "wraddress[9..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
// Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_dual_port_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long Inv[1000005]; void inv(int n) { Inv[1] = 1; for (int i = 2; i <= n; i++) { Inv[i] = (mod - mod / i * Inv[mod % i] % mod) % mod; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; long long tot = 1; for (int i = 1; i < n + 1; i++) { tot *= i; tot %= mod; } vector<int> v; for (int i = 0; i < n; i++) { int add; cin >> add; v.push_back(add); } inv(n); sort(v.rbegin(), v.rend()); long long cur = 0; long long ans = 0; int last = 0; int cnt = 0; for (int i = 0; i < n; i++) { if (v[i] == last) { cur++; cnt++; continue; } if (last != v[0]) { ans += tot * last % mod * Inv[cur] % mod * cnt % mod; ans %= mod; } cur++; cnt = 1; last = v[i]; } if (last != v[0]) { ans += tot * last % mod * Inv[cur] % mod * cnt % mod; ans %= mod; } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int d1, d2, d3; int r; int main() { cin >> d1 >> d2 >> d3; r = d1 + d2 + d3; r = min(r, d1 + d1 + d2 + d2); r = min(r, d1 + d3 + d1 + d3); r = min(r, d2 + d3 + d2 + d3); cout << r << n ; }
|
#include <bits/stdc++.h> using namespace std; int n; long long K; vector<int> E[200000 + 5]; void addEdge(int u, int v) { E[u].push_back(v); E[v].push_back(u); } int sz[200000 + 5], deep[200000 + 5], fa[200000 + 5]; int msz[200000 + 5], root; void dfs1(int x, int f) { sz[x] = 1; msz[x] = 0; for (int y : E[x]) { if (y != f) { dfs1(y, x); sz[x] += sz[y]; msz[x] = max(msz[x], sz[y]); } } msz[x] = max(msz[x], n - sz[x]); if (root == 0 || msz[x] < msz[root]) root = x; } set<pair<int, int> > S[200000 + 5]; long long minans = 0, maxans = 0; int sons[200000 + 5]; void dfs2(int x, int f, int rt) { sz[x] = 1; fa[x] = f; deep[x] = deep[f] + 1; for (int y : E[x]) { if (y != f) { sons[x]++; dfs2(y, x, rt); sz[x] += sz[y]; } } if (sz[x] > 1) S[rt].insert(make_pair(deep[x], x)); minans += sz[x] % 2; maxans += sz[x]; } bool vis[200000 + 5]; int getSon(int x) { for (int t : E[x]) { if (t != fa[x] && !vis[t]) { vis[t] = 1; return t; } } return x; } void del(int x, int rt) { vis[x] = 1; sons[fa[x]]--; if (sons[fa[x]] == 0) S[rt].erase(make_pair(deep[fa[x]], fa[x])); } priority_queue<pair<int, int> > q; vector<int> ans; void dfs3(int x) { if (!vis[x]) ans.push_back(x); for (int y : E[x]) if (y != fa[x]) dfs3(y); } int main() { scanf( %d %lld , &n, &K); for (int i = 1, u, v; i < n; i++) { scanf( %d %d , &u, &v); addEdge(u, v); } dfs1(1, 0); for (int y : E[root]) { dfs2(y, root, y); q.push(make_pair(sz[y], y)); } if (K >= minans && K <= maxans && (maxans - K) % 2 == 0) { puts( YES ); K = (maxans - K) / 2; while (K) { int rt = q.top().second; q.pop(); int lc = S[rt].rbegin()->second; int d = deep[lc]; if (K >= d) { K -= d; int u = getSon(lc), v = getSon(lc); del(u, rt); del(v, rt); printf( %d %d n , u, v); } else { int u = S[rt].lower_bound(make_pair(K, 0))->second; int v = getSon(u); del(u, rt); del(v, rt); printf( %d %d n , u, v); break; } sz[rt] -= 2; if (sz[rt] > 1) q.push(make_pair(sz[rt], rt)); } dfs3(root); for (int i = 0; i < (int)ans.size() / 2; i++) printf( %d %d n , ans[i], ans[i + (int)ans.size() / 2]); } else puts( NO ); }
|
module top(
input PACKAGEPIN,
output [1:0] PLLOUTCORE,
output [1:0] PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_2_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT_PORTB("GENCLK"),
// .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
.PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
.PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.02.2016 18:21:15
// Design Name:
// Module Name: toplevelv
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toplevel
(DC,
RES,
SCLK,
SDIN,
VBAT,
VDD,
JA1,
JA2,
JA3,
JA4,
JA7,
JA8,
JA9,
JA10,
SW0,
SW1,
SW2,
SW3,
SW4,
SW5,
SW6,
SW7,
LD0,
LD1,
LD2,
LD3,
LD4,
LD5,
LD6,
LD7,
GCLK
);
output wire JA1;
output wire JA2;
output wire JA3;
output wire JA4;
output wire JA7;
output wire JA8;
output wire JA9;
output wire JA10;
output wire DC;
output wire RES;
output wire SCLK;
output wire SDIN;
output wire VBAT;
output wire VDD;
input wire SW0;
input wire SW1;
input wire SW2;
input wire SW3;
input wire SW4;
input wire SW5;
input wire SW6;
input wire SW7;
output wire LD0;
output wire LD1;
output wire LD2;
output wire LD3;
output wire LD4;
output wire LD5;
output wire LD6;
output wire LD7;
input wire GCLK;
reg [127:0] str;
always @(posedge GCLK) begin
if (SW1 == 1'b1) begin
str <= "Hello, world!";
end
else begin
str <= "************";
end
end
ZedboardOLED OLED
(
.s1(str),
.s2(str),
.s3(str),
.s4(str),
.DC(DC),
.RES(RES),
.SCLK(SCLK),
.SDIN(SDIN),
.VBAT(VBAT),
.VDD(VDD),
.CLK(GCLK)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long MOD_EXPO(long long b, long long p, long long m) { if (p == 0) return 1; long long ret = MOD_EXPO(b, p / 2, m) % m; ret = (ret * ret) % m; return ((p & 1) ? (ret * b) % m : ret % m); } long long POWER(long long N, long long K) { long long i, ans = 1; for (i = 1; i <= K; i++) ans *= N; return ans; } int SET(int N, int pos) { return (N | (1 << pos)); } int RESET(int N, int pos) { return (N & !(1 << pos)); } bool CHECK(int N, int pos) { return (N & (1 << pos)); } int dx4[] = {1, -1, 0, 0}; int dy4[] = {0, 0, 1, -1}; int dx6[] = {0, 0, 1, -1, 0, 0}; int dy6[] = {1, -1, 0, 0, 0, 0}; int dz6[] = {0, 0, 0, 0, 1, -1}; int dx8[] = {1, -1, 0, 0, -1, 1, -1, 1}; int dy8[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dkx8[] = {-1, 1, -1, 1, -2, -2, 2, 2}; int dky8[] = {2, 2, -2, -2, 1, -1, 1, -1}; int tc = 1; const double eps = 1e-9; const double pi = acos(-1.0); const long long int mx = 1e3; const long long int mod = 1e9 + 7; int dp[5][mx + 5]; int n, arr[mx + 5]; string str; int rec(int i, int prev) { if (i > n) return 0; int &ret = dp[prev][i]; if (ret != -1) return ret; ret = INT_MAX; if (prev != 0) ret = min(ret, rec(i + 1, 0) + (arr[i] != 0)); if (prev != 1) ret = min(ret, rec(i + 1, 1) + (arr[i] != 1)); return ret; } int main() { int i; while (cin >> n >> str) { for (i = 1; i <= n; i++) arr[i] = (str[i - 1] - 0 ); memset(dp, -1, sizeof(dp)); cout << rec(1, 2) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int a; priority_queue<long long int> o, e; for (long long int i = 0; i < n; i++) { cin >> a; if (a % 2 == 0) e.push(a); else o.push(a); } if (e.size() == o.size()) { cout << 0; return 0; } long long int mi = min(e.size(), o.size()); if (e.size() == mi) { for (long long int i = 0; i < mi; i++) e.pop(); for (long long int i = 0; i < mi + 1; i++) o.pop(); } else { for (long long int i = 0; i < mi; i++) o.pop(); for (long long int i = 0; i < mi + 1; i++) e.pop(); } long long int sum = 0; while (!e.empty()) { sum += e.top(); e.pop(); } while (!o.empty()) { sum += o.top(); o.pop(); } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; if (c <= b / 2 && c <= a / 2) cout << First ; else cout << Second ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_SYMBOL_V
`define SKY130_FD_SC_LP__A41O_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_SYMBOL_V
|
module test;
reg fail = 1'b0;
reg [3:0] bus = 4'b0;
initial begin
// Check the initial value.
if (bus !== 4'b0) begin
$display("FAILED: initial value, got %b, expected 0000.", bus);
fail = 1;
end
// Check a bit force and verify a normal bit assign does nothing.
#1 force bus[0] = 1'b1;
bus[0] = 1'bz;
if (bus !== 4'b0001) begin
$display("FAILED: force of bus[0], got %b, expected 0001.", bus);
fail = 1'b1;
end
// Check a part force
#1 force bus[3:2] = 2'b11;
if (bus !== 4'b1101) begin
$display("FAILED: force of bus[3:2], got %b, expected 1101.", bus);
fail = 1'b1;
end
// Check that we can change an unforced bit.
#1 bus[1] = 1'bz;
if (bus !== 4'b11z1) begin
$display("FAILED: assignment of bus[1], got %b, expected 11z1.", bus);
fail = 1'b1;
end
#1 bus[1] = 1'b0;
// Check a bit release.
#1 release bus[0];
bus = 4'b000z;
if (bus !== 4'b110z) begin
$display("FAILED: release of bus[0], got %b, expected 110z.", bus);
fail = 1'b1;
end
// Check a part release.
#1 release bus[3:2];
bus[3] = 1'b0;
if (bus !== 4'b010z) begin
$display("FAILED: release of bus[3:2], got %b, expected 010z.", bus);
fail = 1'b1;
end
// Check a force from the upper thread bits (>=8).
#1 force bus[2:1] = 2'bx1;
if (bus !== 4'b0x1z) begin
$display("FAILED: force of bus[2:1], got %b, expected 0x1z.", bus);
fail = 1'b1;
end
if (!fail) $display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S15_TB_V
`define SKY130_FD_SC_LP__DLYGATE4S15_TB_V
/**
* dlygate4s15: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlygate4s15.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlygate4s15 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S15_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > v, a; vector<pair<double, int> > ans; int n, sum, del, sx, sy, x, y, Nx, Ny; set<int> u; int cmp(pair<int, int> a, pair<int, int> b) { return ((a.first) * (a.first)) + ((a.second) * (a.second)) < ((b.first) * (b.first)) + ((b.second) * (b.second)); } int main() { v.clear(); u.clear(); for (int i = 0; i <= 200; i++) for (int j = i; j <= 200; j++) if (i + j) if (!u.count(((i) * (i)) + ((j) * (j)))) v.push_back(make_pair(i, j)), u.insert(((i) * (i)) + ((j) * (j))); sort(v.begin(), v.end(), cmp); cin >> n; sum = 0; for (int i = 0; i < n; i++) sum += (v[i].first + v[i].second) & 1; a.clear(); del = n; if (sum & 1) { sum += (v[n].first + v[n].second) & 1; for (int i = n - 1; i >= 0; i--) if (!((sum - ((v[i].first + v[i].second) & 1)) & 1)) { del = i; break; } } for (int i = 0; i <= n; i++) if (del != i) a.push_back(v[i]); sx = sy = 0; for (int i = n - 1; i >= 0; i--) { x = a[i].first, y = a[i].second; for (int s = 0; s < 8; s++) { Nx = x, Ny = y; if (s & 1) swap(Nx, Ny); if (s & 2) Nx *= -1; if (s & 4) Ny *= -1; if (((sx + a[i].first) * (sx + a[i].first)) + ((sy + a[i].second) * (sy + a[i].second)) > ((sx + Nx) * (sx + Nx)) + ((sy + Ny) * (sy + Ny))) a[i] = make_pair(Nx, Ny); } sx += a[i].first, sy += a[i].second; } for (int i = 0; i < n; i++) ans.push_back(make_pair(atan2(a[i].second, a[i].first), i)); sort(ans.begin(), ans.end()); cout << YES << endl; sx = 0, sy = 0; for (int i = 0; i < n; i++) { cout << sx << << sy << endl; int id = ans[i].second; sx += a[id].first, sy += a[id].second; } return 0; }
|
module ram0(
// Write port
input wrclk,
input [63:0] di,
input wren,
input [8:0] wraddr,
// Read port
input rdclk,
input rden,
input [8:0] rdaddr,
output reg [63:0] do);
(* ram_style = "block" *) reg [63:0] ram[0:511];
genvar i;
generate
for (i=0; i<1024; i=i+1)
begin
initial begin
ram[i] <= i;
end
end
endgenerate
always @ (posedge wrclk) begin
if (wren == 1) begin
ram[wraddr] <= di;
end
end
always @ (posedge rdclk) begin
if (rden == 1) begin
do <= ram[rdaddr];
end
end
endmodule
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [8:0] write_address;
wire [8:0] read_address;
wire [63:0] read_data;
wire [63:0] write_data;
wire write_enable;
wire read_enable = !write_enable;
wire [8:0] rom_read_address;
reg [63:0] rom_read_data;
always @(posedge clk) begin
rom_read_data[8:0] <= rom_read_address;
rom_read_data[63:9] <= 1'b0;
end
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [8:0] error_address;
wire [63:0] expected_data;
wire [63:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(10),
.DATA_WIDTH(64),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(1),
.MAX_ADDRESS(511),
.LFSR_WIDTH(64),
.LFSR_POLY(64'hd800000000000000) // from Xilinx XAPP52 pg.5
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
) bram (
// Write port
.wrclk(clk),
.di(write_data),
.wren(write_enable),
.wraddr(write_address),
// Read port
.rdclk(clk),
.rden(read_enable),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(64),
.ADDR_WIDTH(10)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
// Copyright 2012 Sriram Radhakrishnan, Varun Sampath, Shilpa Sarode
//
// This file is part of PVS.
//
// PVS is free software: you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the Free Software
// Foundation, either version 3 of the License, or (at your option) any later
// version.
//
// PVS is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// PVS. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns / 1 ns
// catches a pace and widens it using COUNT
// inputs:
// clk_fast - rate to latch input signal
// clk_slow - rate to increment counter
// signal_i - input signal
// output:
// signal_o - output signal
// parameter:
// COUNT - counter val for width, default 15
module pace_catcher
(
clk_fast,
clk_slow,
signal_i,
signal_o
);
//////////// INPUTS & OUTPUTS ////////////
input clk_fast;
input clk_slow;
input signal_i;
output signal_o;
//////////// PARAMETERS ////////////
parameter COUNT = 15; // with clk of 1.5kHz corresponds to 10ms width
parameter s_idle = 0;
parameter s_out = 1;
//////////// SIGNALS & REGS ////////////
reg[15:0] cnt = 0;
reg state = 0;
//////////// LOGIC ////////////
// runs at fast clock to catch input signal
always @(posedge clk_fast) begin
case(state)
s_idle:
begin
state <= (signal_i) ? s_out : s_idle;
end
s_out:
begin
state <= (cnt >= COUNT) ? s_idle : s_out;
end
endcase
end
// runs at slow clock to increment slowly
always @(posedge clk_slow) begin
if (state == s_out) cnt <= cnt + 8'b1;
else if (state == s_idle) cnt <= 8'b0;
end
//////////// OUTPUT ASSIGNS ////////////
assign signal_o = (state == s_out);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 10, INF = 2147483647; int a[MAXN]; int main() { int T, n, i, res = 0; scanf( %d , &T); while (T--) { res = 0; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int ed = a[n]; res = a[n]; bool f2 = 0, f3 = 0, f5 = 0; for (i = 1; i <= n; i++) { if (a[i] * 2 == ed) f2 = true; if (a[i] * 3 == ed) f3 = true; if (a[i] * 5 == ed) f5 = true; } if (f2 && f3 && f5) res = max(res, ed / 2 + ed / 3 + ed / 5); for (i = 1; i <= n; i++) if (a[n] % a[i] == 0) a[i] = INF; sort(a + 1, a + n + 1); while (a[n] == INF) n--; res = max(res, ed + a[n]); for (i = n - 1; i >= 1; i--) if (a[n] % a[i] != 0) { res = max(res, ed + a[n] + a[i]); break; } printf( %d n , res); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-10; const long double INF = (int)1e9 + 34; const int N = (int)1e6 + 34; void ret(int x) { cout << x; exit(0); } int n, k; int a[N]; int b[N], len; bool u[N]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , a + i); srand(3431); sort(a, a + n); a[n] = 100000000; int lst = a[0]; b[len++] = a[0]; for (int i = 1; i < n; i++) if (a[i + 1] - lst >= k) { b[len++] = lst = a[i]; } int mn = a[0]; for (int i = 0; i < n; i++) mn = min(mn, a[i]); vector<int> v; for (int i = 0; i < 30; i++) v.push_back(a[abs((rand() << 16) ^ rand()) % n]); for (int i = 1; i <= 1000000; i++) for (int j = 0; !u[i] && j < (int)v.size(); j++) if (v[j] % i > k) u[i] = true; int l1 = -1; int pr; bool fail; for (int d = mn; d >= 0; d--) { if (u[d]) continue; fail = false; for (int i = 0; !fail && i < len; i++) if (b[i] % d > k) fail = true; if (!fail) { pr = d; break; } l1 = d; } for (int d = pr; d >= 0; d--) { if (u[d]) continue; fail = false; for (int i = n - 1; !fail && i >= 0; i--) if (a[i] % d > k) fail = true; if (!fail) { pr = d; break; } l1 = d; } cout << pr; return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse4 ) using namespace std; constexpr long long mod = 1000000007; const long long INF = mod * mod; const double eps = 1e-12; const double pi = acosl(-1.0); long long mod_pow(long long x, long long n, long long m = mod) { long long res = 1; while (n) { if (n & 1) res = res * x % m; x = x * x % m; n >>= 1; } return res; } struct modint { long long n; modint() : n(0) { ; } modint(long long m) : n(m) { if (n >= mod) n %= mod; else if (n < 0) n = (n % mod + mod) % mod; } operator int() { return n; } }; bool operator==(modint a, modint b) { return a.n == b.n; } modint operator+=(modint& a, modint b) { a.n += b.n; if (a.n >= mod) a.n -= mod; return a; } modint operator-=(modint& a, modint b) { a.n -= b.n; if (a.n < 0) a.n += mod; return a; } modint operator*=(modint& a, modint b) { a.n = ((long long)a.n * b.n) % mod; return a; } modint operator+(modint a, modint b) { return a += b; } modint operator-(modint a, modint b) { return a -= b; } modint operator*(modint a, modint b) { return a *= b; } modint operator^(modint a, long long n) { if (n == 0) return modint(1); modint res = (a * a) ^ (n / 2); if (n % 2) res = res * a; return res; } long long inv(long long a, long long p) { return (a == 1 ? 1 : (1 - p * inv(p % a, a)) / a + p); } modint operator/(modint a, modint b) { return a * modint(inv(b, mod)); } const int max_n = 1 << 10; modint fact[max_n], factinv[max_n]; void init_f() { fact[0] = modint(1); for (int i = 0; i < max_n - 1; i++) { fact[i + 1] = fact[i] * modint(i + 1); } factinv[max_n - 1] = modint(1) / fact[max_n - 1]; for (int i = max_n - 2; i >= 0; i--) { factinv[i] = factinv[i + 1] * modint(i + 1); } } modint comb(int a, int b) { if (a < 0 || b < 0 || a < b) return 0; return fact[a] * factinv[b] * factinv[a - b]; } long long gcd(long long a, long long b) { if (a < b) swap(a, b); while (b) { long long r = a % b; a = b; b = r; } return a; } void solve() { long long a, b; cin >> a >> b; modint ans = 0; for (long long i = 1; i < b; i++) { long long num = a; ans += num * i; modint cr = num * (num + 1) / 2; cr *= i; ans += cr * (modint)b; } cout << ans << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb_pixelfeed #(
parameter fml_depth = 26
) (
input sys_clk,
/* We must take into account both resets :
* VGA reset should not interrupt a pending FML request
* but system reset should.
*/
input sys_rst,
input vga_rst,
input [17:0] nbursts,
input [fml_depth-1:0] baseaddress,
output baseaddress_ack,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
output reg dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
output pixel_valid,
output [15:0] pixel,
input pixel_ack
);
/* FIFO that stores the 64-bit bursts and slices it in 16-bit words */
reg fifo_source_cache;
reg fifo_stb;
wire fifo_valid;
vgafb_fifo64to16 fifo64to16(
.sys_clk(sys_clk),
.vga_rst(vga_rst),
.stb(fifo_stb),
.di(fifo_source_cache ? dcb_dat : fml_di),
.do_valid(fifo_valid),
.do(pixel),
.next(pixel_ack)
);
assign pixel_valid = fifo_valid;
/* BURST COUNTER */
reg sof;
wire counter_en;
reg [17:0] bcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
if(counter_en) begin
if(bcounter == nbursts) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
bcounter <= bcounter + 18'd1;
sof <= 1'b0;
end
end
end
end
/* FML ADDRESS GENERATOR */
wire next_address;
assign baseaddress_ack = sof & next_address;
always @(posedge sys_clk) begin
if(sys_rst) begin
fml_adr <= {fml_depth{1'b0}};
end else begin
if(next_address) begin
if(sof)
fml_adr <= baseaddress;
else
fml_adr <= fml_adr + {{fml_depth-6{1'b0}}, 6'd32};
end
end
end
/* DCB ADDRESS GENERATOR */
reg [1:0] dcb_index;
always @(posedge sys_clk) begin
if(dcb_stb)
dcb_index <= dcb_index + 2'd1;
else
dcb_index <= 2'd0;
end
assign dcb_adr = {fml_adr[fml_depth-1:5], dcb_index, 3'b000};
/* CONTROLLER */
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter TRYCACHE = 4'd1;
parameter CACHE1 = 4'd2;
parameter CACHE2 = 4'd3;
parameter CACHE3 = 4'd4;
parameter CACHE4 = 4'd5;
parameter FML1 = 4'd6;
parameter FML2 = 4'd7;
parameter FML3 = 4'd8;
parameter FML4 = 4'd9;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
/*
* Do not put spurious data into the FIFO if the VGA reset
* is asserted and released during the FML access. Getting
* the FIFO out of sync would result in distorted pictures
* we really want to avoid.
*/
reg ignore;
reg ignore_clear;
always @(posedge sys_clk) begin
if(vga_rst)
ignore <= 1'b1;
else if(ignore_clear)
ignore <= 1'b0;
end
reg next_burst;
assign counter_en = next_burst;
assign next_address = next_burst;
always @(*) begin
next_state = state;
fifo_stb = 1'b0;
next_burst = 1'b0;
fml_stb = 1'b0;
ignore_clear = 1'b0;
dcb_stb = 1'b0;
fifo_source_cache = 1'b0;
case(state)
IDLE: begin
if(~fifo_valid & ~vga_rst) begin
/* We're in need of pixels ! */
next_burst = 1'b1;
ignore_clear = 1'b1;
next_state = TRYCACHE;
end
end
/* Try to fetch from L2 first */
TRYCACHE: begin
dcb_stb = 1'b1;
next_state = CACHE1;
end
CACHE1: begin
fifo_source_cache = 1'b1;
if(dcb_hit) begin
dcb_stb = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE2;
end else
next_state = FML1; /* Not in L2 cache, fetch from DRAM */
end
/* No need to check for cache hits anymore:
* - we fetched from the beginning of a line
* - we fetch exactly a line
* - we do not release dcb_stb so the cache controller locks the line
* Therefore, next 3 fetchs always are cache hits.
*/
CACHE2: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE3;
end
CACHE3: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE4;
end
CACHE4: begin
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
FML1: begin
fml_stb = 1'b1;
if(fml_ack) begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML2;
end
end
FML2: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML3;
end
FML3: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML4;
end
FML4: begin
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:44:18 09/23/2013
// Design Name:
// Module Name: FSM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM(div_clock, reset, enable_cuenta, write_enable,
write_value_reg_en, read_value_reg_en, led_write, led_read, estado);
//ENTRADAS Y SALIDAS
input reset, div_clock;
output write_value_reg_en, read_value_reg_en;
output enable_cuenta, write_enable, led_write, led_read;
output [3:0] estado;
//Definimos todos los estados de la FSM
parameter STATE_0 = 0;
parameter STATE_1 = 1;
parameter STATE_2 = 2;
parameter STATE_3 = 3;
parameter STATE_4 = 4;
//Variable que lleva el estado actual
reg [3:0] state;
//Valores iniciales
initial
begin
state <= -1;
end
//Se hace que la maquina de estados avance con un clock lento
always@(posedge div_clock or posedge reset)
begin
if (reset)
begin
state <= -1;
end
else
begin
case(state)
STATE_0:
begin
state <= STATE_1;
end
STATE_1:
begin
state <= STATE_2;
end
STATE_2:
begin
state <= STATE_3;
end
STATE_3:
begin
state <= STATE_4;
end
STATE_4:
begin
state <= STATE_0;
end
default:
begin
state <= STATE_0;
end
endcase
end
end
assign estado = state;
assign enable_cuenta = (state == STATE_4);
assign write_enable = ~(state == STATE_1);
assign write_value_reg_en = (state == STATE_1);
assign read_value_reg_en = (state == STATE_3);
assign led_write = (state == STATE_0 ) | (state == STATE_1) | (state == STATE_2);
assign led_read = (state == STATE_3) | (state == STATE_4);
endmodule
|
#include <stdio.h> #include <stdlib.h> #define N 200000 #define Q 100000 #define N_ ((N + Q * 2) * (LG + 1)) #define LG 20 #define B (1 << LG) int ll[1 + N_], rr[1 + N_], sz[1 + N_], msk0[1 + N_], msk1[1 + N_], lz[1 + N_], _ = 1; void put(int u, int lg, int x) {int tmp, x0, x1;if (u == 0)return;if ((x & 1 << lg - 1) != 0)tmp = ll[u], ll[u] = rr[u], rr[u] = tmp; x0 = msk0[u] & ~x | msk1[u] & x, x1 = msk1[u] & ~x | msk0[u] & x;msk0[u] = x0, msk1[u] = x1;lz[u] ^= x;} void pus(int u, int lg) {if (lz[u])put(ll[u], lg - 1, lz[u]), put(rr[u], lg - 1, lz[u]), lz[u] = 0;} void pul(int u) {int l = ll[u], r = rr[u];sz[u] = sz[l] + sz[r], msk0[u] = msk0[l] | msk0[r], msk1[u] = msk1[l] | msk1[r];} int add(int u, int lg, int a) {if (u == 0)u = _++;if (lg == 0)sz[u] = 1, msk0[u] = a ^ B - 1, msk1[u] = a; else {if ((a & 1 << lg - 1) == 0)ll[u] = add(ll[u], lg - 1, a);else rr[u] = add(rr[u], lg - 1, a);pul(u);}return u;} void split(int *u, int *v, int lg, int l, int r, int ql, int qr) { int m; if (qr <= l || r <= ql || *u == 0) { *v = 0; return; } if (ql <= l && r <= qr) { *v = *u, *u = 0; return; } pus(*u, lg), *v = _++; m = (l + r) / 2; split(&ll[*u], &ll[*v], lg - 1, l, m, ql, qr), split(&rr[*u], &rr[*v], lg - 1, m, r, ql, qr); pul(*u), pul(*v); } void merge(int *u, int *v, int lg) {if (*u == 0) {*u = *v;return;}if (*v == 0 || lg == 0)return;pus(*u, lg), pus(*v, lg);merge(&ll[*u], &ll[*v], lg - 1), merge(&rr[*u], &rr[*v], lg - 1);pul(*u);} void update_or(int u, int lg, int x) { if (u == 0) return; if ((x & msk0[u] & msk1[u]) == 0) { put(u, lg, x & msk0[u]); return; } pus(u, lg); if ((x & 1 << lg - 1) != 0) put(ll[u], lg - 1, 1 << lg - 1), merge(&rr[u], &ll[u], lg - 1), ll[u] = 0; update_or(ll[u], lg - 1, x), update_or(rr[u], lg - 1, x); pul(u); } int query(int u, int lg, int l, int r, int ql, int qr) { int m; if (qr <= l || r <= ql || u == 0) return 0; if (ql <= l && r <= qr) return sz[u]; pus(u, lg); m = (l + r) / 2; return query(ll[u], lg - 1, l, m, ql, qr) + query(rr[u], lg - 1, m, r, ql, qr); } int main() { int n, q, i, u; scanf( %d%d , &n, &q); u = 0; for (i = 0; i < n; i++) { int a; scanf( %d , &a); u = add(u, LG, a); } while (q--) { int type, l, r; scanf( %d%d%d , &type, &l, &r), r++; if (type != 4) { int x, v; scanf( %d , &x); split(&u, &v, LG, 0, B, l, r); if (type == 1) put(v, LG, B - 1), update_or(v, LG, x ^ B - 1), put(v, LG, B - 1); else if (type == 2) update_or(v, LG, x); else put(v, LG, x); merge(&u, &v, LG); } else printf( %d n , query(u, LG, 0, B, l, r)); } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:13:58 04/26/2015
// Design Name:
// Module Name: HallwayRight
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HallwayRight(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
//Top walls
if((CurrentY < 40) && ~(CurrentX < 0)) begin
mColor[7:0] <= wall;
end
//Right side wall
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
//Bottom wall
else if((~(CurrentY < 440) && (CurrentX < 260)) || (~(CurrentY < 440) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
//floor area - grey
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Bp, typename Ep, typename Mp> inline Mp __powMod(Bp a, Ep b, const Mp &m) { a %= m; Mp res = 1; while (b > 0) { if (b & 1) { res = ((long long)res * a) % m; } a = ((long long)a * a) % m; b >>= 1; } return res % m; } const int MOD = 1e9 + 7; template <typename Tp> inline Tp inv(const Tp &x) { return __powMod(x, MOD - 2, MOD); } const int N = 100000 + 5; int m; int dp[N]; vector<int> prime; int mu[N]; bool notPrime[N]; inline void init() { mu[1] = 1; for (int i = 2; i < N; ++i) { if (!notPrime[i]) { mu[i] = -1; prime.emplace_back(i); } for (const auto &p : prime) { if (i * p >= N) { break; } notPrime[i * p] = true; if (i % p == 0) { mu[i * p] = 0; break; } else { mu[i * p] = -mu[i]; } } } } int main() { init(); scanf( %d , &m); int ans = 1; for (int i = 2, t; i <= m; ++i) { if (mu[i] != 0) { t = m / i; ans = (ans - (long long)mu[i] * t * inv(m - t) % MOD + MOD) % MOD; } } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; long long INF = (1e15) + 1; int n, dp[100004], par[100004]; long long d, arr[100004]; struct Node { Node *leftNode, *rightNode; long long leftBound, rightBound; pair<int, int> mx; Node() { leftNode = rightNode = NULL; leftBound = rightBound = 0LL; mx = {0, 0}; } }; void update(Node *par, long long pos, int dpMax, int ind) { if (par->leftBound == pos && par->rightBound == pos) { if ((par->mx).first < dpMax) { par->mx = {dpMax, ind}; } return; } long long mid = (par->leftBound + par->rightBound) >> 1; if (pos <= mid) { if (par->leftNode == NULL) par->leftNode = new Node(); par->leftNode->leftBound = par->leftBound; par->leftNode->rightBound = mid; update(par->leftNode, pos, dpMax, ind); if ((par->leftNode->mx).first > (par->mx).first) { par->mx = par->leftNode->mx; } } else { if (par->rightNode == NULL) par->rightNode = new Node(); par->rightNode->leftBound = mid + 1; par->rightNode->rightBound = par->rightBound; update(par->rightNode, pos, dpMax, ind); if ((par->rightNode->mx).first > (par->mx).first) { par->mx = par->rightNode->mx; } } } pair<int, int> query(Node *par, long long l, long long r) { if (par == NULL || par->leftBound > r || par->rightBound < l) { return {0, 0}; } if (par->leftBound >= l && par->rightBound <= r) { return par->mx; } long long mid = (par->leftBound + par->rightBound) >> 1; pair<int, int> p1 = query(par->leftNode, l, r); pair<int, int> p2 = query(par->rightNode, l, r); if (p1.first > p2.first) return p1; else return p2; } int main() { scanf( %d%lld , &n, &d); for (int i = 1; i <= n; i++) scanf( %lld , &arr[i]); Node *root = new Node(); root->leftBound = 0LL; root->rightBound = INF; int ans = 0, curInd = 0; for (int i = 1; i <= n; i++) { long long l = max(0LL, arr[i] - d); long long r = min(INF, arr[i] + d); pair<int, int> p1 = query(root, 1LL, l); pair<int, int> p2 = query(root, r, INF); pair<int, int> p = p1; if (p.first < p2.first) p = p2; dp[i] = p.first + 1; par[i] = p.second; update(root, arr[i], dp[i], i); if (dp[i] > ans) { ans = dp[i]; curInd = i; } } printf( %d n , ans); vector<int> inds; while (curInd != 0) { inds.push_back(curInd); curInd = par[curInd]; } reverse(inds.begin(), inds.end()); for (int i = 0; i <= inds.size() - 1; i++) { printf( %d , inds[i]); } return 0; }
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int a[200001]; int i; for (i = 0; i < n; i++) { scanf( %d , &a[i]); } long long buy = a[n - 1]; int pre = a[n - 1]; for (i = n - 2; i >= 0; i--) { if (a[i] >= pre - 1) { if (pre - 1 == 0) break; else buy += pre - 1; pre--; } else { buy += a[i]; pre = a[i]; } } printf( %lld n , buy); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_V
`define SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_lp__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_lp__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_FUNCTIONAL_V
|
module axi_generic_adc (
input adc_clk,
output [NUM_CHANNELS-1:0] adc_enable,
input adc_dovf,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
parameter NUM_CHANNELS = 2;
parameter PCORE_ID = 0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
wire adc_rst;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS];
wire up_rack_s[0:NUM_CHANNELS];
wire up_wack_s[0:NUM_CHANNELS];
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
integer j;
always @(*)
begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= NUM_CHANNELS; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_status_ovf (adc_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd1),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS]),
.up_rack (up_rack_s[NUM_CHANNELS]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i=i+1) begin
up_adc_channel #(.PCORE_ADC_CHID(i)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate
endmodule
|
`timescale 1 ns / 1 ps
/*******************************************************************************
* DescriPixtion: Compute pixel value based on context
* Latency: 800*1.5
******************************************************************************/
module lbp #(
parameter CTX_SIZE = 3,
parameter WIDTH = 12,
parameter LINE_LENGTH = 800
)(
input iClk,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
input iHSync,
input iVSync,
input iLineValid,
input iFrameValid,
output [7:0] oY,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*******************************************************************************
* Wiring
******************************************************************************/
wire [7:0] wGray;
wire wHSync;
wire wVSync;
wire wLineValid;
wire wFrameValid;
/*******************************************************************************
* Context wiring
******************************************************************************/
wire [11:0] wChain [CTX_SIZE-1:0][CTX_SIZE:0];
/*******************************************************************************
* Assignments
******************************************************************************/
assign wChain[0][0] = { wGray, wHSync, wVSync, wLineValid, wFrameValid};
assign oHSync = wChain[1][1][3];
assign oVSync = wChain[1][1][2];
assign oLineValid = wChain[1][1][1];
assign oFrameValid = wChain[1][1][0];
assign oY = { wChain[0][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[0][1][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[0][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[1][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][2][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][1][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[2][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1,
wChain[1][0][11:4] > wChain[1][1][11:4] ? 1'b0 : 1'b1 };
/*******************************************************************************
* Delays generator
******************************************************************************/
genvar i;
genvar j;
generate
for(i = 0; i < CTX_SIZE; i = i + 1)
begin : ctx_delay_inst
for(j = 0; j < (CTX_SIZE - 1); j = j + 1)
begin : ctx_latches_inst
wlatch #(
.WIDTH(WIDTH)
) lth (
.ce(1),
.rst(0),
.clk(iClk),
.in( wChain[i][j]),
.out(wChain[i][j+1])
);
end
delayLine#(
.WIDTH(WIDTH),
.DELAY(LINE_LENGTH - CTX_SIZE + 1)
) ctxDelay (
.ce(1),
.rst(0),
.clk(iClk),
.in( wChain[i][CTX_SIZE-1]),
.out(wChain[i][CTX_SIZE])
);
if(i < (CTX_SIZE - 1)) assign wChain[i][CTX_SIZE] = wChain[i+1][0];
end
endgenerate
/*******************************************************************************
* Convert to grayscale
******************************************************************************/
rgb2gray u1 (
.iClk(iClk),
.iR(iR),
.iG(iG),
.iB(iB),
.iHSync(iHSync),
.iVSync(iVSync),
.iLineValid(iLineValid),
.iFrameValid(iFrameValid),
.oY(wGray),
.oHSync(wHSync),
.oVSync(wVSync),
.oLineValid(wLineValid),
.oFrameValid(wFrameValid)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { short n, before, after; cin >> n; string a; bool flag = false; for (short i = 0; i < n; i++) { cin >> a; cin >> before; cin >> after; if (after >= 2400 && before >= 2400 && after - before > 0) flag = true; } if (flag == true) cout << YES ; else cout << NO ; }
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const long long MOD = 998244353; struct node { int v; node *d, *r; }; node a[1050][1050]; long long n, m, q; void solve() { cin >> n >> m >> q; for (int i = (int)(1); i <= (int)(n); i += 1) { for (int j = (int)(1); j <= (int)(m); j += 1) { cin >> a[i][j].v; } } for (int i = (int)(0); i <= (int)(n); i += 1) { for (int j = (int)(0); j <= (int)(m); j += 1) { a[i][j].r = &a[i][j + 1]; a[i][j].d = &a[i + 1][j]; } } while (q--) { long long e, b, c, d, h, w; cin >> e >> b >> c >> d >> h >> w; node *x, *y, *j, *k; x = y = &a[0][0]; for (int i = (int)(1); i <= (int)(e - 1); i += 1) x = x->d; for (int i = (int)(1); i <= (int)(b - 1); i += 1) x = x->r; for (int i = (int)(1); i <= (int)(c - 1); i += 1) y = y->d; for (int i = (int)(1); i <= (int)(d - 1); i += 1) y = y->r; j = x, k = y; for (int i = (int)(1); i <= (int)(h); i += 1) { x = x->d, y = y->d; swap(x->r, y->r); } for (int i = (int)(1); i <= (int)(w); i += 1) { x = x->r, y = y->r; swap(x->d, y->d); } for (int i = (int)(1); i <= (int)(w); i += 1) { j = j->r, k = k->r; swap(j->d, k->d); } for (int i = (int)(1); i <= (int)(h); i += 1) { j = j->d, k = k->d; swap(j->r, k->r); } } node *x = &a[0][0]; for (int i = (int)(1); i <= (int)(n); i += 1) { x = x->d; node *y = x; for (int j = (int)(1); j <= (int)(m); j += 1) { y = y->r; cout << y->v << ; } cout << endl; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; long long red[210]; long long green[210]; long long blue[210]; long long dp[210][210][210]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int r, g, b; cin >> r >> g >> b; for (int i = 1; i <= r; i++) cin >> red[i]; for (int i = 1; i <= g; i++) cin >> green[i]; for (int i = 1; i <= b; i++) cin >> blue[i]; sort(red, red + r + 1); sort(green, green + g + 1); sort(blue, blue + b + 1); for (int i = 0; i <= r; i++) { for (int j = 0; j <= g; j++) { for (int k = 0; k <= b; k++) { if (i > 0 && j > 0) dp[i][j][k] = max(dp[i][j][k], dp[i - 1][j - 1][k] + red[i] * green[j]); if (j > 0 && k > 0) dp[i][j][k] = max(dp[i][j][k], dp[i][j - 1][k - 1] + green[j] * blue[k]); if (i > 0 && k > 0) dp[i][j][k] = max(dp[i][j][k], dp[i - 1][j][k - 1] + red[i] * blue[k]); } } } cout << dp[r][g][b] << n ; }
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// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for time related expressions.
module vhdl_time_test;
logic a, b;
time tout, tin;
vhdl_time dut(a, b, tout, tin);
always @(a)
begin
$display("a changed at %t", $realtime);
end
initial begin
tin = 100ns;
// Start the test
b = 1'b0;
b = 1'b1;
$display(tout);
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m, p, l, r, cnt[600000], lg[600000], sum[600000], pre[600000][30], f[600000], g[600000]; bool cov[600000 << 6]; char s[600000]; struct Hash { const long long B1 = 233, mod1 = 998244353, B2 = 377, mod2 = 1000000007; long long h1[600000], pw1[600000], h2[600000], pw2[600000]; Hash() { memset(h1, 0, sizeof h1); memset(h2, 0, sizeof h2); } void build() { pw1[0] = pw2[0] = 1; h1[0] = h2[0] = 0; for (int i = 1; i <= n; ++i) { pw1[i] = pw1[i - 1] * B1 % mod1; h1[i] = (h1[i - 1] * B1 + s[i]) % mod1; pw2[i] = pw2[i - 1] * B2 % mod2; h2[i] = (h2[i - 1] * B2 + s[i]) % mod2; } } long long qry(int l, int r) { long long t1 = (h1[r] - h1[l - 1] * pw1[r - l + 1] % mod1 + mod1) % mod1; long long t2 = (h2[r] - h2[l - 1] * pw2[r - l + 1] % mod2 + mod2) % mod2; return t1 << 31 | t2; } } H; struct SA { int sa[600000], sa2[600000], x[600000], y[600000], rk[600000], lcp[22][600000]; void resort(int m) { memset(cnt, 0, sizeof cnt); for (int i = 1; i <= n; ++i) ++cnt[y[i]]; for (int i = 1; i <= m; ++i) cnt[i] += cnt[i - 1]; for (int i = 1; i <= n; ++i) sa2[cnt[y[i]]--] = i; memset(cnt, 0, sizeof cnt); for (int i = 1; i <= n; ++i) ++cnt[x[i]]; for (int i = 1; i <= m; ++i) cnt[i] += cnt[i - 1]; for (int i = n; i; --i) sa[cnt[x[sa2[i]]]--] = sa2[i]; rk[sa[1]] = 1; for (int i = 2; i <= n; ++i) { int u = sa[i], v = sa[i - 1]; rk[u] = rk[v] + (!(x[u] == x[v] && y[u] == y[v])); } } void build() { for (int i = 1; i <= n; ++i) { x[i] = s[i] - a + 1; y[i] = 1; } for (int i = n + 1; i <= n * 2; ++i) rk[i] = 0; resort(26); for (int k = 1; k < n; k <<= 1) { for (int i = 1; i <= n; ++i) { x[i] = rk[i]; y[i] = rk[i + k]; } resort(n); } for (int i = 1, j, h = 0; i <= n; lcp[0][rk[i++]] = h) for (h ? --h : h, j = sa[rk[i] - 1]; j && s[i + h] == s[j + h]; ++h) ; for (int i = 1; i <= 20; ++i) for (int j = 1; j + (1 << i) - 1 <= n; ++j) lcp[i][j] = min(lcp[i - 1][j], lcp[i - 1][j + (1 << (i - 1))]); } int qry(int x, int y) { x = rk[x]; y = rk[y]; if (x > y) swap(x, y); ++x; int l = lg[y - x + 1]; return min(lcp[l][x], lcp[l][y - (1 << l) + 1]); } } sa0, sa1; namespace p0 { bool ask(int l, int r) { for (int i = 0; i < 26; ++i) if (pre[r][i] - pre[l - 1][i] > 1) return 0; return 1; } } // namespace p0 namespace p1 { bool check(int l, int r, int i) { return H.qry(l, r - i) == H.qry(l + i, r); } bool ask(int l, int r) { int len = r - l + 1; for (int i = 1; i * i <= len; ++i) if (len % i == 0) { if (i < len && check(l, r, i)) return 1; if (len / i < len && check(l, r, len / i)) return 1; } return 0; } } // namespace p1 namespace p2 { bool check_border(int l, int r) { int len = r - l + 1; for (int i = 1; i <= p && i < len; ++i) if (H.qry(l, l + i - 1) == H.qry(r - i + 1, r)) return 1; for (int i = 1, mn = n - l + 1; i <= p && sa0.rk[l] + i <= n; ++i) { int t = sa0.rk[l] + i, j = sa0.sa[t]; mn = min(mn, sa0.lcp[0][t]); if (j > l && j <= r && j + mn > r) return 1; } for (int i = 1, mn = n - l + 1; i <= p && sa0.rk[l] - i; ++i) { int t = sa0.rk[l] - i, j = sa0.sa[t]; mn = min(mn, sa0.lcp[0][t + 1]); if (j > l && j <= r && j + mn > r) return 1; } return 0; } bool ask(int l, int r) { if (f[l] <= r || g[r] >= l) return 1; return check_border(l, r); } } // namespace p2 namespace p3 { int seg[600000 << 1]; void build(int x, int l, int r) { if (l == r) { seg[x] = f[l]; return; } int mid = (l + r) >> 1; build((x << 1), l, mid); build((x << 1 | 1), mid + 1, r); seg[x] = min(seg[(x << 1)], seg[(x << 1 | 1)]); } int qmin(int x, int l, int r, int L, int R) { if (l >= L && r <= R) return seg[x]; int mid = (l + r) >> 1, ret = n + 1; if (L <= mid) ret = min(ret, qmin((x << 1), l, mid, L, R)); if (R > mid) ret = min(ret, qmin((x << 1 | 1), mid + 1, r, L, R)); return ret; } bool ask(int l, int r) { if (pre[r][s[l] - a ] - pre[l][s[l] - a ]) return 1; if (pre[r - 1][s[r] - a ] - pre[l - 1][s[r] - a ]) return 1; if (qmin(1, 1, n, l, r) <= r) return 1; return 0; } } // namespace p3 void getsqr() { for (int i = 1; i <= n; ++i) { f[i] = n + 1; g[i] = 0; } for (int i = 1, j = 0; i <= n; ++i) lg[i] = j += (1 << (j + 1)) <= i; for (int i = 1; i <= n; ++i) sum[i] = sum[i - 1] + n / i; for (int i = 1; i <= n; ++i) { int l = 0, r = 0; for (int j = i; j + i <= n; j += i) if (j > r) { l = sa1.qry(n - j + 1, n - (j + i) + 1), r = sa0.qry(j, j + i); l = j - l + 1; r = j + r - 1; if (r - l + 1 < i || cov[sum[i - 1] + j / i]) continue; for (int k = i * 2; l + k * 2 - 1 <= r + i; k += i) cov[sum[k - 1] + (l + k - 1) / k] = 1; for (int k = l; k <= r - i + 1; ++k) { f[k] = min(f[k], k + i * 2 - 1); g[k + i * 2 - 1] = max(g[k + i * 2 - 1], k); } } } p3::build(1, 1, n); } int main() { scanf( %d%s%d , &n, s + 1, &m); p = sqrt(n) + 10; H.build(); sa0.build(); reverse(s + 1, s + n + 1); sa1.build(); reverse(s + 1, s + n + 1); for (int i = 1; i <= n; ++i) for (int j = 0; j < 26; ++j) pre[i][j] = pre[i - 1][j] + (s[i] - a == j); getsqr(); while (m--) { scanf( %d%d , &l, &r); if (p0::ask(l, r)) puts( -1 ); else if (p1::ask(l, r)) puts( 1 ); else if (p2::ask(l, r)) puts( 2 ); else if (p3::ask(l, r)) puts( 3 ); else puts( 4 ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<vector<int>> x(m + 1, vector<int>(n + 1)); for (int i = 1; i <= n; i++) { int k; scanf( %d , &k); for (int j = 1; j <= m; j++) { x[j][i] = x[j][i - 1]; if (j == k) { x[j][i] += 1; } } } vector<int> y(m + 1); for (int i = 1; i <= m; i++) { scanf( %d , &y[i]); } for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { for (int k = 1; k <= m; k++) { if (x[k][j] - x[k][i - 1] != y[k]) { break; } if (k == m) { printf( YES n ); return 0; } } } } printf( NO n ); }
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#include <bits/stdc++.h> using namespace std; int charToDec(char c) { if ((c >= 0 ) && (c <= 9 )) return c - 0 ; if ((c >= A ) && (c <= Z )) return c - A + 10; } char decToChar(int c) { if ((c >= 0) && (c <= 9)) return c + 0 ; if ((c >= 10) && (c <= 26)) return c + A - 10; } long long hzToDec(string s, int a) { long long r = 0; for (int i = 0; i < s.length(); i++) { r *= a; r += charToDec(s[i]); } return r; } string decToHz(long long x, int a) { string s = ; while (x > 0) { s = decToChar(x % a) + s; x = x / a; } if (s == ) s = 0 ; return s; } string toRome(long long X) { string r[3100]; r[3000] = MMM ; r[2000] = MM ; r[1000] = M ; r[900] = CM ; r[800] = DCCC ; r[700] = DCC ; r[600] = DC ; r[500] = D ; r[400] = CD ; r[300] = CCC ; r[200] = CC ; r[100] = C ; r[90] = XC ; r[80] = LXXX ; r[70] = LXX ; r[60] = LX ; r[50] = L ; r[40] = XL ; r[30] = XXX ; r[20] = XX ; r[10] = X ; r[9] = IX ; r[8] = VIII ; r[7] = VII ; r[6] = VI ; r[5] = V ; r[4] = IV ; r[3] = III ; r[2] = II ; r[1] = I ; return r[X / 1000 * 1000] + r[(X % 1000) / 100 * 100] + r[(X % 100) / 10 * 10] + r[X % 10]; } int main() { int a, b; string bb, x; long long x10; cin >> a >> bb >> x; x10 = hzToDec(x, a); if (bb == R ) { cout << toRome(x10); } else cout << decToHz(x10, atoi(bb.c_str())); return 0; }
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`include "DC_define.v"
`include "logfunc.h"
`include "scmemc.vh"
module DC_1_tagcheck #(parameter Width = 15, Size =256, Forward=0, REQ_BITS=7)
//tag 10+counter 2+states 3 =15//29 bits virtual adress
(
input clk
,input reset
,input req_valid
,input write
,input ack_retry
,input [14:0] req_tag
,input[4:0] index
//Search Only for 10 bit tags
,output ack_valid
,output req_retry_to_1_tagcheck
,output [14:0] ack_data_to_1_tagcheck
//****************************************,output [2:0] ack_req_to_L2 //3 bit ack req to L2
,output miss
,output hit
,output[2:0] way
,input coretodc_ld_valid
,output coretodc_ld_retry
,input [4:0] coretodc_ld_req
//---------------------------
// 7 bit store Req,atomic,checkpoint
,input coretodc_std_valid
,output coretodc_std_retry
,input [6:0] coretodc_std
//3 bit DC->L2 Req
,output l1tol2_req_valid
,input l1tol2_req_retry
,output [2:0] l1tol2_req
//5 bit L2 -> DC ACK
,input l2tol1_snack_valid
,input [4:0] l2tol1_snack
// 3 bit Displacement
,output l1tol2_disp_valid
,output [2:0] l1tol2_disp //command out displacement
);
logic[2:0] state_line;
logic [7:0] req_pos,req_pos_in_tag;
reg [1:0] counter,counter_;
//,counter_RRIP;
logic [9:0] req_tag_search;
logic [4:0] set_index;
logic write_1_tagcheck;
logic [14:0] req_data_1_tagbank=req_tag;//req tag = 10 bit tag
assign set_index=index;
assign counter=req_tag[11:10];
assign req_tag_search=req_tag[9:0];
assign req_pos = (set_index*8);
assign write_1_tagcheck=write;
always@(req_tag_search)
begin// all works at time=0 counter-- for RRIP
write_1_tagcheck=1'b1;
counter_=counter-1'b1;
req_data_1_tagbank[11:10]=counter_;
end
DC_1_tagbank
#(.Width(Width), .Size(Size))
tagbank (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.write_1_tagbank (write_1_tagcheck)//we=0 for read
,.req_data (req_data_1_tagbank)
,.ack_retry (ack_retry)
,.req_pos_tag (req_pos_in_tag )//search the set index position
,.req_retry (req_retry_to_1_tagcheck)
,.ack_valid (ack_valid)
,.ack_data (ack_data_to_1_tagcheck)
,.coretodc_ld_valid (coretodc_ld_valid)
,.coretodc_ld_retry (coretodc_ld_retry)
,.coretodc_ld_req (coretodc_ld_req)
,.coretodc_std_valid (coretodc_std_valid)
,.coretodc_std_retry (coretodc_std_retry)
,.coretodc_std (coretodc_std)
,.l2tol1_snack_valid (l2tol1_snack_valid)
,.l2tol1_snack (l2tol1_snack)
,.l1tol2_disp_valid (l1tol2_disp_valid)
,.l1tol2_disp (l1tol2_disp)
,.state_cache(state_line)
);
logic [2:0] way_no;
logic [7:0] way_no_ext;//8 bits needed
//logic NO_TAG_PRESENT=0;
assign hit=1'b0;
assign miss=1'b1;//miss is auto select but if hit then miss=0
always @ (posedge clk) begin
if(reset) begin
way_no <= 0;
end else begin
if(way_no <= 7) begin
way_no <= way_no + 1;
end else begin
way_no <= 0;
end
end
end
assign way_no_ext={{5{1'b0}},way_no};
assign req_pos_in_tag = (req_pos+way_no_ext);
always_comb begin
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin
if(state_line!=`I) begin//what happens if cacheline is hit but in I state?
hit=1'b1;
miss=1'b0;
end
way = way_no;
end else begin//if (ack_data_to_1_tagcheck[9:0]!= req_tag_search)
hit=1'b0;
miss=1'b1;
end
end
/*
always@(req_tag_search or set_index) begin
//if(tag_sel_a_b)begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin
way=way_no;
if(state_line!=`I) begin//what happens if cacheline is hit but in I state?
hit=1'b1;
miss=1'b0;
end
end // req_tag_search
else begin//if (ack_data_to_1_tagcheck[9:0]!= req_tag_search)
hit=1'b0;
miss=1'b1;
end
end//for
end//always
*/
always_comb
begin
if (miss|l1tol2_req_retry)
begin
if(coretodc_ld_valid) begin l1tol2_req_valid=1;l1tol2_req=`SC_CMD_REQ_S; end
else if(coretodc_std_valid) begin l1tol2_req_valid=1;l1tol2_req=`SC_CMD_REQ_M; end
end//if miss
end//always_comb
/*
always_comb begin
if (l2tol1_snack_valid) begin
if((l2tol1_snack==`SC_SCMD_ACK_S)||(l2tol1_snack==`SC_SCMD_ACK_M)||(l2tol1_snack==`SC_SCMD_ACK_S)) begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if (ack_data_to_1_tagcheck[9:0]== req_tag_search) begin //data comming from ram : ack_data_to_1_tagcheck
way=way_no;
if(state_line==`I) begin//what happens if cacheline in I state?
req_data_1_tagbank=req_tag;
write_1_tagcheck=1;//write enable to ram the req data in this tag way
end
end//]== req_tag_search
NO_TAG_PRESENT=1;
end //for
end
end
end*/
//if(state_line!=I) //no cache tag present
/*
always_comb begin
if (l2tol1_snack_valid && NO_TAG_PRESENT) begin
if((l2tol1_snack==`SC_SCMD_ACK_S)||(l2tol1_snack==`SC_SCMD_ACK_M)||(l2tol1_snack==`SC_SCMD_ACK_S))begin
for(way_no=0;way_no<=7;way_no++) begin
way_no_ext={{5{1'b0}},way_no};
req_pos_in_tag = (req_pos+way_no_ext);
if(ack_data_to_1_tagcheck[11:10]==3)begin
req_data_1_tagbank=req_tag;
write_1_tagcheck=1;//write enable to ram the req data in this tag way
end
else begin
counter_RRIP=counter+1;
//req_data_1_tagbank[=ack_data_to_1_tagcheck;// increase the RRIP counters
req_data_1_tagbank[11:10]=counter_RRIP;
write_1_tagcheck=1;
end
end//for
end //if (l2tol1_snack==`SC_SCMD_ACK_S)
end//if valid
end//always_comb
//end//sel
*/
endmodule
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#include <bits/stdc++.h> using namespace std; bool compare(const int &a, const int &b) { return a < b; } int main() { int n; cin >> n; int i = 0; double aux = 0; while (n >= aux) { aux = (1.0 / 6.0) * (i) * (i + 1) * (i + 2); i++; } cout << i - 2 << endl; return 0; }
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/*ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββ¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬βββββββββββ¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬ββββββ¬β¬β¬β¬β¬β¬β¬ββ¬β¬ββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββ¬β¬βββββββ¬β¬β¬β¬β¬β¬βββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬βββββββββββββββββββββββ ββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬ββββ¬β¬β¬β¬β¬β¬βββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬ββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬ββββββββββ¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬βββββββββ¬β¬β¬β¬β¬β¬β¬βββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββ¬β¬ββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββ¬β¬β¬β¬βββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬βββ¬ββ¬β¬βββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬βββ¬β¬β¬β¬β¬βββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββ¬βββββ¬β¬β¬βββββ¬β¬β¬β¬β¬β¬βββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬βββ¬ββββββ¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬βββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬βββββββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββ¬ββββ¬β¬β¬β¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬β¬βββββββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββββββββββββββ¬β¬β¬β¬β¬β¬ββββββββββββββββββββββββββββββββββ ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ */ /* ______ __ __ __ __ ________ _______ __ __ ______ ______ ______ ______ __ __ / | | / | | / / / / | | | ββββββ ββ | ββ ββ / ββ ββββββββ βββββββ | ββ | ββ ββββββ ββββββ ββββββ ββββββ ββ | ββ | ββ__| ββ ββ__| ββ βββ / βββ ββ__ | ββ | ββ | ββ__| ββ ββ__| ββ ββ___ ββ ββ___ ββ ββ__| ββ βββ | ββ | ββ ββ ββ ββ ββββ ββββ ββ | ββ | ββ | ββ ββ ββ ββ ββ ββ | ββ ββ ββββ ββ | ββββββββ ββββββββ ββ ββ ββ ββ βββββ | ββ | ββ | ββββββββ ββββββββ_ ββββββ _ ββββββ ββββββββ ββ ββ ββ | ββ | ββ ββ | ββ ββ βββ| ββ ββ_____| ββ__/ ββ | ββ | ββ ββ | ββ __| ββ __| ββ ββ | ββ ββ ββββ | ββ | ββ ββ | ββ ββ β | ββ ββ ββ ββ | ββ | ββ ββ | ββ ββ ββ ββ ββ ββ | ββ ββ βββ ββ ββ ββ ββ ββ ββ ββββββββ βββββββ ββ ββ ββ ββ ββββββ ββββββ ββ ββ ββ ββ */ /* __ __ __ __ __ ______ ______ _______ ______ __ | | | | / / | / | | ββ | ββ ______ ______ ____| ββ ββ_______ ______ _| ββ_ ______ | ββββββ ββββββ βββββββ ββββββ ββ _______ ______ | ββ__| ββ/ | / ββ / | ββ / | ββ__| ββ ββ ββ ββ__/ ββ ββ ββ | / | | ββ ββ ββββββ ββββββ βββββββ ββ βββββββ ββββββ ββββββ | ββββββ | ββ ββ ββ | ββ ββ ββ | ββ βββββββ ββββββ | ββββββββ ββ ββ/ ββ ββ | ββ ββ ββ | ββ ββ | ββ | ββ __| ββ | ββ | ββββββββ ββ __| βββββββ| ββ __ | ββ ββ / ββ | ββ | ββ ββββββββ βββββββ ββ__| ββ ββ ββ | ββ ββ__| ββ | ββ| ββ__/ ββ | ββ | ββ ββ__/ ββ | ββ__/ | ββ_ ββββββ βββββββ | ββ | ββ ββ ββ ββ ββ ββ ββ ββ | ββ ββ ββ ββ ββ ββ ββ | ββ | ββ ββ ββ ββ ββ ββ | ββ ββ ββ ββ ββ ββ βββββββ βββββββ βββββββ ββ ββ ββ_ βββββββ ββββ ββββββ ββ ββ ββββββ ββ ββββββ ββ βββββββ βββββββ | __| ββ ββ ββ ββββββ */ #include<bits/stdc++.h> #define ll long long #define ld long double #define f(i,n) for(ll i=0;i<(n);i++) #define f1(i,n) for(ll i=1;i<=n;i++) #define el n #define sq(a) (a)*(a) #define pb push_back #define asort(a,n) sort(a,a+n) #define dsort(a,n) sort(a,a+n,greater<>()) #define vasort(v) sort(v.begin(), v.end()); #define vdsort(v) sort(v.begin(), v.end(),greater<>()); #define cina(arr) f(i,n) cin >> arr[i]; #define YES cout << YES n #define Yes cout << Yes <<el #define yes cout << yes <<el #define NO cout << NO n #define No cout << No <<el #define no cout << no <<el #define covid19 ios_base::sync_with_stdio(false);cin.tie(0);cout.tie(0); #define TC int t; cin >> t; while(t--) const double pi=acos(-1); using namespace std; int main() { #ifndef ONLINE_JUDGE clock_t start = clock(); #endif covid19; TC { ll n; cin >> n; for (ll i = 0; i < 32; i++) { ll x = pow(2, i); if (x > n) { cout << x / 2 - 1; break; } } cout << el; } #ifndef ONLINE_JUDGE clock_t end = clock(); double time_taken = double(end - start) / double(CLOCKS_PER_SEC); cout << Time taken: << time_taken; cout << sec n ; #endif } /* NOTESSS decimal digit root :: d(n)=1+((nβ1)mod9) */
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#include <bits/stdc++.h> using namespace std; long long T, A, B, res; vector<long long> P; int main() { cin >> T >> A >> B; if (T == 1) { if (A == 1) { if (B == 1) { res = -1; } } else { if (B % A == 0) { ++res; } while (B > 0) { P.push_back(B % A); B /= A; } long long cp = 1; for (int i = 0; i < ((int)P.size()); i++) { A -= P[i] * cp; cp *= T; } if (A == 0) { ++res; } } } else { if (A < T) { if (B == A) { res = 1; } } else if (A == T) { if (B == A) { res = 2; } } else { if (A == B) { ++res; } while (B > 0) { P.push_back(B % A); B /= A; } long long cp = 1; for (int i = 0; i < ((int)P.size()); i++) { A -= P[i] * cp; cp *= T; } if (A == 0) { ++res; } } } if (res == -1) { cout << inf n ; } else { cout << res << n ; } return 0; }
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#include <bits/stdc++.h> int n; int a[(200010) << 1], b[(200010) << 1]; int pa[(200010) << 1], sa[(200010) << 1]; int pb[(200010) << 1], sb[(200010) << 1]; struct node { int x, y; } p[(200010)]; long long solve(int t) { memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); memset(pa, 0, sizeof(pa)); memset(pb, 0, sizeof(pb)); memset(sa, 0, sizeof(sa)); memset(sb, 0, sizeof(sb)); for (int i = 0; i < (200010) << 1; ++i) { b[i] = ((200010) << 1) - 1; } for (int i = 0; i < n; ++i) { if ((p[i].x & 1) ^ t) continue; a[p[i].x] = std::max(a[p[i].x], p[i].y); b[p[i].x] = std::min(b[p[i].x], p[i].y); } pb[0] = sb[((200010) << 1) - 1] = ((200010) << 1) - 1; for (int i = 1; i < (200010) << 1; ++i) { pa[i] = std::max(pa[i - 1], a[i]); pb[i] = std::min(pb[i - 1], b[i]); } for (int i = ((200010) << 1) - 2; ~i; --i) { sa[i] = std::max(sa[i + 1], a[i]); sb[i] = std::min(sb[i + 1], b[i]); } long long ret = 0; for (int i = 1 + t; i < ((200010) << 1) - 1; i += 2) { int l = std::min(pa[i - 1], sa[i + 1]); int r = std::max(pb[i - 1], sb[i + 1]); if (l <= r) { ret += (200010); continue; } if ((l ^ i) & 1) ++l; if ((r ^ i) & 1) --r; ret += ((((200010) << 1) - 1 - l) >> 1) + 1; ret += (r >> 1) + 1; } return ret; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); p[i] = {x + y + (200010), x - y + (200010)}; } long long ans = 1ll * ((200010) << 1) * (((200010) << 1) - 2) / 2 - solve(0) - solve(1); printf( %I64d n , ans); return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 16:24:58 05/12/2016
// Design Name:
// Module Name: keycode_to_ascii
// Project Name:
// Target Devices:
// Tool versions:
// Description: Circuito combinacional que decodifica el cΓ³digo de tecla a cΓ³digo ASCII
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module keycode_to_ascii
(
input wire [7:0] key_code,
output reg [7:0] ascii_code
);
always@*
begin
case(key_code)
8'h05: ascii_code = 8'h21;//F1(!) Reset del rtc
8'h06: ascii_code = 8'h22;//F2(")
8'h1c: ascii_code = 8'h41;//A Salida de configuracion sin configurar
8'h23: ascii_code = 8'h44;//D Apagar alarma del timer
8'h2b: ascii_code = 8'h46;//F entrar en configuracion fecha
8'h33: ascii_code = 8'h48;//H entra en configuracion hora
8'h3a: ascii_code = 8'h4d;//M
8'h2d: ascii_code = 8'h52;//R
8'h1b: ascii_code = 8'h53;//S cambiar formato hora
8'h2c: ascii_code = 8'h54;//T entra en configuracion timer
8'h72: ascii_code = 8'h35;//flecha abajo (5)
8'h6b: ascii_code = 8'h34;//flecha izquierda (4)
8'h74: ascii_code = 8'h36;//flecha derecha (6)
8'h75: ascii_code = 8'h38;//flecha arriba (8)
8'h5a: ascii_code = 8'h0d;//Enter
default ascii_code = 8'b0;//NULL char
endcase
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DFBBP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int UNDEF = -1; const long long INF = 1e18; template <typename T> inline bool chkmax(T &aa, T bb) { return aa < bb ? aa = bb, true : false; } template <typename T> inline bool chkmin(T &aa, T bb) { return aa > bb ? aa = bb, true : false; } int rint(); char rch(); long long rlong(); const int mv = 160; const int mc = ((mv * (mv - 1)) / 2) + 1; const int ma = 31; bitset<mc> f[mv][ma]; void reset() { for (int v = 0; v < mv; v++) for (int ai = 0; ai < ma; ai++) f[v][ai].reset(); } vector<int> solve(vector<int> &a) { vector<int> fail; sort(a.begin(), a.end()); int alim = a.size(); f[0][0][a[0]] = true; { int v = 0; int klim = (v * (v + 1)) / 2; if (f[(v)][alim - 1][klim]) { return vector<int>({a[0]}); } } for (int v = 1; v < mv; v++) { for (int sai = 0; sai < alim; sai++) { for (int dai = sai; dai <= min(alim - 1, sai + 1); dai++) { int shift = a[dai]; f[(v)][dai] |= (f[(v)-1][sai] << shift); } } int klim = (v * (v + 1)) / 2; if (f[(v)][alim - 1][klim]) { vector<int> final; int ai = alim - 1; int k = klim; for (int x = v; x >= 1; x--) { final.push_back(a[ai]); k -= a[ai]; if (f[x - 1][ai][k]) { ai = ai; } else { ai--; } } final.push_back(a[0]); sort(final.begin(), final.end()); return final; } bitset<mc> filt; filt.set(); filt >>= klim; filt <<= klim; for (int ai = 0; ai < alim; ai++) { f[(v)][ai] &= filt; } } return fail; } bool vans[mv + 2][mv + 2]; void recurse(vector<int> &r) { int n = r.size() - 1; if (n == 0) return; vector<int> R; R.push_back(-1); int sum = 0; for (int i = 1; i <= n; i++) { sum += r[i]; R.push_back(sum); } int s = n - 1 - r[n]; vector<int> F; F.resize(n + 1); for (int v = 1; v <= n; v++) F[v] = R[v] - (v * (v - 1)) / 2; int j = 1; vector<int> rp = r; for (int x = 1; x <= n; x++) vans[n][x] = 1; vans[n][n] = 0; vector<int> vj; vj.resize(s + 1); for (int d = 1; d <= s; d++) { int vmin = max(1, vj[d - 1] + 1); int ans = vmin; for (int v = n - 1; v >= vmin; v--) { if (F[v] < d) { ans = v + 1; break; } } vj[d] = ans; } for (int d = 1; d <= s; d++) { int j = vj[d]; assert(j <= n - 1); vans[n][j] = 0; vans[j][n] = 1; rp[j]--; } rp.resize(rp.size() - 1); recurse(rp); } vector<int> fgot; int comb(vector<int> &va) { auto got = solve(va); fgot = got; if (got.size() == 0) { printf( =( n ); return 0; } else { vector<int> r; r.push_back(-1); for (auto &w : got) r.push_back(w); recurse(r); int sz = got.size(); printf( %d n , sz); for (int x = 1; x <= sz; x++) { for (int y = 1; y <= sz; y++) { printf( %d , (int)vans[x][y]); } printf( n ); } return sz; } } void test() { reset(); memset(vans, 0, sizeof vans); vector<int> va; int p = (rand() % 100); for (int x = 0; x <= 30; x++) { if (rand() % 100 <= p) va.push_back(x); } if (va.size() == 0) va.push_back(rand() % 31); int got = comb(va); if (got != 0) { set<int> s; for (int x = 1; x <= got; x++) { assert(vans[x][x] == 0); int degout = 0; for (int y = 1; y <= got; y++) { degout += vans[x][y]; } s.insert(degout); } for (int x = 1; x <= got; x++) { for (int y = 1; y <= got; y++) { if (x == y) continue; assert(vans[x][y] + vans[y][x] == 1); } } set<int> sa; for (auto &w : va) sa.insert(w); if (s != sa) { for (auto &w : sa) printf( %d , w); printf( sa n ); for (auto &w : s) printf( %d , w); printf( s n ); for (auto &w : fgot) printf( %d , w); printf( fgot n ); exit(1); } } } void go() { for (int k = 0; k < 100000; k++) { srand(clock()); test(); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n = rint(); vector<int> va; va.reserve(n); for (int i = 0; i < n; i++) { int x = rint(); va.push_back(x); } comb(va); } static char stdinBuffer[1024]; static char *stdinDataEnd = stdinBuffer + sizeof(stdinBuffer); static const char *stdinPos = stdinDataEnd; void readAhead(size_t amount) { size_t remaining = stdinDataEnd - stdinPos; if (remaining < amount) { memmove(stdinBuffer, stdinPos, remaining); size_t sz = fread(stdinBuffer + remaining, 1, sizeof(stdinBuffer) - remaining, stdin); stdinPos = stdinBuffer; stdinDataEnd = stdinBuffer + remaining + sz; if (stdinDataEnd != stdinBuffer + sizeof(stdinBuffer)) *stdinDataEnd = 0; } } int rint() { readAhead(16); int x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; } char rch() { readAhead(16); while (*stdinPos == || *stdinPos == n ) ++stdinPos; char ans = *stdinPos; ++stdinPos; return ans; } long long rlong() { readAhead(32); long long x = 0; bool neg = false; while (*stdinPos == || *stdinPos == n ) ++stdinPos; if (*stdinPos == - ) { ++stdinPos; neg = true; } while (*stdinPos >= 0 && *stdinPos <= 9 ) { x *= 10; x += *stdinPos - 0 ; ++stdinPos; } return neg ? -x : x; }
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