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#include <bits/stdc++.h> using namespace std; long long s; int main() { int n, a, b, c, d; cin >> n >> a >> b >> c >> d; for (int x = 1; x <= n; x++) { int y = x + b - c; int z = x + a - d; int w = y + a - d; if (y <= n && z <= n && w <= n && y > 0 && z > 0 && w > 0) s++; } s *= n; cout << s; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long INFL = 1LL << 60; const int INF = 1 << 30; const long long MOD = 998244353; double EPS = 1e-10; vector<long long> dy = {0, 1, 0, -1, 1, 1, -1, -1, 0}; vector<long long> dx = {1, 0, -1, 0, 1, -1, 1, -1, 0}; void pres(double A) { printf( %.12lf n , A); } void BinarySay(long long x, long long y = 60) { for (int i = 0; i < (y); i++) cout << (x >> (y - 1 - i) & 1); cout << endl; } long long cnt_bit(long long x) { return __builtin_popcountll(x); } long long pow_long(long long x, long long k) { long long res = 1; while (k > 0) { if (k % 2) res *= x; x *= x; k /= 2; } return res; } long long pow_mod(long long x, long long k) { x %= MOD; long long res = 1; while (k > 0) { if (k % 2) { res *= x; res %= MOD; } x *= x; x %= MOD; k /= 2; } return res; } long long inverse(long long x) { return pow_mod(x, MOD - 2); }; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long x, long long y) { long long res = x / gcd(x, y); res *= y; return res; }; const int MAXcomb = 200010; long long fac[MAXcomb], finv[MAXcomb], inv[MAXcomb]; void COMinit() { fac[0] = fac[1] = 1; finv[0] = finv[1] = 1; inv[1] = 1; for (int i = 2; i < MAXcomb; i++) { fac[i] = fac[i - 1] * i % MOD; inv[i] = MOD - inv[MOD % i] * (MOD / i) % MOD; finv[i] = finv[i - 1] * inv[i] % MOD; } } long long comb(int n, int k) { if (n < k) return 0; if (n < 0 || k < 0) return 0; return fac[n] * finv[k] % MOD * finv[n - k] % MOD; } const int MAXkai = 200010; long long kai_memo[MAXkai]; long long kai(long long N) { if (kai_memo[N] != 0) return kai_memo[N]; if (N <= 1) return 1; return kai_memo[N] = N * kai(N - 1) % MOD; } long long disit(long long second, long long base = 10) { long long res = 0; while (second) { res++; second /= base; } return res; } vector<long long> divisor(long long n) { vector<long long> res(0); for (long long i = 1; i * i <= n; i++) { if (n % i == 0) { res.push_back(i); if (i != n / i) res.push_back(n / i); } } sort(res.begin(), res.end()); return res; } void solve() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < (n); i++) cin >> a[i]; sort(a.begin(), a.end()); long long sum = 0; for (int i = 0; i < (n); i++) sum += a[i]; int m; cin >> m; for (int i = 0; i < (m); i++) { int q; cin >> q; cout << sum - a[n - q] << endl; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); solve(); }
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//################ //# ------------ # //# NoName270805 # //# ------------ # //################ //#pragma GCC optimize( Ofast ) //#pragma GCC optimize( unroll-loops ) //#pragma GCC target( avx,avx2,fma ) //GNU G++17 7.3.0: No long long for faster code //GNU G++17 9.2.0 (64 bit, msys 2): Long long only for faster code #include<bits/stdc++.h> using namespace std; #define superfastboy ios_base::sync_with_stdio(false);cin.tie(0);cout.tie(0); #define tests int t;cin>>t;while(t--) #define pb push_back #define pf push_front #define fi first #define se second #define mp make_pair #define int long long #define ll long long #define ull unsigned long long typedef vector<int> vi; typedef pair<int,int> pii; ll const inf=1e15+7,mod=1e9+7,p=10; ll const N=270805; void solve(){ int n; cin>>n; int a[n+5],tmp=105; for(int i=0;i<n;i++){ cin>>a[i]; tmp=min(tmp,a[i]); } int ans=0; for(int i=0;i<n;i++){ if(tmp!=a[i])ans++; } cout<<ans<< n ; } signed main(){ // freopen( .inp , r ,stdin); // freopen( .out , w ,stdout); superfastboy tests solve(); }
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#include <bits/stdc++.h> using namespace std; int main() { int n, x; scanf( %d%d , &n, &x); if (n == 1) { printf( YES n ); printf( %d n , x); } else if (n == 2) { if (x == 0) printf( NO n ); else { printf( YES n ); printf( 0 %d n , x); } } else { printf( YES n ); int tmp = 0; int a = (1 << 17); int b = (1 << 18); for (int i = 0; i < n - 3; i++) { printf( %d , i); tmp ^= i; } printf( %d %d %d n , a, b, a ^ b ^ tmp ^ x); } return 0; }
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#include <bits/stdc++.h> using namespace std; map<long long, long long> mp; int main() { long long k, i; cin >> k; string s; cin >> s; long long ans = 0, cnt = 0; long long n = s.length(); mp[0] = 1; for (i = 0; i < n; i++) { if (s[i] == 1 ) { cnt++; } if (cnt >= k) { ans += mp[cnt - k]; } mp[cnt]++; } cout << ans; }
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/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 32456 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w512,
w511,
w4,
w507,
w4056,
w4057,
w32456;
assign w1 = i_data0;
assign w32456 = w4057 << 3;
assign w4 = w1 << 2;
assign w4056 = w507 << 3;
assign w4057 = w1 + w4056;
assign w507 = w511 - w4;
assign w511 = w512 - w1;
assign w512 = w1 << 9;
assign o_data0 = w32456;
//multiplier_block area estimate = 4833.25917057353;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
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#include <bits/stdc++.h> const int oo = 0x3f3f3f3f; const double PI = acos(-1.0); const double EPS = 1e-8; using namespace std; int read() { int d, f = 1; char c; while (!isdigit(c = getchar())) if (c == - ) f = -1; d = c ^ 0 ; while (isdigit(c = getchar())) d = (d * 10) + (c ^ 0 ); return d * f; } void rekt() { puts( YES ); exit(0); } int main() { int n; while (cin >> n) { int x0 = read(), y0 = read(); pair<long long, char> dir[8]; for (int i = 0; i < 8; ++i) dir[i].first = 1000000000000000000ll; for (int i = 0; i < n; ++i) { char c[2]; scanf( %s , c); int x = read(), y = read(); if (y == y0) { if (x < x0 && x0 - x < dir[0].first) dir[0].first = x0 - x, dir[0].second = c[0]; else if (x > x0 && x - x0 < dir[1].first) dir[1].first = x - x0, dir[1].second = c[0]; } else if (x == x0) { if (y < y0 && y0 - y < dir[2].first) dir[2].first = y0 - y, dir[2].second = c[0]; else if (y > y0 && y - y0 < dir[3].first) dir[3].first = y - y0, dir[3].second = c[0]; } else if (abs(x - x0) == abs(y - y0)) { if (x < x0 && y < y0 && x0 - x < dir[4].first) dir[4].first = x0 - x, dir[4].second = c[0]; else if (x > x0 && y < y0 && x - x0 < dir[5].first) dir[5].first = x - x0, dir[5].second = c[0]; else if (x < x0 && y > y0 && x0 - x < dir[6].first) dir[6].first = x0 - x, dir[6].second = c[0]; else if (x > x0 && y > y0 && x - x0 < dir[7].first) dir[7].first = x - x0, dir[7].second = c[0]; } } for (int i = 0; i < 4; ++i) if (dir[i].second == R || dir[i].second == Q ) rekt(); for (int i = 4; i < 8; ++i) if (dir[i].second == B || dir[i].second == Q ) rekt(); puts( NO ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxm = 1e6; int pre[maxm * 2 + 10]; bool a[maxm + 10]; int N; int main(int argc, const char* argv[]) { scanf( %d , &N); for (int i = 1; i <= N; i++) { int val; scanf( %d , &val); pre[val] = -1; a[val] = true; } int small = 0; int big = small; while (big <= maxm * 2) { while (big <= maxm * 2 && pre[big] != -1) { big++; } for (int i = small + 1; i <= big; i++) { pre[i] = small; } small = big; } int ans = 0; for (int i = 1; i <= maxm; i++) { if (!a[i]) continue; for (int j = i + i; j <= maxm * 2; j += i) { ans = max(ans, pre[j] % i); } } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; int sum[maxn], t, n, q, l, r; char s[maxn]; set<int> v[4 * maxn + 10]; int main() { scanf( %d , &t); while (t--) { sum[0] = 0; scanf( %d%d%s , &n, &q, (s + 1)); for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + (s[i] == + ? 1 : -1) * (i & 1 ? 1 : -1); v[sum[i - 1] + sum[i] + 2 * maxn].clear(); } for (int i = 1; i <= n; i++) v[sum[i - 1] + sum[i] + 2 * maxn].insert(i); while (q--) { scanf( %d%d , &l, &r); if (sum[r] == sum[l - 1]) printf( 0 n ); else { int k = r - l + 1; if (k % 2 == 0) printf( 2 n%d , l), l++; else printf( 1 n ); printf( %d n , *v[sum[r] + sum[l - 1] + 2 * maxn].lower_bound(l)); } } } return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:60777216 ) using namespace std; int err; vector<char> best; vector<char> curr; int n, r; int it; void go(int pos, int f1, int f2, int errors) { if (err <= errors) return; if (pos == -1) { err = errors; best = curr; } else { if (f1 == f2) { curr[pos] = T ; go(-1, 0, 0, errors + (pos + 1 < n && curr[pos + 1] == curr[pos])); } else if (f1 > f2) { curr[pos] = T ; go(pos - 1, f1 - f2, f2, errors + (pos + 1 < n && curr[pos + 1] == curr[pos])); } else { curr[pos] = B ; go(pos - 1, f1, f2 - f1, errors + (pos + 1 < n && curr[pos + 1] == curr[pos])); } } } int gcd(int a, int b) { while (a && b) if (a > b) a %= b; else b %= a; return a + b; } int ngcd(int a, int b) { int res = 0; while (a && b) if (a > b) res += a / b, a %= b; else res += b / a, b %= a; return res; } int main() { cin >> n >> r; vector<int> nm; for (int other = 1; other <= r; other++) { int g = gcd(other, r); if (g == 1) { int t = ngcd(other, r); if (t == n) { nm.push_back(other); } } } if (nm.size() == 0) puts( IMPOSSIBLE ); else { err = n + 1; curr.resize(n); for (int i = (0); i < (nm.size()); i++) { go(n - 1, r, nm[i], 0); go(n - 1, nm[i], r, 0); } cout << err << endl; for (int i = (0); i < (best.size()); i++) printf( %c , best[i]); puts( ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int q, n; cin >> q; while (q--) { cin >> n; vector<int> a(1 + n), answer(1 + n, 0); map<int, unordered_set<int> > m; vector<bool> vis(n + 1, false); for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 1; i <= n; ++i) { if (!vis[i]) { int j = i; vis[i] = true; while (a[j] != i) { m[i].insert(j); j = a[j]; vis[j] = true; } m[i].insert(j); } } for (auto p : m) { int temp = p.second.size(); answer[p.first] = temp; for (auto r : p.second) { answer[r] = temp; } } for (int i = 1; i <= n; ++i) cout << answer[i] << ; cout << n ; } return 0; }
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/*
* This module accepts incoming data from PS2 interface
* Copyright (C) 2010 Donna Polehn <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse_datain (
input clk,
input reset,
input wait_for_incoming_data,
input start_receiving_data,
input ps2_clk_posedge,
input ps2_clk_negedge,
input ps2_data,
output reg [7:0] received_data,
output reg received_data_en // If 1, new data has been received
);
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if (reset == 1'b1) s_ps2_receiver <= PS2_STATE_0_IDLE;
else s_ps2_receiver <= ns_ps2_receiver;
end
always @(*) begin // Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if((wait_for_incoming_data == 1'b1) && (received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) && (received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if (reset == 1'b1) data_count <= 3'h0;
else if((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if(s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) data_shift_reg <= 8'h00;
else if((s_ps2_receiver == PS2_STATE_2_DATA_IN) && (ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk) begin
if(reset == 1'b1) received_data <= 8'h00;
else if(s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk) begin
if(reset == 1'b1) received_data_en <= 1'b0;
else if((s_ps2_receiver == PS2_STATE_4_STOP_IN) && (ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m, c; int a[1005]; bool check() { bool good = a[0] > 0; for (int i = 1; i < n; i++) good &= (a[i] > 0) && (a[i] >= a[i - 1]); return good; } int main() { cin >> n >> m >> c; for (int i = 0; i < n; i++) a[i] = 0; while (m--) { if (check()) return 0; int p; cin >> p; if (p <= c / 2) { for (int i = 0; i < n; i++) { if (a[i] == 0) { a[i] = p; cout << i + 1; break; } if (a[i] > p) { a[i] = p; cout << i + 1; break; } } } else { for (int i = n - 1; i >= 0; i--) { if (a[i] == 0) { a[i] = p; cout << i + 1; break; } if (a[i] < p) { a[i] = p; cout << i + 1; break; } } } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mox = 1e6 + 9; long long ha[mox]; long long mod = 1e9 + 7; long long d[mox]; bool visit[mox]; long long ma[mox]; bool visit2[mox]; long long ta(long long a, long long b) { long long ans = 1; long long c = a; while (b) { if (b % 2) { ans = (ans * c) % mod; } c = (c * c) % mod; b /= 2; } return ans; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; string t; cin >> t; d[0] = 1; for (long long i = 0; i < t.size(); i++) { long long x = (d[i] * (t[i] - a + 1)) % mod; ha[i] = (ha[i - 1] + x) % mod; d[i + 1] = (d[i] * 27) % mod; } long long ans = 0; for (long long i = t.size() - 1; i >= 1; i--) { long long x = (ha[t.size() - 1] - ha[i - 1] + mod) % mod; long long y = ta(d[i], mod - 2); x = (x * y) % mod; if (x == ha[t.size() - 1 - i]) { visit[i] = 1; } } for (long long i = 0; i < m; i++) { cin >> ma[i]; visit2[ma[i]] = 1; } for (long long i = 1; i < m; i++) { if (ma[i] - ma[i - 1] < t.size()) { if (visit[ma[i] - ma[i - 1]] == 0) { cout << 0; exit(0); } } } long long x = 0; long long o = 0; for (long long i = 1; i <= n; i++) { if (visit2[i] == 1) { x = i + t.size() - 1; } if (i > x) { o += 1; } } long long w = 1; for (long long i = 0; i < o; i++) { w = (w * 26) % mod; } cout << w; }
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//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> bool chkmin(T &x, T y) { return x > y ? x = y, 1 : 0; } template <typename T> bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } int readint() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int cys = 1000000009; int n, m, tot; long long d[105][105], siz[105], tmp[105], ans[105], v[20005], nxt[20005], h[105], fac[105], inv[105], rt[105], f[105][105], rs[105]; bool vis[105]; long long mod(long long x) { return x >= cys ? x - cys : x; } long long qpow(long long x, long long p) { long long ret = 1; for (; p; p >>= 1, x = x * x % cys) if (p & 1) ret = ret * x % cys; return ret; } void addedge(int x, int y) { v[++tot] = y; nxt[tot] = h[x]; h[x] = tot; v[++tot] = x; nxt[tot] = h[y]; h[y] = tot; } void dfs(int u, int r) { memset(d[u], 0, sizeof(d[u])); d[u][0] = 1; siz[u] = 1; if (r) rt[u] = r; int cnt = 0; for (int p = h[u]; p; p = nxt[p]) { if (vis[v[p]]) { cnt++; continue; } vis[v[p]] = 1; dfs(v[p], r); for (int i = 0; i <= siz[u] + siz[v[p]]; i++) tmp[i] = 0; for (int i = 0; i < siz[u]; i++) for (int j = 0; j <= siz[v[p]]; j++) tmp[i + j] = mod(tmp[i + j] + d[u][i] * d[v[p]][j] % cys * fac[i + j] % cys * inv[i] % cys * inv[j] % cys); siz[u] += siz[v[p]]; for (int i = 0; i <= siz[u]; i++) d[u][i] = tmp[i]; } if (cnt <= 1) d[u][siz[u]] = d[u][siz[u] - 1]; if (u == r) rs[u] = siz[u]; } int main() { n = readint(); m = readint(); fac[0] = inv[0] = 1; for (int i = 1; i <= n; i++) fac[i] = fac[i - 1] * i % cys; inv[n] = qpow(fac[n], cys - 2); for (int i = n - 1; i >= 1; i--) inv[i] = inv[i + 1] * (i + 1) % cys; for (int i = 1; i <= m; i++) addedge(readint(), readint()); ans[0] = 1; for (int i = 1; i <= n; i++) { if (!vis[i]) { vis[i] = true; dfs(i, i); for (int j = 0; j <= n; j++) f[i][j] = d[i][j]; } else { for (int j = 1; j <= n; j++) if (rt[j] == rt[i]) vis[j] = 0; vis[i] = true; dfs(i, 0); for (int j = 0; j <= n; j++) f[rt[i]][j] = mod(f[rt[i]][j] + d[i][j]); } } for (int i = 1; i <= n; i++) { if (rt[i] == i) { for (int j = 0; j < rs[i]; j++) f[i][j] = f[i][j] * fac[rs[i] - j - 1] % cys * inv[rs[i] - j] % cys; for (int j = 0; j <= n; j++) tmp[j] = 0; for (int j = 0; j <= n; j++) for (int k = 0; k <= n; k++) tmp[j + k] = mod(tmp[j + k] + ans[j] * f[i][k] % cys * fac[j + k] % cys * inv[j] % cys * inv[k] % cys); for (int j = 0; j <= n; j++) ans[j] = tmp[j]; } } for (int i = 0; i <= n; i++) printf( %lld n , ans[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_0_V
`define SKY130_FD_SC_LP__A21O_0_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_0 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_0 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_0_V
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n, a, b, ans = 0; cin >> n >> a >> b; if (b >= 0) { if (b >= n) { ans = b % n; ans += a; } else ans = a + b; if (ans > n) ans %= n; } else if (n == -b) { ans = a; } else { if (b == -1) { a += b; if (a == 0) ans = n; else ans = a; } else { int k = 0; while (k != b) { a--; k--; if (a == 0) a = n; } if (a < 0) ans = -a; else ans = a; } } cout << ans << n ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_BEHAVIORAL_PP_V
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MN = 70; struct mat { long long T[MN][MN]; void O() { for (int i = 0; i < MN; i++) for (int j = 0; j < MN; j++) T[i][j] = 1e18; } }; mat mult(mat a, mat b) { mat ret; ret.O(); for (int i = 0; i < MN; i++) { for (int j = 0; j < MN; j++) { for (int k = 0; k < MN; k++) { ret.T[i][j] = min(ret.T[i][j], a.T[i][k] + b.T[k][j]); } } } return ret; } mat exp(mat x, int n) { mat ret; ret.O(); for (int i = 0; i < MN; i++) ret.T[i][i] = 0; while (n) { if (n & 1) ret = mult(ret, x); x = mult(x, x); n >>= 1; } return ret; } int X, K, N, Q; int C[10]; pair<int, int> W[30]; map<int, int> chk; vector<int> Mask; int inv[256]; mat P, Y, A; int main() { scanf( %d %d %d %d , &X, &K, &N, &Q); for (int i = 1; i <= K; i++) { scanf( %d , &C[i]); } for (int i = 0; i < Q; i++) { scanf( %d %d , &W[i].first, &W[i].second); W[i].first--; chk[W[i].first] = W[i].second; } sort(W, W + Q); for (int i = 0; i < (1 << K); i++) { int cnt = 0; for (int j = 0; j < K; j++) if (i & (1 << j)) cnt++; if (cnt == X) Mask.push_back(i); } for (int i = 0; i < Mask.size(); i++) inv[Mask[i]] = i; A.O(); A.T[0][0] = 0; P.O(); for (int i = 0; i < Mask.size(); i++) { int mask = Mask[i]; if (!(mask & 1)) { P.T[i][inv[mask >> 1]] = 0; continue; } for (int j = 1; j <= K; j++) { if (mask & (1 << j)) continue; int mask2 = mask ^ (1 << j); mask2 >>= 1; P.T[i][inv[mask2]] = C[j]; } } int cur_len = X; for (int q = Q - 1; q >= 0; q--) { int len = N - W[q].first; if (len > cur_len) { A = mult(exp(P, len - cur_len), A); cur_len = len; } while (cur_len < N - W[q].first + K && cur_len < N) { int p = N - cur_len - 1; Y.O(); for (int i = 0; i < Mask.size(); i++) { int mask = Mask[i]; if (!(mask & 1)) { Y.T[i][inv[mask >> 1]] = 0; continue; } for (int j = 1; j <= K; j++) { if (mask & (1 << j)) continue; int mask2 = mask ^ (1 << j); mask2 >>= 1; Y.T[i][inv[mask2]] = C[j] + (chk.find(p + j) != chk.end() ? chk[p + j] : 0); } } A = mult(Y, A); cur_len++; } } if (N > cur_len) { A = mult(exp(P, N - cur_len), A); } printf( %lld , A.T[inv[(1 << X) - 1]][0]); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 3e5 + 10; class SegmentTree { public: long long addv[N * 4]; int ql, qr, qx; void set(int l, int r, int x = 0) { ql = l, qr = r, qx = x; } void add(int l, int r, int o = 1) { if (ql <= l && r <= qr) { addv[o] += qx; return; } int mid = (l + r) >> 1; if (ql <= mid) add(l, mid, o << 1); if (mid < qr) add(mid + 1, r, o << 1 | 1); } long long query(int l, int r, int o = 1) { long long ret = addv[o]; if (l == r) { return ret; } int mid = (l + r) >> 1; if (ql <= mid) ret += query(l, mid, o << 1); if (mid < qr) ret += query(mid + 1, r, o << 1 | 1); return ret; } } st; vector<int> v[N]; vector<pair<int, int>> qr[N]; int depth[N]; int h = 0; long long ans[N]; void dfs(int x, int fa = 0) { depth[x] = depth[fa] + 1; h = max(h, depth[x]); for (auto &y : v[x]) { if (y == fa) continue; dfs(y, x); } } void solve(int x, int fa = 0) { int l = depth[x]; for (auto &p : qr[x]) { int r; int val; tie(r, val) = p; st.set(l, r, val); st.add(1, h); } st.set(l, l); ans[x] = st.query(1, h); for (auto &y : v[x]) { if (y == fa) continue; solve(y, x); } for (auto &p : qr[x]) { int r; int val; tie(r, val) = p; st.set(l, r, -val); st.add(1, h); } } int main() { int n; scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); v[x].push_back(y); v[y].push_back(x); } dfs(1); int q; scanf( %d , &q); while (q--) { int x, d, val; scanf( %d%d%d , &x, &d, &val); d = min(h, depth[x] + d); qr[x].push_back({d, val}); } solve(1); for (int i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tot, d[105]; int read() { int _ = 0, ___ = 1; char __ = getchar(); while (__ > 9 || __ < 0 ) { if (__ == - ) ___ = -1; __ = getchar(); } while (__ >= 0 && __ <= 9 ) { _ = _ * 10 + __ - 0 ; __ = getchar(); } return _ * ___; } int get(int x) { int sum = 0; while (x) { sum += x % 10; x /= 10; } return sum; } int main() { n = read(); for (int i = max(n - 81, 0); i <= n; i++) { int x = get(i); if (x + i == n) d[++tot] = i; } printf( %d n , tot); for (int i = 1; i <= tot; i++) printf( %d , d[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, q, s, cntlog2[2050] = {0}; int main() { scanf( %d , &q); while (q--) { memset(cntlog2, 0, sizeof(cntlog2)); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &s); if (s <= 2048) cntlog2[s]++; } for (int i = 1; i < 2048; i++) { while (cntlog2[i] >= 2) { cntlog2[i] -= 2; cntlog2[2 * i]++; } } if (cntlog2[2048]) { printf( YES n ); } else { printf( NO n ); } } return 0; }
|
`include "spi_master.v"
`include "milisecond_timer.v"
module oled_init (
input clk,
input reset,
input init_start,
output reg init_fin,
output spi_csn,
output spi_sdo,
output spi_sclk,
output spi_dcn, // active=command mode, inactive=data mode
output reg spi_resn,
output reg spi_vbatn,
output reg spi_vddn
);
assign spi_dcn = 1'b0; // always in cmd mode during init
`define INIT_SM_W 5
localparam DELAY_W = 12;
localparam DELAY_1MS = 1;
localparam DELAY_VBATON = 100;
localparam STATE_IDLE = `INIT_SM_W'h00;
localparam STATE_VDDON = `INIT_SM_W'h01;
localparam STATE_DISPOFF = `INIT_SM_W'h02;
localparam STATE_RESETON = `INIT_SM_W'h03;
localparam STATE_RESETOFF = `INIT_SM_W'h04;
localparam STATE_CHARGEPUMP1= `INIT_SM_W'h05;
localparam STATE_CHARGEPUMP2= `INIT_SM_W'h06;
localparam STATE_PRECHARGE1 = `INIT_SM_W'h07;
localparam STATE_PRECHARGE2 = `INIT_SM_W'h08;
localparam STATE_VBATON = `INIT_SM_W'h09;
localparam STATE_CONTRAST1 = `INIT_SM_W'h0A;
localparam STATE_CONTRAST2 = `INIT_SM_W'h0B;
localparam STATE_INVERT1 = `INIT_SM_W'h0C;
localparam STATE_INVERT2 = `INIT_SM_W'h0D;
localparam STATE_COMCONFIG1 = `INIT_SM_W'h0E;
localparam STATE_COMCONFIG2 = `INIT_SM_W'h0F;
localparam STATE_DISPLAYON = `INIT_SM_W'h10;
localparam STATE_DONE = `INIT_SM_W'h11;
reg [`INIT_SM_W-1:0] current_state;
reg [DELAY_W-1:0] delay_ms;
reg delay_start;
wire delay_fin;
reg [7:0] spi_data;
reg spi_start;
wire spi_fin;
always @(posedge clk or posedge reset) begin
if (reset) begin
init_fin <= 'b0;
spi_resn <= 'b1;
spi_vbatn <= 'b1;
spi_vddn <= 'b1;
current_state <= STATE_IDLE;
delay_start <= 'b0;
delay_ms <= 'b0;
spi_start <= 'b0;
spi_data <= 'b0;
end else begin
case (current_state)
STATE_IDLE: begin
if (init_start==1'b1) begin
current_state <= STATE_VDDON;
spi_vddn <= 1'b0;
delay_start <= 'b1;
delay_ms <= DELAY_1MS;
end
end
STATE_VDDON: begin
delay_start <= 'b0;
if (delay_fin == 1'b1) begin
current_state <= STATE_DISPOFF;
spi_data <= 8'hAE;
spi_start <= 'b1;
end
end
STATE_DISPOFF: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_RESETON;
spi_resn <= 'b0;
delay_start <= 'b1;
delay_ms <= DELAY_1MS;
end
end
STATE_RESETON: begin
delay_start <= 'b0;
if (delay_fin==1'b1) begin
current_state <= STATE_RESETOFF;
spi_resn <= 'b1;
delay_start <= 'b1;
delay_ms <= DELAY_1MS;
end
end
STATE_RESETOFF: begin
delay_start <= 'b0;
if (delay_fin==1'b1) begin
current_state <= STATE_CHARGEPUMP1;
spi_start <= 'b1;
spi_data <= 8'h8D;
end
end
STATE_CHARGEPUMP1: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_CHARGEPUMP2;
spi_start <= 'b1;
spi_data <= 8'h14;
end
end
STATE_CHARGEPUMP2: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_PRECHARGE1;
spi_start <= 'b1;
spi_data <= 8'hD9;
end
end
STATE_PRECHARGE1: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_PRECHARGE2;
spi_start <= 'b1;
spi_data <= 8'hF1;
end
end
STATE_PRECHARGE2: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_VBATON;
spi_vbatn <= 'b0;
delay_start <= 'b1;
delay_ms <= DELAY_VBATON;
end
end
STATE_VBATON: begin
delay_start <= 'b0;
if (delay_fin==1'b1) begin
current_state <= STATE_CONTRAST1;
spi_start <= 'b1;
spi_data <= 8'h81;
end
end
STATE_CONTRAST1: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_CONTRAST2;
spi_start <= 'b1;
spi_data <= 8'h0F;
end
end
STATE_CONTRAST2: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_INVERT1;
spi_start <= 'b1;
spi_data <= 8'hA1;
end
end
STATE_INVERT1: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_INVERT2;
spi_start <= 'b1;
spi_data <= 8'hC8;
end
end
STATE_INVERT2: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_COMCONFIG1;
spi_start <= 'b1;
spi_data <= 8'hDA;
end
end
STATE_COMCONFIG1: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_COMCONFIG2;
spi_start <= 'b1;
spi_data <= 8'h20;
end
end
STATE_COMCONFIG2: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_DISPLAYON;
spi_start <= 'b1;
spi_data <= 8'hAF;
end
end
STATE_DISPLAYON: begin
spi_start <= 'b0;
if (spi_fin==1'b1) begin
current_state <= STATE_DONE;
init_fin <= 1'b1;
end
end
STATE_DONE: begin
if (init_start==1'b0) begin
init_fin <= 'b0;
current_state <= STATE_IDLE;
end
end
endcase
end
end
spi_master i_spi_master (
.clk(clk),
.reset(reset),
.spi_start(spi_start),
.spi_data(spi_data),
.spi_fin(spi_fin),
.spi_csn(spi_csn),
.spi_sdo(spi_sdo),
.spi_sclk(spi_sclk)
);
milisecond_timer i_milisecond_timer(
.clk(clk),
.reset(reset),
.delay_start(delay_start),
.delay_ms(delay_ms),
.delay_fin(delay_fin)
);
endmodule
|
`timescale 1ns / 1ps
/*
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF530 (Terrible Fire 030 Accelerator).
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module tf530_ram(
input CLKCPU,
input RESET,
input A0,
input A1,
input [8:2] AB,
input [23:12] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
input IDEWAIT,
output INT2,
input AS20,
input RW20,
input DS20,
// cache and burst control
input CBREQ,
output CBACK,
output CIIN,
output STERM,
// 32 bit internal cycle.
// i.e. assert OVR
output INTCYCLE,
// spare / debug
output SPARE,
// ram chip control
output [3:0] RAMCS,
output RAMOE
);
reg AS20_D = 1'b1;
reg DS20_D = 1'b1;
reg STERM_D = 1'b1;
wire BUS_CYCLE = (~DS20_D | DS20);
reg configured = 'b0;
reg shutup = 'b0;
reg [7:0] data_out = 'h00;
reg [7:0] base = 'h40;
wire GAYLE_INT2;
wire [7:0] GAYLE_DOUT;
//
wire IDE_ACCESS = (A[23:15] != {8'hDA, 1'b0}) | DS20 | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | DS20 | AS20;
wire GAYLE_READ = (GAYLE_ACCESS | ~RW20);
gayle GAYLE(
.CLKCPU ( CLKCPU ),
.RESET ( RESET ),
.CS ( GAYLE_ACCESS ),
.DS ( DS20 ),
.RW ( RW20 ),
.A18 ( A[18] ),
.A ( {1,b0, A[13:12]}),
.IDE_INT( IDEINT ),
.INT2 ( GAYLE_INT2 ),
.DIN ( D ),
.DOUT ( GAYLE_DOUT )
);
// 0xE80000
wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | AS20 | DS20 | shutup | configured;
wire Z2_READ = (Z2_ACCESS | ~RW20);
wire Z2_WRITE = (Z2_ACCESS | RW20);
wire RAM_ACCESS = ({A[23:21]} != {base[7:5]}) | AS20 | DS20 | ~configured;
wire [6:0] zaddr = {AB[7:2],A1};
always @(posedge CLKCPU) begin
AS20_D <= AS20;
DS20_D <= DS20;
STERM_D <= INTCYCLE | ~STERM_D;
if (RESET == 1'b0) begin
configured <= 1'b0;
shutup <= 1'b0;
STERM_D <= 1'b1;
end else begin
if (Z2_WRITE === 1'b0) begin
case (zaddr)
'h24: begin
base[7:4] <= D[7:4];
configured <= 1'b1;
end
'h25: base[3:0] <= D[7:4];
'h26: shutup <= 1'b1;
endcase
end
data_out <= 8'hff;
// the Gayle/Gary ID shift register.
if (Z2_READ == 1'b0) begin
// zorro config ROM
case (zaddr)
'h00: data_out[7:4] <= 4'he;
'h01: data_out[7:4] <= 4'h6;
'h02: data_out[7:4] <= 4'h7;
'h03: data_out[7:4] <= 4'h7;
'h04: data_out[7:4] <= 4'h7;
'h08: data_out[7:4] <= 4'he;
'h09: data_out[7:4] <= 4'hc;
'h0a: data_out[7:4] <= 4'h2;
'h0b: data_out[7:4] <= 4'h7;
'h10: data_out[7:4] <= 4'hc;
'h12: data_out[7:4] <= 4'hc;
'h13: data_out[7:4] <= 4'h6;
endcase
end else if (GAYLE_READ == 1'b0) begin
data_out <= GAYLE_DOUT;
end
end
end
wire RAMCS3n = A1 | A0; //
wire RAMCS2n = (~SIZ[1] & SIZ[0] & ~A0) | A1;
wire RAMCS1n = (SIZ[1] & ~SIZ[0] & ~A1 & ~A0) | (~SIZ[1] & SIZ[0] & ~A1) |(A1 & A0);
wire RAMCS0n = (~SIZ[1] & SIZ[0] & ~A1 ) | (~SIZ[1] & SIZ[0] & ~A0 ) | (SIZ[1] & ~A1 & ~A0 ) | (SIZ[1] & ~SIZ[0] & ~A1 );
// disable all the RAM.
assign RAMOE = RAM_ACCESS;
assign RAMCS = {RAMCS3n | RAM_ACCESS, RAMCS2n | RAM_ACCESS, RAMCS1n | RAM_ACCESS , RAMCS0n | RAM_ACCESS};
assign INTCYCLE = RAM_ACCESS & GAYLE_ACCESS;
// disable all burst control.
assign STERM = STERM_D;
assign CBACK = 1'b1; //STERM_D | CBREQ;
// cache the sram.
assign CIIN = 1'b0; //~RAM_ACCESS;
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
assign D = Z2_READ & GAYLE_READ ? 8'bzzzzzzzz : data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long modulo(long long a, long long b) { long long c = a % b; return (c < 0) ? c + b : c; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; vector<long long> vec(n); for (auto &it : vec) cin >> it; sort(vec.begin(), vec.end()); int i; for (i = n - 1; i >= 0; i--) { if (vec[i] <= i + 1) { break; } } cout << i + 2 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2222; const long long INF = 1e9 + 19; const int ALF = 26; int n; string s[N]; vector<vector<int>> nextS[N]; int m; int id[N]; string t; pair<int, int> dp[N][N]; vector<vector<int>> nextT; pair<int, int> nextG[N][ALF]; void read() { cin >> n; for (int i = 0; i < n; i++) cin >> s[i]; scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &id[i]); id[i]--; } cin >> t; } void calcNext(string ss, vector<vector<int>> &a) { int nn = ss.size(); a.resize(nn + 1, vector<int>(ALF, INF)); for (int i = nn - 1; i >= 0; i--) { for (int j = 0; j < ALF; j++) a[i][j] = a[i + 1][j]; a[i][ss[i] - a ] = i; } } void upd(pair<int, int> &A, pair<int, int> B) { A = min(A, B); } int solve() { memset(dp, 63, sizeof(dp)); dp[0][0] = make_pair(0, 0); for (int i = 0; i < n; i++) nextS[i].clear(); nextT.clear(); calcNext(t, nextT); for (int i = 0; i < n; i++) { calcNext(s[i], nextS[i]); } memset(nextG, 63, sizeof(nextG)); for (int i = m - 1; i >= 0; i--) { for (int j = 0; j < ALF; j++) nextG[i][j] = nextG[i + 1][j]; for (int j = 0; j < ALF; j++) if (nextS[id[i]][0][j] != INF) nextG[i][j] = make_pair(i, nextS[id[i]][0][j]); } for (int i = 0; i < (int)t.size(); i++) { for (int j = 0; j <= i; j++) { if (dp[i][j].first < INF) { int x = dp[i][j].first; int y = dp[i][j].second; for (int ch = 0; ch < ALF; ch++) { if (nextT[i][ch] < INF) { pair<int, int> p2; if (nextS[id[x]][y][ch] < INF) { p2 = make_pair(x, nextS[id[x]][y][ch]); } else { p2 = nextG[x + 1][ch]; } if (p2.first < INF) { p2.second++; upd(dp[nextT[i][ch] + 1][j + 1], p2); } } } } } } int answer = 0; for (int pos = 0; pos <= (int)t.size(); pos++) for (int i = 0; i <= (int)t.size(); i++) if (dp[pos][i].first < INF) answer = max(i, answer); return answer; } int dp2[N][N]; void upd(int &A, int B) { A = max(A, B); } int stupid() { string tmp; for (int i = 0; i < m; i++) tmp += s[id[i]]; n = 1; s[0] = tmp; m = 1; id[0] = 0; dp2[0][0] = 0; for (int i = 0; i <= (int)s[0].size(); i++) for (int j = 0; j <= (int)t.size(); j++) { if (i == 0 && j == 0) continue; dp2[i][j] = -INF; if (i > 0) upd(dp2[i][j], dp2[i - 1][j]); if (j > 0) upd(dp2[i][j], dp2[i][j - 1]); if (i > 0 && j > 0 && s[0][i - 1] == t[j - 1]) upd(dp2[i][j], dp2[i - 1][j - 1] + 1); } return dp2[s[0].size()][t.size()]; } void printAns(int xx) { printf( %d n , xx); } void genTest() { int T = 6; n = rand() % T + 1; for (int i = 0; i < n; i++) { int len = rand() % T + 1; s[i] = ; for (int j = 0; j < len; j++) s[i] += a + rand() % T; } m = rand() % T + 1; for (int i = 0; i < m; i++) id[i] = rand() % n; int len = rand() % T + 1; t = ; for (int i = 0; i < len; i++) t += a + rand() % T; } void printTest() { cout << n << endl; for (int i = 0; i < n; i++) cout << s[i] << endl; cout << m << endl; for (int i = 0; i < m; i++) cout << id[i] + 1 << ; cout << endl; cout << t << endl; } void stress() { for (int tt = 0;; tt++) { cerr << tt << = << tt << endl; genTest(); auto r1 = solve(); auto r2 = stupid(); cerr << ( << r1 << , << r2 << ) = ( << r1 << , << r2 << ) n ; ; assert(r1 == r2); } } int main() { if (1) { read(); printAns(solve()); } else { stress(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 20; int c[MAX_N], d[MAX_N], num[MAX_N]; int dp[MAX_N][MAX_N * 100]; int n, m, c0, d0, a, b; int main() { while (scanf( %d%d%d%d , &n, &m, &c0, &d0) != EOF) { for (int i = 1; i <= m; i++) { scanf( %d%d , &a, &b); num[i] = a / b; scanf( %d%d , &c[i], &d[i]); } memset(dp, 0, sizeof dp); for (int i = 0; i <= n; i++) dp[0][i] = i / c0 * d0; for (int i = 1; i <= m; i++) for (int j = 0; j <= n; j++) for (int k = 0; k <= num[i]; k++) { if (j / c[i] < k) break; dp[i][j] = max(dp[i][j], dp[i - 1][j - c[i] * k] + d[i] * k); } int res = 0; for (int i = 0; i <= n; i++) res = max(res, dp[m][i]); printf( %d n , res); } return 0; }
|
/*
-- ============================================================================
-- FILE NAME : if_stage.v
-- DESCRIPTION : IFXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "cpu.h"
/********** W
[ **********/
module if_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** SPMC^tF[X **********/
input wire [`WordDataBus] spm_rd_data, // ÇÝoµf[^
output wire [`WordAddrBus] spm_addr, // AhX
output wire spm_as_, // AhXXg[u
output wire spm_rw, // ÇÝ^«
output wire [`WordDataBus] spm_wr_data, // «Ýf[^
/********** oXC^tF[X **********/
input wire [`WordDataBus] bus_rd_data, // ÇÝoµf[^
input wire bus_rdy_, // fB
input wire bus_grnt_, // oXOg
output wire bus_req_, // oXNGXg
output wire [`WordAddrBus] bus_addr, // AhX
output wire bus_as_, // AhXXg[u
output wire bus_rw, // ÇÝ^«
output wire [`WordDataBus] bus_wr_data, // «Ýf[^
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
input wire [`WordAddrBus] new_pc, // Vµ¢vOJE^
input wire br_taken, // ªò̬§
input wire [`WordAddrBus] br_addr, // ªòæAhX
output wire busy, // rW[M
/********** IF/IDpCvCWX^ **********/
output wire [`WordAddrBus] if_pc, // vOJE^
output wire [`WordDataBus] if_insn, // ½ß
output wire if_en // pCvCf[^ÌLø
);
/********** àÚ±M **********/
wire [`WordDataBus] insn; // tFb`µ½½ß
/********** oXC^tF[X **********/
bus_if bus_if (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
M
.busy (busy), // rW[M
/********** CPUC^tF[X **********/
.addr (if_pc), // AhX
.as_ (`ENABLE_), // AhXLø
.rw (`READ), // ÇÝ^«
.wr_data (`WORD_DATA_W'h0), // «Ýf[^
.rd_data (insn), // ÇÝoµf[^
/********** XNb`pbhC^tF[X **********/
.spm_rd_data (spm_rd_data), // ÇÝoµf[^
.spm_addr (spm_addr), // AhX
.spm_as_ (spm_as_), // AhXXg[u
.spm_rw (spm_rw), // ÇÝ^«
.spm_wr_data (spm_wr_data), // «Ýf[^
/********** oXC^tF[X **********/
.bus_rd_data (bus_rd_data), // ÇÝoµf[^
.bus_rdy_ (bus_rdy_), // fB
.bus_grnt_ (bus_grnt_), // oXOg
.bus_req_ (bus_req_), // oXNGXg
.bus_addr (bus_addr), // AhX
.bus_as_ (bus_as_), // AhXXg[u
.bus_rw (bus_rw), // ÇÝ^«
.bus_wr_data (bus_wr_data) // «Ýf[^
);
/********** IFXe[WpCvCWX^ **********/
if_reg if_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** tFb`f[^ **********/
.insn (insn), // tFb`µ½½ß
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
.new_pc (new_pc), // Vµ¢vOJE^
.br_taken (br_taken), // ªò̬§
.br_addr (br_addr), // ªòæAhX
/********** IF/IDpCvCWX^ **********/
.if_pc (if_pc), // vOJE^
.if_insn (if_insn), // ½ß
.if_en (if_en) // pCvCf[^ÌLø
);
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Generic Asynchronous FIFO //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module afifo
#(
parameter D_WIDTH = 32
)
(
input wr_clk,
input rd_clk,
input [D_WIDTH-1:0] i_data,
output [D_WIDTH-1:0] o_data,
input i_push,
input i_pop,
output o_full,
output o_empty
);
reg [2:0] wr_pointer = 'd0, rd_pointer = 'd0;
reg [2:0] wr_pointer_d1 = 'd0, rd_pointer_d1 = 'd0;
reg [2:0] wr_pointer_d2 = 'd0, rd_pointer_d2 = 'd0;
wire [2:0] wr_pointer_rd, rd_pointer_wr;
reg [D_WIDTH-1:0] data [3:0];
always @( posedge wr_clk )
if ( i_push && !o_full )
begin
wr_pointer <= wr_pointer + 1'd1;
data[wr_pointer[1:0]] <= i_data;
end
always @( posedge wr_clk )
begin
rd_pointer_d1 <= gray8(rd_pointer);
rd_pointer_d2 <= rd_pointer_d1;
end
always @( posedge rd_clk )
if ( i_pop && !o_empty )
rd_pointer <= rd_pointer + 1'd1;
always @( posedge rd_clk )
begin
wr_pointer_d1 <= gray8(wr_pointer);
wr_pointer_d2 <= wr_pointer_d1;
end
assign wr_pointer_rd = ungray8(wr_pointer_d2);
assign rd_pointer_wr = ungray8(rd_pointer_d2);
assign o_data = data[rd_pointer[1:0]];
assign o_full = {~wr_pointer[2], wr_pointer[1:0]} == rd_pointer_wr;
assign o_empty = wr_pointer_rd == rd_pointer;
function [2:0] gray8;
input [2:0] binary;
begin
case(binary)
3'b000 : gray8 = 3'b000;
3'b001 : gray8 = 3'b001;
3'b010 : gray8 = 3'b011;
3'b011 : gray8 = 3'b010;
3'b100 : gray8 = 3'b110;
3'b101 : gray8 = 3'b111;
3'b110 : gray8 = 3'b101;
3'b111 : gray8 = 3'b100;
endcase
end
endfunction
function [2:0] ungray8;
input [2:0] gray;
begin
case(gray)
3'b000 : ungray8 = 3'b000;
3'b001 : ungray8 = 3'b001;
3'b011 : ungray8 = 3'b010;
3'b010 : ungray8 = 3'b011;
3'b110 : ungray8 = 3'b100;
3'b111 : ungray8 = 3'b101;
3'b101 : ungray8 = 3'b110;
3'b100 : ungray8 = 3'b111;
endcase
end
endfunction
endmodule
|
#include <bits/stdc++.h> inline long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline void sub(long long &a, long long b) { a -= b; if (a < 0) a += 1000000007; } inline void add(long long &a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; } template <typename T> inline T const &MAX(T const &a, T const &b) { return a > b ? a : b; } template <typename T> inline T const &MIN(T const &a, T const &b) { return a < b ? a : b; } inline long long qp(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % 1000000007; a = a * a % 1000000007, b >>= 1; } return ans; } inline long long qp(long long a, long long b, long long c) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % c; a = a * a % c, b >>= 1; } return ans; } using namespace std; const unsigned long long ba = 233; const double eps = 1e-5; const long long INF = 0x3f3f3f3f3f3f3f3f; const int N = 1000 + 10, maxn = 1000000 + 10, inf = 0x3f3f3f3f; vector<long long> v; int main() { long long n; scanf( %lld , &n); if (n % 3 != 0) return 0 * puts( 0 ); n /= 3; for (long long i = 1; i * i <= n; i++) { if (n % i == 0) { v.push_back(i); if (i * i != n) v.push_back(n / i); } } sort(v.begin(), v.end()); int ans = 0; for (int i = 0; i < v.size() && v[i] * v[i] * v[i] <= n; i++) { for (int j = i; j < v.size() && v[i] * v[j] * v[j] <= n; j++) { long long x = v[i], y = v[j], z = n / v[i] / v[j], a, b, c; if (z < y || x * y * z != n) continue; if ((x - y + z) % 2 != 0) continue; b = (x - y + z) / 2; a = x - b; c = z - b; if (a > b || a > c || b > c || a <= 0 || b <= 0 || c <= 0) continue; set<int> s; s.insert(a), s.insert(b), s.insert(c); if (s.size() == 3) ans += 6; else if (s.size() == 2) ans += 3; else ans += 1; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> void pv(T a, T b) { for (T i = a; i != b; ++i) cout << *i << ; cout << endl; } template <class T> void chmin(T &t, T f) { if (t > f) t = f; } template <class T> void chmax(T &t, T f) { if (t < f) t = f; } int in() { int x; scanf( %d , &x); return x; } int N; long long T[10010], C[10010]; int main() { int i; for (; ~scanf( %d , &N);) { for (i = 0; i < N; ++i) { T[i] = in(); C[i] = in(); } long long ans = 0; long long t = 0; for (i = 0; i < N; ++i) { if (t <= T[i]) { chmax(ans, C[i]); t = T[i] + C[i]; } else { chmax(ans, (t - T[i]) + C[i]); t += C[i]; } } cout << t << << ans << endl; } return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: icblbc_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module icblbc_ram (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL icblbc_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct Boot { int _pos; char _char; }; struct PairBoots { Boot _left; Boot _right; }; int main() { int n; string leftBoots; string rightBoots; vector<vector<Boot>> leftBootsBucket(27); vector<vector<Boot>> rightBootsBucket(27); vector<PairBoots> ans; cin >> n; cin.ignore(); getline(cin, leftBoots); getline(cin, rightBoots); for (int i = 0; i < n; i++) { Boot leftBoot; leftBoot._pos = i; leftBoot._char = leftBoots[i]; if (leftBoot._char == ? ) leftBootsBucket[26].push_back(leftBoot); else leftBootsBucket[leftBoots[i] - a ].push_back(leftBoot); Boot rightBoot; rightBoot._pos = i; rightBoot._char = rightBoots[i]; if (rightBoot._char == ? ) rightBootsBucket[26].push_back(rightBoot); else rightBootsBucket[rightBoots[i] - a ].push_back(rightBoot); } for (int i = 0; i < 27; i++) { for (int j = 0; j < leftBootsBucket[i].size() || j < rightBootsBucket[i].size(); j++) { PairBoots temp; if (j < leftBootsBucket[i].size() && j < rightBootsBucket[i].size()) { temp._left = leftBootsBucket[i][j]; temp._right = rightBootsBucket[i][j]; } else { if (j < leftBootsBucket[i].size()) { if (rightBootsBucket[26].size() != 0) { temp._left = leftBootsBucket[i][j]; temp._right = rightBootsBucket[26][rightBootsBucket[26].size() - 1]; rightBootsBucket[26].pop_back(); goto here; } } if (j < rightBootsBucket[i].size()) { if (leftBootsBucket[26].size() != 0) { temp._left = leftBootsBucket[26][leftBootsBucket[26].size() - 1]; temp._right = rightBootsBucket[i][j]; leftBootsBucket[26].pop_back(); goto here; } } break; } here: ans.push_back(temp); } } cout << ans.size() << n ; for (auto i : ans) { cout << i._left._pos + 1 << << i._right._pos + 1 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_4_V
`define SKY130_FD_SC_HD__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_4_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 7; int a[N], n, q; long long sum[N << 2][11], mul[11] = {1}; long long SUM[11], LA[11]; int lazy[N << 2][11]; void pushup(int rt) { for (int i = 0; i < 10; ++i) { sum[rt][i] = sum[rt << 1][i] + sum[rt << 1 | 1][i]; } } void pushdown(int rt) { for (int i = 0; i < 10; ++i) SUM[i] = sum[rt << 1][i], LA[i] = lazy[rt << 1][i]; for (int i = 0; i < 10; ++i) { int u = i, v = lazy[rt][i]; if (u == v) continue; for (int j = 0; j < 10; ++j) { if (lazy[rt << 1][j] == u) { LA[j] = lazy[rt][i]; } } SUM[lazy[rt][i]] += sum[rt << 1][i]; SUM[i] -= sum[rt << 1][i]; } for (int i = 0; i < 10; ++i) sum[rt << 1][i] = SUM[i], lazy[rt << 1][i] = LA[i]; for (int i = 0; i < 10; ++i) SUM[i] = sum[rt << 1 | 1][i], LA[i] = lazy[rt << 1 | 1][i]; for (int i = 0; i < 10; ++i) { int u = i, v = lazy[rt][i]; if (u == v) continue; for (int j = 0; j < 10; ++j) { if (lazy[rt << 1 | 1][j] == u) { LA[j] = lazy[rt][i]; } } SUM[lazy[rt][i]] += sum[rt << 1 | 1][i]; SUM[i] -= sum[rt << 1 | 1][i]; } for (int i = 0; i < 10; ++i) sum[rt << 1 | 1][i] = SUM[i], lazy[rt << 1 | 1][i] = LA[i]; for (int i = 0; i < 10; ++i) lazy[rt][i] = i; } void build(int l, int r, int rt) { for (int i = 0; i < 10; ++i) lazy[rt][i] = i; if (l == r) { int x = a[l], index = 0; while (x) { int y = x % 10; x /= 10; sum[rt][y] += mul[index]; index++; } return; } int mid = (l + r) >> 1; build(l, mid, rt << 1); build(mid + 1, r, rt << 1 | 1); pushup(rt); } void update(int l, int r, int rt, int L, int R, int x, int y) { if (L <= l && r <= R) { for (int j = 0; j < 10; ++j) { if (lazy[rt][j] == x) { lazy[rt][j] = y; sum[rt][y] += sum[rt][x]; sum[rt][x] = 0; } } return; } pushdown(rt); int mid = (l + r) >> 1; if (L <= mid) update(l, mid, rt << 1, L, R, x, y); if (R > mid) update(mid + 1, r, rt << 1 | 1, L, R, x, y); pushup(rt); } long long query(int l, int r, int rt, int L, int R) { if (L <= l && r <= R) { long long ret = 0; for (int i = 0; i < 10; ++i) ret += sum[rt][i] * i; return ret; } pushdown(rt); int mid = (l + r) >> 1; long long ret = 0; if (L <= mid) ret += query(l, mid, rt << 1, L, R); if (R > mid) ret += query(mid + 1, r, rt << 1 | 1, L, R); return ret; } int main() { for (int i = 1; i < 11; ++i) mul[i] = mul[i - 1] * 10; scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } build(1, n, 1); while (q--) { int op, L, R, x, y; scanf( %d , &op); if (op == 1) { scanf( %d%d%d%d , &L, &R, &x, &y); if (x == y) continue; update(1, n, 1, L, R, x, y); } else { scanf( %d%d , &L, &R); printf( %lld n , query(1, n, 1, L, R)); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; double mas[10000][3]; void optim(int cnt, double Px, double Py, double Pz, double vs, double vp) { double l = 0, r = 0; double x1 = mas[cnt][0]; double y1 = mas[cnt][1]; double z1 = mas[cnt][2]; double x2 = mas[cnt + 1][0]; double y2 = mas[cnt + 1][1]; double z2 = mas[cnt + 1][2]; for (int i = 0; i < cnt; i++) { l += sqrt((mas[i][0] - mas[i + 1][0]) * (mas[i][0] - mas[i + 1][0]) + (mas[i][1] - mas[i + 1][1]) * (mas[i][1] - mas[i + 1][1]) + (mas[i][2] - mas[i + 1][2]) * (mas[i][2] - mas[i + 1][2])); r += sqrt((mas[i][0] - mas[i + 1][0]) * (mas[i][0] - mas[i + 1][0]) + (mas[i][1] - mas[i + 1][1]) * (mas[i][1] - mas[i + 1][1]) + (mas[i][2] - mas[i + 1][2]) * (mas[i][2] - mas[i + 1][2])); } int j = cnt; r += sqrt((mas[j][0] - mas[j + 1][0]) * (mas[j][0] - mas[j + 1][0]) + (mas[j][1] - mas[j + 1][1]) * (mas[j][1] - mas[j + 1][1]) + (mas[j][2] - mas[j + 1][2]) * (mas[j][2] - mas[j + 1][2])); l /= vs; r /= vs; while (r - l > 1E-12) { double m = (r + l) / 2; double xx = (x1 + x2) / 2, yy = (y1 + y2) / 2, zz = (z1 + z2) / 2; double dist2 = sqrt((xx - Px) * (xx - Px) + (yy - Py) * (yy - Py) + (zz - Pz) * (zz - Pz)); double t2 = dist2 / vp; if (t2 - m > 1E-10) { l = m; x1 = xx; y1 = yy; z1 = zz; } else if (t2 - m < -1E-10) { r = m; x2 = xx; y2 = yy; z2 = zz; } else { l = m; x1 = xx; y1 = yy; z1 = zz; break; } } printf( %.6lf n , l); printf( %.6lf %.6lf %.6lf n , x1, y1, z1); } int main() { int n; cin >> n; double vs, vp; for (int i = 0; i <= n; i++) cin >> mas[i][0] >> mas[i][1] >> mas[i][2]; cin >> vp >> vs; double Px, Py, Pz; cin >> Px >> Py >> Pz; bool f = false; int cnt = 0; double dist = 0; if (fabs(Px - mas[0][0]) < 1E-7 && fabs(Py - mas[0][1]) < 1E-7 && fabs(Pz - mas[0][2]) < 1E-7) { cout << YES << endl; printf( %.6lf n , 0.0); printf( %.6lf %.6lf %.6lf n , Px, Py, Pz); return 0; } for (int i = 0; i < n; i++) { dist += sqrt((mas[i][0] - mas[i + 1][0]) * (mas[i][0] - mas[i + 1][0]) + (mas[i][1] - mas[i + 1][1]) * (mas[i][1] - mas[i + 1][1]) + (mas[i][2] - mas[i + 1][2]) * (mas[i][2] - mas[i + 1][2])); double dist2 = sqrt((mas[i + 1][0] - Px) * (mas[i + 1][0] - Px) + (mas[i + 1][1] - Py) * (mas[i + 1][1] - Py) + (mas[i + 1][2] - Pz) * (mas[i + 1][2] - Pz)); double t1 = dist / vs; double t2 = dist2 / vp; if (t1 - t2 > -1E-14) { cnt = i; f = true; break; } } if (!f) { cout << NO ; return 0; } else cout << YES << endl; optim(cnt, Px, Py, Pz, vs, vp); return 0; }
|
//`include"DataPath.v"
//`include"Controller.v"
module CPU(input clk,rst);
wire[1:0] stackContrl,pcContrl;
wire[5:0] cntrlInstruc;
DataPath dp(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
Controller cntrl(clk,rst,RdOrR2,AluOrMem,RFWE,MWE,stackContrl,pcContrl,Zero,Cout,cntrlInstruc);
endmodule
module CPUTB();
initial begin
$dumpfile("CPUTB.vcd");
$dumpvars;
end
//integer outfile,regFile;
integer i,ramOut;
reg clk,rst;
parameter delta = 10;
initial begin clk = 0; forever #delta clk = ~clk; end
CPU UUT(clk,rst);
initial begin
ramOut = $fopen("ramModified.bin") | 1;
//regFile = $fopen("regsOut.bin") | 1;
rst=0;
#1 rst=1;
#(1+delta) rst=0;
for(i=0;i<500;i=i+1)
begin
//#(2*delta) $fdisplay(regFile, "%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d,%4d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7],UUT.dp.Alu.Zero);
#(2*delta) $display("%8d,%8d,%8d,%8d,%8d,%8d,%8d,%8d",UUT.dp.RF.registers[0],UUT.dp.RF.registers[1],UUT.dp.RF.registers[2],UUT.dp.RF.registers[3],UUT.dp.RF.registers[4],UUT.dp.RF.registers[5],UUT.dp.RF.registers[6],UUT.dp.RF.registers[7]);
end
for(i=0;i<256;i=i+1)
begin
$fdisplay(ramOut, "%8b", UUT.dp.Mem.data[i]);
end
$finish;
end
endmodule
|
(* src = "../../verilog/extadc.v:1", top = 1 *)
module ExtADC (
(* intersynth_port = "Reset_n_i", src = "../../verilog/extadc.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/extadc.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/extadc.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/extadc.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:11" *)
output SensorPower_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:13" *)
output SensorStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "Inputs_i", src = "../../verilog/extadc.v:15" *)
input SensorReady_i,
(* intersynth_conntype = "Bit", intersynth_port = "AdcDoConvert_o", src = "../../verilog/extadc.v:17" *)
output AdcStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "AdcConvComplete_i", src = "../../verilog/extadc.v:19" *)
input AdcDone_i,
(* intersynth_conntype = "Word", intersynth_port = "AdcValue_i", src = "../../verilog/extadc.v:21" *)
input[15:0] AdcValue_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/extadc.v:23" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/extadc.v:25" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/extadc.v:27" *)
input[15:0] Threshold_i
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$728.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$extract$\Counter_RV1_Timer$725.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$extract$\Counter_RV1_Timer$725.Overflow_s ;
(* src = "../../verilog/extadc.v:167" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/extadc.v:43" *)
wire StoreNewValue;
(* src = "../../verilog/extadc.v:41" *)
wire TimerEnable;
(* src = "../../verilog/extadc.v:39" *)
wire TimerOvfl;
(* src = "../../verilog/extadc.v:40" *)
wire TimerPreset;
wire FSM_1_Out7_s;
wire FSM_1_Out8_s;
wire FSM_1_Out9_s;
wire FSM_1_Out10_s;
wire FSM_1_Out11_s;
wire FSM_1_Out12_s;
wire FSM_1_Out13_s;
wire FSM_1_Out14_s;
wire FSM_1_CfgMode_s;
wire FSM_1_CfgClk_s;
wire FSM_1_CfgShift_s;
wire FSM_1_CfgDataIn_s;
wire FSM_1_CfgDataOut_s;
AbsDiff \$extract$\AbsDiff$726 (
.A_i(AdcValue_i),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$728.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$728.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$728.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$extract$\Counter_RV1_Timer$725.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$extract$\Counter_RV1_Timer$725.D_s ),
.Direction_i(1'b1),
.Enable_i(TimerEnable),
.Overflow_o(\$extract$\Counter_RV1_Timer$725.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(TimerOvfl)
);
WordRegister \$extract$\WordRegister$727 (
.Clk_i(Clk_i),
.D_i(AdcValue_i),
.Enable_i(StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
FSM FSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(AdcDone_i),
.In1_i(Enable_i),
.In2_i(SensorReady_i),
.In3_i(TimerOvfl),
.In4_i(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.In5_i(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s ),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(CpuIntr_o),
.Out1_o(SensorStart_o),
.Out2_o(StoreNewValue),
.Out3_o(AdcStart_o),
.Out4_o(SensorPower_o),
.Out5_o(TimerEnable),
.Out6_o(TimerPreset),
.Out7_o(FSM_1_Out7_s),
.Out8_o(FSM_1_Out8_s),
.Out9_o(FSM_1_Out9_s),
.Out10_o(FSM_1_Out10_s),
.Out11_o(FSM_1_Out11_s),
.Out12_o(FSM_1_Out12_s),
.Out13_o(FSM_1_Out13_s),
.Out14_o(FSM_1_Out14_s),
.CfgMode_i(FSM_1_CfgMode_s),
.CfgClk_i(FSM_1_CfgClk_s),
.CfgShift_i(FSM_1_CfgShift_s),
.CfgDataIn_i(FSM_1_CfgDataIn_s),
.CfgDataOut_o(FSM_1_CfgDataOut_s)
);
assign FSM_1_CfgMode_s = 1'b0;
assign FSM_1_CfgClk_s = 1'b0;
assign FSM_1_CfgShift_s = 1'b0;
assign FSM_1_CfgDataIn_s = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 5; long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; set<long long> s; bool f = 1; if (k == 1) { cout << YES << n ; continue; } for (long long i = 0; i < n; i++) { if (a[i] == 0) continue; long long temp = a[i]; while (temp > 0) { for (long long j = 0; j < 1e5; j++) { if (temp < power(k, j)) { temp -= power(k, j - 1); if (s.count(j - 1)) { f = 0; break; } else { s.insert(j - 1); } break; } } } if (f == 0 || temp != 0) { f = 0; break; } } cout << (f == 0 ? NO : YES ) << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog wrapper for dlygate4sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_1_V
|
module xxx_xxxxxx (input wire clk, input wire reset);
typedef enum reg [4:0] {IDLE, IIII, HHHHH,
AA_OP, AA_CMRD, AA_CMRD_WAIT, AA_RMW, AA_RMW_WAIT, AA_CMLLL, AA_CMLLL_WAIT, AA_NEXT,
BB_OP, BB_CMLLL, BB_CMLLL_WAIT, BB_NEXT,
CC_OP, CC_NEXT_OOOO,
DD_OP, DD_CMRD, DD_CMRD_WAIT, DD_ACCUM, DD_CMLLL, DD_CMLLL_WAIT,
EE_OP, EE_NEXT_OOOO,
FF_OP,
zxcvzxcv, cvbncvbn} xxxxxx_state_e;
xxxxxx_state_e current_state;
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= IDLE;
end
else begin
unique case (current_state)
IDLE : begin
qwerty <= '0;
if (~qqq_empty)
current_state <= HHHHH;
end
AA_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left < 4)
lll_wcnt <= jjjj_left[2:0];
else
lll_wcnt <= FOUR[2:0];
current_state <= AA_CMLLL_WAIT;
end
HHHHH : begin
qqq_opiuy <= 1'b1;
if (qqq_opiuy) begin
qqq_opiuy <= '0;
current_state <= IIII;
end
end
AA_OP : begin
if (aa_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
jjjj_left <= tgbyhn;
current_state <= AA_CMRD;
end
end
AA_CMRD : begin
uuuuu <= 1'b1;
current_state <= AA_CMRD_WAIT;
end
IIII : begin
qqq_opiuy <= '0;
if (err_iiii) begin
current_state <= zxcvzxcv;
end
else begin
unique0 case (opm_cur)
`XXXCP : current_state <= AA_OP;
`XXXZR : current_state <= BB_OP;
default : current_state <= zxcvzxcv;
endcase // unique0 case
end // else: !if(err_iiii)
end // case: IIII
AA_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (err_cmrd_par) begin
current_state <= zxcvzxcv;
end
else begin
if (err_cmrd_csel) begin
current_state <= zxcvzxcv;
end
else begin : assign_writecvbn
lllcvbn <= asdf ? ghjk : rdcvbn;
lll_par <= asdf ? cvbn : rd_par;
current_state <= AA_CMLLL;
end
end // else: !if(err_cmrd_par)
end // if (kjkjkjkjk)
end // case: AA_CMRD_WAIT
AA_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= AA_NEXT;
end
end
end // case: AA_CMLLL_WAIT
AA_NEXT : begin
if (qwerty) begin
qwerty <= '0;
unique case (opm_cur)
`XXXCP : current_state <= cvbncvbn;
`XXXSG : current_state <= CC_NEXT_OOOO;
default : current_state <= zxcvzxcv;
endcase // unique case
end // if (qwerty)
else begin
jjjj_left <= jjjj_left - 4;
current_state <= AA_CMRD;
end // else: !if(qwerty)
end // case: AA_NEXT
BB_OP : begin
if (bb_pgm_err) begin
current_state <= zxcvzxcv;
end
else begin
lllcvbn <= '0;
lll_par <= '0;
jjjj_left <= tgbyhn;
current_state <= BB_CMLLL;
end
end // case: BB_OP
BB_CMLLL : begin
lll_start <= 1'b1;
if (jjjj_left <= 4) begin
lll_wcnt <= jjjj_left[2:0];
qwerty <= 1'b1;
end
else begin
lll_wcnt <= FOUR[2:0];
end
current_state <= BB_CMLLL_WAIT;
end // case: BB_CMLLL
BB_CMLLL_WAIT : begin
lll_start <= '0;
if (lll_done) begin
if (alalala) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= BB_NEXT;
end
end
end // case: BB_CMLLL_WAIT
BB_NEXT : begin
if (qwerty) begin
qwerty <= '0;
current_state <= cvbncvbn;
end
else begin
jjjj_left <= jjjj_left - 4;
current_state <= BB_CMLLL;
end
end
CC_OP : begin
jjjj_left_oooo <= tgbyhn;
if (tgbyhn <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= tgbyhn;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // case: CC_OP
CC_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
rd_rrrr <= rd_rrrr + ttttt_cur;
lll_rrrr <= lll_rrrr + oooo_cur;
if (jjjj_left_oooo <= oooo_cur) begin
last_oooo <= 1'b1;
jjjj_left <= jjjj_left_oooo;
end
else begin
jjjj_left <= oooo_cur;
end
current_state <= AA_CMRD;
end // else: !if(last_oooo)
end // case: CC_NEXT_OOOO
DD_OP : begin
accumulate_sum <= '0;
jjjj_left <= tgbyhn;
current_state <= DD_CMRD;
end
DD_CMRD : begin
uuuuu <= 1'b1;
if (jjjj_left <= 4) begin
qwerty <= 1'b1;
end
current_state <= DD_CMRD_WAIT;
end
DD_CMRD_WAIT : begin
uuuuu <= '0;
if (kjkjkjkjk) begin
if (zazaz) begin
current_state <= zxcvzxcv;
end
else begin
current_state <= DD_ACCUM;
end
end
end // case: DD_CMRD_WAIT
DD_ACCUM : begin
if (qwerty) begin
current_state <= DD_CMLLL;
end
else begin
current_state <= DD_CMRD;
end
end
DD_CMLLL : begin
lll_start <= 1'b1;
current_state <= DD_CMLLL_WAIT;
end
DD_CMLLL_WAIT : begin
lll_start <= '0;
end
EE_OP : begin
jjjj_left_oooo <= tgbyhn;
current_state <= AA_CMRD;
end
EE_NEXT_OOOO : begin
if (last_oooo) begin
current_state <= cvbncvbn;
end
else begin
end
end
FF_OP : begin
asdf <= 1'b1;
current_state <= CC_OP;
end
zxcvzxcv : begin
current_state <= cvbncvbn;
end
cvbncvbn : begin
if (dci_cur) begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
else if (crq_ready) begin
crq_start <= 1'b1;
crqcvbn <= complcvbn;
crq_proc_id <= proc_id_cur;
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
end // case: cvbncvbn
default : begin
current_state <= IDLE;
cmd_proc_done <= 1'b1;
end
endcase // unique case
end // else: !if(reset)
end // always _ff
endmodule // xxx_xxxxxx
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; long long n, x; void printbin(long long a) { for (int i = 20; i >= 0; i--) { long long c = a & (1LL << i); cout << bool(c); } cout << n ; } int main() { cin >> n >> x; long long reversed = 0; reversed |= 1LL << 17; if (n == 1) { cout << YES n << x; return 0; } if (n == 2 && x == 0) { cout << NO n ; return 0; } if (n == 2) { cout << YES n << 0 << << x << n ; return 0; } cout << YES n ; long long value = 0; long long test = 0; for (int i = 1; i <= n - 3; i++) { cout << i << ; value ^= i; test ^= i; } reversed = x ^ value; reversed |= 1LL << 17; long long temp2 = 1LL << 17; if (reversed == 1LL << 17) { reversed |= 1LL << 18; long long temp = 1LL << 18; cout << reversed << << temp << << (temp ^ reversed) << n ; } else { cout << reversed << << temp2 << << 0 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, k; pair<long long, long long> a[100007]; int r[100007]; int c[100007]; int used[100007]; long long ans = -1; bool cmp1(int x, int y) { return (a[x].first < a[y].first); } bool cmp2(int x, int y) { return (a[x].second < a[y].second); } void input() { cin >> n >> k; int i; long long xx1, yy1, xx2, yy2; for (i = 1; i <= n; i++) { cin >> xx1 >> yy1 >> xx2 >> yy2; xx1 *= 2; yy1 *= 2; xx2 *= 2; yy2 *= 2; a[i].first = (xx1 + xx2) / 2; a[i].second = (yy1 + yy2) / 2; r[i] = c[i] = i; } } void solve() { sort(r + 1, r + n + 1, cmp1); sort(c + 1, c + n + 1, cmp2); int i, j; int mask; int lim = (2 << (2 * k)); vector<int> v; for (mask = 0; mask < lim; mask++) { int u = mask; v.clear(); for (j = 0; j < k; j++) { int ost = (u % 4); u /= 4; if (ost == 0) { for (i = 1; i <= n; i++) { if (used[r[i]] == 1) { continue; } used[r[i]] = 1; v.push_back(r[i]); break; } } else if (ost == 1) { for (i = n; i >= 1; i--) { if (used[r[i]] == 1) { continue; } used[r[i]] = 1; v.push_back(r[i]); break; } } else if (ost == 2) { for (i = 1; i <= n; i++) { if (used[c[i]] == 1) { continue; } used[c[i]] = 1; v.push_back(c[i]); break; } } else { for (i = n; i >= 1; i--) { if (used[c[i]] == 1) { continue; } used[c[i]] = 1; v.push_back(c[i]); break; } } } long long xx1, yy1, xx2, yy2; xx1 = xx2 = yy1 = yy2 = 0; for (i = 1; i <= n; i++) { if (used[r[i]] == 0) { xx1 = a[r[i]].first; break; } } for (i = n; i >= 1; i--) { if (used[r[i]] == 0) { xx2 = a[r[i]].first; break; } } for (i = 1; i <= n; i++) { if (used[c[i]] == 0) { yy1 = a[c[i]].second; break; } } for (i = n; i >= 1; i--) { if (used[c[i]] == 0) { yy2 = a[c[i]].second; break; } } if (xx1 == xx2) { if (k != n) { xx2++; } } if (yy1 == yy2) { if (k != n) { yy2++; } } long long s = (xx2 - xx1 + 1) / 2; s *= ((yy2 - yy1 + 1) / 2); if (ans == -1 || ans > s) { ans = s; } for (i = 0; i < k; i++) { used[v[i]] = 0; } } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); input(); solve(); return 0; }
|
// Seven-segment display controller
// Author: Ross MacArthur (https://github.com/rossmacarthur)
// Description:
// - Cycles through selecting each of the displays
// - Outputs the corresponding display value for each display
module SS_Control #(N = 4) (
input clk, // clock freq of about 750 Hz
input rst,
input [N*4-1:0] numbers, // list of 4 bit numbers to display
output [N-1:0] displays, // the displays (active low)
output [6:0] segments // abcdefg segments (active low)
);
reg [6:0] abcdefg [N-1:0];
reg [$clog2(N)+1:0] count;
assign displays = ~reset ? ~(1'b1 << count) : ~1'b0;
assign segments = abcdefg[count];
always @(posedge clk) count <= (count == N-1) ? 1'b0 : count + 1'b1;
generate
for (genvar i = 0; i < N; i = i+1) begin : decoder
always @(*) begin
case(numbers[i*4+3:i*4])
4'h0 : abcdefg[i] <= 7'h01;
4'h1 : abcdefg[i] <= 7'h4F;
4'h2 : abcdefg[i] <= 7'h12;
4'h3 : abcdefg[i] <= 7'h06;
4'h4 : abcdefg[i] <= 7'h4C;
4'h5 : abcdefg[i] <= 7'h24;
4'h6 : abcdefg[i] <= 7'h20;
4'h7 : abcdefg[i] <= 7'h0F;
4'h8 : abcdefg[i] <= 7'h00;
4'h9 : abcdefg[i] <= 7'h04;
4'hA : abcdefg[i] <= 7'h08;
4'hB : abcdefg[i] <= 7'h60;
4'hC : abcdefg[i] <= 7'h31;
4'hD : abcdefg[i] <= 7'h42;
4'hE : abcdefg[i] <= 7'h30;
4'hF : abcdefg[i] <= 7'h38;
endcase
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
// Copyright 2018 Julius Baxter
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_bidir_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through
) (
input wire a_clk,
input wire a_rst_n,
input wire a_winc,
input wire [DSIZE-1:0] a_wdata,
input wire a_rinc,
output wire [DSIZE-1:0] a_rdata,
output wire a_full,
output wire a_afull,
output wire a_empty,
output wire a_aempty,
input wire a_dir, // dir = 1: this side is writing, dir = 0: this side is reading
input wire b_clk,
input wire b_rst_n,
input wire b_winc,
input wire [DSIZE-1:0] b_wdata,
input wire b_rinc,
output wire [DSIZE-1:0] b_rdata,
output wire b_full,
output wire b_afull,
output wire b_empty,
output wire b_aempty,
input wire b_dir // dir = 1: this side is writing, dir = 0: this side is reading
);
wire [ASIZE-1:0] a_addr, b_addr;
wire [ASIZE-1:0] a_waddr, a_raddr, b_waddr, b_raddr;
wire [ ASIZE:0] a_wptr, b_rptr, a2b_wptr, b2a_rptr;
wire [ ASIZE:0] a_rptr, b_wptr, a2b_rptr, b2a_wptr;
assign a_addr = a_dir ? a_waddr : a_raddr;
assign b_addr = b_dir ? b_waddr : b_raddr;
//////////////////////////////////////////////////////////////////////////////
// A-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync b write pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_wptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_wptr),
.dest_ptr (b2a_wptr)
);
// Sync b read pointer to a domain
sync_ptr #(ASIZE)
sync_b2a_rptr
(
.dest_clk (a_clk),
.dest_rst_n (a_rst_n),
.src_ptr (b_rptr),
.dest_ptr (b2a_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (a is writing)
wptr_full #(ASIZE)
a_wptr_inst
(
.wclk (a_clk),
.wrst_n (a_rst_n),
.winc (a_winc),
.wq2_rptr (b2a_rptr),
.awfull (a_afull),
.wfull (a_full),
.waddr (a_waddr),
.wptr (a_wptr)
);
// dir == 1 read pointer on a side calculation
rptr_empty #(ASIZE)
a_rptr_inst
(
.rclk (a_clk),
.rrst_n (a_rst_n),
.rinc (a_rinc),
.rq2_wptr (b2a_wptr),
.arempty (a_aempty),
.rempty (a_empty),
.raddr (a_raddr),
.rptr (a_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// B-side logic
//////////////////////////////////////////////////////////////////////////////
// Sync a write pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_wptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_wptr),
.dest_ptr (a2b_wptr)
);
// Sync a read pointer to b domain
sync_ptr #(ASIZE)
sync_a2b_rptr
(
.dest_clk (b_clk),
.dest_rst_n (b_rst_n),
.src_ptr (a_rptr),
.dest_ptr (a2b_rptr)
);
// The module handling the write requests
// outputs valid when dir == 0 (b is writing)
wptr_full #(ASIZE)
b_wptr_inst
(
.wclk (b_clk),
.wrst_n (b_rst_n),
.winc (b_winc),
.wq2_rptr (a2b_rptr),
.awfull (b_afull),
.wfull (b_full),
.waddr (b_waddr),
.wptr (b_wptr)
);
// dir == 1 read pointer on b side calculation
rptr_empty #(ASIZE)
b_rptr_inst
(
.rclk (b_clk),
.rrst_n (b_rst_n),
.rinc (b_rinc),
.rq2_wptr (a2b_wptr),
.arempty (b_aempty),
.rempty (b_empty),
.raddr (b_raddr),
.rptr (b_rptr)
);
//////////////////////////////////////////////////////////////////////////////
// FIFO RAM
//////////////////////////////////////////////////////////////////////////////
fifomem_dp #(DSIZE, ASIZE, FALLTHROUGH)
fifomem_dp
(
.a_clk (a_clk),
.a_wdata (a_wdata),
.a_rdata (a_rdata),
.a_addr (a_addr),
.a_rinc (a_rinc & !a_dir),
.a_winc (a_winc & a_dir),
.b_clk (b_clk),
.b_wdata (b_wdata),
.b_rdata (b_rdata),
.b_addr (b_addr),
.b_rinc (b_rinc & !b_dir),
.b_winc (b_winc & b_dir)
);
endmodule
`resetall
|
// Based on US Patent # 4,486,739 (expired)
// Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code
// Author: Franaszek et al.
//
// https://patentimages.storage.googleapis.com/67/2d/ad/0258c2f0d807bf/US4486739.pdf
//
`include "bsg_defines.v"
module bsg_8b10b_decode_comb
( input [9:0] data_i
, input rd_i
, output logic [7:0] data_o
, output logic k_o
, output logic rd_o
, output logic data_err_o
, output logic rd_err_o
);
wire A = data_i[0];
wire B = data_i[1];
wire C = data_i[2];
wire D = data_i[3];
wire E = data_i[4];
wire I = data_i[5];
wire F = data_i[6];
wire G = data_i[7];
wire H = data_i[8];
wire J = data_i[9];
// Commonly found functions (some in patent, others are not)
wire AxorB = A ^ B;
wire AandB = A & B;
wire NAandNB = ~A & ~B;
wire CxorD = C ^ D;
wire CandD = C & D;
wire NCandND = ~C & ~D;
wire ExnorI = ~(E ^ I);
wire EandI = E & I;
wire NEandNI = ~E & ~I;
wire FxorG = F ^ G;
wire FandG = F & G;
wire NFandNG = ~F & ~G;
wire HxorJ = H ^ J;
wire HandJ = H & J;
wire NHandNJ = ~H & ~J;
// From FIG. 10
wire P22 = (AandB & NCandND) | (CandD & NAandNB) | (AxorB & CxorD);
wire P13 = (AxorB & NCandND) | (CxorD & NAandNB);
wire P31 = (AxorB & CandD) | (CxorD & AandB);
// From FIG. 11
wire N0 = P22 & A & C & ExnorI;
wire N1 = P22 & ~A & ~C & ExnorI;
wire N2 = P22 & B & C & ExnorI;
wire N3 = P22 & ~B & ~C & ExnorI;
wire N4 = NAandNB & NEandNI;
wire N5 = AandB & EandI;
wire N6 = P13 & D & EandI;
wire N7 = P13 & ~I;
wire N8 = P13 & ~E;
wire N9 = P31 & I;
wire N10 = CandD & EandI;
wire N11 = NCandND & NEandNI;
wire N12 = ~E & I & G & HandJ;
wire N13 = E & ~I & ~G & NHandNJ;
assign k_o = (N10 | N11) | (N12 & P13) | (N13 & P31);
// From FIG. 12
wire M0 = N1 | N8;
wire M1 = N5 | N11 | N9;
wire M2 = N9 | N2 | N6;
wire M3 = N0 | N8;
wire M4 = N8 | N11 | N4;
wire M5 = N1 | N7;
wire M6 = N6 | N3;
wire T0 = M6 | M0 | M1;
wire T1 = M1 | M3 | M2;
wire T2 = M2 | M0 | M4;
wire T3 = M1 | M3 | M6;
wire T4 = M5 | M4 | M6;
assign data_o[0] = A ^ T0;
assign data_o[1] = B ^ T1;
assign data_o[2] = C ^ T2;
assign data_o[3] = D ^ T3;
assign data_o[4] = E ^ T4;
// From FIG.13
wire N14 = G & HandJ;
wire N15 = HandJ & F;
wire N16 = FandG & J;
wire N17 = NFandNG & ~H;
wire N18 = NFandNG & HandJ;
wire N19 = ~F & NHandNJ;
wire N20 = NHandNJ & ~G;
wire N21 = ~HandJ & ~NHandNJ & N11;
wire M7 = N14 | N15 | N21;
wire M8 = N16 | N17 | N18;
wire M9 = N19 | N21 | N20;
wire M10 = N20 | N15 | N21;
wire T5 = M7 | M8;
wire T6 = M8 | M9;
wire T7 = M8 | M10;
assign data_o[5] = F ^ T5;
assign data_o[6] = G ^ T6;
assign data_o[7] = H ^ T7;
// Everything else is not found in the patent
wire rd6p = (P31 & ~NEandNI) | (P22 & EandI); // 5b/6b code disparity +2
wire rd6n = (P13 & ~EandI) | (P22 & NEandNI); // 5b/6b code disparity -2
wire rd4p = (FxorG & HandJ) | (HxorJ & FandG); // 3b/4b code disparity +2
wire rd4n = (FxorG & NHandNJ) | (HxorJ & NFandNG); // 3b/4b code disparity -2
assign rd_o = ~NHandNJ & (rd4p | HandJ | (((D | ~NEandNI) & ((rd_i & P31) |
((rd_i | ~P13) & EandI) | (((rd_i & P22) | P31) & ~(NEandNI)) |
(D & EandI))) & ((FandG & NHandNJ) | N18 | (FxorG & HxorJ))));
assign data_err_o = (NAandNB & NCandND) |
(AandB & CandD) |
(NFandNG & NHandNJ) |
(FandG & HandJ) |
(EandI & FandG & H) |
(NEandNI & N17) |
(E & ~I & N14) |
(~E & I & N20) |
(~P31 & N13) |
(~P13 & N12) |
(N7 & ~E) |
(N9 & E) |
(FandG & NHandNJ & rd6p) |
(N18 & rd6n) |
(N10 & N17) |
(N11 & FandG & H) |
(rd6p & rd4p) |
(rd6n & rd4n) |
(AandB & C & NEandNI & (NFandNG | rd4n)) |
(NAandNB & ~C & EandI & (FandG | rd4p)) |
(((EandI & N20) | (NEandNI & N14)) & ~(CandD & E) & ~(NCandND & ~E));
// Running disparity errors detection
assign rd_err_o = (rd6p & rd4p) | (rd6n & rd4n) | // Delta disparity check
(rd_i & rd6p) | (~rd_i & rd6n) | // Disparity check for 5b/6b code
(rd_i & ~rd6n & FandG) | (~rd_i & ~rd6p & NFandNG) | // Disparity check for 3b/4b code
(rd_i & ~rd6n & rd4p) | (~rd_i & ~rd6p & rd4n) | // Resulting disparity check
(rd_i & AandB & C) | (~rd_i & NAandNB & ~C); // Additional check for DX.Y = D7.?
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100, inf = 0x3f3f3f3f, mod = 1e9 + 7, M = 1e6 + 1000; const long long INF = 0x3f3f3f3f3f3f3f3f; long long sp(long long a, long long b, long long d) { if (!b) return 1; return b % 2 ? sp(a * a, b / 2, d) * a % d : sp(a * a, b / 2, d); } long long sp1(long long a, long long b) { if (!b) return 1; return b % 2 ? sp1(a * a, b / 2) * a : sp1(a * a, b / 2); } long long lowbit(long long x) { return x & (-x); } long long exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1; y = 0; return a; } else { long long d = exgcd(b, a % b, y, x); y -= (a / b) * x; return d; } } long long t, n; char str[N]; long long ck(char s) { long long l = 1, r = n, x = 0; while (l <= r) { if (str[l] == str[r]) { l++; r--; } else { if (str[l] == s) { l++; x++; } else if (str[r] == s) { r--; x++; } else { return -1; } } } return x; } int main() { cin >> t; while (t--) { scanf( %lld%s , &n, str + 1); long long ans = -1; for (int i = 0; i <= 25; i++) { char s = i + a ; long long x = ck(s); if (x == -1) continue; if (ans == -1 || ans > x) ans = x; } cout << ans << endl; } }
|
module wait_time_module (reset, work, clk, wait_time);
//counting the wait_time
input clk,work,reset;
output [11:0] wait_time;
reg [11:0] wait_time;
reg [5:0] i;
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
wait_time <= 0;
i <= 0;
end
else if (work == 0)
begin
//if(i >= 59)
if(i >= 4)
begin
wait_time <= wait_time +1;
i <= 0;
end
else i <= i+1;
end
end
/*always @ (posedge clk)
begin
if(!reset&!work)
begin
if(i >= 1)
//if(i >= 59)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else i <= i+1;
end
else
begin
wait_time <= 0;
i <= 0;
end
end*/
/*
assign rw = reset||work;
always @ (posedge clk or negedge rw)begin
if(!rw)begin
wait_time <= 0;
i <= 0;
end
else
begin
case({reset,work})
2'b00:begin
//if(i >= 59)
if(i >= 1)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else
i <= i+1;
end
default:
begin
wait_time <= 0;
i <= 0;
end
endcase
end
end
*/
/*
assign rw = reset||work;
always @ (posedge clk or posedge rw)
begin
if(rw)
begin
wait_time <= 0;
i <= 0;
end
else
begin
case({reset,work})
2'b00:begin
//if(i >= 59)
if(i >= 1)
begin
wait_time <= BCD_counter(wait_time);
i <= 0;
end
else i <= i+1;
end
default:
begin
wait_time <= 0;
i <= 0;
end
endcase
end
end*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int Tn; cin >> Tn; while (Tn--) { int n, x; cin >> n >> x; int mx = 0, flag = 0; while (n--) { int t; cin >> t; if (t == x) flag = 1; mx = max(mx, t); } if (!flag) printf( %d n , max((x - 1) / mx + 1, 2)); else printf( %d n , 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; const int MOD = 1e9 + 7; int m, d, L; int bit[2001]; long long dp[2001][2001]; void add(long long &x, long long y) { x = (x + y) % MOD; } long long DFS(int pos, int preyu, bool yes) { if (pos == L) return preyu == 0; if (!yes && dp[pos][preyu] != -1) return dp[pos][preyu]; long long ans = 0; int End = yes ? bit[pos] : 9; for (int i = 0; i <= End; i++) { if (pos % 2 == 0 && i == d) continue; if (pos % 2 == 1 && i != d) continue; add(ans, DFS(pos + 1, (preyu * 10 + i) % m, yes && i == End)); } if (!yes) dp[pos][preyu] = ans; return ans; } long long Count(string str) { int len = str.size(); int cnt = 0; for (int i = 0; i < len; i++) bit[i] = str[i] - 0 ; return DFS(0, 0, 1); } bool judge(string str) { int len = str.size(); int yu = 0; for (int i = 0; i < len; i++) { int v = str[i] - 0 ; yu = yu * 10 + v; yu %= m; if ((i + 1) & 1 && v == d) return false; if (i & 1 && v != d) return false; } return yu == 0; } int main() { memset(dp, (-1), sizeof(dp)); cin >> m >> d; string a, b; cin >> a >> b; L = a.size(); cout << (Count(b) - Count(a) + judge(a) + MOD) % MOD << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; string i_str(int n) { char buff[10]; sprintf(buff, %d , n); return string(buff); } int main() { int a, b; cin >> a >> b; if (a < b) { cout << b; return 0; } string sa, sb, t, r = , si = ; sb = i_str(b); for (int j = a + 1; j <= 1000000; j++) { r = ; si = i_str(j); int ni = si.length(); for (int i = 0; i < ni; i++) { if (si[i] == 4 ) r = r + si[i]; if (si[i] == 7 ) r = r + si[i]; }; if (r == sb) { cout << j; return 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, sum = 0; cin >> n >> m; vector<int> v; for (int i = 0; i < n; i++) { int ff; cin >> ff; v.push_back(ff); } for (int i = 0; i < m; i++) { int x; cin >> x; if (x == 1) { int l, k; cin >> l >> k; v[l - 1] = k - sum; } if (x == 2) { int y; cin >> y; { sum += y; } } if (x == 3) { int ans; cin >> ans; cout << v[ans - 1] + sum << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; while (cin >> n >> m) { int str[550][550], cnt[550], ans[550]; memset(str, 0, sizeof(str)); memset(cnt, 0, sizeof(cnt)); memset(ans, 0, sizeof(ans)); for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; str[u][v] = str[v][u] = 1; cnt[u]++; cnt[v]++; } for (int i = 1; i <= n; i++) if (cnt[i] == n - 1) ans[i] = 1; for (int i = 1; i <= n; i++) if (ans[i] == 0) for (int j = i + 1; j <= n; j++) if (str[i][j] == 0) ans[j] = 2; bool flag = 1; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if ((abs(ans[i] - ans[j]) == 2 && str[i][j]) || (abs(ans[i] - ans[j]) < 2 && !str[i][j])) { cout << No << endl; flag = false; break; } } if (!flag) break; } if (!flag) continue; cout << Yes << endl; for (int i = 1; i <= n; i++) printf( %c , ans[i] + a ); cout << endl; } return 0; }
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_2_V
`define SKY130_FD_SC_LS__EINVP_2_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_2 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_2 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR2B_FUNCTIONAL_PP_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Text mode CRT SM
// File : sm_txt_crt.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This state machine is used when in crt cycle is active
// and in text-mode. This machine generates svga_reg to
// the memory module and waits for the svga-ack and this
// procedure is repeated for 16 cycles and then waits for
// data-xfer for 16 cycles.
//
// This module state machine also generates dummy fifo
// reads of data, ie data[7-0], data[11]. This data
// along with scanline register data [5:0] and extension
// register data is used to generate crt address to read
// the memory from plane2 or plane3 of the memory and
// load into 3rd plane of fifo-bank depending on the
// paged font bit.
//
// If paged font bit is set then plane3 data of memory
// is loaded into the fifo else plane2 data of memory is
// loaded into the fifo.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module sm_txt_crt
(
input start_txt_sm,
input sync_c_crt_line_end,
input hreset_n,
input crt_gnt,
input svga_ack,
input mem_clk,
input text_mode,
input dum_ff_rd_cnt0,
input data_complete,
input [7:0] c_hde, // Number of text characters on a line
output tx_cnt_inc,
output txt_crt_svga_req,
output dum_ff_read,
output enrd_tx_addr,
output enrd_font_addr,
output extend_font_addr
);
//
// Define Varaibles
//
reg [2:0] tx_cnt_qout;
reg [3:0] current_state;
reg [3:0] next_state;
reg [5:0] char_count; // Keep track of how many characters req.
reg tc_s0, tc_s1;
reg tc_s1x, tc_s2;
reg tc_s2x, tc_s3;
reg tc_s3x, tc_s4;
reg tc_s5, tc_s5x;
reg tc_s6;
wire cpu_rd_reset;
wire txt_cnt_0;
wire cntx_inc;
wire char_done;
//
// Define state machine varibles
//
parameter txt_crt_state0 = 4'b0000,
txt_crt_state1x = 4'b0001,
txt_crt_state2 = 4'b0011,
txt_crt_state1 = 4'b0111,
txt_crt_state2x = 4'b0010,
txt_crt_state3 = 4'b1010,
txt_crt_state3x = 4'b1011,
txt_crt_state5 = 4'b1111,
txt_crt_state4 = 4'b1110,
txt_crt_state5x = 4'b1101,
txt_crt_state6 = 4'b1100;
// Keep track of the number of characters being read in. Once over the max
// We will no longer request until the next scanline
always @ (posedge mem_clk or negedge hreset_n)
if (!hreset_n) char_count <= 6'b0;
else if (sync_c_crt_line_end) char_count <= 6'b0;
else if (tc_s6 && data_complete) char_count <= char_count + 1;
// Need to add extra characters for panning (can pan up to 3)
assign char_done = {char_count, 3'b0} >= c_hde + 4;
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) current_state <= txt_crt_state0;
else if (sync_c_crt_line_end) current_state <= txt_crt_state0;
else current_state <= next_state;
end
always @* begin
tc_s0 = 1'b0;
tc_s1 = 1'b0;
tc_s1x = 1'b0;
tc_s2 = 1'b0;
tc_s2x = 1'b0;
tc_s3 = 1'b0;
tc_s3x = 1'b0;
tc_s4 = 1'b0;
tc_s5 = 1'b0;
tc_s5x = 1'b0;
tc_s6 = 1'b0;
case (current_state) // synopsys parallel_case full_case
txt_crt_state0: begin
tc_s0 = 1'b1;
if (crt_gnt & start_txt_sm & text_mode && ~char_done)
next_state = txt_crt_state1x;
else
next_state = txt_crt_state0;
end
txt_crt_state1x: begin
tc_s1x = 1'b1;
if (svga_ack)
next_state = txt_crt_state2;
else
next_state = txt_crt_state1x;
end
txt_crt_state2: begin
tc_s2 = 1'b1;
if (~txt_cnt_0)
next_state = txt_crt_state1;
else
next_state = txt_crt_state2x;
end
txt_crt_state1: begin
tc_s1 = 1'b1;
if (svga_ack)
next_state = txt_crt_state2;
else
next_state = txt_crt_state1;
end
txt_crt_state2x: begin
tc_s2x = 1'b1;
next_state = txt_crt_state3;
end
txt_crt_state3: begin
tc_s3 = 1'b1;
if (data_complete == 1)
next_state = txt_crt_state3x;
else
next_state = txt_crt_state3;
end
txt_crt_state3x: begin
tc_s3x = 1'b1;
next_state = txt_crt_state5;
end
txt_crt_state4: begin
tc_s4 = 1'b1;
next_state = txt_crt_state5;
end
txt_crt_state5: begin
tc_s5 = 1'b1;
if (~dum_ff_rd_cnt0 & svga_ack)
next_state = txt_crt_state4;
else if (dum_ff_rd_cnt0 & svga_ack)
next_state = txt_crt_state5x;
else
next_state = txt_crt_state5;
end
txt_crt_state5x: begin
tc_s5x = 1'b1;
next_state = txt_crt_state6;
end
txt_crt_state6: begin
tc_s6 = 1'b1;
if (data_complete)
next_state = txt_crt_state0;
else
next_state = txt_crt_state6;
end
endcase
end
assign dum_ff_read = (tc_s4 | tc_s5x);
assign enrd_tx_addr = (tc_s2 | tc_s2x);
assign txt_crt_svga_req = (tc_s1x |((tc_s1 | tc_s2) & ~txt_cnt_0) |
tc_s3x | (tc_s4 | tc_s5) );
assign enrd_font_addr = (tc_s4 | tc_s5x);
assign extend_font_addr = tc_s4 | tc_s5 | tc_s5x;
assign tx_cnt_inc = (svga_ack & (tc_s2 | tc_s1)) | tc_s2x;
assign cntx_inc = svga_ack & (tc_s1x | tc_s2 | tc_s1);
assign txt_cnt_0 = ~|tx_cnt_qout;
always @ (posedge mem_clk or negedge hreset_n) begin
if (~hreset_n) tx_cnt_qout <= 0;
else if (sync_c_crt_line_end) tx_cnt_qout <= 0;
else if (cntx_inc) tx_cnt_qout <= tx_cnt_qout + 1;
end
endmodule
|
module mmio_if (
clk_i_clk,
hps_ddr3_mem_a,
hps_ddr3_mem_ba,
hps_ddr3_mem_ck,
hps_ddr3_mem_ck_n,
hps_ddr3_mem_cke,
hps_ddr3_mem_cs_n,
hps_ddr3_mem_ras_n,
hps_ddr3_mem_cas_n,
hps_ddr3_mem_we_n,
hps_ddr3_mem_reset_n,
hps_ddr3_mem_dq,
hps_ddr3_mem_dqs,
hps_ddr3_mem_dqs_n,
hps_ddr3_mem_odt,
hps_ddr3_mem_dm,
hps_ddr3_oct_rzqin,
cpc_keys_keys,
uart_tx_o,
uart_rx_i,
uart_reset_o,
uart_clk_i_clk);
input clk_i_clk;
output [14:0] hps_ddr3_mem_a;
output [2:0] hps_ddr3_mem_ba;
output hps_ddr3_mem_ck;
output hps_ddr3_mem_ck_n;
output hps_ddr3_mem_cke;
output hps_ddr3_mem_cs_n;
output hps_ddr3_mem_ras_n;
output hps_ddr3_mem_cas_n;
output hps_ddr3_mem_we_n;
output hps_ddr3_mem_reset_n;
inout [31:0] hps_ddr3_mem_dq;
inout [3:0] hps_ddr3_mem_dqs;
inout [3:0] hps_ddr3_mem_dqs_n;
output hps_ddr3_mem_odt;
output [3:0] hps_ddr3_mem_dm;
input hps_ddr3_oct_rzqin;
output [79:0] cpc_keys_keys;
output uart_tx_o;
input uart_rx_i;
output uart_reset_o;
input uart_clk_i_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long c[105], x[105][105], dp[105][105][105]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m, k, i, j, l, p, ans = 10000000000000000; cin >> n >> m >> k; for (i = 1; i <= n; i++) cin >> c[i]; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) cin >> x[i][j]; for (i = 0; i <= 100; i++) for (j = 0; j <= 100; j++) for (l = 0; l <= 100; l++) dp[i][j][l] = 10000000000000000; if (c[1] == 0) { for (i = 1; i <= m; i++) dp[1][1][i] = x[1][i]; } else dp[1][1][c[1]] = 0; for (i = 2; i <= n; i++) { if (c[i] == 0) { for (p = 1; p <= k; p++) { for (j = 1; j <= m; j++) { for (l = 1; l <= m; l++) { if (j == l) { dp[i][p][l] = min(dp[i][p][l], dp[i - 1][p][j] + x[i][l]); } else { dp[i][p + 1][l] = min(dp[i][p + 1][l], dp[i - 1][p][j] + x[i][l]); } } } } } else { for (p = 1; p <= k; p++) { for (j = 1; j <= m; j++) { if (j == c[i]) { dp[i][p][c[i]] = min(dp[i][p][c[i]], dp[i - 1][p][j]); } else { dp[i][p + 1][c[i]] = min(dp[i][p + 1][c[i]], dp[i - 1][p][j]); } } } } } if (c[n] == 0) { for (i = 1; i <= m; i++) ans = min(ans, dp[n][k][i]); } else ans = dp[n][k][c[n]]; if (ans != 10000000000000000) cout << ans; else cout << -1; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1.0e-11; const double pi = acos(-1.0); int main() { string s; cin >> s; int n = s.size(); vector<int> points; for (long long i = 0; i < (int)(s).size(); i++) { if (s[i] == . ) { points.push_back(i); } } if (points.empty() || points.front() == 0 || points.front() > 8 || points.back() == n - 1 || n - 1 - points.back() > 3) { cout << NO n ; return 0; } vector<bool> sep((int)(s).size(), false); for (long long i = 1; i <= (int)(points).size() - 1; i++) { if (points[i] - points[i - 1] - 1 < 2 || points[i] - points[i - 1] - 1 > 11) { cout << NO n ; return 0; } int d = points[i] - points[i - 1] - 1; if (d > 8) { sep[points[i] - 8] = true; continue; } sep[points[i - 1] + 2] = true; } cout << YES n ; for (long long i = 0; i < (int)(s).size(); i++) { if (sep[i]) { cout << endl; } cout << s[i]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<long long> > g; vector<bool> used; void dfs(long long v, long long &h, long long &e) { used[v] = true; h++; e += g[v].size(); for (int i = 0; i < g[v].size(); ++i) { if (!used[g[v][i]]) dfs(g[v][i], h, e); } } int main() { long long n, m; cin >> n >> m; g.resize(n); used.resize(n); for (int i = 0; i < m; ++i) { long long u, v; cin >> u >> v; g[u - 1].push_back(v - 1); g[v - 1].push_back(u - 1); } for (int i = 0; i < n; ++i) { if (!used[i]) { long long h = 0, e = 0; dfs(i, h, e); if (h * (h - 1) != e) { cout << NO ; return 0; } } } cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { int a, b, c; cin >> a >> b >> c; if (c == 0) { if (a <= b) cout << 0 << endl; else cout << 1 << endl; continue; } else if (a + c <= b) { cout << 0 << endl; continue; } int res; if (a == b) { res = c / 2; if (c % 2 == 1) res++; } else if (a > b) { if (b + c < a) res = c + 1; else if (b + c == a) res = c; else { if ((b + c - a) % 2 == 1) res = (b + c - a) / 2 + 1 + a - b; else res = (b + c - a) / 2 + a - b; } } else { if ((a + c - b) % 2 == 1) res = (a + c - b) / 2 + 1; else res = (a + c - b) / 2; } cout << res << endl; } }
|
#include <bits/stdc++.h> using namespace std; int a[111111]; int b[111111]; int main() { int n, i, j; vector<pair<int, int> > v; scanf( %d , &n); a[0] = a[1] = 1; for (i = 2; i <= n; i++) { if (a[i] == 0) { for (j = i * 2; j <= n; j += i) a[j] = 1; } } for (i = n / 2; i > 0; i--) { if (a[i] == 0) { vector<int> w; for (j = i; j <= n; j += i) { if (b[j] == 0) w.push_back(j); } if (w.size() % 2 == 0) { for (j = 0; j < w.size(); j += 2) { v.push_back(make_pair(w[j], w[j + 1])); b[w[j]] = b[w[j + 1]] = 1; } } else { for (j = 0; j < w.size(); j++) { if (w[j] % 2 == 0) { swap(w[j], w.back()); break; } } for (j = 0; j < w.size() - 1; j += 2) { v.push_back(make_pair(w[j], w[j + 1])); b[w[j]] = b[w[j + 1]] = 1; } } } } printf( %d n , v.size()); for (i = 0; i < v.size(); i++) printf( %d %d n , v[i].first, v[i].second); return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,popcnt,abm,mmx,tune=native ) mt19937 rng(time(NULL)); const int inf = 1e9 + 100; const long long linf = 2e18; const long long maxn = 2e5 + 100; const int mod = 1e9 + 7; vector<int> g[maxn]; int c[maxn]; bool f = 1; void dfs(int v, int cl) { c[v] = cl; for (int i : g[v]) { if (c[i] == 0) dfs(i, cl == 1 ? 2 : 1); else if (c[i] == cl) f = 0; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; vector<pair<int, int> > ans(m); for (int i = 0; i < m; ++i) { cin >> ans[i].first >> ans[i].second; g[ans[i].first - 1].push_back(ans[i].second - 1); g[ans[i].second - 1].push_back(ans[i].first - 1); } for (int i = 0; i < n; ++i) if (!c[i]) dfs(i, 1); if (f) { cout << YES n ; for (auto i : ans) { if (c[i.first - 1] == 2) cout << 1; else cout << 0; } } else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, n, k, sum = 0; bool flag = false; set<long long> S; scanf( %I64d%I64d , &n, &k); for (i = 1; i <= sqrt(n); i++) { if (n % i == 0) { S.insert(i); S.insert(n / i); } } if (S.size() >= k) flag = true; if (flag) { set<long long>::iterator it; it = S.begin(); while (k--) { it++; } it--; cout << *it; } else cout << -1; return 0; }
|
`timescale 1ns / 1ps
/**
Register file:
* 2 asyncrhonous read ports
* 1 synchronous write port
*/
module regfile(
input wire clk, // clock to trigger write
input wire rst, // reset
input wire [4:0] raddr1, raddr2, waddr, // the registers numbers to read or write
input wire [31:0] wdata, // data to write
input wire w_en, // write enable
output wire [31:0] rdata1, rdata2 // the register values read
);
reg [31:0] rf [31:0]; // 32 registers each 32 bits long
assign rdata1 = rf [raddr1];
assign rdata2 = rf [raddr2];
integer ii;
initial
begin
for ( ii = 0; ii < 32; ii= ii + 1 )
rf[ii] = 0;
end
always @(posedge clk)
begin
if (rst)
rf[0] <= 0;
else
if(w_en)
rf [waddr] <= wdata;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5; const long long M = 1e4; const long long mod = 1e9 + 7; const long long inf = 1e9; long long read() { long long s = 0; register bool neg = 0; register char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) neg |= (c == - ); for (; c >= 0 && c <= 9 ; s = s * 10 + (c ^ 48), c = getchar()) ; s = (neg ? -s : s); return s; } long long a, s[N + 5], r[N + 5]; long double val[N + 5]; vector<long long> p[63], q[63]; bool cmp(long long p1, long long p2) { return val[p1] < val[p2]; } signed main() { a = read(); for (long long i = (1); i <= (a); ++i) { s[i] = read(); long long j = 0, x = s[i]; for (; x; ++j) if (x & (1ll << j)) { if ((x ^ (1ll << j))) q[j].push_back(i); x ^= (1ll << j); } --j; p[j].push_back(i); } long long L = 0; for (long long i = (61); i >= (0); --i) { if (!((long long)((p[i]).size()))) continue; if (((long long)((p[i]).size())) > ((long long)((q[i]).size())) + 1) { puts( No ); return 0; } sort(q[i].begin(), q[i].end(), cmp); r[p[i][0]] = L; val[p[i][0]] = val[L] - 1e18; L = p[i][0]; for (long long j = (1); j <= (((long long)((p[i]).size())) - 1); ++j) { long long k = p[i][j], t = q[i][j - 1]; val[k] = (val[t] + val[r[t]]) / 2; r[k] = r[t]; r[t] = k; } } puts( Yes ); for (long long i = L; i; i = r[i]) printf( %lld , s[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long a, b, c, i, l, j, x, s, y, ans; int main() { cin >> a >> b >> c >> l; s = 0; for (i = l + 1; i >= 1; i--) s += i * (i + 1) / 2; ans = 0; for (i = 0; i <= l; i++) { x = a + i; if (b > x || c > x) continue; y = min(l - i, x - b - c) + 1; if (y < 0) y = 0; ans += (1 + y) * y / 2; } for (i = 0; i <= l; i++) { x = b + i; if (a > x || c > x) continue; y = min(l - i, x - a - c) + 1; if (y < 0) y = 0; ans += (1 + y) * y / 2; } for (i = 0; i <= l; i++) { x = c + i; if (a > x || b > x) continue; y = min(l - i, x - a - b) + 1; if (y < 0) y = 0; ans += (1 + y) * y / 2; } cout << s - ans; return 0; }
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/uart/uart_baud_clk.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Generates a tick signal at OVERSAMPLE_RATE times the baud rate. Should be fed to the uart_rx
* and uart_tx blocks.
***************************************************************************************************/
module uart_baud_clk
#(
parameter SYS_CLK_FREQ = 50000000,
parameter BAUD = 19200,
parameter BAUD_CLK_OVERSAMPLE_RATE = 16
)
(
input wire clk,
input wire reset,
output wire baud_clk_tick
);
localparam [15:0] CLKS_PER_OVERSAMPLE_TICK = (SYS_CLK_FREQ / BAUD) / BAUD_CLK_OVERSAMPLE_RATE;
// Registers
reg [15:0] q_cnt;
wire [15:0] d_cnt;
always @(posedge clk, posedge reset)
begin
if (reset)
q_cnt <= 0;
else
q_cnt <= d_cnt;
end
assign d_cnt = (q_cnt == (CLKS_PER_OVERSAMPLE_TICK - 1)) ? 16'h0000 : (q_cnt + 16'h0001);
assign baud_clk_tick = (q_cnt == (CLKS_PER_OVERSAMPLE_TICK - 1)) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 100, mod = 998244353; int n, c[N], s[N]; int qpow(int x, int y) { int res = 1; while (y) { if (y & 1) res = 1ll * res * x % mod; x = 1ll * x * x % mod, y >>= 1; } return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &c[i]); sort(c + 1, c + n + 1), reverse(c + 1, c + n + 1); for (int i = 1; i <= n; ++i) s[i] = (s[i - 1] + c[i]) % mod; int iv = qpow(n, mod - 2); for (int i = 1; i <= n; ++i) { int ans = 0; for (int j = i + 1; j <= n; j += i) ans = (ans + 1ll * (s[min(n, j + i - 1)] - s[j - 1] + mod) * ((j - 1) / i) % mod) % mod; printf( %lld , 1ll * ans * iv % mod); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void amin(T& a, const T& b) { if (a > b) a = b; } template <class T> inline void amax(T& a, const T& b) { if (a < b) a = b; } template <class T> inline void rv(vector<T>& v, int n) { vector<T>(n).swap(v); for (int i = 0; i < (n); i++) cin >> v[i]; } inline void rv(int* v, int n) { for (int i = 0; i < (n); i++) scanf( %d , &v[i]); } inline void rv(long long* v, int n) { for (int i = 0; i < (n); i++) scanf( %lld , &v[i]); } inline vector<int> rvi(int n) { vector<int> v(n); for (int i = 0; i < (n); i++) scanf( %d , &v[i]); return v; } inline vector<long long> rvl(int n) { vector<long long> v(n); for (int i = 0; i < (n); i++) scanf( %lld , &v[i]); return v; } inline vector<string> rvs(int n) { vector<string> v(n); for (int i = 0; i < (n); i++) scanf( %s , &v[i]); return v; } template <class T> inline void readvv(vector<vector<T>>& v, int m, int n) { vector<vector<T>>(m).swap(v); for (int i = 0; i < (m); i++) readv(v[i], n); } inline void pvi(vector<int>& v) { for (int i = 0; i < (v.size()); i++) printf( %d , v[i]); printf( n ); } inline void pvl(vector<long long>& v) { for (int i = 0; i < (v.size()); i++) { printf( %lld , v[i]); } printf( n ); } inline void pvs(vector<string>& v) { for (int i = 0; i < (v.size()); i++) { printf( %s n , v[i].c_str()); } } int main() { long long n; long double s; cin >> n >> s; vector<vector<long long>> g(n); for (int i = 0; i < (n - 1); i++) { long long u, v; cin >> u >> v; g[u - 1].push_back(v - 1); g[v - 1].push_back(u - 1); } long double leaves = 0, two = 2; for (int i = 0; i < (n); i++) { if (g[i].size() == 1) leaves++; } cout << setprecision(20) << endl; cout << ((two * s) / leaves) << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BEHAVIORAL_V
|
module data_ram_wb #(
parameter addr_high = 32'h0000ffff,
parameter addr_low = 32'h00001000) (
// wishbone signals
input [31:0] dat_i,
output [31:0] dat_o,
input [31:0] adr_i,
input we_i,
input [3:0] sel_i,
input cyc_i,
input stb_i,
output reg ack_o,
input [2:0] cti_i,
// clock
input clk_i,
// async reset
input rst_i);
wire [31:0] wr_data;
// mux for data to ram
assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
ram #(.addr_high(addr_high),
.addr_low(addr_low),
.read_only(1'b0)) data_memory(
.data_i(wr_data),
.data_o(dat_o),
.addr_i(adr_i),
.wren_i(we_i & ack_o),
.clk_i(clk_i));
// ack_o
always @ (posedge clk_i or posedge rst_i) begin
if (rst_i)
ack_o <= 1'b0;
else if (!ack_o) begin
if (cyc_i & stb_i)
ack_o <= 1'b1;
end
else if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111))
ack_o <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e6; const int inf = (1ll << 31) - 1; int p[maxn], l[maxn]; int n; pair<pair<int, int>, int> e[maxn]; pair<int, int> st[maxn]; int sum[maxn], answer[maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &p[i], &l[i]); } int m; scanf( %d , &m); for (int i = 0; i < m; ++i) { int l, r; scanf( %d%d , &l, &r); l--; r--; e[i] = make_pair(make_pair(l, r), i); } sort(e, e + m); reverse(e, e + m); int ei = 0, stn = 0; for (int i = n - 1; i >= 0; --i) { int end = p[i] + l[i]; while (stn > 0 && st[stn - 1].first <= p[i] + l[i]) { end = max(end, st[stn - 1].second); --stn; } st[stn++] = make_pair(p[i], end); sum[stn - 1] = 0; if (stn > 1) sum[stn - 1] += sum[stn - 2] + st[stn - 2].first - end; while (ei < m && e[ei].first.first == i) { int pos = lower_bound(st, st + stn, make_pair(p[e[ei].first.second], inf), greater<pair<int, int> >()) - st; answer[e[ei].second] = sum[stn - 1] - sum[pos]; ei++; } } for (int i = 0; i < m; ++i) printf( %d n , answer[i]); return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_one_cold (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter inactive = `OVL_INACTIVE_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ONE_COLD";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_one_cold_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_one_cold_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_one_cold_psl_logic.v"
`else
`endmodule // ovl_one_cold
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_TB_V
`define SKY130_FD_SC_HD__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hd__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_TB_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); template <typename T> void chmin(T &x, const T &y) { if (x > y) x = y; } template <typename T> void chmax(T &x, const T &y) { if (x < y) x = y; } template <typename T> T gcd(T x, T y) { return y ? gcd(y, x % y) : x; } template <class T> inline bool read(T &ret) { char c = getchar(); int sgn; if (c == EOF) return 0; while (c != - && (c < 0 || c > 9 )) c = getchar(); sgn = (c == - ) ? -1 : 1; ret = (c == - ) ? 0 : (c - 0 ); while (static_cast<void>(c = getchar()), c >= 0 && c <= 9 ) ret = ret * 10 + (c - 0 ); ret *= sgn; return 1; } template <class T> inline void write(T x) { if (x > 9) out(x / 10); putchar(x % 10 + 0 ); } const int N = 1e5 + 5; int x[4], y[4], an[N], n; void doit(int j) { int k = 0; for (int i = 0; i < (int)(4); ++i) y[i] = x[i]; while (true) { if (j == 4 || y[j] == 0) break; an[k++] = j; --y[j]; if (j > 0 && y[j - 1] > 0) --j; else ++j; } if (k == n) { cout << YES << endl << an[0]; for (int i = 1; i < (int)(n); ++i) cout << << an[i]; cout << endl; exit(0); } } void solve(int times) { for (int i = 0; i < (int)(4); ++i) cin >> x[i], n += x[i]; for (int j = 0; j < (int)(4); ++j) doit(j); cout << NO << endl; } void Init() {} int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int times = 1; { solve(times++); Init(); } return 0; }
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long x[100007], y[100007], xx, yy, m, p, q; long long ans; int get(int p, int q) { while ((x[q] - x[p]) * (yy - y[p]) - (y[q] - y[p]) * (xx - x[p]) <= 0) q = q % n + 1; q = (q + n - 2) % n + 1; return q; } int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %I64d%I64d , &x[i], &y[i]); for (cin >> m; m; m--) { cin >> xx >> yy; int now = 0; ans = 0; for (int i = 1; i <= n; i++) if ((xx - x[i]) * (y[i % n + 1] - y[i]) - (yy - y[i]) * (x[i % n + 1] - x[i]) < 0) now++; if (now != 0 && now != n) { cout << 0 << endl; continue; } for (p = 1, q = get(1, 1); p <= n; p++, q = get(p, q)) { int r = ((q - p) % n + n) % n; ans += ((long long)r) * (r - 1) / 2; } ans = ((long long)n * (n - 1) * (n - 2) / 6 - ans); cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> int main(int argc, const char* argv[]) { int n; std::cin >> n; std::string s; std::cin >> s; std::vector<int> v0(n); for (int i = 0; i < n; i++) v0[i] = s[i] - 0 ; bool add = true; std::vector<int> v1(n); for (int i = 0; i < n; i++) { if (add) v1[i] = v0[i] + 1; else v1[i] = v0[i]; if (v1[i] == 2) { add = true; v1[i] = 0; } else add = false; } int count = 0; for (int i = 0; i < n; i++) if (v0[i] != v1[i]) count++; std::cout << count << std::endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2013 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / / User Interface to Global Clock, Reset and 3-State Controls
// /___/ /\ Filename : STARTUPE3.v
// \ \ / \ Timestamp : Tue Jul 9 16:30:16 PDT 2013
// \___\/\___\
//
// Revision:
// 07/12/13 - Initial version.
// 02/06/14 - Fixed tristate of USRCCLKTS (CR 766066).
// 04/15/14 - Updated FCSBO, DO and DI to connect to glbl (CR 763244).
// 05/27/14 - New simulation library message format.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module STARTUPE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter PROG_USR = "FALSE",
parameter real SIM_CCLK_FREQ = 0.0
)(
output CFGCLK,
output CFGMCLK,
output [3:0] DI,
output EOS,
output PREQ,
input [3:0] DO,
input [3:0] DTS,
input FCSBO,
input FCSBTS,
input GSR,
input GTS,
input KEYCLEARB,
input PACK,
input USRCCLKO,
input USRCCLKTS,
input USRDONEO,
input USRDONETS
);
reg SIM_CCLK_FREQ_BINARY;
reg [2:0] PROG_USR_BINARY;
time CFGMCLK_PERIOD = 20000;
reg cfgmclk_out;
localparam MODULE_NAME = "STARTUPE3";
assign glbl.GSR = GSR;
assign glbl.GTS = GTS;
wire start_count;
integer edge_count = 0;
reg preq_deassert = 0;
reg PREQ_out = 0;
wire EOS_out;
// Counters and Flags
reg [2:0] edge_count_cclko = 0;
reg [2:0] cclko_wait_count = 3'b010;
reg start_glbl_cclko = 0;
initial begin
case (PROG_USR)
"FALSE" : PROG_USR_BINARY = 3'b000;
"TRUE" : PROG_USR_BINARY = 3'b111;
default : begin
$display("Error: [Unisim %s-101] PROG_USR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PROG_USR);
$finish;
end
endcase
if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0))
SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ;
else begin
$display("Error: [Unisim %s-102] SIM_CCLK_FREQ attribute is set to %f. Legal values for this attribute are 0.0 to 10.0. Instance: %m", MODULE_NAME, SIM_CCLK_FREQ);
$finish;
end
end
//-------------------------------------------------------------------------------
//----------------- Initial -----------------------------------------------------
//-------------------------------------------------------------------------------
initial begin
cfgmclk_out = 0;
forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out;
end
//-------------------------------------------------------------------------------
//-------------------- PREQ -----------------------------------------------------
//-------------------------------------------------------------------------------
assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0;
always @(posedge cfgmclk_out) begin
if(start_count)
edge_count = edge_count + 1;
else
edge_count = 0;
if(edge_count == 35)
preq_deassert <= 1'b1;
else
preq_deassert <= 1'b0;
end
always @(negedge glbl.PROGB_GLBL, posedge preq_deassert)
PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert;
//-------------------------------------------------------------------------------
//-------------------- ERROR MSG ------------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge PACK) begin
if(PREQ_out == 1'b0)
$display("Error: [Unisim %s-1] PACK received with no associate PREQ. Instance: %m", MODULE_NAME);
end
//-------------------------------------------------------------------------------
//--------------------- EOS -----------------------------------------------------
//-------------------------------------------------------------------------------
assign EOS_out = ~glbl.GSR;
//-------------------------------------------------------------------------------
//-------------------- glbl.CCLKO ---------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge USRCCLKO) begin
if(EOS_out) edge_count_cclko <= edge_count_cclko + 1;
end
always @(edge_count_cclko)
if (edge_count_cclko == cclko_wait_count)
start_glbl_cclko = 1;
//-------------------------------------------------------------------------------
//-------------------- OUTPUT ---------------------------------------------------
//-------------------------------------------------------------------------------
assign CFGMCLK = cfgmclk_out;
assign PREQ = PREQ_out;
assign EOS = EOS_out;
// assign glbl.CCLKO_GLBL = start_glbl_cclko ? ~USRCCLKTS? USRCCLKO : 1'b1 : 1'b1;
assign glbl.CCLKO_GLBL = start_glbl_cclko ? (~USRCCLKTS ? USRCCLKO : 1'bz) : 1'b1;
assign glbl.FCSBO_GLBL = ~FCSBTS ? FCSBO : 1'bz;
assign glbl.DO_GLBL[0] = ~DTS[0] ? DO[0] : 1'bz;
assign glbl.DO_GLBL[1] = ~DTS[1] ? DO[1] : 1'bz;
assign glbl.DO_GLBL[2] = ~DTS[2] ? DO[2] : 1'bz;
assign glbl.DO_GLBL[3] = ~DTS[3] ? DO[3] : 1'bz;
assign DI = glbl.DI_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; mt19937 rnnnd(chrono::steady_clock::now().time_since_epoch().count()); inline int read() { int x = 0, f = 1, c = getchar(); while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = (x << 1) + (x << 3) + (c ^ 48); c = getchar(); } return f == 1 ? x : -x; } const int N = 1e5 + 4; int n, m, c[N], vis[N], dep[N], up1[N], up2[N]; vector<int> e[N], ans; void upd(int x, int v) { if (!v || dep[v] >= dep[x]) return; if (!up1[x] || dep[v] < dep[up1[x]]) { up2[x] = up1[x]; up1[x] = v; } else if (!up2[x] || dep[v] < dep[up2[x]]) up2[x] = v; } bool dfs_1(int x) { vis[x] = 2; for (auto v : e[x]) { if (!vis[v]) { dep[v] = dep[x] + 1; if (dfs_1(v)) return 1; upd(x, up1[v]); upd(x, up2[v]); } else if (vis[v] == 1) return 1; else upd(x, v); } vis[x] = 1; return 0; } void dfs_3(int x) { vis[x] = 3; if (!up1[x] || (!up2[x] && up1[up1[x]])) { up1[x] = 1; ans.push_back(x); } else up1[x] = 0; for (auto v : e[x]) if (vis[v] != 3) dfs_3(v); } inline void solve() { for (int i = 1; i <= n; i++) e[i].clear(); n = read(); m = read(); for (int i = 1, u, v; i <= m; i++) { u = read(); v = read(); e[u].push_back(v); } for (int i = 1; i <= n; i++) c[i] = i; shuffle(c + 1, c + n + 1, rnnnd); for (int i = 1; i <= min(n, 100); i++) { memset(vis, 0, sizeof(int) * (n + 1)); memset(up1, 0, sizeof(int) * (n + 1)); memset(up2, 0, sizeof(int) * (n + 1)); memset(dep, 0, sizeof(int) * (n + 1)); if (dfs_1(c[i])) continue; dfs_3(c[i]); if (ans.size() * 5 >= n) { sort(ans.begin(), ans.end()); for (auto v : ans) cout << v << ; puts( ); } else puts( -1 ); ans.clear(); return; } puts( -1 ); } int main() { for (int T = read(); T--;) solve(); return (0 - 0); }
|
#include <bits/stdc++.h> using namespace std; map<string, int> m; int main() { int n; cin >> n; string h; cin >> h; m[h]++; for (int i = 0; i < n; i++) { string s; cin >> s; string a = , b = ; for (int i = 0; i < 3; i++) a += s[i]; for (int i = 5; i < 8; i++) b += s[i]; m[a]++; m[b]++; } cout << (m[h] % 2 ? home : contest ) << endl; }
|
module VGAController(
input iClk,
input inRst,
input [7:0] iR,
input [7:0] iG,
input [7:0] iB,
output [7:0] oR,
output [7:0] oG,
output [7:0] oB,
output oHSync,
output oVSync,
output oLineValid,
output oFrameValid
);
/*****************************************************************
* H timings
****************************************************************/
parameter H_SYNC_PULSE = 96;
parameter H_SYNC_BACK = 48;
parameter H_SYNC_DATA = 640;
parameter H_SYNC_FRONT = 16;
parameter H_SYNC_TOTAL = H_SYNC_FRONT + H_SYNC_PULSE + H_SYNC_BACK + H_SYNC_DATA;
/*****************************************************************
* V timings
****************************************************************/
parameter V_SYNC_PULSE = 2;
parameter V_SYNC_BACK = 36;
parameter V_SYNC_DATA = 480;
parameter V_SYNC_FRONT = 7;
parameter V_SYNC_TOTAL = V_SYNC_FRONT + V_SYNC_PULSE + V_SYNC_BACK + V_SYNC_DATA;
/*****************************************************************
* Data offsets
****************************************************************/
parameter H_START_DATA = H_SYNC_BACK + H_SYNC_PULSE + H_SYNC_FRONT;
parameter V_START_DATA = V_SYNC_BACK + V_SYNC_PULSE + V_SYNC_FRONT;
parameter H_STOP_DATA = H_START_DATA + H_SYNC_DATA;
parameter V_STOP_DATA = V_START_DATA + V_SYNC_DATA;
/*****************************************************************
* Sync pulses offsets
****************************************************************/
parameter H_START_PULSE = H_SYNC_FRONT;
parameter V_START_PULSE = V_SYNC_FRONT;
parameter H_STOP_PULSE = H_SYNC_FRONT + H_SYNC_PULSE;
parameter V_STOP_PULSE = V_SYNC_FRONT + V_SYNC_PULSE;
/*****************************************************************
* Internal schedule counters
****************************************************************/
reg [12:0] mHCounter = 0;
reg [12:0] mVCounter = 0;
/*****************************************************************
* Async assignments
****************************************************************/
assign oVSync = (mVCounter >= V_START_PULSE && mVCounter < V_STOP_PULSE && inRst ) ? 0 : 1;
assign oHSync = (mHCounter >= H_START_PULSE && mHCounter < H_STOP_PULSE && inRst ) ? 0 : 1;
assign oFrameValid = (mVCounter >= V_START_DATA && mVCounter < V_STOP_DATA && inRst ) ? 1 : 0;
assign oLineValid = (mHCounter >= H_START_DATA && mHCounter < H_STOP_DATA && oFrameValid) ? 1 : 0;
assign oR = (oLineValid && oFrameValid && inRst) ? iR : 0;
assign oG = (oLineValid && oFrameValid && inRst) ? iG : 0;
assign oB = (oLineValid && oFrameValid && inRst) ? iB : 0;
/*****************************************************************
* Pixel counter generator
****************************************************************/
always@(negedge iClk or negedge inRst)
begin
if(~inRst) mHCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1)) mHCounter <= 0;
else mHCounter <= mHCounter + 1;
end
end
/*****************************************************************
* Line counter generator
****************************************************************/
always@(negedge iClk or negedge inRst)
begin
if(~inRst) mVCounter <= 0;
else
begin
if(mHCounter == (H_SYNC_TOTAL - 1))
begin
if(mVCounter == (V_SYNC_TOTAL - 1)) mVCounter <= 0;
else mVCounter <= mVCounter + 1;
end
else mVCounter <= mVCounter;
end
end
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1;
input CLK;
input RST_N;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK /* or negedge RST_N */ )
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST_N == 0)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */)
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if ( RST_N )
end
// synopsys translate_on
endmodule
|
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this start_of_frametware and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//ft_master_interface.v
`timescale 1ns/1ps
module sim_interface (
//boilerplate
input rst,
input clk,
//Sim Interface
output o_sim_master_ready,
input i_sim_in_reset,
input i_sim_in_ready,
input [31:0] i_sim_in_command,
input [31:0] i_sim_in_address,
input [31:0] i_sim_in_data,
input [31:0] i_sim_in_data_count,
input i_sim_out_ready,
output o_sim_out_en,
output [31:0] o_sim_out_status,
output [31:0] o_sim_out_address,
output [31:0] o_sim_out_data,
output [27:0] o_sim_out_data_count,
//master interface
input i_master_ready,
output reg o_ih_reset,
output reg o_ih_ready,
output reg [31:0] o_in_command,
output reg [31:0] o_in_address,
output reg [31:0] o_in_data,
output reg [27:0] o_in_data_count,
output reg o_oh_ready,
input i_oh_en,
input [31:0] i_out_status,
input [31:0] i_out_address,
input [31:0] i_out_data,
input [27:0] i_out_data_count
);
//Local Parameters
//Registers/Wires
//Submodules
//Asynchronous Logic
assign o_sim_master_ready = i_master_ready;
assign o_sim_out_en = i_oh_en;
assign o_sim_out_status = i_out_status;
assign o_sim_out_address = i_out_address;
assign o_sim_out_data = i_out_data;
assign o_sim_out_data_count = i_out_data_count;
//Synchronous Logic
always @ (i_sim_in_reset) begin
o_ih_reset = i_sim_in_reset;
end
always @ (i_sim_in_ready) begin
o_ih_ready = i_sim_in_ready;
end
always @ (i_sim_in_command) begin
o_in_command = i_sim_in_command;
end
always @ (i_sim_in_address) begin
o_in_address = i_sim_in_address;
end
always @ (i_sim_in_data) begin
o_in_data = i_sim_in_data;
end
always @ (i_sim_in_data_count) begin
o_in_data_count = i_sim_in_data_count;
end
always @ (i_sim_out_ready) begin
o_oh_ready = i_sim_out_ready;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int main() { vector<int> p; vector<int> n; vector<int> z; int t; cin >> t; int x; for (int i = 0; i < t; i++) { cin >> x; if (x > 0) p.push_back(x); else if (x < 0) n.push_back(x); else z.push_back(x); } if (t == 1) cout << x; else if (z.size() == t) { for (int i = 0; i < z.size(); i++) cout << z[i] << ; } else if (z.size() + n.size() == t) { if (n.size() == 1) cout << 0; else { if (n.size() % 2 != 0) { sort(n.rbegin(), n.rend()); for (int i = 1; i < n.size(); i++) cout << n[i] << ; } else { for (int i = 0; i < n.size(); i++) cout << n[i] << ; } } } else if ((p.size() > 0 || p.size() == 0) && (n.size() > 0 || n.size() == 0)) { for (int i = 0; i < p.size(); i++) cout << p[i] << ; if (n.size() % 2 == 0) { for (int i = 0; i < n.size(); i++) cout << n[i] << ; } else { sort(n.rbegin(), n.rend()); for (int i = 1; i < n.size(); i++) cout << n[i] << ; } } }
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#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; void solve() { long long x; cin >> x; long long n = 2; long long tot = (n * (n - 1)) / 2; long long ans = 0; while (tot <= x) { ans++; n *= 2; tot += (n * (n - 1)) / 2; } cout << ans << endl; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> static const int INF = std::numeric_limits<int>::max(); int dp[101][201]; int main() { int n; std::cin >> n; std::vector<int> t(n), w(n); for (int i = 0; i < n; ++i) { std::cin >> t[i] >> w[i]; } memset(dp, -1, sizeof(dp)); dp[0][0] = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < 200; ++j) { if (dp[i][j] == -1) continue; if (dp[i + 1][j] == -1) { dp[i + 1][j] = dp[i][j] + w[i]; } else { dp[i + 1][j] = std::min(dp[i + 1][j], dp[i][j] + w[i]); } if (dp[i + 1][j + t[i]] == -1) { dp[i + 1][j + t[i]] = dp[i][j]; } else { dp[i + 1][j + t[i]] = std::min(dp[i + 1][j + t[i]], dp[i][j]); } } } int res = INF; for (int i = 0; i <= 200; ++i) { if (dp[n][i] == -1 || dp[n][i] > i) continue; res = i; break; } std::cout << res << std::endl; }
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#include <bits/stdc++.h> using namespace std; void arr(string &s); int main() { int n = 0, k = 0, m = 0; bool b = 0; cin >> n >> k; string s = ; cin >> s; arr(s); for (int i = 0; i < s.length(); i++) switch (s[i]) { case G : m = i; i = s.length(); break; } for (int i = m; i < s.length(); i += k) switch (s[i]) { case T : b = 1; i = s.length(); break; case # : i = s.length(); break; } switch (b) { case 1: cout << YES n ; break; default: cout << NO n ; } } void arr(string &s) { int a = 0, b = 0; string v = s; for (int i = 0; i < s.length(); i++) { switch (s[i]) { case G : a = i; break; case T : b = i; break; } } if (a > b) { for (int i = 1; i <= s.length(); i++) v[i - 1] = s[s.length() - i]; s = v; } }
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#include <bits/stdc++.h> using namespace std; const long long LLINF = 1e18 + 7; const long long INF = 1e9 + 7; const long long EPS = 1e-9 - 7; const long long MAX = 1e2 + 7; const long long MOD = 1e9 + 7; int n, d, dp[MAX]; string s; bool can[MAX], flag = false; int main() { memset(dp, MAX, sizeof dp); cin >> n >> d >> s; for (int i = 0; i < n; i++) { if (s[i] == 1 ) { can[i + 1] = true; } } for (int i = n - 1; i >= 1; i--) { if (n - i <= d && can[i]) { flag = true; dp[i] = 1; } } if (!flag) { cout << -1 << endl; return 0; } for (int i = n - 1; i >= 1; i--) { for (int j = i - 1; j >= 1; j--) { if (i - j <= d && can[j] && can[i]) { dp[j] = min(dp[j], dp[i] + 1); } } } if (dp[1] >= n) { cout << -1 << endl; return 0; } cout << dp[1] << endl; return 0; }
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#include<bits/stdc++.h> #define ll long long int using namespace std; int t; int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; int sum=0; int odd=-1; vector<int> a(n); for (int q=0;q<n;q++){ int x; cin>>x; a[q]=x; sum+=x; if (odd==-1 && x%2==1){ odd=q; } } if (sum%2==1){ cout<<0<< n ; }else{ int s=sum/2; bool dp[n+1][s+1]; for (int i=0;i<=n;i++){ dp[i][0]=true; } for (int j=1;j<=s;j++){ dp[0][j]=false; } for (int i=1;i<=n;i++){ for (int j=1;j<=s;j++){ if (dp[i-1][j]==true){ dp[i][j]=true; }else{ if (a[i-1]>j){ dp[i][j]=false; }else{ dp[i][j]=dp[i-1][j-a[i-1]]; } } } } if (dp[n][s]==false){ cout<<0<< n ; }else{ if (odd!=-1){ cout<<1<< n ; cout<<odd+1<< n ; }else{ int idx=-1; int mn=33; for (int i=0;i<n;i++){ if (mn > __builtin_ctz(a[i])){ mn=__builtin_ctz(a[i]); idx=i; } } cout<<1<< n ; cout<<idx+1<< n ; } } } }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 14:50:35
// Design Name:
// Module Name: _8_to_3_priority_encoder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module _8_to_3_priority_encoder_tb(
);
reg [7:0] v;
reg in;
wire [2:0] y;
wire out;
wire gs;
_8_to_3_priority_encoder DUT (.v(v), .en_in_n(in), .y(y), .en_out(out), .gs(gs));
initial begin
{in, v} = 9'b1_xxxx_xxxx;
#10 {in, v} = 9'b1_xxxx_xxxx;
#10 {in, v} = 9'b0_1111_1111;
#10 {in, v} = 9'b0_xxxx_xxx0;
#10 {in, v} = 9'b0_xxxx_xx01;
#10 {in, v} =9'b0_xxxx_x011 ;
#10 {in, v} =9'b0_xxxx_0111 ;
#10 {in, v} = 9'b0_xxx0_1111;
#10 {in, v} = 9'b0_xx01_1111;
#10 {in, v} = 9'b0_x011_1111;
#10 {in, v} = 9'b0_0111_1111;
#20;
end
endmodule
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module diffeq_paj_convert (clk, reset,Xinport, Yinport, Uinport, Aport, DXport, Xoutport, Youtport, Uoutport );
input[31:0] Xinport;
input[31:0] Yinport;
input[31:0] Uinport;
input[31:0] Aport;
input[31:0] DXport;
input clk;
input reset;
output[31:0] Xoutport;
output[31:0] Youtport;
output[31:0] Uoutport;
reg[31:0] Xoutport;
reg[31:0] Youtport;
reg[31:0] Uoutport;
reg[31:0] x_var;
reg[31:0] y_var;
reg[31:0] u_var;
wire[31:0] temp;
reg looping;
assign temp = u_var * DXport;
always @(posedge clk)
begin
if (reset == 1'b1)
begin
looping <= 1'b0;
x_var <= 0;
y_var <= 0;
u_var <= 0;
end
else
if (looping == 1'b0)
begin
x_var <= Xinport;
y_var <= Yinport;
u_var <= Uinport;
looping <= 1'b1;
end
else if (x_var < Aport)
begin
u_var <= (u_var - (temp/*u_var * DXport*/ * 3 * x_var)) - (DXport * 3 * y_var);
y_var <= y_var + temp;//(u_var * DXport);
x_var <= x_var + DXport;
looping <= looping;
end
else
begin
Xoutport <= x_var ;
Youtport <= y_var ;
Uoutport <= u_var ;
looping <= 1'b0;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m; char mp[103][103]; int main() { int i, j, cnt; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %s , mp[i]); cnt = 0; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) if (mp[i][j] == . ) break; if (j != n) cnt++; } if (cnt == n) { for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (mp[i][j] == . ) { printf( %d %d n , i + 1, j + 1); break; } return 0; } int a, v, c; cnt = 0; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) if (mp[j][i] == . ) break; if (j != n) cnt++; } if (cnt == n) { for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (mp[j][i] == . ) { printf( %d %d n , j + 1, i + 1); break; } return 0; } puts( -1 ); return 0; }
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