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// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
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#include <bits/stdc++.h> using namespace std; double tick() { static clock_t oldtick; clock_t newtick = clock(); double diff = 1.0 * (newtick - oldtick) / CLOCKS_PER_SEC; oldtick = newtick; return diff; } long long gcd(long long a, long long b) { if ((a == 0) || (b == 0)) { return a + b; } return gcd(b, a % b); } long long powMod(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return (res % 1000000007); } long long pow2(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = (res * a); a = (a * a); b >>= 1; } return res; } bool isPrime(long long a) { for (long long i = 3; (i * i) <= a; i += 2) { if ((a % i) == 0) return false; } if ((a != 2) && ((a % 2) == 0)) { return false; } if (a == 1) { return false; } return true; } string conLlToStr(long long a) { stringstream mystr; mystr << a; return mystr.str(); } long long conStrToLl(string st) { long long numb = 0; long long len = st.size(), i, j = 0; for (long long i = len - 1; i >= 0; i--) { numb += (pow2(10, j) * (st[i] - 0 )); j++; } return numb; } long long basenoToDecimal(string st, long long basee) { long long i = 0, j, anss = 0; for (long long j = (int)st.length() - 1; j >= 0; j--) { anss += (st[j] - 0 ) * pow2(basee, i); i++; } return anss; } string decimalToString(long long num, long long basee) { long long i = 0, j, opop; string anss = ; vector<string> stri; stri.push_back( 0 ); stri.push_back( 1 ); stri.push_back( 2 ); stri.push_back( 3 ); stri.push_back( 4 ); stri.push_back( 5 ); stri.push_back( 6 ); stri.push_back( 7 ); stri.push_back( 8 ); stri.push_back( 9 ); stri.push_back( A ); stri.push_back( B ); stri.push_back( C ); stri.push_back( D ); stri.push_back( E ); stri.push_back( F ); if (num == 0) { return 0 ; } while (num) { opop = (num % basee); anss += stri[opop]; num /= basee; } reverse(anss.begin(), anss.end()); return anss; } long long my_sqrt(long long x) { long long y = (long long)(sqrtl((long double)x) + 0.5); while (y * y < x) { y++; } while (y * y > x) { y--; } if (y * y == x) { return y; } return -1; } long long my_crt(long long x) { long long y = (long long)(powl((long double)x, 1.0 / 3.0) + 0.5); while (y * y * y < x) { y++; } while (y * y * y > x) { y--; } if (y * y * y == x) { return y; } return -1; } const int dx[] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dy[] = {1, 1, 0, -1, -1, -1, 0, 1}; string S[100010]; vector<string> stringContained[100010][30]; vector<pair<string, string> > firstString, secondString; vector<pair<pair<string, string>, pair<string, string> > > ans; set<int> numVowel; vector<string> temp; bool isVowel(char ch) { if (ch == a || ch == e || ch == i || ch == o || ch == u ) { return 1; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int N; cin >> N; for (long long i = 1; i <= N; i++) { cin >> S[i]; int vowel = 0; char lastVowel; for (long long j = 0; j <= (int)S[i].length() - 1; j++) { if (isVowel(S[i][j])) { vowel++; lastVowel = S[i][j]; } } if (vowel) { numVowel.insert(vowel); stringContained[vowel][lastVowel - a ].push_back(S[i]); } } for (auto it = numVowel.begin(); it != numVowel.end(); ++it) { int i = (*it); for (long long j = 0; j <= 25; j++) { for (int k = 0; k < (int)stringContained[i][j].size(); k += 2) { if ((k + 1) < (int)stringContained[i][j].size()) { secondString.push_back(make_pair(stringContained[i][j][k], stringContained[i][j][k + 1])); } } if (stringContained[i][j].size() % 2) { temp.push_back(stringContained[i][j][stringContained[i][j].size() - 1]); } } for (int k = 0; k < (int)temp.size(); k += 2) { if ((k + 1) < (int)temp.size()) { firstString.push_back(make_pair(temp[k], temp[k + 1])); } } temp.clear(); } int ind1 = 0, ind2 = 0; while (ind1 < firstString.size() && ind2 < secondString.size()) { ans.push_back(make_pair( make_pair(firstString[ind1].first, secondString[ind2].first), make_pair(firstString[ind1].second, secondString[ind2].second))); ind1 += 1; ind2 += 1; } for (int k = ind2; k < (int)secondString.size(); k += 2) { if ((k + 1) < (int)secondString.size()) { ans.push_back(make_pair( make_pair(secondString[k].first, secondString[k + 1].first), make_pair(secondString[k].second, secondString[k + 1].second))); } } cout << ans.size() << n ; for (long long i = 0; i <= (int)ans.size() - 1; i++) { cout << ans[i].first.first << << ans[i].first.second << n ; cout << ans[i].second.first << << ans[i].second.second << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); set<int> a; int n, t; cin >> n; while (n--) { cin >> t; a.insert(t); } cout << ((a.count(0) == 1) ? a.size() - 1 : a.size()); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, s, x, k, ans = 0, ch = 0; cin >> n >> s; s = 8 * s; vector<long long int> vec(n); vector<pair<long long int, long long int>> dat; for (long long int i = 0; i < n; i++) cin >> vec[i]; sort(vec.begin(), vec.end()); dat.push_back(make_pair(vec[0], 1)); x = vec[0]; for (long long int i = 1; i < n; i++) { if (vec[i] != x) { dat.push_back(make_pair(vec[i], 1)); x = vec[i]; } else { dat[dat.size() - 1].second++; } } while (1) { k = 0; while (pow(2, k) < dat.size() - ch) k++; k = n * k; if (k <= s) break; ch++; } x = 0; for (long long int i = 0; i < ch; i++) x = x + dat[i].second; ans = x; for (long long int i = 0; i < ch; i++) { x = x - dat[ch - i - 1].second + dat[dat.size() - i - 1].second; if (x < ans) ans = x; } cout << ans << endl; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int MAX = 2e3 + 5; const long long MAX2 = 11; const long long MOD = 998244353; const long long MOD2 = 1000005329; const long long INF = 2e18; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1, 0}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1, 0}; const double pi = acos(-1); const double EPS = 1e-9; const int block = 2000; int q, x, y, cnt; map<string, pair<long long, long long>> ans, dp; map<string, bool> jen; map<string, vector<string>> isi; string s, ty, c; pair<long long, long long> solve(string o) { if (!jen.count(o)) return ans[o]; if (isi[o].empty()) return {0, 0}; if (dp.count(o)) return dp[o]; int hit = isi[o].size() - 1; long long mx = 0, ttl = 0; pair<long long, long long> res; if (jen[o]) { for (auto i : isi[o]) { res = solve(i); mx = max(mx, res.second); ttl += res.first; } return dp[o] = {ttl + 2 * ans[o].first + hit * ans[o].second, mx + 2 * ans[o].first}; } { for (auto i : isi[o]) { res = solve(i); mx = max(mx, res.first); ttl += res.second; } return dp[o] = {mx + 2 * ans[o].first, ttl + 2 * ans[o].first + hit * ans[o].second}; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> q; while (q--) { cin >> ty; x = y = cnt = 0; if (ty == Widget ) { cin >> s; c = ; for (auto i : s) { if (i == ( || i == ) || i == , ) ++cnt; else if (cnt == 1) x = x * 10 + i - 0 ; else if (cnt == 2) y = y * 10 + i - 0 ; else c.push_back(i); } ans[c] = {x, y}; } else if (ty == VBox ) { cin >> s; ans[s]; jen[s]; } else if (ty == HBox ) { cin >> s; ans[s]; jen[s] = 1; } else { s = c = ; for (auto i : ty) { if (i == . ) ++cnt; else if (i == ( ) { if (c == pack ) cnt = 2; else if (c == set_border ) cnt = 3; else if (c == set_spacing ) cnt = 4; c = ; } else if (i == ) ) continue; else if (cnt == 0) s.push_back(i); else if (cnt == 1 || cnt == 2) c.push_back(i); else if (cnt == 3 || cnt == 4) x = x * 10 + i - 0 ; else return 1; } if (cnt == 2) isi[s].push_back(c); else if (cnt == 3) ans[s].first = x; else ans[s].second = x; } } pair<long long, long long> res; for (auto i : ans) { res = solve(i.first); cout << i.first << << res.first << << res.second << n ; } return 0; }
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/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
// Accumulates an arbitrary number of inputs with saturation
// restart the sum when input "zero" is high
module jt12_single_acc #(parameter
win=14, // input data width
wout=16 // output data width
)(
input clk,
input clk_en /* synthesis direct_enable */,
input [win-1:0] op_result,
input sum_en,
input zero,
output reg [wout-1:0] snd
);
// for full resolution use win=14, wout=16
// for cut down resolution use win=9, wout=12
// wout-win should be > 0
reg signed [wout-1:0] next, acc, current;
reg overflow;
wire [wout-1:0] plus_inf = { 1'b0, {(wout-1){1'b1}} }; // maximum positive value
wire [wout-1:0] minus_inf = { 1'b1, {(wout-1){1'b0}} }; // minimum negative value
always @(*) begin
current = sum_en ? { {(wout-win){op_result[win-1]}}, op_result } : {wout{1'b0}};
next = zero ? current : current + acc;
overflow = !zero &&
(current[wout-1] == acc[wout-1]) &&
(acc[wout-1]!=next[wout-1]);
end
always @(posedge clk) if( clk_en ) begin
acc <= overflow ? (acc[wout-1] ? minus_inf : plus_inf) : next;
if(zero) snd <= acc;
end
endmodule // jt12_single_acc
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_1_V
`define SKY130_FD_SC_LP__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_1_V
|
#include <bits/stdc++.h> using namespace std; long long int dp[2010][2010]; long long int a[2010]; long long int b[2010]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i]; } for (int i = 0; i <= 2000; i++) { for (int j = 0; j <= 2000; j++) { dp[i][j] = 10000000000000000; } } dp[0][0] = 0; for (int i = 1; i <= n; i++) { long long int o = a[i] + 1; for (int j = 0; j <= n; j++) { o = a[i] + 1; if (j == 0) { dp[i][j] = 0; } if (o >= j) { o = j; } if (j >= o) { dp[i][j] = min(b[i] + dp[i - 1][j - (o)], dp[i][j]); } dp[i][j] = min(dp[i][j], dp[i - 1][j]); } } cout << dp[n][n] << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int n, l, k, i, p[256], a[256], j, w; double f[201][512][201], aa; int main() { scanf( %d%d%d , &n, &l, &k); k = min(k, n); for (i = 0; i < n; ++i) scanf( %d , p + i); for (i = 0; i < n; ++i) scanf( %d , a + i); f[0][k + 256][0] = 1; for (i = 0; i < n; ++i) for (j = -i; j <= n; ++j) for (w = 0; w <= i; ++w) if (f[i][j + 256][w] > 0) { f[i + 1][256 + min(j + a[i], n)][w + 1] += f[i][j + 256][w] * p[i] / 100; f[i + 1][j + 256][w] += f[i][j + 256][w] * (100 - p[i]) / 100; } for (j = 0; j <= n; ++j) for (w = l; w <= n; ++w) aa += f[n][j + 256][w]; printf( %.12lf n , aa); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s[n]; int a[n]; for (int x = 0; x < n; x++) { cin >> s[x]; a[x] = s[x].length(); } for (int x = 0; x < n; x++) { for (int y = 0; y < n - 1; y++) { if (a[y] > a[y + 1]) { int t = a[y]; a[y] = a[y + 1]; a[y + 1] = t; string temp = s[y]; s[y] = s[y + 1]; s[y + 1] = temp; } } } int f = 0; for (int x = 0; x < n; x++) { int i; for (int y = x + 1; y < n; y++) { i = s[y].find(s[x], 0); if (i == -1) { f = 1; break; } } if (f == 1) { break; } } if (f == 1) { cout << NO ; } else { cout << YES << endl; for (int x = 0; x < n; x++) { cout << s[x] << endl; } } }
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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline long long read() { long long x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(long long a) { if (a < 0) { a = -a; putchar( - ); } if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(long long a) { write(a); puts( ); } inline void wri(long long a) { write(a); putchar( ); } const int N = 205; const long long inf = 4e18; int n, m; long long f[N][N], k, g[N][N]; string F[N]; long long sol(string x) { int len = x.length(); x = + x; int p = 0; memset(f, 0, sizeof(f)); for (int i = 1; i <= len; i++) x[i] -= 0 ; f[0][x[1]] = 1; for (int i = 1; i <= len; i++) { if (i > 1) p = f[p][x[i]]; if (i < len && x[i + 1] == 0) f[i][0] = i + 1; else f[i][0] = f[p][0]; if (i < len && x[i + 1] == 1) f[i][1] = i + 1; else f[i][1] = f[p][1]; } for (int i = 0; i <= len; i++) { g[i][0] = f[i][0] == len; g[i][1] = f[i][1] == len; } for (int i = 2; i <= n; i++) { for (int j = 0; j <= len; j++) { f[j][i] = f[f[j][i - 2]][i - 1]; g[j][i] = min(inf, g[j][i - 2] + g[f[j][i - 2]][i - 1]); } } return g[0][n]; } int main() { n = read(); k = read(); m = read(); string s = ; F[0] = 0 ; F[1] = 1 ; for (int i = 2; i <= n; i++) { F[i] = F[i - 2] + F[i - 1]; if (F[i].length() > m) F[i] = F[i].substr(F[i].length() - m, m); } m = min(m, (int)F[n].length()); for (int i = 1; i <= m; i++) { if (s.length() && F[n].substr(F[n].length() - s.length(), s.length()) == s) { if (--k == 0) { cout << s << endl; return 0; } } s += 0 ; long long t = sol(s); if (t < k) { k -= t; s.pop_back(); s += 1 ; } } cout << s << endl; }
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#include <bits/stdc++.h> int main() { int i, j, k, n, t, c1, c2, c3, c4, c5; scanf( %d%d%d%d%d , &c1, &c2, &c3, &c4, &c5); t = c1 + c2 + c3 + c4 + c5; if (t == 0) printf( -1 n ); else if (t % 5 == 0) printf( %d n , t / 5); else printf( -1 n ); }
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#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; long long a, b, c, d, e, f, k; bool check(long long x, long long y) { if (k == 0) { return x == c && y == d; } return ((c - x) * e + (d - y) * f) % k == 0 && (e * (d - y) + f * (x - c)) % k == 0; } int main() { while (cin >> a >> b >> c >> d >> e >> f) { k = e * e + f * f; if (check(a, b) || check(-a, -b) || check(b, -a) || check(-b, a)) { cout << YES << endl; } else cout << NO << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int sum = 0; bool ok = false; for (int i = 1; i <= n; i++) { sum = i + sum; if (n == 1 || n == sum) { cout << YES << endl; break; } if (sum > n) { ok = true; break; } } if (ok) cout << NO << endl; return 0; }
|
module jsrflipfloptb;
wire q, qbar;
reg clk,rst;
reg [1:0] sr;
jsrflipflop jsrff(q,qbar,clk,rst,sr);
always #5 clk = ~clk;
initial
begin
clk = 1'b0;
rst = 1; # 10; rst = 0; #10;
$display("RSLT\ts\tr\tq\tqbar");
sr = 0; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
sr = 1; # 10; // Another value
if ( q === 1'b0 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
sr = 2; # 10; // Another value
if ( q === 1'b1 ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
sr = 3; # 10; // Another value
if ( q === 1'bx ) // Test for inversion
$display ("PASS\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
else
$display ("FAIL\t%d\t%d\t%d\t%d",sr[1],sr[0],q,qbar);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void reverseStr(string& str) { int n = str.length(); for (int i = 0; i < n / 2; i++) swap(str[i], str[n - i - 1]); } int main() { string str, str1; cin >> str; cin >> str1; reverseStr(str); if (str == str1) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int N = 100010; int n, k, m; int a[N]; int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; int cnt = 0; while (k > 0) { cnt += 1; k -= cnt; } cout << a[k + cnt]; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void print(T t) { cout << t << endl; } long long n = 0, t = 0; long long small = -1e18, big = 1e18; const long long mod = 1e9 + 7; map<long long, long long> occ; map<pair<long long, long long>, long long> occP; void print2dVec(vector<vector<long long>> v) { for (int i = 0; i < v.size(); ++i) { cout << i << : ; for (int j = 0; j < v[i].size(); ++j) { cout << v[i][j] << ; } print( ); } } void printSet(set<int> s) { for (auto itr = s.begin(); itr != s.end(); ++itr) { cout << *itr << ; } } long long factorial(int n) { long long ans = 1; for (int i = 1; i <= n; ++i) { ans *= i; } return ans; } long long findGCD(long long a, long long b) { long long ans = 1; for (int i = 1; i <= min(a, b); ++i) { if (a % i == 0 && b % i == 0) { ans = i; } } return ans; } long long findLCM(long long a, long long b) { for (long long i = min(a, b); i <= a * b; ++i) { if (i % a == 0 && i % b == 0) { return i; } } return -1; } bool isPrime(int num) { if (num <= 1) return false; if (num <= 3) return true; int range = sqrt(num); if (num % 2 == 0 || num % 3 == 0) return false; for (int i = 5; i <= range; i += 6) if (num % i == 0 || num % (i + 2) == 0) return false; return true; } vector<long long> primeFactors(long long x) { vector<long long> fac; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { while (x % i == 0) { fac.push_back(i); x /= i; } } } return fac; } bool sortVec(const vector<long long>& v1, const vector<long long>& v2) { return v1[0] < v2[0]; } bool check(long long val) { return false; } long long binsearch(long long low, long long high) { while (low < high) { long long mid = (low + high) / 2; if (check(mid)) { high = mid; } else { low = mid + 1; } } return low; } unordered_map<long long, long long> d; long long rib(long long n, long long a, long long b, long long c) { if (n == 0) return 0; if (n < 0) return small; if (d.count(n)) return d[n]; else { d[n] = 1 + max(rib(n - a, a, b, c), max(rib(n - b, a, b, c), rib(n - c, a, b, c))); return d[n]; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed; cout << setprecision(10); ; long long n, a, b, c; cin >> n >> a >> b >> c; cout << rib(n, a, b, c); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 20; long long int c[15][maxn]; int lowbit(int x) { return x & (-x); } void upDate(int pos, long long int val, int which) { while (pos <= maxn - 20) { c[which][pos] += val; pos += lowbit(pos); } } long long int ask(int pos, int which) { long long int ans = 0; while (pos) { ans += c[which][pos]; pos -= lowbit(pos); } return ans; } long long int dp[maxn][15]; void work() { int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) { int x; cin >> x; dp[i][1] = 1; for (int j = 2; j <= k + 1; ++j) { dp[i][j] += ask(x - 1, j - 1); } for (int j = 1; j <= k + 1; ++j) { upDate(x, dp[i][j], j); } } long long int ans = 0; for (int i = 1; i <= n; ++i) ans += dp[i][k + 1]; cout << ans << endl; } int main() { ios::sync_with_stdio(false); work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 100001; long long n, k, l[MAX], inf = 1000000000000; multiset<long long> kek; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) { cin >> l[i + 1]; } long long a; cin >> a; long long ans = 0; kek.insert(inf); for (int i = 1; i <= n; i++) { long long b; cin >> b; kek.insert(b); while (k < l[i]) { if (*(kek.begin()) == inf) { cout << -1; return 0; } long long take = *(kek.begin()); kek.erase(kek.find(take)); k += a; ans += take; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<vector<long long>> a; bool tr = true; for (long long l, r, i = 0; i < n; i++) { cin >> l >> r; a.push_back({l, r}); } sort(a.begin(), a.end(), [](const vector<long long>& a, const vector<long long>& b) -> bool { if (a[0] == b[0]) { return a[1] < b[1]; } else { return a[0] < b[0]; } }); long long f = -1, s = -1; for (long long i = 0; i < n; i++) { if (tr && a[i][0] > f) { f = a[i][1]; } else if (tr && a[i][0] > s) { s = a[i][1]; } else { tr = false; } } if (tr) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
`timescale 1ns/1ns
module camera
(
input refclk,
input reset_n,
output pixclk,
output vsync,
output hsync,
output [7:0] data
);
reg [12:0] hs_counter = 0;
reg [9:0] vs_counter = 0;
assign pixclk = refclk;
always @(negedge refclk)
begin
if(reset_n == 0)
begin
hs_counter = 0;
vs_counter = 0;
end
else
begin
if(hs_counter == 1567)
begin
hs_counter <= 0;
if(vs_counter == 510)
vs_counter <= 0;
else
vs_counter <= vs_counter + 1;
end
else
hs_counter <= hs_counter + 1;
end
end
reg clk2 = 0;
always@(negedge refclk)
clk2 <= !clk2;
reg [16:0] pixel_counter = 0;
always@(posedge clk2)
begin
if(hs_counter == 1566)
pixel_counter <= 0;
else
pixel_counter <= pixel_counter + 1;
end
reg [7:0] temp_data;
wire [15:0] line_counter;
reg [15:0] line_counter_2;
reg data_part = 0;
always@(negedge refclk)
begin
if(reset_n == 0)
begin
data_part <= 0;
temp_data <= 0;
end
else
begin
if(!clk2)
temp_data[7:0] <= pixel_counter[15:8];
else
temp_data[7:0] <= pixel_counter[7:0];
end
end
assign data = temp_data;
assign vsync = vs_counter < 3 && reset_n != 0 ? 1 : 0;
assign hsync = vs_counter > 19 && vs_counter < 500 && hs_counter < 1280 && reset_n != 0 ? 1 : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const string pocetno = 0000000000 ; const string oznake = RGBYW ; const int maxn = 105; int N, razlicite, sol = maxn * maxn; vector<pair<int, int> > V; set<string> S; void rijesi() { for (int maska = 0; maska < (1 << 10) + 1; maska++) { S.clear(); int tmp = 0; for (int i = 0; i < 10; i++) if (maska & (1 << i)) tmp++; for (int i = 0; i < N; i++) { string stanje = pocetno; for (int j = 0; j < 5; j++) { if (maska & (1 << j) && V[i].first == j) stanje[j] = 1 ; if (maska & (1 << (j + 5)) && V[i].second == j) stanje[j + 5] = 1 ; } S.insert(stanje); } if (S.size() == razlicite) sol = min(sol, tmp); } printf( %d n , sol); } void ucitaj() { scanf( %d , &N); for (int i = 0; i < N; i++) { string s; cin >> s; V.push_back(make_pair(oznake.find(s[0]), s[1] - 0 - 1)); S.insert(s); } razlicite = S.size(); } int main(void) { ucitaj(); rijesi(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353, INF = 1e9; const long long N = 2e5 + 1; const double ep = 1e-10; const double pi = 3.141592653589793238; void floyd() { long long n; cin >> n; string a, b; cin >> a >> b; long long a1 = 0, a2 = 0, k = 0, ans = INF, in = -1, in2 = -1; for (long long i = 0; i < n; i++) { if (a[i] == 1 ) a1++; if (b[i] == 1 ) a2++; if (a[i] == 1 && b[i] == 0 ) { k++; in2 = i; } if (a[i] == 1 && b[i] == 1 ) { in = i; } } if (a1 != a2 && (n - a1 + 1) != a2) { cout << -1 << n ; return; } if (a1 == a2) { ans = min(k * 2, INF); } string t = a; for (long long i = 0; i < n; i++) { if (a[i] == 1 ) a[i] = 0 ; else a[i] = 1 ; } if (in != -1) { a[in] = 1 ; long long k1 = 0, k2 = 0, k3 = 0, d = INF; for (long long i = 0; i < n; i++) { if (a[i] == 1 ) k1++; if (b[i] == 1 ) k2++; if (a[i] == 1 && b[i] == 0 ) { k3++; } } if (k1 == k2) { d = k3 * 2 + 1; } ans = min(ans, d); } for (long long i = 0; i < n; i++) { if (t[i] == 1 ) t[i] = 0 ; else t[i] = 1 ; } if (in2 != -1) { t[in2] = 1 ; long long k1 = 0, k2 = 0, k3 = 0, d = INF; for (long long i = 0; i < n; i++) { if (t[i] == 1 ) k1++; if (b[i] == 1 ) k2++; if (t[i] == 1 && b[i] == 0 ) { k3++; } } if (k1 == k2) { d = k3 * 2 + 1; } ans = min(ans, d); } if (ans == INF) { cout << -1 << n ; return; } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; cin >> t; while (t--) { floyd(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; void qmax(long long &x, long long y) { if (x < y) x = y; } void qmin(long long &x, long long y) { if (x > y) x = y; } inline long long read() { char s; long long k = 0, base = 1; while ((s = getchar()) != - && s != EOF && !(isdigit(s))) ; if (s == EOF) exit(0); if (s == - ) base = -1, s = getchar(); while (isdigit(s)) { k = k * 10 + (s ^ 0 ); s = getchar(); } return k * base; } inline void write(long long x) { static char cnt, num[15]; cnt = 0; if (!x) { putchar( 0 ); return; } for (; x; x /= 10) num[++cnt] = x % 10; for (; cnt; putchar(num[cnt--] + 48)) ; } const long long maxn = 100000 + 100; long long n, d, b, d1; long long a[maxn]; long long s1[maxn], s2[maxn]; signed main() { n = read(); d = read(); b = read(); d1 = n / 2 * b; for (long long i = 1; i <= n; i++) a[i] = read(); for (long long i = 1; i <= n; i++) { s1[i] = min(a[i], d1) + s1[i - 1]; d1 -= min(d1, a[i]); } d1 = n / 2 * b; for (long long i = n; i >= 1; i--) { s2[i] = min(a[i], d1) + s2[i + 1]; d1 -= min(d1, a[i]); } d1 = 0; long long R = n / 2, r = 0, ans1 = 0, ans2 = 0; for (long long i = 1; i <= R; i++) { r += d + 1; r = min(n, r); if (d1 + b <= s1[r]) d1 += b; else ans1++; } R = (n + 1) / 2 + 1; d1 = 0; r = 0; long long l = n + 1; for (long long i = n; i >= R; i--) { l -= d + 1; l = max(1ll, l); if (d1 + b <= s2[l]) d1 += b; else ans2++; } cout << max(ans1, ans2); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_2_V
`define SKY130_FD_SC_HS__DIODE_2_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__diode_2 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hs__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__diode_2 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_2_V
|
#include <bits/stdc++.h> int main() { int n, m; scanf( %d%d , &n, &m); std::vector<std::vector<int>> graph(n); for (int i = 0; i < m; ++i) { int a, b; scanf( %d%d , &a, &b); a--; b--; graph.at(a).push_back(b); graph.at(b).push_back(a); } std::vector<int> color(n, -1); bool ok = true; for (int s = 0; s < n && ok; ++s) { if (!~color[s]) { std::vector<int> queue; queue.push_back(s); color[s] = 0; for (int h = 0; h < static_cast<int>(queue.size()); ++h) { auto u = queue[h]; for (int v : graph.at(u)) { if (!~color[v]) { color[v] = color[u] ^ 1; queue.push_back(v); } ok &= color[u] != color[v]; } } } } if (ok) { std::vector<std::vector<int>> result(2); for (int i = 0; i < n; ++i) { result[color[i]].push_back(i); } for (int i = 0; i < 2; ++i) { printf( %d n , static_cast<int>(result[i].size())); for (auto&& v : result[i]) { printf( %d , v + 1); } puts( ); } } else { puts( -1 ); } }
|
module \$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module \$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
AL_MAP_LUT1 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]));
end else
if (WIDTH == 2) begin
AL_MAP_LUT2 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]));
end else
if (WIDTH == 3) begin
AL_MAP_LUT3 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]));
end else
if (WIDTH == 4) begin
AL_MAP_LUT4 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]));
end else
if (WIDTH == 5) begin
AL_MAP_LUT5 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]));
end else
if (WIDTH == 6) begin
AL_MAP_LUT6 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]), .f(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_1_V
`define SKY130_FD_SC_LP__A2BB2OI_1_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_1_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Funnel Shifter
// File : ded_funshf.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module ded_funshf
#(parameter BYTES = 4)
(
input mclock,
`ifdef BYTE16 input [6:0] rad, // fifo read address.
`elsif BYTE8 input [5:0] rad, // fifo read address.
`else input [4:0] rad, `endif // fifo read address.
input [(BYTES<<3)-1:0] bsd0, // data in from fifo_0
input [(BYTES<<3)-1:0] bsd1, // data in from fifo_1
input apat8_4, // Area 8x8 mode.
input apat32_4, // Area 32x32 mode.
output reg [(BYTES<<3)-1:0] bsout, // funnel shifter output.
output [BYTES-1:0] cx_sel // color expand data
);
`ifdef BYTE16 reg [6:0] rad_1, rad_d; // fifo read address.
`elsif BYTE8 reg [5:0] rad_1, rad_d; // fifo read address.
`else reg [4:0] rad_1, rad_d; `endif// fifo read address.
reg [(BYTES<<4)-1:0] bsin; // data in from fifo.
reg [31:0] bpck_dat;
reg [4:0] cx_rad;
wire [1:0] n_a32_rad;
wire [1:0] a32_rad;
wire [3:0] bso_sel;
wire [127:0] bs1;
wire [135:0] bs2;
wire [151:0] bs4;
wire [183:0] bs8;
wire [BYTES-1:0] cx1;
wire [BYTES:0] cx2;
wire [BYTES+2:0] cx4;
wire [BYTES+6:0] cx8;
wire [BYTES+14:0] cx16;
/************************************************************************/
// The RAD value needs to be delayed one clock. This is due to the new Rams
// which has everything delayed one cycle
always @(posedge mclock) begin
rad_1 <= rad;
rad_d <= rad_1;
bsin <= {bsd1,bsd0};
end
/************************************************************************/
/* BYTE ADDRESSING */
/************************************************************************/
assign n_a32_rad = {2{~apat32_4}} & rad_d[4:3];
`ifdef BYTE16
assign bso_sel = {rad_d[6:5],n_a32_rad};
always @*
bsout = bs1;
assign bs1 = bso_sel[0] ? bs2[135:8] : bs2[127:0];
assign bs2 = bso_sel[1] ? bs4[151:16] : bs4[135:0];
assign bs4 = bso_sel[2] ? bs8[183:32] : bs8[151:0];
assign bs8 = bso_sel[3] ? bsin[247:64] : bsin[183:0];
`endif
`ifdef BYTE8
always @*
case ({rad_d[5],n_a32_rad})
3'h0: bsout = bsin[63:0];
3'h1: bsout = bsin[71:8];
3'h2: bsout = bsin[79:16];
3'h3: bsout = bsin[87:24];
3'h4: bsout = bsin[95:32];
3'h5: bsout = bsin[103:40];
3'h6: bsout = bsin[111:48];
3'h7: bsout = bsin[119:56];
endcase
`endif
`ifdef BYTE4
always @*
case (n_a32_rad)
2'h0: bsout = bsin[31:0];
2'h1: bsout = bsin[39:8];
2'h2: bsout = bsin[47:16];
2'h3: bsout = bsin[55:24];
endcase
`endif
/************************************************************************/
/* Packed one bit per pixel mux */
/************************************************************************/
assign a32_rad = {2{apat32_4}} & rad_d[4:3];
// FB: added to increase MC clock speed
always @(posedge mclock) begin
bpck_dat <= (apat8_4) ? {4{bsout[7:0]}} : bsout[31:0];
cx_rad <= {a32_rad, rad_d[2:0]};
end
`ifdef BYTE16
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[16:1] : cx2[15:0];
assign cx2 = cx_rad[1] ? cx4[18:2] : cx4[16:0];
assign cx4 = cx_rad[2] ? cx8[22:4] : cx8[18:0];
assign cx8 = cx_rad[3] ? cx16[30:8] : cx16[22:0];
assign cx16 = cx_rad[4] ? {bpck_dat[14:0],bpck_dat[31:16]} : bpck_dat[30:0];
`endif
`ifdef BYTE8
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[8:1] : cx2[7:0];
assign cx2 = cx_rad[1] ? cx4[10:2] : cx4[8:0];
assign cx4 = cx_rad[2] ? cx8[14:4] : cx8[10:0];
assign cx8 = cx_rad[3] ? cx16[22:8] : cx16[14:0];
assign cx16 = cx_rad[4] ? {bpck_dat[6:0],bpck_dat[31:16]} : bpck_dat[22:0];
`endif
`ifdef BYTE4
assign cx_sel = cx1;
assign cx1 = cx_rad[0] ? cx2[4:1] : cx2[3:0];
assign cx2 = cx_rad[1] ? cx4[6:2] : cx4[4:0];
assign cx4 = cx_rad[2] ? cx8[10:4] : cx8[6:0];
assign cx8 = cx_rad[3] ? cx16[18:8] : cx16[10:0];
assign cx16 = cx_rad[4] ? {bpck_dat[3:0],bpck_dat[31:16]} : bpck_dat[18:0];
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mx[] = {0, 2, 3, 1}; long long get_base(long long n) { long long b = 4; for (;;) { if (b > n) return b / 4; b <<= 2; } return 0; } long long func1(long long n) { long long b = get_base(n); return (n - b) / 3 + b; } long long func2(long long n) { long long b = get_base(n); long long m = (n - b - 1) / 3; long long bb = b; vector<int> v; while (bb >= 4) { v.push_back(m % 4); m /= 4; bb /= 4; } long long r = b + b; bb = b / 4; for (int i = v.size() - 1; i >= 0; i--) { r += bb * mx[v[i]]; bb /= 4; } if (n == 2) return 2; return r; } int main() { int t; long long n, ans; ios::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { cin >> n; if (n % 3 == 0) ans = func1(n - 2) ^ func2(n - 1); else if (n % 3 == 1) ans = func1(n); else ans = func2(n); cout << ans << endl; } return 0; }
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 11:17:35
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <= 7) begin : GENSTOP
mult2 #(.SW(SW))
inst_mult (
.DatA(Data_A_i),
.DatB(Data_B_i),
.DatO(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW(SW/2)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW((SW/2)+1)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW((SW/2)+1)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW(SW/2+2)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; long long dp[101][101][11][2]; long long k1, k2; long long solve(long long n1, long long n2, long long count, long long flag) { if (n1 < 0 || n2 < 0) { return 0; } if (n1 == 0 && n2 == 0) { return 1; } if (flag != -1 && dp[n1][n2][count][flag] != -1) { return dp[n1][n2][count][flag]; } long long i; long long ans = 0; if (flag != 1) { for (i = 1; i <= k2; i++) { ans += solve(n1, n2 - i, i, 1); ans %= (long long)1e8; } } if (flag != 0) { for (i = 1; i <= k1; i++) { ans += solve(n1 - i, n2, i, 0); ans %= (long long)1e8; } } if (flag != -1) dp[n1][n2][count][flag] = ans; return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n1, n2; cin >> n1 >> n2 >> k1 >> k2; memset(dp, -1, sizeof(dp)); cout << solve(n1, n2, 0, -1); return 0; }
|
`include "senior_defines.vh"
module register_file
#(parameter ctrl_w = `RF_CTRL_WIDTH,
parameter nat_w = `SENIOR_NATIVE_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire [nat_w-1:0] pass_through_dat_i,
input wire [ctrl_w-1:0] ctrl_i,
input wire [nat_w-1:0] dat_i,
input wire [nat_w-1:0] dm_dat_i,
input wire register_enable_i,
output reg [nat_w-1:0] dat_a_o,
output reg [nat_w-1:0] dat_b_o
);
reg [nat_w-1:0] theRF [31:0];
wire [nat_w-1:0] out_a;
wire [nat_w-1:0] out_b;
// Internal Declarations
always@(posedge clk_i) begin
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN) begin
theRF[ctrl_i`RF_WRITE_REG_SEL] <= dat_i;
end
if(register_enable_i && ctrl_i`RF_WRITE_REG_EN_DM &&
ctrl_i`RF_WRITE_REG_SEL != ctrl_i`RF_WRITE_REG_SEL_DM) begin
theRF[ctrl_i`RF_WRITE_REG_SEL_DM] <= dm_dat_i;
end
end
wire [5:0] ctrl_i_opa;
wire [5:0] ctrl_i_opb;
assign ctrl_i_opa = ctrl_i`RF_OPA;
assign ctrl_i_opb = ctrl_i`RF_OPB;
assign out_a = theRF[ctrl_i_opa[4:0]];
assign out_b = theRF[ctrl_i_opb[4:0]];
// output logic
// mux for operand A
always @(*) begin
case (ctrl_i_opa[5])
1'b0: dat_a_o=out_a;
1'b1: dat_a_o=pass_through_dat_i;
endcase // case(id_rf_opa_sel_i[5])
end
// mux for operand B
always@(*) begin
case (ctrl_i_opb[5])
1'b0: dat_b_o=out_b;
1'b1: dat_b_o=pass_through_dat_i;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string cad; cin >> n >> cad; int res = 0; for (int i = 0; i < n; ++i) { if (cad[i] == 0 ) { res++; break; } else { res++; } } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p = 0, q = 0; cin >> n; string str; cin >> str; for (int i = 0; i < n; i++) { if (str[i] == F && str[i + 1] == S ) p = p + 1; if (str[i] == S && str[i + 1] == F ) q = q + 1; } if (q > p) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void inp_out() {} int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); inp_out(); long long int n, m; cin >> n >> m; vector<pair<long long int, long long int>> a(n); long long int cnt = 0; multiset<pair<long long int, long long int>> st; vector<multiset<long long int>> adj(m + 1); for (long long int i = 0; i < n; ++i) { cin >> a[i].first >> a[i].second; adj[a[i].first].insert(a[i].second); if (a[i].first == 1) ++cnt; else st.insert({a[i].second, a[i].first}); } vector<long long int> ans(n + 1, 3e18); for (long long int i = max(1ll, cnt); i <= n; ++i) { vector<multiset<long long int>> temp_adj = adj; multiset<pair<long long int, long long int>> temp_st = st; long long int val = cnt, cost = 0; for (long long int j = 2; j <= m; ++j) { while (temp_adj[j].size() >= i) { cost += *temp_adj[j].begin(); temp_st.erase(temp_st.find({*temp_adj[j].begin(), j})); temp_adj[j].erase(temp_adj[j].begin()); ++val; } } if (val > i) continue; while (val < i) { cost += (*temp_st.begin()).first; temp_st.erase(temp_st.begin()); ++val; } ans[i] = cost; } long long int fa = *min_element(ans.begin(), ans.end()); cout << fa; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 17:39:32 03/02/2016
// Design Name:
// Module Name: Modificacion_Frec_Conmu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Modificacion_Frec_Conmu
(
input wire CLK_100MHz,
input wire aumentar_Frec,
input wire disminuir_Frec,
input wire funct_select,
input wire reset,
output wire CLK_dividido,
output wire CLK_1kHz,
output wire [3:0] OutContadorAD_InMDF //Conexiones entre contador y bloque MDF (traductor y divisor de clock), también para la FSM
);
wire OutRegistroAumentar_InContadorADAumentar; //Conexiones entre registro y contador A/D
wire OutRegistroDisminuir_InContadorADDisminuir;
Registro_Universal Instancia_Registro_Universal(
.aumentar(aumentar_Frec), //boton aumentar
.disminuir(disminuir_Frec), //boton disminuir
.clk(CLK_100MHz), //system clock
.reset(reset), //system reset
.chip_select(~funct_select), //Control data (funct_select)
.out_aumentar(OutRegistroAumentar_InContadorADAumentar), //boton aumentar
.out_disminuir(OutRegistroDisminuir_InContadorADDisminuir) //boton disminuir
);
Contador_Ascendente_Descendente Instancia_Contador_Ascendente_Descendente(
.clk(CLK_100MHz),
.reset(reset),
.enUP(OutRegistroAumentar_InContadorADAumentar),
.enDOWN(OutRegistroDisminuir_InContadorADDisminuir),
.q(OutContadorAD_InMDF)
);
MDF Instancia_MDF(
.clk(CLK_100MHz),
.rst(reset),
.entrada(OutContadorAD_InMDF),
.salida(CLK_dividido),
.salida_1kHz(CLK_1kHz),
.q()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double EPS = 0.0000001; const double PI = acos(-1); const long long INFLL = 0x7FFFFFFFFFFFFFFF; const int INF = 0x7FFFFFFF; template <typename T> inline void next(T &num) { char c; num = 0; do { c = getchar_unlocked(); } while (c != EOF && c == && c == n && c == t ); int sign = (c == - ? -1 : 1); if (c != - ) num += (c - 0 ); while ((c = getchar_unlocked()) != EOF && c != n && c != t && c != ) { num *= 10; num += (c - 0 ); } num *= sign; } inline string getstr() { string str; char k; while ((k = getchar_unlocked()) == || k == n ) { k = getchar_unlocked(); if (k == || k == n ) continue; else break; } str.push_back(k); while ((k = getchar_unlocked()) != EOF && k != n && k != t && k != v && k != 0 && k != ) str.push_back(k); return str; } const int M = 50005; long long n, a[M]; long long ans; void dfs(long long n, int p, long long now) { if (now > ans) return; if (!n) { ans = min(ans, now); return; } if (!p) return; int need = n / a[p]; dfs(n - need * a[p], p - 1, now + p * need); dfs((need + 1) * a[p] - n, p - 1, now + p * (need + 1)); } int main() { cin >> n; for (int i = int(1), _b = int(16); i <= _b; i++) a[i] = a[i - 1] * 10 + 1; ans = n; dfs(n, 16, 0); cout << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1010, max_range = 1000001; int edge[maxn][3 * maxn], reached[maxn], start[3 * maxn], len[3 * maxn], vert[3 * maxn][2], n, m, res; FILE *in; int nb(int v, int e) { if (vert[e][0] == v) return vert[e][1]; else return vert[e][0]; } int dfs(int sz, int x, int v) { reached[v] = 1; if (v == n) return 1; int e, u; for (int i = 1; i <= edge[v][0]; i++) { e = edge[v][i]; u = nb(v, e); if (reached[u] == 0 && x >= start[e] && x - start[e] <= len[e] - sz) { if (dfs(sz, x, u) == 1) return 1; } } return 0; } bool check(int sz) { int res = 0; for (int i = 1; i <= m; i++) if (len[i] >= sz) { memset(reached, 0, sizeof(reached)); res = dfs(sz, start[i], 1); if (res == 1) break; } return res == 1; } void init() { int x, y, l, r; fscanf(in, %d %d , &n, &m); for (int i = 1; i <= m; i++) { fscanf(in, %d %d %d %d , &x, &y, &l, &r); edge[x][0]++; edge[x][edge[x][0]] = i; edge[y][0]++; edge[y][edge[y][0]] = i; start[i] = l; len[i] = r - l + 1; vert[i][0] = x; vert[i][1] = y; } } int solve() { int l = 0, r = max_range, s = (l + r) / 2; while (r - l > 1) { if (check(s)) l = s; else r = s; s = (l + r) / 2; } return s; } int main() { in = stdin; init(); res = solve(); if (res == 0) printf( Nice work, Dima! n ); else printf( %d , res); return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; long long a[101], b[101]; int main() { long long i, j, k, l, n, c, m, x, y, lft, rgt, p, q; cin >> n; for (i = 0; i < 2 * n; i++) { cin >> a[i]; } sort(a, a + 2 * n); c = 0; p = 0; long long mnm = 1267357834; for (i = 0; i < 2 * n; i++) { if (i > 0) { p = 0; for (j = 0; j < i; j++) { b[p++] = a[j]; } } for (j = i + 1; j < 2 * n; j++) { q = p; for (k = i + 1; k < 2 * n; k++) { if (k != j) { b[q++] = a[k]; } } long long x = 0; for (k = 0; k < q; k += 2) { x += abs(b[k] - b[k + 1]); } mnm = min(mnm, x); } } cout << mnm << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_SYMBOL_V
`define SKY130_FD_SC_LS__A222O_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
input C2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_SYMBOL_V
|
`include "mux.v"
module HalfAdder(input a,b, output sum, carry);
Xor g1(a, b, sum);
And g2(a, b, carry);
endmodule
module FullAdder(input a,b,c, output sum, carry);
wire s1, c1, c2;
Xor g1(a, b, s1);
Xor g2(s1, c, sum);
And g3(a, b, c1);
And g4(s1, c, c2);
Xor g5(c2, c1, carry);
endmodule
module Add16(input[15:0] a,b, output[15:0] out);
wire [15:0] c;
FullAdder g01(a[0], b[0], 1'b0, out[0], c[0]);
FullAdder g02(a[1], b[1], c[0], out[1], c[1]);
FullAdder g03(a[2], b[2], c[1], out[2], c[2]);
FullAdder g04(a[3], b[3], c[2], out[3], c[3]);
FullAdder g05(a[4], b[4], c[3], out[4], c[4]);
FullAdder g06(a[5], b[5], c[4], out[5], c[5]);
FullAdder g07(a[6], b[6], c[5], out[6], c[6]);
FullAdder g08(a[7], b[7], c[6], out[7], c[7]);
FullAdder g09(a[8], b[8], c[7], out[8], c[8]);
FullAdder g10(a[9], b[9], c[8], out[9], c[9]);
FullAdder g11(a[10], b[10], c[9], out[10], c[10]);
FullAdder g12(a[11], b[11], c[10], out[11], c[11]);
FullAdder g13(a[12], b[12], c[11], out[12], c[12]);
FullAdder g14(a[13], b[13], c[12], out[13], c[13]);
FullAdder g15(a[14], b[14], c[13], out[14], c[14]);
FullAdder g16(a[15], b[15], c[14], out[15], c[15]);
endmodule
module Inc16(input[15:0] in, output[15:0] out);
Add16 g1(in, 16'h1, out);
endmodule
// x[16], y[16], // 16-bit inputs
// zx, // zero the x input?
// nx, // negate the x input?
// zy, // zero the y input?
// ny, // negate the y input?
// f, // compute out = x + y (if 1) or x & y (if 0)
// no; // negate the out output?
// out[16], zr, ng; // zr:zero, ng:negative
module ALU(input[15:0] x, y, input zx,nx,zy,ny,f,no, output[15:0] out, output zr, ng);
wire[15:0] x1, notx1, x2, y1, noty1, y2, andxy, addxy, o1, noto1, o2;
wire orLow, orHigh, notzr;
Mux16 g1(x, 16'b0, zx, x1); // if (zx == 1) set x = 0
Not16 g2(x1, notx1);
Mux16 g3(x1, notx1, nx, x2); // if (nx == 1) set x = !x
Mux16 g4(y, 16'b0, zy, y1); // if (zy == 1) set y = 0
Not16 g5(y1, noty1);
Mux16 g6(y1, noty1, ny, y2); // if (ny == 1) set y = !y
Add16 g7(x2, y2, addxy); // addxy = x + y
And16 g8(x2, y2, andxy); // andxy = x & y
Mux16 g9(andxy, addxy, f, o1); // if (f == 1) set out = x + y else set out = x & y
Not16 g10(o1, noto1);
Mux16 g11(o1, noto1, no, o2); // if (no == 1) set out = !out
// o2 就是 out, 但必須中間節點才能再次當作輸入，所以先用 o2。
And16 g12(o2, o2, out);
Or8Way g13(out[7:0], orLow); // orLow = Or(out[0..7]);
Or8Way g14(out[15:8], orHigh);// orHigh = Or(out[8..15]);
Or g15(orLow, orHigh, notzr); // nzr = Or(out[0..15]);
Not g16(notzr, zr); // zr = !nzr
And g17(o2[15], o2[15], ng); // ng = out[15]
And16 g18(o2, o2, out);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> const int N = 100001; int Pri[200005]; int NN, Cnt[100005], Mac[100005]; bool Use[200005]; void GetPrimeList() { int TmpN = sqrt(N); for (int i = 2; i <= N; ++i) Use[i] = true; for (int i = 2; i <= N; ++i) { if (Use[i]) Pri[++Pri[0]] = i; for (int j = 1; j <= Pri[0] && i * Pri[j] <= N; ++j) { Use[i * Pri[j]] = false; if (i % Pri[j] == 0) break; } if (i <= TmpN) NN = Pri[0]; } ++NN; for (int i = 1; i <= N; ++i) Use[i] = false; } int Add(int x) { int t = x; for (int i = 1; i <= NN; ++i) if (t % Pri[i] == 0) { if (Cnt[Pri[i]] != 0) return Mac[Pri[i]]; for (; t % Pri[i] == 0; t /= Pri[i]) ; } if (t != 1 && Cnt[t] != 0) return Mac[t]; t = x; for (int i = 1; i <= NN; ++i) if (t % Pri[i] == 0) { ++Cnt[Pri[i]]; Mac[Pri[i]] = x; for (; t % Pri[i] == 0; t /= Pri[i]) ; } if (t != 1) { ++Cnt[t]; Mac[t] = x; } Use[x] = true; return -1; } void Del(int x) { int t = x; for (int i = 1, j, k; i <= NN; ++i) if (t % Pri[i] == 0) { --Cnt[Pri[i]]; Mac[Pri[i]] = 0; for (; t % Pri[i] == 0; t /= Pri[i]) ; } if (t != 1) { --Cnt[t]; Mac[t] = 0; } Use[x] = false; } int main() { GetPrimeList(); int n, m, num; char op; scanf( %d %d n , &n, &m); for (int i = 1, ret; i <= m; ++i) { scanf( %c %d n , &op, &num); if (op == + ) { if (Use[num]) puts( Already on ); else { ret = Add(num); if (ret == -1) puts( Success ); else printf( Conflict with %d n , ret); } } else { if (!Use[num]) puts( Already off ); else { Del(num); puts( Success ); } } } return 0; }
|
//========================================================================
// Verilog Components: Registers
//========================================================================
// Note that we place the register output earlier in the port list since
// this is one place we might actually want to use positional port
// binding like this:
//
// wire [p_nbits-1:0] result_B;
// vc_Reg#(p_nbits) result_AB( clk, result_B, result_A );
`ifndef VC_REGS_V
`define VC_REGS_V
`include "vc-assert.v"
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop
//------------------------------------------------------------------------
module vc_Reg
#(
parameter p_nbits = 1
)(
input clk, // Clock input
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d // Data input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
q <= d;
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop
//------------------------------------------------------------------------
// Just a copy of vc_Reg used for testing explicit module names
module vc_RegExplicitModuleName
#(
parameter p_nbits = 1
)(
input clk, // Clock input
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d // Data input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
q <= d;
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with reset
//------------------------------------------------------------------------
module vc_ResetReg
#(
parameter p_nbits = 1,
parameter p_reset_value = 0
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d // Data input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
q <= reset ? p_reset_value : d;
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with enable
//------------------------------------------------------------------------
module vc_EnReg
#(
parameter p_nbits = 1
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d, // Data input (sampled on rising clk edge)
input en // Enable input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
if ( en )
q <= d;
// Assertions
always @( posedge clk )
if ( !reset )
`VC_ASSERT_NOT_X( en );
endmodule
//------------------------------------------------------------------------
// Postive-edge triggered flip-flop with enable and reset
//------------------------------------------------------------------------
module vc_EnResetReg
#(
parameter p_nbits = 1,
parameter p_reset_value = 0
)(
input clk, // Clock input
input reset, // Sync reset input (sampled on rising edge)
output [p_nbits-1:0] q, // Data output
input [p_nbits-1:0] d, // Data input (sampled on rising clk edge)
input en // Enable input (sampled on rising clk edge)
);
reg q;
always @( posedge clk )
if ( reset || en )
q <= reset ? p_reset_value : d;
// Assertions
always @( posedge clk )
if ( !reset )
`VC_ASSERT_NOT_X( en );
endmodule
`endif /* VC_REGS_V */
|
#include <bits/stdc++.h> int main() { int m, n; scanf( %d %d , &n, &m); if (n == 1) { if (m == 2) { printf( 0 n ); printf( 1 1 n ); printf( 1 2 n ); printf( 1 1 n ); return 0; } else { printf( 1 n ); printf( 1 %d 1 1 n , m); for (int i = 1; i <= m; ++i) printf( 1 %d n , i); printf( 1 1 n ); } } else if (m == 1) { if (n == 2) { printf( 0 n ); printf( 1 1 n ); printf( 2 1 n ); printf( 1 1 n ); return 0; } else { printf( 1 n ); printf( %d 1 1 1 n , n); for (int i = 1; i <= n; ++i) printf( %d 1 n , i); printf( 1 1 n ); } } else if (n % 2 == 0) { printf( 0 n ); for (int i = 1; i <= n; ++i) printf( %d 1 n , i); bool direita = true; for (int lin = n; lin >= 1; --lin) { if (direita) { for (int j = 2; j <= m; ++j) printf( %d %d n , lin, j); } else { for (int j = m; j > 1; --j) printf( %d %d n , lin, j); } direita = !direita; } printf( 1 1 n ); } else if (m % 2 == 0) { printf( 0 n ); for (int j = 1; j <= m; ++j) printf( 1 %d n , j); bool baixo = true; for (int col = m; col >= 1; --col) { if (baixo) { for (int i = 2; i <= n; ++i) printf( %d %d n , i, col); } else { for (int i = n; i > 1; --i) printf( %d %d n , i, col); } baixo = !baixo; } printf( 1 1 n ); } else { printf( 1 n ); printf( %d %d 1 1 n , n, m); bool direita = true; for (int i = 1; i <= n; ++i) { if (direita) { for (int j = 1; j <= m; ++j) printf( %d %d n , i, j); } else { for (int j = m; j >= 1; --j) printf( %d %d n , i, j); } direita = !direita; } printf( 1 1 n ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, p; string s, x, y; cin >> n; cin.ignore(); while (n--) { getline(cin, s); a = 0; b = 0; p = s.length(); if (s[0] == m && s[1] == i && s[2] == a && s[3] == o && s[4] == . ) { a = 1; } if (s[p - 1] == . && s[p - 2] == a && s[p - 3] == l && s[p - 4] == a && s[p - 5] == l ) { b = 1; } if (a == 1 && b == 1) { cout << OMG>.< I don t know! << endl; continue; } if (a == 1) { cout << Rainbow s << endl; continue; } if (b == 1) { cout << Freda s << endl; continue; } cout << OMG>.< I don t know! << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int num[3]; cin >> num[0] >> num[1] >> num[2]; char c1 = * , c2 = * ; if (num[0] == 1) c1 = + ; if (num[2] == 1) c2 = + ; if (num[1] == 1 && num[0] != 1 && num[2] != 1) { cout << max(num[0] * (num[1] + num[2]), (num[0] + num[1]) * num[2]); return 0; } if (c1 == + && c2 == * ) { cout << ((num[0] + num[1]) * num[2]); return 0; } if (c2 == + && c1 == * ) { cout << (num[0] * (num[1] + num[2])); return 0; } if (c1 == + && c2 == + ) { cout << (num[0] + num[1] + num[2]); return 0; } cout << (num[0] * num[1] * num[2]); return 0; }
|
module top;
int q_tst [$];
int q_tmp [$];
int elem;
integer idx;
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1'b0;
end
endtask
task automatic check_idx_value(integer idx,
int expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %0d (%0d)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1'b0;
end
endtask
initial begin
passed = 1'b1;
q_tst.delete(0); // Warning: skip delete on an empty queue
check_size(0, `__FILE__, `__LINE__);
check_idx_value(0, 0, `__FILE__, `__LINE__);
elem = q_tst.pop_front(); // Warning: cannot pop_front() an empty queue
if (elem !== 'X) begin
$display("Failed: pop_front() != 'X (%0d)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back(); // Warning: cannot pop_back() an empty queue
if (elem !== 'X) begin
$display("Failed: pop_back() != 'X (%0d)", elem);
passed = 1'b0;
end
q_tst.push_back(2);
q_tst.push_front(1);
q_tst.push_back(3);
q_tst.push_back(100);
q_tst.delete(3); // Should $ work here?
q_tst.delete(3); // Warning: skip an out of range delete()
q_tst.delete(-1); // Warning: skip delete with negative index
q_tst.delete('X); // Warning: skip delete with undefined index
check_size(3, `__FILE__, `__LINE__);
if (q_tst[0] !== 1) begin
$display("Failed: element [0] != 1 (%0d)", q_tst[0]);
passed = 1'b0;
end
if (q_tst[1] !== 2) begin
$display("Failed: element [1] != 2 (%0d)", q_tst[1]);
passed = 1'b0;
end
if (q_tst[2] !== 3) begin
$display("Failed: element [2] != 3 (%0d)", q_tst[2]);
passed = 1'b0;
end
if (q_tst[3] !== 'X) begin
$display("Failed: element [3] != 'X (%0d)", q_tst[3]);
passed = 1'b0;
end
if (q_tst[-1] !== 'X) begin
$display("Failed: element [-1] != 'X (%0d)", q_tst[-1]);
passed = 1'b0;
end
if (q_tst['X] !== 'X) begin
$display("Failed: element ['X] != 'X (%0d)", q_tst['X]);
passed = 1'b0;
end
check_idx_value(-1, 0.0, `__FILE__, `__LINE__);
check_idx_value('X, 0.0, `__FILE__, `__LINE__);
elem = q_tst.pop_front();
if (elem !== 1) begin
$display("Failed: element pop_front() != 1 (%0d)", elem);
passed = 1'b0;
end
elem = q_tst.pop_back();
if (elem !== 3) begin
$display("Failed: element pop_back() != 3 (%0d)", elem);
passed = 1'b0;
end
check_size(1, `__FILE__, `__LINE__);
if ((q_tst[0] !== q_tst[$]) || (q_tst[0] !== 2)) begin
$display("Failed: q_tst[0](%0d) != q_tst[$](%0d) != 2",
q_tst[0], q_tst[$]);
passed = 1'b0;
end
q_tst.delete();
check_size(0, `__FILE__, `__LINE__);
q_tst.push_front(5);
q_tst.push_front(100);
q_tst.push_back(100);
elem = q_tst.pop_back;
elem = q_tst.pop_front;
check_size(1, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
q_tst[0] = 1;
q_tst[1] = 3;
q_tst[1] = 2;
q_tst[2] = 3;
q_tst[-1] = 10; // Warning: will not be added (negative index)
q_tst['X] = 10; // Warning: will not be added (undefined index)
q_tst[4] = 10; // Warning: will not be added (out of range index)
idx = -1;
q_tst[idx] = 10; // Warning: will not be added (negative index)
idx = 3'b0x1;
q_tst[idx] = 10; // Warning: will not be added (undefined index)
idx = 4;
q_tst[idx] = 10; // Warning: will not be added (out of range index)
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst.delete();
q_tst[0] = 2;
q_tst.insert(1, 4);
q_tst.insert(0, 1);
q_tst.insert(2, 3);
q_tst.insert(-1, 10); // Warning: will not be added (negative index)
q_tst.insert('X, 10); // Warning: will not be added (undefined index)
q_tst.insert(5, 10); // Warning: will not be added (out of range index)
check_size(4, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
check_idx_value(3, 4, `__FILE__, `__LINE__);
q_tst = '{3, 2, 1};
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 3, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 1, `__FILE__, `__LINE__);
q_tmp = '{1, 2};
q_tst = q_tmp;
q_tmp[0] = 3;
q_tmp[2] = 1;
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1.0, `__FILE__, `__LINE__);
check_idx_value(1, 2.0, `__FILE__, `__LINE__);
q_tst[2] = 3;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst = {1, 2};
check_size(2, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
q_tst = '{};
check_size(0, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; cout << 0 << << 0 << << n; return 0; }
|
#include <bits/stdc++.h> using namespace std; class Node { public: Node *prev, *next; int k; Node(int K) { k = K; prev = next = NULL; }; void insert(int K) { Node *n = new Node(K); n->prev = this; if (this->next == NULL) this->next = n; else { Node *t = this->next; this->next = n; n->next = t; t->prev = n; } }; void insertBack(int K) { Node *n = new Node(K); n->next = this; if (this->prev == NULL) this->prev = n; else { Node *t = this->prev; this->prev = n; n->prev = t; t->next = n; } }; void del() { Node *p = this->prev, *n = this->next; if (p) p->next = n; if (n) n->prev = p; delete this; }; void delNext() { if (this->next) this->next->del(); }; }; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T; cin >> T; while (T) { T--; string s; cin >> s; Node *head = new Node(s[0] - 0 ); Node *curr = head; for (int i = 1; i < s.size(); i++) { curr->insert(s[i] - 0 ); curr = curr->next; } curr = head->next; Node *cache = head; while (curr) { if (cache->k % 2 != curr->k % 2) { while (cache->k < curr->k) cache = cache->next; if (cache == curr) { curr = curr->next; continue; } cache->insertBack(curr->k); if (curr->next) { curr = curr->next; curr->prev->del(); } else { curr = curr->prev; curr->next->del(); curr = NULL; } } else { curr = curr->next; } } while (cache->prev) cache = cache->prev; while (cache) { cout << cache->k; cache = cache->next; if (cache && cache->prev) cache->prev->del(); } cout << endl; } return 0; }
|
/*
* schoolMIPS - small MIPS CPU for "Young Russian Chip Architects"
* summer school ( )
*
* originally based on Sarah L. Harris MIPS CPU
*
* Copyright(c) 2017 Stanislav Zhelnio
* Aleksandr Romanov
*/
`include "sm_cpu.vh"
module sm_cpu
(
input clk, // clock
input rst_n, // reset
input [ 4:0] regAddr, // debug access reg address
output [31:0] regData, // debug access reg data
output [31:0] imAddr, // instruction memory address
input [31:0] imData // instruction memory data
);
//control wires
wire pcSrc;
wire regDst;
wire regWrite;
wire aluSrc;
wire aluZero;
wire [ 2:0] aluControl;
//program counter
wire [31:0] pc;
wire [31:0] pcBranch;
wire [31:0] pcNext = pc + 1;
wire [31:0] pc_new = ~pcSrc ? pcNext : pcBranch;
sm_register r_pc(clk ,rst_n, pc_new, pc);
//program memory access
assign imAddr = pc;
wire [31:0] instr = imData;
//debug register access
wire [31:0] rd0;
assign regData = (regAddr != 0) ? rd0 : pc;
//register file
wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16];
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instr[25:21] ),
.a2 ( instr[20:16] ),
.a3 ( a3 ),
.rd0 ( rd0 ),
.rd1 ( rd1 ),
.rd2 ( rd2 ),
.wd3 ( wd3 ),
.we3 ( regWrite )
);
//sign extension
wire [31:0] signImm = { {16 { instr[15] }}, instr[15:0] };
assign pcBranch = pcNext + signImm;
//alu
wire [31:0] srcB = aluSrc ? signImm : rd2;
sm_alu alu
(
.srcA ( rd1 ),
.srcB ( srcB ),
.oper ( aluControl ),
.shift ( instr[10:6 ] ),
.zero ( aluZero ),
.result ( wd3 )
);
//control
sm_control sm_control
(
.cmdOper ( instr[31:26] ),
.cmdFunk ( instr[ 5:0 ] ),
.aluZero ( aluZero ),
.pcSrc ( pcSrc ),
.regDst ( regDst ),
.regWrite ( regWrite ),
.aluSrc ( aluSrc ),
.aluControl ( aluControl )
);
endmodule
module sm_control
(
input [5:0] cmdOper,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output reg regDst,
output reg regWrite,
output reg aluSrc,
output reg [2:0] aluControl
);
reg branch;
reg condZero;
assign pcSrc = branch & (aluZero == condZero);
always @ (*) begin
branch = 1'b0;
condZero = 1'b0;
regDst = 1'b0;
regWrite = 1'b0;
aluSrc = 1'b0;
aluControl = `ALU_ADD;
casez( {cmdOper,cmdFunk} )
default : ;
{ `C_SPEC, `F_ADDU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end
{ `C_SPEC, `F_OR } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end
{ `C_SPEC, `F_SRL } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end
{ `C_SPEC, `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
{ `C_SPEC, `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
{ `C_ADDIU, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end
{ `C_LUI, `F_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end
{ `C_BEQ, `F_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BNE, `F_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
endcase
end
endmodule
module sm_alu
(
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
always @ (*) begin
case (oper)
default : result = srcA + srcB;
`ALU_ADD : result = srcA + srcB;
`ALU_OR : result = srcA | srcB;
`ALU_LUI : result = (srcB << 16);
`ALU_SRL : result = srcB >> shift;
`ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU : result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule
module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf [31:0];
assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
always @ (posedge clk)
if(we3) rf [a3] <= wd3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCON_BLACKBOX_V
`define SKY130_FD_SC_HS__FAHCON_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCON_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; double dp[105][105][105][3] = {{{{0}}}}; bool used[105][105][105] = {{{0}}}; void f(int a, int b, int c) { if (used[a][b][c]) return; ; used[a][b][c] = 1; if (a == 0) dp[a][b][c][1] = 1; else if (b == 0) dp[a][b][c][2] = 1; else if (c == 0) dp[a][b][c][0] = 1; else { f(a - 1, b, c); f(a, b - 1, c); f(a, b, c - 1); int tmp = a * b + b * c + c * a; for (int i = 0; i < (3); i++) { dp[a][b][c][i] = dp[a - 1][b][c][i] * a * c / tmp + dp[a][b - 1][c][i] * a * b / tmp + dp[a][b][c - 1][i] * b * c / tmp; } }; return; } int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); f(a, b, c); printf( %.9f %.9f %.9f n , dp[a][b][c][0], dp[a][b][c][1], dp[a][b][c][2]); return 0; }
|
#include <bits/stdc++.h> using namespace std::chrono; using namespace std; const long long int mod = 998244353; const int inf = 1e9 + 7; long long int f(long long int x, long long int n) { long long int r = 1; while (n > 0) { if (n % 2 == 1) r = (r * x) % mod; x = (x * x) % mod; n /= 2; } return r; } long long int fac[400010], invf[400010]; void buildfactorial() { fac[0] = 1; fac[1] = 1; for (int i = 2; i < 400010; i++) fac[i] = ((long long int)i * fac[i - 1]) % mod; for (int i = 0; i < 400010; ++i) { invf[i] = f(fac[i], mod - 2); } } long long int C(int n, int r) { if (n < r) return 0; return (((fac[n] * invf[r]) % mod) * invf[n - r]) % mod; } long double dist(long double x1, long double y1, long double x2, long double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } struct node { int v, d, p; }; void solve() { int n; cin >> n; string s[n]; for (int i = 0; i < n; ++i) cin >> s[i]; for (int i = n - 2; i >= 0; --i) { string t = ; for (int j = 0; j < min(s[i].length(), s[i + 1].length()); ++j) { if (s[i][j] > s[i + 1][j]) break; else if (s[i][j] < s[i + 1][j]) { t = s[i]; break; } t += s[i][j]; } s[i] = t; } for (int i = 0; i < n; ++i) cout << s[i] << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) solve(); }
|
`timescale 1ns/1ps
module DdrCtl1Sim;
reg clock0;
reg clock90;
reg clock2x0;
reg clock2x90;
reg clock2x180;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [31:0] page;
wire ready;
wire ddrctl_ddr_cke;
wire ddrctl_ddr_csn;
wire ddrctl_ddr_rasn;
wire ddrctl_ddr_casn;
wire ddrctl_ddr_wen;
wire [1:0] ddrctl_ddr_ba;
wire [12:0] ddrctl_ddr_addr;
wire [1:0] ddrctl_ddr_dm;
wire [15:0] ddrctl_ddr_dq;
wire [1:0] ddrctl_ddr_dqs;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#500000 $finish;
end
initial begin
#0 clock0 = 1;
forever #10 clock0 = ~clock0;
end
initial begin
#5 clock90 = 1;
forever #10 clock90 = ~clock90;
end
initial begin
#0 clock2x0 = 1;
forever #5 clock2x0 = ~clock2x0;
end
initial begin
#2.5 clock2x90 = 1;
forever #5 clock2x90 = ~clock2x90;
end
initial begin
#5 clock2x180 = 1;
forever #5 clock2x180 = ~clock2x180;
end
initial begin
#0 reset = 0;
#60 reset = 1;
#40 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
# 204615 inst = {`DdrCtl1_LA0,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA1,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA2,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA3,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LD0,8'hAA};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hBB};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hCC};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hDD};
inst_en = 1;
#20 inst = {`DdrCtl1_WRP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
#180 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
#5500 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
// // Test disabled instruction.
// #240 inst = {`DdrCtl1_LD1,8'h0A};
// inst_en = 0;
// #20 inst = {`DdrCtl1_LD1,8'h01};
// inst_en = 1;
// // // Test bad instruction.
// // // #20 inst = {8'hF,8'h10};
// // // inst_en = 1;
// // // #20 inst = {`DdrCtl1_LD2,8'hA0};
// // // inst_en = 1;
// // // #40 reset = 1;
// // // #80 reset = 0;
// // // #20 inst = {`DdrCtl1_LD2,8'hAB};
// // // inst_en = 1;
// // // #20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
// // // inst_en = 1;
// // Test writing to another bank.
#200 inst = {`DdrCtl1_LA0,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA1,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA2,8'h00};
inst_en = 1;
#20 inst = {`DdrCtl1_LA3,8'h01};
inst_en = 1;
#20 inst = {`DdrCtl1_LD0,8'hEE};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hFF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'h11};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'h22};
inst_en = 1;
#20 inst = {`DdrCtl1_WRP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#200 inst = {`DdrCtl1_LD0,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD1,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD2,8'hEF};
inst_en = 1;
#20 inst = {`DdrCtl1_LD3,8'hEF};
inst_en = 1;
#180 inst = {`DdrCtl1_RDP,8'bxxxxxxxx};
inst_en = 1;
#20 inst = {`DdrCtl1_NOP,8'bxxxxxxxx};
inst_en = 1;
#20 inst_en = 0;
end // initial begin
Ddr
ddr (.Clk(clock2x0),
.Clk_n(clock2x180),
.Cke(ddrctl_ddr_cke),
.Cs_n(ddrctl_ddr_csn),
.Ras_n(ddrctl_ddr_rasn),
.Cas_n(ddrctl_ddr_casn),
.We_n(ddrctl_ddr_wen),
.Ba(ddrctl_ddr_ba),
.Addr(ddrctl_ddr_addr),
.Dm(ddrctl_ddr_dm),
.Dq(ddrctl_ddr_dq),
.Dqs(ddrctl_ddr_dqs));
DdrCtl1
ddrctl (.clock0(clock0),
.clock90(clock90),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.page(page),
.ready(ready),
.ddr_clock0(clock2x0),
.ddr_clock90(clock2x90),
.ddr_cke(ddrctl_ddr_cke),
.ddr_csn(ddrctl_ddr_csn),
.ddr_rasn(ddrctl_ddr_rasn),
.ddr_casn(ddrctl_ddr_casn),
.ddr_wen(ddrctl_ddr_wen),
.ddr_ba(ddrctl_ddr_ba),
.ddr_addr(ddrctl_ddr_addr),
.ddr_dm(ddrctl_ddr_dm),
.ddr_dq(ddrctl_ddr_dq),
.ddr_dqs(ddrctl_ddr_dqs));
endmodule // DdrCtl1Sim
|
module AUDIO_ADC(
// host
clk,
reset,
read,
readdata,
//available,
empty,
clear,
// dac
bclk,
adclrc,
adcdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input read;
output [(DATA_WIDTH-1):0] readdata;
output empty;
input clear;
input bclk;
input adclrc;
input adcdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
reg [4:0] bit_index; //0~31
reg valid_bit;
reg reg_adc_left;
reg [(DATA_WIDTH-1):0] reg_adc_serial_data;
reg [(DATA_WIDTH-1):0] adcfifo_writedata;
reg adcfifo_write;
wire adcfifo_full;
reg wait_one_clk;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//===== Serialize data (I2S) to ADC-FIFO =====
wire is_left_ch;
assign is_left_ch = ~adclrc;
always @ (posedge bclk)
begin
if (reset || clear)
begin
bit_index = DATA_WIDTH;
reg_adc_left = is_left_ch;
adcfifo_write = 1'b0;
valid_bit = 0;
end
else
begin
if (adcfifo_write)
adcfifo_write = 1'b0; // disable write at second cycle
if (reg_adc_left ^ is_left_ch)
begin // channel change
reg_adc_left = is_left_ch;
valid_bit = 1'b1;
wait_one_clk = 1'b1;
if (reg_adc_left)
bit_index = DATA_WIDTH;
end
// serial bit to adcfifo
if (valid_bit && wait_one_clk)
wait_one_clk = 1'b0;
else if (valid_bit && !wait_one_clk)
begin
bit_index = bit_index - 1'b1;
reg_adc_serial_data[bit_index] = adcdat;
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
begin
if (bit_index == 0 && !adcfifo_full)
begin // write data to adcfifo
adcfifo_writedata = reg_adc_serial_data;
adcfifo_write = 1'b1; // enable write at first cycle
end
valid_bit = 0;
end
end
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo adc_fifo(
// write (adc write to fifo)
.wrclk(bclk),
.wrreq(adcfifo_write),
.data(adcfifo_writedata),
.wrfull(adcfifo_full),
.aclr(clear), // sync with wrclk
// read (host read from fifo)
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdempty(empty)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:07:49 02/26/2016
// Design Name:
// Module Name: Alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Alu(
input [31:0] input1,
input [31:0] input2,
input [3:0] aluCtr,
output reg zero,
output reg [31:0] aluRes
);
always @(input1 or input2 or aluCtr)
begin
case(aluCtr)
'b0000: //AND
begin
aluRes = input1 & input2;
zero = 0;
end
'b0001: //OR
begin
aluRes = input1 | input2;
zero = 0;
end
'b0010: //add
begin
aluRes = input1 + input2;
zero = 0;
end
'b0110: //sub
begin
aluRes = input1 - input2;
if(aluRes == 0)
zero = 1;
else zero = 0;
end
'b0111: //set on less than
begin
zero = 0;
if(input1<input2) //could cause some trouble!!!!!!!!!!
aluRes = 1;
else aluRes = 0;
end
'b1100: //NOR
begin
aluRes = input1 | input2;
aluRes = ~aluRes;
zero = 0;
end
default:
begin
aluRes = 0;
zero = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; const int N = 1005; vector<pair<int, int>> graph[N]; vector<int> ans; int vis[N]; int v[N]; void dfs(int pos) { vis[pos] = 1; v[pos] = 1; for (auto& e : graph[pos]) { if (vis[e.first] == 0) { if (e.second == 0) { int c = max(ans[e.first], ans[pos]); ans[e.first] = c; ans[pos] = c; } else { if (ans[e.first] <= ans[pos]) { ans[e.first] = ans[pos] + 1; } } dfs(e.first); } } vis[pos] = 0; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; while (t--) { int n; cin >> n; string str; cin >> str; int cnt = 1; for (int i = 0; i < n; i++) { ans.push_back(1); } for (int i = 0; i < str.length(); i++) { if (str[i] == = ) { graph[cnt].push_back({cnt - 1, 0}); graph[cnt - 1].push_back({cnt, 0}); } else if (str[i] == L ) { graph[cnt].push_back({cnt - 1, 1}); } else { graph[cnt - 1].push_back({cnt, 1}); } cnt++; } for (int i = 0; i < n; i++) { if (v[i] == 0) { dfs(i); } } for (auto& e : ans) { cout << e << ; } cout << endl; } return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// lvt_reg.v: Register-based binary-coded LVT (Live-Value-Table) //
// //
// Author: Ameer M. Abdelhadi (, ) //
// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module lvt_reg
#( parameter MEMD = 16, // memory depth
parameter nRPORTS = 2 , // number of reading ports
parameter nWPORTS = 2 , // number of writing ports
parameter RDW = 0 , // new data for Read-During-Write
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
parameter IFILE = "" // initialization file, optional
)( input clk , // clock
input [ nWPORTS-1:0] WEnb , // write enable for each writing port
input [`log2(MEMD )*nWPORTS-1:0] WAddr, // write addresses - packed from nWPORTS write ports
input [`log2(MEMD )*nRPORTS-1:0] RAddr, // read addresses - packed from nRPORTS read ports
output [`log2(nWPORTS)*nRPORTS-1:0] RBank); // read bank selector - packed from nRPORTS read ports
localparam ADDRW = `log2(MEMD ); // address width
localparam LVTW = `log2(nWPORTS); // required memory width
// Generate Bank ID's to write into LVT
reg [LVTW*nWPORTS-1:0] WData1D ;
wire [LVTW -1:0] WData2D [nWPORTS-1:0];
genvar gi;
generate
for (gi=0;gi<nWPORTS;gi=gi+1) begin: GenerateID
assign WData2D[gi]=gi;
end
endgenerate
// pack ID's into 1D array
`ARRINIT;
always @* `ARR2D1D(nWPORTS,LVTW,WData2D,WData1D);
mpram_reg #( .MEMD (MEMD ), // memory depth
.DATAW (LVTW ), // data width
.nRPORTS(nRPORTS ), // number of reading ports
.nWPORTS(nWPORTS ), // number of writing ports
.RDW (RDW ), // provide new data when Read-During-Write?
.IZERO (IZERO ), // binary / Initial RAM with zeros (has priority over IFILE)
.IFILE (IFILE )) // initialization file, optional
mpram_reg_ins ( .clk (clk ), // clock - in
.WEnb (WEnb ), // write enable for each writing port - in : [ nWPORTS-1:0]
.WAddr (WAddr ), // write addresses - packed from nWPORTS write ports - in : [ADDRW*nWPORTS-1:0]
.WData (WData1D ), // write data - packed from nRPORTS read ports - in : [LVTW *nWPORTS-1:0]
.RAddr (RAddr ), // read addresses - packed from nRPORTS read ports - in : [ADDRW*nRPORTS-1:0]
.RData (RBank )); // read data - packed from nRPORTS read ports - out: [LVTW *nRPORTS-1:0]
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:29:35 03/29/2015
// Design Name:
// Module Name: regfileparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module regfileparam_behav
#(parameter BITSIZE = 16,
parameter ADDSIZE = 4)
(output [BITSIZE-1:0] adat,
output [BITSIZE-1:0] bdat,
output [BITSIZE-1:0] zeroDat,
input [ADDSIZE-1:0] ra, // Read A Address
input [ADDSIZE-1:0] rb, // Read B Address
input [ADDSIZE-1:0] rw, // Write Address
input [BITSIZE-1:0] wdat,
input wren,
input clk, rst
);
integer i;
reg [BITSIZE-1:0] array_reg [2**ADDSIZE-1:0];
always @(posedge clk, negedge rst) begin
if(~rst) begin
for(i = 0; i < 2**ADDSIZE; i = i + 1) begin
array_reg[i] <= 0;
end
end
else if(wren) begin
array_reg[rw] <= wdat;
end
end
// Asynchronous Read
assign adat = array_reg[ra];
assign bdat = array_reg[rb];
assign zeroDat = array_reg[0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
/**
* lsbufiso1p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_BLACKBOX_V
|
/*
* Copyright (C) 2009 Onno Kortmann <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* THIS FILE HAS BEEN AUTOMATICALLY GENERATED FROM avr_tmpl.v.
* --- DO NOT EDIT MANUALLY! ---
*/
module ATmega8(clk, PB, PC, PD);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PB;
inout [7:0] PC;
inout [7:0] PD;
integer handle;
defparam core.progfile=progfile;
defparam core.name="atmega8";
AVRCORE core(clk);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
avr_pin #("B6") pb6(PB[6]);
avr_pin #("B7") pb7(PB[7]);
avr_pin #("C0") pc0(PC[0]);
avr_pin #("C1") pc1(PC[1]);
avr_pin #("C2") pc2(PC[2]);
avr_pin #("C3") pc3(PC[3]);
avr_pin #("C4") pc4(PC[4]);
avr_pin #("C5") pc5(PC[5]);
avr_pin #("C6") pc6(PC[6]);
avr_pin #("D0") pd0(PD[0]);
avr_pin #("D1") pd1(PD[1]);
avr_pin #("D2") pd2(PD[2]);
avr_pin #("D3") pd3(PD[3]);
avr_pin #("D4") pd4(PD[4]);
avr_pin #("D5") pd5(PD[5]);
avr_pin #("D6") pd6(PD[6]);
avr_pin #("D7") pd7(PD[7]);
endmodule
|
`include "system_conf.v"
`include "../components/lm32_top/lm32_include.v" // for {IROM,DRAM}_ADDR_WIDTH
`include "../components/lm32_top/lm32_include_all.v"
module superkdf9 (
input wire clk, rst
,output wire [3:0] led
,input wire [31:0] interrupt_n
,output wire [10:0] user_opcode
,output wire [31:0] user_operand_0
,output wire [31:0] user_operand_1
,input wire [31:0] user_result
,input wire user_complete
,output wire user_valid
);
`include "../components/lm32_top/lm32_functions.v" // for clogb2_v1
wire [31:0] irom_q_rd, irom_q_wr;
wire [31:0] dram_q_rd, dram_q_wr /* unused */;
wire irom_clk_rd, irom_clk_wr;
wire irom_rst_rd, irom_rst_wr;
wire [31:0] irom_d_rd /* unused */, irom_d_wr;
wire [32-2-1:0] irom_addr_rd, irom_addr_wr;
wire irom_en_rd, irom_en_wr;
wire irom_write_rd, irom_write_wr;
wire dram_clk_rd, dram_clk_wr;
wire dram_rst_rd, dram_rst_wr;
wire [31:0] dram_d_rd /* unused */, dram_d_wr;
wire [32-2-1:0] dram_addr_rd, dram_addr_wr;
wire dram_en_rd, dram_en_wr;
wire dram_write_rd, dram_write_wr;
// IROM {{{
bram #(
.size(1+`CFG_IROM_LIMIT - `CFG_IROM_BASE_ADDRESS),
.name("irom")
) irom (
.ClockA(irom_clk_rd),
.ClockB(irom_clk_wr),
.ResetA(irom_rst_rd),
.ResetB(irom_rst_wr),
.AddressA(irom_addr_rd),
.AddressB(irom_addr_wr),
.DataInA(irom_d_rd), /* unused */
.DataInB(irom_d_wr),
.DataOutA(irom_q_rd),
.DataOutB(irom_q_wr), /* unused */
.ClockEnA(irom_en_rd),
.ClockEnB(irom_en_wr),
.WriteA(irom_write_rd),
.WriteB(irom_write_wr)
);
// }}}
// DRAM {{{
bram #(
.size(8192), // only provide necessary
.name("irom")
) dram (
.ClockA(dram_clk_rd),
.ClockB(dram_clk_wr),
.ResetA(dram_rst_rd),
.ResetB(dram_rst_wr),
.AddressA(dram_addr_rd),
.AddressB(dram_addr_wr),
.DataInA(dram_d_rd), /* unused */
.DataInB(dram_d_wr),
.DataOutA(dram_q_rd),
.DataOutB(dram_q_wr),
.ClockEnA(dram_en_rd),
.ClockEnB(dram_en_wr),
.WriteA(dram_write_rd),
.WriteB(dram_write_wr)
);
// }}}
lm32_top superkdf9(
// instruction wishbone bus (unused) {{{
.I_ADR_O(),
.I_DAT_O(),
.I_DAT_I(),
.I_SEL_O(),
.I_WE_O(),
.I_ACK_I(),
.I_ERR_I(),
.I_RTY_I(),
.I_CTI_O(),
.I_BTE_O(),
.I_LOCK_O(),
.I_CYC_O(),
.I_STB_O(), // }}}
// data wishbone bus (unused) {{{
.D_ADR_O(),
.D_DAT_O(),
.D_DAT_I(),
.D_SEL_O(),
.D_WE_O(),
.D_ACK_I(),
.D_ERR_I(),
.D_RTY_I(),
.D_CTI_O(),
.D_BTE_O(),
.D_LOCK_O(),
.D_CYC_O(),
.D_STB_O(), // }}}
.clk_i(clk), .rst_i(rst),
.interrupt_n(interrupt_n),
// the exposed IROM {{{
.irom_clk_rd(irom_clk_rd),
.irom_clk_wr(irom_clk_wr),
.irom_rst_rd(irom_rst_rd),
.irom_rst_wr(irom_rst_wr),
.irom_d_rd(irom_d_rd), /* unused */
.irom_d_wr(irom_d_wr),
.irom_q_rd(irom_q_rd),
.irom_q_wr(irom_q_wr),
.irom_addr_rd(irom_addr_rd[`IROM_ADDR_WIDTH-1:0]),
.irom_addr_wr(irom_addr_wr[`IROM_ADDR_WIDTH-1:0]),
.irom_en_rd(irom_en_rd),
.irom_en_wr(irom_en_wr),
.irom_write_rd(irom_write_rd),
.irom_write_wr(irom_write_wr), // }}}
// the exposed DRAM {{{
.dram_clk_rd(dram_clk_rd),
.dram_clk_wr(dram_clk_wr),
.dram_rst_rd(dram_rst_rd),
.dram_rst_wr(dram_rst_wr),
.dram_d_rd(dram_d_rd), /* unused */
.dram_d_wr(dram_d_wr),
.dram_q_rd(dram_q_rd),
.dram_q_wr(dram_q_wr), /* unused */
.dram_addr_rd(dram_addr_rd[`DRAM_ADDR_WIDTH-1:0]),
.dram_addr_wr(dram_addr_wr[`DRAM_ADDR_WIDTH-1:0]),
.dram_en_rd(dram_en_rd),
.dram_en_wr(dram_en_wr),
.dram_write_rd(dram_write_rd),
.dram_write_wr(dram_write_wr), // }}}
// user instruction {{{
.user_result(user_result),
.user_complete(user_complete),
.user_valid(user_valid),
.user_opcode(user_opcode),
.user_operand_0(user_operand_0),
.user_operand_1(user_operand_1) // }}}
);
endmodule
// vim: set fdm=marker :
|
module user_io(
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
input [7:0] CORE_TYPE,
output [5:0] JOY0,
output [5:0] JOY1,
output [2:0] MOUSE_BUTTONS,
output KBD_MOUSE_STROBE,
output [1:0] KBD_MOUSE_TYPE,
output [7:0] KBD_MOUSE_DATA,
output [1:0] BUTTONS,
output [1:0] SWITCHES
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [5:0] cnt;
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [3:0] but_sw;
reg kbd_mouse_strobe;
reg [1:0] kbd_mouse_type;
reg [7:0] kbd_mouse_data;
reg [2:0] mouse_buttons;
assign JOY0 = joystick0;
assign JOY1 = joystick1;
assign KBD_MOUSE_DATA = kbd_mouse_data; // 8 bit movement data
assign KBD_MOUSE_TYPE = kbd_mouse_type; // 0=mouse x,1=mouse y, 2=keycode, 3=OSD kbd
assign KBD_MOUSE_STROBE = kbd_mouse_strobe; // strobe, data valid on rising edge
assign MOUSE_BUTTONS = mouse_buttons; // state of the two mouse buttons
assign BUTTONS = but_sw[1:0];
assign SWITCHES = but_sw[3:2];
always@(negedge SPI_CLK) begin
if(cnt < 8)
SPI_MISO <= CORE_TYPE[7-cnt];
end
always@(posedge SPI_CLK) begin
if(SPI_SS_IO == 1) begin
cnt <= 0;
end else begin
sbuf[6:1] <= sbuf[5:0];
sbuf[0] <= SPI_MOSI;
cnt <= cnt + 1;
if(cnt == 7) begin
cmd[7:1] <= sbuf;
cmd[0] <= SPI_MOSI;
end
if(cnt == 8) begin
if(cmd == 4)
kbd_mouse_type <= 2'b00; // first mouse axis
else if(cmd == 5)
kbd_mouse_type <= 2'b10; // keyboard
else if(cmd == 6)
kbd_mouse_type <= 2'b11; // OSD keyboard
end
// strobe is set whenever a valid byte has been received
kbd_mouse_strobe <= 0;
// first payload byte
if(cnt == 15) begin
if(cmd == 1) begin
but_sw[3:1] <= sbuf[2:0];
but_sw[0] <= SPI_MOSI;
end
if(cmd == 2) begin
joystick0[5:1] <= sbuf[4:0];
joystick0[0] <= SPI_MOSI;
end
if(cmd == 3) begin
joystick1[5:1] <= sbuf[4:0];
joystick1[0] <= SPI_MOSI;
end
// mouse, keyboard or OSD
if((cmd == 4)||(cmd == 5)||(cmd == 6)) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
end
end
// mouse handling
if(cmd == 4) begin
// second byte contains movement data
if(cnt == 23) begin
kbd_mouse_data[7:1] <= sbuf[6:0];
kbd_mouse_data[0] <= SPI_MOSI;
kbd_mouse_strobe <= 1;
kbd_mouse_type <= 2'b01;
end
// third byte contains the buttons
if(cnt == 31) begin
mouse_buttons[2:1] <= sbuf[1:0];
mouse_buttons[0] <= SPI_MOSI;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 120000 + 10; const double PI = acos(-1); pair<double, double> operator+(pair<double, double> a, pair<double, double> b) { return make_pair(a.first + b.first, a.second + b.second); } pair<double, double> operator-(pair<double, double> a, pair<double, double> b) { return make_pair(a.first - b.first, a.second - b.second); } pair<double, double> operator*(pair<double, double> a, pair<double, double> b) { return make_pair(a.first * b.first - a.second * b.second, a.first * b.second + a.second * b.first); } pair<double, double> operator/(pair<double, double> a, double t) { return make_pair(a.first / t, a.second / t); } int rev[N], lim; pair<double, double> w[N]; void initrever(int n, int &lim) { lim = 1; for (; lim < n; lim <<= 1) ; for (int i = 1; i < lim; i++) { rev[i] = (rev[i >> 1] >> 1); if (i & 1) rev[i] |= (lim >> 1); } for (int i = 0; i < lim; i++) { double t = 2 * PI * i / lim; w[i] = make_pair(cos(t), sin(t)); } return; } void FFT(vector<pair<double, double> > &a, int t) { int lim = a.size(); if (t < 0) { for (int i = 1; i < lim; i++) { if (i < (lim - i)) swap(a[i], a[lim - i]); } } for (int i = 0; i < lim; i++) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int i = 2; i <= lim; i <<= 1) { for (int j = 0; j < lim; j += i) { for (int k = 0; k < (i >> 1); k++) { pair<double, double> first = a[j + k], second = a[j + k + (i >> 1)] * w[lim / i * k]; a[j + k] = (first + second); a[j + k + (i >> 1)] = (first - second); } } } if (t < 0) { for (int i = 0; i < lim; i++) a[i] = a[i] / lim; } return; } vector<pair<double, double> > f[2]; int n, a, p; double reduce(double first) { long long tmp = llround(first); tmp %= p; return (double)tmp; } void add1() { swap(f[0], f[1]); for (int i = 0; i <= 1; i++) { for (int j = n; j >= 1; j--) { f[i][j].first = reduce(f[i][j].first + f[i][j - 1].first); } } f[1][1].first = reduce(f[1][1].first + 1); return; } void put(vector<pair<double, double> > v) { for (int i = 0; i < (int)v.size(); i++) printf( %lf , v[i].first); printf( n ); return; } void pro2(int v) { FFT(f[0], 1), FFT(f[1], 1); for (int i = 0; i < lim; i++) { pair<double, double> first = f[v & 1][i] * (f[0][i] + f[1][i]) + f[0][i] + f[v & 1][i]; pair<double, double> second = f[(v & 1) ^ 1][i] * (f[0][i] + f[1][i]) + f[1][i] + f[(v & 1) ^ 1][i]; f[0][i] = first, f[1][i] = second; } FFT(f[0], -1), FFT(f[1], -1); for (int i = 0; i <= 1; i++) { for (int j = 0; j <= n; j++) { f[i][j].first = reduce(f[i][j].first); f[i][j].second = 0; } for (int j = n + 1; j < lim; j++) f[i][j] = make_pair(0, 0); } return; } vector<int> num; int main() { scanf( %d%d%d , &n, &a, &p); initrever(n * 2 + 1, lim); f[0].resize(lim), f[1].resize(lim); for (int no = a; no > 1; no /= 2) { num.push_back(no); } num.push_back(1); reverse(num.begin(), num.end()); f[1][1].first = 1; int ans = 0; for (int i = 0; i < (int)num.size() - 1; i++) { for (int j = 1; j <= n; j += 2) { ans = (ans + llround(f[1][j].first)) % p; } pro2(num[i]); if (num[i] * 2 < num[i + 1]) add1(); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; string ent = n ; string space = ; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; string s; cin >> s; int zero, one; zero = one = 0; for (int i = 0; i < n; i++) { if (s[i] == 48) zero++; else one++; } if (one != zero) { cout << 1 << ent + s + ent; } else { int j = n - 1; string s_new; for (int i = 0; i < n; i++) { if (one != zero) { j = i; break; } s_new += s[i]; if (s[i] == 48) zero--; else one--; } cout << 2 << ent + s_new + space; for (int i = j; i < n; i++) { cout << s[i]; } cout << ent; } }
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#include <cstdio> #include <iostream> using namespace std; const int M = 20005; const int N = 31; #define make make_pair #define pii pair<int,int> int read() { int x=0,f=1;char c; while((c=getchar())< 0 || c> 9 ) {if(c== - ) f=-1;} while(c>= 0 && c<= 9 ) {x=(x<<3)+(x<<1)+(c^48);c=getchar();} return x*f; } int n,q,a[M],lg[M],f[M][20][N],g[N],tmp[N];pii dp[M][20]; //f[i][j][k]:stand for the max (l+al) can reach from i through 2^j jumps and k delete int ask(int l,int r)//ask the l of max (l+al) { int k=lg[r-l+1]; return max(dp[l][k],dp[r-(1<<k)+1][k]).second; } void init() { for(int j=1;(1<<j)<=n;j++)//st for(int i=1;i+(1<<j)-1<=n;i++) dp[i][j]=max(dp[i][j-1],dp[i+(1<<j-1)][j-1]); for(int i=1;i<=n;i++) for(int j=0;j<N;j++) f[i][0][j]=min(n,i+a[i]+j);//this min is necessary for(int j=1;(1<<j)<=n;j++) for(int i=1;i<=n;i++)//please don t limit the range of i for(int k=0;k<N;k++) for(int x=0;x<=k;x++) { int t=ask(i,f[i][j-1][x]);//find the position f[i][j][k]=max(f[i][j][k],f[t][j-1][k-x]); } } signed main() { n=read();q=read(); for(int i=1;i<=n;i++) { a[i]=read(); dp[i][0]=make(min(n,a[i]+i),i); if(i>1) lg[i]=lg[i>>1]+1; } init(); while(q--) { int l=read(),r=read(),k=read(),ans=0; if(l==r) {puts( 0 );continue;} if(l+a[l]+k>=r) {puts( 1 );continue;} for(int i=0;i<=k;i++) g[i]=l; for(int x=15;x>=0;x--) { if((1<<x)>n) continue; for(int i=0;i<=k;i++) tmp[i]=g[i]; for(int i=0;i<=k;i++) { int t=ask(l,g[i]); for(int j=0;i+j<=k;j++) tmp[i+j]=max(tmp[i+j],f[t][x][j]); } int fl=0; for(int i=0;i<=k;i++) if(tmp[i]>=r) fl=1; if(fl) continue; for(int i=0;i<=k;i++) g[i]=tmp[i]; ans+=(1<<x); } printf( %d n ,ans+1); } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFXTP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; map<pair<string, int>, vector<pair<string, int> > > edg; queue<string> que; map<string, int> num, por; set<string> sett; int main() { int n, i, k, l, r, a, b, j; cin >> n; string s, t, S; for (i = 0; i < n; i++) { cin >> s >> a; if (!i) { que.push(s); num[s] = a; S = s; por[s] = 1; } cin >> k; for (j = 0; j < k; j++) { cin >> t >> b; edg[{s, a}].push_back({t, b}); } } pair<string, int> st; while (!que.empty()) { sett.insert(que.front()); st.first = que.front(); st.second = num[st.first]; que.pop(); for (i = 0; i < edg[st].size(); i++) { if (!num.count(edg[st][i].first)) { num[edg[st][i].first] = edg[st][i].second; por[edg[st][i].first] = por[st.first] + 1; que.push(edg[st][i].first); } else { if (por[st.first] + 1 == por[edg[st][i].first] && edg[st][i].second > num[edg[st][i].first]) { num[edg[st][i].first] = edg[st][i].second; } } } } sett.erase(S); cout << sett.size() << n ; for (auto j : sett) { cout << j << << num[j] << n ; } }
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#include <bits/stdc++.h> using namespace std; int a[13] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; int run(int x) { if ((x % 4 == 0 && x % 100 != 0) || (x % 400 == 0)) return 1; else return 0; } int main() { int y1, y2, m1, m2, d1, d2; int i, j; scanf( %d:%d:%d , &y1, &m1, &d1); scanf( %d:%d:%d , &y2, &m2, &d2); int t; if (y1 > y2) { t = y1; y1 = y2; y2 = t; t = m1; m1 = m2; m2 = t; t = d1; d1 = d2; d2 = t; } else if (y1 == y2) { if (m1 > m2) { t = m1; m1 = m2; m2 = t; t = d1; d1 = d2; d2 = t; } else if (m1 == m2) { if (d1 > d2) { t = d1; d1 = d2; d2 = t; } } } int sum = 0; for (i = y1 + 1; i < y2; i++) { if (run(i)) sum += 366; else sum += 365; } int num = a[m1 - 1] + d1; int num2 = a[m2 - 1] + d2; if (y1 != y2) { if (run(y1)) { if (m1 > 2) num = 365 - num; else num = 366 - num; } else num = 365 - num; if (run(y2)) { if (m2 > 2) num2++; } sum += num; sum += num2; } else { if (run(y1)) if (m1 > 2) num++; if (run(y2)) if (m2 > 2) num2++; sum += num2 - num; } cout << sum << endl; }
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#include <bits/stdc++.h> int b; struct Matrix { long long int x[110][110]; } A, B, C; Matrix operator*(Matrix A, Matrix B) { Matrix C; for (int i = 1; i <= b; i++) { for (int j = 1; j <= b; j++) { C.x[i][j] = 0; for (int k = 1; k <= b; k++) { C.x[i][j] += A.x[i][k] * B.x[k][j]; C.x[i][j] %= 1000000007; } } } return C; } void func(long long int k) { for (int i = 1; i <= b; i++) for (int j = 1; j <= b; j++) B.x[i][j] = C.x[i][j] = 0; for (int i = 1; i <= b; i++) B.x[i][i] = C.x[i][i] = 1; C = A; while (k) { if (k % 2 == 1) B = B * C; k /= 2; C = C * C; } } int main() { long long int a; scanf( %lld%d , &a, &b); for (int i = 1; i <= b; i++) for (int j = 1; j <= b; j++) A.x[i][j] = 0; A.x[1][1] = 1, A.x[1][b] = 1; for (int i = 2; i <= b; i++) A.x[i][i - 1] = 1; if (a < b) { printf( 1 ); return 0; } func(a - b); long long int s = 0; for (int i = 1; i <= b; i++) s += B.x[1][i], s %= 1000000007; s += B.x[1][1], s %= 1000000007; printf( %lld , s); }
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#include <bits/stdc++.h> using namespace std; const int infint = 1e9; const long long inf = 1e18; const int MOD = (int)1e9 + 7; const int MAXN = (int)3e5 + 7; const int LOG = 17; int a[MAXN], n, IL[MAXN], IR[MAXN], Lp, Rp, ans, L, R; pair<int, int> G, seg[LOG][2 * MAXN]; pair<int, int> operator*(const pair<int, int> &a, pair<int, int> b) { return {min(a.first, b.first), max(a.second, b.second)}; } void update(int BASE, int idx, int x, int y) { for (seg[BASE][idx += 3 * n] = {x, y}; idx > 1; idx >>= 1) seg[BASE][idx >> 1] = seg[BASE][idx] * seg[BASE][idx ^ 1]; } pair<int, int> get(int BASE, int l, int r) { pair<int, int> res = {3 * n, 0}; for (l += 3 * n, r += 3 * n; l < r; l >>= 1, r >>= 1) { if (l & 1) res = res * seg[BASE][l++]; if (r & 1) res = res * seg[BASE][--r]; } return res; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = n; i < 3 * n; i++) a[i] = a[i % n]; for (int i = 0; i < LOG; i++) for (int j = 0; j < MAXN; j++) seg[i][j] = {3 * n, 0}; for (int i = 0; i < 3 * n; i++) { update(0, i, max(0, i - a[i]), min(i + a[i], 3 * n - 1)); IL[i] = max(0, i - a[i]), IR[i] = min(i + a[i], 3 * n - 1); } for (int i = 1; i < LOG; i++) { for (int j = 0; j < 3 * n; j++) { G = get(i - 1, IL[j], IR[j] + 1); Lp = G.first, Rp = G.second; IL[j] = Lp, IR[j] = Rp; update(i, j, Lp, Rp); } } if (n == 1) return cout << 0, 0; for (int j = n; j < 2 * n; j++) { ans = 0, L = j, R = j; for (int lg = 16; lg >= 0; lg--) { G = get(lg, L, R + 1); if (G.second - G.first + 1 < n) { ans += (1 << lg); Lp = G.first, Rp = G.second; L = Lp, R = Rp; } } printf( %d , ans + 1); } }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using db = double; int mod = 1000000007; db pie = 3.1415926535; int spf[5000005]; int mm = 5000000; int pre[5000005]; void help() { int i; for (i = 1; i <= mm; i++) { spf[i] = i; } for (i = 2; i <= mm; i += 2) { spf[i] = 2; } int j; for (i = 3; i * i <= mm; i += 2) { if (spf[i] == i) { for (j = i * i; j <= mm; j += i) { if (spf[j] == j) spf[j] = i; } } } pre[0] = 0; pre[1] = 0; for (i = 2; i <= mm; i++) { int m = i; int cnt = 0; while (m > 1) { cnt++; m = m / spf[m]; } pre[i] = cnt; pre[i] += pre[i - 1]; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; help(); while (t--) { int a, b; cin >> a >> b; int ans = pre[a] - pre[b]; cout << ans << n ; } }
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#include<bits/stdc++.h> #include<unordered_map> #include<unordered_set> #define f(i,a,b) for( int i=a;i<=b;++i) #define ff(i,a,b) for( int i=a;i>=b;--i) #define debug(x) cerr << #x << : << x << << endl using namespace std; typedef long long ll; typedef unsigned long long ull; typedef long double ld; typedef pair<int, int> pii; typedef pair<string, string> pss; const ll mod = 1e9 + 7; const ll mod2 = 998244353; const ll inf = 2e18; const double tiaohe = 0.57721566490153286060651209; ll oula(ll x) { ll res = x;f(i, 2, x / i) { if (x % i == 0) { res = res / i * (i - 1);while (x % i == 0) x /= i; } }if (x > 1) res = res / x * (x - 1);return res; } ll quickmod(ll a, ll n, ll m) { ll s = 1;while (n) { if (n & 1) { s = s * a % m; }a = (a*a) % m;n = n / 2; }return s; } ll gcd(ll a, ll b) { return b ? gcd(b, a%b) : a; } void ex_gcd(ll a, ll b, ll &x, ll &y, ll &d) { if (!b) { d = a, x = 1, y = 0; } else { ex_gcd(b, a % b, y, x, d);y -= x * (a / b); } } ll inv(ll t, ll p) { ll d, x, y;ex_gcd(t, p, x, y, d);return d == 1 ? (x % p + p) % p : -1; } bool isPrime(ll x) { if (x == 2)return true;if (x % 2 == 0)return false;for (ll i = 2;i*i <= x;i++) if (x % i == 0)return false; return true; } inline ll in() { char ch = getchar();ll x = 0, f = 1;while (ch< 0 || ch> 9 ) { if (ch == - )f = -1;ch = getchar(); }while (ch >= 0 &&ch <= 9 ) { x = x * 10 + ch - 0 ;ch = getchar(); }return x * f; } void print(double x) { printf( %.6lf n , x); } //double a = log(n) +tiaohe + 1.0 / (2 * n); double eqa = (1 + sqrt(5.0)) / 2.0; double E = 2.7182818284; const double eps = 1e-8; double pi = acos(-1); const int N = 5e5 + 100; int n, m; ll k; int a[N], b[N],id; ll M[2], LCM; pair<ll,ll> st[N];//等价类起点 pair<ll,ll> linear( ll B[], ll M[], int n) { //求解 A[i]x = B[i] (mod M[i]), 总共 n 个线性 方程组, → ll x = 0, m = 1; for (int i = 0; i < n; i++) { ll a = m, b = B[i] - x, d = gcd(M[i], a); if (b % d != 0) return pair<ll,ll>(0, -1);//答案不存在，返回-1 ll t = b / d * inv(a / d, M[i] / d) % (M[i] / d); x = x + m * t; m *= M[i] / d; } x = (x % m + m) % m; return pair<ll, ll>{x,m};//返回的 x 就是答案，m 是最后的 lcm 值 } ll pos[N][2]; bool check(ll mid) { ll res = mid;//减去命中的 f(i, 1, id) { if (st[i].second == -1) { continue; } if (st[i].first > mid)continue; ll num = (ll)ceil((mid-1-st[i].first)*1.0/LCM); res -= num; } //cout << mid << << res << endl; return res <= k; } void work(ll k) { ll l = 0, r = 2e18,res=0; while (l <= r) { ll mid = l + r >> 1; if (check(mid)) { res = mid; l = mid + 1; } else { r = mid - 1; } } cout << res << endl; } int main() { #ifndef ONLINE_JUDGE freopen( in.txt , r , stdin); #endif cin >> n >> m >> k; unordered_map<int, int> mp; f(i, 1, n)a[i] = in(), mp[a[i]] = i-1; f(i, 1, m)b[i] = in(); id = 0; f(i, 1, m) { if (mp.count(b[i])) { pos[++id][0] = mp[b[i]]; pos[id][1] = i-1; } } LCM= 1ll*n * m / gcd(n, m); M[0] = n, M[1] = m; f(i, 1, id) { st[i] = linear(pos[i], M, 2); //cout << st[i].first << << st[i].second << endl; } work(k); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 1e3; string s, sq; int z1[maxn + 10], z2[maxn + 10], pref[1010], suff[1010], rez; void calc(string ss, int z[]) { int l = -1; int r = -1; for (int i = 1; i < ss.size(); i++) { if (i > r) { l = i; r = l - 1; while (r + 1 < ss.size() && ss[r + 1] == ss[r + 1 - l]) r++; z[i] = r - l + 1; } else { if (i + z[i - l] - 1 < r) z[i] = z[i - l]; else { l = i; while (r + 1 < ss.size() && ss[r + 1] == ss[r + 1 - l]) r++; z[i] = r - l + 1; } } } } int main() { cin >> s; int q; scanf( %d , &q); for (int qi = 1; qi <= q; qi++) { cin >> sq; if (sq.size() == 1) continue; string pom = sq + $ + s; calc(pom, z1); reverse(s.begin(), s.end()); reverse(sq.begin(), sq.end()); pom = sq + $ + s; calc(pom, z2); reverse(s.begin(), s.end()); for (int i = 0; i < s.size(); i++) z1[i] = z1[i + sq.size() + 1]; for (int i = 0; i < pom.size() / 2; i++) swap(z2[i], z2[pom.size() - 1 - i]); fill(pref, pref + 1001, 1000000000); fill(suff, suff + 1001, -1); int e = 0; for (int i = 0; i < s.size(); i++) { int id = z1[i]; if (id == sq.size()) { rez++; e = 1; break; } if (pref[id] == 1000000000) pref[id] = i; id = z2[i]; if (id == sq.size()) { rez++; e = 1; break; } suff[id] = i; } for (int i = sq.size() - 1; i >= 1; i--) { pref[i] = min(pref[i], pref[i + 1]); suff[i] = max(suff[i], suff[i + 1]); } if (e == 1) continue; for (int i = 1; i < sq.size(); i++) { if (pref[i] == -1 || suff[sq.size() - i] == -1) continue; if (pref[i] + i - 1 < suff[sq.size() - i] - (sq.size() - i) + 1) { rez++; break; } } } printf( %d n , rez); return 0; }
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#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3,Ofast,no-stack-protector,unroll-loops,fast-math ) const int maxn = 2e3 + 7; int32_t main() { int n, d, e; cin >> n >> d >> e; int ans = 1e9 + 7; for (int i = 1; i * 5 * e <= n; i++) { int t = i * 5 * e; t = n - t; t %= (d); ans = min(ans, t); } int t = n % d; ans = min(ans, t); cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; set<long long int> blacklist; long long int par(long long int* parent, long long int f, long long int n) { if (parent[f] < 0) return parent[f]; if (parent[f] == f) return f; else { parent[f] = par(parent, parent[f], n); return parent[f]; } } void unio(long long int* parent, long long int f, long long int s, long long int pf, long long int ps) { if (pf < ps) parent[ps] = pf; else parent[pf] = ps; } void utilfun(long long int* parent, vector<long long int>* adj, pair<long long int, long long int>* edge, long long int n, long long int m, long long int a, long long int b) { for (long long int i = 0; i < m; i++) { long long int f = edge[i].first; long long int s = edge[i].second; if (f == a || f == b || s == a || s == b) { continue; } else { long long int pf = par(parent, f, n); long long int ps = par(parent, s, n); unio(parent, f, s, pf, ps); } } long long int ind = -2; for (long long int i = 0; i < m; i++) { long long int f = edge[i].first; long long int s = edge[i].second; if ((f == a || s == a) && (s != b && f != b)) { long long int ot = f + s - a; long long int pot = par(parent, ot, n); if (pot >= 0) { parent[pot] = ind; ind--; } } } for (long long int i = 0; i < m; i++) { long long int f = edge[i].first; long long int s = edge[i].second; if ((f == b || s == b) && (s != a && f != a)) { long long int ot = f + s - b; long long int pot = par(parent, ot, n); if (pot == -1) { continue; } else if (pot < -1) { blacklist.insert(pot); } else parent[pot] = b; } } } int main() { long long int t; cin >> t; while (t--) { blacklist.clear(); long long int n, m, a, b; cin >> n >> m >> a >> b; a--; b--; vector<long long int> adj[n]; pair<long long int, long long int> edge[m]; long long int parent[n]; for (long long int i = 0; i < n; i++) parent[i] = i; for (long long int i = 0; i < m; i++) { long long int x, y; cin >> x >> y; x--; y--; adj[x].push_back(y); adj[y].push_back(x); edge[i] = {x, y}; } utilfun(parent, adj, edge, n, m, a, b); long long int ac = 0; long long int bc = -1; set<long long int>::iterator itr; for (long long int i = 0; i < n; i++) { long long int pot = par(parent, i, n); if (blacklist.find(pot) != blacklist.end()) continue; if (pot < -1) ac++; else if (pot == b) bc++; } cout << ac * bc << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int N = 2000 + 10; int n; int pa, pb, p, q; int cp[N][N]; int strong[N]; int f[N]; void add(int &t, int s) { t += s; if (t >= MOD) t -= MOD; } void mul(int &t, int s) { t = (long long)t * s % MOD; } int pow(int s, int n) { long long ret = 1; while (n) if (n % 2) ret = ret * s % MOD, n--; else s = (long long)s * s % MOD, n >>= 1; return ret; } int inv(int s) { return pow(s, MOD - 2); } int main() { cin >> n >> pa >> pb; p = (long long)pa * inv(pb) % MOD; q = (MOD - p + 1) % MOD; f[0] = 0; f[1] = 0; cp[0][0] = 1; for (int i = 1; i <= n; i++) { cp[i][0] = 1; for (int j = 1; j <= i; j++) { cp[i][j] = ((long long)cp[i - 1][j - 1] * pow(q, i - j) + (long long)cp[i - 1][j] * pow(p, j)) % MOD; } } strong[1] = 1; for (int i = 2; i <= n; i++) { int res = 0; for (int j = 1; j < i; j++) { int tmp = strong[j]; mul(tmp, cp[i][j]); add(res, tmp); } strong[i] = (1 - res + MOD) % MOD; } for (int s = 2; s <= n; s++) { int res = 0; for (int i = 1; i < s; i++) { int cur = 1; mul(cur, strong[i]); mul(cur, cp[s][i]); int games = 0; add(games, i * (s - i)); add(games, i * (i - 1) / 2); add(games, f[i]); add(games, f[s - i]); mul(cur, games); add(res, cur); } int coeff = 1; mul(coeff, strong[s]); mul(coeff, cp[s][s]); int tmp = coeff; mul(tmp, s * (s - 1) / 2); add(res, tmp); coeff = (1 + MOD - coeff) % MOD; mul(res, inv(coeff)); f[s] = res; } cout << f[n] << endl; return 0; }
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 2-11-2018
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
module jt12_pg_sum (
input [ 3:0] mul,
input [19:0] phase_in,
input pg_rst,
input signed [5:0] detune_signed,
input [16:0] phinc_pure,
output reg [19:0] phase_out,
output reg [ 9:0] phase_op
);
reg [16:0] phinc_premul;
reg [19:0] phinc_mul;
always @(*) begin
phinc_premul = phinc_pure + {{11{detune_signed[5]}},detune_signed};
phinc_mul = ( mul==4'd0 ) ? {4'b0,phinc_premul[16:1]} : ({3'd0,phinc_premul} * mul);
phase_out = pg_rst ? 20'd0 : (phase_in + { phinc_mul});
phase_op = phase_out[19:10];
end
endmodule // jt12_pg_sum
|
// test_data_dma.v
`timescale 1ns / 1ps
module test_data_dma;
// avalon clock interface
reg clk = 0;
reg reset = 1;
// avalon mm slave: control port
reg [1:0]avs_ctrl_address = 2'bxx;
reg avs_ctrl_write = 0;
reg [31:0]avs_ctrl_writedata = 32'hxxxx_xxxx;
reg avs_ctrl_read = 0;
wire [31:0]avs_ctrl_readdata;
// avalon mm master: DMA data write port
wire [31:0]avm_data_address;
wire avm_data_write;
wire [15:0]avm_data_writedata;
reg avm_data_waitrequest;
wire [1:0]avm_data_byteenable;
// avalon conduit: external data source
reg write;
wire waitrq;
reg [15:0]data;
always #10 clk = !clk;
initial #25 reset = 0;
// --- data generator -----------------------------------------------------
integer dg_cnt = 0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
data <= 100;
write <= 0;
end
else
begin
write <= (dg_cnt % 10) > 2;
dg_cnt = dg_cnt + 1;
if (write & !waitrq) data <= data + 1;
end
end
// --- ram ----------------------------------------------------------------
integer ram_cnt = 0;
always @(posedge clk)
begin
ram_cnt = ram_cnt + 1;
avm_data_waitrequest <= (ram_cnt % 13) >= 11;
end
// --- DMA programming ----------------------------------------------------
task WriteCtrl(input [1:0]register, input [31:0]data);
begin
@(posedge clk);
avs_ctrl_write <= 1;
avs_ctrl_address <= register;
avs_ctrl_writedata <= data;
@(posedge clk)
avs_ctrl_write <= 0;
avs_ctrl_address <= 2'bxx;
avs_ctrl_writedata <= 32'hxxxx_xxxx;
end
endtask
initial
begin
#160;
WriteCtrl(0, 32'h0100_0000);
WriteCtrl(1, 100);
WriteCtrl(2, 1);
#2000 $stop(2);
end
data_dma DUT
(
.csi_clock_clk(clk),
.csi_clock_reset(reset),
// avalon mm slave: control port
.avs_ctrl_address(avs_ctrl_address),
.avs_ctrl_write(avs_ctrl_write),
.avs_ctrl_writedata(avs_ctrl_writedata),
.avs_ctrl_read(avs_ctrl_read),
.avs_ctrl_readdata(avs_ctrl_readdata),
// avalon mm master: DMA data write port
.avm_data_address(avm_data_address),
.avm_data_write(avm_data_write),
.avm_data_writedata(avm_data_writedata),
.avm_data_waitrequest(avm_data_waitrequest),
.avm_data_byteenable(avm_data_byteenable),
// avalon conduit: external data source
.write(write),
.waitrq(waitrq),
.data(data)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_2_V
`define SKY130_FD_SC_MS__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_2_V
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
// $Revision: #7 $
// $Date: 2010/04/27 $
// $Author: jyeap $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_tse_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
// Please check the false paths setting in TSE SDC
(*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
reg altera_tse_reset_synchronizer_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
altera_tse_reset_synchronizer_chain_out <= 1'b1;
end
else begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
end
assign reset_out = altera_tse_reset_synchronizer_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x, y, nr; int a[110], b[110]; bool used[110]; int main() { cin >> n; cin >> x; for (int i = 1; i <= x; ++i) { cin >> nr; used[nr] = true; } cin >> y; for (int i = 1; i <= y; ++i) { cin >> nr; used[nr] = true; } for (int i = 1; i <= n; ++i) { if (!used[i]) { cout << Oh, my keyboard! ; return 0; } } cout << I become the guy. ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_BLACKBOX_V
`define SKY130_FD_SC_HD__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_BLACKBOX_V
|
#include <bits/stdc++.h> int main() { int i, j, count, n, a[5001], flag[5001]; scanf( %d , &n); count = 0; memset(flag, 0, sizeof(int) * 5001); for (i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] > n) count++; else if (flag[a[i]] == 1) count++; else flag[a[i]] = 1; } printf( %d n , count); return 0; }
|
/*
* Titor - Barrel Processor - Easy to replicate register
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Register
`else
`define INC_Register
`timescale 1 ns / 100 ps
// Register module
module Register (
value,
memory,
datapath,
sel_memory,
sel_datapath,
clk,
reset
);
`include "definition/Definition.v"
output reg [WORD-1:0] value; // the value stored in the register
input [WORD-1:0] memory;
input [WORD-1:0] datapath;
input sel_memory;
input sel_datapath;
input clk;
input reset;
always @(posedge clk) begin
if(reset) begin value <= 0; end
else if(sel_memory) begin value <= memory; end
else if(sel_datapath) begin value <= datapath; end
else begin value <= value; end
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_cpu_registers.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_cpu_registers.v,v $
// Revision 1.6 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.5 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.4 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.3 2004/01/22 10:16:08 mohor
// cpu_stall_o activated as soon as bp occurs.
//
// Revision 1.2 2004/01/17 17:01:14 mohor
// Almost finished.
//
// Revision 1.1 2004/01/16 14:53:33 mohor
// *** empty log message ***
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
module dbg_cpu_registers (
data_i,
we_i,
tck_i,
bp_i,
rst_i,
cpu_clk_i,
ctrl_reg_o,
cpu_stall_o,
cpu_rst_o
);
input [`DBG_CPU_CTRL_LEN -1:0] data_i;
input we_i;
input tck_i;
input bp_i;
input rst_i;
input cpu_clk_i;
output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
output cpu_stall_o;
output cpu_rst_o;
reg cpu_reset;
wire [2:1] cpu_op_out;
reg stall_bp, stall_bp_csff, stall_bp_tck;
reg stall_reg, stall_reg_csff, stall_reg_cpu;
reg cpu_reset_csff;
reg cpu_rst_o;
// Breakpoint is latched and synchronized. Stall is set and latched.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i)
stall_bp <= 1'b0;
else if(bp_i)
stall_bp <= 1'b1;
else if(stall_reg_cpu)
stall_bp <= 1'b0;
end
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
stall_bp_csff <= 1'b0;
stall_bp_tck <= 1'b0;
end
else
begin
stall_bp_csff <= stall_bp;
stall_bp_tck <= stall_bp_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
stall_reg_csff <= 1'b0;
stall_reg_cpu <= 1'b0;
end
else
begin
stall_reg_csff <= stall_reg;
stall_reg_cpu <= stall_reg_csff;
end
end
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
// Writing data to the control registers (stall)
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
stall_reg <= 1'b0;
else if (stall_bp_tck)
stall_reg <= 1'b1;
else if (we_i)
stall_reg <= data_i[0];
end
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cpu_reset <= 1'b0;
else if(we_i)
cpu_reset <= data_i[1];
end
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_reset_csff <= 1'b0;
cpu_rst_o <= 1'b0;
end
else
begin
cpu_reset_csff <= cpu_reset;
cpu_rst_o <= cpu_reset_csff;
end
end
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int dx[] = {0, 0, -1, 1}; const int dy[] = {1, -1, 0, 0}; const int N = 505; int n, m; char adj[N][N]; bool vis[N][N]; struct node { int type, x, y; node() {} node(int type, int x, int y) : type(type), x(x), y(y) {} void print() { if (type == 0) putchar( B ); else if (type == 1) putchar( R ); else putchar( D ); printf( %d %d n , x + 1, y + 1); } }; vector<node> ans; void dfs(int x, int y) { vis[x][y] = 1; for (int i = 0; i < 4; i++) { int xx = x + dx[i]; int yy = y + dy[i]; if (xx >= 0 && xx < n && yy >= 0 && yy < m && vis[xx][yy] == 0) { ans.push_back(node(0, xx, yy)); dfs(xx, yy); ans.push_back(node(2, xx, yy)); ans.push_back(node(1, xx, yy)); } } } int main() { while (scanf( %d%d , &n, &m) != EOF) { ans.clear(); memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) scanf( %s , adj[i]); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (adj[i][j] == # ) vis[i][j] = 1; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) if (vis[i][j] == 0) { ans.push_back(node(0, i, j)); dfs(i, j); } } int len = (int)ans.size(); printf( %d n , len); for (int i = 0; i < len; i++) ans[i].print(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n < 3) { cout << -1; return 0; } if (n == 3) { cout << 210; return 0; } int A[] = {50, 80, 170, 20, 200, 110}; int nA[] = {2, 2, 3, 2, 3, 3}; int j = 0; for (int i = 4; i <= n; i++) { if (j == 6) j = 0; if (i == n) { cout << 1; for (int k = 1; k < n - nA[j]; k++) { cout << 0 ; } cout << A[j]; } j++; } return 0; }
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#include <bits/stdc++.h> using namespace std; long long t, n, sum, t1, ans; string st; int main() { cin >> t; while (t--) { cin >> n; cin >> st; int a = 0, b = 0; for (int i = 0; i < n; i++) { if (st[i] == ( ) a++; if (st[i] == ) ) { if (a) a--; else b++; } } cout << min(a, b) << n ; } }
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module opc3cpu( inout[15:0] data, output[15:0] address, output rnw, input clk, input reset_b);
parameter FETCH0=0, FETCH1=1, RDMEM=2, RDMEM2=3, EXEC=4 ;
parameter AND=5'bx0000, LDA=5'bx0001, NOT=5'bx0010, ADD=5'bx0011;
parameter LDAP=5'b01001, STA=5'b11000, STAP=5'b01000;
parameter JPC=5'b11001, JPZ=5'b11010, JP=5'b11011, JSR=5'b11100;
parameter RTS=5'b11101, BSW=5'b11110;
reg [15:0] OR_q, PC_q;
reg [15:0] ACC_q;
reg [2:0] FSM_q;
reg [4:0] IR_q;
reg C_q;
wire writeback_w = ((FSM_q == EXEC) && (IR_q == STA || IR_q == STAP)) & reset_b ;
assign rnw = ~writeback_w ;
assign data = (writeback_w)?ACC_q:16'bz ;
assign address = ( writeback_w || FSM_q == RDMEM || FSM_q==RDMEM2)? OR_q:PC_q;
always @ (posedge clk or negedge reset_b )
if (!reset_b)
FSM_q <= FETCH0;
else
case(FSM_q)
FETCH0 : FSM_q <= FETCH1;
FETCH1 : FSM_q <= (IR_q[4])?EXEC:RDMEM ;
RDMEM : FSM_q <= (IR_q==LDAP)?RDMEM2:EXEC;
RDMEM2 : FSM_q <= EXEC;
EXEC : FSM_q <= FETCH0;
endcase
always @ (posedge clk)
begin
IR_q <= (FSM_q == FETCH0)? data[15:11] : IR_q;
OR_q[15:0] <= data ;
if ( FSM_q == EXEC )
casex (IR_q)
JSR : ACC_q <= PC_q ;
AND : {C_q, ACC_q} <= {1'b0, ACC_q & OR_q};
BSW : ACC_q <= {ACC_q[7:0], ACC_q[15:8]};
NOT : ACC_q <= ~OR_q;
LDA : ACC_q <= OR_q;
LDAP : ACC_q <= OR_q;
ADD : {C_q,ACC_q} <= ACC_q + C_q + OR_q;
default: {C_q,ACC_q} <= {C_q,ACC_q};
endcase
end
always @ (posedge clk or negedge reset_b )
if (!reset_b) // On reset start execution at 0x00 to leave page zero clear for variables
PC_q <= 16'h0000;
else
if ( FSM_q == FETCH0 || FSM_q == FETCH1 )
PC_q <= PC_q + 1;
else
case (IR_q)
JP : PC_q <= OR_q;
JPC : PC_q <= (C_q)?OR_q:PC_q;
JPZ : PC_q <= ~(|ACC_q)?OR_q:PC_q;
JSR : PC_q <= OR_q;
RTS : PC_q <= ACC_q;
default: PC_q <= PC_q;
endcase
endmodule
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module membus_1_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_wr_rs,
input wire m_rq_cyc,
input wire m_rd_rq,
input wire m_wr_rq,
input wire [21:35] m_ma,
input wire [18:21] m_sel,
input wire m_fmc_select,
input wire [0:35] m_mb_write,
output wire m_addr_ack,
output wire m_rd_rs,
output wire [0:35] m_mb_read,
// Slave 0
output wire s0_wr_rs,
output wire s0_rq_cyc,
output wire s0_rd_rq,
output wire s0_wr_rq,
output wire [21:35] s0_ma,
output wire [18:21] s0_sel,
output wire s0_fmc_select,
output wire [0:35] s0_mb_write,
input wire s0_addr_ack,
input wire s0_rd_rs,
input wire [0:35] s0_mb_read
);
wire [0:35] mb_out = m_mb_write | s0_mb_read;
assign m_addr_ack = s0_addr_ack;
assign m_rd_rs = s0_rd_rs;
assign m_mb_read = mb_out;
assign s0_wr_rs = m_wr_rs;
assign s0_rq_cyc = m_rq_cyc;
assign s0_rd_rq = m_rd_rq;
assign s0_wr_rq = m_wr_rq;
assign s0_ma = m_ma;
assign s0_sel = m_sel;
assign s0_fmc_select = m_fmc_select;
assign s0_mb_write = mb_out;
endmodule
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#include <bits/stdc++.h> using namespace std; int dadsadasda; const int INF = 0x3f3f3f3f; const long long LLINF = 1e18; const int MAXN = 3e5; int n; int a[MAXN]; int ans[MAXN]; priority_queue<pair<int, int> > pq; int father[MAXN], siz[MAXN], cnt[MAXN]; void makeSet(int nn, int m) { for (int i = nn; i <= m; ++i) { father[i] = -1; siz[i] = 0; cnt[i] = 1; } } int find(int x) { if (father[x] == -1) return x; return father[x] = find(father[x]); } void unio(int x, int y) { if (siz[x] > siz[y]) { father[y] = x; cnt[x] += cnt[y]; } else { father[x] = y; cnt[y] += cnt[x]; if (siz[x] == siz[y]) siz[y]++; } } bool active[MAXN]; int main() { dadsadasda = scanf( %d , &n); for (int i = 0; i < n; i++) { dadsadasda = scanf( %d , &a[i]); pq.push({a[i], i}); } makeSet(0, n - 1); while (!pq.empty()) { auto p = pq.top(); pq.pop(); active[p.second] = true; if (p.second > 0 && find(p.second) != find(p.second - 1) && active[p.second - 1]) unio(find(p.second), find(p.second - 1)); if (p.second < n - 1 && find(p.second) != find(p.second + 1) && active[p.second + 1]) unio(find(p.second), find(p.second + 1)); int sz = cnt[find(p.second)]; ans[sz] = max(ans[sz], p.first); } for (int i = n - 1; i >= 1; i--) { ans[i] = max(ans[i], ans[i + 1]); } for (int i = 1; i < n + 1; i++) { printf( %d , ans[i]); } printf( n ); return 0; }
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