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#include <bits/stdc++.h> const int maxn = 3e5 + 5; using namespace std; long long n, m; int main() { scanf( %d%d , &n, &m); if (min(n, m) == 1) { long long t = max(n, m); long long ti = t / 6, res = t % 6; printf( %lld n , ti * 6 + max(0ll, res - 3) * 2); return 0; } if ((n % 2) && (m % 2)) { printf( %lld n , n * m - 1); } else if (n % 2 == 0 && m % 2 == 0) { if (max(n, m) <= 2) printf( 0 n ); else printf( %lld n , n * m); } else { if (min(n, m) == 2) { long long t = max(n, m); if (t == 3 || t == 7) printf( %lld n , n * m - 2); else printf( %lld n , n * m); } else printf( %lld n , n * m); } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; long double r, v; long double eps = 1e-8; const long double mpi = acos(-1.0); inline long double dist(long double theta) { return 2.0L * r * (sin(theta) + theta); } inline double ti(long double theta, long long ni) { return 2.0L * r * (mpi * ni + theta) / v; } void solve() { int si, fi; scanf( %d%d , &si, &fi); long double d = fi - si; long long ni = d / (2.0L * mpi * r); long double left = 0; long double right = mpi; d -= 2.0L * r * mpi * ni; long double dleft = dist(left); long double dright = dist(right); long double e = eps * v; while (dright - dleft > e) { long double mid = (right + left) / 2.0L; long double dmid = dist(mid); if (dmid > d) { right = mid; dright = dmid; } else { left = mid; dleft = dmid; } } double res = ti(right, ni); printf( %.10f n , res); return; } int main() { int n, ri, vi; scanf( %d%d%d , &n, &ri, &vi); r = ri; v = vi; while (n--) { solve(); } cout.flush(); return 0; }
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#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int INF = 1000000000; const int MOD = 1000000007; long long b(long long a, long long n, long long mod) { if (n == 0) { return 1; } if (n == 1) { return a % mod; } long long t = b(a, n / 2, mod); t *= t; t %= mod; if (n % 2) { t *= a; } t %= mod; return t; } int main() { long long n, m; cin >> n >> m; cout << (b(3, n, m) - 1 + m) % m; return 0; }
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`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
`define LABEL_LOOP 8'd2
`define LABEL_LOOP1 8'd9
`define LABEL_LOOP2 8'd16
`define LABEL_LOOP3 8'd23
`define LABEL_LOOP4 8'd30
`define LABEL_LOOP5 8'd37
`define LABEL_LOOP6 8'd44
`define LABEL_LOOP7 8'd51
`define LABEL_LOOP8 8'd58
`define LABEL_LOOP9 8'd65
`define LABEL_LOOP10 8'd72
`define LABEL_CONTINUE 8'd5
`define LABEL_CONTINUE1 8'd8
`define LABEL_CONTINUE2 8'd12
`define LABEL_CONTINUE3 8'd15
`define LABEL_CONTINUE4 8'd19
`define LABEL_CONTINUE5 8'd22
`define LABEL_CONTINUE6 8'd26
`define LABEL_CONTINUE7 8'd29
`define LABEL_CONTINUE8 8'd33
`define LABEL_CONTINUE9 8'd36
`define LABEL_CONTINUE10 8'd40
`define LABEL_CONTINUE11 8'd43
`define LABEL_CONTINUE12 8'd47
`define LABEL_CONTINUE13 8'd50
`define LABEL_CONTINUE14 8'd54
`define LABEL_CONTINUE15 8'd57
`define LABEL_CONTINUE16 8'd61
`define LABEL_CONTINUE17 8'd64
`define LABEL_CONTINUE18 8'd68
`define LABEL_CONTINUE19 8'd71
`define LABEL_CONTINUE20 8'd75
`define LABEL_CONTINUE21 8'd78
always @ ( iAddress )
begin
case (iAddress)
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R1,16'd72 };//carga H
//LABEL_LOOP:
2: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
3: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE ,16'd0 };
4: oInstruction = { `JMP , `LABEL_LOOP ,16'd0 };
//LABEL_CONTINUE
5: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
6: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE1 ,16'd0 };
7: oInstruction = { `JMP , `LABEL_CONTINUE ,16'd0 };
//`LABEL_CONTINUE1
8: oInstruction = { `STO , `R1,16'd101 };//carga E
//LABEL_LOOP1:
9: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
10: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE2 ,16'd0 };
11: oInstruction = { `JMP , `LABEL_LOOP1 ,16'd0 };
//`LABEL_CONTINUE2
12: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
13: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE3 ,16'd0 };
14:oInstruction = { `JMP , `LABEL_CONTINUE2 ,16'd0 };
//`LABEL_CONTINUE3
15: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP2:
16: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
17: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE4 ,16'd0 };
18: oInstruction = { `JMP , `LABEL_LOOP2 ,16'd0 };
//`LABEL_CONTINUE4
19: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
20: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE5 ,16'd0 };
21: oInstruction = { `JMP , `LABEL_CONTINUE4 ,16'd0 };
//`LABEL_CONTINUE5
22: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP3:
23: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
24: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE6 ,16'd0 };
25: oInstruction = { `JMP , `LABEL_LOOP3 ,16'd0 };
//`LABEL_CONTINUE6
26: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
27: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE7 ,16'd0 };
28: oInstruction = { `JMP , `LABEL_CONTINUE6 ,16'd0 };
//`LABEL_CONTINUE7
29: oInstruction = { `STO , `R1,16'd111 };//carga O
//LABEL_LOOP4:
30: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
31: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE8 ,16'd0 };
32: oInstruction = { `JMP , `LABEL_LOOP4 ,16'd0 };
//`LABEL_CONTINUE8
33: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
34: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE9 ,16'd0 };
35: oInstruction = { `JMP , `LABEL_CONTINUE8 ,16'd0 };
//`LABEL_CONTINUE9
36: oInstruction = { `STO , `R1,16'd32 };//carga space
//LABEL_LOOP5:
37: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
38: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE10 ,16'd0 };
39: oInstruction = { `JMP , `LABEL_LOOP5 ,16'd0 };
//`LABEL_CONTINUE10
40: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
41: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE11 ,16'd0 };
42: oInstruction = { `JMP , `LABEL_CONTINUE10 ,16'd0 };
//`LABEL_CONTINUE11
43: oInstruction = { `STO , `R1,16'd119 };//carga W
//LABEL_LOOP6:
44: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
45: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE12 ,16'd0 };
46: oInstruction = { `JMP , `LABEL_LOOP6 ,16'd0 };
//`LABEL_CONTINUE12
47: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
48: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE13 ,16'd0 };
49: oInstruction = { `JMP , `LABEL_CONTINUE12 ,16'd0 };
//`LABEL_CONTINUE13
50: oInstruction = { `STO , `R1,16'd111 };//carga O
//LABEL_LOOP7:
51: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
52: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE14 ,16'd0 };
53: oInstruction = { `JMP , `LABEL_LOOP7 ,16'd0 };
//`LABEL_CONTINUE14
54: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
55: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE15 ,16'd0 };
56: oInstruction = { `JMP , `LABEL_CONTINUE14 ,16'd0 };
//`LABEL_CONTINUE15
57: oInstruction = { `STO , `R1,16'd111 };//carga R
//LABEL_LOOP8:
58: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
59: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE16 ,16'd0 };
60: oInstruction = { `JMP , `LABEL_LOOP8 ,16'd0 };
//`LABEL_CONTINUE16
61: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
62: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE17 ,16'd0 };
63: oInstruction = { `JMP , `LABEL_CONTINUE16 ,16'd0 };
//`LABEL_CONTINUE17
64: oInstruction = { `STO , `R1,16'd108 };//carga L
//LABEL_LOOP9:
65: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
66: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE18 ,16'd0 };
67: oInstruction = { `JMP , `LABEL_LOOP9 ,16'd0 };
//`LABEL_CONTINUE18
68: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
69: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE19 ,16'd0 };
70: oInstruction = { `JMP , `LABEL_CONTINUE18 ,16'd0 };
//`LABEL_CONTINUE19
71: oInstruction = { `STO , `R1,16'd100 };//carga D
//LABEL_LOOP10:
72: oInstruction = { `LCD , 8'd0, `R1 , 8'd0 };
73: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE20 ,16'd0 };
74: oInstruction = { `JMP , `LABEL_LOOP10 ,16'd0 };
//`LABEL_CONTINUE20
75: oInstruction = { `SLH , 8'd0, `R1 , 8'd0 };
76: oInstruction = { `BRANCH_IF_NSYNC , `LABEL_CONTINUE21 ,16'd0 };
77: oInstruction = { `JMP , `LABEL_CONTINUE20 ,16'd0 };
//`LABEL_CONTINUE21
78: oInstruction = { `STO , `R1,16'd100 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int read() { int s = 0; char c = getchar(), lc = + ; while (c < 0 || 9 < c) lc = c, c = getchar(); while ( 0 <= c && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return lc == - ? -s : s; } void write(int x) { if (x < 0) { putchar( - ); x = -x; } if (x < 10) putchar(x + 0 ); else { write(x / 10); putchar(x % 10 + 0 ); } } void print(int x, char c = n ) { write(x); putchar(c); } void L(int x) { putchar( L ); putchar( ); print(x); } void R(int x) { putchar( R ); putchar( ); print(x); } char a[N]; signed main() { scanf( %s , a + 1); int n = strlen(a + 1); print(4); L(2); L(2); R(2); R(n + 2 + n - 1); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
`define SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probec_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD2_PP_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd2 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD2_PP_SYMBOL_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: upd77c25_pgmrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module upd77c25_pgmrom (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [23:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "49152"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long a[1003]; int main() { long long n, s; cin >> n >> s; long long miner = 0x3f3f3f3f3f3f3f3f; long long sumer = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; sumer += a[i]; miner = min(miner, a[i]); } if (sumer < s) { cout << -1 << endl; return 0; } sumer = 0; for (long long i = 0; i < n; i++) { sumer += a[i] - miner; a[i] = miner; } if (sumer >= s) { cout << miner << endl; } else { long long need = s - sumer; miner -= need / n; if (need % n != 0) { miner--; } cout << miner << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; char s[N]; int n, f[N], mk[N], cnt[N]; vector<int> p; void init() { for (int i = 2; i < N; i++) if (!mk[i]) { p.push_back(i); for (int j = i + i; j < N; j += i) mk[j] = true; } } int main() { scanf( %s , s + 1); n = strlen(s + 1); init(); memset(mk, 0, sizeof(mk)); for (int i = 0; i < p.size(); i++) { if (p[i] * 2 > n) break; for (int j = 1; j * p[i] <= n; j++) mk[p[i] * j] = true; } int tot = 0, mx = 0, pos; for (int i = 1; i <= n; i++) { cnt[s[i] - a ]++; if (mk[i]) tot++; } for (int i = 0; i < 26; i++) if (mx < cnt[i]) mx = cnt[i], pos = i; if (mx < tot) { cout << NO << n ; return 0; } puts( YES ); for (int i = 1; i <= n; i++) { if (mk[i]) printf( %c , a + pos), cnt[pos]--, tot--; else for (int j = 0; j < 26; j++) if (j == pos && cnt[j] > tot || (j != pos && cnt[j])) { printf( %c , a + j); cnt[j]--; break; } } return 0; }
|
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p*2 + 3;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_r;
logic [width_p-1:0] a_r;
logic [width_p-1:0] b_r;
logic eq_lo;
logic lt_lo;
logic le_lo;
logic [width_p-1:0] min_lo;
logic [width_p-1:0] max_lo;
bsg_fpu_cmp #(
.e_p(8)
,.m_p(23)
) dut (
.a_i(a_r)
,.b_i(b_r)
,.eq_o(eq_lo)
,.lt_o(lt_lo)
,.le_o(le_lo)
,.lt_le_invalid_o()
,.eq_invalid_o()
,.min_o(min_lo)
,.max_o(max_lo)
,.min_max_invalid_o()
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_r)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
eq_lo
, lt_lo
, le_lo
, min_lo
, max_lo
};
logic [width_p-1:0] a_n, b_n;
logic v_n;
always_comb begin
if (v_r == 1'b0) begin
tr_yumi_li = tr_v_lo;
v_n = tr_v_lo;
{a_n, b_n} = tr_v_lo
? tr_data_lo[0+:width_p*2]
: {a_r, b_r};
end
else begin
tr_yumi_li = 1'b0;
v_n = tr_ready_lo
? 1'b0
: v_r;
{a_n, b_n} = {a_r, b_r};
end
end
always_ff @ (posedge clk) begin
if (reset) begin
v_r <= 1'b0;
a_r <= '0;
b_r <= '0;
end
else begin
v_r <= v_n;
a_r <= a_n;
b_r <= b_n;
end
end
initial begin
wait(done_lo);
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:18:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.v
// Design : system_xlconstant_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_0
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; int flag = 0, f = 0; cin >> s1 >> s2; int l = s1.length(); for (int i = 0; i < l; i++) { if (s1[i] < a ) { s1[i] += 32; } if (s2[i] < a ) s2[i] += 32; if (s1[i] != s2[i]) { f = i; flag = 1; break; } } if (flag == 0) cout << 0 ; else { if (s1[f] > s2[f]) cout << 1 ; else cout << -1 ; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:14:13 05/10/2015
// Design Name:
// Module Name: Expansion
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Expansion(
right,
ouput
);
input [32:1] right;
output reg [48:1] ouput;
wire [32:1] right;
always @ (right)
begin
ouput[1]<= right[32];
ouput[2]<= right[1];
ouput[3]<= right[2];
ouput[4]<= right[3];
ouput[5]<= right[4];
ouput[6]<= right[5];
ouput[7]<= right[4];
ouput[8]<= right[5];
ouput[9]<= right[6];
ouput[10]<= right[7];
ouput[11]<= right[8];
ouput[12]<= right[9];
ouput[13]<= right[8];
ouput[14]<= right[9];
ouput[15]<= right[10];
ouput[16]<= right[11];
ouput[17]<= right[12];
ouput[18]<= right[13];
ouput[19]<= right[12];
ouput[20]<= right[13];
ouput[21]<= right[14];
ouput[22]<= right[15];
ouput[23]<= right[16];
ouput[24]<= right[17];
ouput[25]<= right[16];
ouput[26]<= right[17];
ouput[27]<= right[18];
ouput[28]<= right[19];
ouput[29]<= right[20];
ouput[30]<= right[21];
ouput[31]<= right[20];
ouput[32]<= right[21];
ouput[33]<= right[22];
ouput[34]<= right[23];
ouput[35]<= right[24];
ouput[36]<= right[25];
ouput[37]<= right[24];
ouput[38]<= right[25];
ouput[39]<= right[26];
ouput[40]<= right[27];
ouput[41]<= right[28];
ouput[42]<= right[29];
ouput[43]<= right[28];
ouput[44]<= right[29];
ouput[45]<= right[30];
ouput[46]<= right[31];
ouput[47]<= right[32];
ouput[48]<= right[1];
end
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:48:31 MST 2014
// Date : Tue Feb 10 12:36:17 2015
// Host : austin_workstation_1 running 64-bit Fedora release 20 (Heisenbug)
// Command : write_verilog -force -mode synth_stub
// /home/luis/FIRMWARE/git/vhdl/ip_blocks/sip_capture_x4/src/fifo_64_in_out/fifo_64in_out_stub.v
// Design : fifo_64in_out
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1157-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.4" *)
module fifo_64in_out(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, valid, rd_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[63:0],wr_en,rd_en,dout[63:0],full,empty,valid,rd_data_count[11:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
output valid;
output [11:0]rd_data_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, mnPre[(100005)], mxPre[(100005)], mnSuf[(100005)], mxSuf[(100005)]; pair<int, int> a[2][(100005)]; long long solve(int ax) { sort(a[ax] + 1, a[ax] + 1 + n); for (int i = 1; i <= n; ++i) { mnPre[i] = min(mnPre[i - 1], a[ax][i].second); mxPre[i] = max(mxPre[i - 1], a[ax][i].second); } for (int i = n; i >= 1; --i) { mnSuf[i] = min(mnSuf[i + 1], a[ax][i].second); mxSuf[i] = max(mxSuf[i + 1], a[ax][i].second); } long long r = (1LL << 60) - 1; long long m = 0; int mn, mx; for (int i = 59; i >= 0; --i) { bool allowed = 0; m = r - (1LL << i); allowed = (1LL * (a[ax][n].first - a[ax][1].first) * (a[ax][n].first - a[ax][1].first)) <= m; for (int en = 1, st = 1; en <= n && !allowed; ++en) { while ((1LL * (a[ax][en].first - a[ax][st].first) * (a[ax][en].first - a[ax][st].first)) > m) ++st; mn = min(mnPre[st - 1], mnSuf[en + 1]); mx = max(mxPre[st - 1], mxSuf[en + 1]); allowed = (1LL * (mx - mn) * (mx - mn)) <= m && max((1LL * (mn) * (mn)), (1LL * (mx) * (mx))) + max((1LL * (a[ax][en].first) * (a[ax][en].first)), (1LL * (a[ax][st].first) * (a[ax][st].first))) <= m; } if (allowed) r -= (1LL << i); } return r; } int main() { scanf( %d , &n); for (int i = 1, x, y; i <= n; ++i) { scanf( %d%d , &x, &y); a[0][i] = {x, y}, a[1][i] = {y, x}; } printf( %I64d , min(solve(0), solve(1))); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvn (
VPWR,
VGND,
Z ,
A ,
TE_B
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE_B;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_PP_SYMBOL_V
|
#include <bits/stdc++.h> struct sur { int c1, c2, c3, c4; inline bool colsame() { return c1 == c3 && c2 == c4 && c1 != c2; } inline bool same() { return c1 == c2 && c2 == c3 && c3 == c4; } inline void right_rotate() { int t = c4; c4 = c2; c2 = c1; c1 = c3; c3 = t; return; } inline void left_rotate() { int t = c4; c4 = c3; c3 = c1; c1 = c2; c2 = t; return; } inline void rotate() { int t = c1; c1 = c4; c4 = t; t = c2; c2 = c3; c3 = t; return; } inline void read() { scanf( %d%d%d%d , &c1, &c2, &c3, &c4); return; } friend inline bool round(sur s1, sur s2, sur s3, sur s4) { if (!(s1.colsame() && s2.colsame() && s3.colsame() && s4.colsame())) return 0; if (s1.c1 == s2.c2 && s2.c1 == s3.c2 && s3.c1 == s4.c2 && s4.c1 == s1.c2) return 1; if (s1.c2 == s2.c1 && s2.c2 == s3.c1 && s3.c2 == s4.c1 && s4.c2 == s1.c1) return 1; return 0; } } code[7]; template <class Tp> inline void swap(Tp &a, Tp &b) { Tp t = a; a = b; b = t; return; } int main() { int i; for (i = 1; i <= 6; i++) code[i].read(); if (code[4].same() && code[5].same()) { code[6].rotate(); puts(round(code[1], code[2], code[3], code[6]) ? YES : NO ); } else if (code[1].same() && code[3].same()) { code[4].right_rotate(); code[2].right_rotate(); code[5].right_rotate(); code[6].right_rotate(); puts(round(code[4], code[2], code[5], code[6]) ? YES : NO ); } else if (code[2].same() && code[6].same()) { code[1].right_rotate(); code[3].left_rotate(); code[4].rotate(); puts(round(code[4], code[1], code[5], code[3]) ? YES : NO ); } else puts( NO ); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 Yossi Nivin.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [15:0] in16;
reg [31:0] in32;
reg [63:0] in64;
// Non-standard size
reg [9:0] in10;
reg [20:0] in21;
reg [58:0] in59;
reg [69:0] in70;
reg [31:0] ctrl0;
reg [31:0] ctrl1;
reg [31:0] ctrl2;
reg [4:0] result_16_1;
reg [4:0] result_16_2;
reg [4:0] result_16_3;
reg [5:0] result_32_1;
reg [5:0] result_32_2;
reg [5:0] result_32_3;
reg [6:0] result_64_1;
reg [6:0] result_64_2;
reg [6:0] result_64_3;
reg [3:0] result_10_3;
reg [4:0] result_21_3;
reg [5:0] result_59_3;
reg [6:0] result_70_3;
initial begin
if ($countbits(32'b111100000000, '1) != 4) $stop;
if ($countbits(32'b111100000000, '0) != 28) $stop;
if ($countbits(32'b111100000000, '0, '1) != 32) $stop;
if ($countbits(4'bxxx0, 'x) != 3) $stop;
if ($countbits(4'bzzz0, 'z) != 3) $stop;
if ($countbits(4'b1zz0, 'z, '0) != 3) $stop;
if ($countbits(4'b1xx0, 'x, '0) != 3) $stop;
if ($countbits(4'b1xx0, 'x, '0, '1) != 4) $stop;
if ($countbits(4'bzzx0, 'x, 'z) != 3) $stop;
end
always @* begin
result_16_1 = $countbits(in16, ctrl0);
result_16_2 = $countbits(in16, ctrl0, ctrl1);
result_16_3 = $countbits(in16, ctrl0, ctrl1, ctrl2);
result_32_1 = $countbits(in32, ctrl0);
result_32_2 = $countbits(in32, ctrl0, ctrl1);
result_32_3 = $countbits(in32, ctrl0, ctrl1, ctrl2);
result_64_1 = $countbits(in64, ctrl0);
result_64_2 = $countbits(in64, ctrl0, ctrl1);
result_64_3 = $countbits(in64, ctrl0, ctrl1, ctrl2);
result_10_3 = $countbits(in10, ctrl0, ctrl1, ctrl2);
result_21_3 = $countbits(in21, ctrl0, ctrl1, ctrl2);
result_59_3 = $countbits(in59, ctrl0, ctrl1, ctrl2);
result_70_3 = $countbits(in70, ctrl0, ctrl1, ctrl2);
end
logic [31:0] val = 32'h70008421;
integer cyc = 0;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 0) begin
// Constants
if ($countbits(32'b11001011101, '1) != 7) $stop;
if ($countbits(32'b11001011101, '1, 'z) != 7) $stop;
if ($countbits(32'b11001011101, '1, '0) != 32) $stop;
if ($countbits(20'b11001011101, '1, '0) != 20) $stop;
if ($countbits(20'b1100x01z101, '1, '0) != 18) $stop;
if ($countbits(20'b1100x01z101, 2, 2'bx1) != 18) $stop;
if ($countbits(32'b1100x01z101, 'x, 'z) != 2) $stop;
if ($countbits(32'b1100x01z101, 'x, 'z, '1) != 7) $stop;
if ($countbits(val, '1) != 7) $stop;
if ($countones(val) != 7) $stop;
if ($countbits(val, '0) != 25) $stop;
if ($countbits(val, '0, '1) != 32) $stop;
// Optimization may depend on position of X, so need to walk it
if ($countbits(val, 'x) != 0) $stop;
if ($countbits(val, 'x, '1) != 7) $stop;
if ($countbits(val, '1, 'x) != 7) $stop;
if ($countbits(val, '1, '1, 'x) != 7) $stop;
if ($countbits(val, 'x, '0) != 25) $stop;
if ($countbits(val, 'x, '0, '1) != 32) $stop;
// Optimization may depend on position of Z, so need to walk it
if ($countbits(val, 'z) != 0) $stop;
if ($countbits(val, 'z, '1) != 7) $stop;
if ($countbits(val, '1, 'z) != 7) $stop;
if ($countbits(val, '1, '1, 'z) != 7) $stop;
if ($countbits(val, 'z, '0) != 25) $stop;
if ($countbits(val, 'z, '0, '1) != 32) $stop;
//
if ($countbits(val, 'x, 'z) != 0) $stop;
end
else if (cyc == 1) begin
in16 <= 16'h0AF0;
in32 <= 32'hA0F300;
in64 <= 64'hA5A5A5A5A5A5A5A5;
in10 <= 10'b1010_1011;
in21 <= 21'h10F102;
in59 <= 59'h7050137210;
in70 <= 70'hF00030008000;
ctrl0 <= '0;
ctrl1 <= '1;
ctrl2 <= '1;
end
else if (cyc == 2) begin
if (result_16_1 != 10) $stop;
if (result_16_2 != 16) $stop;
if (result_16_3 != 16) $stop;
if (result_32_1 != 24) $stop;
if (result_32_2 != 32) $stop;
if (result_32_3 != 32) $stop;
if (result_64_1 != 32) $stop;
if (result_64_2 != 64) $stop;
if (result_64_3 != 64) $stop;
if (result_10_3 != 10) $stop;
if (result_21_3 != 21) $stop;
if (result_59_3 != 59) $stop;
if (result_70_3 != 70) $stop;
in16 <= 16'h82B;
in32 <= 32'h305372;
in64 <= 64'h7777777777777777;
in10 <= 10'b1001_0111;
in21 <= 21'h91040C;
in59 <= 59'h12345678;
in70 <= 70'hF11111111;
// Confirm upper bits of the control arguments are ignored
ctrl0 <= 5;
ctrl1 <= 3;
ctrl2 <= 2;
end
else if (cyc == 3) begin
if (result_16_1 != 5) $stop;
if (result_16_2 != 5) $stop;
if (result_16_3 != 16) $stop;
if (result_32_1 != 10) $stop;
if (result_32_2 != 10) $stop;
if (result_32_3 != 32) $stop;
if (result_64_1 != 48) $stop;
if (result_64_2 != 48) $stop;
if (result_64_3 != 64) $stop;
if (result_10_3 != 10) $stop;
if (result_21_3 != 21) $stop;
if (result_59_3 != 59) $stop;
if (result_70_3 != 70) $stop;
end
else if (cyc == 4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000009; long long poww(long long base, long long power) { long long ret = 1; for (long long i = 0; i < power; i++) { ret *= base; ret %= mod; } return ret; } int main() { long long ans; long long n, m; while (~scanf( %I64d%I64d , &n, &m)) { ans = 1; long long sum = poww(2, m); for (long long i = 1; i <= n; i++) { ans *= (sum - i); ans %= mod; } printf( %I64d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; namespace GR1 { vector<int> solve(int N, int num_exact_matches, int num_common, const vector<int>& B) { vector<queue<int> > pos(N + 2); for (int i = 0, _n = (N); i < _n; ++i) { int b = B[i]; pos[b].push(i); } int missing = 0; set<pair<int, int>, greater<pair<int, int> > > S; for (int v = (1), _b = (N + 1); v <= _b; ++v) if (!pos[v].empty()) S.emplace(int((pos[v]).size()), v); else missing = v; assert(missing > 0); vector<int> res(N); vector<bool> exact(N); for (int t = 0, _n = (num_exact_matches); t < _n; ++t) { auto it = S.begin(); int v = it->second; S.erase(it); queue<int>& q = pos[v]; int i = q.front(); q.pop(); res[i] = v; exact[i] = true; if (!q.empty()) S.emplace(int((q).size()), v); } int num_mismatches = N - num_common; int max_freq = S.begin()->first; if (max_freq * 2 > N - num_exact_matches + num_mismatches) return {}; vector<int> block; for (auto it : S) { int v = it.second; while (!pos[v].empty()) { int j = pos[v].front(); pos[v].pop(); block.push_back(j); } } for (int t = 0, _n = ((N - num_exact_matches) / 2); t < _n; ++t) block.push_back(block[t]); for (int k = 0, _n = (N - num_exact_matches); k < _n; ++k) { int i = block[k]; int j = block[k + (N - num_exact_matches) / 2]; res[i] = B[j]; }; ; for (int i = 0, _n = (N); i < _n; ++i) { if (exact[i]) continue; if (res[i] == B[i]) { assert(num_mismatches > 0); --num_mismatches; res[i] = missing; } }; ; for (int i = 0; i < N && num_mismatches > 0; ++i) { if (exact[i] || res[i] == missing) continue; --num_mismatches; res[i] = missing; } assert(num_mismatches == 0); return res; } } // namespace GR1 namespace GR2 { vector<int> solve(int N, int num_exact_matches, int num_common, const vector<int>& B) { vector<queue<int> > pos(N + 2); for (int i = 0, _n = (N); i < _n; ++i) { int b = B[i]; pos[b].push(i); } int missing = 0; set<pair<int, int>, greater<pair<int, int> > > S; for (int v = (1), _b = (N + 1); v <= _b; ++v) if (!pos[v].empty()) S.emplace(int((pos[v]).size()), v); else missing = v; assert(missing > 0); vector<int> res(N); for (int t = 0, _n = (num_exact_matches); t < _n; ++t) { auto it = S.begin(); int v = it->second; S.erase(it); queue<int>& q = pos[v]; int i = q.front(); q.pop(); res[i] = v; if (!q.empty()) S.emplace(int((q).size()), v); } int num_mismatches = N - num_common; num_common -= num_exact_matches; while (num_common > 0) { assert(!S.empty()); auto max_it = S.begin(); int v = max_it->second; S.erase(max_it); assert(!pos[v].empty()); int i = pos[v].front(); pos[v].pop(); if (B[i] == v) { if (int((S).size()) > 0) { auto max2_it = S.begin(); int w = max2_it->second; S.erase(max2_it); assert(!pos[w].empty()); int j = pos[w].front(); pos[w].pop(); if (!pos[w].empty()) S.emplace(int((pos[w]).size()), w); res[i] = w; --num_common; if (num_common > 0) { res[j] = v; --num_common; } } else if (num_mismatches > 0) { res[i] = missing; --num_mismatches; } else return {}; } else { res[i] = v; --num_common; } if (!pos[v].empty()) S.emplace(int((pos[v]).size()), v); } for (int i = 0, _n = (N); i < _n; ++i) { if (res[i] == 0) { assert(num_mismatches > 0); --num_mismatches; res[i] = missing; } } return res; } } // namespace GR2 int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(nullptr); int TC; cin >> TC; for (int tc = (1), _b = (TC); tc <= _b; ++tc) { int N, x, y; cin >> N >> x >> y; vector<int> B(N); for (int i = 0, _n = (N); i < _n; ++i) cin >> B[i]; vector<int> res = GR1::solve(N, x, y, B); if (res.empty()) cout << NO n ; else { cout << YES n ; for (int a : res) cout << a << ; cout << n ; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
|
// Test implicit casts during procedural non-blocking assignments.
module implicit_cast();
real src_r;
bit unsigned [7:0] src_u2;
bit signed [7:0] src_s2;
logic unsigned [7:0] src_u4;
logic signed [7:0] src_s4;
logic unsigned [7:0] src_ux;
logic signed [7:0] src_sx;
real dst_r;
bit unsigned [3:0] dst_u2s;
bit signed [3:0] dst_s2s;
bit unsigned [11:0] dst_u2l;
bit signed [11:0] dst_s2l;
logic unsigned [3:0] dst_u4s;
logic signed [3:0] dst_s4s;
logic unsigned [11:0] dst_u4l;
logic signed [11:0] dst_s4l;
bit failed;
initial begin
failed = 0;
src_r = -7;
src_u2 = 7;
src_s2 = -7;
src_u4 = 7;
src_s4 = -7;
src_ux = 8'bx0z00111;
src_sx = 8'bx0z00111;
$display("cast to real");
dst_r <= src_r; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r <= src_u2; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r <= src_s2; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r <= src_u4; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r <= src_s4; #1 $display("%g", dst_r); if (dst_r != -7.0) failed = 1;
dst_r <= src_ux; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
dst_r <= src_sx; #1 $display("%g", dst_r); if (dst_r != 7.0) failed = 1;
$display("cast to small unsigned bit");
dst_u2s <= src_r; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s <= src_u2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s <= src_s2; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s <= src_u4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s <= src_s4; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd9) failed = 1;
dst_u2s <= src_ux; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
dst_u2s <= src_sx; #1 $display("%d", dst_u2s); if (dst_u2s !== 4'd7) failed = 1;
$display("cast to small signed bit");
dst_s2s <= src_r; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s <= src_u2; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s <= src_s2; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s <= src_u4; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s <= src_s4; #1 $display("%d", dst_s2s); if (dst_s2s !== -4'sd7) failed = 1;
dst_s2s <= src_ux; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
dst_s2s <= src_sx; #1 $display("%d", dst_s2s); if (dst_s2s !== 4'sd7) failed = 1;
$display("cast to large unsigned bit");
dst_u2l <= src_r; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l <= src_u2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l <= src_s2; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l <= src_u4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd7) failed = 1;
dst_u2l <= src_s4; #1 $display("%d", dst_u2l); if (dst_u2l !== 12'd4089) failed = 1;
dst_u2l <= src_ux; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
dst_u2l <= src_sx; #1 $display("%b", dst_u2l); if (dst_u2l !== 12'b000000000111) failed = 1;
$display("cast to large signed bit");
dst_s2l <= src_r; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l <= src_u2; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l <= src_s2; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l <= src_u4; #1 $display("%d", dst_s2l); if (dst_s2l !== 12'sd7) failed = 1;
dst_s2l <= src_s4; #1 $display("%d", dst_s2l); if (dst_s2l !== -12'sd7) failed = 1;
dst_s2l <= src_ux; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
dst_s2l <= src_sx; #1 $display("%b", dst_s2l); if (dst_s2l !== 12'b000000000111) failed = 1;
$display("cast to small unsigned logic");
dst_u4s <= src_r; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s <= src_u2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s <= src_s2; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s <= src_u4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s <= src_s4; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd9) failed = 1;
dst_u4s <= src_ux; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
dst_u4s <= src_sx; #1 $display("%d", dst_u4s); if (dst_u4s !== 4'd7) failed = 1;
$display("cast to small signed logic");
dst_s4s <= src_r; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s <= src_u2; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s <= src_s2; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s <= src_u4; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s <= src_s4; #1 $display("%d", dst_s4s); if (dst_s4s !== -4'sd7) failed = 1;
dst_s4s <= src_ux; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
dst_s4s <= src_sx; #1 $display("%d", dst_s4s); if (dst_s4s !== 4'sd7) failed = 1;
$display("cast to large unsigned logic");
dst_u4l <= src_r; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l <= src_u2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l <= src_s2; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l <= src_u4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd7) failed = 1;
dst_u4l <= src_s4; #1 $display("%d", dst_u4l); if (dst_u4l !== 12'd4089) failed = 1;
dst_u4l <= src_ux; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'b0000x0z00111) failed = 1;
dst_u4l <= src_sx; #1 $display("%b", dst_u4l); if (dst_u4l !== 12'bxxxxx0z00111) failed = 1;
$display("cast to large signed logic");
dst_s4l <= src_r; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l <= src_u2; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l <= src_s2; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l <= src_u4; #1 $display("%d", dst_s4l); if (dst_s4l !== 12'sd7) failed = 1;
dst_s4l <= src_s4; #1 $display("%d", dst_s4l); if (dst_s4l !== -12'sd7) failed = 1;
dst_s4l <= src_ux; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'b0000x0z00111) failed = 1;
dst_s4l <= src_sx; #1 $display("%b", dst_s4l); if (dst_s4l !== 12'bxxxxx0z00111) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
reg signed [17:0] o_r;
assign o = o_r;
always @(posedge sys_clk) begin
if(load) begin
err = 18'd0;
o_r = init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive_r) begin
o_r = o_r + {1'b0, q_r};
if(correct)
o_r = o_r + 18'd1;
end else begin
o_r = o_r - {1'b0, q_r};
if(correct)
o_r = o_r - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_16to1_sel4_7_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
din11_WIDTH = 32,
din12_WIDTH = 32,
din13_WIDTH = 32,
din14_WIDTH = 32,
din15_WIDTH = 32,
din16_WIDTH = 32,
din17_WIDTH = 32,
dout_WIDTH = 32
)(
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [6 : 0] din5,
input [6 : 0] din6,
input [6 : 0] din7,
input [6 : 0] din8,
input [6 : 0] din9,
input [6 : 0] din10,
input [6 : 0] din11,
input [6 : 0] din12,
input [6 : 0] din13,
input [6 : 0] din14,
input [6 : 0] din15,
input [6 : 0] din16,
input [3 : 0] din17,
output [6 : 0] dout);
// puts internal signals
wire [3 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
wire [6 : 0] mux_1_2;
wire [6 : 0] mux_1_3;
wire [6 : 0] mux_1_4;
wire [6 : 0] mux_1_5;
wire [6 : 0] mux_1_6;
wire [6 : 0] mux_1_7;
// level 2 signals
wire [6 : 0] mux_2_0;
wire [6 : 0] mux_2_1;
wire [6 : 0] mux_2_2;
wire [6 : 0] mux_2_3;
// level 3 signals
wire [6 : 0] mux_3_0;
wire [6 : 0] mux_3_1;
// level 4 signals
wire [6 : 0] mux_4_0;
assign sel = din17;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = (sel[0] == 0)? din5 : din6;
assign mux_1_3 = (sel[0] == 0)? din7 : din8;
assign mux_1_4 = (sel[0] == 0)? din9 : din10;
assign mux_1_5 = (sel[0] == 0)? din11 : din12;
assign mux_1_6 = (sel[0] == 0)? din13 : din14;
assign mux_1_7 = (sel[0] == 0)? din15 : din16;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3;
assign mux_2_2 = (sel[1] == 0)? mux_1_4 : mux_1_5;
assign mux_2_3 = (sel[1] == 0)? mux_1_6 : mux_1_7;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
assign mux_3_1 = (sel[2] == 0)? mux_2_2 : mux_2_3;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fahcin (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM , A, B, ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> int main(void) { int m, n; char a[100001], b[100001]; scanf( %s , a); scanf( %s , b); n = strlen(a); m = strlen(b); if (n == m) { if (strcmp(a, b) == 0) printf( -1 ); else printf( %d , m); } else if (n > m) { printf( %d , n); } else printf( %d , m); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > adj[100005]; int dp[300005]; int x[300005]; int main() { ios_base::sync_with_stdio(0); int i, j; cin >> n >> m; while (m--) { int u, v, e; cin >> u >> v >> e; adj[e].push_back(make_pair(u, v)); } for (i = 1; i <= 1e5; i++) { for (j = 0; j < adj[i].size(); j++) { int u = adj[i][j].second; x[u] = 0; } for (j = 0; j < adj[i].size(); j++) { int u = adj[i][j].first; int v = adj[i][j].second; x[v] = max(x[v], dp[u] + 1); } for (j = 0; j < adj[i].size(); j++) { int u = adj[i][j].second; dp[u] = max(dp[u], x[u]); } } int res = 0; for (i = 1; i <= n; i++) res = max(res, dp[i]); cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tb[100], w1, w2, l = 1; int main() { scanf( %d , &n); for (int i = 0; i < n / 2; i++) scanf( %d , &tb[i]); sort(tb, tb + n / 2); for (int i = 0; i < n / 2; i++) { w1 += abs(tb[i] - l); l += 2; } l = 2; for (int i = 0; i < n / 2; i++) { w2 += abs(tb[i] - l); l += 2; } printf( %d , min(w1, w2)); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int a[N]; long long sum[N]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i); sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) sum[i] = sum[i - 1] + a[i]; long long ans_sum = 0; int ans_len = 0, pos = 1, len = 1; for (int i = 1; i <= n; i++) { int l = 0, r = min(i - 1, n - i); while (l < r) { int ml = (2 * l + r) / 3, mr = (2 * r + l + 2) / 3; long long suml = sum[i] - sum[i - ml - 1] + sum[n] - sum[n - ml]; long long sumr = sum[i] - sum[i - mr - 1] + sum[n] - sum[n - mr]; if (suml * (2 * mr + 1) < sumr * (2 * ml + 1)) l = ml + 1; else r = mr - 1; } long long tmp_sum = sum[i] - sum[i - l - 1] + sum[n] - sum[n - l] - (l * 2 + 1LL) * a[i]; if (tmp_sum * len > ans_sum * (2 * l + 1)) ans_sum = tmp_sum, ans_len = l, pos = i, len = 2 * l + 1; } printf( %d n , ans_len * 2 + 1); for (int i = pos - ans_len; i <= pos; i++) printf( %d , a[i]); for (int i = n - ans_len + 1; i <= n; i++) printf( %d , a[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; int c[80][80], m; struct tree { int n, ans[80], f[80][5000], g[80][5000]; int root, sum, siz[5000], w[5000], a[5000], tot; bool vis[5000]; vector<int> v[5000]; inline void getrt(int x, int fa) { siz[x] = 1; w[x] = 0; for (int i = 0; i < v[x].size(); i++) if (v[x][i] != fa && !vis[v[x][i]]) { getrt(v[x][i], x); siz[x] += siz[v[x][i]]; w[x] = max(w[x], siz[v[x][i]]); } w[x] = max(w[x], sum - siz[x]); if (!root || w[x] < w[root]) root = x; } inline void dfs(int x, int fa) { a[++tot] = x; siz[x] = 1; for (int i = 0; i < v[x].size(); i++) if (v[x][i] != fa && !vis[v[x][i]]) { dfs(v[x][i], x); siz[x] += siz[v[x][i]]; } } inline void work(int x) { tot = 0; dfs(x, 0); int i, j, k; memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); f[0][x] = g[0][x] = 1; for (i = 1; i <= m; i++) for (j = 1; j <= tot; j++) { for (k = 0; k < v[a[j]].size(); k++) { if (vis[v[a[j]][k]]) continue; if (a[j] != x) f[i][a[j]] = (f[i][a[j]] + f[i - 1][v[a[j]][k]]) % mod; g[i][a[j]] = (g[i][a[j]] + g[i - 1][v[a[j]][k]]) % mod; } } for (i = 1; i <= tot; i++) { if (a[i] == x) { for (j = 0; j <= m; j++) ans[j] = (ans[j] + g[j][a[i]]) % mod; } else { for (j = 0; j <= m; j++) for (k = 0; k + j <= m; k++) ans[k + j] = (ans[k + j] + (long long)f[j][a[i]] * g[k][a[i]] % mod) % mod; } } vis[x] = 1; for (i = 0; i < v[x].size(); i++) if (!vis[v[x][i]]) { root = 0; sum = siz[v[x][i]]; getrt(v[x][i], x); work(root); } } inline void solve() { sum = n; root = 0; memset(vis, 0, sizeof(vis)); memset(ans, 0, sizeof(ans)); getrt(1, 0); work(root); } }; tree t1, t2; int main() { int i, j, k; scanf( %d%d%d , &t1.n, &t2.n, &m); c[0][0] = 1; for (i = 1; i <= m; i++) c[i][i] = c[i][0] = 1; for (i = 1; i <= m; i++) for (j = 1; j < i; j++) c[i][j] = (c[i - 1][j] + c[i - 1][j - 1]) % mod; for (i = 0; i <= t1.n; i++) t1.v[i].clear(); for (i = 0; i <= t2.n; i++) t2.v[i].clear(); for (i = 1; i < t1.n; i++) { int x, y; scanf( %d%d , &x, &y); t1.v[x].push_back(y); t1.v[y].push_back(x); } for (i = 1; i < t2.n; i++) { int x, y; scanf( %d%d , &x, &y); t2.v[x].push_back(y); t2.v[y].push_back(x); } t1.solve(), t2.solve(); int Ans = 0; for (i = 0; i <= m; i++) Ans = (Ans + (long long)t1.ans[i] * t2.ans[m - i] % mod * c[m][i]) % mod; cout << Ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<pair<int, bool>> v(2 * n); for (int i = 0; i < 2 * n; i++) cin >> v[i].first, v[i].second = true; long long ans = 0, cc = 0; for (int i = 0; i < 2 * n; i++) { if (!v[i].second) continue; cc = 0; v[i].second = false; for (int j = i + 1; j < 2 * n; j++) { if (v[j].second && v[i].first != v[j].first) { cc++; } else if (v[i].first == v[j].first) { v[j].second = false; break; } } ans += cc; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int chill = 1; while (chill--) { solve(); } }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:1000000000 ) #pragma GCC optimize( Ofast,no-stack-protector ) using namespace std; const int maxn = (int)2e5 + 10; vector<int> ed[maxn]; int t[maxn], h[maxn]; long long dp[maxn][2]; void go(int v, int p) { vector<pair<long long, int> > g; int in = 0; int out = 0; long long sc = 0; for (int u : ed[v]) { if (u == p) { continue; } go(u, v); if (h[u] > h[v]) { out++; sc += dp[u][0]; } else if (h[u] < h[v]) { in++; sc += dp[u][1]; } else { out++; g.push_back(make_pair(-dp[u][0] + dp[u][1], u)); sc += dp[u][0]; } } sort((g).begin(), (g).end()); for (int it = 0; it < 2; it++) { if (p != -1) if (it == 0) { in++; } else { out++; } long long ans = (long long)1e18; long long cur = sc; for (int i = 0; i <= (int)g.size(); i++) { ans = min(ans, cur + max(in + i, out - i) * (long long)t[v]); if (i != (int)g.size()) cur += g[i].first; } dp[v][it] = ans; if (p != -1) if (it == 0) { in--; } else { out--; } } } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { scanf( %d , &t[i]); } for (int i = 0; i < n; i++) { scanf( %d , &h[i]); } for (int i = 0; i < n - 1; i++) { int x, y; scanf( %d %d , &x, &y); x--; y--; ed[x].push_back(y); ed[y].push_back(x); } go(0, -1); cout << dp[0][0] << n ; }
|
#include <bits/stdc++.h> using namespace std; const long double PI = acos(-1); const long long MOD = 1000000007; const long long FMOD = 998244353; long long cnt1, cnt2, x, y; bool isSafe(long long mid) { long long div1 = mid / x; long long div2 = mid / y; long long div3 = mid / (x * y); long long no = mid - (div1 + div2 - div3); long long p = div1 - div3; long long q = div2 - div3; long long ans1 = cnt1 - q; long long ans2 = cnt2 - p; if (ans1 < 0) ans1 = 0; if (ans2 < 0) ans2 = 0; return (ans1 + ans2) <= no; } signed main() { cin >> cnt1 >> cnt2 >> x >> y; long long beg = 0, end = 1e10; long long ans = 0; while (beg <= end) { long long mid = (beg + end) / 2; if (isSafe(mid)) { ans = mid; end = mid - 1; } else { beg = mid + 1; } } cout << ans; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_32x24.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Coding style changed.
//
// Revision 1.3 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.2 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1 2004/04/08 11:00:46 simont
// Add support for 512B instruction cache.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_32x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [31:24] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [31:24] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
`endif
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(1'b0),
.ADDR({3'h0, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(1'b0),
.ADDR({3'h0, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(1'b0),
.ADDR({4'b0000, addr}),
.DI({8'h00, di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
addr_reg <= {aw{1'b0}};
else if (ce)
addr_reg <= addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module aes_192 (state, key, out);
input [127:0] state;
input [191:0] key;
output [127:0] out;
reg [127:0] s0;
reg [191:0] k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
always @ (*)
begin
s0 <= state ^ key[191:64];
k0 <= key;
end
expand_key_type_D_192 a0 (k0, 8'h1, k1, k0b);
expand_key_type_B_192 a1 (k1, k2, k1b);
expand_key_type_A_192 a2 (k2, 8'h2, k3, k2b);
expand_key_type_C_192 a3 (k3, 8'h4, k4, k3b);
expand_key_type_B_192 a4 (k4, k5, k4b);
expand_key_type_A_192 a5 (k5, 8'h8, k6, k5b);
expand_key_type_C_192 a6 (k6, 8'h10, k7, k6b);
expand_key_type_B_192 a7 (k7, k8, k7b);
expand_key_type_A_192 a8 (k8, 8'h20, k9, k8b);
expand_key_type_C_192 a9 (k9, 8'h40, k10, k9b);
expand_key_type_B_192 a10 (clk,k10, k11, k10b);
expand_key_type_A_192 a11 (clk,k11, 8'h80, , k11b);
one_round
r1 (s0, k0b, s1),
r2 (s1, k1b, s2),
r3 (s2, k2b, s3),
r4 (s3, k3b, s4),
r5 (s4, k4b, s5),
r6 (s5, k5b, s6),
r7 (s6, k6b, s7),
r8 (s7, k7b, s8),
r9 (s8, k8b, s9),
r10 (s9, k9b, s10),
r11 (s10, k10b, s11);
final_round
rf (s11, k11b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_192 (in, rcon, out_1, out_2);
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
S4
S4_0 ({k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign k2b = k2a ^ k6a;
assign k3b = k3a ^ k6a;
assign {k4b, k5b} = {k4a, k5a};
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
/* expand k2,k3,k4,k5 for every two clock cycles */
module expand_key_type_B_192 (in, out_1, out_2);
input [191:0] in;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v2 = k1 ^ k2;
assign v3 = v2 ^ k3;
assign v4 = v3 ^ k4;
assign v5 = v4 ^ k5;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
always @ (*)
out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
assign out_2 = {k2a, k3a, k4a, k5a};
endmodule
/* expand k0,k1,k4,k5 for every two clock cycles */
module expand_key_type_C_192 (in, rcon, out_1, out_2);
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v4 = k3 ^ k4;
assign v5 = v4 ^ k5;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
S4
S4_0 ({v5[23:0], v5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule
/* expand k0,k1 for every two clock cycles */
module expand_key_type_D_192 (in, rcon, out_1, out_2);
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5,
v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (*)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
S4
S4_0 ({k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (*)
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; int n, x, tot = 0, Ans = 0, prime[maxn]; bool isprime[maxn]; map<int, int> sg, st; void init() { memset(isprime, true, sizeof(isprime)); isprime[1] = false; for (int i = 2; i < maxn; i++) { if (isprime[i]) prime[++tot] = i; for (int j = 1; j <= tot && i * prime[j] < maxn; j++) { isprime[i * prime[j]] = false; if (i % prime[j] == 0) break; } } } void gao(int x) { for (int i = 1; prime[i] * prime[i] <= x; i++) { int t = 0; while (x % prime[i] == 0) { x /= prime[i]; t++; } if (t) st[prime[i]] |= 1 << (t - 1); } if (x != 1) st[x] |= 1; } int getsg(int x) { if (x == 0) return 0; if (sg.count(x)) return sg[x]; map<int, int> vis; int p = x, t = 0; while (p) p >>= 1, t++; for (int i = 1; i <= t; i++) { vis[getsg((x >> i) | (x & ((1 << i - 1) - 1)))] = 1; } for (int i = 0;; i++) if (!vis[i]) return sg[x] = i; } int main() { init(); scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &x), gao(x); for (map<int, int>::iterator it = st.begin(); it != st.end(); it++) Ans ^= getsg(it->second); if (Ans) puts( Mojtaba ); else puts( Arpa ); return 0; }
|
module iir (clk, reset, start, din, params, dout, ready,iir_start,iir_done);
input clk, reset, start;
input [7:0] din;
input [15:0] params;
output [7:0] dout;
reg [7:0] dout;
output ready;
reg ready;
reg temp_ready;
reg [6:0] finite_counter;
wire count0;
input iir_start;
output iir_done;
wire iir_done;
reg del_count0;
reg [15:0] a1, a2, b0, b1, b2, yk1, yk2;
reg [7:0] uk, uk1, uk2 ;
reg [28:0] ysum ;
reg [26:0] yk ;
reg [22:0] utmp;
reg [3:0] wait_counter ;
// temporary variable
wire [31:0] yo1, yo2;
//wire [23:0] b0t, b1t, b2t;
wire [22:0] b0t, b1t, b2t;
wire [22:0] b0tpaj, b1tpaj, b2tpaj;
reg [3:0] obf_state, obf_next_state ;
reg [7:0] temp_uk, temp_uk1, temp_uk2 ;
reg [15:0] temp_a1, temp_a2, temp_b0, temp_b1, temp_b2, temp_yk1, temp_yk2;
reg [28:0] temp_ysum ;
reg [26:0] temp_yk ;
reg [22:0] temp_utmp;
reg [7:0] temp_dout;
reg [3:0] temp_wait_counter ;
parameter
idle = 4'b0001 ,
load_a2 = 4'b0010 ,
load_b0 = 4'b0011 ,
load_b1 = 4'b0100 ,
load_b2 = 4'b0101 ,
wait4_start = 4'b0110 ,
latch_din = 4'b0111 ,
compute_a = 4'b1000 ,
compute_b = 4'b1001 ,
compute_yk = 4'b1010 ,
wait4_count = 4'b1011 ,
latch_dout = 4'b1100 ;
always @(posedge clk)
begin
case (obf_state )
idle :
begin
if (iir_start)
obf_next_state <= load_a2 ;
else
obf_next_state <= idle;
temp_a1 <= params ;
end
load_a2 :
begin
obf_next_state <= load_b0 ;
temp_a2 <= params ;
end
load_b0 :
begin
obf_next_state <= load_b1 ;
temp_b0 <= params ;
end
load_b1 :
begin
obf_next_state <= load_b2 ;
temp_b1 <= params ;
end
load_b2 :
begin
obf_next_state <= wait4_start ;
temp_b2 <= params ;
end
wait4_start :
begin
if (start)
begin
obf_next_state <= latch_din ;
temp_uk <= din ;
end
else
begin
obf_next_state <= wait4_start ;
temp_uk <= uk;
end
temp_ready <= wait4_start;
end
latch_din :
begin
obf_next_state <= compute_a ;
end
compute_a :
begin
obf_next_state <= compute_b ;
temp_ysum <= yo1[31:3] + yo2[31:3];
end
compute_b :
begin
obf_next_state <= compute_yk ;
// temp_utmp <= b0t[23:0] + b1t[23:0] + b2t[23:0];
temp_utmp <= b0t + b1t + b2t;
end
compute_yk :
begin
obf_next_state <= wait4_count ;
temp_uk1 <= uk ;
temp_uk2 <= uk1 ;
temp_yk <= ysum[26:0] + {utmp[22], utmp[22], utmp[22], utmp[22], utmp};
temp_wait_counter <= 4 ;
end
wait4_count :
begin
if (wait_counter==0 )
begin
obf_next_state <= latch_dout ;
temp_dout <= yk[26:19];
temp_yk1 <= yk[26:11] ;
temp_yk2 <= yk1 ;
end
else
begin
obf_next_state <= wait4_count ;
temp_dout <= dout;
temp_yk1 <= yk1;
//temp_yk2 <= yk2;
end
temp_wait_counter <= wait_counter - 1;
end
latch_dout :
if (count0)
obf_next_state <= idle;
else
obf_next_state <= wait4_start ;
endcase
end
//assign yo1 = mul_tc_16_16(yk1, a1, clk);
assign yo1 = yk1 * a1;
//assign yo2 = mul_tc_16_16(yk2, a2, clk);
assign yo2 = yk2*a2;
//assign b0t = mul_tc_8_16(uk, b0, clk);
//assign b1t = mul_tc_8_16(uk1, b1, clk);
//assign b2t = mul_tc_8_16(uk2, b2, clk);
assign b0t = uk*b0;
assign b1t = uk1*b1;
assign b2t = uk2*b2;
// paj added to solve unused high order bit
assign b0tpaj = b0t;
assign b1tpaj = b1t;
assign b2tpaj = b2t;
// A COEFFICENTS
always @(posedge clk or posedge reset) begin
if (reset ) begin
uk <= 0 ;
uk1 <= 0 ;
uk2 <= 0 ;
yk1 <= 0 ;
yk2 <= 0 ;
yk <= 0 ;
ysum <= 0 ;
utmp <= 0 ;
a1 <= 0 ;
a2 <= 0 ;
b0 <= 0 ;
b1 <= 0 ;
b2 <= 0 ;
dout <= 0 ;
obf_state <= idle ;
ready <= 0;
end
else begin
obf_state <= obf_next_state ;
uk1 <= temp_uk1;
uk2 <= temp_uk2;
yk <= temp_yk;
uk <= temp_uk ;
a1 <= temp_a1 ;
a2 <= temp_a2 ;
b0 <= temp_b0 ;
b1 <= temp_b1 ;
b2 <= temp_b2 ;
ysum <= temp_ysum;
utmp <= temp_utmp;
dout <= temp_dout;
yk1 <= temp_yk1;
yk2 <= temp_yk2;
ready <= temp_ready;
end
end
// wait counter, count 4 clock after sum is calculated, to
// time outputs are ready, and filter is ready to accept next
// input
always @(posedge clk or posedge reset ) begin
if (reset )
wait_counter <= 0 ;
else begin
wait_counter <= temp_wait_counter ;
end
end
always @(posedge clk) begin
if (reset)
finite_counter<=100;
else
if (iir_start)
finite_counter<=finite_counter -1;
else
finite_counter<=finite_counter;
end
assign count0=finite_counter==7'b0;
always @(posedge clk) begin
del_count0 <= count0;
end
assign iir_done = (count0 && ~del_count0);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : Top.vf
// /___/ /\ Timestamp : 12/01/2014 17:59:05
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family spartan3e -verilog C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.vf -w C:/Users/samue_000/Documents/FPGA/Projects/Stopwatch/sevensegdecoder/Top.sch
//Design Name: Top
//Device: spartan3e
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module DigitToSeg(in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
mclk,
an,
dp,
seg);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
input [3:0] in4;
input [3:0] in5;
input [3:0] in6;
input [3:0] in7;
input [3:0] in8;
input mclk;
output [7:0] an;
output [6:0] seg;
output dp;
//wire swt7;
wire XLXN_94;
wire [3:0] XLXN_102;
wire [2:0] XLXN_109;
sevensegdecoder XLXI_6 (.nIn(XLXN_102[3:0]),
.ssOut(seg[6:0]));
mux4_4bus XLXI_45 (.I0(in1[3:0]),
.I1(in2[3:0]),
.I2(in3[3:0]),
.I3(in4[3:0]),
.I4(in5[3:0]),
.I5(in6[3:0]),
.I6(in7[3:0]),
.I7(in8[3:0]),
.Sel(XLXN_109[2:0]),
.Y(XLXN_102[3:0]));
segClkDevider XLXI_47 (.clk(mclk),
.rst(),
.clk_div(XLXN_94));
//GND XLXI_48 (.G(swt7));
counter3bit XLXI_49 (.clk(XLXN_94),
.rst(),
.Q(XLXN_109[2:0]));
decoder_3_8 XLXI_50 (.I(XLXN_109[2:0]),
.dp(dp),
.an(an[7:0]));
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// $Id$
//
// Module: vlan_remover.v
// Project: NF2.1 OpenFlow Switch
// Author: Jad Naous <>
// Description: removes the VLAN info if existing and puts it in a module header.
///////////////////////////////////////////////////////////////////////////////
module vlan_remover
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Interface to the next stage
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
// --- Misc
input reset,
input clk
);
`CEILDIV_FUNC
//------------------ Internal Parameters --------------------------
localparam SKIP_HDRS = 0,
CHECK_VLAN = 1,
GET_VLAN_TAG = 2,
WAIT_EOP = 3;
localparam NUM_STATES = 7;
localparam WAIT_PREPROCESS = 0,
ADD_MODULE_HEADER = 1,
WRITE_MODULE_HEADERS = 2,
REMOVE_VLAN = 3,
WRITE_MODIFIED_PKT = 4,
WRITE_LAST_WORD = 5,
SEND_UNMODIFIED_PKT = 6;
//---------------------- Wires/Regs -------------------------------
wire [DATA_WIDTH-1:0] fifo_data_out;
wire [CTRL_WIDTH-1:0] fifo_ctrl_out;
reg [3:0] preprocess_state;
reg [15:0] vlan_tag;
reg tag_vld, tag_found;
reg [NUM_STATES-1:0] process_state_nxt, process_state;
reg fifo_rd_en;
reg out_wr_nxt;
reg [DATA_WIDTH-1:0] out_data_nxt;
reg [CTRL_WIDTH-1:0] out_ctrl_nxt;
reg [DATA_WIDTH-1:0] fifo_data_out_d1;
reg [CTRL_WIDTH-1:0] fifo_ctrl_out_d1;
//----------------------- Modules ---------------------------------
fallthrough_small_fifo
#(.WIDTH(CTRL_WIDTH+DATA_WIDTH), .MAX_DEPTH_BITS(3))
input_fifo
(.din ({in_ctrl, in_data}), // Data in
.wr_en (in_wr), // Write enable
.rd_en (fifo_rd_en), // Read the next word
.dout ({fifo_ctrl_out, fifo_data_out}),
.full (),
.prog_full (),
.nearly_full (fifo_nearly_full),
.empty (fifo_empty),
.reset (reset),
.clk (clk)
);
//------------------------ Logic ----------------------------------
assign in_rdy = !fifo_nearly_full;
/* This state machine checks if there is a VLAN id and gets it */
always @(posedge clk) begin
if(reset) begin
preprocess_state <= SKIP_HDRS;
vlan_tag <= 0;
tag_vld <= 0;
tag_found <= 0;
end
else begin
case (preprocess_state)
SKIP_HDRS: begin
if (in_wr && in_ctrl==0) begin
preprocess_state <= CHECK_VLAN;
end
end
CHECK_VLAN: begin
if(in_wr) begin
if(in_data[31:16] == `VLAN_ETHERTYPE) begin
vlan_tag <= in_data[15:0];
preprocess_state <= GET_VLAN_TAG;
end
else begin
preprocess_state <= WAIT_EOP;
tag_vld <= 1'b1;
tag_found <= 1'b0;
end
end
end
GET_VLAN_TAG: begin
if(in_wr) begin
tag_vld <= 1'b1;
tag_found <= 1'b1;
preprocess_state <= WAIT_EOP;
end
end
WAIT_EOP: begin
if(in_wr && in_ctrl != 0) begin
tag_vld <= 0;
preprocess_state <= SKIP_HDRS;
end
end
default:preprocess_state <=SKIP_HDRS;
endcase // case(preprocess_state)
end // else: !if(reset)
end // always @ (posedge clk)
/* This state machine will remove the VLAN info from the pkt */
always @(*) begin
process_state_nxt = process_state;
fifo_rd_en = 0;
out_wr_nxt = 0;
out_data_nxt = fifo_data_out;
out_ctrl_nxt = fifo_ctrl_out;
case (process_state)
WAIT_PREPROCESS: begin
if(tag_vld) begin
if(tag_found) begin
process_state_nxt = ADD_MODULE_HEADER;
end
else begin
process_state_nxt = SEND_UNMODIFIED_PKT;
end
end // if (tag_vld)
end // case: WAIT_PREPROCESS
ADD_MODULE_HEADER: begin
if(out_rdy) begin
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = {{(DATA_WIDTH-16){1'b0}}, vlan_tag};
out_ctrl_nxt = `VLAN_CTRL_WORD;
process_state_nxt = WRITE_MODULE_HEADERS;
end
end
WRITE_MODULE_HEADERS: begin
if(out_rdy) begin
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = fifo_data_out_d1;
out_ctrl_nxt = fifo_ctrl_out_d1;
if(fifo_ctrl_out_d1 == `IO_QUEUE_STAGE_NUM) begin
// Decrement byte-count and word-count in IOQ since we will remove vlan tags
out_data_nxt[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS]
= fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4;
out_data_nxt[`IOQ_WORD_LEN_POS+15:`IOQ_WORD_LEN_POS]
= ceildiv((fifo_data_out_d1[`IOQ_BYTE_LEN_POS+15:`IOQ_BYTE_LEN_POS] - 4), 8);
end
if(fifo_ctrl_out_d1 == 0) begin
process_state_nxt = REMOVE_VLAN;
end
end
end // case: WRITE_MODULE_HEADERS
REMOVE_VLAN: begin
if(out_rdy) begin
process_state_nxt = WRITE_MODIFIED_PKT;
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = {fifo_data_out_d1[63:32], fifo_data_out[63:32]};
out_ctrl_nxt = fifo_ctrl_out_d1;
end
end // case: REMOVE_VLAN
WRITE_MODIFIED_PKT: begin
if(out_rdy && !fifo_empty) begin
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = {fifo_data_out_d1[31:0], fifo_data_out[63:32]};
out_ctrl_nxt = fifo_ctrl_out_d1;
if(fifo_ctrl_out != 0) begin
if(fifo_ctrl_out[7:4] != 0) begin
out_ctrl_nxt = (fifo_ctrl_out >> 4);
end
// We will write one more word in any case
process_state_nxt = WRITE_LAST_WORD;
end
end
end // case: WRITE_MODIFIED_PKT
WRITE_LAST_WORD: begin
if(out_rdy) begin
if(fifo_ctrl_out_d1[3:0] != 0) begin
out_ctrl_nxt = (fifo_ctrl_out_d1 << 4);
out_wr_nxt = 1;
out_data_nxt = {fifo_data_out_d1[31:0], 32'h600d_f00d};
end
else begin
// The data on this stage doesn't have meaningful contents.
// Put no-meaning value here.
out_ctrl_nxt = 0;
out_wr_nxt=0;
out_data_nxt=0;
end
if(tag_vld && tag_found) begin
process_state_nxt = ADD_MODULE_HEADER;
end
else if(tag_vld && !tag_found) begin
process_state_nxt = SEND_UNMODIFIED_PKT;
end
else begin
process_state_nxt = WAIT_PREPROCESS;
end
end // if (out_rdy)
end // case: WRITE_LAST_WORD
SEND_UNMODIFIED_PKT: begin
if(out_rdy && !fifo_empty) begin
if(fifo_ctrl_out_d1 == 0 && fifo_ctrl_out != 0) begin
if(tag_vld && tag_found) begin
process_state_nxt = ADD_MODULE_HEADER;
end
else if(tag_vld && !tag_found) begin
process_state_nxt = SEND_UNMODIFIED_PKT;
end
else begin
process_state_nxt = WAIT_PREPROCESS;
end
end
fifo_rd_en = 1;
out_wr_nxt = 1;
out_data_nxt = fifo_data_out;
out_ctrl_nxt = fifo_ctrl_out;
end
end // case: SEND_UNMODIFIED_PKT
default:process_state_nxt=WAIT_PREPROCESS;
endcase // case(process_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
process_state <= WAIT_PREPROCESS;
out_wr <= 0;
out_data <= 0;
out_ctrl <= 1;
fifo_data_out_d1 <= 0;
fifo_ctrl_out_d1 <= 1;
end
else begin
process_state <= process_state_nxt;
out_wr <= out_wr_nxt;
out_data <= out_data_nxt;
out_ctrl <= out_ctrl_nxt;
if(fifo_rd_en) begin
fifo_data_out_d1 <= fifo_data_out;
fifo_ctrl_out_d1 <= fifo_ctrl_out;
end
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // vlan_remover
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_MS__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ms__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_PWRGOOD_PP_P_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class t> t mag(t a) { return a > 0 ? a : -a; } template <class T> T cdiv(T num, T den) { return (num / den) + (num % den > 0); } std::ifstream term( /dev/tty ); std::string tempstring; using ll = int_fast64_t; using ii = pair<ll, ll>; using vi = vector<int>; using vl = vector<ll>; using vii = vector<ii>; int tc = 1; const ll sij = 40001000; const ll mod = 1000000007ll; ll n, m; bool vis[1510][1510]; string vec[1510]; int mx[] = {0, 0, -1, 1}, my[] = {-1, 1, 0, 0}; ii st; ll msk[1510][1510], msy[1510][1510]; int esc(int tcase) { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> vec[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (vec[i][j] == S ) { st = {i, j}; } } } st.first = st.first + n * mod; st.second = st.second + m * mod; msk[st.first % n][st.second % m] = st.first; msy[st.first % n][st.second % m] = st.second; queue<ii> q; q.push(st); while (!q.empty()) { ii cr = q.front(); q.pop(); for (int i = 0; i < 4; i++) { ll gx = cr.first + mx[i], gy = cr.second + my[i]; if (vec[gx % n][gy % m] == # ) continue; if (msk[gx % n][gy % m] == 0) { q.push({gx, gy}); msk[gx % n][gy % m] = gx; msy[gx % n][gy % m] = gy; continue; } if (msk[gx % n][gy % m] != gx or msy[gx % n][gy % m] != gy) { cout << Yes ; return 0; } } } cout << No ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (int i = 1; i <= tc; i++) esc(i); }
|
#include <bits/stdc++.h> using namespace std; vector<long long> a; int main() { long long t; cin >> t; for (long long ind = 0; ind < t; ++ind) { long long n, k; cin >> n >> k; string s; cin >> s; a.clear(); a.resize(26, 0); long long num = n / k, ans = 0; for (long long i = 0; i < k; ++i) { if (i > k - i - 1) break; for (long long j = i; j < n; j += k) { a[s[j] - a ]++; } bool p = false; if (i != k - i - 1) { p = true; for (long long j = k - i - 1; j < n; j += k) { a[s[j] - a ]++; } } long long m = a[0]; for (long long j = 1; j < 26; ++j) { if (a[j] > m) m = a[j]; } if (p) ans += 2 * num - m; else ans += num - m; a.clear(); a.resize(26, 0); } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; int a[110][110]; int main() { int n, m, i, j; while (~scanf( %d %d , &n, &m)) { for (i = 0; i < n; i++) for (j = 0; j < m; j++) scanf( %d , &a[i]); if (n & 1) { cout << n << endl; continue; } int vis; for (i = 0; i < m; i++) { for (j = 0, vis = 0; j < n; j++) { if (a[j][i] != a[n - j - 1][i]) { vis = 1; break; } } if (vis) break; } if (vis) cout << n << endl; else { while (1) { n /= 2; if (n == 1 || (n & 1)) { cout << n << endl; break; } for (i = 0; i < m; i++) { for (j = 0, vis = 0; j < n; j++) { if (a[j][i] != a[n - j - 1][i]) { vis = 1; break; } } if (vis) break; } if (vis) { cout << n << endl; break; } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, b; cin >> n >> b; long long a[n + 1]; for (int i = 0; i < n; ++i) { cin >> a[i]; } a[n] = b; sort(a, a + n + 1); if (a[0] == b) { cout << a[n - 1] - a[0]; } else { if (a[n] == b) { cout << a[n] - a[1]; } else { long long s1, s2, s3, s4, ans; s1 = (b - a[0]) + (a[n - 1] - a[0]); ans = s1; s2 = (a[n] - b) + (a[n] - a[1]); ans = min(ans, s2); s3 = (b - a[1]) + (a[n] - a[1]); ans = min(ans, s3); s4 = (a[n - 1] - b) + (a[n - 1] - a[0]); ans = min(ans, s4); cout << ans; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; #define rep(i, a, b) for(int i=a; i<=b; i++) #define repd(i, a, b) for(int i=a; i>=b; i--) #define vi vector<int> #define vll vector<long long> #define pii pair<int,int> #define pll pair<long long,long long> #define pb push_back #define fr first #define sc second #define vb vector<bool> typedef long long ll; typedef unsigned long long ull; /*struct cmp { bool operator()(const pair<int, pii> &p1, const pair<int, pii> &p2) { return p1.fr > p2.fr; } };*/ void google(){ static int tc=1; cout<< Case # <<tc<< : ; tc++; } int n; void solve(int tc = 1) { vi v(n); for(int i=0;i<n;i++) cin>>v[i]; int cnt=0; ll h=0; priority_queue<ll> q; for(int i=0;i<n;i++){ h+=v[i]; if(v[i]<0){ q.push(-v[i]); } cnt++; if(h<0){ int val=q.top(); q.pop(); cnt--; h+=val; } // cout<<cnt<< <<h<<endl; } cout<<cnt<<endl; } int main() { /*#ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif*/ ios::sync_with_stdio(false); cin.tie(0); //cout << setprecision(16) << fixed; int t = 1; // cin >> t; int tc=0; while (t--) { cin>>n; tc++; solve(tc); } }
|
#include <bits/stdc++.h> using namespace std; int tipo[100000 + 5]; int main() { int n, x, y, z, m; cin >> n >> m; memset(tipo, -1, sizeof(tipo)); for (int i = 0; i < m; ++i) { cin >> x >> y >> z; x--, y--, z--; bool enc = 0; if (tipo[x] != -1) { enc = 1; tipo[y] = (tipo[x] + 1) % 3; tipo[z] = (tipo[x] + 2) % 3; } else if (tipo[y] != -1) { enc = 1; tipo[x] = (tipo[y] + 1) % 3; tipo[z] = (tipo[y] + 2) % 3; } else if (tipo[z] != -1) { enc = 1; tipo[x] = (tipo[z] + 1) % 3; tipo[y] = (tipo[z] + 2) % 3; } if (enc == 0) { tipo[x] = 0, tipo[y] = 1, tipo[z] = 2; } } for (int i = 0; i < n; ++i) { if (i == 0) cout << tipo[i] + 1; else cout << << tipo[i] + 1; } puts( ); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_0_V
`define SKY130_FD_SC_LP__A41OI_0_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_0 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a41oi_0 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_0_V
|
#include <bits/stdc++.h> using namespace std; bool pd[5005][5005]; char str[5005]; int n; bool vis[5050]; bool dfs(int u, int lst) { vis[u] = 1; for (int i = 1; i <= n; ++i) { if (!pd[u][i]) continue; if (lst != -1 && pd[i][lst]) { printf( %d %d %d n , lst, u, i); return 1; } if (!vis[i] && dfs(i, u)) return 1; } return 0; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %s , str + 1); for (int j = 1; j <= n; ++j) if (str[j] == 1 ) pd[i][j] = 1; } for (int i = 1; i <= n; ++i) if (!vis[i] && dfs(i, -1)) { return 0; } printf( -1 n ); return 0; }
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream multiplexer
*/
module axis_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_axis_tready_reg = 0, s_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_axis_tvalid[select_reg];
wire current_s_tready = s_axis_tready[select_reg];
wire current_s_tlast = s_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_axis_tready_next = 0;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && (s_axis_tvalid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
end
// generate ready signal on selected port
s_axis_tready_next = (m_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = current_s_tid;
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_axis_tready_reg <= s_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; char A[5] = { a , e , i , o , u }; int main() { int k; cin >> k; int rol = 0, col = 0; for (int i = 5; i <= sqrt(k); ++i) { if ((k % i == 0) && (k / i >= 5)) { rol = i; col = k / i; break; } } if (rol == 0) { cout << -1; } else { for (int i = 1; i <= rol; ++i) { for (int j = 0; j < col; ++j) { cout << A[(i + j) % 5]; } } } }
|
#include <bits/stdc++.h> using namespace std; bool check(char s) { if (s == A || s == H || s == I || s == M || s == O || s == T || s == U || s == V || s == W || s == X || s == Y ) return true; else return false; } int main() { int n, i, x, p; bool ans = true; string st; cin >> st; n = st.size(); if (n == 1 && check(st[0]) == true) { cout << YES n ; ; } else if (n == 2 && st[0] == st[1] && check(st[0]) == true) { cout << YES n ; ; } else if (n >= 3) { ans = true; x = 0, p = n - 1; while (x <= p) { if (st[x] == st[p] && check(st[x]) == true) { x += 1, p -= 1; } else { ans = false; break; } } if (ans == false) { cout << NO n ; ; } else { cout << YES n ; ; } } else { cout << NO n ; ; } }
|
`include "Global_Macros.v"
module Write_Back(
clk_i,
rst_i,
gbl_stl_i,
wait_to_fill_pipe_i,
control_signal_i,
p_i,
dat_i,
eff_adr_i,
mem_stl_i,
a_o,
x_o,
y_o,
mem_w_enb_o,
mem_w_cnt_o,
mem_w_adr_o,
mem_w_dat_o
`ifdef DEBUG
,debug_o
`endif
);
//Input signals :
input wire clk_i;
input wire rst_i;
input wire gbl_stl_i;
input wire wait_to_fill_pipe_i;
input wire [`execut_cntrl_o_width - 1:0] control_signal_i;
input wire [7:0] p_i;
input wire [15:0] dat_i;
input wire [15:0] eff_adr_i;
input wire mem_stl_i;
//Output signals :
output wire [7:0] a_o;
output wire [7:0] x_o;
output wire [7:0] y_o;
output reg mem_w_enb_o;
output reg [1:0] mem_w_cnt_o;
output reg [15:0] mem_w_adr_o;
output reg [23:0] mem_w_dat_o;
`ifdef DEBUG
output wire [`WRB_DBG_WIDTH - 1:0] debug_o;
`endif
//Internal registers :
reg [7:0] a_reg;
reg [7:0] x_reg;
reg [7:0] y_reg;
//Assignments :
assign a_o = a_reg;
assign x_o = x_reg;
assign y_o = y_reg;
`ifdef DEBUG
assign debug_o = mem_w_adr_o;
`endif
//Blocks :
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
mem_w_cnt_o <= `ONE;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
mem_w_enb_o <= 1'h0;
end
else
begin
mem_w_enb_o <= `cntrl_wb_mem_wr;
mem_w_cnt_o <= ( `cntrl_wb_mem_wr_cnt == `ONE ) ? 2'h0 :
( `cntrl_wb_mem_wr_cnt == `TWO ) ? 2'h1 : 2'h2;
mem_w_dat_o <= {p_i, dat_i};
mem_w_adr_o <= eff_adr_i;
end
end
always @(posedge clk_i)
begin
if(rst_i == 1'h1)
begin
a_reg <= 8'h0;
x_reg <= 8'h0;
y_reg <= 8'h0;
end
else if(gbl_stl_i == 1'h1 || mem_stl_i == 1'h1)
begin
end
else if(wait_to_fill_pipe_i == 1'h1)
begin
end
else
begin
a_reg <= (`cntrl_wb_ra_ld == 1'h1) ? dat_i[7:0] : a_reg;
x_reg <= (`cntrl_wb_rx_ld == 1'h1) ? dat_i[7:0] : x_reg;
y_reg <= (`cntrl_wb_ry_ld == 1'h1) ? dat_i[7:0] : y_reg;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; const long long maxF = (long long)1e9 * 1e9; const int maxn = 100, maxm = 100, maxlen = maxn + maxm + 1; int n, m, len, map[maxn + 5][maxm + 5], pri[maxlen], cir[maxlen]; long long dp[maxlen][(maxlen >> 1) + 1], k; long long cal() { memset(dp, 0, sizeof(dp)); dp[0][1] = 1; int up = len >> 1; for (int p = 1; p < len; p++) for (int d = 0; d <= up; d++) { if (cir[p] != 1 && d < up) dp[p][d] += dp[p - 1][d + 1]; if (cir[p] != -1 && d > 0) dp[p][d] += dp[p - 1][d - 1]; if (dp[p][d] >= maxF) dp[p][d] = maxF; } return dp[len - 1][0]; } int main() { cin >> n >> m >> k; memset(pri, -1, sizeof(pri)); for (int i = 0, t; i < n; i++) for (int j = 0; j < m; j++) { cin >> t; pri[i + j] = pri[i + j] == -1 ? t : min(pri[i + j], t); } len = n + m - 1; memset(cir, 0, sizeof(cir)); cir[0] = 1; cir[len - 1] = -1; for (int t = 1; t < len - 1; t++) { int pos, minPri = 100000000; for (int p = 1; p < len - 1; p++) if (cir[p] == 0 && minPri > pri[p]) pos = p, minPri = pri[p]; cir[pos] = 1; long long s = cal(); if (k > s) k -= s, cir[pos] = -1; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << (cir[i + j] == 1 ? ( : ) ); cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; vector<int> edge[200010]; int dp[200010][2][2]; int leaf[200010]; void dfsLeaf(int u) { if (edge[u].size() == 0) { leaf[u] = 1; return; } for (int i = 0; i < edge[u].size(); ++i) { int v = edge[u][i]; dfsLeaf(v); leaf[u] += leaf[v]; } } void dfsDp(int u) { if (edge[u].size() == 0) { dp[u][0][1] = dp[u][1][0] = dp[u][0][0] = dp[u][1][1] = 1; return; } dp[u][0][0] = 0; dp[u][0][1] = 0; dp[u][1][0] = 1; dp[u][1][1] = 1000000000; for (int i = 0; i < edge[u].size(); ++i) { int v = edge[u][i]; dfsDp(v); dp[u][0][0] = max(dp[u][0][0], dp[v][1][0] + leaf[u] - leaf[v]); dp[u][0][1] += dp[v][1][1]; dp[u][1][0] += dp[v][0][0] - 1; dp[u][1][1] = min(dp[u][1][1], dp[v][0][1]); } } int main() { int u, v; while (cin >> n) { for (int i = 1; i < n; ++i) { cin >> u >> v; edge[u].push_back(v); } memset(leaf, 0, sizeof(leaf)); dfsLeaf(1); dfsDp(1); cout << dp[1][0][0] << << dp[1][0][1] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, m; cin >> n >> m; long long int arr[n]; vector<long long int> a, onsum, offsum; for (long long int i = 0; i < n; i++) { cin >> arr[i]; } a.push_back(arr[0]); for (long long int i = 1; i < n; i++) { a.push_back(arr[i] - arr[i - 1]); } a.push_back(m - arr[n - 1]); long long int sum1 = 0, sum2 = 0; for (long long int i = 0; i < a.size(); i++) { if (i % 2 == 0) { sum1 = sum1 + a[i]; offsum.push_back(sum1); } else { sum2 = sum2 + a[i]; onsum.push_back(sum2); } } long long int sum = 0; vector<long long int> z; for (long long int i = 0; i < onsum.size(); i++) { if (i == 0) sum = offsum[i] + onsum[onsum.size() - 1] - 1; else sum = offsum[i] + onsum[onsum.size() - 1] - onsum[i - 1] - 1; z.push_back(sum); } sum = 0; for (long long int i = 0; i < a.size(); i++) { if (i % 2 == 0) sum = sum + a[i]; } z.push_back(sum); sort(z.begin(), z.end()); cout << z[z.size() - 1]; return 0; }
|
#include<bits/stdc++.h> #define PI acos(-1.0) #define eps 1e-8 #define fi first #define se second #define m_p make_pair //#define int long long #define IOS ios::sync_with_stdio(false),cin.tie(0),cout.tie(0) using namespace std; typedef long long ll; typedef unsigned int uint; const double E_num = 0.57721566490153286060651209; const int maxn = 2e3 + 10; const int N = 5e5 + 10; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; int n,m,w; int mp[maxn][maxn]; ll dis1[maxn][maxn],dis2[maxn][maxn],ans1 = 1e18,ans2 = 1e18; queue<pair<int,int>> q; inline void bfs1(int x,int y) { #define dis dis1 memset(dis,INF,sizeof(dis)); q.push(m_p(x,y)); dis[x][y] = 0; while(!q.empty()) { x = q.front().fi,y = q.front().se; q.pop(); if(dis[x - 1][y] > dis[x][y] + w && mp[x - 1][y] >= 0) { q.push(m_p(x - 1,y)); dis[x - 1][y] = dis[x][y] + w; } if(dis[x + 1][y] > dis[x][y] + w && mp[x + 1][y] >= 0) { q.push(m_p(x + 1,y)); dis[x + 1][y] = dis[x][y] + w; } if(dis[x][y - 1] > dis[x][y] + w && mp[x][y - 1] >= 0) { q.push(m_p(x,y - 1)); dis[x][y - 1] = dis[x][y] + w; } if(dis[x][y + 1] > dis[x][y] + w && mp[x][y + 1] >= 0) { q.push(m_p(x,y + 1)); dis[x][y + 1] = dis[x][y] + w; } } #undef dis } inline void bfs2(int x,int y) { #define dis dis2 memset(dis,INF,sizeof(dis)); q.push(m_p(x,y)); dis[x][y] = 0; while(!q.empty()) { x = q.front().fi,y = q.front().se; q.pop(); if(dis[x - 1][y] > dis[x][y] + w && mp[x - 1][y] >= 0) { q.push(m_p(x - 1,y)); dis[x - 1][y] = dis[x][y] + w; } if(dis[x + 1][y] > dis[x][y] + w && mp[x + 1][y] >= 0) { q.push(m_p(x + 1,y)); dis[x + 1][y] = dis[x][y] + w; } if(dis[x][y - 1] > dis[x][y] + w && mp[x][y - 1] >= 0) { q.push(m_p(x,y - 1)); dis[x][y - 1] = dis[x][y] + w; } if(dis[x][y + 1] > dis[x][y] + w && mp[x][y + 1] >= 0) { q.push(m_p(x,y + 1)); dis[x][y + 1] = dis[x][y] + w; } } #undef dis } int main() { IOS; cin >> n >> m >> w; for(int i = 0;i <= m + 1; ++i) { mp[0][i] = mp[n + 1][i] = -1; } for(int i = 1;i <= n + 1; ++i) { mp[i][0] = mp[i][m + 1] = -1; } for(int i = 1;i <= n; ++i) { for(int j = 1;j <= m; ++j) { cin >> mp[i][j]; } } bfs1(1,1); bfs2(n,m); for(int i = 1;i <= n; ++i) { for(int j = 1;j <= m; ++j) { if(mp[i][j] > 0) ans1 = min(ans1,dis1[i][j] + mp[i][j]); } } for(int i = 1;i <= n; ++i) { for(int j = 1;j <= m; ++j) { if(mp[i][j] > 0) ans2 = min(ans2,dis2[i][j] + mp[i][j]); } } ans1 = min(dis1[n][m] ,ans1 + ans2); if(ans1 < 1e18) cout << ans1 << endl; else cout << -1 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; char v[2100][2100]; int n, m; int sumx[2100][2100]; int sumy[2100][2100]; long long ans1, ans2, ans3, cima, baixo; int main() { bool ok; scanf( %d %d , &n, &m); for (int i = 0; i < n; ++i) scanf( %s , v[i]); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (j > 0) sumx[i][j] = sumx[i][j - 1]; sumx[i][j] += (v[i][j] == . ); } } for (int j = 0; j < m; ++j) { for (int i = 0; i < n; ++i) { if (i > 0) sumy[i][j] = sumy[i - 1][j]; sumy[i][j] += (v[i][j] == . ); } } for (int i = 1; i < m - 1; ++i) if (sumy[n - 1][i] == n) ans1++; for (int i = 1; i < n - 1; ++i) if (sumx[i][m - 1] == m) ans1++; for (int i = 1; i < n - 1; ++i) { ok = true; if (v[i][0] == # ) ok = false; if (ok) for (int j = 1; j < m - 1; ++j) { if (v[i][j] != . ) { ok = false; break; } if (sumy[i - 1][j] == i) ans2++; if (sumy[n - 1][j] - sumy[i][j] == n - i - 1) ans2++; } if (v[i][m - 1] == # ) continue; for (int j = m - 2; j >= 1 && v[i][j] == . ; --j) { if (sumy[i - 1][j] == i) ans2++; if (sumy[n - 1][j] - sumy[i][j] == n - i - 1) ans2++; } } for (int i = 1; i < n - 1; ++i) { cima = baixo = 0; for (int j = 1; j < m - 1; ++j) { if (v[i][j] == # ) { cima = baixo = 0; continue; } if (sumy[i][j] == i + 1) { ans3 += baixo + cima; if (j > 1 && v[i][j - 1] == . && sumy[i][j - 1] == i + 1) ans3--; } if (sumy[n - 1][j] - sumy[i][j] == n - i - 1) { ans3 += baixo + cima; if (j > 1 && v[i][j - 1] == . && sumy[n - 1][j - 1] - sumy[i][j - 1] == n - i - 1) ans3--; } if (sumy[i][j] == i + 1) cima++; if (sumy[n - 1][j] - sumy[i][j] == n - i - 1) baixo++; } } for (int j = 1; j < m - 1; ++j) { cima = baixo = 0; for (int i = 1; i < n - 1; ++i) { if (v[i][j] == # ) { cima = baixo = 0; continue; } if (sumx[i][j] == j + 1) { ans3 += baixo + cima; if (i > 1 && v[i - 1][j] == . && sumx[i - 1][j] == j + 1) ans3--; } if (sumx[i][m - 1] - sumx[i][j] == m - j - 1) { ans3 += baixo + cima; if (i > 1 && v[i - 1][j] == . && sumx[i - 1][m - 1] - sumx[i - 1][j] == m - j - 1) ans3--; } if (sumx[i][j] == j + 1) cima++; if (sumx[i][m - 1] - sumx[i][j] == m - j - 1) baixo++; } } printf( %lld n , ans1 + ans2 + ans3); return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; template <typename T> inline void read(T &x) { char c; bool nega = 0; while ((!isdigit(c = getchar())) && (c != - )) ; if (c == - ) { nega = 1; c = getchar(); } x = c - 48; while (isdigit(c = getchar())) x = x * 10 + c - 48; if (nega) x = -x; } template <typename T> inline void writep(T x) { if (x > 9) writep(x / 10); putchar(x % 10 + 48); } template <typename T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } writep(x); } template <typename T> inline void writeln(T x) { write(x); putchar( n ); } int n, s; int a[2000]; deque<int> pos[2001]; map<int, int> m; int f[2001]; int trace[2001]; int g[2001]; int dist_inc(int u, int v) { if (v >= u) return v - u; return v + n - u; } int dist_dec(int u, int v) { if (v <= u) return u - v; return u + n - v; } int dist(int u, int v) { return min(abs(u - v), n - abs(u - v)); } void output(int x) { putchar( +- [x < 0]); writeln(abs(x)); } void rebuild(int u) { if (a[u] > 1) rebuild(trace[u]); if ((a[u] == 1) && (a[s] == 1)) { output(0); return; } int x = a[u]; int sz = pos[x].size(); int i = trace[u]; if (pos[x].size() == 1) { if (dist(i, u) == dist_inc(i, u)) { output(dist(i, u)); } else { output(-dist(trace[u], u)); } } else { while (dist_inc(pos[x].back(), i) + dist_inc(i, pos[x].front()) != dist_inc(pos[x].back(), pos[x].front())) { pos[x].push_back(pos[x].front()); pos[x].pop_front(); } if (i == s) { if (a[s] == 0) g[s] = 0; else g[s] = f[s]; } int maxs = dist_inc(i, pos[x].front()); int tmax = pos[x].front(); for (int j = (0); j < (sz); j++) { if (j) { if (maxs < dist_inc(pos[x][j - 1], pos[x][j])) { maxs = dist_inc(pos[x][j - 1], pos[x][j]); tmax = pos[x][j]; } } if (pos[x][j] == u) break; } if (f[u] == g[i] + n + dist_inc(i, u) - maxs * 2) { int last = i; for (int j = (0); j < (sz); j++) { if (pos[x][j] == tmax) break; last = pos[x][j]; output(dist_inc((j == 0) ? i : pos[x][j - 1], pos[x][j])); } for (int j = (sz - 1); j >= (0); j--) { output(-dist_dec((j == sz - 1) ? last : pos[x][j + 1], pos[x][j])); if (pos[x][j] == tmax) { if (tmax == u) break; output(dist_inc(tmax, u)); break; } } return; } maxs = dist_dec(i, pos[x].back()); tmax = pos[x].back(); for (int j = (sz - 1); j >= (0); j--) { if (j < sz - 1) { if (maxs < dist_dec(pos[x][j + 1], pos[x][j])) { maxs = dist_dec(pos[x][j + 1], pos[x][j]); tmax = pos[x][j]; } } if (pos[x][j] == u) break; } if (f[u] == g[i] + n + dist_dec(i, u) - maxs * 2) { int last = i; for (int j = (sz - 1); j >= (0); j--) { if (pos[x][j] == tmax) break; last = pos[x][j]; output(-dist_dec((j == sz - 1) ? i : pos[x][j + 1], pos[x][j])); } for (int j = (0); j < (sz); j++) { output(dist_inc((j == 0) ? last : pos[x][j - 1], pos[x][j])); if (pos[x][j] == tmax) { if (tmax == u) break; output(-dist_dec(tmax, u)); break; } } return; } } } int main() { read(n); read(s); s--; for (int i = (0); i < (n); i++) read(a[i]); if (a[s] == *min_element(a, a + n)) { a[s]--; } for (int i = (0); i < (n); i++) m[a[i]] = 0; { int cnt = 0; for (auto &t : m) t.second = ++cnt; } for (int i = (0); i < (n); i++) { a[i] = m[a[i]]; pos[a[i]].push_back(i); } if (a[s] != 1) pos[0].push_back(s); for (int x = (1 + (a[s] == 1)); x <= (m.size()); x++) { for (int i : pos[x - 1]) g[i] = f[i]; for (int i : pos[x]) f[i] = 1e9; int sz = pos[x].size(); for (int i : pos[x - 1]) { if (pos[x].size() == 1) { if (f[pos[x][0]] > g[i] + dist(i, pos[x][0])) { f[pos[x][0]] = g[i] + dist(i, pos[x][0]); trace[pos[x][0]] = i; } } else { while (dist_inc(pos[x].back(), i) + dist_inc(i, pos[x].front()) != dist_inc(pos[x].back(), pos[x].front())) { pos[x].push_back(pos[x].front()); pos[x].pop_front(); } int maxs = dist_inc(i, pos[x].front()); for (int j = (0); j < (sz); j++) { if (j) maxs = max(maxs, dist_inc(pos[x][j - 1], pos[x][j])); if (f[pos[x][j]] > g[i] + n + dist_inc(i, pos[x][j]) - maxs * 2) { f[pos[x][j]] = g[i] + n + dist_inc(i, pos[x][j]) - maxs * 2; trace[pos[x][j]] = i; } } maxs = dist_dec(i, pos[x].back()); for (int j = (sz - 1); j >= (0); j--) { if (j + 1 < sz) maxs = max(maxs, dist_dec(pos[x][j + 1], pos[x][j])); if (f[pos[x][j]] > g[i] + n + dist_dec(i, pos[x][j]) - maxs * 2) { f[pos[x][j]] = g[i] + n + dist_dec(i, pos[x][j]) - maxs * 2; trace[pos[x][j]] = i; } } } } } int best = pos[m.size()][0]; for (int i : pos[m.size()]) if (f[i] < f[best]) best = i; writeln(f[best]); rebuild(best); }
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///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
///////////////////////////////////////////////////////////////////////////////
// Title : Synchronous FIFO model
// File : sfifo.v
// Author : Frank Bruno
// Created : 14-May-2009
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module generates a Synchronous FIFO
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// The file below this point is mdifiable by the licensee:
`timescale 1ns / 10ps
module ssi_sfifo
#
(
parameter WIDTH = 32,
parameter DEPTH = 8,
parameter DLOG2 = 3,
parameter AFULL = 3
)
(
input [WIDTH-1:0] data,
input wrreq,
input rdreq,
input clock,
input aclr,
output reg [WIDTH-1:0] q,
output full,
output empty,
output reg [DLOG2-1:0] usedw,
output almost_full
);
reg [WIDTH-1:0] ram[DEPTH-1:0];
reg [DLOG2-1:0] wr_addr;
reg [DLOG2-1:0] rd_addr;
always @(posedge clock, posedge aclr)
if (aclr) begin
usedw <= 'b0;
wr_addr <= 'b0;
rd_addr <= 'b0;
q <= 'b0;
end else begin
case ({wrreq, rdreq})
2'b10: usedw <= usedw + 8'h1;
2'b01: usedw <= usedw - 8'h1;
endcase // case ({wrreq, rdreq})
if (wrreq) ram[wr_addr] <= data;
if (wrreq) wr_addr <= wr_addr + 8'h1;
if (rdreq) begin
rd_addr <= rd_addr + 8'h1;
q <= ram[rd_addr];
end
//q <= ram[rd_addr];
end // else: !if(aclr)
//assign q = ram[rd_addr];
assign full = &usedw;
assign empty = ~|usedw;
assign almost_full = usedw > AFULL;
endmodule // sfifo
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long n, k; cin >> n >> k; vector<vector<char>> board(n, vector<char>(n, . )); vector<vector<long long>> cnt(n, vector<long long>(n, 0)); for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { cin >> board[i][j]; } } for (long long i = 0; i < n; i++) { for (long long j = 0; j <= n - k; j++) { bool flag = true; for (long long x = j; x < j + k; x++) { if (board[i][x] != . ) { flag = false; break; } } if (!flag) continue; for (long long x = j; x < j + k; x++) { cnt[i][x]++; } } } for (long long i = 0; i <= n - k; i++) { for (long long j = 0; j < n; j++) { bool flag = true; for (long long x = i; x < i + k; x++) { if (board[x][j] != . ) { flag = false; break; } } if (!flag) continue; for (long long x = i; x < i + k; x++) { cnt[x][j]++; } } } long long mxX = 0, mxY = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (cnt[i][j] > cnt[mxX][mxY]) { mxX = i; mxY = j; } } } cout << mxX + 1 << << mxY + 1; return 0; }
|
//======================================================================
//
// tb_blake2.v
// -----------
// Testbench for the Blake2 top level wrapper.
//
//
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_blake2();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_write_read;
reg [7 : 0] tb_address;
reg [31 : 0] tb_data_in;
wire [31 : 0] tb_data_out;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg error_found;
reg [31 : 0] read_data;
reg [511 : 0] extracted_data;
reg display_cycle_ctr;
reg display_read_write;
//----------------------------------------------------------------
// Blake2 device under test.
//----------------------------------------------------------------
blake2 dut(
// Clock and reset.
.clk(tb_clk),
.reset_n(tb_reset_n),
// Control.
.cs(tb_cs),
.we(tb_write_read),
// Data ports.
.address(tb_address),
.write_data(tb_data_in),
.read_data(tb_data_out)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut;
begin
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
// Set clock, reset and DUT input signals to
// defined values at simulation start.
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h00;
tb_data_in = 32'h00000000;
end
endtask // init_dut
//----------------------------------------------------------------
// blake2_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : blake2_test
$display(" -- Testbench for blake2 started --");
init_dut();
reset_dut();
$display("State at init after reset:");
dump_dut_state();
display_test_result();
$display("*** blake2 simulation done.");
$finish;
end // blake2_test
endmodule // tb_blake2
//======================================================================
// EOF tb_blake2.v
//======================================================================
|
`timescale 1ns / 100ps
module sasc_brg(/*AUTOARG*/
// Outputs
sio_ce, sio_ce_x4,
// Inputs
clk, arst_n
);
output sio_ce; // baud rate
output sio_ce_x4; // baud rate x 4
input clk;
input arst_n;
reg sio_ce;
reg sio_ce_x4;
parameter br_38400_16MHz = 103; // 16e6 / (38400*4) = 104 = 103 + 1
`define BRX4pre &{brx4_cntr[6:5],brx4_cntr[2:0]}
reg [6:0] brx4_cntr;
reg [1:0] br_cntr;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
brx4_cntr <= 0;
else if (`BRX4pre)
brx4_cntr <= 0;
else
brx4_cntr <= brx4_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
br_cntr <= 0;
else if (`BRX4pre)
br_cntr <= br_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
begin
sio_ce_x4 <= 1'b0;
sio_ce <= 1'b0;
end
else
begin
sio_ce_x4 <= `BRX4pre;
sio_ce <= (&br_cntr) & (`BRX4pre);
end
endmodule // sasc_brg
|
Require Import Algebra OwnTacts Equal.
(* Natural numbers is is the simplest inductive type. *)
(* For a type to be natural numbers is has to have the following properties (The Peano Axioms) : *)
(* 1 : forall n in N, *)
(* There should exists a successor 'Succ' to n. (n + 1) *)
(* 2 : forall n, m in N, *)
(* If n and m is different, their successors should be different. *)
(* 3 : There should exist a element, which is not the successor of anything, denoted 'ZERO'. *)
(* 4 : For a property P, if 'P n' is true for 'ZERO' and for an element 'a' in N, then it implies that *)
(* that the successor of 'a' is also true, then 'P n' is true. Which is exactly the 'Induction principle'! *)
(* And actually what we are doing when we prove theorems about natural numbers, is to construct the *)
(* 'Induction Tree' for natural numbers: *)
(* P (ZERO) forall n in N, P (n) -> P (Succ n) *)
(* ============================================== *)
(* P n *)
(* So we have a very strong relation between Natural Numbers and Induction and Induction and Recursion *)
(* is intertwined, so inductive types are ideal for recursive functions. *)
Inductive Nat : Set :=
| ZERO : Nat (* Base case *)
| Succ : Nat -> Nat. (* Inductive case *)
(* As always, we need a way of telling if elements are equal. *)
(* This is our first recursive function, when working with recursive data structures in Coq *)
(* We use a fixpoint, which is able to call itself, compared to a definition which cannot. *)
Fixpoint eq_Nat (n m : Nat) : Prop :=
match n, m with
| ZERO , ZERO => True
| Succ n', ZERO => False
| ZERO , Succ m' => False
| Succ n', Succ m' => eq_Nat n' m'
end.
Notation "A =N= B" := (eq_Nat A B) (at level 70, no associativity).
Lemma eq_Nat_ZERO_ZERO :
ZERO =N= ZERO.
Proof.
unfold eq_Nat.
exact I.
Qed.
Lemma eq_Nat_Succ_ZERO :
forall n : Nat,
not (Succ n =N= ZERO).
Proof.
intro n.
unfold not.
intro H.
unfold eq_Nat in H.
contradiction H.
Qed.
Lemma eq_Nat_ZERO_Succ :
forall m : Nat,
not (ZERO =N= Succ m).
Proof.
intro n.
unfold not.
intro H.
unfold eq_Nat in H.
contradiction H.
Qed.
Lemma eq_Nat_Succ_Succ :
forall n m : Nat,
eq_Nat n m <-> eq_Nat (Succ n) (Succ m) .
Proof.
intros n m.
unfold eq_Nat.
fold eq_Nat.
split.
intro H.
exact H.
intro H.
exact H.
Qed.
Lemma eq_Nat_is_reflexive :
Reflexive Nat eq_Nat.
Proof.
unfold Reflexive.
intro n.
induction n as [ | n' IHn']. (* Whenever we have a inductive type, we use 'induction' to reason about *)
(* the base case and inductive case of the type, assuming P n. *)
(* Base case *)
exact eq_Nat_ZERO_ZERO.
apply <- eq_Nat_Succ_Succ.
exact IHn'.
Qed.
Lemma eq_Nat_is_symmetric :
Symmetric Nat eq_Nat.
Proof.
unfold Symmetric.
intros n. (* By waiting introducing all variables, we get a stronger induction hypothesis *)
induction n as [ | n' IHn']; intros [ | m']; intro H.
exact H.
apply eq_Nat_ZERO_Succ in H.
contradiction H.
apply eq_Nat_Succ_ZERO in H.
contradiction H.
apply -> eq_Nat_Succ_Succ.
apply (IHn' m').
apply <- eq_Nat_Succ_Succ in H.
exact H.
Qed.
Lemma eq_Nat_is_transitive :
Transitive Nat eq_Nat.
Proof.
unfold Transitive.
intros n.
induction n as [ | n' IHn']; intros [ | m'] l; intros H_1 H_2.
exact H_2.
case l as [ | l'].
exact eq_Nat_ZERO_ZERO.
apply eq_Nat_ZERO_Succ in H_1.
contradiction H_1.
apply eq_Nat_Succ_ZERO in H_1.
contradiction H_1.
case l as [ | l'].
contradiction (eq_Nat_Succ_ZERO m' H_2).
apply (IHn' m' l').
apply eq_Nat_Succ_Succ in H_1.
exact H_1.
apply eq_Nat_Succ_Succ in H_2.
exact H_2.
Qed.
Theorem eq_Nat_is_a_valid_equal :
Equal Nat eq_Nat.
Proof.
unfold Equal.
split.
exact eq_Nat_is_reflexive.
split.
exact eq_Nat_is_symmetric.
exact eq_Nat_is_transitive.
Qed.
(* The addition function for natural numbers *)
Definition unit_test_addtion (candidate : Nat -> Nat -> Nat) :=
(candidate ZERO ZERO =N= ZERO) /\
(candidate (Succ ZERO) ZERO =N= Succ ZERO) /\
(candidate (Succ ZERO) (Succ ZERO) =N= Succ (Succ ZERO)).
Definition specification_of_addition (add' : Nat -> Nat -> Nat) : Prop :=
(forall m : Nat,
add' ZERO m =N= m) /\
(forall n m,
add' (Succ n) m =N= Succ (add' n m)).
Theorem specification_of_addition_is_unique :
forall add add' : Nat -> Nat -> Nat,
specification_of_addition add ->
specification_of_addition add' ->
forall n m : Nat,
add n m =N= add' n m.
Proof.
intros add add'.
unfold specification_of_addition.
intros [H_add_ZERO H_add_Succ] [H_add'_ZERO H_add'_Succ].
intro n.
induction n as [ | n' IHn ]; intro m.
apply (eq_Nat_is_transitive (add ZERO m) m (add' ZERO m)).
assert (H_add_ZERO_m := H_add_ZERO m). (* We use 'assert' to make an assertion. This time we *)
(* instantiate H_add_ZERO with the variable m. *)
exact H_add_ZERO_m.
assert (H_add'_ZERO_m := H_add'_ZERO m).
apply eq_Nat_is_symmetric in H_add'_ZERO_m.
exact H_add'_ZERO_m.
assert (H_add_Succ_n'_m := H_add_Succ n' m).
assert (H_add'_Succ_n'_m := H_add'_Succ n' m).
apply (eq_Nat_is_transitive (add (Succ n') m) (Succ (add n' m)) (add' (Succ n') m)).
exact H_add_Succ_n'_m.
apply eq_Nat_is_symmetric.
apply (eq_Nat_is_transitive (add' (Succ n') m) (Succ (add' n' m)) (Succ (add n' m))).
exact H_add'_Succ_n'_m.
apply -> eq_Nat_Succ_Succ.
apply eq_Nat_is_symmetric.
exact (IHn m).
Qed.
(* If you did not prove Booleans with eq_bool', try taking a look at it now. *)
(* TODO: Define everything self. *)
Require Import Arith.
(* Proving with the built-in nat *)
Theorem Nat_and_addition_is_a_monoid :
Monoid nat plus eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists O.
intro n.
split.
exact (plus_0_r n).
exact (plus_0_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
unfold Associative.
exact plus_assoc.
Qed.
Theorem Nat_and_multiplication_is_a_monoid :
Monoid nat mult eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists 1.
intro n.
split.
exact (mult_1_r n).
exact (mult_1_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
unfold Associative.
exact mult_assoc.
Qed.
Theorem Nat_and_max_is_a_monoid :
Monoid nat max eq.
Proof.
unfold Monoid.
split.
unfold Neutral.
exists 0.
intro n.
split.
exact (Max.max_0_r n).
exact (Max.max_0_l n).
unfold Semi_Group.
split.
exact (eq_is_a_valid_Equal nat).
exact Max.max_assoc.
Qed.
Proposition Nat_and_min_is_NOT_a_monoid :
not (Monoid nat min eq).
Proof.
unfold Monoid.
unfold not.
intros [H_no_neutral_element _].
unfold Neutral in H_no_neutral_element.
destruct H_no_neutral_element as [not_O H_not_neutral].
destruct (H_not_neutral (S not_O)) as [H_absurd _].
rewrite -> Min.min_r in H_absurd.
apply n_Sn in H_absurd.
contradiction.
exact (le_n_Sn not_O).
Qed.
(* Please continue with Lists *)
|
#include <bits/stdc++.h> using namespace std; void fastio() { ios_base::sync_with_stdio(0); cin.tie(0); } int main() { fastio(); long long int n; cin >> n; long long int ans = 0; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (long long int i = 0; i < n; i += 2) { long long int sum = 0; for (long long int j = i + 1; j < n; j += 2) { long long int x = a[j] - sum; if (x < 0) { } else { ans += min(a[i], x); if (sum) ans++; } sum -= a[j]; if (sum < 0) { if (abs(sum) > a[i]) break; else { a[i] += sum; sum = 0; } } if (j + 1 < n) sum += a[j + 1]; } } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int t, n, m, x = 0, y = 0, flag = 0, cnt = 0, sum = 0, sum1 = 0, sum0 = 0, flag1 = 0; int a1, a2, a3, b1, b2, b3; vector<int> d; cin >> t; int a[t]; for (int i = 0; i < t; i++) { cin >> a[i]; } x = t - 1; while (x > 0 && a[x - 1] < a[x]) { x--; } cout << x << n ; return 0; }
|
/*
* Titor - Preshift - Prepares signals for input into the butterfly unit
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_PRESHIFT
`else
`define INC_PRESHIFT
`timescale 1 ns / 100 ps
// This module handles most of the messy junk that goes into the butterfly unit
// There are some nasty things still in it but the non-recyclables are here
module Preshift (
boperand,
bamount,
btype,
bopcode,
immediate,
reg1,
reg2,
reg3,
shift_I,
shift_IR,
shift_type,
swapshift,
amount,
enable
);
`include "definition/Definition.v"
output reg [WORD-1:0] boperand; // the argument to be shifted or swapped by the butterfly unit
output reg [WORD-1:0] bamount; // the amount or control bits by which to shift in the butterfly unit
output reg [WORD-1:0] btype; // whether to do a shift or swap type operation
output reg [WORD-1:0] bopcode; // what type of swap or shift operation
input [WORD-1:0] immediate; // the immedaite value in the instruction
input [WORD-1:0] reg1; // reg1
input [WORD-1:0] reg2; // reg2
input [WORD-1:0] reg3; // reg3
input [WORD-1:0] shift_I; // the instruction-immediate value
input [WIDTH_SHIFT_IR-1:0] shift_IR; // the instruction flag indicating if a shift is controlled by an imm or reg value
input [WIDTH_SHIFT_TYPE-1:0] shift_type; // the instruction code indicating the kind of shift/rotate
input swapshift; // choose between swap or shift operations
input [WORD-1:0] amount; // the control path value dictating a swap
input enable; // if false just pass reg2 through this and the butterfly unit unharmed
always @(*) begin
if(enable) begin
case(swapshift)
PS_SWAP: begin
boperand <= reg1 | immediate;
bamount <= amount;
btype <= PS_SWAP;
bopcode <= 0;
end
PS_SHIFT: begin
boperand <= reg2;
case(shift_IR)
IMM: bamount <= shift_I;
REG: bamount <= reg3;
default bamount <= 0;
endcase
btype <= PS_SHIFT;
bopcode <= shift_type;
end
default: begin
boperand <= 0;
bamount <= 0;
btype <= 0;
bopcode <= 0;
end
endcase
end
else begin
boperand <= reg2;
bamount <= 0;
btype <= PS_SWAP;
bopcode <= 0;
end
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int r, g, b; cin >> r >> g >> b; int a[3] = {r, g, b}; int i = 0; while (a[0] > 0 || a[1] > 0 || a[2] > 0) { if (a[i % 3] > 0) a[i % 3] -= 2; i++; } cout << 30 + i - 1; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_4_V
`define SKY130_FD_SC_HD__MUX2I_4_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_4_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gen_context_pkt
#(parameter PROT_ENG_FLAGS=1,
parameter DSP_NUMBER=0)
(input clk, input reset, input clear,
input trigger, output sent,
input [31:0] streamid,
input [63:0] vita_time,
input [31:0] message,
input [31:0] seqnum,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
localparam CTXT_IDLE = 0;
localparam CTXT_PROT_ENG = 1;
localparam CTXT_HEADER = 2;
localparam CTXT_STREAMID = 3;
localparam CTXT_TICS = 4;
localparam CTXT_TICS2 = 5;
localparam CTXT_MESSAGE = 6;
localparam CTXT_FLOWCTRL = 7;
localparam CTXT_DONE = 8;
reg [33:0] data_int;
wire src_rdy_int, dst_rdy_int;
reg [3:0] seqno;
reg [3:0] ctxt_state;
reg [63:0] err_time;
reg [31:0] stored_message;
always @(posedge clk)
if(reset | clear)
stored_message <= 0;
else
if(trigger)
stored_message <= message;
else if(ctxt_state == CTXT_DONE)
stored_message <= 0;
// Don't want to clear most of this to avoid getting stuck with a half packet in the pipe
always @(posedge clk)
if(reset)
begin
ctxt_state <= CTXT_IDLE;
seqno <= 0;
end
else
case(ctxt_state)
CTXT_IDLE :
if(trigger)
begin
err_time <= vita_time;
if(PROT_ENG_FLAGS)
ctxt_state <= CTXT_PROT_ENG;
else
ctxt_state <= CTXT_HEADER;
end
CTXT_DONE :
begin
ctxt_state <= CTXT_IDLE;
seqno <= seqno + 4'd1;
end
default :
if(dst_rdy_int)
ctxt_state <= ctxt_state + 1;
endcase // case (ctxt_state)
assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) );
always @*
case(ctxt_state)
CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd24 }; // UDP port 1 or 3
CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100000001, seqno, 16'd6 };
CTXT_STREAMID : data_int <= { 2'b00, streamid };
CTXT_TICS : data_int <= { 2'b00, err_time[63:32] };
CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
CTXT_MESSAGE : data_int <= { 2'b00, message };
CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum };
default : data_int <= {2'b00, 32'b00};
endcase // case (ctxt_state)
fifo_short #(.WIDTH(34)) ctxt_fifo
(.clk(clk), .reset(reset), .clear(0),
.datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
.dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
assign data_o[35:34] = 2'b00;
endmodule // gen_context_pkt
|
/*
* Zero delay memory module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module memory (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o
);
// Registers and nets
reg [15:0] ram[0:2**19-1];
wire we;
wire [7:0] bhw, blw;
// Assignments
assign wb_dat_o = ram[wb_adr_i];
assign wb_ack_o = wb_stb_i;
assign we = wb_we_i & wb_stb_i & wb_cyc_i;
assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
: ram[wb_adr_i][15:8];
assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
: ram[wb_adr_i][7:0];
// Behaviour
always @(posedge wb_clk_i)
if (we) ram[wb_adr_i] <= { bhw, blw };
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_57x64.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_57x64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input aclr;
input [56:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [56:0] q;
output rdempty;
output wrempty;
output wrfull;
output [5:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "57"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "57"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "57"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 57 0 INPUT NODEFVAL "data[56..0]"
// Retrieval info: USED_PORT: q 0 0 57 0 OUTPUT NODEFVAL "q[56..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 6 0 OUTPUT NODEFVAL "wrusedw[5..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 57 0 data 0 0 57 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 57 0 @q 0 0 57 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 6 0 @wrusedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long n, nn = 0, nm = 0, dr[5069], dh[10069], pd[5069], pr[5069], fq[10069], sbt[10069], sm = 0, z = 1e18; vector<pair<long long, long long>> fz[5069], al[10069]; pair<long long, long long> sk[5069]; vector<long long> pst[5069]; bitset<10069> vtd; void ae(long long x, long long y, long long w) { al[x].push_back({y, w}); al[y].push_back({x, w}); } void bd(long long x) { long long i, sz = al[x].size(), l; vtd[x] = 1; sbt[x] = fq[x]; for (i = 0; i < sz; i++) { l = al[x][i].first; if (!vtd[l]) { bd(l); sbt[x] += sbt[l]; } } } void dfs(long long x) { long long i, sz = al[x].size(), l, w; vtd[x] = 1; z = min(z, sm); for (i = 0; i < sz; i++) { l = al[x][i].first; w = al[x][i].second; if (!vtd[l]) { nn += sbt[x] - sbt[l]; sm += w * (nn - (n - nn)); dfs(l); sm -= w * (nn - (n - nn)); nn -= sbt[x] - sbt[l]; } } } int main() { long long i, j, k, l, w, ll, c, p = 0, sz, bg, lca; for (i = 2; i <= 5000; i++) { if (fz[i].empty()) { p++; for (j = i; j <= 5000; j += i) { for (c = 0, k = j; k % i == 0; k /= i, c++) ; fz[j].push_back({p, c}); dr[j] += c; } } } nm = 5000; for (i = 1; i <= 5000; i++) { sz = fz[i].size(); lca = dh[i - 1]; if (sz) { bg = fz[i][sz - 1].first; for (j = 1; j < bg; j++) { lca -= pd[j]; } } for (j = 0; j < sz; j++) { l = fz[i][j].first; w = fz[i][j].second; pd[l] += w; } dh[i] = dh[i - 1] + dr[i]; l = 0; for (; nn && sk[nn].second >= lca; nn--) { l = sk[nn].first; } if (l) { nn++; sk[nn] = {l, lca}; sz = pst[l].size(); if (lca < dh[pst[l][sz - 1]]) { nm++; dh[nm] = lca; pst[l].push_back(nm); sz++; } pr[i] = pst[l][sz - 1]; } nn++; sk[nn] = {i, dh[i]}; pst[i].push_back(i); } for (i = 1; i <= 5000; i++) { sz = pst[i].size(); for (j = 0; j < sz; j++) { l = pst[i][j]; if (j) { ae(ll, l, dh[ll] - dh[l]); } ll = l; } if (pr[i]) { ae(pst[i][sz - 1], pr[i], dh[pst[i][sz - 1]] - dh[pr[i]]); } } scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld , &k); k += !k; fq[k]++; sm += dh[k]; } bd(1); vtd.reset(); nn = 0; dfs(1); printf( %lld n , z); }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; int n, par[N], up[N], h[N], max_h[N]; vector<int> child[N], vec, ans; void dfs(int v = 0) { for (int u : child[v]) { h[u] = max_h[u] = h[v] + 1; dfs(u); max_h[v] = max(max_h[v], max_h[u]); } sort(child[v].begin(), child[v].end(), [](int u, int v) { return max_h[u] < max_h[v]; }); } void bamboo(int v = 0) { if (v) up[v] = vec.back(); vec.push_back(v); for (int u : child[v]) bamboo(u); } void solve(int v = 0) { while (v && up[v] != par[v]) { ans.push_back(v); up[v] = up[up[v]]; } for (int u : child[v]) solve(u); } int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { cin >> par[i]; child[par[i]].push_back(i); } dfs(); bamboo(); for (int v : vec) cout << v << ; cout << n ; solve(); cout << ans.size() << n ; for (int u : ans) cout << u << ; }
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: ldelay5.v,v 1.1 2001/12/26 23:45:57 sib4 Exp $
// Test for delays in structural logic. Multiple UDP instances.
module test;
wire [1:2] q, a, b;
drec U1(q[1], a[1], b[1]);
drec U2(q[2], a[2], b[2]);
initial $display("PASSED");
endmodule
module drec (q, a, b);
output q;
input a, b;
U_drec #1 U(q, a, b);
endmodule
primitive U_drec (q, a, b);
output q;
input a, b;
table
1 0 : 1 ;
0 1 : 0 ;
endtable
endprimitive
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int BIT[4][11][MAXN * 2], n; void add(int BIT[], int p, int x) { for (int i = p; i <= n; i += ((i) & (-(i)))) BIT[i] += x; } int ask(int BIT[], int p) { int res = 0; for (int i = p; i; i -= ((i) & (-(i)))) res += BIT[i]; return res; } char str[MAXN], tmp[11]; ; int biao[233]; int HASH(int i, int Base) { --i; return i / Base + (i % Base) * (n / Base) + min(i % Base, n % Base) + 1; } int main(void) { biao[ A ] = 0; biao[ G ] = 1; biao[ C ] = 2; biao[ T ] = 3; scanf( %s , str + 1); n = strlen(str + 1); for (int i = 1; i <= n; ++i) { str[i] = biao[str[i]]; for (int Base = 1; Base <= 10; ++Base) { add(BIT[str[i]][Base], HASH(i, Base), 1); } } int q; cin >> q; while (q--) { int op, l, r; scanf( %d%d , &op, &l); if (op == 1) { scanf( %s , tmp); for (int Base = 1; Base <= 10; ++Base) add(BIT[str[l]][Base], HASH(l, Base), -1); str[l] = biao[tmp[0]]; for (int Base = 1; Base <= 10; ++Base) add(BIT[str[l]][Base], HASH(l, Base), 1); } else { scanf( %d%s , &r, tmp); int Base = min(int(strlen(tmp)), r - l + 1), res = 0; for (int i = 0; i < Base; ++i) { res += ask(BIT[biao[tmp[i]]][Base], HASH((r - l - i) / Base * Base + l + i, Base)) - ask(BIT[biao[tmp[i]]][Base], HASH(l + i, Base) - 1); } printf( %d n , res); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_SYMBOL_V
`define SKY130_FD_SC_LP__ISOLATCH_SYMBOL_V
/**
* isolatch: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; if ((n - 1) * n / 2 <= k) { cout << no solution << endl; return 0; } long x, y; x = y = 0; while (n--) { cout << x << << y++ << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) cout << i << ; cout << endl; } return 0; }
|
module taxi_top (reset, pulse, clk,
price_seg1, price_seg2, price_seg3,
wait_time_seg1, wait_time_seg2,
mileage_seg1, mileage_seg2, mileage_seg3);
input reset;
input pulse,clk;
output [6:0] price_seg1, price_seg2, price_seg3,
wait_time_seg1, wait_time_seg2,
mileage_seg1, mileage_seg2, mileage_seg3;
//8 segments
wire [15:0] wait_time_BCD; //decimal values in BCD
wire [15:0] price_BCD;
wire [15:0] mileage_BCD;
wire [11:0] price;
wire [11:0] wait_time; //binary
wire [11:0] mileage;
wire clk_1;
wire clk_10000;
wire [11:0] number_of_halfkm;
wire work;
BCD_decode BCD_inst1(
.binary(wait_time),
.bcd(wait_time_BCD)
);
BCD_decode BCD_inst2(
.binary(price),
.bcd(price_BCD)
);
BCD_decode BCD_inst3(
.binary(mileage),
.bcd(mileage_BCD)
);
clk_1Hz M1(
.clk(clk),
.clk_1(clk_1)
);
clk_10000Hz M2(
.clk(clk),
.clk_10000(clk_10000)
);
round_counter_module rcm1(
.reset(reset),
.work(work),
.pulse(pulse),
.mileage(mileage),
.clk(clk_10000),
.number_of_halfkm(number_of_halfkm),
.clk_1(clk_1)
);
price_module price_inst(
.reset(reset),
.wait_time(wait_time),
.number_of_halfkm(number_of_halfkm),
.price(price)
);
wait_time_module wt(
.reset(reset),
.work(work),
.clk(clk_1),
.wait_time(wait_time)
);
decode hex1 (.data(price_BCD [3:0]),.hex(price_seg1));
decode hex2 (.data(price_BCD [7:4]),.hex(price_seg2));
decode hex3 (.data(price_BCD [11:8]),.hex(price_seg3));
decode hex4 (.data(mileage_BCD [3:0]),.hex(mileage_seg1));
decode hex5 (.data(mileage_BCD [7:4]),.hex(mileage_seg2));
decode hex6 (.data(mileage_BCD [11:8]),.hex(mileage_seg3));
decode hex7 (.data(wait_time_BCD [3:0]),.hex(wait_time_seg1));
decode hex8 (.data(wait_time_BCD [7:4]),.hex(wait_time_seg2));
endmodule
/*
LED dispay descriptions
left wait_time
middle mileage
right price
*/
|
#include <bits/stdc++.h> const int N = 1e6 + 10; const int M = 9699690; const int mod = 1e9 + 7, Gi = 332748118; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3fll; const int SIZE = 1 << 21; char ibuf[SIZE], *iS, *iT; using std::pair; template <class T> void read(T &x) { x = 0; int f = 0; char c = getchar(); while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = x * 10 + c - 0 , c = getchar(); if (f) x = -x; } int random(int i) { return rand() % i + 1; } template <class T> void ckmax(T &x, T y) { x = x > y ? x : y; } template <class T> void ckmin(T &x, T y) { x = x < y ? x : y; } template <class T> T Abs(T x) { return x > 0 ? x : -x; } inline int plus(int x, int y) { return x + y >= mod ? x + y - mod : x + y; } int qp(int d, int k) { int f = 1; while (k) { if (k & 1) f = (1ll * (f) * (d) % mod); d = (1ll * (d) * (d) % mod), k >>= 1; } return f; } int n, m, a[N], b[N], tmp[N]; pair<int, int> p[N]; long long ans; void msort(int l, int r) { if (l == r) return; int mid = l + r >> 1; msort(l, mid), msort(mid + 1, r); int lp = l, rp = mid + 1, ct = 0; while (lp <= mid && rp <= r) { if (a[lp] <= a[rp]) tmp[++ct] = a[lp++], ans += rp - 1 - mid; else tmp[++ct] = a[rp++]; } while (lp <= mid) tmp[++ct] = a[lp++], ans += rp - 1 - mid; while (rp <= r) tmp[++ct] = a[rp++]; for (int i = (l); i <= (r); i++) a[i] = tmp[i + 1 - l]; } int tag[N << 2], mi[N << 2]; void build(int id, int l, int r) { tag[id] = 0; if (l == r) { mi[id] = l - 1; return; } int mid = l + r >> 1; build(id << 1, l, mid), build(id << 1 | 1, mid + 1, r); mi[id] = std::min(mi[id << 1], mi[id << 1 | 1]); } void pushdown(int id) { if (tag[id]) { tag[id << 1] += tag[id]; tag[id << 1 | 1] += tag[id]; mi[id << 1] += tag[id]; mi[id << 1 | 1] += tag[id]; tag[id] = 0; } } void upt(int id, int L, int R, int l, int r, int d) { if (l <= L && R <= r) { tag[id] += d; mi[id] += d; return; } if (l > R || r < L) return; int Mid = L + R >> 1; pushdown(id); upt(id << 1, L, Mid, l, r, d); upt(id << 1 | 1, Mid + 1, R, l, r, d); mi[id] = std::min(mi[id << 1], mi[id << 1 | 1]); } void work() { read(n), read(m); for (int i = (1); i <= (n); i++) read(a[i]), p[i] = std::make_pair(a[i], i); ans = 0; msort(1, n); for (int i = (1); i <= (m); i++) read(b[i]); std::sort(p + 1, p + 1 + n); std::sort(b + 1, b + 1 + m); build(1, 1, n + 1); int ld = 1, lu = 1; for (int i = (1); i <= (m); i++) { while (ld <= n && p[ld].first <= b[i]) upt(1, 1, n + 1, p[ld++].second + 1, n + 1, -1); while (lu <= n && p[lu].first < b[i]) upt(1, 1, n + 1, 1, p[lu++].second, 1); ans += mi[1]; } printf( %lld n , ans); } int main() { int T = 1; read(T); while (T--) work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long modpow(long long a, long long b, long long mod = (long long)(1e9 + 7)) { if (!b) return 1; a %= mod; return modpow(a * a % mod, b / 2, mod) * (b & 1 ? a : 1) % mod; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int mxn = 1e5, mod = 1e9 + 9; long long ans = 0; int n; int x[mxn], y[mxn]; int support[mxn]; bool inqueue[mxn]; map<int, map<int, int> > ds; priority_queue<int, vector<int>, greater<int> > pq; priority_queue<int, vector<int>, less<int> > pq2; int take(int i, int j) { if (!ds.count(i) || !ds[i].count(j)) return -1; return ds[i][j]; } void supportAdjust(int i) { if (i == -1) return; support[i] = 0; for (int d = -1; d <= 1; d++) if (take(x[i] + d, y[i] - 1) != -1) support[i]++; if (y[i] == 0) support[i] = 30000; } void evaluate(int i) { if (i == -1) return; bool b4 = inqueue[i]; inqueue[i] = false; for (int d = -1; d <= 1; d++) if (take(x[i] + d, y[i] + 1) != -1) inqueue[i] |= support[take(x[i] + d, y[i] + 1)] == 1; inqueue[i] ^= 1; if (!b4 && inqueue[i]) { pq.push(i); pq2.push(i); } } void takeout(int turn) { int i; if (turn % 2 == 0) { while (pq2.size() && !inqueue[pq2.top()]) pq2.pop(); if (!pq2.size()) return; i = pq2.top(); pq2.pop(); } else { while (pq.size() && !inqueue[pq.top()]) pq.pop(); if (!pq.size()) return; i = pq.top(); pq.pop(); } ans = ((ans * n) % mod + i) % mod; inqueue[i] = 0; ds[x[i]].erase(y[i]); for (int d = -1; d <= 1; d++) supportAdjust(take(x[i] + d, y[i] + 1)); for (int d = -2; d <= 2; d++) evaluate(take(x[i] + d, y[i])); for (int d = -1; d <= 1; d++) evaluate(take(x[i] + d, y[i] - 1)); } void solve() { scanf( %d , &n); for (int i = 0; i < n; i++) inqueue[i] = 0; for (int i = 0; i < n; i++) { scanf( %d , &x[i]); scanf( %d , &y[i]); if (!ds.count(x[i])) ds[x[i]] = map<int, int>(); ds[x[i]][y[i]] = i; } for (int i = 0; i < n; i++) supportAdjust(i); for (int i = 0; i < n; i++) evaluate(i); for (int i = 0; i < n; i++) takeout(i); cout << ans % mod << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; }
|
//--------------------------------------------------------------------------------
//
// data_align.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// This module takes the sampled input, and shifts/compacts the data to
// eliminate any disabled groups. ie:
//
// Channels 0,1,2 are disabled:
// sto_data[7:0] = channel3 (sti_data[31:24])
//
// Channels 1,2 are disabled:
// sto_data[15:0] = {channel3,channel0} (sti_data[31:24],sti_data[7:0])
//
// Compacting the data like this allows for easier RLE & filling of SRAM.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module data_align #(
parameter integer DW = 32, // data width
parameter integer KW = DW/8 // keep width
)(
// system signals
input wire clk,
input wire rst,
// configuration/control signals
input wire [3:0] disabledGroups,
// input stream
input wire sti_valid,
input wire [31:0] sti_data,
// output stream
output reg sto_valid,
output reg [31:0] sto_data
);
//
// Registers...
//
reg [1:0] insel0;
reg [1:0] insel1;
reg insel2;
//
// Input data mux...
//
always @ (posedge clk)
begin
case (insel0[1:0])
2'h3 : sto_data[ 7: 0] <= sti_data[31:24];
2'h2 : sto_data[ 7: 0] <= sti_data[23:16];
2'h1 : sto_data[ 7: 0] <= sti_data[15: 8];
default : sto_data[ 7: 0] <= sti_data[ 7: 0];
endcase
case (insel1[1:0])
2'h2 : sto_data[15: 8] <= sti_data[31:24];
2'h1 : sto_data[15: 8] <= sti_data[23:16];
default : sto_data[15: 8] <= sti_data[15: 8];
endcase
case (insel2)
1'b1 : sto_data[23:16] <= sti_data[31:24];
default : sto_data[23:16] <= sti_data[23:16];
endcase
sto_data[31:24] <= sti_data[31:24];
end
//
// This block computes the mux settings for mapping the various
// possible channels combinations onto the 32 bit BRAM block.
//
// If one group is selected, inputs are mapped to bits [7:0].
// If two groups are selected, inputs are mapped to bits [15:0].
// If three groups are selected, inputs are mapped to bits [23:0].
// Otherwise, input pass unchanged...
//
// Each "insel" signal controls the select for an output mux.
//
// ie: insel0 controls what is -output- on bits[7:0].
// Thus, if insel0 equal 2, sto_data[7:0] = sti_data[23:16]
//
always @(posedge clk)
begin
case (disabledGroups)
// 24 bit configs...
4'b0001 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0010 : begin insel2 <= 1'b1; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b0100 : begin insel2 <= 1'b1; insel1 <= 2'h0; insel0 <= 2'h0; end
// 16 bit configs...
4'b0011 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h2; end
4'b0101 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h1; end
4'b1001 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h1; end
4'b0110 : begin insel2 <= 1'b0; insel1 <= 2'h2; insel0 <= 2'h0; end
4'b1010 : begin insel2 <= 1'b0; insel1 <= 2'h1; insel0 <= 2'h0; end
4'b1100 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
// 8 bit configs...
4'b0111 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h3; end
4'b1011 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h2; end
4'b1101 : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h1; end
// remaining
default : begin insel2 <= 1'b0; insel1 <= 2'h0; insel0 <= 2'h0; end
endcase
end
always @(posedge clk, posedge rst)
if (rst) sto_valid <= 1'b0;
else sto_valid <= sti_valid;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long qpow(long long x, long long y) { long long ret = 1; while (y) { if (y & 1) ret = ret * x % MOD; y >>= 1; x = x * x % MOD; } return ret % MOD; } int main() { long long n, sum = 0, C = 1; scanf( %lld , &n); for (int i = 1; i <= n; i++) { C = C * (n - i + 1) % MOD * qpow(i, MOD - 2) % MOD; if (i & 1) sum = (sum + C * qpow(3, i) % MOD * qpow(3, n * (n - i))) % MOD; else sum = ((sum - C * qpow(3, i) % MOD * qpow(3, n * (n - i))) % MOD + MOD) % MOD; } sum = sum * 2 % MOD; C = 1; long long ans = 0; for (int i = 0; i < n; i++) { if (i) C = C * (n - i + 1) % MOD * qpow(i, MOD - 2) % MOD; long long tmp = qpow(((1 - qpow(3, i)) % MOD + MOD) % MOD, n); if (n & 1) tmp = (tmp + qpow(3, i * n)) % MOD; else tmp = (tmp - qpow(3, i * n) + MOD) % MOD; if (i & 1) ans = (ans + tmp * C) % MOD; else ans = ((ans - tmp * C) % MOD + MOD) % MOD; } cout << (sum + ans * 3) % MOD << endl; return 0; }
|
/// date:2016/3/5 3/6 am: 10:57 done!
/// engineer:ZhaiShaoMIn
/// module function:because there are two kinds of uploadregs to
/// OUT_rep: inst_cache ,data_cache and memory, so we need to determine which can be writed into OUT_rep.
module arbiter_for_OUT_rep(//input
clk,
rst,
OUT_rep_rdy,
v_dc_rep,
v_mem_rep,
dc_rep_flit,
mem_rep_flit,
dc_rep_ctrl,
mem_rep_ctrl,
//output
ack_OUT_rep,
ack_dc_rep,
ack_mem_rep,
select // select 1/2
);
//input
input clk;
input rst;
input OUT_rep_rdy;
input v_dc_rep;
input v_mem_rep;
input [15:0] dc_rep_flit;
input [15:0] mem_rep_flit;
input [1:0] dc_rep_ctrl;
input [1:0] mem_rep_ctrl;
//output
output ack_OUT_rep;
output ack_dc_rep;
output ack_mem_rep;
output [1:0] select; // select 1/2
//parameter for fsm state
parameter arbiter_idle=3'b001;
parameter dc_uploading=3'b010;
parameter mem_uploading=3'b100;
//parameter of cmd
parameter nackrep_cmd=5'b10101;
parameter SCflurep_cmd=5'b11100;
reg [2:0] nstate;
reg [2:0] state;
reg priority1;
reg ack_OUT_rep;
reg ack_dc_rep;
reg ack_mem_rep;
reg update_priority;
reg [1:0] select;
/// nstate and output function
always@(*)
begin
nstate=state;
ack_OUT_rep=1'b0;
ack_dc_rep=1'b0;
ack_mem_rep=1'b0;
update_priority=1'b0;
select=2'b00;
case(state)
arbiter_idle:
begin
if({v_dc_rep,v_mem_rep}==2'b11)
begin
update_priority=1'b1;
if(priority1)
begin
nstate=dc_uploading;
end
else
begin
nstate=mem_uploading;
end
end
else if({v_dc_rep,v_mem_rep}==2'b01)
begin
nstate=mem_uploading;
end
else if({v_dc_rep,v_mem_rep}==2'b10)
begin
nstate=dc_uploading;
end
end
dc_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_dc_rep=1'b1;
select=2'b01;
if(dc_rep_ctrl==2'b11||dc_rep_ctrl==2'b01&&(dc_rep_flit[9:5]==SCflurep_cmd||dc_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
mem_uploading:
begin
if(OUT_rep_rdy)
begin
ack_OUT_rep=1'b1;
ack_mem_rep=1'b1;
select=2'b10;
if(mem_rep_ctrl==2'b11||mem_rep_ctrl==2'b01&&(mem_rep_flit[9:5]==SCflurep_cmd||mem_rep_flit[9:5]==nackrep_cmd))
begin
nstate=arbiter_idle;
end
end
end
endcase
end
// fsm state reg
always@(posedge clk)
begin
if(rst)
state<=3'b001;
else
state<=nstate;
end
always@(posedge clk)
begin
if(rst)
priority1<=1'b0;
else if(update_priority)
priority1<=~priority1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9 + 7; const int N = (int)3e5 + 4; const int M = 1001; int n, k; int a[6]; double ans; void f(int s) { if (s == k) { for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { if (a[i] > a[j]) { ++ans; } } } return; } for (int i = 0; i < n; ++i) { for (int j = i; j < n; ++j) { reverse(a + i, a + j + 1); f(s + 1); reverse(a + i, a + j + 1); } } } int main() { cin >> n >> k; for (int i = 0; i < n; ++i) { cin >> a[i]; } f(0); for (int i = 0; i < k; ++i) { ans /= n; ans /= (n + 1); ans *= 2.0; } printf( %.10lf , ans); return 0; }
|
// Author: Adam Nunez,
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module KeyPadScanner(
input Reset,
input Clock,
input [3:0] RowIn,
output [3:0] ColOut,
output reg LFSRReset,
input LFSRFlg,
output reg [3:0] RowColVector,
output reg KeyRdy,
input KeyRd
);
// This module assumes an 8-pin 4 by 4 matrix keypad is connected
// with its input pins on ColOut and output pin on RowIn. The
// Scanner flips through columns on the key pad checking if a key is
// depressed, when one is found the KeyRdy signal is set high, the
// key data is placed on RowColVector and the scanner waits for KeyRd
// to continue scanning.
parameter Scan=2'b00, Calculate=2'b01, Analyize=2'b10, WaitForRead=2'b11;
reg [1:0] State;
reg [2:0] Counter;
reg [15:0] Data;
reg [3:0] Col;
reg [3:0] Sum;
reg ZeroChecker;
reg waitbit;
assign ColOut[0] = Col[0] ? 1'bz : 1'b0;
assign ColOut[1] = Col[1] ? 1'bz : 1'b0;
assign ColOut[2] = Col[2] ? 1'bz : 1'b0;
assign ColOut[3] = Col[3] ? 1'bz : 1'b0;
always @(posedge Clock, negedge Reset) begin
if (Reset == 0) begin
State <= Scan;
Col <= 4'b0111;
LFSRReset <= 0;
KeyRdy <= 0;
RowColVector <= 4'b1101;
Counter <= 0;
Data <= 16'hFFFF;
Sum <= 0;
ZeroChecker <= 0;
waitbit <= 0;
end
else begin
case(State)
Scan: begin
if(LFSRFlg == 1) begin
case(Col)
4'b0111: begin
if(waitbit == 1) begin
Data[15:12] <= RowIn;
Col <= 4'b1011;
waitbit <= 0;
end
else waitbit <= 1;
end
4'b1011: begin
if(waitbit == 1) begin
Data[11:8] <= RowIn;
Col <= 4'b1101;
waitbit <= 0;
end
else waitbit <= 1;
end
4'b1101: begin
if(waitbit == 1) begin
Data[7:4] <= RowIn;
Col <= 4'b1110;
waitbit <= 0;
end
else waitbit <= 1;
end
4'b1110: begin
if(waitbit == 1) begin
Data[3:0] <= RowIn;
Col <= 4'b0111;
State <= Calculate;
waitbit <= 0;
end
else waitbit <= 1;
end
default: begin
Col <= 4'b1110;
Counter <= 0;
end
endcase
LFSRReset <= 0;
end
else begin
LFSRReset <= 1;
end
end
Calculate: begin
Sum <= ~Data[0] + ~Data[1] + ~Data[2] + ~Data[3]
+ ~Data[4] + ~Data[5] + ~Data[6] + ~Data[7]
+ ~Data[8] + ~Data[9] + ~Data[10] + ~Data[11]
+ ~Data[12] + ~Data[13] + ~Data[14] + ~Data[15];
State <= Analyize;
end
Analyize: begin
if (ZeroChecker== 1'b1) begin
if(Sum == 4'b0001) begin
Counter <= Counter + 1'b1;
if(Counter == 3'b100) begin
case(Data)
16'hFFFE : RowColVector <= 4'b0000;
16'hFFFD : RowColVector <= 4'b0100;
16'hFFFB : RowColVector <= 4'b1000;
16'hFFF7 : RowColVector <= 4'b1100;
16'hFFEF : RowColVector <= 4'b0001;
16'hFFDF : RowColVector <= 4'b0101;
16'hFFBF : RowColVector <= 4'b1001;
16'hFF7F : RowColVector <= 4'b1101;
16'hFEFF : RowColVector <= 4'b0010;
16'hFDFF : RowColVector <= 4'b0110;
16'hFBFF : RowColVector <= 4'b1010;
16'hF7FF : RowColVector <= 4'b1110;
16'hEFFF : RowColVector <= 4'b0011;
16'hDFFF : RowColVector <= 4'b0111;
16'hBFFF : RowColVector <= 4'b1011;
16'h7FFF : RowColVector <= 4'b1111;
default : RowColVector <= 4'b0000;
endcase
KeyRdy <= 1;
State <= WaitForRead;
Counter <= 0;
ZeroChecker <= 0;
end
end
else if (Sum == 4'b0000) begin
Counter <= 0;
State <= Scan;
end
else begin
ZeroChecker <= 1'b0;
Counter <= 0;
State <= Scan;
end
end
else if (Sum == 4'b0000) begin
ZeroChecker <= 1'b1;
State <= Scan;
end
else State <= Scan;
end
WaitForRead: begin
if(KeyRd == 1) begin
KeyRdy <= 0;
LFSRReset <= 0;
State <= Scan;
end
end
default: begin
State <= Scan;
Col <= 4'b1110;
LFSRReset <= 0;
KeyRdy <= 1;
RowColVector <= 4'b1111;
Counter <= 0;
Data <= 16'hFFFF;
Sum <= 0;
end
endcase
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* - Supports input and/or output registers on FIFO
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
*
* fifo_v #(.fifo_elements_t(int), .size(8), .output_reg(1)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers with output register
*
* Output Register
* ===============
*
* Instantiate a FIFO of length (size-1) + an output register and bypass logic
*
* output_reg = 0 (default) - no output register
* output_reg = 1 - instantiate a single output register
*
* _
* ______ |\ | |
* _|-[_FIFO_]-->| |__| |__ Out
* |----------->| | |_|
* bypass |/ Reg.
*
*
* Input Register
* ==============
*
* input_reg = 0 (default) - no input register, FIFO receives data directly
* input_reg = 1 - assume **external** input register and bypass logic
* input_reg = 2 - instantiate input register and bypass logic
*
* In case 1. the FIFO is still of length 'size' as it is assumed the external
* input register is always enabled (used when building VC buffers).
*
* _ ______ |\
* | | |-[_FIFO_]-->| |___ Out
* | |__|___________>| |
* |_| |/
* Reg.
*
* Input and Output Registers
* ==========================
*
* Can set input_reg=2, output_reg=1 to create FIFO with both input and output
* registers. FIFO behaviour remains identical at the cycle-level with the
* addition of input/output registers.
*
* InReg OutReg
* _ ______ _
* | |---[_FIFO_]---| |
* | | |____________| |___|\
* |_| | |_| | |__ Out
* |__________________| |
* |/
* FIFO Initialisation
* ===================
*
* init_fifo_contents = 0 - FIFO is empty on reset
* init_fifo_contents = 1 - FIFO is nearly_full on reset (mem[i]=1'b1<<i, mem[size]=0)
* init_fifo_contents = 2 - FIFO is nearly empty on reset (mem[0]=1)
*
*
* ===============================================================================
*/
// other FIFO types: double buffered, two slower FIFOs + output register
// FIFOs with second entry outputs (as required by router)
// pending write input register
//
// - second output with output registers [two output registers?]
//
//`ifdef VCS
//import fifo_package::*;
//`endif
/************************************************************************************
*
* FIFO
*
************************************************************************************/
//typedef flit_t fifo_elements_t;
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
} fifov_flags_t;
`include "types.v"
module LAG_fifo_v_ (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer_ #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags_ #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags_ (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer_ (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); multiset<int> list; for (int i = 0; i < n; i++) { cin >> v[i]; } for (int i = 0; i < n; i++) { int x; cin >> x; list.insert(x); } for (int i = 0; i < n; ++i) { auto current = list.lower_bound(n - v[i]); if (current == list.end()) { current = list.begin(); } cout << (v[i] + *current) % n << ; list.erase(current); } }
|
#include <bits/stdc++.h> using namespace std; int n, q, k; struct node { int c[2], fa, siz, tot; int val, id, mid, mv; bool rev; node() { rev = false; } } t[600010]; void maintain(int rt) { t[rt].siz = t[t[rt].c[0]].siz + t[t[rt].c[1]].siz + t[rt].tot; t[rt].mid = t[rt].id; t[rt].mv = t[rt].val; if (t[rt].c[0] && t[t[rt].c[0]].mv < t[rt].mv) t[rt].mv = t[t[rt].c[0]].mv, t[rt].mid = t[t[rt].c[0]].mid; if (t[rt].c[1] && t[t[rt].c[1]].mv < t[rt].mv) t[rt].mv = t[t[rt].c[1]].mv, t[rt].mid = t[t[rt].c[1]].mid; return; } bool isroot(int k) { return (t[t[k].fa].c[0] != k && t[t[k].fa].c[1] != k); } void connect(int k, int f, int p) { t[k].fa = f; t[f].c[p] = k; return; } int id(int k) { return (t[t[k].fa].c[0] == k ? 0 : 1); } void rotate(int x) { int y = t[x].fa, z = t[y].fa, fx = id(x), fy = id(y); if (!isroot(y)) t[z].c[fy] = x; t[x].fa = z; connect(t[x].c[fx ^ 1], y, fx); connect(y, x, fx ^ 1); maintain(y); maintain(x); return; } void pushdown(int rt) { if (!t[rt].rev) return; t[t[rt].c[0]].rev ^= 1; t[t[rt].c[1]].rev ^= 1; swap(t[rt].c[0], t[rt].c[1]); t[rt].rev = false; return; } stack<int> s; void splay(int x) { s.push(x); for (int i = x; !isroot(i); i = t[i].fa) s.push(t[i].fa); while (!s.empty()) { pushdown(s.top()); s.pop(); } while (!isroot(x)) { int y = t[x].fa; if (isroot(y)) { rotate(x); break; } if (id(x) == id(y)) { rotate(y); rotate(x); } else { rotate(x); rotate(x); } } return; } void access(int k) { for (int i = 0; k; i = k, k = t[k].fa) { splay(k); t[k].tot += t[t[k].c[1]].siz; t[k].tot -= t[i].siz; t[k].c[1] = i; maintain(k); } return; } void makeroot(int k) { access(k); splay(k); t[k].rev ^= 1; return; } void link(int x, int y) { makeroot(x); makeroot(y); t[x].fa = y; t[y].tot += t[x].siz; maintain(y); return; } void cut(int x, int y) { makeroot(x); access(y); splay(x); t[x].c[1] = 0; t[y].fa = 0; t[x].siz -= t[y].siz; maintain(x); return; } struct edge { int u, v, t; bool del; } es[600010]; int en = 0; int main() { scanf( %d%d%d , &n, &q, &k); int ecur = 0; int cur = 1; int ty, x, y; for (int i = 1; i <= n; ++i) t[i].siz = t[i].tot = 1, t[i].val = t[i].mv = 0x3f3f3f3f; for (int i = 1; i <= q; ++i) { scanf( %d , &ty); if (ty == 1) { scanf( %d%d , &x, &y); es[++en] = (edge){x, y, cur, false}; makeroot(x); access(y); splay(x); int v = y; while (t[v].fa) v = t[v].fa; if (v == x) { splay(y); int cute = t[y].mid; cut(es[cute].u, cute + n); cut(es[cute].v, cute + n); es[cute].del = true; } t[en + n].siz = 1; t[en + n].val = cur; t[en + n].id = en; t[en + n].mv = cur; t[en + n].mid = en; link(x, en + n); link(y, en + n); } if (ty == 2) { scanf( %d , &x); makeroot(x); printf( %d n , t[x].siz); } if (ty == 3) { ++cur; while (ecur < en && es[ecur + 1].t <= cur - k) { ++ecur; if (!es[ecur].del) { cut(es[ecur].u, ecur + n); cut(es[ecur].v, ecur + n); } } } } return 0; }
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample tests that the supply0 and supply1 nets take on
* the proper initial value. This adds to the supply1 test some
* constant drivers that could tickle constant propagation bugs.
*/
module test;
supply0 gnd;
supply1 vdd;
// These should drop away as meaningless.
assign gnd = 1;
assign vdd = 0;
initial begin #1
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int get(int x) { int cnt = 0; while (x >= 10) { int sum = 0; while (x) { sum += x % 10; x /= 10; } cnt++; x = sum; } return cnt; } int main() { string s; cin >> s; if (s.size() == 1) cout << 0 << endl; else { int n = 0; for (int i = 0; i < s.size(); i++) n += s[i] - 0 ; cout << get(n) + 1 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, r; cin >> n >> r; if (r <= (n + 1) / 2) { cout << (2 * r - 1) << endl; } else { r -= (n + 1) / 2; cout << 2 * r << endl; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_BEHAVIORAL_V
|
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