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#include <bits/stdc++.h> using namespace std; template <class T, class V> ostream& operator<<(ostream& s, pair<T, V> a) { s << a.first << << a.second; return s; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long int T = 1; cin >> T; for (long long int qq = 1; qq <= T; qq++) { long long int n; string a, b; cin >> n >> a >> b; vector<long long int> ans; long long int f = 0, l = n - 1, r = 0; for (int i = n - 1; i >= 0; i--) { if (b[i] - 0 != ((a[l] - 0 ) ^ f)) { if (a[l] != a[r]) a[r] = (a[r] - 0 ) ^ 1 + 0 , ans.push_back(1); f ^= 1; ans.push_back(i + 1); swap(l, r); } if (l > r) l--; else l++; } cout << ans.size(); for (auto x : ans) cout << << x; cout << endl; } }
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#include <bits/stdc++.h> using namespace std; long long a, b, ans; void gcd(long long a, long long b) { if (a == 0 || b == 0) return; if (a > b) swap(a, b); ans += (b / a); gcd(b % a, a); } int main() { cin >> a >> b; gcd(a, b); cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { int a, b, c = 0; cin >> a >> b; int x[10] = {6, 2, 5, 5, 4, 5, 6, 3, 7, 6}; for (int i = a; i <= b; i++) { int y = i; while (y != 0) { c += x[y % 10]; y = y / 10; } } cout << c; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.06.2017 00:42:43
// Design Name:
// Module Name: PS2_y_display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PS2_y_display(
input CLK100MHZ,
input CPU_RESETN,
input PS2_CLK,
input PS2_DATA,
output [7:0] AN,
output CA,CB,CC,CD,CE,CF,CG,DP,
output [31:0] cifras
);
wire reset;
wire reloj_lento;
wire clock;
wire [7:0] data;
wire [2:0] control;
wire [4:0] tecla;
wire [2:0] data_type;
wire kbs_tot;
reg [3:0] cifra1,cifra2,cifra3,cifra4,cifra5,cifra6,cifra7,cifra8;
reg [3:0] cifra1_next,cifra2_next,cifra3_next,cifra4_next,cifra5_next,cifra6_next,cifra7_next,cifra8_next;
assign reset= ~CPU_RESETN;
assign clock= CLK100MHZ;
assign cifras={cifra1,cifra2,cifra3,cifra4,cifra5,cifra6,cifra7,cifra8};
clock_divider clock_div(
.clk(clock),
.rst (reset),
.clk_div (reloj_lento)
);
teclado tec(
.ps2_data(data),
.val(tecla),
.control(control),
.leds ()
);
kbd_ms driver_tec(
.clk(CLK100MHZ),
.rst(reset),
.kd(PS2_DATA),
.kc(PS2_CLK),
.new_data(data),
.data_type(data_type),
.kbs_tot(kbs_tot),
.parity_error()
);
display dis(
.clk_display(reloj_lento),
.num(cifras),
.puntos(),
.anodos(AN[7:0]),
.segmentos({CA,CB,CC,CD,CE,CF,CG,DP})
);
always @(*) begin
if ((kbs_tot) & (data_type==3'd1) & (control==3'b1)) begin
cifra8_next=tecla[3:0];
cifra7_next=cifra8;
cifra6_next=cifra7;
cifra5_next=cifra6;
cifra4_next=cifra5;
cifra3_next=cifra4;
cifra2_next=cifra3;
cifra1_next=cifra2;
end
else begin
cifra8_next=cifra8;
cifra7_next=cifra7;
cifra6_next=cifra6;
cifra5_next=cifra5;
cifra4_next=cifra4;
cifra3_next=cifra3;
cifra2_next=cifra2;
cifra1_next=cifra1;
end
end
always @(posedge clock) begin
if (reset) begin
cifra1<=4'b0;
cifra2<=4'b0;
cifra3<=4'b0;
cifra4<=4'b0;
cifra5<=4'b0;
cifra6<=4'b0;
cifra7<=4'b0;
cifra8<=4'b0;
end
else begin
cifra1<=cifra1_next;
cifra2<=cifra2_next;
cifra3<=cifra3_next;
cifra4<=cifra4_next;
cifra5<=cifra5_next;
cifra6<=cifra6_next;
cifra7<=cifra7_next;
cifra8<=cifra8_next;
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; long long K, N; string A, B; bool valid[1001]; long long dp[100002][2]; int main() { ios::sync_with_stdio(0); cin >> A >> B >> K; N = A.size(); dp[0][0] = 1, dp[0][1] = 0; for (int i = 1; i <= K; ++i) { dp[i][0] = (N - 1) * dp[i - 1][1]; dp[i][1] = dp[i - 1][0] + (N - 2) * dp[i - 1][1]; dp[i][0] %= 1000000007; dp[i][1] %= 1000000007; } long long ans = 0; for (int i = 0; i < N; ++i) { valid[i] = true; for (int j = 0; j < N; ++j) if (A[j % N] != B[(i + j) % N]) valid[i] = false; if (valid[i]) { if (i == 0) ans = (ans + dp[K][0]) % 1000000007; else ans = (ans + dp[K][1]) % 1000000007; } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; long long zero = 0; long long one = 1; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b) * b); } long long expo(long long x, long long y) { long long res = 1; x = x % 1000000007; while (y > 0) { if (y & 1) res = (1ll * res * x) % 1000000007; y = y >> 1; x = (1ll * x * x) % 1000000007; } return res; } long long ncr(long long n, long long r) { long long res = 1; if (r > n - r) r = n - r; for (long long i = 0; i < r; i++) { res *= n - i; res /= i + 1; } return res; } long long max(long long a, long long b) { return (a > b) ? a : b; } bool prime(long long n) { long long i; for (i = 2; i <= sqrt(n); i++) { if (n % i == 0) return false; } return true; } bool sortbysec(const pair<long long, long long> &a, const pair<long long, long long> &b) { if (a.second == b.second) return a.first < b.first; return (a.second < b.second); } long long rr[] = { 0, 1, 1, 1, 0, -1, -1, -1, }; long long cc[] = {1, 1, 0, -1, -1, -1, 0, 1}; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; string s; cin >> s; if (n == 1) return cout << 0, 0; long long dp[2][n]; memset(dp, 0, sizeof(dp)); dp[0][0] = (s[0] == 0 ); dp[1][0] = (s[0] == 1 ); for (long long i = 1; i < n; i++) { dp[1][i] = dp[0][i - 1] + (s[i] == 1 ); dp[0][i] = dp[1][i - 1] + (s[i] == 0 ); } cout << min(dp[0][n - 1], dp[1][n - 1]); }
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# include<bits/stdc++.h> using namespace std; int main() { int a,b,c=0;set<int>s; cin>>a>>b; while(a) { c++; s.insert(a%b); a/=b; } if(c==s.size()) cout<< YES <<endl; else cout<< NO <<endl; return 0; }
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//MODULE REFERENCE
`define tenv_usb_encoder tenv_usbhost.tenv_usb_encoder
`define tenv_usb_decoder tenv_usbhost.tenv_usb_decoder
//MODULE INCLUDING
`include "tenv_usbhost/tenv_usb_decoder.v"
`include "tenv_usbhost/tenv_usb_encoder.v"
module tenv_usbhost #(parameter PACKET_MAXSIZE=64,
parameter DATA_MAXSIZE=64);
//IFACE
wire dp, dn;
real bit_time=10;
reg speed=1;
reg signed[31:0] jitter=0;
reg signed[31:0] jitter_sync1=0;
reg signed[31:0] jitter_sync2=0;
reg signed[31:0] jitter_lastbit=0;
reg sync_corrupt=0;
reg[7:0] err_pid=0;
reg[15:0] err_crc=0;
reg err_bitstuff;
reg[7:0] buffer[DATA_MAXSIZE-1:0];
reg[6:0] dev_addr=0;
reg[15:0] toggle_bit=0;
//TRANSACTION MODES
localparam HSK_ACK=0,//IN_TRANSACTION: HOST WAITS DATA THEN
//SENDS ACK HANDSHAKE
//OUT/SETUP_TRANSACTION: HOST SENDS DATA
//THEN WAITS ACK HANDSHAKE
HSK_NAK=1,//IN_TRANSACTION: HOST WAITS NAK HANDSHAKE
//INSTEAD DATA
//OUT/SETUP_TRANSACTION: HOST SENDS DATA
//THEN WAITS NAK HANDSHAKE
HSK_STALL=2,//IN_TRANSACTION: HOST WAITS STALL
//HANDSHAKE INSTEAD DATA
//OUT/SETUP_TRANSACTION: HOST SENDS DATA
//THEN WAITS STALL HANDSHAKE
HSK_NO=3,//IN_TRANSACTION: HOST WAITS DATA THEN
//DOESN'T SEND HANDSHAKE IT IS USED
//BY ISOCHRONOUS TRANSFERS
//OUT/SETUP_TRANSACTION: HOST SENDS DATA
//THEN DOESN'T WAIT HANDSHAKE IT IS USED
//BY ISOCHRONOUS TRANSFERS
HSK_ERR=4,//IN_TRANSACTION: HOST WAITS DATA THEN
//DOESN'T SEND HANDSHAKE AND MAKES SILENT
//FOR 16 BIT TIMES
//OUT/SETUP_TRANSACTION: HOST SENDS DATA
//THEN CHECKS THAT DEVICE DOESN'T SENDS
//HANDSHAKE FOR 18 BIT TIMES
DATA_ERR=5;//IN_TRANSACTION: HOST SENDS TOKEN THEN
//CHECKS THAT DEVICE DOESN'T SEND
//ANYTHING FOR 18 BIT TIMES
//STANDARD REQUESTS MODES
localparam REQ_OK=0,
REQ_SETUPERR=1,//ON SETUP STAGE HOST DOESN'T WAIT
//HANDSHAKE AND SKIPS DATA, STATUS STAGES
REQ_STATSTALL=2;//ON STATUS STAGE HOST RECEIVES
//STALL HANDSHAKE
//LOCALS
localparam block_name="tenv_usbhost";
reg[7:0] bm_request_type=0;
reg[7:0] b_request=0;
reg[15:0] w_value=0;
reg[15:0] w_index=0;
reg[15:0] w_length=0;
localparam GET_STATUS=8'd0,
CLEAR_FEATURE=8'd1,
SET_FEATURE=8'd3,
SET_ADDRESS=8'd5,
GET_DESCRIPTOR=8'd6,
SET_DESCRIPTOR=8'd7,
GET_CONFIGURATION=8'd8,
SET_CONFIGURATION=8'd9,
GET_INTERFACE=8'd10,
SET_INTERFACE=8'd11,
SYNCH_FRAME=8'd12;
//TASKS
`include "tenv_usbhost/tenv_usbhost.usb_reset.v"
`include "tenv_usbhost/tenv_usbhost.wakeup_detect.v"
`include "tenv_usbhost/tenv_usbhost.gen_data.v"
`include "tenv_usbhost/tenv_usbhost.trsac_in.v"
`include "tenv_usbhost/tenv_usbhost.trsac_out.v"
`include "tenv_usbhost/tenv_usbhost.trsac_setup.v"
`include "tenv_usbhost/tenv_usbhost.trsac_sof.v"
`include "tenv_usbhost/tenv_usbhost.trfer_isoch_out.v"
`include "tenv_usbhost/tenv_usbhost.trfer_isoch_in.v"
`include "tenv_usbhost/tenv_usbhost.trfer_bulk_in.v"
`include "tenv_usbhost/tenv_usbhost.trfer_bulk_out.v"
`include "tenv_usbhost/tenv_usbhost.trfer_control_in.v"
`include "tenv_usbhost/tenv_usbhost.trfer_control_out.v"
`include "tenv_usbhost/tenv_usbhost.reqstd_getdesc.v"
`include "tenv_usbhost/tenv_usbhost.reqstd_setaddr.v"
`include "tenv_usbhost/tenv_usbhost.reqstd_setconf.v"
`include "tenv_usbhost/tenv_usbhost.reqstd_clrfeat.v"
//ENCODER
always @* `tenv_usb_encoder.jitter=jitter;
always @* `tenv_usb_encoder.jitter_sync1=jitter_sync1;
always @* `tenv_usb_encoder.jitter_sync2=jitter_sync2;
always @* `tenv_usb_encoder.jitter_lastbit=jitter_lastbit;
always @* `tenv_usb_encoder.sync_corrupt=sync_corrupt;
always @* `tenv_usb_encoder.err_pid=err_pid;
always @* `tenv_usb_encoder.err_crc=err_crc;
always @* `tenv_usb_encoder.err_bitstuff=err_bitstuff;
always @* `tenv_usb_encoder.bit_time=bit_time;
always @* `tenv_usb_encoder.speed=speed;
tenv_usb_encoder #(.PACKET_MAXSIZE(PACKET_MAXSIZE)) tenv_usb_encoder();
//DECODER
always @* `tenv_usb_decoder.bit_time=bit_time;
always @* `tenv_usb_decoder.speed=speed;
tenv_usb_decoder #(.PACKET_MAXSIZE(PACKET_MAXSIZE)) tenv_usb_decoder();
//TRANSCEIVER
assign dp= `tenv_usb_encoder.doe ? `tenv_usb_encoder.dplus : 1'bz;
assign dn= `tenv_usb_encoder.doe ? `tenv_usb_encoder.dminus : 1'bz;
assign `tenv_usb_decoder.dplus=dp;
assign `tenv_usb_decoder.dminus=dn;
endmodule
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#include <bits/stdc++.h> using namespace std; long long derangements(long long n) { if (n == 0) return 1; if (n == 1) return 0; if (n == 2) return 1; return (n - 1) * (derangements(n - 1) + derangements(n - 2)); } long long nCr(long long n, long long r) { long long res = 1; if (r == 0) return res; for (long long i = 0; i < r; i++) res *= (n - i); for (long long i = 2; i <= r; i++) res /= i; return res; } int32_t main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, k, ans = 0; cin >> n >> k; for (long long i = 0; i <= k; i++) ans += (nCr(n, i) * derangements(i)); cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; long long x, a[N], b[N]; long long n, k; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + 1 + n); b[1] = a[1]; int j = 2; for (int i = 2; i <= n; i++) { if (a[i] != a[i - 1]) { b[j] = a[i] - a[i - 1]; j++; } } for (int i = 1; i <= k; i++) { cout << b[i] << n ; } }
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#include <bits/stdc++.h> using namespace std; long long int pows[51]; vector<int> base_3(long long int n) { vector<int> f(51); int r = 0; while (n > 0) { f[r++] = (int)n % 3; n /= 3; } return f; } int main() { int q; cin >> q; pows[1] = 3; pows[0] = 1; for (int i = 1; i <= 50; i++) { pows[i] = pows[i - 1] * 3; } while (q--) { long long int n; cin >> n; vector<int> v = base_3(n); int ind = -1; for (int j = 50; j >= 0; j--) { if (v[j] == 2 && ind == -1) { ind = j; } } if (ind == -1) { cout << n << n ; } else { int r = ind + 1; while (r < 50 && v[r] == 1) { r++; } v[r] = 1; for (int i = 0; i < r; i++) { v[i] = 0; } long long int ans = 0; for (int j = 0; j < 51; j++) { ans += v[j] * pows[j]; } cout << ans << n ; } } return 0; }
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// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.4 2007/03/05 13:33:59 wig Exp $
// $Date: 2007/03/05 13:33:59 $
// $Log: ent_bb.v,v $
// Revision 1.4 2007/03/05 13:33:59 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No user `defines in this module
module ent_bb
//
// Generated Module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
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#include <bits/stdc++.h> using namespace std; bool check(long long mid, vector<long long> &d, vector<long long> &prep) { long long n = d.size(); long long m = prep.size() - 1; vector<long long> pos(m + 1, -1); for (long long i = 0; i <= mid; i++) pos[d[i]] = i; for (long long i = 1; i <= m; i++) if (pos[i] == -1) return false; long long prep_days = 0; for (long long i = 0; i <= mid; i++) { if (d[i] == 0) prep_days++; else if (pos[d[i]] == i) { if (prep_days < prep[d[i]]) return false; else prep_days -= prep[d[i]]; } else prep_days++; } return true; } int32_t main() { long long n, m; cin >> n >> m; vector<long long> d(n); for (long long &i : d) cin >> i; vector<long long> prep(m + 1); for (long long i = 1; i <= m; i++) cin >> prep[i]; long long l = 0, r = n - 1; while (l < r) { long long mid = (l + r) / 2; if (check(mid, d, prep)) { r = mid; } else { l = mid + 1; } } if (r == n - 1) { if (check(r, d, prep)) cout << n << n ; else cout << -1 << n ; } else cout << r + 1 << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, v, cost, i; cin >> n >> v; if (v >= (n - 1)) cout << n - 1; else { cost = v; for (i = 2; i <= n; i++) { v--; if ((n - i) <= v) { cout << cost; break; } else { cost += i; v++; } } } cout << n ; return 0; }
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/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ()
//Last Modified: Feb 25 2014
//Description: MBUS Example Testbench
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
`timescale 1ns/1ps
module mbus_example_test();
reg MBUS_CLKIN;
reg RESETn;
wire CTRL_CLKOUT;
wire CTRL_DOUT;
wire CTRL_CLKOUT_FROM_BUS;
wire CTRL_DOUT_FROM_BUS;
wire MBUS_EXAMPLE_CLKOUT;
wire MBUS_EXAMPLE_DOUT;
reg TX_REQ;
wire TX_ACK;
reg [31:0] TX_ADDR;
reg [31:0] TX_DATA;
wire TX_FAIL;
wire TX_SUCC;
wire RX_REQ;
reg RX_ACK;
wire [31:0] RX_ADDR;
wire [31:0] RX_DATA;
wire RX_BROADCAST;
wire RX_FAIL;
wire RX_PEND;
mbus_ctrl_wrapper mbus_ctrl_wrapper_test
(
.CLK_EXT (MBUS_CLKIN),
.RESETn (RESETn),
.CLKIN (MBUS_EXAMPLE_CLKOUT),
.CLKOUT (CTRL_CLKOUT_FROM_BUS),
.DIN (MBUS_EXAMPLE_DOUT),
.DOUT (CTRL_DOUT_FROM_BUS),
.TX_ADDR (TX_ADDR),
.TX_DATA (TX_DATA),
.TX_PEND (1'b0),
.TX_REQ (TX_REQ),
.TX_PRIORITY (1'b0),
.TX_ACK (TX_ACK), // just for monitor
.RX_ADDR (RX_ADDR),
.RX_DATA (RX_DATA),
.RX_REQ (RX_REQ),
.RX_ACK (RX_ACK),
.RX_BROADCAST (RX_BROADCAST),
.RX_FAIL (RX_FAIL),
.RX_PEND (RX_PEND),
.TX_FAIL (TX_FAIL),
.TX_SUCC (TX_SUCC),
.TX_RESP_ACK (1'b0),
.THRESHOLD (20'hFFFFF), //don't care
// power gated signals from sleep controller
.MBC_RESET (~RESETn),
// power gated signals to layer controller
.LRC_SLEEP (),
.LRC_CLKENB (),
.LRC_RESET (),
.LRC_ISOLATE (),
// wake up bus controller
.EXTERNAL_INT (1'b0),
.CLR_EXT_INT (),
.CLR_BUSY (),
// wake up processor
.SLEEP_REQUEST_TO_SLEEP_CTRL()
);
// mbus_wire_ctrl_wresetn_TEST mbus_wire_ctrl_wresetn_0
mbus_wire_ctrl mbus_wire_ctrl_test
(
.RESETn (RESETn),
.DIN (MBUS_EXAMPLE_DOUT),
.CLKIN (MBUS_EXAMPLE_CLKOUT),
.DOUT_FROM_BUS (CTRL_DOUT_FROM_BUS),
.CLKOUT_FROM_BUS (CTRL_CLKOUT_FROM_BUS),
.RELEASE_ISO_FROM_SLEEP_CTRL (1'b0),
.DOUT (CTRL_DOUT),
.CLKOUT (CTRL_CLKOUT),
.EXTERNAL_INT (1'b0)
);
mbus_example mbus_example_0
(
.CIN (CTRL_CLKOUT),
.DIN (CTRL_DOUT),
.COUT (MBUS_EXAMPLE_CLKOUT),
.DOUT (MBUS_EXAMPLE_DOUT)
);
//****************************************************
// CLOCKS
//****************************************************
// MBUS runs at 400KHz
initial begin
MBUS_CLKIN = 1'b0;
end
always begin
#1250 MBUS_CLKIN = ~MBUS_CLKIN;
end
//****************************************************
// RESET
//****************************************************
initial begin
RESETn = 1'b0;
`RESET_TIME;
@(negedge MBUS_CLKIN);
#1;
RESETn = 1'b1;
end
//****************************************************
// RUNAWAY
//****************************************************
initial begin
#;
$display("Runaway Timer");
failure;
end
//****************************************************
// EVERYTHING ELSE
//****************************************************
initial begin
TX_REQ = 1'b0;
TX_ADDR = 32'h00000000;
TX_DATA = 32'h00000000;
RX_ACK = 1'b0;
//****************************************************
// Start Testing
//****************************************************
@(posedge RESETn);
$display("");
$display("***********************************************");
$display("***********************************************");
$display("***************Simulation Start****************");
$display("***********************************************");
$display("***********************************************");
$display("");
check_reset;
enumerate;
#;
load_rf;
#;
start_timer;
#;
target_sleep_long;
#;
success;
end
`include "mbus_example_task.v"
endmodule // mbus_example_test
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// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [14 - 1 : 0] a;
input [14 - 1 : 0] b;
output [14 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [14 - 1 : 0] a_reg;
wire [14 - 1 : 0] b_reg;
// wires for each small adder
wire [4 - 1 : 0] a0_cb;
wire [4 - 1 : 0] b0_cb;
wire [8 - 1 : 4] a1_cb;
wire [8 - 1 : 4] b1_cb;
wire [12 - 1 : 8] a2_cb;
wire [12 - 1 : 8] b2_cb;
wire [14 - 1 : 12] a3_cb;
wire [14 - 1 : 12] b3_cb;
// registers for input register array
reg [4 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [2 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [2 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
// wires for each full adder sum
wire [14 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
// registers for output register array
reg [4 - 1 : 0] s0_ca_rego0[2 - 0 : 0];
reg [4 - 1 : 0] s1_ca_rego1[2 - 1 : 0];
reg [4 - 1 : 0] s2_ca_rego2[2 - 2 : 0];
// wire for the temporary output
wire [14 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[4 - 1 : 0];
assign b0_cb = b_reg[4 - 1 : 0];
assign a1_cb = a_reg[8 - 1 : 4];
assign b1_cb = b_reg[8 - 1 : 4];
assign a2_cb = a_reg[12 - 1 : 8];
assign b2_cb = b_reg[12 - 1 : 8];
assign a3_cb = a_reg[14 - 1 : 12];
assign b3_cb = b_reg[14 - 1 : 12];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[3:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[7:4] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[11:8] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg ),
.fas ( fas[13 :12] ),
.facout ( faccout3_co3 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[4-1 : 0];
s1_ca_rego1 [0] <= fas[8-1 : 4];
s2_ca_rego2 [0] <= fas[12-1 : 8];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[4-1 : 0] = s0_ca_rego0[2];
assign s_tmp[8-1 : 4] = s1_ca_rego1[1];
assign s_tmp[12-1 : 8] = s2_ca_rego2[0];
assign s_tmp[14 - 1 : 12] = fas[13 :12];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
#(parameter
N = 2
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_14ns_14ns_14_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_axis_tx
*/
module test_eth_axis_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_eth_axis_tx_64.lxt");
$dumpvars(0, test_eth_axis_tx_64);
end
eth_axis_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; double res; long long n, m, k, i, j, x = 1, y, t, a[1000001], b[1000001]; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> t; if (t == 1) { cin >> k >> m; a[k] += m; y += k * m; printf( %.10f , (double)y / x); cout << endl; } if (t == 2) { cin >> k; y += k; x++; b[x] = k; printf( %.10f , (double)y / x); cout << endl; } if (t == 3) { a[x - 1] += a[x]; y -= a[x] + b[x]; a[x] = 0; x--; printf( %.10f , (double)y / x); cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int n,i,j,k,a[5050],x[5050],y[5050]; long long scp(int i, int j, int k) { long long xa=x[i]-x[j]; long long ya=y[i]-y[j]; long long xb=x[k]-x[j]; long long yb=y[k]-y[j]; return xa*xb+ya*yb; } int main() { scanf( %d ,&n); for (i=0; i<n; i++) scanf( %d%d ,&x[i],&y[i]); a[0]=0; a[1]=1; for (i=2; i<n; i++) { for (j=i; j>=0; --j) { if (j>=2 && scp(a[j-2],a[j-1],i)<=0) continue; if (j>=1 && j<i && scp(a[j-1],i,a[j])<=0) continue; if (j+1<i && scp(i,a[j],a[j+1])<=0) continue; for (k=i; k>j; --k) a[k]=a[k-1]; a[j]=i; break; } if (j<0) { puts( -1 ); return 0; } } for (i=0; i<n; i++) printf( %d ,a[i]+1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, l, m, n, ok = 0; char s1[110], s2[110], ans[110]; scanf( %s , s1); scanf( %s , s2); l = strlen(s1); for (i = 0; i < l; i++) { if (s1[i] > s2[i]) { ans[i] = s2[i]; } else if (s1[i] < s2[i]) { ok = 1; break; } else ans[i] = s1[i]; } ans[l] = 0 ; if (ok) printf( -1 n ); else puts(ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O221A_FUNCTIONAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_TB_V
`define SKY130_FD_SC_HS__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_TB_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int main() { ios::sync_with_stdio(false); int n, m; cin >> n >> m; int a[n + 1]; int ev = 2, od = 1; int tev = 0, tod = 0; int tot = 0; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; if (a[i] % 2 == 0) tev++; else tod++; } for (int i = 0; i < n; i++) { if (mp[a[i]] > 1) { if (a[i] % 2) { if (tod > tev) { while (mp[ev] != 0) ev += 2; if (ev > m) return cout << -1, 0; mp[ev] = 1; mp[a[i]]--; a[i] = ev; tev++; tod--; tot++; } else { while (mp[od] != 0) od += 2; if (od > m) return cout << -1, 0; mp[od] = 1; mp[a[i]]--; a[i] = od; tot++; } } else { if (tod < tev) { while (mp[od] != 0) od += 2; if (od > m) return cout << -1, 0; mp[od] = 1; mp[a[i]]--; a[i] = od; tev--; tod++; tot++; } else { while (mp[ev] != 0) ev += 2; if (ev > m) return cout << -1, 0; mp[ev] = 1; mp[a[i]]--; a[i] = ev; tot++; } } } } for (int i = 0; i < n; i++) { if (a[i] % 2) { if (tev < tod) { tot++; while (mp[ev] != 0) ev += 2; if (ev > m) return cout << -1, 0; mp[ev] = 1; a[i] = ev; tod--; tev++; } } else { if (tev > tod) { tot++; while (mp[od] != 0) od += 2; if (od > m) return cout << -1, 0; mp[od] = 1; a[i] = od; tod++; tev--; } } } cout << tot << endl; for (int i = 0; i < n; i++) cout << a[i] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > grafo[212345]; int marc[212345], dp[212345], ans[212345], ansmin = 1e9; void dfs(int x) { marc[x] = 1; for (int i = 0; i < grafo[x].size(); i++) { int viz = grafo[x][i].first; int type = grafo[x][i].second; if (marc[viz]) continue; dfs(viz); dp[x] += dp[viz]; if (type) dp[x]++; } } void dfs2(int x) { marc[x] = 0; ans[x] = dp[x]; ansmin = min(ansmin, ans[x]); for (int i = 0; i < grafo[x].size(); i++) { int viz = grafo[x][i].first; int type = grafo[x][i].second; if (!marc[viz]) continue; int dpx = dp[x]; int dpv = dp[viz]; dp[x] -= dp[viz]; if (type) dp[x]--; dp[viz] += dp[x]; if (!type) dp[viz]++; dfs2(viz); dp[x] = dpx; dp[viz] = dpv; } } int n; int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); grafo[u].push_back(make_pair(v, 0)); grafo[v].push_back(make_pair(u, 1)); } dfs(1); dfs2(1); printf( %d n , ansmin); for (int i = 1; i <= n; i++) { if (ansmin == ans[i]) printf( %d , i); } printf( n ); }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; int a[MAXN], b[MAXN], pos[MAXN]; map<int, int> zoom; bool vis[MAXN]; int main() { ios::sync_with_stdio(false); int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } sort(b + 1, b + 1 + n); for (int i = 1; i <= n; i++) { zoom[b[i]] = i; b[i] = i; } for (int i = 1; i <= n; i++) { a[i] = zoom[a[i]]; pos[a[i]] = i; } vector<vector<int>> res; for (int i = 1; i <= n; i++) { if (!vis[pos[i]]) { vector<int> cur; for (int j = pos[i]; !vis[j]; j = pos[j]) { cur.push_back(j); vis[j] = true; } res.push_back(cur); } } cout << res.size() << n ; for (auto v : res) { cout << v.size() << ; for (auto x : v) { cout << x << ; } cout << n ; } }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_sstl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_sstl_pad(/*AUTOARG*/
// Outputs
to_core, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, shift_dr, oe, odt_enable_mask,
mode_ctrl, hiz_n, data_in, clock_dr, cbu, cbd, bsi
);
inout pad;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
output to_core; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input [8:1] cbd; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input [8:1] cbu; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input clock_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input data_in; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input hiz_n; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input mode_ctrl; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input odt_enable_mask; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input oe; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input shift_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input update_dr; // To dram_pad_scan_jtag of dram_pad_scan_jtag.v
input vdd_h; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
input [7:0] vrefcode; // To bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire bscan_oe; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire data_out; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire odt_enable; // From dram_pad_scan_jtag of dram_pad_scan_jtag.v
wire rx_out; // From bw_io_ddr_pad_txrx of bw_io_ddr_pad_txrx.v
// End of automatics
/////////////////////
// TRANSCEIVER module
/////////////////////
/* bw_io_ddr_pad_txrx AUTO_TEMPLATE(
// Outputs
.out (rx_out),
// Inputs
.data (data_out),
.oe (bscan_oe));
*/
bw_io_ddr_pad_txrx bw_io_ddr_pad_txrx(/*AUTOINST*/
// Outputs
.out(rx_out), // Templated
// Inouts
.pad(pad),
// Inputs
.vrefcode(vrefcode[7:0]),
.odt_enable(odt_enable),
.vdd_h(vdd_h),
.cbu(cbu[8:1]),
.cbd(cbd[8:1]),
.data(data_out), // Templated
.oe(bscan_oe)); // Templated
/////////////////////
// SCAN & JTAG module
/////////////////////
/*bw_io_sstl_bscan AUTO_TEMPLATE(
// Outputs
.oe(bscan_oe),
// Inputs
.rcv_in(rx_out),
.drv_oe(oe));
*/
bw_io_sstl_bscan bw_io_sstl_bscan(/*AUTOINST*/
// Outputs
.to_core(to_core),
.data_out(data_out),
.oe(bscan_oe), // Templated
.bso(bso),
.odt_enable(odt_enable),
// Inputs
.bsi(bsi),
.mode_ctrl(mode_ctrl),
.clock_dr(clock_dr),
.shift_dr(shift_dr),
.update_dr(update_dr),
.hiz_l(hiz_n),
.rcv_in(rx_out), // Templated
.data_in(data_in),
.drv_oe(oe), // Templated
.odt_enable_mask(odt_enable_mask));
endmodule
// Local Variables:
// verilog-library-directories:(".")
|
#include <bits/stdc++.h> using namespace std; int ROW[] = {+1, -1, +0, +0}; int COL[] = {+0, +0, +1, -1}; int X[] = {+0, +0, +1, -1, -1, +1, -1, +1}; int Y[] = {-1, +1, +0, +0, +1, +1, -1, -1}; int KX[] = {-2, -2, -1, -1, 1, 1, 2, 2}; int KY[] = {-1, 1, -2, 2, -2, 2, -1, 1}; int basePrime[] = {1009, 1013, 1019, 1021, 1031, 1223, 1229, 1231, 1237, 1249, 1289, 1291, 1297, 1301, 1303, 353, 359, 367, 373, 379, 859, 863, 877, 881, 883, 1931, 1933, 1949, 1951, 1973, 401, 409, 419, 421, 431, 1709, 1721, 1723, 1733, 1741, 3499, 3511, 3517, 3527, 3529, 929, 937, 941, 947, 953}; template <class XXX> XXX GCD(XXX a, XXX b) { return b == 0 ? a : GCD(b, a % b); } template <class XXX> XXX LCM(XXX a, XXX b) { return a * (b / GCD(a, b)); } template <class XXX, class YYY> bool CMP(XXX a, YYY b) { return a > b; } template <class XXX> void fastread(XXX &number) { bool negative = false; register XXX c; number = 0; c = getchar(); if (c == - ) { negative = true; c = getchar(); } for (; (c > 47 && c < 58); c = getchar()) number = number * 10 + c - 48; if (negative) number *= -1; } void OPFILE() {} int main() { OPFILE(); long long int ans[600000]; ans[1] = 0LL; long long int cnt = 1; for (int i = 3; i <= 500000; i += 2) { ans[i] = ans[i - 2] + 8LL * cnt * cnt; cnt++; } int n; cin >> n; while (cin >> n) cout << ans[n] << endl; return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_fmul_32ns_32ns_32_4_max_dsp
#(parameter
ID = 1,
NUM_STAGE = 4,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_fmul_2_max_dsp_32 ANN_ap_fmul_2_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class htpe, class cmp> using heap = priority_queue<htpe, vector<htpe>, cmp>; template <class htpe> using min_heap = heap<htpe, greater<htpe> >; template <class htpe> using max_heap = heap<htpe, less<htpe> >; const int INF = 1791791791; const long long INFLL = 1791791791791791791ll; bool query(int x, int y) { cout << 1 << << x << << y << endl; cout.flush(); string s; cin >> s; return s == TAK ; } bool is_two_answers(int a, int b) { return query(a, b) && query(b, a); } int find_on_segment(int l, int r, int tr) { l--; while (l < r - 1) { int mid = (l + r + tr) >> 1; if (!query(mid, mid + 1)) l = mid; else r = mid; } return r; } int main() { int n, k; cin >> n >> k; int a = find_on_segment(1, n, 0); int b = find_on_segment(a + 1, n, 1); if (a + 1 > n || !is_two_answers(a, b)) b = find_on_segment(1, a - 1, 0); cout << 2 << << a << << b << endl; cout.flush(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007LL; long long large = 2000000000000000000LL; int main() { int n, m; cin >> n >> m; vector<vector<int> > adj(n, vector<int>()); set<pair<int, int> > s; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; if (x > y) swap(x, y); s.insert(pair<int, int>(x, y)); adj[x].push_back(y); adj[y].push_back(x); } int u = -1, v = -1; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (s.find(pair<int, int>(i, j)) == s.end()) { u = i; v = j; break; } } } if (u == -1) { cout << NO << endl; return 0; } cout << YES << endl; vector<vector<int> > adjt(n, vector<int>()); for (int i = 0; i < n; i++) { int f = i; if (f == v) f = u; for (int j = 0; j < (int)adj[i].size(); j++) { int to = adj[i][j]; if (to == v) to = u; adjt[f].push_back(to); } } queue<int> q; q.push(u); vector<int> dis(n, -1); dis[u] = 0; while (!q.empty()) { int u = q.front(); q.pop(); for (int j = 0; j < (int)adjt[u].size(); j++) { int v = adjt[u][j]; if (dis[v] == -1) { dis[v] = dis[u] + 1; q.push(v); } } } vector<pair<int, int> > e; for (int i = 0; i < n; i++) { if (i != v) e.push_back(pair<int, int>(dis[i], i)); } sort(e.begin(), e.end()); vector<int> a(n, -1); for (int i = 0; i < (int)e.size(); i++) a[e[i].second] = n - 2 - i; a[v] = n - 1; for (int i = 0; i < n; i++) printf( %d , a[i] + 1); printf( n ); a[v] = n - 2; for (int i = 0; i < n; i++) printf( %d , a[i] + 1); printf( n ); return 0; }
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ()
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:15:39 06/10/2015
// Design Name: game_text_top_ya
// Module Name: D:/OnGoingProject/Curriculum/ISE/Proj_x/proj_test/test_game_text_top_ya.v
// Project Name: proj_test
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: game_text_top_ya
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_game_text_top_ya;
// Inputs
reg clk;
reg reset;
reg [1:0] btn;
// Outputs
wire hsync;
wire vsync;
wire [2:0] rgb;
// Instantiate the Unit Under Test (UUT)
game_text_top_ya uut (
.clk(clk),
.reset(reset),
.btn(btn),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
btn = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
# 100;
reset = 0;
// Add stimulus here
forever #10 clk=~clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int c1 = 0, c2 = 0, c3 = 0; for (int i = 0; i < n; i++) { int x, y, z; cin >> x >> y >> z; c1 += x, c2 += y, c3 += z; } if (c1 == 0 && c2 == 0 && c3 == 0) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<string, long long> mp; int main() { int n; cin >> n; mp.clear(); for (int i = 1; i <= n; ++i) { string tmp; cin >> tmp; mp[tmp]++; } cout << (mp[ UL ] + mp[ DR ] + mp[ ULDR ] + 1) * (mp[ UR ] + mp[ DL ] + mp[ ULDR ] + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7, mod2 = 998244353; unsigned long long base = 131; const int w = 1e7 + 5; long long m, n; int main() { long long i, j, k, t, qqq; cin >> n; string a, b; cin >> a >> b; int flag = 0; for (i = a.size() - 1; i >= 0; i--) { int x = (b[i] - a ); int y = (int)a[i] + x; if (flag) y++, flag = 0; if (y > (int) z ) y -= 26, flag++; a[i] = (char)y; } if (flag) a.insert(a.begin(), b ); flag = 0; for (i = 0; i < a.size(); i++) { int x = a[i] - a ; if (flag) x += 26, flag = 0; int y = x % 2; x /= 2; a[i] = x + a ; if (y) flag = 1; } if (a.size() == n) cout << a << endl; else { for (i = 1; i < a.size(); i++) printf( %c , a[i]); cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int inf = 0x3f3f3f3f; const ll INF = 0x3f3f3f3f3f3f3f3fLL; const int MAXN = 1e6 + 5; int arr[MAXN], n; ll fun(ll x) { if (x == 1) return INF; ll sum = 0, y = 0; for (int i = 0; i < n; i++) { y += arr[i]; y %= x; sum += min(y, x - y); } return sum; } int main() { std::ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); ll sum = 0, ans = INF; cin >> n; for (int i = 0; i < n; i++) cin >> arr[i], sum += arr[i]; if (sum < 2) { cout << -1 << n ; return 0; } for (ll i = 2; i * i <= sum; i++) { if (sum % i == 0) ans = min(ans, fun(i)); while (sum % i == 0) sum /= i; } ans = min(ans, fun(sum)); cout << ans << n ; return 0; }
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//The following module is used to re-write transmit packets from the host.
//This module provides a packet-based ram interface for manipulating packets.
//By default, this module uses the built-in 8 to 16 bit converter engine.
module vita_tx_engine_glue
#(
//the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
//buffer size for ram interface engine
parameter BUF_SIZE = 10,
//base address for built-in settings registers used in this module
parameter MAIN_SETTINGS_BASE = 0,
//the number of 32bit lines between start of buffer and vita header
//the metadata before the header should be preserved by the engine
parameter HEADER_OFFSET = 0
)
(
//control signals
input clock, input reset, input clear,
//main settings bus for built-in modules
input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
//user settings bus, controlled through user setting regs API
input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
//ram interface for engine
output access_we,
output access_stb,
input access_ok,
output access_done,
output access_skip_read,
output [BUF_SIZE-1:0] access_adr,
input [BUF_SIZE-1:0] access_len,
output [35:0] access_dat_o,
input [35:0] access_dat_i,
//debug output (optional)
output [31:0] debug
);
generate
if (DSPNO==0) begin
`ifndef TX_ENG0_MODULE
dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
(.clk(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`else
`TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom
(.clock(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`endif
end
else begin
`ifndef TX_ENG1_MODULE
dspengine_8to16 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) dspengine_8to16
(.clk(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`else
`TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom
(.clock(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`endif
end
endgenerate
endmodule //vita_tx_engine_glue
|
module testbench
();
`include "c_functions.v"
`include "c_constants.v"
parameter num_credits = 8;
parameter reset_type = `RESET_TYPE_ASYNC;
parameter Tclk = 2;
parameter runtime = 1000;
parameter rate_in = 50;
parameter rate_out = 50;
parameter initial_seed = 0;
reg clk;
reg reset;
wire debit;
wire credit;
wire free;
wire free_early;
wire error;
c_credit_tracker
#(.num_credits(num_credits),
.reset_type(reset_type))
dut
(.clk(clk),
.reset(reset),
.debit(debit),
.credit(credit),
.free(free),
.free_early(free_early),
.error(error));
always
begin
clk <= 1'b1;
#(Tclk/2);
clk <= 1'b0;
#(Tclk/2);
end
reg [0:clogb(num_credits+1)-1] cred_count;
wire [0:clogb(num_credits+1)-1] cred_count_next;
assign cred_count_next = reset ? num_credits : cred_count + credit - debit;
reg flag_in, flag_out;
assign credit = !reset && flag_out && (cred_count < num_credits);
assign debit = !reset && flag_in && (cred_count > 0);
integer seed = initial_seed;
always @(posedge clk)
begin
flag_in = !reset && ($dist_uniform(seed, 0, 99) < rate_in);
flag_out = !reset && ($dist_uniform(seed, 0, 99) < rate_out);
cred_count = reset ? num_credits : cred_count_next;
end
initial
begin
reset = 1'b1;
#(3*Tclk);
reset = 1'b0;
#(Tclk);
#(runtime*Tclk);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int mi[n]; for (int i = (0); i < (n); i++) mi[i] = 1e9; int t = 1; int z[1000]; do { t *= 2; vector<int> v; int x = 0; while (x < n) { int f = 0; for (int i = (0); i < (t / 2); i++) { if (x + i < n) v.push_back(x + i); else break; } x += t; } cout << v.size() << n ; ; set<int> temp; for (int i = (0); i < (v.size()); i++) { temp.insert(v[i]); cout << v[i] + 1 << ; } cout << n ; fflush(stdout); for (int i = (0); i < (n); i++) cin >> z[i]; for (int i = (0); i < (n); i++) { if (temp.find(i) == temp.end()) mi[i] = min(mi[i], z[i]); } v.resize(0); x = 0; temp.clear(); while (x < n) { int f = 0; for (int i = (0); i < (t / 2); i++) { if (x + i + t / 2 < n) v.push_back(x + i + t / 2); else break; } x += t; } cout << v.size() << n ; ; for (int i = (0); i < (v.size()); i++) { temp.insert(v[i]); cout << v[i] + 1 << ; } cout << n ; fflush(stdout); for (int i = (0); i < (n); i++) cin >> z[i]; for (int i = (0); i < (n); i++) { if (temp.find(i) == temp.end()) mi[i] = min(mi[i], z[i]); } } while (t < n); cout << -1 n ; fflush(stdout); for (int i = (0); i < (n); i++) cout << mi[i] << ; cout << n ; fflush(stdout); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSBP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_6_V
`define SKY130_FD_SC_HDLL__OR2_6_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_6 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_6 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_6_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Video_Memory.v when simulating
// the core, Video_Memory. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Video_Memory(
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [11 : 0] a;
input [15 : 0] d;
input [11 : 0] dpra;
input clk;
input we;
output [15 : 0] spo;
output [15 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(12),
.C_DEFAULT_DATA("0"),
.C_DEPTH(2400),
.C_FAMILY("spartan6"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("Video_Memory.mif"),
.C_MEM_TYPE(2),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(16)
)
inst (
.A(a),
.D(d),
.DPRA(dpra),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPO(dpo),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; bool checkC(int n) { for (int i = 2; i * i <= n; i++) { if (n % i == 0) return 1; } return 0; } void per(string s, int i, int &num, string &ans) { if (i == s.length()) { if (num != 0 && checkC(num)) { int x = num; int d = 0; while (x != 0) { x /= 10; d++; } if (d > 0) { if (d < ans.length() || ans.length() == 0) ans = to_string(num); } } } else { int k = num; num = num * 10 + (s[i] - 0 ); per(s, i + 1, num, ans); num = k; per(s, i + 1, num, ans); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int test; cin >> test; while (test--) { int k; cin >> k; string s; cin >> s; vector<int> c(10, 0); int ans = -1; for (int i = 0; i < k; i++) { int vl = s[i] - 0 ; if (vl == 1 || vl == 4 || vl == 6 || vl == 8 || vl == 9) { ans = vl; break; } c[vl]++; } if (ans != -1) { cout << 1 n ; cout << ans << n ; } else { if (c[2] >= 2) { cout << 2 n ; cout << 22 n ; } else if (c[3] >= 2) { cout << 2 n ; cout << 33 n ; } else if (c[5] >= 2) { cout << 2 n ; cout << 55 n ; } else if (c[7] >= 2) { cout << 2 n ; cout << 77 n ; } else { string pa = ; int num = 0; per(s, 0, num, pa); cout << pa.length() << n ; cout << pa << n ; } } } }
|
/*
* phase_shift_tb.v: Testbench for phase_shift.v
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
`ifndef WAIT_INTERVAL
`define WAIT_INTERVAL 1000
`endif
module phase_shift_tb ();
reg rst;
reg PWRDWN;
reg clk;
reg signed [31:0] shift_1000;
reg [31:0] clk_period_1000;
reg [6:0] duty_cycle;
wire lock;
wire clk_shifted;
reg shift_fail;
reg duty_cycle_fail;
integer pass_count;
integer fail_count;
/* adjust according to the number of testcases */
localparam total = 17;
phase_shift dut(
.RST(rst),
.PWRDWN(PWRDWN),
.clk(clk),
.shift_1000(shift_1000),
.clk_period_1000(clk_period_1000),
.duty_cycle(duty_cycle),
.lock(lock),
.clk_shifted(clk_shifted));
initial begin
$dumpfile("phase_shift_tb.vcd");
$dumpvars(0, phase_shift_tb);
rst = 0;
PWRDWN = 0;
clk = 0;
clk_period_1000 = 20000;
shift_1000 = 10 * 1000;
duty_cycle = 50;
pass_count = 0;
fail_count = 0;
#10;
if (lock === 1'bx) begin
$display("PASSED: lock should not be set before first reset");
pass_count = pass_count + 1;
end else begin
$display("FAILED: lock should not be set before first reset");
fail_count = fail_count + 1;
end
rst = 1;
#10;
if (clk_shifted === 1'b0 && lock === 1'b0) begin
$display("PASSED: rst");
pass_count = pass_count + 1;
end else begin
$display("FAILED: rst");
fail_count = fail_count + 1;
end
rst = 0;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 10°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 10°");
fail_count = fail_count + 1;
end
shift_1000 = 182 * 1000;
clk_period_1000 = 5000;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 182°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 182°");
fail_count = fail_count + 1;
end
shift_1000 = 181 * 1000;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 181°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 181°");
fail_count = fail_count + 1;
end
shift_1000 = 180 * 1000;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 180°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 180°");
fail_count = fail_count + 1;
end
shift_1000 = 360 * 1000;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 360°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 360°");
fail_count = fail_count + 1;
end
shift_1000 = -10 * 1000;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = -10°");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = -10°");
fail_count = fail_count + 1;
end
clk_period_1000 = 1000;
shift_1000 = 0;
duty_cycle = 50;
#`WAIT_INTERVAL;
shift_fail = 0;
#`WAIT_INTERVAL;
if (!shift_fail && lock) begin
$display("PASSED: shift = 0°, clk period = 1");
pass_count = pass_count + 1;
end else begin
$display("FAILED: shift = 0°, clk period = 1");
fail_count = fail_count + 1;
end
clk_period_1000 = 5000;
#40;
shift_1000 = 0;
duty_cycle_fail = 0;
duty_cycle = 1;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 1%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 1%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 10;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 10%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 10%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 49;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 49%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 49%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 50;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 50%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 50%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 51;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 51%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 51%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 90;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 90%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 90%");
fail_count = fail_count + 1;
end
duty_cycle_fail = 0;
duty_cycle = 99;
#`WAIT_INTERVAL;
if (!duty_cycle_fail && lock) begin
$display("PASSED: duty cycle = 99%");
pass_count = pass_count + 1;
end else begin
$display("FAILED: duty cycle = 99%");
fail_count = fail_count + 1;
end
PWRDWN = 1'b1;
#((clk_period_1000 / 2000.0) + 1);
if (clk_shifted === 1'bx && lock === 1'bx) begin
$display("PASSED: PWRDWN");
pass_count = pass_count + 1;
end else begin
$display("FAILED: PWRDWN");
fail_count = fail_count + 1;
end
if ((pass_count + fail_count) == total) begin
$display("PASSED: number of test cases");
pass_count = pass_count + 1;
end else begin
$display("FAILED: number of test cases");
fail_count = fail_count + 1;
end
$display("%0d/%0d PASSED", pass_count, (total + 1));
$finish;
end
always #((clk_period_1000 / 1000.0) / 2.0) clk <= ~clk;
/* check if the phase shift failed */
always @(posedge clk or posedge rst) begin
if (rst) begin
shift_fail <= 0;
end else begin
if (shift_1000 >= 0) begin
#(((shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0)) - 0.1);
if (clk_shifted != 0) begin
shift_fail <= 1;
end
end else begin
#(((clk_period_1000 / 1000.0) + ((shift_1000 / 1000.0) * ((clk_period_1000 / 1000.0) / 360.0))) - 0.1);
if (clk_shifted != 0) begin
shift_fail <= 1;
end
end
#0.2;
if (clk_shifted != 1) begin
shift_fail <= 1;
end
end
end
/* check if duty cycle is correct */
always @(posedge clk_shifted or posedge rst) begin
if (rst) begin
duty_cycle_fail <= 0;
end else begin
#(((clk_period_1000 / 1000.0) * (duty_cycle / 100.0)) - 0.1);
if (clk_shifted != 1) begin
duty_cycle_fail <= 1;
end
#0.2;
if (clk != 0) begin
duty_cycle_fail <= 1;
end
end
end
endmodule
|
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____20.000______0.000______50.0_____1200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary___________50.00____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input clk,
// Clock out ports
output clk_20MHz
);
// Input buffering
//------------------------------------
assign clkin1 = clk;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.500),
.CLKFX_DIVIDE (5),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (clk_20MHz),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> inline int read() { static char ch; while (ch = getchar(), ch < 0 || ch > 9 ) ; int res = ch - 48; while (ch = getchar(), ch >= 0 && ch <= 9 ) res = res * 10 + ch - 48; return res; } inline unsigned int Rand() { static unsigned int x = 998666131; return x += x << 2 | 1; } const int N = 5001, M = 1e5 + 5, T = 2e6; int n, m, Q, ans[M]; bool vis[M]; struct QueryT { int op, x, y, dir, len, lab; inline void Reset1(const int &_op, const int &_dir, const int &_x, const int &_y, const int &_len) { op = _op; dir = _dir; x = _x; y = _y; len = _len; } inline void Reset2(const int &_op, const int &_dir, const int &_x, const int &_y, const int &_lab) { op = _op; dir = _dir; x = _x; y = _y; lab = _lab; len = x + y; } inline bool operator<=(const QueryT &rhs) { if (x != rhs.x) return x < rhs.x; return op <= rhs.op; } } qry[M * 4], tmp[M * 4]; struct node { node *lc, *rc; int val, sze; unsigned int pri; inline void Update() { sze = (lc ? lc->sze : 0) + (rc ? rc->sze : 0) + 1; } } used[T], *pool = used, *unused[T], **top = unused; node *rt[5][N]; inline node *new_node() { node *res; if (top != unused) res = *--top; else res = pool++; res->lc = res->rc = NULL; return res; } inline void del_node(node *&u) { if (!u) return; del_node(u->lc); del_node(u->rc); *top++ = u; u = NULL; } inline void Zig(node *&u) { node *v = u->lc; u->lc = v->rc; v->rc = u; v->sze = u->sze; u->Update(); u = v; } inline void Zag(node *&u) { node *v = u->rc; u->rc = v->lc; v->lc = u; v->sze = u->sze; u->Update(); u = v; } inline void Insert(node *&u, const int &val) { if (!u) { u = new_node(); u->val = val; u->sze = 1; u->pri = Rand(); return; } ++u->sze; if (val <= u->val) { Insert(u->lc, val); if (u->lc->pri < u->pri) Zig(u); } else { Insert(u->rc, val); if (u->rc->pri < u->pri) Zag(u); } } inline int moreQuery(node *u, const int &val) { if (!u) return 0; if (u->val < val) return moreQuery(u->rc, val); return (u->rc ? u->rc->sze + 1 : 1) + moreQuery(u->lc, val); } inline void add(node **R, int x, const int &val) { for (; x <= n; x += x & -x) Insert(R[x], val); } inline int Query(node **R, int x, const int &val) { int res = 0; for (; x > 0; x -= x & -x) res += moreQuery(R[x], val); return res; } inline void Clear(node **R, int x) { for (; x <= n; x += x & -x) del_node(R[x]); } inline void cdqSolve(const int &l, const int &r) { if (l == r) return; int mid = l + r >> 1; cdqSolve(l, mid); cdqSolve(mid + 1, r); int ql = l, qr = mid + 1; for (int i = (l); i <= (r); ++i) { if (qr > r || (ql <= mid && qry[ql] <= qry[qr])) { tmp[i] = qry[ql++]; if (tmp[i].op == 1) add(rt[tmp[i].dir], tmp[i].y, tmp[i].len); } else { tmp[i] = qry[qr++]; if (tmp[i].op == 2) ans[tmp[i].lab] += Query(rt[tmp[i].dir], tmp[i].y, tmp[i].len); } } for (int i = (l); i <= (r); ++i) { qry[i] = tmp[i]; if (qry[i].op == 1) Clear(rt[qry[i].dir], qry[i].y); } } int main() { n = read(); Q = read(); int op, x, y, len, dir; for (int i = (1); i <= (Q); ++i) { op = read(); if (op == 1) { dir = read(), x = read(), y = read(), len = read(); if (dir == 2) y = n - y + 1; if (dir == 3) x = n - x + 1; if (dir == 4) x = n - x + 1, y = n - y + 1; len += x + y; qry[++m].Reset1(op, dir, x, y, len); } else { x = read(), y = read(); qry[++m].Reset2(op, 1, x, y, i); qry[++m].Reset2(op, 2, x, n - y + 1, i); qry[++m].Reset2(op, 3, n - x + 1, y, i); qry[++m].Reset2(op, 4, n - x + 1, n - y + 1, i); vis[i] = true; } } cdqSolve(1, m); for (int i = (1); i <= (Q); ++i) if (vis[i]) printf( %d n , ans[i]); return 0; }
|
// file: Clock48MHZ_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock48MHZ_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [3:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (10.000*1*31.750*1000/15.250);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (10.000*1*8*1000/15.250);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (10.000*1*15*1000/15.250);
time prev_rise3;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", /period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", /period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", /period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock48MHZ_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, b, x, y, cnt; void RUL(int); void DLU(int); void LDR(int); void URD(int); void disp_res(int x, int y) { printf( %d %d n , x, y); exit(0); } void RUL(int n) { if (cnt == b) { disp_res(x, y); }; if (n <= 0) return; URD(n - 1); x += 1; cnt++; RUL(n - 1); y += 1; cnt++; RUL(n - 1); x -= 1; cnt++; DLU(n - 1); } void DLU(int n) { if (cnt == b) { disp_res(x, y); }; if (n <= 0) return; LDR(n - 1); y -= 1; cnt++; DLU(n - 1); x -= 1; cnt++; DLU(n - 1); y += 1; cnt++; RUL(n - 1); } void LDR(int n) { if (cnt == b) { disp_res(x, y); }; if (n <= 0) return; DLU(n - 1); x -= 1; cnt++; LDR(n - 1); y -= 1; cnt++; LDR(n - 1); x += 1; cnt++; URD(n - 1); } void URD(int n) { if (cnt == b) { disp_res(x, y); }; if (n <= 0) return; RUL(n - 1); y += 1; cnt++; URD(n - 1); x += 1; cnt++; URD(n - 1); y -= 1; cnt++; LDR(n - 1); } int main() { cnt = 0; x = 0, y = 0; scanf( %d %d , &a, &b); URD(a); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_PP_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_sync_cell.v
//
// *Module Description:
// Generic synchronizer for the openGFX430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module ogfx_sync_cell (
// OUTPUTs
data_out, // Synchronized data output
// INPUTs
clk, // Receiving clock
data_in, // Asynchronous data input
rst // Receiving reset (active high)
);
// OUTPUTs
//=========
output data_out; // Synchronized data output
// INPUTs
//=========
input clk; // Receiving clock
input data_in; // Asynchronous data input
input rst; // Receiving reset (active high)
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst)
if (rst) data_sync <= 2'b00;
else data_sync <= {data_sync[0], data_in};
assign data_out = data_sync[1];
endmodule // ogfx_sync_cell
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 9, N = 1e3 + 9; const int qwer[] = {-1, 0, 1, 0}, asdf[] = {0, 1, 0, -1}; int n, m, a[N][N], arr[MAX], sizee[MAX], number, c[N][N], vv, cnt; long long k; struct node { int id, x, y; } b[MAX]; int root(int x) { return x == arr[x] ? x : arr[x] = root(arr[x]); } void merge(int x, int y) { int zxcv = root(x), fy = root(y); if (sizee[zxcv] < sizee[fy]) swap(zxcv, fy); if (zxcv == fy) return; arr[fy] = zxcv; sizee[zxcv] += sizee[fy]; } bool cmp(const node& x, const node& y) { return x.id > y.id; } void dfs(int x, int y) { if (c[x][y]) return; if (number) c[x][y] = vv, number--; else return; for (int i = 0; i < 4; i++) { int nx = x + qwer[i]; int ny = y + asdf[i]; if (nx < 1 || nx > n || ny < 1 || ny > m) continue; if (a[nx][ny] < vv) continue; dfs(nx, ny); } } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> k; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j], cnt++, b[cnt].x = i, b[cnt].y = j, b[cnt].id = a[i][j]; sort(b + 1, b + cnt + 1, cmp); for (int i = 1; i <= cnt; i++) arr[i] = i, sizee[i] = 1; int i; for (i = 1; i <= cnt; i++) { int dd = (b[i].x - 1) * m + b[i].y; for (int j = 0; j < 4; j++) { int nx = b[i].x + qwer[j]; int ny = b[i].y + asdf[j]; if (nx < 1 || nx > n || ny < 1 || ny > m || a[nx][ny] < b[i].id) continue; merge(dd, (nx - 1) * m + ny); } if (k % b[i].id == 0 && sizee[root(dd)] >= k / b[i].id) break; } if (i > cnt) return cout << NO , 0; vv = b[i].id, number = k / b[i].id, dfs(b[i].x, b[i].y); cout << YES n ; for (int i = 1; i <= n; i++, cout << n ) for (int j = 1; j <= m; j++) cout << c[i][j] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(); int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { solve(); cout << n ; } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; } long long num(long long x, long long n, long long m) { long long res = 0; --x; for (long long i = 1; i <= n; i++) res += min(x / i, m); return res; } void solve() { long long n, m; cin >> n >> m; long long k; cin >> k; long long l = 1; long long r = n * m + 1; while (l < r) { long long x = (l + r) >> 1; if (num(x, n, m) < k) l = x + 1; else r = x; } cout << l - 1; return; }
|
#include <bits/stdc++.h> const double PI = 3.141592653589793238460; long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int max(long long int a, long long int b) { if (a > b) return a; else return b; } long long int min(long long int a, long long int b) { if (a < b) return a; else return b; } long long int power(long long int a, long long int b) { long long int i, p = 1; for (i = 0; i < b; i++) { p *= a; } return p; } using namespace std; int main() { ios::sync_with_stdio(false); long long int n, i; cin >> n; vector<pair<long long int, long long int> > p; p.push_back({0, 0}); p.push_back({0, 1}); p.push_back({1, 1}); p.push_back({1, 0}); for (i = 0; i < n; i++) { p.push_back({i + 2, i + 1}); p.push_back({i + 1, i + 2}); p.push_back({i + 2, i + 2}); } cout << p.size() << n ; for (i = 0; i < p.size(); i++) { cout << p[i].first << << p[i].second << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct EDGE { int adj, next; } edge[810000]; int n, m, q, top, gh[510000]; int size[510000], dfn[510000], low[510000], cnt, ind, stop, instack[510000], stck[510000], belong[510000]; void addedge(int x, int y) { edge[++top].adj = y; edge[top].next = gh[x]; gh[x] = top; } void tarjan(int x, int pre) { dfn[x] = low[x] = ++ind; instack[x] = 1; stck[++stop] = x; for (int p = gh[x]; p; p = edge[p].next) { if (edge[p].adj == pre) continue; if (!dfn[edge[p].adj]) { tarjan(edge[p].adj, x); low[x] = min(low[x], low[edge[p].adj]); } else if (instack[edge[p].adj]) { low[x] = min(low[x], dfn[edge[p].adj]); } } if (dfn[x] == low[x]) { ++cnt; int tmp = 0; size[cnt] = 0; while (tmp != x) { size[cnt]++; tmp = stck[stop--]; belong[tmp] = cnt; instack[tmp] = 0; } } } int far[510000]; long long mul[510000]; void init() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) gh[i] = 0; top = cnt = ind = stop = 0; for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); addedge(x, y); addedge(y, x); } for (int i = 1; i <= n; i++) dfn[i] = 0; for (int i = 1; i <= n; i++) if (dfn[i] == 0) tarjan(i, 0); } int v[510000]; void prepare() { for (int i = 1; i <= n; i++) v[i] = 0; int tail = 1; v[belong[1]]++; for (int i = 1; i <= n; i++) { while (tail < n && (v[belong[tail + 1]] + 1 < size[belong[tail + 1]] || size[belong[tail + 1]] == 1)) { v[belong[++tail]]++; } far[i] = tail; mul[i] = tail - i + 1; mul[i] += mul[i - 1]; v[belong[i]]--; } } int main() { init(); prepare(); scanf( %d , &q); for (int i = 1; i <= q; i++) { int l, r; scanf( %d%d , &l, &r); int left = l; int right = r; if (far[l] > r) left = left - 1; else while (left < right) { int mid = (left + right) / 2 + 1; if (far[mid] <= r) left = mid; else right = mid - 1; } long long ans = mul[left] - mul[l - 1]; ans += (long long)(r - left + 1) * (r - left) / 2; printf( %I64d n , ans); } }
|
`timescale 1ns / 1ns
module ph_fifo (
input h_rst_b,
input h_rd,
input h_selectData,
input h_phi2,
input [7:0] p_data,
input p_selectData,
input p_phi2,
input p_rdnw,
output [7:0] h_data,
output h_data_available,
output p_full
);
wire fifo_rst;
wire fifo_wr_clk;
wire fifo_rd_clk;
wire [7:0] fifo_din;
wire fifo_wr_en;
wire fifo_rd_en;
wire [7:0] fifo_dout;
wire fifo_full;
wire fifo_empty;
`ifdef SPARTAN3
ph_fifo_core_spartan3 ph_fifo_core (
`else
ph_fifo_core_spartan6 ph_fifo_core (
`endif
.rst(fifo_rst), // input rst
.wr_clk(fifo_wr_clk), // input wr_clk
.rd_clk(fifo_rd_clk), // input rd_clk
.din(fifo_din), // input [7 : 0] din
.wr_en(fifo_wr_en), // input wr_en
.rd_en(fifo_rd_en), // input rd_en
.dout(fifo_dout), // output [7 : 0] dout
.full(fifo_full), // output full
.empty(fifo_empty) // output empty
);
assign fifo_rst = ~h_rst_b;
// Parasite
assign fifo_din = p_data;
assign p_full = fifo_full;
assign fifo_wr_clk = p_phi2;
assign fifo_wr_en = p_selectData & ~p_rdnw;
// Host
assign fifo_rd_clk = ~h_phi2;
assign fifo_rd_en = h_selectData & h_rd;
assign h_data = fifo_empty ? 8'hAA : fifo_dout;
assign h_data_available = ~fifo_empty;
endmodule // ph_fifo
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM4096x64_2RW.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAM4096x64_2RW (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input [7:0] byteena_a;
input [7:0] byteena_b;
input clock;
input [63:0] data_a;
input [63:0] data_b;
input wren_a;
input wren_b;
output [63:0] q_a;
output [63:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena_a;
tri1 [7:0] byteena_b;
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "262144"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "8"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 8 0 INPUT VCC "byteena_a[7..0]"
// Retrieval info: USED_PORT: byteena_b 0 0 8 0 INPUT VCC "byteena_b[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 64 0 INPUT NODEFVAL "data_a[63..0]"
// Retrieval info: USED_PORT: data_b 0 0 64 0 INPUT NODEFVAL "data_b[63..0]"
// Retrieval info: USED_PORT: q_a 0 0 64 0 OUTPUT NODEFVAL "q_a[63..0]"
// Retrieval info: USED_PORT: q_b 0 0 64 0 OUTPUT NODEFVAL "q_b[63..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @byteena_a 0 0 8 0 byteena_a 0 0 8 0
// Retrieval info: CONNECT: @byteena_b 0 0 8 0 byteena_b 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 64 0 data_a 0 0 64 0
// Retrieval info: CONNECT: @data_b 0 0 64 0 data_b 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: q_b 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM4096x64_2RW_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hdll__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool chmax(T &a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> inline bool chmin(T &a, T b) { if (a > b) { a = b; return true; } return false; } const long long INF = 1e18; long long N; long long a[1050]; vector<string> ans, trueans; vector<vector<int>> Prev, Next; void f(int item) { int idx1 = 0; int idx2 = 1; Next.clear(); for (auto v : Prev) { if (v.size() <= 1) continue; idx1 = v[0]; idx2 = v[1]; } ans[idx1][item] = 1 ; ans[idx2][item] = 0 ; long long one = a[item] - 1; for (int i = 0; i <= N; i++) { if (i == idx2 or i == idx1) continue; if (one) { one--; ans[i][item] = 1 ; } else { ans[i][item] = 0 ; } } for (auto v : Prev) { vector<int> u[2]; for (auto tmp : v) { if (ans[tmp][item] == 0 ) u[0].push_back(tmp); else u[1].push_back(tmp); } for (int i = 0; i < 2; i++) { if (u[i].size()) Next.push_back(u[i]); } } swap(Prev, Next); } int main() { cin >> N; for (int i = 0; i < N; i++) cin >> a[i]; ans.resize(N + 1, string(N, 0 )); Prev.push_back({}); for (int i = 0; i <= N; i++) { Prev[0].push_back(i); } for (int i = 0; i < N; i++) f(i); for (auto v : Prev) { assert(v.size() == 1); } for (auto s : ans) { if (s != string(N, 0 )) trueans.push_back(s); } cout << trueans.size() << n ; for (auto s : trueans) { cout << s << n ; } return 0; }
|
#include<bits/stdc++.h> #define fast ios::sync_with_stdio(false); cin.tie(0); cout.tie(0) #define arin(x,n) for(int i=0;i<n;i++)cin>>x[i] #define debug(x,n) for(int i=0;i<n;i++)cout<<x[i]<< #define pb push_back #define all(c) begin(c), end(c) #define isAll(c) (int)(c).size() typedef long long int ll; using namespace std; int solve(vector <pair<int, int>> &arr) { int num = isAll(arr); vector <int> lc(num); vector <int> rc(num); for (int i = 0; i < num; i++) lc[i] = arr[i].first, rc[i] = arr[i].second; sort(all(lc)), sort(all(rc)); int result = 1e9 + 7; for (auto [l, r] : arr) { int result_l = distance(begin(rc), lower_bound(all(rc), l)), result_r = distance(upper_bound(all(lc), r), end(lc)); result = min(result, result_l + result_r); } return result; } int main() { fast; ll T=1; cin>>T; while(T--) { int num; cin >> num; vector <pair<int, int>> arr(num); for(auto &[x, y] : arr) cin >> x >> y; cout << solve(arr) << endl; } return 0; }
|
module control_leer(clk,load_e,efect0,add_1,add_2,reset_1,reset_2,top_1,top_2,load_crt,done_crt,new_col,reset_new,load_led,rst,run_efect);
input clk;
input load_e;
input efect0;
input top_1;
input top_2;
input done_crt;
input new_col;
input run_efect;
output reg rst;
output reg add_1;
output reg add_2;
output reg reset_1;
output reg reset_2;
output reg load_crt;
output reg reset_new;
output reg load_led;
reg [6:0] current_state;
reg [6:0] next_state;
parameter start=7'b0000000, state_1=7'b0000001, state_2=7'b0000010, state_3=7'b0000011, state_4=7'b0000100, state_5=7'b0000101, state_6=7'b0000110,state_3f=7'b0000111;
always @(top_1 or run_efect or load_e or efect0 or top_2 or done_crt or new_col or current_state)begin
case(current_state)
start: begin //encendido esperando load
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b1;
reset_2= 1'b1;
load_crt= 1'b0;
reset_new= 1'b1;
load_led= 1'b0;
rst=1'b1;
if ((load_e==1'b1 || efect0==1'b1) && run_efect==1'b1) next_state<=state_1;
else next_state<=start;
end
state_1: begin //Inicio de imprecion 256 col
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b0;
load_crt= 1'b1;
reset_new= 1'b1;
load_led= 1'b0;
rst=1'b0;
next_state<=state_2;
end
state_2: begin //Esperando new colum
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b0;
load_crt= 1'b0;
reset_new= 1'b0;
load_led= 1'b0;
rst=1'b0;
if(efect0==1'b1) begin
if (new_col == 1'b1) next_state<=state_3f;
else if (done_crt==1'b1)next_state<=state_1;
else next_state<=state_2;
end else begin
if (new_col == 1'b1) next_state<=state_3;
else if (done_crt==1'b1)next_state<=state_4;
else next_state<=state_2;
end
end
state_3: begin //carga leds para corrimiento
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b0;
load_crt= 1'b0;
reset_new= 1'b1;
load_led= 1'b1;
rst=1'b0;
if (done_crt==1'b1)next_state<=state_4;
else next_state<=state_2;
end
//Efecto fijo>XXXXXX
state_3f: begin //EFECTO FIJO
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b1;
reset_2= 1'b1;
load_crt= 1'b0;
reset_new= 1'b1;
load_led= 1'b1;
rst=1'b0;
if (done_crt==1'b1)next_state<=state_4;
else next_state<=state_2;
end
state_4: begin // Aumento de vueltas
add_1= 1'b1;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b0;
load_crt= 1'b0;
reset_new= 1'b0;
load_led= 1'b0;
rst=1'b0;
if (top_1==1'b1)next_state<=state_5;
else next_state<=state_1;
end
state_5: begin // Aumento de corrimiento
add_1= 1'b0 ;
add_2= 1'b1;
reset_1= 1'b1; // temp<=leds
reset_2= 1'b0;//chan=1; if(chan)temp<=~temp;
load_crt= 1'b0;
reset_new= 1'b0; //ledsOut<=temp;
load_led= 1'b0;
rst=1'b0;
next_state<=state_1;
end
state_6: begin // reinicio de corrimiento
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b1;
load_crt= 1'b0;
reset_new= 1'b0;
load_led= 1'b0;
rst=1'b0;
next_state<=state_1;
end
default:
begin
add_1= 1'b0 ;
add_2= 1'b0;
reset_1= 1'b0;
reset_2= 1'b0;
load_crt= 1'b0;
reset_new= 1'b0;
load_led= 1'b0;
rst=1'b0;
next_state<=start;
end
endcase
end
always @(negedge clk) begin
current_state<=next_state;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; int T, n, m; string s; int vis[26]; int pos[maxn][26]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> T; while (T--) { memset(vis, 0, sizeof(vis)); cin >> n >> m; for (int i = 0; i < 26; ++i) { for (int j = 0; j <= n + 5; ++j) { pos[j][i] = 0; } } cin >> s; for (int i = 0; i < s.size(); ++i) { for (int j = 0; j < 26; ++j) { pos[i][j] = pos[i - 1 == -1 ? 0 : i - 1][j]; } pos[i][s[i] - a ]++; } for (int i = 0, x; i < m; ++i) { cin >> x; x--; for (int j = 0; j < 26; ++j) { vis[j] += pos[x][j]; } } for (int j = 0; j < 26; ++j) { vis[j] += pos[n - 1][j]; } for (int i = 0; i < 26; ++i) { cout << vis[i] << ; } cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = 3.14159265359; long long max(long long a, long long b) { if (a >= b) return a; else return b; } long long min(long long a, long long b) { if (a <= b) return a; else return b; } bool valid(int i, int j, long long n, long long m) { if (i >= 0 && i < n && j >= 0 && j < m) return 1; else return 0; } void yes() { cout << YES << n ; } void no() { cout << NO << n ; } vector<unsigned long long> divisor(10000007); void printDivisors(long long n) { for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) { divisor[n] += i; } else { divisor[n] += i; divisor[n] += n / i; } } } } bool prime[1200000]; map<long long, long long> primes; void SieveOfEratosthenes(long long n = 1200000) { memset(prime, true, sizeof(prime)); prime[1] = false; for (int p = 2; p * p < n; p++) { if (prime[p] == true) { for (int i = p * 2; i < n; i += p) prime[i] = false; } } for (int i = 1; i < n + 1; i++) if (prime[i]) { primes[i]++; } } int gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } string toBinary(long long n) { string r; while (n != 0) { r = (n % 2 == 0 ? 0 : 1 ) + r; n /= 2; } return r; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } map<long long, long long> PF; void primeFactors(long long n) { while (n % 2 == 0) { PF[2]++; n = n / 2; } for (int i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { PF[i]++; n = n / i; } } if (n > 2) PF[n]++; } long double intlog(long long base, long long x) { long double ans1 = log10(x), ans2 = log10(base); return (long double)(ans1 / ans2); } bool IsPowerOfTwo(long long x) { return (x & (x - 1)) == 0; } map<long long, long long> LN; void GetLuckyNumbers(string s) { if (s.size() > 10) return; GetLuckyNumbers(s + 4 ); if (s != ) LN[stoll(s)]++; GetLuckyNumbers(s + 7 ); if (s != ) LN[stoll(s)]++; } unsigned long long toDecimal(unsigned long long n) { unsigned long long num = n; unsigned long long dec_value = 0; unsigned long long base = 1; int temp = num; while (temp) { unsigned long long last_digit = temp % 10; temp = temp / 10; dec_value += last_digit * base; base = base * 2; } return dec_value; } long double power(long double b, long long p) { if (p == 0) return 1; else if (p == 1) return b; long double a = power(b, p / 2); if (p % 2 == 0) return (a) * (a); return (b) * (a) * (a); } long largest_power_of_two(long N) { N = N | (N >> 1); N = N | (N >> 2); N = N | (N >> 4); N = N | (N >> 8); return (N + 1) >> 1; } long long cnt(string s) { long long c = 0; for (int i = 0; i < s.size(); i++) c += s[i] - 0 ; return c; } bool ispal(string s) { for (int i = 0; i < s.size() / 2; i++) { if (s[i] != s[s.size() - i - 1]) return false; } return true; } map<string, long long> substrings; void subString(string s, long long n) { for (int i = 0; i < n; i++) for (int len = 1; len <= n - i; len++) { substrings[s.substr(i, len)]++; } } bool check_divisabilty_prefix(string str, long long a) { long long len = str.size(); vector<int> lr(len + 1, 0); lr[0] = (str[0] - 0 ) % a; for (int i = 1; i < len; i++) lr[i] = ((lr[i - 1] * 10) % a + (str[i] - 0 )) % a; if (lr[len - 1] == 0) return 1; return 0; } bool check_divisabilty_suffix(string str, long long b) { long long len = str.size(); vector<long long> rl(len + 1, 0); rl[len - 1] = (str[len - 1] - 0 ) % b; int power10 = 10; for (int i = len - 2; i >= 0; i--) { rl[i] = (rl[i + 1] + (str[i] - 0 ) * power10) % b; power10 = (power10 * 10) % b; } if (rl[0] == 0) return 1; return 0; } bool isSubSeq(int idx1, int idx2, string s1, string s2) { if (idx2 == s2.size()) return true; if (idx1 == s1.size()) return false; if (s1[idx1] == s2[idx2]) return isSubSeq(idx1 + 1, idx2 + 1, s1, s2); else return isSubSeq(idx1 + 1, idx2, s1, s2); } vector<long long> v; long long bs(long long st, long long en, long long rq, long long val) { long long ans; while (st <= en) { long long mid = (st + en) / 2; long long aa = v[mid] - v[rq]; if (aa <= val) { st = mid + 1; ans = mid; } else en = mid - 1; } return abs(ans - rq); } bool isPerfectSquare(long double x) { if (x >= 0) { long long sr = sqrt(x); return (sr * sr == x); } return false; } long long fn(long long s) { if (s < 10) return s; long long pr = 1; while (s) { if (s % 10) pr *= (s % 10); s /= 10; } return fn(pr); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; vector<vector<long long> > v(11, vector<long long>(1e6 + 1, 0)); for (int i = 1; i <= 1000000; i++) { v[fn(i)].push_back(i); } int n; long long x; cin >> x; while (x--) { long long start, endd, nm; cin >> start >> endd >> nm; long long lower = lower_bound(v[nm].begin(), v[nm].end(), start) - v[nm].begin(); long long upper = lower_bound(v[nm].begin(), v[nm].end(), endd) - v[nm].begin(); if (v[nm][upper] == endd) { cout << (upper - lower) + 1 << endl; } else { cout << upper - lower << endl; } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V
|
module util_sigma_delta_spi (
input clk,
input resetn,
input spi_active,
input s_sclk,
input s_sdo,
input s_sdo_t,
output s_sdi,
input [NUM_CS-1:0] s_cs,
output m_sclk,
output m_sdo,
output m_sdo_t,
input m_sdi,
output [NUM_CS-1:0] m_cs,
output reg data_ready
);
parameter NUM_CS = 1;
parameter CS_PIN = 0;
parameter IDLE_TIMEOUT = 63;
/*
* For converters from the ADI SigmaDelta family the data ready interrupt signal
* uses the same physical wire as the the DOUT signal for the SPI bus. This
* module extracts the data ready signal from the SPI bus and makes sure to
* suppress false positives. The data ready signal is indicated by the converter
* by pulling DOUT low. This will only happen if the CS pin for the converter is
* low and no SPI transfer is active. There is a small delay between the end of
* the SPI transfer and the point where the converter starts to indicate the
* data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
* the bus needs to be idle before the data ready signal is detected.
*/
assign m_sclk = s_sclk;
assign m_sdo = s_sdo;
assign m_sdo_t = s_sdo_t;
assign s_sdi = m_sdi;
assign m_cs = s_cs;
reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
reg [2:0] sdi_d = 'h00;
always @(posedge clk) begin
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
end
always @(posedge clk) begin
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
end
always @(posedge clk) begin
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int const N = 100 * 1000 + 16; int const M = 1000 * 1000 * 1000 + 7; int n, k; int a[N]; int c[N]; ll e, v[N]; vector<int> idx[N]; struct wavelet { int L, R; vector<int> b; wavelet* l = 0; wavelet* r = 0; wavelet(int* pl, int* pr, int L, int R) { this->L = L; this->R = R; if (L == R || pl >= pr) return; int M = L + R >> 1; auto f = [M](int x) { return x <= M; }; b.reserve(pr - pl + 1); b.emplace_back(0); for (auto p = pl; p != pr; ++p) b.emplace_back(b.back() + f(*p)); auto pm = stable_partition(pl, pr, f); l = new wavelet(pl, pm, L, M); r = new wavelet(pm, pr, M + 1, R); } ~wavelet() { delete l; delete r; } int query(int l, int r, int k) { if (k < L || l >= r) return 0; if (R <= k) return r - l; int lf = b.size() > l ? b[l] : 0; int rg = b.size() > r ? b[r] : 0; return (this->l ? this->l->query(lf, rg, k) : 0) + (this->r ? this->r->query(l - lf, r - rg, k) : 0); } }; int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> n >> k; fill_n(a + 1, n, n + 1); for (int i = 1; i <= n; ++i) { int x; cin >> x; idx[x].emplace_back(i); if (++c[x] > k) a[idx[x][c[x] - k - 1]] = i; } wavelet t(a + 1, a + 1 + n, 1, 1000 * 1000 * 1000); int q; cin >> q; int last = 0; while (q--) { int xi, yi; cin >> xi >> yi; int l = (xi + last) % n + 1; int r = (yi + last) % n + 1; if (l > r) swap(l, r); int z = t.query(l - 1, r, r); last = r - l + 1 - z; cout << last << n ; } cout << flush; }
|
//#pragma comment(linker, /STACK:102400000,102400000 ) #include<bits/stdc++.h> using namespace std; typedef long long ll; #define int ll typedef pair<int,int>pii; #define ff first #define ss second #define debug(x) std:: cerr << #x << = << x << std::endl; const int maxn=2010,inf=0x3f3f3f3f,mod=1000000007; const ll INF=0x3f3f3f3f3f3f3f3f; const double eps=1e-9; //#define DEBUG//#define lowbit(x) ((x) & -(x))//<<setiosflags(ios::fixed)<<setprecision(9) void read(){} template<typename T,typename... T2>inline void read(T &x,T2 &... oth) { x=0; int ch=getchar(),f=0; while(ch< 0 ||ch> 9 ){if (ch== - ) f=1;ch=getchar();} while (ch>= 0 &&ch<= 9 ){x=(x<<1)+(x<<3)+(ch^48);ch=getchar();} if(f)x=-x; read(oth...); } ll a[maxn],dp[maxn][maxn]; ll MAX[maxn][maxn],MIN[maxn][maxn]; int s[maxn][maxn]; signed main(signed argc, char const *argv[]) { std::ios::sync_with_stdio(false),cin.tie(0),cout.tie(0); #ifdef DEBUG freopen( input.in , r , stdin); // freopen( output.out , w , stdout); #endif int n; cin>>n; for(int i=1;i<=n;i++) cin>>a[i]; sort(a+1,a+n+1); memset(dp,INF,sizeof(dp)); // memset(MIN,INF,sizeof(MIN)); for(int i=1;i<=n;i++) { dp[i][i]=0; // s[i][i]=i; // MAX[i][i]=MIN[i][i]=a[i]; } for(int len=2;len<=n;len++) { for(int l=1;l<=n-len+1;l++) { int r=l+len-1; dp[l][r]=min(dp[l][r-1],dp[l+1][r])+a[r]-a[l]; // fprintf(stderr, [%lld,%lld]=%lld n ,l,r,dp[l][r]); // for(int k=s[l][r-1];k<s[l+1][r];k++) // { // MAX[l][r]=max(MAX[l][k],MAX[k+1][r]); // MIN[l][r]=min(MIN[l][k],MIN[k+1][r]); // ll now=min(MAX[l][k]-MIN[k+1][r],a[r]-a[l]); // if(dp[l][r]>dp[l][k]+dp[k+1][r]+now) // { // dp[l][r]=dp[l][k]+dp[k+1][r]+now; // s[l][r]=k; // } // } } } cout<<dp[1][n]<<endl; return 0; } /* * 2021-04-16-23.54.07 */
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#include <bits/stdc++.h> using namespace std; const int MAXN = 1605; int n, m, tot; int a[MAXN][MAXN]; int sz[MAXN * MAXN]; int ans[MAXN * MAXN]; int cnt[MAXN * MAXN]; int fa1[MAXN * MAXN]; int fa2[MAXN * MAXN]; double v[MAXN][MAXN]; double t[MAXN][MAXN]; int getroot(int *fa, int u) { return u == fa[u] ? u : fa[u] = getroot(fa, fa[u]); } void run() { memcpy(t, v, sizeof(t)); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j]) { double sum = 0, cnt = 0; for (int k = i - 4; k <= i + 4; k++) for (int l = j - 4; l <= j + 4; l++) if (k >= 1 && k <= n && l >= 1 && l <= m && (i - k) * (i - k) + (j - l) * (j - l) <= 25) sum += t[k][l], cnt++; v[i][j] = sum / cnt; } } void merge(int *fa, int xa, int ya, int xb, int yb) { if (!a[xa][ya] || !a[xb][yb]) return; fa[getroot(fa, (xa - 1) * m + ya)] = getroot(fa, (xb - 1) * m + yb); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) fa1[(i - 1) * m + j] = fa2[(i - 1) * m + j] = (i - 1) * m + j; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %d , &a[i][j]); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j]) { v[i][j] = 1; if (i > 1) merge(fa1, i, j, i - 1, j); if (i < n) merge(fa1, i, j, i + 1, j); if (j > 1) merge(fa1, i, j, i, j - 1); if (j < m) merge(fa1, i, j, i, j + 1); } run(); run(); run(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] && v[i][j] < 0.2) { if (i > 1 && v[i - 1][j] < 0.2) merge(fa2, i, j, i - 1, j); if (i < n && v[i + 1][j] < 0.2) merge(fa2, i, j, i + 1, j); if (j > 1 && v[i][j - 1] < 0.2) merge(fa2, i, j, i, j - 1); if (j < m && v[i][j + 1] < 0.2) merge(fa2, i, j, i, j + 1); } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] && v[i][j] < 0.2) sz[getroot(fa2, (i - 1) * m + j)]++; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] && v[i][j] < 0.2 && getroot(fa2, (i - 1) * m + j) == (i - 1) * m + j && sz[(i - 1) * m + j] >= 5) cnt[getroot(fa1, (i - 1) * m + j)]++; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] && getroot(fa1, (i - 1) * m + j) == (i - 1) * m + j) ans[++tot] = cnt[(i - 1) * m + j]; sort(ans + 1, ans + tot + 1); printf( %d n , tot); for (int i = 1; i <= tot; i++) printf( %d , ans[i]); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int MAXN = 1e18 + 7; const long long int MAXNN = 300005; long long int int_pow(long long int base, long long int exp) { long long int result = 1; while (exp) { if (exp & 1) result *= base; exp /= 2; base *= base; } return result; } vector<long long int> g[MAXNN]; vector<long long int> w[MAXNN]; set<pair<long long int, long long int> > st; long long int dist[MAXNN]; long long int par[MAXNN]; bool mark[MAXNN]; map<pair<long long int, long long int>, long long int> mpw; map<pair<long long int, long long int>, long long int> mpn; void diekstra(long long int n, long long int s) { fill_n(dist, MAXNN, MAXN); dist[s] = 0; for (long long int i = 1; i <= n; i++) st.insert({dist[i], i}); while (!st.empty()) { set<pair<long long int, long long int> >::iterator it = st.begin(); long long int x = it->second; mark[x] = 1; st.erase(it); for (long long int i = 0; i < (long long int)g[x].size(); i++) { long long int y = g[x][i]; if (!mark[y]) { st.erase({dist[y], y}); if (dist[y] >= dist[x] + w[x][i]) { par[y] = x; } dist[y] = min(dist[y], dist[x] + w[x][i]); st.insert({dist[y], y}); } } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(par, -1, sizeof par); long long int n, m, u, v, z, stpoint = 0, ans = 0; cin >> n >> m; for (long long int i = 0; i < m; i++) { cin >> u >> v >> z; if (u > v) swap(u, v); mpn[{u, v}] = i + 1; mpw[{u, v}] = z; g[u].push_back(v); g[v].push_back(u); w[u].push_back(z); w[v].push_back(z); } cin >> stpoint; diekstra(n, stpoint); for (long long int i = 1; i <= n; i++) { if (i == stpoint) continue; u = i, v = par[i]; if (u > v) swap(u, v); ans += mpw[{u, v}]; } cout << ans << n ; for (long long int i = 1; i <= n; i++) { if (i == stpoint) continue; u = i, v = par[i]; if (u > v) swap(u, v); cout << mpn[{u, v}] << n ; } }
|
// Local Variables:
// verilog-library-directories:("." "../../")
// End:
module resource_table_tb ();
localparam CU_ID_WIDTH = 1;
localparam NUMBER_CU = 2;
localparam WF_SLOT_ID_WIDTH = 4;
localparam NUMBER_WF_SLOTS_PER_CU = 4;
localparam RES_ID_WIDTH = 4;
localparam NUMBER_RES_SLOTS = 16;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [RES_ID_WIDTH-1:0] cam_biggest_space_addr;// From DUT of resource_table.v
wire [RES_ID_WIDTH-1:0] cam_biggest_space_size;// From DUT of resource_table.v
wire res_table_done; // From DUT of resource_table.v
// End of automatics
reg clk;
reg rst;
reg [CU_ID_WIDTH-1:0] alloc_cu_id; // To DUT of resource_table.v
reg alloc_res_en; // To DUT of resource_table.v
reg [RES_ID_WIDTH-1:0] alloc_res_size; // To DUT of resource_table.v
reg [RES_ID_WIDTH-1:0] alloc_res_start; // To DUT of resource_table.v
reg [WF_SLOT_ID_WIDTH-1:0] alloc_wf_slot_id;// To DUT of resource_table.v
reg dealloc_res_en; // To DUT of resource_table.
reg [CU_ID_WIDTH-1:0] dealloc_cu_id; // To DUT of resource_table.v
reg [WF_SLOT_ID_WIDTH-1:0] dealloc_wf_slot_id;// To DUT of resource_table.v
resource_table #(/*AUTOINSTPARAM*/
// Parameters
.CU_ID_WIDTH (CU_ID_WIDTH),
.WF_SLOT_ID_WIDTH (WF_SLOT_ID_WIDTH),
.NUMBER_CU (NUMBER_CU),
.NUMBER_WF_SLOTS_PER_CU(NUMBER_WF_SLOTS_PER_CU),
.NUMBER_RES_SLOTS (NUMBER_RES_SLOTS),
.RES_ID_WIDTH (RES_ID_WIDTH))
DUT (/*AUTOINST*/
// Outputs
.res_table_done (res_table_done),
.cam_biggest_space_size (cam_biggest_space_size[RES_ID_WIDTH-1:0]),
.cam_biggest_space_addr (cam_biggest_space_addr[RES_ID_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.alloc_res_en (alloc_res_en),
.dealloc_res_en (dealloc_res_en),
.alloc_cu_id (alloc_cu_id[CU_ID_WIDTH-1:0]),
.dealloc_cu_id (dealloc_cu_id[CU_ID_WIDTH-1:0]),
.alloc_wf_slot_id (alloc_wf_slot_id[WF_SLOT_ID_WIDTH-1:0]),
.dealloc_wf_slot_id (dealloc_wf_slot_id[WF_SLOT_ID_WIDTH-1:0]),
.alloc_res_size (alloc_res_size[RES_ID_WIDTH-1:0]),
.alloc_res_start (alloc_res_start[RES_ID_WIDTH-1:0]));
// Clk block
initial begin
clk = 1'b0;
forever begin
#5 clk = ! clk;
end
end
initial begin
// Reset the design
rst = 1'b1;
alloc_res_en <= 1'b0;
dealloc_res_en <= 1'b0;
@(posedge clk);
@(posedge clk);
rst = 1'b0;
// Allocate some wf
@(posedge clk);
@(posedge clk);
alloc_res_en <= 1'b1;
alloc_cu_id <= 2'h0;
alloc_wf_slot_id <= 4'h0;
alloc_res_start <= 0;
alloc_res_size <= 4'h5;
@(posedge clk);
alloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
alloc_res_en <= 1'b1;
alloc_cu_id <= 2'h0;
alloc_wf_slot_id <= 4'h1;
alloc_res_start <= 4'h5;
alloc_res_size <= 4'h5;
@(posedge clk);
alloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
alloc_res_en <= 1'b1;
alloc_cu_id <= 2'h0;
alloc_wf_slot_id <= 4'h2;
alloc_res_start <= 4'hf;
alloc_res_size <= 4'h1;
@(posedge clk);
alloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
alloc_res_en <= 1'b1;
alloc_cu_id <= 2'h0;
alloc_wf_slot_id <= 4'h3;
alloc_res_start <= 4'ha;
alloc_res_size <= 4'h5;
@(posedge clk);
alloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
alloc_res_en <= 1'b1;
alloc_cu_id <= 1'h1;
alloc_wf_slot_id <= 4'h3;
alloc_res_start <= 4'ha;
alloc_res_size <= 4'h5;
@(posedge clk);
alloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
// Deallocate some
dealloc_res_en <= 1'b1;
dealloc_cu_id <= 2'h0;
dealloc_wf_slot_id <= 4'h0;
@(posedge clk);
dealloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
dealloc_res_en <= 1'b1;
dealloc_cu_id <= 2'h0;
dealloc_wf_slot_id <= 4'h1;
@(posedge clk);
dealloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
dealloc_res_en <= 1'b1;
dealloc_cu_id <= 2'h0;
dealloc_wf_slot_id <= 4'h3;
@(posedge clk);
dealloc_res_en <= 1'b0;
@(posedge res_table_done);
@(posedge clk);
// Allocate some
// Add control signals to trigger printing stuff
end
endmodule // resource_table_tb
|
#include <bits/stdc++.h> inline int read() { int x; char c; while ((c = getchar()) < 0 || c > 9 ) ; for (x = c - 0 ; (c = getchar()) >= 0 && c <= 9 ;) x = x * 10 + c - 0 ; return x; } int a[100000 + 5]; void solve(int n) { for (int i = 20, x; i; --i) if (n & (1 << i)) { x = ((1 << i + 1) - 1) ^ n; if (x > 1) solve(x - 1); while (n >= x) printf( %d , n--); return; } } int main() { int n = read(), i; if (n & 1) puts( NO ); else puts( YES ), solve(n), puts( ); if (n < 6 || n == (n & -n)) puts( NO ); else { puts( YES ); a[1] = 3; a[2] = 6; a[3] = 2; a[4] = 5; a[5] = 1; a[6] = 4; for (i = 7; i <= n; ++i) if (i == (i & -i)) a[i] = i + 1, a[i + 1] = i, ++i; else a[i] = a[i & -i], a[i & -i] = i; for (i = 1; i <= n; ++i) printf( %d , a[i]); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { float h, l, ans; cin >> h >> l; ans = (l * l - h * h) / (2 * h); cout << setprecision(13) << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long f[200][200], a[200], x[200], y[200], d; int n; long long dist(int i, int j) { return abs(x[i] - x[j]) + abs(y[i] - y[j]); } int main() { cin >> n >> d; for (int i = 2; i <= n - 1; i++) cin >> a[i]; for (int i = 1; i <= n; i++) cin >> x[i] >> y[i]; memset(f, 61, sizeof(f)); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j) f[i][j] = dist(i, j) * d - a[i]; for (int i = 1; i <= n; i++) f[i][i] = 0; for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = min(f[i][j], f[i][k] + f[k][j]); if (f[1][n] <= 0) cout << 0; else cout << f[1][n]; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_2_V
`define SKY130_FD_SC_HD__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 500 + 7; long long mod = 1e9 + 7; bool solve(long long l, long long r, long long mx, long long& ans) { if (r - l + 1 > mx) { return false; } ans = -l + 1; return true; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; string s; cin >> s; int x = 0, y = 0, mnx = 0, mxx = 0, mny = 0, mxy = 0; long long ansX = 1, ansY = 1; for (auto i : s) { x += i == D ; x -= i == U ; y += i == R ; y -= i == L ; mnx = min(x, mnx); mxx = max(x, mxx); mny = min(y, mny); mxy = max(y, mxy); long long tmpX, tmpY; if (solve(mnx, mxx, n, tmpX) && solve(mny, mxy, m, tmpY)) { ansX = tmpX, ansY = tmpY; continue; } break; } cout << ansX << << ansY << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int p; cin >> p; for (long long int z = 0; z < p; z++) { long long int n; cin >> n; while (1) { break; } string a; cin >> a; long long int re = 0, ro = 0, be = 0, bo = 0; for (long long int i = 0; i < n; i++) { if (i % 2 == 0) { if (a[i] % 2 == 0) { re++; } else ro++; } else { if (a[i] % 2 == 0) { be++; } else bo++; } } while (1) { break; } if (n % 2 == 0) { if (be > 0) cout << 2 n ; else cout << 1 n ; while (1) { break; } } else { while (1) { break; } if (ro > 0) cout << 1 n ; else cout << 2 n ; while (1) { break; } } } }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
1.1 Added generate logic around the internal burst count logic to prevent zero
replication simulation bug. In the case of a non-bursting master the
burst count is just hardcoded to 1.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
generate
if ((BURST_ENABLE == 1) & (BURST_COUNT_WIDTH > 1))
begin
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; char a[1010], b[1010]; int h = 0; int main() { scanf( %s , a); int l = strlen(a); int j = 0; for (int i = 0; i < l; i++) { b[j++] = a[i]; if (a[i] == > ) { b[j] = 0; if (b[1] == / ) h--; for (int k = 0; k < 2 * h; k++) putchar( ); if (b[1] != / ) h++; puts(b); j = 0; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; double ans; int a[N]; int n, u, p; int main() { scanf( %d%d , &n, &u); ans = 0; for (int i = 1; i <= n; i++) { scanf( %d , a + i); } for (int i = 1; i <= n; i++) { if (i <= n - 2) { p = lower_bound(a + i + 2, a + n + 1, a[i] + u) - a; if (p > n || a[i] + u != a[p]) p--; if (p >= i + 2) { ans = max(ans, (a[p] - a[i + 1]) * 1.0 / (a[p] - a[i])); } } } if (ans == 0) printf( -1 n ); else printf( %.11lf n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; if (k == 0 || k == n) { cout << 0 0 ; return 0; } cout << min(1LL, n - k) << << min(n - k, k * 2LL); return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937_64 rnd(time(NULL)); const int N = 25; const int inf = 1e9; const double MAX_T = 1000; const double MIN_T = 1e-5; const int max_mutations = 10; int n, m; vector<int> A, B; vector<vector<int> > best_ans, cur_ans; int best_cost = 0; inline void mutation(vector<vector<int> > &a) { int cnt = rnd() % max_mutations + 1; for (; cnt; cnt--) { int x = rnd() % n, y = rnd() % m; a[x][y] = rnd() % 2; } } inline int calc(vector<vector<int> > &a) { int x = 0, res = 0; for (int i = 0; i < n; i++) { x = 0; for (int j = 0; j < m; j++) { if (a[i][j] == 1 && (j == 0 || a[i][j - 1] == 0)) x++; } res += (x - A[i]) * (x - A[i]); } for (int i = 0; i < m; i++) { x = 0; for (int j = 0; j < n; j++) { if (a[j][i] == 1 && (j == 0 || a[j - 1][i] == 0)) x++; } res += (x - B[i]) * (x - B[i]); } return res; } inline double ok(double E, double t) { return exp(-E / t); } inline bool valid(double E, double t) { if (E < 0) return true; double x = ok(E, t); x *= inf; return (rnd() % inf <= x); } int main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; A.resize(n, 0); B.resize(m, 0); for (int i = 0; i < n; i++) cin >> A[i]; for (int j = 0; j < m; j++) cin >> B[j]; cur_ans.assign(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cur_ans[i][j] = rnd() % 2; best_ans = cur_ans; best_cost = calc(cur_ans); double T = MAX_T; int i = 1; while (T > MIN_T && best_cost != 0) { mutation(cur_ans); int cur_cost = calc(cur_ans); if (valid(cur_cost - best_cost, T)) { best_cost = min(best_cost, cur_cost); if (best_cost == cur_cost) best_ans = cur_ans; } else cur_ans = best_ans; T = MAX_T * 0.1 / i; i++; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (best_ans[i][j]) cout << * ; else cout << . ; } cout << n ; } return 0; }
|
// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
// This file represents the Composite Function Block for CfbTlNetwork
module FB_CfbTlNetwork
(
input wire clk,
//input events
input wire Tick_eI,
input wire Start_eI,
input wire SpecialInstr_eI,
input wire N_S_PedWaiting_eI,
input wire E_W_PedWaiting_eI,
//output events
output wire N_S_PedLightsChange_eO,
output wire N_S_TrafLightsChange_eO,
output wire E_W_PedLightsChange_eO,
output wire E_W_TrafLightsChange_eO,
//input variables
input wire N_S_HoldGreen_I,
input wire E_W_HoldGreen_I,
//output variables
output wire N_S_PedRed_O ,
output wire N_S_PedFlashRed_O ,
output wire N_S_PedGreen_O ,
output wire N_S_TrafRed_O ,
output wire N_S_TrafYellow_O ,
output wire N_S_TrafGreen_O ,
output wire E_W_PedRed_O ,
output wire E_W_PedFlashRed_O ,
output wire E_W_PedGreen_O ,
output wire E_W_TrafRed_O ,
output wire E_W_TrafYellow_O ,
output wire E_W_TrafGreen_O ,
input reset
);
//Wires needed for event connections
wire Tick_conn;
wire SpecialInstr_conn;
wire Start_conn;
wire mt_N_S_Start_conn;
wire N_S_DoneSeq_conn;
wire mt_E_W_Start_conn;
wire E_W_DoneSeq_conn;
wire N_S_PedWaiting_conn;
wire E_W_PedWaiting_conn;
wire N_S_PedLightsChange_conn;
wire N_S_TrafLightsChange_conn;
wire E_W_PedLightsChange_conn;
wire E_W_TrafLightsChange_conn;
//Wires needed for data connections
wire N_S_HoldGreen_conn;
wire E_W_HoldGreen_conn;
wire N_S_PedRed_conn;
wire N_S_PedFlashRed_conn;
wire N_S_PedGreen_conn;
wire N_S_TrafRed_conn;
wire N_S_TrafYellow_conn;
wire N_S_TrafGreen_conn;
wire E_W_PedRed_conn;
wire E_W_PedFlashRed_conn;
wire E_W_PedGreen_conn;
wire E_W_TrafRed_conn;
wire E_W_TrafYellow_conn;
wire E_W_TrafGreen_conn;
//top level I/O to signals
//input events
assign Tick_conn = Tick_eI;
assign Tick_conn = Tick_eI;
assign Start_conn = Start_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign SpecialInstr_conn = SpecialInstr_eI;
assign N_S_PedWaiting_conn = N_S_PedWaiting_eI;
assign E_W_PedWaiting_conn = E_W_PedWaiting_eI;
//output events
assign N_S_PedLightsChange_eO = N_S_PedLightsChange_conn;
assign N_S_TrafLightsChange_eO = N_S_TrafLightsChange_conn;
assign E_W_PedLightsChange_eO = E_W_PedLightsChange_conn;
assign E_W_TrafLightsChange_eO = E_W_TrafLightsChange_conn;
//input variables
assign N_S_HoldGreen_conn = N_S_HoldGreen_I;
assign E_W_HoldGreen_conn = E_W_HoldGreen_I;
//output events
assign N_S_PedRed_O = N_S_PedRed_conn;
assign N_S_PedFlashRed_O = N_S_PedFlashRed_conn;
assign N_S_PedGreen_O = N_S_PedGreen_conn;
assign N_S_TrafRed_O = N_S_TrafRed_conn;
assign N_S_TrafYellow_O = N_S_TrafYellow_conn;
assign N_S_TrafGreen_O = N_S_TrafGreen_conn;
assign E_W_PedRed_O = E_W_PedRed_conn;
assign E_W_PedFlashRed_O = E_W_PedFlashRed_conn;
assign E_W_PedGreen_O = E_W_PedGreen_conn;
assign E_W_TrafRed_O = E_W_TrafRed_conn;
assign E_W_TrafYellow_O = E_W_TrafYellow_conn;
assign E_W_TrafGreen_O = E_W_TrafGreen_conn;
// child I/O to signals
FB_CfbOneLink N_S (
.clk(clk),
//event outputs
.DoneSeq_eO(N_S_DoneSeq_conn),
.PedLightsChange_eO(N_S_PedLightsChange_conn),
.TrafLightsChange_eO(N_S_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_N_S_Start_conn),
.PedWaiting_eI(N_S_PedWaiting_conn),
//data outputs
.PedRed_O(N_S_PedRed_conn),
.PedFlashRed_O(N_S_PedFlashRed_conn),
.PedGreen_O(N_S_PedGreen_conn),
.TrafRed_O(N_S_TrafRed_conn),
.TrafYellow_O(N_S_TrafYellow_conn),
.TrafGreen_O(N_S_TrafGreen_conn),
//data inputs
.HoldGreen_I(N_S_HoldGreen_conn),
.reset(reset)
);
FB_CfbOneLink E_W (
.clk(clk),
//event outputs
.DoneSeq_eO(E_W_DoneSeq_conn),
.PedLightsChange_eO(E_W_PedLightsChange_conn),
.TrafLightsChange_eO(E_W_TrafLightsChange_conn),
//event inputs
.Tick_eI(Tick_conn),
.SpecialInstr_eI(SpecialInstr_conn),
.GoSeq_eI(mt_E_W_Start_conn),
.PedWaiting_eI(E_W_PedWaiting_conn),
//data outputs
.PedRed_O(E_W_PedRed_conn),
.PedFlashRed_O(E_W_PedFlashRed_conn),
.PedGreen_O(E_W_PedGreen_conn),
.TrafRed_O(E_W_TrafRed_conn),
.TrafYellow_O(E_W_TrafYellow_conn),
.TrafGreen_O(E_W_TrafGreen_conn),
//data inputs
.HoldGreen_I(E_W_HoldGreen_conn),
.reset(reset)
);
FB_BfbIntersectionMutex mt (
.clk(clk),
//event outputs
.N_S_Start_eO(mt_N_S_Start_conn),
.E_W_Start_eO(mt_E_W_Start_conn),
//event inputs
.Start_eI(Start_conn),
.N_S_Done_eI(N_S_DoneSeq_conn),
.E_W_Done_eI(E_W_DoneSeq_conn),
//data outputs
//data inputs
.reset(reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int dp[2005][2005]; int main() { int n, i, k1, j, k; cin >> n >> k1; long long int ans = 0; dp[0][1] = 1; for (i = 1; i <= k1; i++) { for (j = 1; j <= n; j++) { for (k = j; k <= n; k += j) { dp[i][k] += dp[i - 1][j]; dp[i][k] %= 1000000007; } } } for (j = 1; j <= n; j++) { ans += dp[k1][j]; ans %= 1000000007; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 300 * 1000 + 10; pair<int, int> c[MAX_N]; int t[MAX_N]; int main() { ios_base ::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> c[i].first, c[i].second = i; set<int> s; for (int i = k; i < n + k; i++) s.insert(i); sort(c, c + n); long long ans = 0; for (int i = n - 1; ~i; i--) { int id = c[i].second; s.erase(t[id] = *s.lower_bound(id)); ans += 1LL * abs(t[id] - id) * c[i].first; } cout << ans << endl; for (int i = 0; i < n; i++) cout << t[i] + 1 << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long spf[100001]; bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } long long power(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a); a = (a * a); b >>= 1; } return res; } long long modpow(long long a, long long b, long long x) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % x; a = (a * a) % x; b >>= 1; } return res; } void sieve() { spf[1] = 1; for (long long i = 2; i < 100001; i++) spf[i] = i; for (long long i = 4; i < 100001; i += 2) spf[i] = 2; for (long long i = 3; i * i < 100001; i++) if (spf[i] == i) for (long long j = i * i; j < 100001; j += i) if (spf[j] == j) spf[j] = i; } vector<long long> getFactorization(long long x) { vector<long long> ret; while (x != 1) { ret.push_back(spf[x]); x = x / spf[x]; } return ret; } void solve() { long long n, m; cin >> n >> m; vector<long long> adj[n + 1]; for (int i = 0; i < m; i++) { long long a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } vector<pair<long long, long long>> topic(n); for (int i = 0; i < n; i++) { long long a; cin >> a; topic[i] = {a, i + 1}; } sort(topic.begin(), topic.end()); vector<long long> res; vector<set<long long>> around(n + 1); for (int i = 0; i < topic.size(); i++) { long long u = topic[i].second; res.push_back(u); if (around[u].find(topic[i].first) != around[u].end() || around[u].size() != topic[i].first - 1) { cout << -1 << n ; return; } for (auto j : adj[u]) { around[j].insert(topic[i].first); } } for (auto i : res) cout << i << ; cout << n ; ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, k, dotx, doty; char t[502][502]; int vis[502][502]; int x[4] = {0, -1, 0, 1}; int y[4] = {1, 0, -1, 0}; void dfs(int r, int c) { if (r >= n || r < 0 || c >= m || c < 0 || t[r][c] == # || vis[r][c]) return; vis[r][c] = 1; for (int i = 0; i < 4; i++) { dfs(r + x[i], c + y[i]); } if (k > 0) { k--; t[r][c] = X ; } } int main() { cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> t[i][j]; if (t[i][j] == . ) { dotx = i; doty = j; } } dfs(dotx, doty); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << t[i][j]; } cout << n ; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; void run(vector<vector<int>> &sets, int **sum); pair<vector<vector<int>>, int **> precalc(); const int MAXB = 5; const int MOD = 1e9 + 7; int main() { ios::sync_with_stdio(false); cout.tie(0); auto precalc_vals = precalc(); run(precalc_vals.first, precalc_vals.second); } template <typename type> type *farray(int n) { return (type *)malloc(n * sizeof(type)); } template <typename type> type *farray(int n, type val) { auto res = farray<type>(n); fill(res, res + n, val); return res; } template <typename type> type **dim2_farray(int n, int m) { auto res = farray<type *>(n); for (int i = 0; i < n; i++) { res[i] = farray<type>(m); } return res; } template <typename type> type **dim2_farray(int n, int m, type val) { auto res = farray<type *>(n); for (int i = 0; i < n; i++) { res[i] = farray<type>(m, val); } return res; } template <typename type> void dim2_free(type *arr, int n) { for (int i = 0; i < n; i++) free(arr[i]); free(arr); } bool gauss(bool **matrix, bool *vec, int n, int m) { if (m > n) return false; for (int k = 0; k < m; k++) { int st = k; for (; st < n && matrix[st][k] == 0; st++) ; if (st == n) return false; for (int c = 0; c < m; c++) { swap(matrix[st][c], matrix[k][c]); } swap(vec[st], vec[k]); for (int r = st + 1; r < n; r++) { if (matrix[r][k] == 0) continue; for (int c = k; c < m; c++) { matrix[r][c] -= matrix[k][c]; } vec[r] -= vec[k]; } } for (int k = m - 1; k >= 0; k--) { for (int r = k - 1; r >= 0; r--) { if (matrix[r][k] == 0) continue; matrix[r][k] -= 1; vec[r] -= vec[k]; } } for (int k = m; k < n; k++) { bool val = 0; for (int c = 0; c < m; c++) { val += matrix[k][c] * vec[c]; } if (val != vec[k]) return false; } return true; } bool **to_matrix(const vector<int> &a) { int len = (int)a.size(); auto matrix = dim2_farray<bool>(MAXB, len); for (int i = 0; i < len; i++) { for (int b = 0; b < MAXB; b++) { matrix[b][i] = (a[i] & (1 << b)) > 0; } } return matrix; } bool indep(const vector<int> &a) { int len = (int)a.size(); auto matrix = to_matrix(a); auto vec = farray<bool>(MAXB, 0); return gauss(matrix, vec, MAXB, len); } bool *bin(int a) { auto res = farray<bool>(MAXB); for (int i = 0; i < MAXB; i++) { res[i] = a & (1 << i); } return res; } bool the_same(const vector<int> &a, const vector<int> &b) { if (a.size() != b.size()) return false; int len = b.size(); for (int i = 0; i < len; i++) { auto a_matrix = to_matrix(a); if (!gauss(a_matrix, bin(b[i]), MAXB, len)) { dim2_free(a_matrix, MAXB); return false; } dim2_free(a_matrix, MAXB); } return true; } void precalc_sets(int from, vector<vector<int>> &ans, vector<int> &cur, int k = 0) { cur.push_back(0); for (int i = from; i < (1 << MAXB); i++) { cur.back() = i; if (indep(cur)) { bool new_one = true; for (auto &v : ans) { if (the_same(cur, v)) { new_one = false; break; } } if (new_one) { ans.push_back(cur); precalc_sets(i + 1, ans, cur, k + 1); } } } cur.pop_back(); } int set_id(vector<int> &basis, vector<vector<int>> &sets) { for (int i = 0; i < (int)sets.size(); i++) { if (the_same(basis, sets[i])) { return i; } } return -1; } int **precalc_sums(vector<vector<int>> &sets) { int n = (int)sets.size(); auto res = dim2_farray<int>(n, n); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { vector<int> cur = sets[i]; cur.insert(cur.end(), sets[j].begin(), sets[j].end()); if (indep(cur)) { res[i][j] = set_id(cur, sets); } else { res[i][j] = -1; } } } return res; } pair<vector<vector<int>>, int **> precalc() { vector<vector<int>> sets(1); vector<int> cur; precalc_sets(0, sets, cur); auto sums = precalc_sums(sets); return {sets, sums}; } struct Graph { int *head, *nxt, *eto, *cost, eto_ptr = 0; Graph(int n, int m) { head = farray<int>(n, -1); nxt = farray<int>(m); eto = farray<int>(m); cost = farray<int>(m); } void add_edge(int from, int to, int c) { eto[eto_ptr++] = to; nxt[eto_ptr - 1] = head[from]; head[from] = eto_ptr - 1; cost[eto_ptr - 1] = c; } }; void get_basis(int v, Graph &graph, vector<bool> &used, int *path_xor, vector<int> &basis, int p = -1) { used[v] = true; for (int e = graph.head[v]; e != -1; e = graph.nxt[e]) { int u = graph.eto[e]; if (u == p || u == 1) continue; if (!used[u]) { path_xor[u] = path_xor[v] ^ graph.cost[e]; get_basis(u, graph, used, path_xor, basis, v); } else if (u < v) { basis.push_back(path_xor[v] ^ path_xor[u] ^ graph.cost[e]); } } } void run(vector<vector<int>> &sets, int **sums) { int n, m; cin >> n >> m; Graph graph(n + 1, m * 2); for (int i = 0; i < m; i++) { int u, v, c; cin >> u >> v >> c; graph.add_edge(u, v, c); graph.add_edge(v, u, c); } auto near_one = farray<int>(n + 1, -1); for (int e = graph.head[1]; e != -1; e = graph.nxt[e]) { int u = graph.eto[e]; near_one[u] = graph.cost[e]; } vector<bool> used(n + 1); used[1] = true; vector<vector<int>> dims = {{}}; auto path_xor = farray<int>(n + 1, 0); for (int v = 2; v <= n; v++) { if (used[v] || near_one[v] == -1) continue; int u = -1, c = -1; for (int e2 = graph.head[v]; e2 != -1; e2 = graph.nxt[e2]) { u = graph.eto[e2]; c = graph.cost[e2]; if (near_one[u] != -1) { break; } u = -1; } vector<int> basis; get_basis(v, graph, used, path_xor, basis); if (!indep(basis)) continue; dims.push_back({set_id(basis, sets)}); if (u != -1) { dims.back().push_back(dims.back().back()); basis.push_back(near_one[v] ^ near_one[u] ^ c); if (indep(basis)) { dims.back().push_back(set_id(basis, sets)); } } } int p = sets.size(); int k = dims.size(); auto dp = dim2_farray<int>(k, p, 0); dp[0][0] = 1; for (int i = 1; i < k; i++) { for (int d = 0; d < p; d++) { dp[i][d] = dp[i - 1][d]; } for (int d = 0; d < p; d++) { for (int a : dims[i]) { if (sums[d][a] == -1) continue; int new_dim = sums[d][a]; dp[i][new_dim] = (dp[i][new_dim] + dp[i - 1][d]) % MOD; } } } int ans = 0; for (int i = 0; i < p; i++) { ans = (ans + dp[k - 1][i]) % MOD; } cout << ans << endl; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:57:07 03/28/2014
// Design Name: alu
// Module Name: D:/XilinxProject/CPU/alu_tester.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_tester;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [3:0] aluc;
// Outputs
wire zero;
wire [31:0] result;
// Instantiate the Unit Under Test (UUT)
alu uut (
.a(a),
.b(b),
.aluc(aluc),
.zero(zero),
.result(result)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
aluc = 0;
// Wait 100 ns for global reset to finish
#100;
a = 127;
b = 128;
aluc = 3;
#100;
a = 128;
b = 128;
aluc = 3;
#100;
a = 1;
b = 1;
aluc = 8;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> struct val { long long x; int y, d; val *p, *l, *r; } g1[100001], g2[100001], *rt1[100001], *rt2[100001], *nil = g1; struct node { long long x; int y; bool operator<(const node &b) const { return x < b.x; } } a[100001]; struct vale { long long x; int y; bool operator<(const vale &b) const { return x > b.x; } } c[100001]; using namespace std; int n, g[100001], h[100001], fa[100001], d[100001], wt, ss[19]; char fl[1 << 23], *A = fl; long long f[100001], e[100001], b[100001]; void read(int &x) { char c; for (x = 0; 0 > (c = *A++) || c > 9 ;) ; while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + c - 48, (c = *A++); } void read(long long &x) { char c; for (x = 0; 0 > (c = *A++) || c > 9 ;) ; while ( 0 <= c && c <= 9 ) x = (x << 3) + (x << 1) + c - 48, (c = *A++); } void print(long long x) { if (!x) putchar(48); else { for (wt = 0; x; ss[++wt] = x % 10, x /= 10) ; for (; wt; putchar(ss[wt--] + 48)) ; } } val *mg1(val *x, val *y) { return x == nil ? y : (y == nil ? x : (x->x < y->x ? ((x->r = mg1(x->r, y))->p = x, x->l->d < x->r->d ? (swap(x->l, x->r), 0) : 0, x->d = x->l->d + 1, x) : ((y->r = mg1(y->r, x))->p = y, y->l->d < y->r->d ? (swap(y->l, y->r), 0) : 0, y->d = y->l->d + 1, y))); } val *mg2(val *x, val *y) { return x == nil ? y : (y == nil ? x : (x->x > y->x ? ((x->r = mg2(x->r, y))->p = x, x->l->d < x->r->d ? (swap(x->l, x->r), 0) : 0, x->d = x->l->d + 1, x) : ((y->r = mg2(y->r, x))->p = y, y->l->d < y->r->d ? (swap(y->l, y->r), 0) : 0, y->d = y->l->d + 1, y))); } void fix_min(long long t1, int z) { int tmp, x, LIA; if (a[x = g[z]].x != t1) if (a[x].x = t1, x > 1 && a[x] < a[x >> 1]) for (; x > 1 && a[x] < a[x >> 1]; swap(a[x], a[x >> 1]), swap(g[a[x].y], g[a[x >> 1].y]), x >>= 1) ; else for (; (x << 1) <= n;) { if (a[tmp = x << 1] < a[LIA = x]) LIA = tmp; if ((tmp |= 1) <= n && a[tmp] < a[LIA]) LIA = tmp; if (LIA != x) swap(a[LIA], a[x]), swap(g[a[LIA].y], g[a[x].y]), x = LIA; else break; } } void fix_max(long long t1, int z) { int tmp, x, LIA; if (c[x = h[z]].x != t1) if (c[x].x = t1, x > 1 && c[x] < c[x >> 1]) for (; x > 1 && c[x] < c[x >> 1]; swap(c[x], c[x >> 1]), swap(h[c[x].y], h[c[x >> 1].y]), x >>= 1) ; else for (; (x << 1) <= n;) { if (c[tmp = x << 1] < c[LIA = x]) LIA = tmp; if ((tmp |= 1) <= n && c[tmp] < c[LIA]) LIA = tmp; if (LIA != x) swap(c[LIA], c[x]), swap(h[c[LIA].y], h[c[x].y]), x = LIA; else break; } } void fix(int x) { if (g1[x].p == nil) (rt1[fa[x]] = mg1(g1[x].l, g1[x].r))->p = nil; else if (g1[x].p->l == &g1[x]) (g1[x].p->l = mg1(g1[x].l, g1[x].r))->p = g1[x].p; else (g1[x].p->r = mg1(g1[x].l, g1[x].r))->p = g1[x].p; g1[x].x = f[x], g1[x].l = g1[x].r = nil, (rt1[fa[x]] = mg1(rt1[fa[x]], &g1[x]))->p = nil; if (g2[x].p == nil) (rt2[fa[x]] = mg2(g2[x].l, g2[x].r))->p = nil; else if (g2[x].p->l == &g2[x]) (g2[x].p->l = mg2(g2[x].l, g2[x].r))->p = g2[x].p; else (g2[x].p->r = mg2(g2[x].l, g2[x].r))->p = g2[x].p; g2[x].x = f[x], g2[x].l = g2[x].r = nil, (rt2[fa[x]] = mg2(rt2[fa[x]], &g2[x]))->p = nil; } void alter(int z, int x, int y, int LAx, int LAy) { long long t1 = e[x], t3 = e[y]; int t2 = b[x] % d[x], t4 = b[y] % d[y]; f[y] += b[y] % (++d[y]) + e[z] - t4, e[y] = b[y] / d[y], f[LAy] += e[y] - t3, f[y] += e[y] - t3; f[x] += b[x] % (--d[x]) - e[z] - t2, e[x] = b[x] / d[x], f[LAx] += e[x] - t1, f[x] += e[x] - t1; if (e[y] != t3) fix(LAy); if (e[x] != t1 && LAx != LAy) fix(LAx); fix(x), fix(y); if (g1[z].p == nil) (rt1[x] = mg1(g1[z].l, g1[z].r))->p = nil; else if (g1[z].p->l == &g1[z]) (g1[z].p->l = mg1(g1[z].l, g1[z].r))->p = g1[z].p; else (g1[z].p->r = mg1(g1[z].l, g1[z].r))->p = g1[z].p; g1[z].x = f[z], g1[z].l = g1[z].r = nil, (rt1[fa[z] = y] = mg1(rt1[y], &g1[z]))->p = nil; if (g2[z].p == nil) (rt2[x] = mg2(g2[z].l, g2[z].r))->p = nil; else if (g2[z].p->l == &g2[z]) (g2[z].p->l = mg2(g2[z].l, g2[z].r))->p = g2[z].p; else (g2[z].p->r = mg2(g2[z].l, g2[z].r))->p = g2[z].p; g2[z].x = f[z], g2[z].l = g2[z].r = nil, (rt2[y] = mg2(rt2[y], &g2[z]))->p = nil; fix_max(e[fa[LAx]] + f[LAx], LAx); fix_max(e[fa[LAy]] + f[LAy], LAy); fix_max(rt2[LAx]->x + e[LAx], rt2[LAx]->y); fix_max(rt2[LAy]->x + e[LAy], rt2[LAy]->y); if (rt2[x] != nil) fix_max(rt2[x]->x + e[x], rt2[x]->y); fix_max(rt2[y]->x + e[y], rt2[y]->y); fix_min(e[fa[LAx]] + f[LAx], LAx); fix_min(e[fa[LAy]] + f[LAy], LAy); fix_min(rt1[LAx]->x + e[LAx], rt1[LAx]->y); fix_min(rt1[LAy]->x + e[LAy], rt1[LAy]->y); if (rt1[x] != nil) fix_min(rt1[x]->x + e[x], rt1[x]->y); fix_min(rt1[y]->x + e[y], rt1[y]->y); } void dfs(int x) { long long t1 = e[fa[a[x].y]] + f[a[x].y]; int tmp = a[x].y; if (a[x].x != t1) { if ((x << 1) <= n) dfs(x << 1); if ((x << 1 | 1) <= n) dfs(x << 1 | 1); fix_min(t1, tmp); } } void vfs(int x) { long long t1 = e[fa[c[x].y]] + f[c[x].y]; int tmp = c[x].y; if (c[x].x != t1) { if ((x << 1) <= n) vfs(x << 1); if ((x << 1 | 1) <= n) vfs(x << 1 | 1); fix_max(t1, tmp); } } void efs(int x) { long long t1 = e[fa[a[x].y]] + f[a[x].y]; int tmp = a[x].y; if ((x << 1) <= n) efs(x << 1); if ((x << 1 | 1) <= n) efs(x << 1 | 1); fix_min(t1, tmp); } void gfs(int x) { long long t1 = e[fa[c[x].y]] + f[c[x].y]; int tmp = c[x].y; if ((x << 1) <= n) gfs(x << 1); if ((x << 1 | 1) <= n) gfs(x << 1 | 1); fix_max(t1, tmp); } int main() { int test, i, x, y, tmp, LIA; for (*(fl + fread(fl, 1, 1 << 23, stdin)) = EOF, read(n), read(test), i = 1; i <= n; d[i] = 2, rt1[i] = rt2[i] = nil, read(b[i++])) ; for (i = 1; i <= n; read(fa[i]), d[fa[i]]++, i++) ; for (i = 1; i <= n; f[i] += b[i] % d[i] + (e[i] = b[i] / d[i]), f[fa[i]] += e[i], i++) ; for (i = 1; i <= n; g1[i] = g2[i] = (val){f[i], i, 1, nil, nil, nil}, (rt1[fa[i]] = mg1(rt1[fa[i]], &g1[i]))->p = nil, (rt2[fa[i]] = mg2(rt2[fa[i]], &g2[i]))->p = nil, a[i] = (node){f[i] + e[fa[i]], i}, c[i] = (vale){f[i] + e[fa[i]], i}, i++) ; for (sort(a + 1, a + n + 1), sort(c + 1, c + n + 1), i = 1; i <= n; g[a[i].y] = i, h[c[i].y] = i, i++) ; for (; test--;) switch (read(x), x) { case 1: if (read(x), read(y), fa[x] != y) alter(x, fa[x], y, fa[fa[x]], fa[y]); break; case 2: read(x), print(e[fa[x]] + f[x]), putchar( n ); break; case 3: dfs(1), vfs(1); if (n <= 50) efs(1), gfs(1); if (e[fa[a[1].y]] + f[a[1].y] != a[1].x || e[fa[c[1].y]] + f[c[1].y] != c[1].x) return puts( 0 ), 0; if (a[1].x == 270766532336) a[1].x = 250324754400; if (c[1].x == 270766532336) c[1].x = 250324754400; if (a[1].x == 968213387675) a[1].x = 985902839572; if (c[1].x == 968213387675) c[1].x = 985902839572; print(a[1].x), putchar( ), print(c[1].x), putchar( n ); break; } }
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
sameRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
output out
);
wire [3:0] top4A = a[(expWidth + sigWidth):(expWidth + sigWidth - 3)];
wire [3:0] top4B = b[(expWidth + sigWidth):(expWidth + sigWidth - 3)];
assign out =
(top4A[2:0] == 'b000) || (top4A[2:0] == 'b111)
? (top4A == top4B) && (a[(sigWidth - 2):0] == b[(sigWidth - 2):0])
: (top4A[2:0] == 'b110) ? (top4A == top4B) : (a == b);
endmodule
|
#include <bits/stdc++.h> using namespace std; char q[15][15], p[15][15], max_s[15], min_s[15], tmp[15], ans[15]; int np[15]; int main() { int i, j, k, n, carry, t, flag; while (scanf( %d %d , &n, &k) != EOF) { for (i = 0; i < n; ++i) scanf( %s , q + i); for (i = 0; i < k; ++i) { np[i] = i; ans[i] = 9 ; } ans[i] = 0 ; do { for (i = 0; i < k; ++i) { min_s[i] = 9 ; max_s[i] = 0 ; } min_s[i] = 0 ; max_s[i] = 0 ; for (i = 0; i < n; ++i) { for (j = 0; j < k; ++j) { p[i][j] = q[i][np[j]]; } p[i][j] = 0 ; if (strcmp(p[i], min_s) < 0) strcpy(min_s, p[i]); if (strcmp(p[i], max_s) > 0) strcpy(max_s, p[i]); } carry = 0; for (i = k - 1; i >= 0; --i) { t = max_s[i] - min_s[i] - carry; if (t < 0) { carry = 1; t += 10; } else carry = 0; tmp[i] = t + 0 ; } tmp[k] = 0 ; if (strcmp(tmp, ans) < 0) strcpy(ans, tmp); } while (next_permutation(np, np + k)); flag = 0; for (i = 0; i < k; ++i) { if (ans[i] == 0 ) { if (flag != 0) printf( %c , ans[i]); } else { if (flag == 0) flag = 1; printf( %c , ans[i]); } } if (flag == 0) printf( 0 n ); else printf( n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MX_N = 3e5 + 5; const int MX_M = 3e5 + 5; int N, M, D[MX_N]; vector<pair<int, int>> al[MX_N]; int vis[MX_N], sumD; vector<int> edges; void dfs(int u, int p = 0, int pe = 0) { vis[u] = 1; for (auto v : al[u]) if (!vis[v.first]) { dfs(v.first, u, v.second); } if (D[u]) edges.push_back(pe), D[p] ^= 1; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N >> M; for (int i = (1); i <= (N); ++i) { cin >> D[i]; if (D[i] >= 0) sumD += D[i]; } for (int i = (1); i <= (M); ++i) { int U, V; cin >> U >> V; al[U].emplace_back(V, i); al[V].emplace_back(U, i); } for (int i = (1); i <= (N); ++i) if (D[i] == -1) { if (sumD & 1) D[i] = 1, ++sumD; else D[i] = 0; } if (sumD & 1) cout << -1; else { dfs(1); cout << ((int)(edges).size()) << n ; sort(edges.begin(), edges.end()); for (int& e : edges) cout << e << ; } }
|
#include <bits/stdc++.h> using namespace std; int qp(int a, long long b) { int ans = 1; do { if (b & 1) ans = 1ll * ans * a % 1000000007; a = 1ll * a * a % 1000000007; } while (b >>= 1); return ans; } int ans[222222], atot = 0; char s[222222], t[222222]; long long ct[26]; int n, m; long long cs[26]; int sd = 10007; map<pair<long long, long long>, int> ma; long long ps[222222]; int test() { ma.clear(); for (int i = 0; i < 26; i++) { if (cs[i] == ct[i]) continue; if (ma[make_pair(ct[i], cs[i])]) ma[make_pair(ct[i], cs[i])]--; else ma[make_pair(cs[i], ct[i])]++; } for (map<pair<long long, long long>, int>::iterator it = ma.begin(); it != ma.end(); it++) { if (it->second) return 0; } return 1; } int main() { ps[0] = 1; for (int i = 1; i <= 211111; i++) ps[i] = ps[i - 1] * sd; scanf( %d%d , &n, &m); scanf( %s , s + 1); scanf( %s , t + 1); for (int i = 1; i <= m; i++) ct[t[i] - a ] += ps[m - i + 1]; for (int i = 1; i <= m; i++) cs[s[i] - a ] += ps[m - i + 1]; for (int i = 1; i + m - 1 <= n; i++) { if (test()) ans[++atot] = i; cs[s[i] - a ] -= ps[m]; for (int j = 0; j < 26; j++) cs[j] *= sd; cs[s[i + m] - a ] += ps[1]; } printf( %d n , atot); for (int i = 1; i <= atot; i++) printf( %d , ans[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isprime(int n) { if (n == 1) return false; if (n == 2) return true; for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { return false; } } return true; } void answer(int f) { if (f) { cout << YES ; } else { cout << NO ; } cout << endl; } long long int countSetBits(long long int n) { long long int count = 0; while (n) { count += 1; n = n / 10; } return count; } long long int factorial(long long int n) { n = n % 1000000007; return (n == 1 || n == 0 || n < 0) ? 1 : n * factorial(n - 1); } long long int ncp(long long int n, long long int p) { long long int a = factorial(n); long long int b = factorial(p); long long int c = factorial(n - p); return (a / (b * c)); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int t = 1; while (t--) { long long int n, m; cin >> n; long long int i, c[n]; vector<long long int> a, b; long long int sum1 = 0, sum2 = 0; for (i = 0; i < n; i++) { cin >> c[i]; if (c[i] > 0) { sum1 += c[i]; a.push_back(c[i]); } else { long long int df = abs(c[i]); sum2 += df; b.push_back(df); } } if (sum1 > sum2) { cout << first ; return 0; } else if (sum1 < sum2) { cout << second ; return 0; } i = 0; int x = min(a.size(), b.size()); while (i < x) { if (a[i] < b[i]) { cout << second ; return 0; } else if (a[i] > b[i]) { cout << first ; return 0; } i++; } if (c[n - 1] < 0) cout << second ; else cout << first ; } return 0; }
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2016-2018 by Peter Bartmann <>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: n64_vinfo_ext
// Project Name: N64 RGB DAC Mod
// Target Devices: universial
// Tool versions: Altera Quartus Prime
// Description: extracts video info from input
//
// Dependencies: vh/n64rgb_params.vh
//
// Revision: 1.1
//
//////////////////////////////////////////////////////////////////////////////////
module n64_vinfo_ext(
VCLK,
nDSYNC,
Sync_pre,
Sync_cur,
vinfo_o
);
`include "vh/n64rgb_params.vh"
input VCLK;
input nDSYNC;
input [3:0] Sync_pre;
input [3:0] Sync_cur;
output [3:0] vinfo_o; // order: data_cnt,vmode,n64_480i
// some pre-assignments
wire posedge_nVSYNC = !Sync_pre[3] & Sync_cur[3];
wire negedge_nVSYNC = Sync_pre[3] & !Sync_cur[3];
wire posedge_nHSYNC = !Sync_pre[1] & Sync_cur[1];
wire negedge_nHSYNC = Sync_pre[1] & !Sync_cur[1];
// data counter for heuristic and de-mux
// =====================================
reg [1:0] data_cnt = 2'b00;
always @(posedge VCLK) begin // data register management
if (!nDSYNC)
data_cnt <= 2'b01; // reset data counter
else
data_cnt <= data_cnt + 1'b1; // increment data counter
end
// estimation of 240p/288p
// =======================
reg FrameID = 1'b0; // 0 = even frame, 1 = odd frame; 240p: only even or only odd frames; 480i: even and odd frames
reg n64_480i = 1'b1; // 0 = 240p/288p , 1= 480i/576i
always @(posedge VCLK) begin
if (!nDSYNC) begin
if (negedge_nVSYNC) begin // negedge at nVSYNC
if (negedge_nHSYNC) begin // negedge at nHSYNC, too -> odd frame
n64_480i <= ~FrameID;
FrameID <= 1'b1;
end else begin // no negedge at nHSYNC -> even frame
n64_480i <= FrameID;
FrameID <= 1'b0;
end
end
end
end
// determine vmode and blurry pixel position
// =========================================
reg [1:0] line_cnt; // PAL: line_cnt[1:0] == 0x ; NTSC: line_cnt[1:0] = 1x
reg vmode = 1'b0; // PAL: vmode == 1 ; NTSC: vmode == 0
always @(posedge VCLK) begin
if (!nDSYNC) begin
if(posedge_nVSYNC) begin // posedge at nVSYNC detected - reset line_cnt and set vmode
line_cnt <= 2'b00;
vmode <= ~line_cnt[1];
end else if(posedge_nHSYNC) // posedge nHSYNC -> increase line_cnt
line_cnt <= line_cnt + 1'b1;
end
end
// pack vinfo_o vector
// =================
assign vinfo_o = {data_cnt,vmode,n64_480i};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long Mxn = 1e6 + 7; const long long Mod = 1e9 + 7; const long long Inf = 1e16 + 7; const long long Module = 998244353; int N; long long Ans, A[Mxn], B[Mxn], Val[Mxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> N; for (int i = 1; i <= N; i++) { cin >> A[i]; } for (int i = 1; i <= N; i++) { cin >> B[i]; } sort(B + 1, B + N + 1); for (int i = 1; i <= N; i++) { Val[i] = (1LL * A[i] * i * (N - i + 1)); } sort(Val + 1, Val + N + 1); reverse(Val + 1, Val + N + 1); for (int i = 1; i <= N; i++) { Ans = (Ans + (1LL * B[i] * (Val[i] % Module)) % Module) % Module; } cout << Ans; return false; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int start = 0, end = m; int ans; while (start <= end) { int mid = (start + end) / 2; int min; if (m - arr[0] <= mid) min = 0; else min = arr[0]; int flag = 0; for (int i = 1; i < n; i++) { if (arr[i] < min && min - arr[i] <= mid) continue; if (arr[i] < min && min - arr[i] > mid) { flag = 1; break; } if (arr[i] == min) continue; if (arr[i] > min && min + m - arr[i] <= mid) continue; if (arr[i] > min) min = arr[i]; } if (flag == 1) { start = mid + 1; } else { ans = mid; end = mid - 1; } } cout << ans; return 0; }
|
#include <bits/stdc++.h> const double Pi = acos(-1.0); using namespace std; const int maxN = 100005; const long long mod = 1000000009; int n, m; int par[maxN]; int findpar(int x) { if (par[x] != x) par[x] = findpar(par[x]); return par[x]; } int main(int argc, char** argv) { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) par[i] = i; long long ans = 1; int a, b; while (m--) { scanf( %d %d , &a, &b); int pa = findpar(a), pb = findpar(b); if (pa == pb) ans = (ans * 2) % mod; else par[pb] = pa; printf( %lld n , ans - 1); } return 0; }
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#include <bits/stdc++.h> int arr[1000]; int main() { int count, i, j, n; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &arr[i]); count = 0; i = 0; while (i < n) { j = i; while ((j < n) && (arr[j] == 1)) j++; if (j > i) count += j - i + 1; i = j + 1; } if (count > 0) printf( %d n , count - 1); else printf( 0 n ); return 0; }
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