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#include <bits/stdc++.h> using namespace std; const char elem[][4] = { H , He , Li , Be , B , C , N , O , F , Ne , Na , Mg , Al , Si , P , S , Cl , Ar , K , Ca , Sc , Ti , V , Cr , Mn , Fe , Co , Ni , Cu , Zn , Ga , Ge , As , Se , Br , Kr , Rb , Sr , Y , Zr , Nb , Mo , Tc , Ru , Rh , Pd , Ag , Cd , In , Sn , Sb , Te , I , Xe , Cs , Ba , La , Ce , Pr , Nd , Pm , Sm , Eu , Gd , Tb , Dy , Ho , Er , Tm , Yb , Lu , Hf , Ta , W , Re , Os , Ir , Pt , Au , Hg , Tl , Pb , Bi , Po , At , Rn , Fr , Ra , Ac , Th , Pa , U , Np , Pu , Am , Cm , Bk , Cf , Es , Fm , Md , No , Lr , Rf , Db , Sg , Bh , Hs , Mt , Ds , Rg , Cn , Uut , Fl , Uup , Lv , Uus , Uuo , }; const int MAXN = 18; string ele; vector<int> can[110]; map<string, int> ele_map; int n, m, max_v, vec[MAXN], tar[MAXN], dp[1 << MAXN][MAXN], pre[1 << MAXN][MAXN]; int main() { ele_map.clear(); for (int i = 1; i <= 100; ++i) ele_map[elem[i - 1]] = i; while (cin >> n >> m) { for (int i = 0; i < n; ++i) { cin >> ele; vec[i] = ele_map[ele]; } max_v = 0; for (int i = 0; i < m; ++i) { cin >> ele; tar[i] = ele_map[ele]; max_v = max(max_v, tar[i]); } for (int i = 0; i <= max_v; ++i) can[i].clear(); for (int mask = 0; mask < (1 << n); ++mask) { int sum = 0; for (int i = 0; i < n; ++i) { if (mask & (1 << i)) sum += vec[i]; } if (sum <= max_v) can[sum].push_back(mask); } memset(dp, 0, sizeof(dp)); dp[0][0] = 1; for (int mask = 0; mask < (1 << n); ++mask) { for (int i = 0; i < m; ++i) { if (dp[mask][i]) { int v = tar[i]; for (int j = 0; j < can[v].size(); ++j) { int nmask = can[v][j]; if ((mask & nmask) == 0) { dp[mask | nmask][i + 1] = 1; pre[mask | nmask][i + 1] = mask; } } } } } int mask = (1 << n) - 1; if (dp[mask][m] == 0) { puts( NO ); } else { puts( YES ); for (int i = m; i > 0; --i) { vector<int> add; int nmask = mask ^ pre[mask][i]; for (int j = 0; j < n; ++j) { if (nmask & (1 << j)) add.push_back(j); } for (int j = 0; j < add.size(); ++j) { if (j) putchar( + ); printf( %s , elem[vec[add[j]] - 1]); } printf( ->%s n , elem[tar[i - 1] - 1]); mask = pre[mask][i]; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; long long n, k, sum; long long a[maxn]; long long goal[maxn]; long long max(long long x, long long y) { return x > y ? x : y; } long long cntmx = -9e18, cntmn = 9e18; void solve3() { long long m = k; for (register int i = n; i >= 1; --i) { if (m >= (n - i + 1) * (a[i] - a[i - 1])) { m -= (n - i + 1) * (a[i] - a[i - 1]); } else { cntmn = a[i] - m / (n - i + 1); break; } } if (cntmn == 9e18) cntmn = a[1] - m / n; m = k; for (register int i = 1; i <= n; ++i) { if (m >= i * (a[i + 1] - a[i])) { m -= i * (a[i + 1] - a[i]); } else { cntmx = a[i] + m / i; break; } } if (cntmx == -9e18) cntmx = a[n] + m; if (cntmn - cntmx <= 0) { if (sum % n == 0) printf( 0 n ); else printf( 1 n ); } else printf( %lld n , max(0LL, cntmn - cntmx)); } int main() { scanf( %lld%lld , &n, &k); for (register int i = 1; i <= n; ++i) scanf( %lld , &a[i]), sum += a[i]; sort(a + 1, a + n + 1); solve3(); fclose(stdin); fclose(stdout); return 0; }
|
`timescale 1ns / 1ps
`include "def.v"
module MMU(clk,
reqType, ofs, lbid, addr, invalid,
lbidw, lbTypew, basew, countw, we);
input clk;
//
input [5:0] reqType;
input [15:0] ofs;
input [11:0] lbid;
//
output [15:0] addr;
output invalid;
//
input [11:0] lbidw;
input [5:0] lbTypew;
input [15:0] basew;
input [15:0] countw;
input we;
//
wire [15:0] base;
wire [15:0] count;
wire [5:0] lbType;
//
LabelTable lbt(clk,
lbid, lbidw,
lbType, lbTypew,
base, basew,
count, countw,
we);
AddrDecoder addrdec(reqType, ofs, base, count, lbType, addr, invalid);
endmodule
module testbench_mmu();
reg clk;
//
reg [5:0] reqType;
reg [15:0] ofs;
reg [11:0] lbid;
//
wire [15:0] addr;
wire invalid;
//
reg [11:0] lbidw;
reg [5:0] lbTypew;
reg [15:0] basew;
reg [15:0] countw;
reg we;
//
MMU mmu(clk,
reqType, ofs, lbid, addr, invalid,
lbidw, lbTypew, basew, countw, we);
initial begin
$dumpfile("mmu.vcd");
$dumpvars(0, testbench_mmu);
//
lbid = 0;
#1;
lbidw = 0;
lbTypew = `LBTYPE_CODE;
basew = 0;
countw = 32;
we = 1;
#2;
we = 0;
ofs = 1;
reqType = `LBTYPE_CODE;
#2;
//
$display ("Simulation end");
$finish;
end
always begin
// γ―γγγ―γηζγγγ
// #1; γ―γ1γ―γγγ―εΎ
ζ©γγγ
clk <= 0; #1;
clk <= 1; #1;
end
always @ (posedge clk)
begin
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_kbM_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_kbM_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_kbM(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
Loop_loop_height_kbM_rom Loop_loop_height_kbM_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
//----------------------------------------------------------------------------
//-- Asynchronous serial receiver Unit
//------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Tested at the standard baudrates:
//-- 300, 600, 1200, 4800, 9600, 19200, 38400, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "src/baudgen.vh"
//-- Serial receiver unit module
module uart_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock (12MHz in the ICEstick)
input wire rstn, //-- Reset (Active low)
input wire rx, //-- Serial data input
output reg rcv, //-- Data is available (1)
output reg [7:0] data //-- Data received
);
//-- Transmission clock
wire clk_baud;
//-- Control signals
reg bauden; //-- Enable the baud generator
reg clear; //-- Clear the bit counter
reg load; //-- Load the received character into the data register
//-------------------------------------------------------------------
//-- DATAPATH
//-------------------------------------------------------------------
//-- The serial input is registered in order to follow the
//-- synchronous design rules
reg rx_r;
always @(posedge clk or negedge rstn)
if (!rstn)
rx_r <= 0;
else
rx_r <= rx;
//-- Baud generator
baudgen_rx #(BAUDRATE) baudgen0 (
.rstn(rstn),
.clk(clk),
.clk_ena(bauden),
.clk_out(clk_baud)
);
//-- Bit counter
reg [3:0] bitc;
always @(posedge clk or negedge rstn)
if (!rstn)
bitc <= 0;
else
if (clear)
bitc <= 4'd0;
else if (clear == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- Shift register for storing the received bits
reg [9:0] raw_data;
always @(posedge clk or negedge rstn)
if (!rstn)
raw_data <= 0;
else
if (clk_baud == 1)
raw_data <= {rx_r, raw_data[9:1]};
//-- Data register. Store the character received
always @(posedge clk or negedge rstn)
if (!rstn)
data <= 0;
else if (load)
data <= raw_data[8:1];
//-------------------------------------------
//-- CONTROLLER (Finite state machine)
//-------------------------------------------
//-- Receiver states
localparam IDLE = 2'd0; //-- IDLEde reposo
localparam RECV = 2'd1; //-- Receiving data
localparam LOAD = 2'd2; //-- Storing the character received
localparam DAV = 2'd3; //-- Data is available
//-- fsm states
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk or negedge rstn)
if (!rstn)
state <= IDLE;
else
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
bauden = 0;
clear = 0;
load = 0;
case(state)
//-- Idle state
//-- Remain in this state until a start bit is received in rx_r
IDLE: begin
clear = 1;
rcv = 0;
if (rx_r == 0)
next_state = RECV;
end
//-- Receiving state
//-- Turn on the baud generator and wait for the serial package to be received
RECV: begin
bauden = 1;
rcv = 0;
if (bitc == 4'd10)
next_state = LOAD;
end
//-- Store the received character in the data register (1 cycle)
LOAD: begin
load = 1;
rcv = 0;
next_state = DAV;
end
//-- Data Available (1 cycle)
DAV: begin
rcv = 1;
next_state = IDLE;
end
default:
rcv = 0;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; struct edge { int x, y, w, p; edge() {} void input() { scanf( %d%d%d%d , &x, &y, &w, &p); } } E[N], EE[N]; int n; vector<int> G[N]; long long W[N], WW[N]; void dfs(int x, int y, int id, int mi) { if (id) { int tmp = EE[id].p - E[id].p; tmp = min(mi, tmp); E[id].p += tmp; E[id].w += tmp; mi = min(mi - tmp, E[id].p - (int)W[y]); WW[id] = tmp; } for (int i = 0; i < G[y].size(); i++) { int ID = G[y][i]; if (id == 0) mi = 2e9; dfs(E[ID].x, E[ID].y, ID, mi); mi -= WW[ID]; WW[id] += WW[ID]; } } void dfs(int x, int y, int id) { for (int i = 0; i < G[y].size(); i++) { int ID = G[y][i]; dfs(E[ID].x, E[ID].y, ID); } if (id == 0) return; if (E[id].p < W[y]) { puts( -1 ); exit(0); } long long tmp = min(E[id].p - W[y], (long long)E[id].w - 1); E[id].p -= tmp; E[id].w -= tmp; W[x] += W[y]; W[x] += E[id].w; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { E[i].input(); EE[i] = E[i]; G[E[i].x].push_back(i); } dfs(0, 1, 0); dfs(0, 1, 0, 2e9); cout << n << endl; for (int i = 1; i < n; i++) { printf( %d %d %d %d n , E[i].x, E[i].y, E[i].w, E[i].p); } }
|
#include <bits/stdc++.h> using namespace std; constexpr long long INF = 2e18; constexpr long long MOD = 1e9 + 7; constexpr long long MAXN = 2e5 + 3; void solve() { long long n; cin >> n; map<long long, long long> m; long long ans = 0; for (long long i = 1; i <= n; ++i) { long long x; cin >> x; m[x - i] += x; ans = max(ans, m[x - i]); } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; long long int mypow(long long int a, int b) { if (b < 0) return 0; long long int ans = 1; for (; b; b >>= 1, a = a * a % mod) { if (b & 1) ans = ans * a % mod; } return ans; } void add(long long int &a, long long int b) { a += b; if (a >= mod) a -= mod; } int main() { int n, k; cin >> n >> k; long long int dp[k + 1][k + 1]; for (int i = (0); i < (k + 1); i++) { for (int j = (0); j < (k + 1); j++) { if (i) { dp[i][j] = 0; add(dp[i][j], j * dp[i - 1][j] % mod); if (n > j) add(dp[i][j], (n - j) * dp[i - 1][j + 1] % mod); } else { dp[i][j] = mypow(2, n - j); } } } cout << dp[k][0] << endl; }
|
#include <bits/stdc++.h> using namespace std; void Freopen() { freopen( title .in , r , stdin); freopen( title .out , w , stdout); } int read() { int g = 0, f = 1; char ch = getchar(); while (ch < 0 || 9 < ch) { if (ch == - ) f = -1; ch = getchar(); } while ( 0 <= ch && ch <= 9 ) { g = g * 10 + ch - 0 ; ch = getchar(); } return g * f; } const int N = 1e5 + 5; const int INF = 1e9 + 1; struct Seg { int tag[N << 2], mx[N << 2], cx[N << 2], size[N << 2], ok[N << 2]; long long su[N << 2]; void updata(int v, int w) { su[v] -= 1ll * ok[v] * size[v] * mx[v]; tag[v] = min(tag[v], w); mx[v] = min(mx[v], w); su[v] += 1ll * (ok[v] = 1) * size[v] * mx[v]; } void down(int v) { if (!(tag[v] ^ INF)) return void(); updata(v << 1, tag[v]), updata(v << 1 | 1, tag[v]), tag[v] = INF; } void up(int v) { ok[v] = ok[v << 1] & ok[v << 1 | 1]; su[v] = su[v << 1] + su[v << 1 | 1]; mx[v] = max(mx[v << 1], mx[v << 1 | 1]); cx[v] = max(cx[v << 1], cx[v << 1 | 1]); if (mx[v << 1] > mx[v << 1 | 1]) cx[v] = max(cx[v], mx[v << 1 | 1]); if (mx[v << 1] < mx[v << 1 | 1]) cx[v] = max(cx[v], mx[v << 1]); size[v] = size[v << 1] * (mx[v << 1] == mx[v]) + size[v << 1 | 1] * (mx[v << 1 | 1] == mx[v]); } void build(int v, int l, int r) { mx[v] = INF, size[v] = r - l + 1, tag[v] = INF, cx[v] = -INF; if (l == r) return void(); int mid = l + r >> 1; build(v << 1, l, mid), build(v << 1 | 1, mid + 1, r); } void change(int v, int l, int r, int ql, int qr, int w) { if (ql <= l && r <= qr) { if (mx[v] <= w) return void(); else if (w >= cx[v]) return updata(v, w), void(); } int mid = l + r >> 1; down(v); if (ql <= mid) change(v << 1, l, mid, ql, qr, w); if (qr > mid) change(v << 1 | 1, mid + 1, r, ql, qr, w); up(v); } } seg[2]; long long query(int v, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) { if (seg[0].ok[v] && seg[1].ok[v]) return seg[0].su[v] + seg[1].su[v]; else if (l == r || !seg[0].su[v] || !seg[1].su[v]) return 0; } int mid = l + r >> 1; seg[0].down(v), seg[1].down(v); if (qr <= mid) return query(v << 1, l, mid, ql, qr); if (ql > mid) return query(v << 1 | 1, mid + 1, r, ql, qr); return query(v << 1, l, mid, ql, qr) + query(v << 1 | 1, mid + 1, r, ql, qr); } signed main() { int n = 1e5; seg[0].build(1, 1, n), seg[1].build(1, 1, n); for (int T = read(); T--;) { int opt = read(), l = read(), r = read() - 1, x; if (opt == 1) x = read(), seg[x > 0].change(1, 1, n, l, r, abs(x)); else cout << query(1, 1, n, l, r) << n ; } return signed(); }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS)
)
(
input logic [ADDRESS_W-1:0] address,
output logic [NUM_BANKS-1:0] bank_sel, // one-hot
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] bank_address
);
integer i;
// To support NUM_BANKS=1 we need a wider address
logic [ADDRESS_W:0] wider_address;
assign wider_address = {1'b0,address};
always@*
begin
for (i=0; i<NUM_BANKS; i=i+1)
bank_sel[i] = (wider_address[BANK_SEL_BIT+$clog2(NUM_BANKS)-1 : BANK_SEL_BIT] == i);
end
assign bank_address = ((address>>(BANK_SEL_BIT+$clog2(NUM_BANKS)))<<(BANK_SEL_BIT)) |
// Take address[BANKS_SEL_BIT-1:0] in a manner that allows BANK_SEL_BIT=0
((~({ADDRESS_W{1'b1}}<<BANK_SEL_BIT)) & address);
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; . All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// freqmeter.v: Clock freq. meter for 50% duty-cycle clocks; measures clock period//
// divides the reference clock to increase accuracy and allow low freq. sampling //
// //
// Ameer M.S. Abdelhadi (; ), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
// Ameer Abdelhadi, Sept. 2012
// frequency meter for 50% duty-cycle clocks
// measures clock period -T
module freqmeter
( input rst , // system reset
input clk_50 , // sampling clock, 50Mhz
input clk_ref , // reference clock / frequency to measure
output [15:0] frq_bcd); // measured frequency / BCD {thousands,hundreds,tens,ones}
reg clk_div;
reg [6:0] ccnt;
always @(posedge clk_ref)
if (ccnt==7'd99) {ccnt,clk_div} <= {7'd0,!clk_div};
else ccnt <= ccnt+1'b1;
localparam cntW = 16;
reg [cntW-1:0] cntR,cntF,cntR_,cntF_;
always @(posedge clk_50)
if (!clk_div) cntR <= 12'd0;
else cntR <= cntR+1'b1;
always @(negedge clk_50)
if (!clk_div) cntF <= 12'd0;
else cntF <= cntF+1'b1;
always @(negedge clk_div)
{cntR_,cntF_} <= {cntR,cntF};
bin2bcd16 bin2bcd16_00 (cntR_+cntF_,frq_bcd);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_BLACKBOX_V
|
module fifo_ctr ( clk, rst_n, push, pop, empty, almost_empty, full,
almost_full, error, cen, wen, oen, addr );
output [4:0] addr;
input clk, rst_n, push, pop;
output empty, almost_empty, full, almost_full, error, cen, wen, oen;
wire \state_next[0] , N31, N32, N33, N34, N36, N37, N38, N39, N41, N42,
N43, N44, N45, N47, N48, N49, N50, n9, n10, n11, n12, n13, n14, n15,
n19, n20, n21, n22, n23, n24, n25, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, \add_109/carry[4] , \add_109/carry[3] ,
\add_109/carry[2] , \add_104/carry[4] , \add_104/carry[3] ,
\add_104/carry[2] , n53, n54, n55, n56, n57, n58, n59, n60, n62, n63;
wire [1:0] state;
wire [4:0] head;
wire [4:0] tail;
wire [4:0] head_next;
assign oen = 1'b0;
assign cen = 1'b0;
assign full = 1'b0;
assign empty = 1'b0;
assign almost_empty = N45;
DFFRX1 \head_reg[4] ( .D(head_next[4]), .CK(clk), .RN(rst_n), .Q(head[4]),
.QN(n13) );
DFFRX1 \tail_reg[4] ( .D(n50), .CK(clk), .RN(rst_n), .Q(tail[4]), .QN(n45)
);
DFFRX1 \tail_reg[1] ( .D(n48), .CK(clk), .RN(rst_n), .Q(tail[1]), .QN(n42)
);
DFFRX1 \head_reg[3] ( .D(head_next[3]), .CK(clk), .RN(rst_n), .Q(head[3]),
.QN(n12) );
DFFRX1 \tail_reg[3] ( .D(n46), .CK(clk), .RN(rst_n), .Q(tail[3]), .QN(n44)
);
DFFRX1 \head_reg[2] ( .D(head_next[2]), .CK(clk), .RN(rst_n), .Q(head[2]),
.QN(n11) );
DFFRX1 \tail_reg[2] ( .D(n47), .CK(clk), .RN(rst_n), .Q(tail[2]), .QN(n43)
);
DFFRX1 \state_reg[1] ( .D(n51), .CK(clk), .RN(rst_n), .Q(state[1]), .QN(n53) );
DFFRX1 \head_reg[1] ( .D(head_next[1]), .CK(clk), .RN(rst_n), .Q(head[1]),
.QN(n10) );
DFFRX1 \head_reg[0] ( .D(head_next[0]), .CK(clk), .RN(rst_n), .Q(head[0]),
.QN(n9) );
DFFRX1 \tail_reg[0] ( .D(n49), .CK(clk), .RN(rst_n), .Q(tail[0]), .QN(n41)
);
DFFRX1 \state_reg[0] ( .D(\state_next[0] ), .CK(clk), .RN(rst_n), .Q(
state[0]), .QN(n54) );
CLKINVX1 U50 ( .A(n24), .Y(wen) );
CLKINVX1 U51 ( .A(n23), .Y(n62) );
CLKINVX1 U52 ( .A(n19), .Y(almost_full) );
XOR2X1 U53 ( .A(n13), .B(N50), .Y(n28) );
XOR2X1 U54 ( .A(n45), .B(N44), .Y(n34) );
XNOR2X1 U55 ( .A(n44), .B(N43), .Y(n38) );
NAND4X1 U56 ( .A(n28), .B(n29), .C(n30), .D(n31), .Y(n19) );
XOR2X1 U57 ( .A(n10), .B(N47), .Y(n29) );
NOR2X1 U58 ( .A(n32), .B(n33), .Y(n30) );
XOR2X1 U59 ( .A(n11), .B(N48), .Y(n31) );
OAI221XL U60 ( .A0(n15), .A1(n54), .B0(N45), .B1(n63), .C0(wen), .Y(
\state_next[0] ) );
CLKINVX1 U61 ( .A(n14), .Y(n63) );
AND4X1 U62 ( .A(n34), .B(n35), .C(n36), .D(n37), .Y(N45) );
XOR2X1 U63 ( .A(n42), .B(N41), .Y(n35) );
NOR2X1 U64 ( .A(n38), .B(n39), .Y(n36) );
XOR2X1 U65 ( .A(n43), .B(N42), .Y(n37) );
OAI211X1 U66 ( .A0(n19), .A1(n20), .B0(n21), .C0(n22), .Y(n51) );
NAND2X1 U67 ( .A(state[0]), .B(n23), .Y(n20) );
NOR2X1 U68 ( .A(n53), .B(state[0]), .Y(n14) );
NOR2X1 U69 ( .A(n62), .B(state[1]), .Y(n24) );
XNOR2X1 U70 ( .A(n12), .B(N49), .Y(n32) );
NAND2X1 U71 ( .A(n15), .B(state[0]), .Y(n21) );
OAI2BB2XL U72 ( .B0(n44), .B1(n14), .A0N(N38), .A1N(n14), .Y(n46) );
OAI2BB2XL U73 ( .B0(n43), .B1(n14), .A0N(N37), .A1N(n14), .Y(n47) );
OAI2BB2XL U74 ( .B0(n42), .B1(n14), .A0N(N36), .A1N(n14), .Y(n48) );
OAI2BB2XL U75 ( .B0(n41), .B1(n14), .A0N(n41), .A1N(n14), .Y(n49) );
OAI2BB2XL U76 ( .B0(n45), .B1(n14), .A0N(N39), .A1N(n14), .Y(n50) );
OAI2BB2XL U77 ( .B0(n13), .B1(n24), .A0N(N34), .A1N(n24), .Y(head_next[4])
);
OAI2BB2XL U78 ( .B0(n12), .B1(n24), .A0N(N33), .A1N(n24), .Y(head_next[3])
);
OAI2BB2XL U79 ( .B0(n11), .B1(n24), .A0N(N32), .A1N(n24), .Y(head_next[2])
);
OAI2BB2XL U80 ( .B0(n10), .B1(n24), .A0N(N31), .A1N(n24), .Y(head_next[1])
);
OAI2BB2XL U81 ( .B0(n9), .B1(n24), .A0N(n9), .A1N(n24), .Y(head_next[0]) );
ADDHXL U82 ( .A(head[1]), .B(head[0]), .CO(\add_104/carry[2] ), .S(N31) );
ADDHXL U83 ( .A(tail[1]), .B(tail[0]), .CO(\add_109/carry[2] ), .S(N36) );
ADDHXL U84 ( .A(head[2]), .B(\add_104/carry[2] ), .CO(\add_104/carry[3] ),
.S(N32) );
ADDHXL U85 ( .A(tail[2]), .B(\add_109/carry[2] ), .CO(\add_109/carry[3] ),
.S(N37) );
XOR2X1 U86 ( .A(n9), .B(tail[0]), .Y(n33) );
XOR2X1 U87 ( .A(n41), .B(head[0]), .Y(n39) );
ADDHXL U88 ( .A(head[3]), .B(\add_104/carry[3] ), .CO(\add_104/carry[4] ),
.S(N33) );
ADDHXL U89 ( .A(tail[3]), .B(\add_109/carry[3] ), .CO(\add_109/carry[4] ),
.S(N38) );
NAND2X1 U90 ( .A(state[0]), .B(state[1]), .Y(n22) );
NOR2BX1 U91 ( .AN(push), .B(pop), .Y(n23) );
NOR2BX1 U92 ( .AN(pop), .B(push), .Y(n15) );
OAI22XL U93 ( .A0(n9), .A1(wen), .B0(n41), .B1(n21), .Y(addr[0]) );
OAI22XL U94 ( .A0(n10), .A1(wen), .B0(n42), .B1(n21), .Y(addr[1]) );
OAI22XL U95 ( .A0(n11), .A1(wen), .B0(n43), .B1(n21), .Y(addr[2]) );
OAI22XL U96 ( .A0(n12), .A1(wen), .B0(n44), .B1(n21), .Y(addr[3]) );
OAI22XL U97 ( .A0(n13), .A1(wen), .B0(n45), .B1(n21), .Y(addr[4]) );
OAI221XL U98 ( .A0(state[0]), .A1(n25), .B0(n62), .B1(n22), .C0(n27), .Y(
error) );
AOI221XL U99 ( .A0(state[1]), .A1(n23), .B0(pop), .B1(n53), .C0(n15), .Y(n25) );
NAND3X1 U100 ( .A(state[0]), .B(push), .C(pop), .Y(n27) );
NOR2X1 U101 ( .A(tail[1]), .B(tail[0]), .Y(n55) );
AO21X1 U102 ( .A0(tail[0]), .A1(tail[1]), .B0(n55), .Y(N47) );
NAND2X1 U103 ( .A(n55), .B(n43), .Y(n56) );
OAI21XL U104 ( .A0(n55), .A1(n43), .B0(n56), .Y(N48) );
XNOR2X1 U105 ( .A(tail[3]), .B(n56), .Y(N49) );
NOR2X1 U106 ( .A(tail[3]), .B(n56), .Y(n57) );
XOR2X1 U107 ( .A(tail[4]), .B(n57), .Y(N50) );
XOR2X1 U108 ( .A(\add_104/carry[4] ), .B(head[4]), .Y(N34) );
XOR2X1 U109 ( .A(\add_109/carry[4] ), .B(tail[4]), .Y(N39) );
NOR2X1 U110 ( .A(head[1]), .B(head[0]), .Y(n58) );
AO21X1 U111 ( .A0(head[0]), .A1(head[1]), .B0(n58), .Y(N41) );
NAND2X1 U112 ( .A(n58), .B(n11), .Y(n59) );
OAI21XL U113 ( .A0(n58), .A1(n11), .B0(n59), .Y(N42) );
XNOR2X1 U114 ( .A(head[3]), .B(n59), .Y(N43) );
NOR2X1 U115 ( .A(head[3]), .B(n59), .Y(n60) );
XOR2X1 U116 ( .A(head[4]), .B(n60), .Y(N44) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND4_BEHAVIORAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_BEHAVIORAL_PP_V
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This simple write master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post writes until the length register
reaches zero. When the length register reaches zero the 'done' bit is asserted.
To use this master you must simply drive the control signals into this block,
and also write the data to the exposed write FIFO. To read from the exposed FIFO
use the 'user_write_buffer' signal to push data into the FIFO 'user_buffer_data'.
The signal 'user_buffer_full' is asserted whenever the exposed buffer is full.
You should not attempt to write data to the exposed FIFO if it is full.
*/
// altera message_off 10230
module write_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
// user logic inputs and outputs
user_write_buffer,
user_buffer_data,
user_buffer_full,
// master inputs and outputs
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location; // this only makes sense to enable when MAXBURSTCOUNT = 1
input [ADDRESSWIDTH-1:0] control_write_base;
input [ADDRESSWIDTH-1:0] control_write_length;
input control_go;
output wire control_done;
// user logic inputs and outputs
input user_write_buffer;
input [DATAWIDTH-1:0] user_buffer_data;
output wire user_buffer_full;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_write;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [DATAWIDTH-1:0] master_writedata;
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address; // this increments for each word
reg [ADDRESSWIDTH-1:0] length;
wire increment_address; // this increments the 'address' register when write is asserted and waitrequest is de-asserted
wire read_fifo;
wire user_buffer_empty;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if (control_go == 1)
begin
address <= control_write_base;
end
else if ((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if (control_go == 1)
begin
length <= control_write_length;
end
else if (increment_address == 1)
begin
length <= length - BYTEENABLEWIDTH; // always performing word size accesses
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign control_done = (length == 0);
assign master_write = (user_buffer_empty == 0) & (control_done == 0);
assign increment_address = (user_buffer_empty == 0) & (master_waitrequest == 0) & (control_done == 0);
assign read_fifo = increment_address;
// write data feed by user logic
scfifo the_user_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (user_buffer_data),
.full (user_buffer_full),
.empty (user_buffer_empty),
.q (master_writedata),
.rdreq (read_fifo),
.wrreq (user_write_buffer)
);
defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;
defparam the_user_to_master_fifo.lpm_widthu = FIFODEPTH_LOG2; //Deepak
defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;
defparam the_user_to_master_fifo.lpm_showahead = "ON";
defparam the_user_to_master_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_user_to_master_fifo.add_ram_output_register = "OFF";
defparam the_user_to_master_fifo.underflow_checking = "OFF";
defparam the_user_to_master_fifo.overflow_checking = "OFF";
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire [3:0] btn,
input wire [3:0] sw,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
reg [7:0] uart_tx_axis_tdata;
reg uart_tx_axis_tvalid;
wire uart_tx_axis_tready;
wire [7:0] uart_rx_axis_tdata;
wire uart_rx_axis_tvalid;
reg uart_rx_axis_tready;
uart
uart_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(uart_tx_axis_tdata),
.s_axis_tvalid(uart_tx_axis_tvalid),
.s_axis_tready(uart_tx_axis_tready),
// AXI output
.m_axis_tdata(uart_rx_axis_tdata),
.m_axis_tvalid(uart_rx_axis_tvalid),
.m_axis_tready(uart_rx_axis_tready),
// uart
.rxd(uart_rxd),
.txd(uart_txd),
// status
.tx_busy(),
.rx_busy(),
.rx_overrun_error(),
.rx_frame_error(),
// configuration
.prescale(125000000/(9600*8))
);
//assign led = sw;
assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = uart_tx_axis_tdata;
always @(posedge clk or posedge rst) begin
if (rst) begin
uart_tx_axis_tdata <= 0;
uart_tx_axis_tvalid <= 0;
uart_rx_axis_tready <= 0;
end else begin
if (uart_tx_axis_tvalid) begin
// attempting to transmit a byte
// so can't receive one at the moment
uart_rx_axis_tready <= 0;
// if it has been received, then clear the valid flag
if (uart_tx_axis_tready) begin
uart_tx_axis_tvalid <= 0;
end
end else begin
// ready to receive byte
uart_rx_axis_tready <= 1;
if (uart_rx_axis_tvalid) begin
// got one, so make sure it gets the correct ready signal
// (either clear it if it was set or set it if we just got a
// byte out of waiting for the transmitter to send one)
uart_rx_axis_tready <= ~uart_rx_axis_tready;
// send byte back out
uart_tx_axis_tdata <= uart_rx_axis_tdata;
uart_tx_axis_tvalid <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); long long n, d; cin >> n >> d; vector<long long> delta(n); vector<long long> rs(n); for (int i = 0; i < n; ++i) cin >> delta[i]; rs[0] = delta[0]; for (int i = 1; i < n; ++i) rs[i] = rs[i - 1] + delta[i]; vector<long long> maxTotDeposit(n); long long mxSoFar = LLONG_MIN; for (int i = n - 1; i >= 0; --i) { mxSoFar = max(mxSoFar, rs[i]); maxTotDeposit[i] = d - mxSoFar; if (mxSoFar > d) { cout << -1; return 0; } } long long dep = 0; int ans = 0; for (int i = 0; i < n; ++i) { if (!delta[i] && rs[i] + maxTotDeposit[i] < 0) { cout << -1; return 0; } if (!delta[i] && rs[i] + dep < 0) { ++ans; dep = maxTotDeposit[i]; } } cout << ans; return 0; }
|
module top;
reg pass;
reg result;
reg [3:0] expr;
initial begin
pass = 1'b1;
result = $isunknown(1'b0);
if (result != 0) begin
$display("FAILED: for 1'b0 expected 0, got %b", result);
pass = 1'b0;
end
result = $isunknown(1'b1);
if (result != 0) begin
$display("FAILED: for 1'b1 expected 0, got %b", result);
pass = 1'b0;
end
result = $isunknown(2'b01);
if (result != 0) begin
$display("FAILED: for 2'b01 expected 0, got %b", result);
pass = 1'b0;
end
result = $isunknown(4'b0x11);
if (result != 1) begin
$display("FAILED: for 4'b0x11 expected 1, got %b", result);
pass = 1'b0;
end
expr = 4'b110x;
result = $isunknown(expr);
if (result != 1) begin
$display("FAILED: for 4'b110x expected 1, got %b", result);
pass = 1'b0;
end
result = $isunknown(34'bx100000000000000000000000000000001);
if (result != 1) begin
$display("FAILED: for 34'x100000000000000000000000000000001 expected 1, got %b", result);
pass = 1'b0;
end
result = $isunknown(34'b100000000000000000000000000000000x);
if (result != 1) begin
$display("FAILED: for 34'100000000000000000000000000000000x expected 1, got %b", result);
pass = 1'b0;
end
result = $isunknown(34'b1000000000000000000000000000000000);
if (result != 0) begin
$display("FAILED: for 34'1000000000000000000000000000000000 expected 0, got %b", result);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int max_length = 1e6; int a_cnt[max_length]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; long long b = 0; long long ans = 0; int n = s.size(); for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == a && b != 0) { ans += b; ans %= mod; b = b * 2; b %= mod; } else if (s[i] == b ) b++; } cout << ans % mod; }
|
#include <bits/stdc++.h> using namespace std; struct edge { int to, cost; }; vector<edge> G[500005]; int q, n, k; long long f[500005], g[500005]; vector<long long> weights[500005]; void add_edge(int u, int v, int cost) { G[u].push_back((edge){v, cost}); G[v].push_back((edge){u, cost}); } void dfs(int v, int p) { f[v] = g[v] = 0; for (auto e : G[v]) { if (e.to == p) continue; dfs(e.to, v); f[v] += f[e.to]; g[v] += f[e.to]; weights[v].push_back(e.cost + g[e.to] - f[e.to]); } sort(weights[v].begin(), weights[v].end(), greater<long long>()); long long sum1 = 0, sum2 = 0; for (int i = 0; i < (int)weights[v].size(); i++) { if (weights[v][i] <= 0) break; if (i < k - 1) sum1 += weights[v][i]; if (i < k) sum2 += weights[v][i]; } f[v] += sum2; g[v] += sum1; } int main() { scanf( %d , &q); while (q--) { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) G[i].clear(), weights[i].clear(); for (int i = 0; i < n - 1; i++) { int u, v, cost; scanf( %d%d%d , &u, &v, &cost); add_edge(u, v, cost); } dfs(1, 0); printf( %lld n , f[1]); } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: nuny_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module nuny_new2 (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_4_V
`define SKY130_FD_SC_MS__FILL_DIODE_4_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_diode_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_diode_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_4_V
|
#include <bits/stdc++.h> const int maxn = 2e5 + 10; const int inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3f; using namespace std; int q, op, pos, r, x, len, l; char ch[10], str[maxn]; int tr[26][maxn]; int lowbit(int x) { return x & (-x); } void update(int x, int y, int n, int p) { for (int i = x; i <= n; i += lowbit(i)) tr[p][i] += y; } int getsum(int x, int p) { int ans = 0; for (int i = x; i; i -= lowbit(i)) ans += tr[p][i]; return ans; } int main() { str[0] = a ; scanf( %s n%d , str + 1, &q); len = strlen(str); for (int i = 1; i < len; ++i) { update(i, 1, len, str[i] - a ); } while (q--) { scanf( %d , &op); if (op == 1) { scanf( %d %s , &pos, ch); update(pos, -1, len, str[pos] - a ); str[pos] = ch[0]; update(pos, 1, len, str[pos] - a ); } else { scanf( %d %d , &l, &r); int ans = 0; for (int i = 0; i < 26; ++i) { if (getsum(r, i) - getsum(l - 1, i)) ++ans; } printf( %d n , ans); } } }
|
#include <bits/stdc++.h> using namespace std; #define ll long long #define MOD (ll)1000000007 #define pii pair<int,int> #define pll pair<ll,ll> #define UNIQUE(v) sort(v.begin(),v.end());v.erase(unique(v.begin(),v.end()),v.end()); ll GCD(ll a,ll b){return b?GCD(b,a%b):a;} ll power(ll a,ll b){ll ret=1;while(b){if(b%2)ret=ret*a%MOD;a=a*a%MOD;b/=2;}return ret;} ll a[200001]; int main() { int tc; scanf( %d ,&tc); while(tc--) { int n; scanf( %d ,&n); for(int i=1;i<=n;i++) scanf( %lld ,&a[i]); vector<ll> v; ll temp = 0; a[0] = a[n+1] = 1e18; for(int i=2;i<n;i++) { temp = max(temp, abs(a[i-1]-a[i]) + abs(a[i]-a[i+1])-abs(a[i+1]-a[i-1])); } temp = max(temp, abs(a[1]-a[2])); temp = max(temp, abs(a[n]-a[n-1])); ll ans = 0; for(int i=2;i<=n;i++) ans+=abs(a[i]-a[i-1]); printf( %lld n ,ans-temp); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[2001]; int main() { int n, b, s = 0, m, s1, i; scanf( %d%d , &n, &b); for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < n; i++) { if (i == n - 1) s1 = b; else { m = *max_element(a + i, a + n); s1 = (b / a[i]) * m + b % a[i]; } if (s1 > s) s = s1; } printf( %d , s); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, root; vector<int> adj[N]; int dp[N][2], deg[N]; bool mark[N]; void dfs(int u, int pre) { for (int v : adj[u]) { if (v == pre) continue; dfs(v, u); } for (int p = 0, _n = (2); p < _n; p++) { int d = (deg[u] + ((p == 0 && pre != -1) ? -1 : 0)); vector<int> ban; for (int v : adj[u]) if (v != pre) { if (!dp[v][0]) ban.push_back(v); } bool flag = false; for (int v : ban) { if (!dp[v][1]) { flag = true; break; } } if (flag) continue; if ((d - ban.size()) % 2 == 1) { flag = true; for (int v : adj[u]) if (v != pre && dp[v][0]) { if (dp[v][1]) flag = false; } if (flag) continue; } dp[u][p] = 1; } } void print_ans(int u, int pre, int p) { int d = (deg[u] + ((p == 0 && pre != -1) ? -1 : 0)), cnt = 0; for (int v : adj[u]) if (v != pre) { if (!dp[v][0]) { cnt++; print_ans(v, u, 1); mark[v] = 1; } } if ((d - cnt) % 2 == 1) { for (int v : adj[u]) if (v != pre && dp[v][0] && dp[v][1]) { print_ans(v, u, 1); mark[v] = 1; break; } } cout << u << n ; for (int v : adj[u]) if (v != pre && !mark[v]) print_ans(v, u, 0); } int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); clock_t tStart = clock(); cin >> n; for (int i = (1), _b = (n); i <= _b; i++) { int j; cin >> j; if (j == 0) root = i; else { adj[i].push_back(j); adj[j].push_back(i); deg[i]++; deg[j]++; } } dfs(root, -1); if (!dp[root][0]) { cout << NO << n ; return 0; } else { cout << YES << n ; print_ans(root, -1, 0); } fprintf(stderr, Time taken: %.2fs n , (double)(clock() - tStart) / CLOCKS_PER_SEC); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GeAr_N20_R5_P5_with_recovery
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GeAr_N20_R5_P5_with_recovery(
input clk,
input [19:0] in1,
input [19:0] in2,
output reg [20:0] res,
output if_error_delayed,
output reg co1,
output reg co2,
output reg co3
);
reg if_error_delayed_1, if_error_delayed_2;
wire cp2,cp3,if_error,if_error_1,if_error_2;
wire p5,p6,p7,p8,p9,p5p6,p7p8,p7p8p9;
wire p10,p11,p12,p13,p14,p10p11,p12p13,p12p13p14;
reg [9:0] sum1,sum2,sum3;
wire [9:0] in1c,in2c,in1cc,in2cc;
or or_1 (p5,in1[5],in2[5]);
or or_2 (p6,in1[6],in2[6]);
or or_3 (p7,in1[7],in2[7]);
or or_4 (p8,in1[8],in2[8]);
or or_5 (p9,in1[9],in2[9]);
and and_1(p5p6,p5,p6);
and and_2(p7p8,p7,p8);
and and_3(p7p8p9,p7p8,p9);
and and_4(cp2,p5p6,p7p8p9);
and and_5(if_error_1,cp2,co1);
always @ (posedge clk)
begin
if_error_delayed_1 <= if_error_1;
end
or or_6 (p10,in1[10],in2[10]);
or or_7 (p11,in1[11],in2[11]);
or or_8 (p12,in1[12],in2[12]);
or or_9 (p13,in1[13],in2[13]);
or or_10 (p14,in1[14],in2[14]);
and and_6(p10p11,p10,p11);
and and_7(p12p13,p12,p13);
and and_8(p12p13p14,p12p13,p14);
and and_9(cp3,p10p11,p12p13p14);
and and_10(if_error_2,cp3,co2);
always @ (posedge clk)
begin
if_error_delayed_2 <= if_error_2;
end
or or_11 (if_error_delayed,if_error_delayed_1,if_error_delayed_2);
assign in1c[9:0] = {in1[14:6],if_error_delayed_1?1'b1:in1[5]};
assign in2c[9:0] = {in2[14:6],if_error_delayed_1?1'b1:in2[5]};
assign in1cc[9:0] = {in1[19:11],if_error_delayed_2?1'b1:in1[10]};
assign in2cc[9:0] = {in2[19:11],if_error_delayed_2?1'b1:in2[10]};
always @ (*)
begin
{co1,sum1[9:0]} = in1[ 9:0] + in2[ 9:0];
{co2,sum2[9:0]} = in1c[9:0] + in2c[9:0];
{co3,sum3[9:0]} = in1cc[9:0] + in2cc[9:0];
res[20:0] = {co3,sum3[9:5],sum2[9:5],sum1[9:0]};
end
endmodule
|
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module crc_control_unit
(
//OUTPUTS
output reg [1:0] byte_sel,
output bypass_byte0,
output buffer_full,
output read_wait,
output bypass_size,
output set_crc_init_sel,
output clear_crc_init_sel,
output crc_out_en,
output byte_en,
output reset_pending,
//INPUTS
input [1:0] size_in,
input write,
input reset_chain,
input clk,
input rst_n
);
//States definition for state_full
localparam EMPTY = 2'b00;
localparam WRITE_1 = 2'b01;
localparam WRITE_2 = 2'b10;
localparam BYPASS = 2'b11;
//States definition for state_byte
localparam IDLE = 3'b100;
localparam BYTE_0 = 3'b000;
localparam BYTE_1 = 3'b001;
localparam BYTE_2 = 3'b010;
localparam BYTE_3 = 3'b011;
//States definition for state_reset
localparam NO_RESET = 3'b000;
localparam RESET = 3'b001;
localparam WAIT = 3'b010;
localparam WRITE = 3'b011;
localparam RESET_2 = 3'b100;
//Coding for size signal
localparam BYTE = 2'b00;
localparam HALF_WORD = 2'b01;
localparam WORD = 2'b10;
//Flops Definition
reg [1:0] state_full;
reg [2:0] state_byte;
reg [2:0] state_reset;
//Internal signals
reg [1:0] next_state_full;
reg [2:0] next_state_byte;
reg [2:0] next_state_reset;
wire last_byte;
wire has_data;
//FSM for management of writes in the input buffers
//Definition of state register
always @(posedge clk)
begin
if(!rst_n)
state_full <= EMPTY;
else
state_full <= next_state_full;
end
//This signal indicates that the last byte is in processing
assign last_byte = (size_in == BYTE && state_byte == BYTE_0) ||
(size_in == HALF_WORD && state_byte == BYTE_1) ||
(size_in == WORD && state_byte == BYTE_3) ;
//Next state Logic
always @(*)
begin
next_state_full = state_full;
case(state_full)
EMPTY : next_state_full = (write) ? WRITE_1 : EMPTY;
WRITE_1:
begin
if(last_byte)
begin
if(!write)
next_state_full = EMPTY;
end
else
begin
if(write)
next_state_full = WRITE_2;
end
end
WRITE_2:
begin
if(last_byte)
next_state_full = (write) ? BYPASS : WRITE_1;
end
BYPASS :
begin
if(last_byte && !write)
next_state_full = WRITE_1;
end
endcase
end
//The flag full indicates that buffer is full and any attempt of writing must wait
assign buffer_full = (state_full == WRITE_2 && !last_byte) ||
(state_full == BYPASS && !last_byte);
assign read_wait = (state_byte != IDLE);
//This signal controls the selection of the byte0
//When bypass_byte0 = 1 the input of byte_ff is taken
//Otherwise, its output is taken
assign bypass_byte0 = (state_full != BYPASS);
//This signal indicates that there are data in the second position of the buffer
assign has_data = (state_full == WRITE_2) ||
(state_full == BYPASS ) ;
//FSM for management of readings in the buffer
//Definition of state register
always @(posedge clk)
begin
if(!rst_n)
state_byte <= IDLE;
else
state_byte <= next_state_byte;
end
always @(*)
begin
next_state_byte = state_byte;
case(state_byte)
IDLE: next_state_byte = (write) ? BYTE_0 : IDLE;
BYTE_0:
begin
if(size_in == BYTE)
begin
if(!write && !has_data)
next_state_byte = IDLE;
end
else
begin
next_state_byte = BYTE_1;
end
end
BYTE_1:
begin
if(size_in == HALF_WORD)
begin
if(has_data || (write && !buffer_full))
next_state_byte = BYTE_0;
else
next_state_byte = IDLE;
end
else
begin
next_state_byte = BYTE_2;
end
end
BYTE_2:
begin
next_state_byte = BYTE_3;
end
BYTE_3:
begin
if(has_data || (write && !buffer_full))
next_state_byte = BYTE_0;
else
next_state_byte = IDLE;
end
endcase
end
//The signal byte_sel controls the number of byte that will be processed by CRC Unit
always @(*)
begin
byte_sel = 2'b00;
case(state_byte)
BYTE_0: byte_sel = BYTE_0;
BYTE_1: byte_sel = BYTE_1;
BYTE_2: byte_sel = BYTE_2;
BYTE_3: byte_sel = BYTE_3;
endcase
end
//This signal controls the selection of the metadata size
//When bypass_size = 1 the input of size_ff is taken
//Otherwise, its output is taken
assign bypass_size = !( (state_full != BYPASS && state_byte != BYTE_0) ||
(state_full == BYPASS)
);
//This signal enables the write in the crc_out register
assign crc_out_en = (state_byte != IDLE);
//
assign byte_en = (state_byte == BYTE_0 && (size_in == HALF_WORD || size_in == WORD) && state_full != BYPASS) ||
(last_byte && has_data);
//FSM for control of reset of chained operation
//Definition of state register
always @(posedge clk)
begin
if(!rst_n)
state_reset <= NO_RESET;
else
state_reset <= next_state_reset;
end
always @(*)
begin
next_state_reset = state_reset;
case(state_reset)
NO_RESET:
begin
if((reset_chain && !has_data && state_byte != IDLE && !last_byte) || (reset_chain && has_data && last_byte))
next_state_reset = RESET;
if(reset_chain && has_data && !last_byte)
next_state_reset = WAIT;
end
RESET:
begin
if(last_byte)
next_state_reset = NO_RESET;
else
next_state_reset = (write) ? WRITE : RESET;
end
WAIT:
begin
if(last_byte)
next_state_reset = (write) ? WRITE : RESET;
else
next_state_reset = WAIT;
end
WRITE:
begin
if(reset_chain)
next_state_reset = (last_byte) ? RESET : RESET_2;
else
next_state_reset = (last_byte) ? NO_RESET : WRITE;
end
RESET_2:
begin
if(last_byte)
next_state_reset = (write) ? WRITE : RESET;
else
next_state_reset = RESET_2;
end
endcase
end
//This signal set the crc_init_sel flop
//When seted this flop turn on the chained operation of crc
assign set_crc_init_sel = (state_byte == BYTE_0);
//This signal clear the crc_init_sel
//The clear get priority over set
assign clear_crc_init_sel = (state_reset == NO_RESET && last_byte && reset_chain) ||
(state_byte == IDLE && reset_chain ) ||
(state_reset == RESET && last_byte ) ||
(state_reset == WRITE && last_byte ) ||
(state_reset == RESET_2 && last_byte ) ;
assign reset_pending = (state_reset != NO_RESET);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class T, class L> bool smax(T &x, L y) { return x < y ? (x = y, 1) : 0; } template <class T, class L> bool smin(T &x, L y) { return x > y ? (x = y, 1) : 0; } const int maxn = 15e3 + 17, maxk = 1e3 + 17, mod = 1e9 + 7, base = 1e7 + 19, lg = 17, maxq = 3e4 + 17; vector<int> iman[maxq << 2]; int n, k, nq, q, dp[lg][maxk], w[maxn], v[maxn], ans[maxq], po[maxk]; void majid(int st, int en, int idx, int l = 0, int r = q, int id = 1) { if (st <= l && r <= en) { iman[id].push_back(idx); return; } if (en <= l || r <= st) return; int mid = l + r >> 1; majid(st, en, idx, l, mid, id << 1), majid(st, en, idx, mid, r, id << 1 | 1); } void hamid(int l = 0, int r = q, int id = 1, int h = 1) { memcpy(dp[h], dp[h - 1], sizeof dp[h]); for (auto idx : iman[id]) for (int wi = k - w[idx]; wi >= 0; wi--) smax(dp[h][wi + w[idx]], dp[h][wi] + v[idx]); partial_sum(dp[h], dp[h] + k + 1, dp[h], [](int &x, int &y) { return max(x, y); }); if (r - l < 2) { for (int i = 1; i <= k; i++) ans[l] = (ans[l] + (long long)po[i - 1] * dp[h][i]) % mod; return; } int mid = l + r >> 1; hamid(l, mid, id << 1, h + 1), hamid(mid, r, id << 1 | 1, h + 1); } int st[maxn], en[maxn]; int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) cin >> v[i] >> w[i]; po[0] = 1; for (int i = 1; i <= k; i++) po[i] = (long long)po[i - 1] * base % mod; memset(en, 63, sizeof en); cin >> nq; for (int t, x; nq--;) { cin >> t; if (t == 1) cin >> v[n] >> w[n], st[n++] = q; else if (t == 2) cin >> x, en[x - 1] = q; else q++; } for (int i = 0; i < n; i++) majid(st[i], min(q, en[i]), i); hamid(); for (int i = 0; i < q; i++) cout << ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 10; const long long mod = 1e9 + 7; const long long inf = 1e18 + 10; long long n, L, k; string s, ans[N]; int ptr; void doIt(int l, int r) { if (l + 1 == r) { while (ans[l].size() < L) ans[l] += s[ptr], ptr++; return; } char last = s[ptr]; while (1) { for (int i = l; i < r; i++) { if (s[ptr] != last) { doIt(i, r); return; } if (ans[i].size() == L) return; ans[i] += s[ptr]; last = s[ptr]; ptr++; } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> L >> k >> s; sort(s.begin(), s.end()); doIt(0, k); for (int i = 0; i < n; i++) while (ans[i].size() < L) ans[i] += s[ptr], ptr++; sort(ans, ans + n); for (int i = 0; i < n; i++) cout << ans[i] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pp = 0.00000001; const int maxn = 100005; double ans, xo, da, mid; int ci, w, i, n, x[maxn], y[maxn]; bool pd(double k) { double ww, l = -1e9, r = 1e9; int i; for (i = 1; i <= n; i++) { if (k * k < (y[i] - k) * (y[i] - k)) { return 0; } ww = -1.0 * y[i] * y[i] + 2 * y[i] * k; ww = sqrt(ww); if (l < x[i] - ww) l = x[i] - ww; if (r > x[i] + ww) r = x[i] + ww; } if (l <= r) return true; else return false; } int main() { scanf( %d , &n); for (i = 1; i <= n; i++) { scanf( %d%d , &x[i], &y[i]); if (y[i] > 0) w++; else y[i] = -y[i]; } if (w != 0 && w != n) { printf( -1 n ); return 0; } xo = 0; da = 50000000000000.4949989; ci = 0; while (ci <= 100) { ci++; mid = (xo + da) / 2; if (pd(mid)) { ans = mid; da = mid; } else xo = mid; } printf( %lf n , mid); return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:167177216 ) int main() { double y1, y2, yw, xa, ya, r; cin >> y1 >> y2 >> yw >> xa >> ya >> r; double ll = 0, rr = xa; yw -= r; double yt = y1 + r + 1e-9; for (int i = 0; i < 300; ++i) { double xm = (ll + rr) / 2; double dx1 = -xm, dy1 = yt - yw; double a1 = acos(-dy1 / sqrt(dx1 * dx1 + dy1 * dy1)); dx1 = xa - xm, dy1 = ya - yw; double a2 = acos(-dy1 / sqrt(dx1 * dx1 + dy1 * dy1)); if (a1 > a2) rr = xm; else ll = xm; } double xm = (ll + rr) / 2; double a = yw - yt, b = -xm, c = -b * yt; double d = fabs(b * y2 + c) / sqrt(a * a + b * b); if (d + 1e-9 < r) { cout << -1 << endl; return 0; } cout.precision(20); cout << xm << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<int> adjc[100005]; vector<int> cadj[100005]; struct edge { int u, v, c; }; class dsu { public: dsu(vector<int> vert) : vert(vert) { n = vert.size(); par.resize(n); iota(par.begin(), par.end(), 0); } int root(int u) { if (par[u] == u) { return u; } return (par[u] = root(par[u])); } void merge(int u, int v) { int ui = lower_bound(vert.begin(), vert.end(), u) - vert.begin(); int vi = lower_bound(vert.begin(), vert.end(), v) - vert.begin(); int ru = root(ui), rv = root(vi); if (ru != rv) { if (rand() % 2) { swap(ru, rv); } par[ru] = rv; } } bool ced(int u, int v) { int ui = lower_bound(vert.begin(), vert.end(), u) - vert.begin(); int vi = lower_bound(vert.begin(), vert.end(), v) - vert.begin(); if ((ui == n || (vert[ui] != u)) || (vi == n || (vert[vi] != v))) return 0; return (root(ui) == root(vi)); } int n; vector<int> vert, par; }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<edge> e; for (int i = 0; i < m; i++) { int u, v, c; cin >> u >> v >> c; e.push_back({u, v, c}); cadj[c].push_back(u); cadj[c].push_back(v); adjc[u].push_back(c); adjc[v].push_back(c); } for (int i = 1; i <= n; i++) { sort(adjc[i].begin(), adjc[i].end()); adjc[i].resize(unique(adjc[i].begin(), adjc[i].end()) - adjc[i].begin()); } vector<dsu> cdsu; for (int i = 1; i <= m; i++) { sort(cadj[i].begin(), cadj[i].end()); cadj[i].resize(unique(cadj[i].begin(), cadj[i].end()) - cadj[i].begin()); cdsu.emplace_back(cadj[i]); } for (edge ed : e) { cdsu[ed.c - 1].merge(ed.u, ed.v); } map<pair<int, int>, int> dp; int q; cin >> q; while (q--) { int u, v; cin >> u >> v; if (adjc[u].size() > adjc[v].size()) { swap(u, v); } if (dp.find({u, v}) != dp.end()) { cout << dp[{u, v}] << endl; continue; } int ans = 0; for (auto c : adjc[u]) { ans += cdsu[c - 1].ced(u, v); } cout << ans << endl; dp[{u, v}] = ans; } return 0; }
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast,unroll-loops,no-stack-protector,fast-math ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) const long long mod = 1e9 + 7; const long long N = 1e5 + 5; void solve(void) { long long a, flag = 0; string b; cin >> a >> b; long long n = b.length(); for (long long i = 0; i < n; i++) { if (b[i] != 9 ) { flag = 1; break; } } n -= flag; cout << n * a << n ; } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed << setprecision(10); ; long long ___ = 1; cin >> ___; while (___--) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_BLACKBOX_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int h[4] = {0, 0, 1, -1}; int v[4] = {1, -1, 0, 0}; vector<vector<int> > adj; bool *visited; int num[501][501]; bool done = false; int sourceR, sourceC, destR, destC; void DFS(int vertix) { if (!done) { visited[vertix] = true; for (int i = 0; i < adj[vertix].size(); i++) { if (!done && visited[adj[vertix][i]] && adj[vertix][i] == num[destR - 1][destC - 1]) { if (visited[vertix]) { done = true; cout << YES << endl; return; } } if (!done && !visited[adj[vertix][i]]) { DFS(adj[vertix][i]); } } } } int main() { int n, m; cin >> n >> m; visited = new bool[n * m]; vector<int> temp; int cnt = 0; char a[501][501]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { adj.push_back(temp); cin >> a[i][j]; visited[cnt] = false; num[i][j] = cnt++; } } cin >> sourceR >> sourceC >> destR >> destC; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == X ) { visited[num[i][j]] = true; } for (int k = 0; k < 4; k++) { if (i + h[k] >= 0 && i + h[k] < n && j + v[k] >= 0 && j + v[k] < m) { adj[num[i][j]].push_back(num[i + h[k]][j + v[k]]); } } } } DFS(num[sourceR - 1][sourceC - 1]); if (!done) { cout << NO << endl; } return 0; }
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module can create clock signals that have a frequency lower *
* than those a PLL can generate. *
* *
* Revision: 1.2 *
* *
* Used in IP Cores: *
* Altera UP Avalon Audio and Video Config *
* *
******************************************************************************/
module altera_up_slow_clock_generator (
// Inputs
clk,
reset,
enable_clk,
// Bidirectionals
// Outputs
new_clk,
rising_edge,
falling_edge,
middle_of_high_level,
middle_of_low_level
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CB = 10; //COUNTER BITS
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input enable_clk;
// Bidirectionals
// Outputs
output reg new_clk;
output reg rising_edge;
output reg falling_edge;
output reg middle_of_high_level;
output reg middle_of_low_level;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [CB:1] clk_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
clk_counter <= 'h0;
else if (enable_clk)
clk_counter <= clk_counter + 1;
end
always @(posedge clk)
begin
if (reset)
new_clk <= 1'b0;
else
new_clk <= clk_counter[CB];
end
always @(posedge clk)
begin
if (reset)
rising_edge <= 1'b0;
else
rising_edge <= (clk_counter[CB] ^ new_clk) & ~new_clk;
end
always @(posedge clk)
begin
if (reset)
falling_edge <= 1'b0;
else
falling_edge <= (clk_counter[CB] ^ new_clk) & new_clk;
end
always @(posedge clk)
begin
if (reset)
middle_of_high_level <= 1'b0;
else
middle_of_high_level <=
clk_counter[CB] &
~clk_counter[(CB - 1)] &
(&(clk_counter[(CB - 2):1]));
end
always @(posedge clk)
begin
if (reset)
middle_of_low_level <= 1'b0;
else
middle_of_low_level <=
~clk_counter[CB] &
~clk_counter[(CB - 1)] &
(&(clk_counter[(CB - 2):1]));
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: shifter.v (tranlate from shifter.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from shifter.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Shifter Unit
// AUTHOR: Steve Rhoads ()
// Matthias Gruenewald
// DATE CREATED: 2/2/01
// FILENAME: shifter.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software \'as is\' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements the 32-bit shifter unit.
//-------------------------------------------------------------------
`include "yf32_define.v"
module shifter (value, shift_amount, shift_func, c_shift);
input [31:0] value;
input [ 4:0] shift_amount;
input [ 1:0] shift_func;
output [31:0] c_shift;
// type shift_function_type is (
// shift_nothing, shift_left_unsigned,
// shift_right_signed, shift_right_unsigned);
wire [31: 0] shift1L ;
wire [31: 0] shift2L ;
wire [31: 0] shift4L ;
wire [31: 0] shift8L ;
wire [31: 0] shift16L;
wire [31: 0] shift1R ;
wire [31: 0] shift2R ;
wire [31: 0] shift4R ;
wire [31: 0] shift8R ;
wire [31: 0] shift16R;
wire [31:16] fills ;
assign fills = (shift_func == `shift_right_signed &
value[31]) ? 16'b1111111111111111 : 16'b0000000000000000;
assign shift1L = (shift_amount[0]) ? {value [30:0], 1'b0} :value;
assign shift2L = (shift_amount[1]) ? {shift1L[29:0], 2'b0} :shift1L;
assign shift4L = (shift_amount[2]) ? {shift2L[27:0], 4'b0} :shift2L;
assign shift8L = (shift_amount[3]) ? {shift4L[23:0], 8'b0} :shift4L;
assign shift16L = (shift_amount[4]) ? {shift8L[15:0], 16'b0} :shift8L;
assign shift1R = (shift_amount[0]) ? {fills[31], value[31:1]}:value;
assign shift2R = (shift_amount[1]) ? {fills[31:30],shift1R[31: 2]}: shift1R;
assign shift4R = (shift_amount[2]) ? {fills[31:28],shift2R[31: 4]}: shift2R;
assign shift8R = (shift_amount[3]) ? {fills[31:24],shift4R[31: 8]}: shift4R;
assign shift16R = (shift_amount[4]) ? {fills[31:16],shift8R[31:16]}: shift8R;
`ifdef shifter_type_GENERIC
reg [31:0] c_shift;
/*
assign c_shift = (shift_func == `shift_left_unsigned) ? shift16L :
(shift_func == `shift_right_unsigned |
shift_func == `shift_right_signed) ? shift16R : `ZERO ;
*/
always @(shift_func or shift16L or shift16R) begin
case(shift_func) // synopsys parallel_case
`shift_left_unsigned : c_shift = shift16L;
`shift_right_unsigned,
`shift_right_signed : c_shift = shift16R;
default : c_shift = `ZERO;
endcase
end
`endif
`ifdef shifter_type_TRISTATE
wire [31:0] c_shift;
assign c_shift = (shift_func == `shift_left_unsigned) ? shift16L:{32{1'bz}};
assign c_shift = (shift_func == `shift_right_unsigned |
shift_func == `shift_right_signed) ? shift16R:{32{1'bz}};
assign c_shift = (shift_func == `shift_nothing) ? `ZERO : {32{1'bz}} ;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) int main() { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); long long n, p, d, w; cin >> n >> p >> w >> d; for (register int y = (0); y <= (w); ++y) { long long x = (p - y * d) / w; if (x < 0) continue; if (x * w + y * d != p) continue; if (x + y <= n) { cout << x << << y << << n - x - y << n ; return 0; } } cout << -1 << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int q, n, i, j, k, t; long long int a[3]; cin >> t; long long int area[5]; while (t--) { long long int a, b, x, y; cin >> a >> b >> x >> y; area[1] = (b - y - 1) * a; area[2] = (y)*a; area[3] = (a - x - 1) * b; area[4] = (x)*b; long long int ans = -1; for (i = 1; i <= 4; i++) { ans = max(ans, area[i]); } cout << ans << n ; } return 0; }
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: Line_Buffer.v
// Megafunction Name(s):
// altshift_taps
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Line_Buffer (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x);
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps0x;
output [11:0] taps1x;
output [11:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [35:0] sub_wire0;
wire [11:0] sub_wire5;
wire [23:12] sub_wire3 = sub_wire0[23:12];
wire [11:0] sub_wire4 = sub_wire0[11:0];
wire [35:24] sub_wire2 = sub_wire0[35:24];
wire [35:24] sub_wire1 = sub_wire2[35:24];
wire [11:0] taps2x = sub_wire1[35:24];
wire [11:0] taps1x = sub_wire3[23:12];
wire [11:0] taps0x = sub_wire4[11:0];
wire [11:0] shiftout = sub_wire5[11:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire5)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
altshift_taps_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 3,
altshift_taps_component.tap_distance = 800,
altshift_taps_component.width = 12;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "3"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "800"
// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "3"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "800"
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
// Retrieval info: USED_PORT: taps2x 0 0 12 0 OUTPUT NODEFVAL taps2x[11..0]
// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
// Retrieval info: CONNECT: taps2x 0 0 12 0 @taps 0 0 12 24
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; char cc[10] = RGBYW ; int d[5][5]; int cnt(int x) { int res = 0; while (x) { res += x & 1; x >>= 1; } return res; } int main() { int(n); scanf( %d , &n); for (int i = 0; i < (n); ++i) { char s[10]; scanf( %s , (s)); int x, y; for (int j = 0; j < (5); ++j) { if (s[0] == cc[j]) { x = j; break; } } y = s[1] - 1 ; d[x][y]++; } int an = 10; for (int i = 0; i < (32); ++i) for (int j = 0; j < (32); ++j) { int ha[6][6] = {}; for (int k1 = 0; k1 < (5); ++k1) for (int k2 = 0; k2 < (5); ++k2) { if (d[k1][k2]) { if (((i >> k1) & 1) && ((j >> k2) & 1)) { ha[k1 + 1][k2 + 1]++; } else if (((i >> k1) & 1) && ((j >> k2) & 1) == 0) { ha[k1 + 1][0]++; } else if (((i >> k1) & 1) == 0 && ((j >> k2) & 1)) { ha[0][k2 + 1]++; } else ha[0][0]++; } } bool err = false; for (int k1 = 0; k1 < (6); ++k1) for (int k2 = 0; k2 < (6); ++k2) { if (ha[k1][k2] > 1) err = true; } if (!err) an = min(an, cnt(i) + cnt(j)); } printf( %d n , an); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_TB_V
`define SKY130_FD_SC_HS__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VPWR = 1'b0;
#180 A0 = 1'b1;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 S0 = 1'b1;
#280 S1 = 1'b1;
#300 VGND = 1'b1;
#320 VPWR = 1'b1;
#340 A0 = 1'b0;
#360 A1 = 1'b0;
#380 A2 = 1'b0;
#400 A3 = 1'b0;
#420 S0 = 1'b0;
#440 S1 = 1'b0;
#460 VGND = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VGND = 1'b1;
#540 S1 = 1'b1;
#560 S0 = 1'b1;
#580 A3 = 1'b1;
#600 A2 = 1'b1;
#620 A1 = 1'b1;
#640 A0 = 1'b1;
#660 VPWR = 1'bx;
#680 VGND = 1'bx;
#700 S1 = 1'bx;
#720 S0 = 1'bx;
#740 A3 = 1'bx;
#760 A2 = 1'bx;
#780 A1 = 1'bx;
#800 A0 = 1'bx;
end
sky130_fd_sc_hs__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( avx2 ) using namespace std; void solve() { int q; cin >> q; unordered_map<string, string> map; while (q--) { string a, b; cin >> a >> b; if (map.find(a) != map.end()) { string s = map[a]; map.erase(a); map[b] = s; continue; } map[b] = a; } cout << map.size() << n ; for (auto i : map) { cout << i.second << << i.first << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) { solve(); } return 0; }
|
//======================================================================
//
// mkmif_core.v
// ------------
// The actual core module for the Master Key Memory (MKM) interface.
// The interface is implemented to use the Microchip 23K640 serial
// sram as external storage. The core acts as a SPI Master for the
// external memory including SPI clock generation.
//
// The current version of the core does not provide any functionality
// to protect against remanence.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Assured AB.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module mkmif_core(
input wire clk,
input wire reset_n,
output wire spi_sclk,
output wire spi_cs_n,
input wire spi_do,
output wire spi_di,
input wire read_op,
input wire write_op,
input wire init_op,
output wire ready,
output wire valid,
input wire [15 : 0] sclk_div,
input wire [15 : 0] addr,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam SPI_READ_DATA_CMD = 8'h03;
localparam SPI_WRITE_DATA_CMD = 8'h02;
localparam SPI_READ_STATUS_CMD = 8'h05;
localparam SPI_WRITE_STATUS_CMD = 8'h01;
localparam SEQ_MODE_NO_HOLD = 8'b01000001;
localparam CTRL_IDLE = 0;
localparam CTRL_READY = 1;
localparam CTRL_READ = 2;
localparam CTRL_WRITE = 3;
localparam CTRL_INIT = 4;
localparam CTRL_OP_START = 5;
localparam CTRL_OP_WAIT = 6;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg valid_reg;
reg valid_new;
reg valid_we;
reg [31 : 0] read_data_reg;
reg read_data_we;
reg [3 : 0] mkmif_ctrl_reg;
reg [3 : 0] mkmif_ctrl_new;
reg mkmif_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] spi_read_data;
reg [55 : 0] spi_write_data;
reg spi_set;
reg spi_start;
wire spi_ready;
reg [2 : 0] spi_length;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign valid = valid_reg;
assign read_data = read_data_reg;
//----------------------------------------------------------------
// spi
// The actual spi interfacce
//----------------------------------------------------------------
mkmif_spi spi(
.clk(clk),
.reset_n(reset_n),
.spi_sclk(spi_sclk),
.spi_cs_n(spi_cs_n),
.spi_do(spi_do),
.spi_di(spi_di),
.set(spi_set),
.start(spi_start),
.length(spi_length),
.divisor(sclk_div),
.ready(spi_ready),
.wr_data(spi_write_data),
.rd_data(spi_read_data)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 0;
valid_reg <= 0;
read_data_reg <= 32'h0;
mkmif_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ready_we)
ready_reg <= ready_new;
if (valid_we)
valid_reg <= valid_new;
if (read_data_we)
read_data_reg <= spi_read_data;
if (mkmif_ctrl_we)
mkmif_ctrl_reg <= mkmif_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// mkmif_ctrl
// Main control FSM.
//----------------------------------------------------------------
always @*
begin : mkmif_ctrl
spi_set = 0;
spi_start = 0;
spi_length = 3'h0;
spi_write_data = 56'h0;
read_data_we = 0;
ready_new = 0;
ready_we = 0;
valid_new = 0;
valid_we = 0;
mkmif_ctrl_new = CTRL_IDLE;
mkmif_ctrl_we = 0;
case (mkmif_ctrl_reg)
CTRL_IDLE:
begin
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
CTRL_READY:
begin
ready_new = 1;
ready_we = 1;
if (read_op)
begin
ready_new = 0;
ready_we = 1;
valid_new = 0;
valid_we = 1;
mkmif_ctrl_new = CTRL_READ;
mkmif_ctrl_we = 1;
end
if (write_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_WRITE;
mkmif_ctrl_we = 1;
end
if (init_op)
begin
ready_new = 0;
ready_we = 1;
mkmif_ctrl_new = CTRL_INIT;
mkmif_ctrl_we = 1;
end
end
CTRL_READ:
begin
spi_set = 1;
spi_write_data = {SPI_READ_DATA_CMD, addr, 32'h0};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_WRITE:
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_DATA_CMD, addr, write_data};
spi_length = 3'h7;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
CTRL_INIT:
begin
if (spi_ready)
begin
spi_set = 1;
spi_write_data = {SPI_WRITE_STATUS_CMD, SEQ_MODE_NO_HOLD, 40'h0};
spi_length = 3'h2;
mkmif_ctrl_new = CTRL_OP_START;
mkmif_ctrl_we = 1;
end
end
CTRL_OP_START:
begin
spi_start = 1;
mkmif_ctrl_new = CTRL_OP_WAIT;
mkmif_ctrl_we = 1;
end
CTRL_OP_WAIT:
begin
if (spi_ready)
begin
read_data_we = 1;
valid_new = 1;
valid_we = 1;
mkmif_ctrl_new = CTRL_READY;
mkmif_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (mkmif_ctrl_reg)
end // mkmif_ctrl
endmodule // mkmif
//======================================================================
// EOF mkmif.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_FUNCTIONAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; bool compare(const pair<int, int>& i, const pair<int, int>& j) { return i.first < j.first; } int ncr(int n, int k) { if (n < k) return 0; int C[n + 1][k + 1]; int i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= min(i, k); j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % 1000000007; } } return C[n][k]; } long long modpowIter(long long a, long long b, long long c) { long long ans = 1; while (b != 0) { if (b % 2 == 1) ans = (ans * a) % LLONG_MAX; a = (a * a) % LLONG_MAX; b /= 2; } return ans; } string intobin(int n) { string s = ; if (n == 0) s = 0 ; while (n) { if (n % 2) s = 1 + s; else s = 0 + s; n /= 2; } return s; } int bintoin(string s) { long long n = 0; vector<long long> v; v.push_back(1); for (int i = 0; i < 400; i++) { v.push_back((v[v.size() - 1] * 2) % 1000003); } for (int i = s.length() - 1; i > -1; i--) { n = (n + (s[i] - 0 ) * v[s.length() - i - 1]) % 1000003; } return n; } long long nc2(long long n, long long k) { if (n < k) return 0; return (n * (n - 1)) / 2; } bool prime[1000001]; void SieveOfEratosthenes(int n) { memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } } int main() { int n; cin >> n; int m; cin >> m; int arr[n]; double b[n]; for (int i = 0; i < n; i++) { cin >> arr[i] >> b[i]; } int dp[n]; dp[0] = 1; for (int i = 1; i <= n - 1; i++) { dp[i] = 1; for (int j = 0; j < i; j++) { if (arr[i] >= arr[j] && dp[i] < dp[j] + 1) dp[i] = dp[j] + 1; } } cout << n - (*max_element(dp, dp + n)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(NULL); cin.sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) { int a, b, x, y; cin >> a >> b >> x >> y; cout << max(max(((a - 1) - x) * b, ((b - 1) - y) * a), max((x)*b, (y)*a)) << n ; } return 0; }
|
// MBT 2/28/2015
//
// This module computes gray(x+1),
// where x is a binary value.
//
// It has not been determined whether this beats
// synthesis of (x+1) ^ ((x+1) >> 1). Synopsys has some
// killer adder implementations.
// However, it has a good shot, since it uses
// mostly ands and not xors.
//
/*
Since x and x+1 differ by at most 1 bit, we
can figure out which bit it is that will change.
Take for example:
x g(x) g(x+1) diff
000 000 001 001
001 001 011 010
010 011 010 001
011 010 110 100
100 110 111 001
101 111 101 010
110 101 100 001
111 100 000 100
We can replicate diff with:
x and-scan drop_hi 0append1 (~(x >> 1) & x) drop_hi
000 000 00 0001 0001 001
001 001 01 0011 0010 010
010 000 00 0001 0001 001
011 011 11 0111 0100 100
100 000 00 0001 0001 001
101 001 01 0011 0010 010
110 000 00 0001 0001 001
111 111 11 0111 0100 100
*/
`include "bsg_defines.v"
module bsg_binary_plus_one_to_gray #(parameter `BSG_INV_PARAM(width_p ))
(input [width_p-1:0] binary_i
, output [width_p-1:0] gray_o
);
wire [width_p-1:0] binary_scan;
bsg_scan #(.width_p(width_p)
,.and_p(1)
,.lo_to_hi_p(1)
) scan_and (.i(binary_i), .o(binary_scan));
wire [width_p:0] temp = { 1'b0, binary_scan[width_p-2:0], 1'b1};
wire [width_p-1:0] edge_detect = ~temp[width_p:1] & temp[width_p-1:0];
// xor gray code of binary_i with the bit that should change
assign gray_o = (binary_i >> 1) ^ (binary_i) ^ edge_detect;
endmodule
`BSG_ABSTRACT_MODULE(bsg_binary_plus_one_to_gray)
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, pair<long long, long long>>> v; long long a, b, w, cnt; long long parent[100005], sz[100005]; void init(long long n) { for (long long i = 1; i <= n; i++) parent[i] = i, sz[i] = 1; } long long root(long long x) { if (parent[x] == x) return x; return parent[x] = root(parent[x]); } long long mst(long long n, long long k) { long long ans = 0; for (long long i = 0; i < n; i++) { long long x = v[i].second.first, y = v[i].second.second, z = v[i].first; if (x == a && y == b) continue; long long px = root(x), py = root(y); if (px != py) { if (sz[px] < sz[py]) swap(px, py); ans += z; sz[px] += sz[py]; parent[py] = px; cnt++; } } if (cnt != k) return -1; return ans; } int main() { long long t, n, i, j, m, ans = 0; cin >> n >> m; for (i = 1; i <= m; i++) { long long x, y, z; cin >> x >> y >> z; if (x > y) swap(x, y); v.push_back({z, {x, y}}); } a = v[0].second.first, b = v[0].second.second, w = v[0].first; sort(v.begin(), v.end()); init(n); cnt = 2; sz[a] = 2; parent[b] = a; long long ans1 = w + mst(m, n); init(n); cnt = 1; long long ans2 = mst(m, n); if (ans2 >= 0) cout << w - (ans1 - ans2); else cout << 1000000000; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_PP_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : chip_top.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/chip.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.29 - lichangbeiju - Change the xx_ to xx_n.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "cpu.h"
`include "bus.h"
module bus_if (
input wire clk, //clock
input wire reset, //reset
input wire stall, //delay signal
input wire flush, //refresh signal
output reg busy, //bus busy signal
input wire [`WordAddrBus] addr, //cpu address = if_pc
input wire as_n, //cpu : address valid
input wire rw, //cpu : read/write
input wire [`WordDataBus] wr_data, //cpu write data
output reg [`WordDataBus] rd_data, //cpu : read data
input wire [`WordDataBus] spm_rd_data, //spm : read data
output wire [`WordAddrBus] spm_addr, //spm : address
output reg spm_as_n, //spm : address valid
output wire spm_rw, //spm : read/write
output wire [`WordDataBus] spm_wr_data, //
input wire [`WordDataBus] bus_rd_data, //bus : read data
input wire bus_rdy_n, //bus : ready
input wire bus_grant_n, //bus : grant
output reg bus_req_n, //bus : request
output reg [`WordAddrBus] bus_addr, //bus : address
output reg bus_as_n, //bus : address select
output reg bus_rw, //
output reg [`WordDataBus] bus_wr_data //
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
// `define UDP
// `define CLK_TEST_EN
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
reg [`BusIfStateBus] state; //bus inteface state
reg [`WordDataBus] rd_buf; //read buffer
wire [`BusSlaveIndexBus] s_index; //slave index
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the master grant logic
//------------------------------------------------------------------------------------------------
/********** generate the bus slave index**********/
//use the MSB 3 bit to control the index
assign s_index = addr[`BusSlaveIndexLoc];
/********** output assignemnt**********/
assign spm_addr = addr;
assign spm_rw = rw;
assign spm_wr_data = wr_data;
/********** memory access control**********/
always @(*) begin
/* default */
rd_data = `WORD_DATA_W'h0;
spm_as_n = `DISABLE_N;
busy = `DISABLE;
/* bus interface state */
case (state)
`BUS_IF_STATE_IDLE : begin //idle
/* memory access */
if ((flush == `DISABLE) && (as_n == `ENABLE_N)) begin
/* select the access target */
if (s_index == `BUS_SLAVE_1) begin // SPM access control
if (stall == `DISABLE) begin //dectect the delay[stall]
spm_as_n = `ENABLE_N;
if (rw == `READ) begin //read access control
rd_data = spm_rd_data;
end
end
end else begin //access the bus
busy = `ENABLE;
end
end
end
`BUS_IF_STATE_REQ : begin //bus request
busy = `ENABLE;
end
`BUS_IF_STATE_ACCESS : begin //read access
/* wait the ready */
if (bus_rdy_n == `ENABLE_N) begin //bus ready
if (rw == `READ) begin //read control
rd_data = bus_rd_data;
end
end else begin //the bus is not ready
busy = `ENABLE;
end
end
`BUS_IF_STATE_STALL : begin //delay
if (rw == `READ) begin //read control
rd_data = rd_buf;
end
end
endcase
end
/********** bus interface state contrl **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* asynchronous reset */
state <= #1 `BUS_IF_STATE_IDLE;
bus_req_n <= #1 `DISABLE_N;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_as_n <= #1 `DISABLE_N;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
rd_buf <= #1 `WORD_DATA_W'h0;
end else begin
/* bus interface state */
case (state)
`BUS_IF_STATE_IDLE : begin //Idle
/* memory access */
if ((flush == `DISABLE) && (as_n == `ENABLE_N)) begin
/* select the access target*/
if (s_index != `BUS_SLAVE_1) begin // access the bus
state <= #1 `BUS_IF_STATE_REQ;
bus_req_n <= #1 `ENABLE_N;
bus_addr <= #1 addr;
bus_rw <= #1 rw;
bus_wr_data <= #1 wr_data;
end
end
end
`BUS_IF_STATE_REQ : begin //bus request
/* wait the bus grant */
if (bus_grant_n == `ENABLE_N) begin //get the grant
state <= #1 `BUS_IF_STATE_ACCESS;
bus_as_n <= #1 `ENABLE_N;
end
end
`BUS_IF_STATE_ACCESS : begin //access the bus
/* disable the address select */
bus_as_n <= #1 `DISABLE_N;
/* wait the bus ready*/
if (bus_rdy_n == `ENABLE_N) begin //the bus is ready
bus_req_n <= #1 `DISABLE_N;
bus_addr <= #1 `WORD_ADDR_W'h0;
bus_rw <= #1 `READ;
bus_wr_data <= #1 `WORD_DATA_W'h0;
/* save the read data into buffer*/
if (bus_rw == `READ) begin //read access
rd_buf <= #1 bus_rd_data;
end
/* detect the stall */
if (stall == `ENABLE) begin //have a stall
state <= #1 `BUS_IF_STATE_STALL;
end else begin //have not a stall
state <= #1 `BUS_IF_STATE_IDLE;
end
end
end
`BUS_IF_STATE_STALL : begin //STALL
/* detect the stall */
if (stall == `DISABLE) begin //disable the stall
state <= #1 `BUS_IF_STATE_IDLE;
end
end
endcase
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
#include <bits/stdc++.h> using namespace std; struct edge { int x, y, z, id; } e[200005]; vector<int> to[200005]; int fa[200005], f[200005][18], deep[200005], g[200005][18], id[200005], ans[200005]; bool flag[200005]; int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } void dfs(int x, int fa) { f[x][0] = fa, deep[x] = deep[fa] + 1; for (auto tar : to[x]) if (tar != fa) dfs(tar, x); } pair<int, int> lca(int x, int y) { int res = 0; if (deep[x] < deep[y]) swap(x, y); for (int k = 17; k >= 0; k--) if (deep[f[x][k]] >= deep[y]) res = max(res, g[x][k]), x = f[x][k]; if (x == y) return {x, res}; for (int k = 17; k >= 0; k--) if (f[x][k] != f[y][k]) res = max(res, max(g[x][k], g[y][k])), x = f[x][k], y = f[y][k]; res = max(res, max(g[x][0], g[y][0])); return {f[x][0], res}; } void merge(int from, int to, int v) { from = find(from); while (deep[from] > deep[to]) { ans[id[from]] = v; fa[from] = find(f[from][0]); from = find(from); } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d%d%d , &e[i].x, &e[i].y, &e[i].z), e[i].id = i; sort(e + 1, e + m + 1, [&](edge a, edge b) { return a.z < b.z; }); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) { int fx = find(e[i].x), fy = find(e[i].y); if (fx != fy) to[e[i].x].push_back(e[i].y), to[e[i].y].push_back(e[i].x), fa[fx] = fy; else flag[i] = 1; } dfs(1, 0); for (int i = 1; i <= m; i++) if (!flag[i]) g[deep[e[i].x] < deep[e[i].y] ? e[i].y : e[i].x] [0] = e[i].z, id[deep[e[i].x] < deep[e[i].y] ? e[i].y : e[i].x] = e[i].id; for (int k = 1; k <= 17; k++) for (int i = 1; i <= n; i++) f[i][k] = f[f[i][k - 1]][k - 1], g[i][k] = max(g[i][k - 1], g[f[i][k - 1]][k - 1]); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) if (flag[i]) { auto g = lca(e[i].x, e[i].y); ans[e[i].id] = g.second; merge(e[i].x, g.first, e[i].z), merge(e[i].y, g.first, e[i].z); } for (int i = 1; i <= m; i++) printf( %d , ans[i] ? ans[i] - 1 : -1); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline bool ig(char c) { return c >= 0 && c <= 9 ; } inline void read(int &oi) { char c; int f = 1, res = 0; while (c = getchar(), (!ig(c)) && c != - ) ; c == - ? f = -1 : res = (c ^ 48); while (c = getchar(), ig(c)) res = res * 10 + (c ^ 48); oi = f * res; } inline void print(int oi) { if (oi < 0) putchar( - ), oi = ~oi + 1; if (oi > 9) print(oi / 10); putchar(oi % 10 + 48); } int n, m, ans; struct Edge { int x, y, z; bool operator<(const Edge &b) const { return z > b.z; } } e[200005]; int fa[200005]; bool s[200005]; inline int gfa(int u) { return u ^ fa[u] ? fa[u] = gfa(fa[u]) : u; } int main() { read(n); read(m); for (int i = 1; i <= m; ++i) read(e[i].x), read(e[i].y), read(e[i].z); sort(e + 1, e + 1 + m); for (int i = 1; i <= n; ++i) fa[i] = i, s[i] = true; for (int i = 1; i <= m; ++i) { int fx = gfa(e[i].x), fy = gfa(e[i].y); if ((fx ^ fy) && (s[fx] || s[fy])) ans += e[i].z, fa[fx] = fy, s[fy] = s[fy] & s[fx]; else if (!(fx ^ fy) && s[fx]) s[fx] = false, ans += e[i].z; } print(ans); putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int v[1000005]; int main() { int n, m, i, first, second, lastdif = -0x3f3f3f3f; cin >> n; for (i = 1; i <= n; ++i) cin >> v[i]; for (i = 2; i <= n; ++i) { if (v[i] - v[i - 1] != lastdif && lastdif != -0x3f3f3f3f) { cout << v[n]; return 0; ; } lastdif = v[i] - v[i - 1]; } cout << v[n] + lastdif; return 0; }
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long t; cin >> t; while (t--) { long long a, b, c; cin >> a >> b >> c; if (a < c) cout << 1; else cout << -1; cout << ; if (c < a * b) cout << b; else cout << -1 ; cout << endl; } }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_dest_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
output [C_ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output fifo_ready,
input fifo_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [3:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
assign sync_id_ret = sync_id;
wire data_enabled;
wire [C_ID_WIDTH-1:0] data_id;
wire _fifo_ready;
// We are not allowed to just de-assert valid, but if the streaming target does
// not accept any samples anymore we'd lock up the DMA core. So retain the last
// beat when disabled until it is accepted. But if in the meantime the DMA core
// is re-enabled and new data becomes available overwrite the old.
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
);
dmac_response_generator # (
.C_ID_WIDTH(C_ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
assign fifo_ready = _fifo_ready | ~enabled;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y; string s, t; cin >> x >> y >> s >> t; int arr[y - x + 1]; int mx = -1, res; for (int i = 0; i < y - x + 1; i++) { int k = i; arr[i] = 0; for (int j = 0; j < x; j++, k++) { if (t[k] == s[j]) arr[i] += 1; } if (mx < arr[i]) { mx = arr[i]; res = i; } } cout << x - mx << endl; for (int i = res, j = 0; j < x; i++, j++) { if (t[i] != s[j]) cout << j + 1 << ; } return 0; }
|
`include "bsg_defines.v"
`include "config_defs.v"
module config_snooper
(input clk, // destination side clock from pins
input reset, // destination side reset from pins
input config_s config_i, // from IO pads
output [data_max_bits_lp - 1 : 0] id_o,
output [data_max_bits_lp - 1 : 0] data_o
);
localparam data_rx_len_lp = (data_max_bits_lp + (data_max_bits_lp / data_frame_len_lp) + frame_bit_size_lp);
// + frame_bit_size_lp means the end, or msb of received data is always framing bits
// if data_max_bits_lp is a multiple of data_frame_len_lp, "00" is expected at the end of received data
localparam shift_width_lp = (data_rx_len_lp + frame_bit_size_lp +
id_width_lp + frame_bit_size_lp +
len_width_lp + frame_bit_size_lp +
valid_bit_size_lp);
// shift register width of this node
localparam header_len_lp = (shift_width_lp - data_rx_len_lp);
localparam sync_shift_len_lp = sync_len_lp + 2; // + 2 is to integrate the two edge detecting flip-flops
/* The communication packet is defined as follows:
* msb lsb
* | data_rx | frame bits | node id | frame bits | packet length | frame bits | valid bits |
*
* valid bit is defined as "10".
* packet length equals the number of bits in one complete packet, i.e. msb - lsb + 1.
* frame bits are certain patterns to separate packet content, defined as '0'.
* node id is an unique integer to identify current node.
* data_rx contains the data payload and framing bits inserted every data_frame_len_lp bits.
*
* Before use, reset the configuration node is mandatory by sending continuous '1's, and the
* minimum length of the reset sequence is (frame_bit_size_lp * 2 + len_width_lp), or the
* indicated field above.
*
* Each node contains a shift register that represents the same structure of a complete packet,
* and the node begins interpret received packet once it sees a '0' in the lsb of the shift
* register. The node determines if it is the target according to the node id bits. If so, the
* node captures received data, remove framing bits and write the data to its internal register.
* Otherwise, the node simply passes every bit to its subsequent node.
*/
typedef struct packed {
logic [data_rx_len_lp - 1 : 0] rx; // data_rx
logic f2; // frame bit 2
logic [id_width_lp - 1 : 0] id; // node id
logic [frame_bit_size_lp - 1 : 0] f1; // frame bit 1
logic [len_width_lp - 1 : 0] len; // packet length
logic [frame_bit_size_lp - 1 : 0] f0; // frame bit 0
logic [valid_bit_size_lp - 1 : 0] valid; // valid bits
} node_packet_s; // ==> can be reduced
node_packet_s shift_n, shift_r; // shift register
logic [id_width_lp - 1 : 0] node_id, node_id_r;
logic feedback; // lfsr feedback bit for id_tag
logic [id_tag_bits_lp - 1 : 0] id_tag, id_tag_r; // lfsr to generate pseudo-random tags
logic cfg_reset; // configuration network reset signal
logic valid; // begin of packet signal
logic data_en; // data_r write enable
logic ready_n, ready_r; // data_r ready and corresponding registers for clock domain crossing
// no combinational logic between ready_r and its destination side receiver,
// to reduce the change to go metastable
logic [len_width_lp - 1 : 0] packet_len;
logic [$bits(integer) - 1 : 0] data_framed_bits_int; // to avoid type casting warnings from Lint
logic [len_width_lp - 1 : 0] data_framed_bits, data_bits; // valid data bits in the packet
logic [$bits(integer) - 1 : 0] count_n_int; // to avoid type casting warnings from Lint
logic [len_width_lp - 1 : 0] count_n, count_r; // bypass counter
logic count_non_zero; // bypass counter is zero signal
logic [data_rx_len_lp - 1 : 0] data_rx;
logic [data_max_bits_lp - 1 : 0] data_snoop, data_mask; // snooped data and corresponding data mask
logic [data_max_bits_lp - 1 : 0] data_n, data_r; // data payload register
logic [sync_shift_len_lp - 1 : 0] sync_shift_n, sync_shift_r; // clock domain crossing syncronization registers + edge detection registers
// The following two signals are used to detect the reset posedge.
// Suppose that apart from this configuration network the remaining part of
// the chip resets on 1 of the reset_input, now if the configuration
// registers are made to reset on posedge of the reset_input, it is possible
// to configure those registers while the rest of chip is being reset,
// reducing the chance for the chip to go metastable. The reset_input is
// pulled down when it's safe to believe all configuration registers are
// properly loaded and stable.
// Here it is not necessary to reset configuration registers strictly on the
// posedge of reset_input, therefore the following two signals are used to
// detect a delayed posedge of reset_input.
logic r_e_s_e_t_r; // registered reset, to be used with reset input to detect posedge of reset
logic default_en; // derived reset-to-default in destination clock domain
logic data_dst_en; // data_dst_r write enable
logic [data_max_bits_lp - 1 : 0] data_dst, data_dst_r; // destination side data payload register
logic [id_width_lp - 1 : 0] node_id_dst, node_id_dst_r;
logic [id_tag_bits_lp - 1 : 0] id_tag_dst, id_tag_dst_r;
assign count_n_int = (valid) ? (packet_len - 1) : ((count_non_zero) ? (count_r - 1) : count_r);
assign count_n = count_n_int[0 +: len_width_lp];
// Load packet length to counter at the beginning of a packet, and
// decrease its value while it's non-zero. The node does not care
// about content in its shift register when the counter is not zero.
assign shift_n = {config_i.cfg_bit, shift_r[1 +: shift_width_lp - 1]};
assign feedback = id_tag_r[7] ^ id_tag_r[5] ^ id_tag_r[4] ^ id_tag_r[3]; // 8-bit max-period lfsr formula: x ** 8 + x ** 6 + x ** 5 + x ** 4 + 1
assign id_tag = {id_tag_r[0 +: id_tag_bits_lp - 1], feedback};
always_ff @ (posedge config_i.cfg_clk) begin
if (cfg_reset) begin
count_r <= 0;
node_id_r <= '0;
id_tag_r <= '1; // has to be non-zero initial value
data_r <= '0;
ready_r <= 0;
end else begin
count_r <= count_n;
if (data_en) begin
id_tag_r <= id_tag;
node_id_r <= node_id;
data_r <= data_n;
ready_r <= ready_n;
end
end
shift_r <= shift_n;
end
assign ready_n = ready_r ^ data_en; // xor, invert ready signal when data_en is 1
assign sync_shift_n = {(ready_r ^ cfg_reset), sync_shift_r[1 +: sync_shift_len_lp - 1]}; // clock domain crossing synchronization line
assign default_en = reset & (~ r_e_s_e_t_r); // (reset == 1) & (r_e_s_e_t_r == 0)
// The NAND gate array is used as filters to clear cross clock domain data's
// metastability when entering a new clock domain. Ths idea is based on the
// assumption that a normal 4-transistor NAND gate (A, B -> A nand B) is
// safe to block signal A when signal B is 0. When signal B is 1, its output
// may hover when signal A is transitioning, and the unstable output may
// violate the receiver register's setup time constraints.
// In this config node context, signal data_r is from a different clock
// domain than data_dst_en and data_dst.
rNandMeta #(.width_p(data_max_bits_lp))
data_dst_filter (.data_a_i(data_r),
.data_b_i({data_max_bits_lp {data_dst_en}}),
.nand_o(data_dst) );
rNandMeta #(.width_p(id_width_lp))
node_id_dst_filter (.data_a_i(node_id_r),
.data_b_i({id_width_lp {data_dst_en}}),
.nand_o(node_id_dst) );
rNandMeta #(.width_p(id_tag_bits_lp))
id_tag_dst_filter (.data_a_i(id_tag_r),
.data_b_i({id_tag_bits_lp {data_dst_en}}),
.nand_o(id_tag_dst) );
always_ff @ (posedge clk) begin
if (reset) begin
r_e_s_e_t_r <= 1;
end else begin
r_e_s_e_t_r <= 0;
end
if (default_en) begin
data_dst_r <= '0;
node_id_dst_r <= '0;
id_tag_dst_r <= '1;
end else begin
if (data_dst_en) begin
data_dst_r <= ~data_dst; // data_dst is the inverted receiving data
node_id_dst_r <= ~node_id_dst; // node_id_dst is the inverted node_id_r
id_tag_dst_r <= ~id_tag_dst; // id_tag_dst is the inverted id_tag_r
end
end
sync_shift_r <= sync_shift_n;
end
// An inverted ready_r from config domain indicates a valid data_r word is ready to be captured.
// If an edge occurs in ready_r, sooner or later the sync line detects it by having different bits in the least significant 2 positions.
// This implementation depends on that the least significant 2 bits in sync line are *NOT* metastable. When they also go metastable,
// the circuit may fail. Extend the length of sync_len_lp could increase mean time between failures.
assign data_dst_en = sync_shift_r[0] ^ sync_shift_r[1];
assign cfg_reset = & shift_r[0 +: reset_len_lp]; // reset sequence is an all '1' string of reset_len_lp length
assign valid = (~count_non_zero) ? (shift_r.valid == 2'b10) : 1'b0; // shift_r.valid == "10" means a valid packet arrives
assign packet_len = shift_r.len;
assign node_id = shift_r.id;
assign data_rx = shift_r.rx;
// This generate block is to remove framing bits and wire only data payload
// bits to the config data register of this node.
genvar i;
generate // remove framing bits in data
for(i = 0; i < data_rx_len_lp - frame_bit_size_lp; i++) begin // the end, or msb of a transferred data is always '0' which is discarded
if ((i + 1) % (data_frame_len_lp + frame_bit_size_lp)) begin // bit is payload when % returns non-zero
assign data_snoop[i - i / (data_frame_len_lp + frame_bit_size_lp)] = data_rx[i];
end
end
endgenerate
generate // generate data_mask
for(i = 0; i < data_max_bits_lp; i++) begin // the end, or msb of a transferred data is always '0' which is discarded
assign data_mask[i] = (i < data_bits);
end
endgenerate
assign data_n = data_snoop & data_mask;
assign data_framed_bits_int = (packet_len - header_len_lp - 1); // minus 1 means to remove the msb framing bit
assign data_framed_bits = data_framed_bits_int[0 +: len_width_lp];
always_comb begin: cal_data_bits // calculate valid data bits in packet ==> need a better decoding logic
if ( (0 < data_framed_bits) && (data_framed_bits < 8) ) begin //==> fix the sign problem
data_bits = data_framed_bits;
end else if ( (8 < data_framed_bits) && (data_framed_bits < 17) ) begin
data_bits = data_framed_bits - 1;
end else if ( (17 < data_framed_bits) && (data_framed_bits < 26) ) begin
data_bits = data_framed_bits - 2;
end else if ( (26 < data_framed_bits) && (data_framed_bits < 33) ) begin
data_bits = data_framed_bits - 3;
end else begin // not valid data_framed_bits value
data_bits = 0;
end
end
assign data_en = valid;
assign count_non_zero = | count_r;
// Output signals
assign id_o = { {(data_max_bits_lp - id_width_lp - id_tag_bits_lp) {1'b0}}, id_tag_dst_r, node_id_dst_r };
assign data_o = data_dst_r; // data_dst_r is the inverted data_r
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; if (str[0] > 4 && str[0] != 9 ) str[0] = (char)( 9 - str[0] + 0 ); for (int x = 1; x < (int)str.length(); x++) if (str[x] > 4 ) str[x] = (char)( 9 - str[x] + 0 ); cout << str << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Inf = 0x3f3f3f3f; const long long INF = 0x3f3f3f3f3f3f3f3fll; const int qwq = 1 << 19; int N, Q; int a[qwq]; struct Query { int r1, c1, r2, c2, id; Query(int r1, int c1, int r2, int c2, int id) : r1(r1), c1(c1), r2(r2), c2(c2), id(id) {} bool inline operator<(const Query& a) const { return r2 < a.r2; } }; struct Segtree { int dt[qwq << 1]; void inline init() { memset(dt, Inf, sizeof(dt)); } void inline add(int a, int x) { a += qwq; dt[a] = x; while (a >>= 1) dt[a] = min(dt[a << 1], dt[a << 1 | 1]); } int inline get(int l, int r) { int res = Inf; for (l += qwq, r += qwq + 1; l < r; l >>= 1, r >>= 1) { if (l & 1) res = min(res, dt[l++]); if (r & 1) res = min(res, dt[--r]); } return res; } } sl, sr, qj; vector<Query> q1, q2; int ans[qwq]; vector<int> dd; int inline mianx(int a, int l, int r) { return max(min(a, r), l); } int inline Ubval(int val) { int l = -1, r = ((int)(dd).size()); while (r - l > 1) { int m = (l + r) >> 1; if (a[dd[m]] > val) r = m; else l = m; } return r; } int inline Lbpos(int val) { return lower_bound((dd).begin(), (dd).end(), val) - dd.begin(); } int inline FLbpos(int val) { return upper_bound((dd).begin(), (dd).end(), val, greater<int>()) - dd.begin(); } void inline solve() { int qid = 0; sl.init(); sr.init(); qj.init(); for (int i = 1; i <= (N); ++i) qj.add(i, a[i]); for (int i = 1; i <= (N); ++i) { while (((int)(dd).size()) && a[dd.back()] >= a[i]) dd.pop_back(); sl.add(((int)(dd).size()), a[i] - 2 * i); sr.add(((int)(dd).size()), -a[i] - 2 * i); int rp = ((int)(dd).size()); dd.push_back(i); while (qid < ((int)(q1).size()) && q1[qid].r2 == i) { int id = q1[qid].id; int r1 = q1[qid].r1, c1 = q1[qid].c1; int r2 = q1[qid].r2, c2 = q1[qid].c2; int lp = Lbpos(r1); ans[id] = min(ans[id], r2 - r1 + c2 + 1); ans[id] = min(ans[id], r2 - r1 + abs(min(c1, a[dd[lp]]) - c2)); int rpos = Ubval(c2), lpos = rpos - 1, pos; rpos = mianx(rpos, lp, rp); lpos = mianx(lpos, lp, rp); if (abs(a[dd[lpos]] - c2) < abs(a[dd[rpos]] - c2)) pos = lpos; else pos = rpos; ans[id] = min(ans[id], r2 - r1 + abs(a[dd[pos]] - c2) + 1); rpos = Ubval(c2), lpos = rpos - 1; rpos = mianx(rpos, 0, lp); lpos = mianx(lpos, -1, lp - 1); ans[id] = min(ans[id], r2 + r1 + sr.get(0, lpos) + c2 + 1); ans[id] = min(ans[id], r2 + r1 + sl.get(rpos, lp - 1) - c2 + 1); int sp = min(Ubval(min(c1, a[dd[lp]])), lp); rpos = Ubval(c2), lpos = rpos - 1; rpos = mianx(rpos, 0, sp); lpos = mianx(lpos, -1, sp - 1); ans[id] = min(ans[id], r2 + r1 + sr.get(0, lpos) + c2); ans[id] = min(ans[id], r2 + r1 + sl.get(rpos, sp - 1) - c2); ++qid; } } dd.clear(); sl.init(); sr.init(); --qid; for (int i = (N); ((-1) > 0 ? i <= (1) : i >= (1)); i += (-1)) { while (((int)(dd).size()) && a[dd.back()] >= a[i]) dd.pop_back(); sl.add(((int)(dd).size()), a[i] + 2 * i); sr.add(((int)(dd).size()), -a[i] + 2 * i); int rp = ((int)(dd).size()); dd.push_back(i); while (~qid && q1[qid].r2 == i) { int id = q1[qid].id; int r1 = q1[qid].r1, c1 = q1[qid].c1; int r2 = q1[qid].r2, c2 = q1[qid].c2; int rpos = Ubval(c2), lpos = rpos - 1; rpos = mianx(rpos, 0, rp + 1); lpos = mianx(lpos, -1, rp); ans[id] = min(ans[id], sr.get(0, lpos) + c2 - r2 - r1 + 1); ans[id] = min(ans[id], sl.get(rpos, rp) - c2 - r2 - r1 + 1); int sp = min(Ubval(min(qj.get(r1, r2), c1)), rp); rpos = Ubval(c2), lpos = rpos - 1; rpos = mianx(rpos, 0, sp); lpos = mianx(lpos, -1, sp - 1); ans[id] = min(ans[id], sr.get(0, lpos) + c2 - r2 - r1); ans[id] = min(ans[id], sl.get(rpos, sp - 1) - c2 - r2 - r1); --qid; } } } int main() { scanf( %d , &N); for (int i = 1; i <= (N); ++i) scanf( %d , a + i); scanf( %d , &Q); memset(ans, Inf, sizeof(ans)); for (int i = 1; i <= (Q); ++i) { int r1, c1, r2, c2; scanf( %d%d%d%d , &r1, &c1, &r2, &c2); if (r1 <= r2) q1.push_back(Query(r1, c1, r2, c2, i)); else q2.push_back(Query(N - r1 + 1, c1, N - r2 + 1, c2, i)); } sort((q1).begin(), (q1).end()); solve(); reverse(a + 1, a + N + 1); sort((q2).begin(), (q2).end()); q2.swap(q1); solve(); for (int i = 1; i <= (Q); ++i) printf( %d n , ans[i]); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_pipe_misc.v
// Version : 1.11
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcieCore_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_1_V
`define SKY130_FD_SC_LS__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:42:11 01/30/2016
// Design Name: instruction_decode
// Module Name: /home/poche002/Desktop/ArqComp/Trabajo_final/arquitectura_tpf/instruction_decode_tb.v
// Project Name: arquitectura_tpf
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: instruction_decode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module instruction_decode_tb;
// Inputs
reg clk;
reg reset;
reg [31:0] pc_incrementado_in;
reg [31:0] instruction;
reg RegWrite;
reg [4:0] address_write;
reg [31:0] data_write;
// Outputs
wire [31:0] pc_incrementado_out;
wire [31:0] reg_data1;
wire [31:0] reg_data2;
wire [31:0] sgn_extend_data_imm;
wire [4:0] rd;
wire [4:0] rt;
wire wb_RegWrite_out;
wire wb_MemtoReg_out;
wire m_Branch_out;
wire m_MemRead_out;
wire m_MemWrite_out;
wire ex_RegDst_out;
wire ex_ALUOp0_out;
wire ex_ALUOp1_out;
wire ex_ALUSrc_out;
// Instantiate the Unit Under Test (UUT)
instruction_decode uut (
.clk(clk),
.reset(reset),
.pc_incrementado_in(pc_incrementado_in),
.instruction(instruction),
.RegWrite(RegWrite),
.address_write(address_write),
.data_write(data_write),
.pc_incrementado_out(pc_incrementado_out),
.reg_data1(reg_data1),
.reg_data2(reg_data2),
.sgn_extend_data_imm(sgn_extend_data_imm),
.rd(rd),
.rt(rt),
.wb_RegWrite_out(wb_RegWrite_out),
.wb_MemtoReg_out(wb_MemtoReg_out),
.m_Branch_out(m_Branch_out),
.m_MemRead_out(m_MemRead_out),
.m_MemWrite_out(m_MemWrite_out),
.ex_RegDst_out(ex_RegDst_out),
.ex_ALUOp0_out(ex_ALUOp0_out),
.ex_ALUOp1_out(ex_ALUOp1_out),
.ex_ALUSrc_out(ex_ALUSrc_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
pc_incrementado_in = 0;
instruction = 0;
RegWrite = 0;
address_write = 0;
data_write = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#5
begin
pc_incrementado_in = 32'b00000000_00000000_00000000_00000100;
instruction = 32'b00000000_00000000_00000000_00000000;
address_write = 5'b00100;
data_write = 1024;
end
#5 RegWrite = 1;
#3 RegWrite = 0;
#5 instruction = 32'b10001100_10000100_00000000_00000000;
#5 instruction = 32'b10101100_10000100_00000000_00000000;
#5 instruction = 32'b00010000_10000100_00000000_00000000;
end
always
#1 clk=~clk;
endmodule
|
`include "src/rom.v"
`include "src/serializer.v"
`include "src/transmitter.v"
`include "src/receiver.v"
`include "src/comparator.v"
`include "src/iserdes_sdr_ddr_test.v"
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led,
inout wire [9:0] io
);
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0])
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire CLK = clk;
wire RST = rst_sr[0];
// ============================================================================
// Test uints
wire [9:0] error;
genvar i;
generate for (i=0; i<10; i=i+1) begin
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_RATE = (i < 7) ? "SDR" : "DDR";
iserdes_sdr_ddr_test #
(
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE (DATA_RATE)
)
iserdes_test
(
.CLK (CLK),
.RST (RST),
.IO_DAT (io[i]),
.O_ERROR (error[i])
);
end endgenerate
// ============================================================================
// I/O connections
reg [23:0] heartbeat_cnt;
always @(posedge CLK)
heartbeat_cnt <= heartbeat_cnt + 1;
assign led[9: 0] = (RST) ? 9'd0 : ~error;
assign led[ 10] = heartbeat_cnt[22];
assign led[15:11] = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 50 + 5; const int oo = 1000000000; bool u[N][N]; int n, m; int ans = -1; int a[N][N], l[N][N]; int d[4][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; char s[N]; struct pis { int x, y; pis() {} pis(int x, int y) : x(x), y(y) {} } f[10 * N * N]; inline int Solve(int x, int y) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) l[i][j] = oo; int front = 0, top = 1; f[1] = pis(x, y); l[x][y] = 0; while (front < top) { pis p = f[++front]; u[p.x][p.y] = 0; for (int i = 0; i < 4; i++) { int dx = p.x + d[i][0]; int dy = p.y + d[i][1]; if (dx >= 1 && dx <= n && dy >= 1 && dy <= m) { int dis = a[p.x][p.y] != a[dx][dy]; if (l[p.x][p.y] + dis < l[dx][dy]) { l[dx][dy] = l[p.x][p.y] + dis; if (!u[dx][dy]) { u[dx][dy] = 1; f[++top] = pis(dx, dy); } } } } } int MAX = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (a[i][j] && l[i][j] > MAX) MAX = l[i][j]; return MAX; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , s); for (int j = 1; j <= m; j++) { if (s[j - 1] == B ) ans = oo; a[i][j] = s[j - 1] == W ? 0 : 1; } } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) ans = min(ans, Solve(i, j)); printf( %d n , ans + 1); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, tt[1005]; vector<int> a[1005]; void dfs(int u) { if (tt[u] == 1) { printf( %d , u); return; } tt[u] = 1; for (int i = 0; i < a[u].size(); ++i) dfs(a[u][i]); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); a[i].push_back(x); } for (int i = 1; i <= n; ++i) { dfs(i); for (int j = 1; j <= n; ++j) tt[j] = 0; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 5, mod = 1e9 + 7, inf = 1e18; long long n, q, a[maxn], mx[2ll][maxn]; pair<long long, long long> dp[2ll][maxn]; void cal_mx0(long long x) { long long l = n - 1ll, sum = a[n]; for (long long i = n; i > 0; i--) { if (l == 0) { mx[0][i] = 1; sum -= a[i]; continue; } while ((l > 0) && (sum + a[l] <= x)) { sum += a[l]; l--; } mx[0][i] = l + 1ll; sum -= a[i]; } } void cal_mx1(long long x) { long long r = 2ll, sum = a[1]; for (long long i = 1; i <= n; i++) { if (r == n + 1ll) { mx[1][i] = n; sum -= a[i]; continue; } while ((r <= n) && (sum + a[r] <= x)) { sum += a[r]; r++; } mx[1][i] = r - 1ll; sum -= a[i]; } } void cal_dp0() { long long sum = 0; for (long long i = 1; i <= n; i++) { sum += a[i]; if (mx[0][i] == 1) { dp[0][i] = {1, sum}; continue; } dp[0][i].first = dp[0][mx[0][i] - 1ll].first + 1ll; dp[0][i].second = dp[0][mx[0][i] - 1ll].second; } } void cal_dp1() { long long sum = 0; for (long long i = n; i > 0; i--) { sum += a[i]; if (mx[1][i] == n) { dp[1][i] = {1, sum}; continue; } dp[1][i].first = dp[1][mx[1][i] + 1ll].first + 1ll; dp[1][i].second = dp[1][mx[1][i] + 1ll].second; } } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> q; long long second = 0; for (long long i = 1; i <= n; i++) { cin >> a[i]; second += a[i]; } a[n + 1ll] = inf; a[0] = inf; while (q--) { long long x; cin >> x; if (x >= second) { cout << 1 << n ; continue; } cal_mx0(x); cal_mx1(x); cal_dp0(); cal_dp1(); long long ans = min(dp[0][n].first, dp[1][1].first); for (long long i = 1; i < n; i++) { long long z = 0; if ((dp[0][i].second + dp[1][i + 1ll].second) <= x) z = 1ll; ans = min(ans, dp[0][i].first + dp[1ll][i + 1ll].first - z); } cout << ans << n ; } }
|
#include <bits/stdc++.h> using namespace std; void in(long long int &number) { bool negative = false; register int c; number = 0; c = getchar(); if (c == - ) { negative = true; c = getchar(); } for (; (c > 47 && c < 58); c = getchar()) number = number * 10 + c - 48; if (negative) number *= -1; } void in(int &number) { bool negative = false; register int c; number = 0; c = getchar(); if (c == - ) { negative = true; c = getchar(); } for (; (c > 47 && c < 58); c = getchar()) number = number * 10 + c - 48; if (negative) number *= -1; } int k[100005]; int main() { int n, m; in(n); in(m); memset(k, 0, sizeof(k)); vector<long long int> a(n); for (int i = 0; i <= n - 1; i++) in(a[i]); vector<int> dp(n); dp[n - 1] = 1; k[a[n - 1]] = 1; for (int i = n - 2; i >= 0; i--) { if (k[a[i]] == 0) { dp[i] = dp[i + 1] + 1; k[a[i]] = 1; } else dp[i] = dp[i + 1]; } while (m--) { int l; in(l); l--; cout << dp[l] << n ; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_lp__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_lp__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_V
|
module memory(address,in,out,write,clk);
input [7:0] in;
input clk,write;
input [14:0] address;
output [7:0] out;
reg [7:0] mem [0:255];
reg [14:0] addreg;
always @(negedge clk)
begin
if(write ==1'b0)
begin
mem[address] <= in;
addreg <= address;
end
end
assign out = mem[addreg];
endmodule
module mem16(address, write,clk, in, out,ir14);
input [15:0] in;
input [15:0] address;
input write,clk,ir14;
output reg [15:0] out;
reg wreven,wrodd;
reg[15:0] addreg;
always @(*)
begin
addreg<= address;
end
reg [7:0] outeven,outodd,ineven,inodd;
memory even(.address(address[15:1]),.in(ineven),.out(outeven),.clk(clk),.write(wreven));
memory odd (.address(address[15:1]),.in(ineven),.out(outeven),.clk(clk),.write(wrodd));
//for in signals of individual memories
always @(*)
begin
if(ir14==0)
begin
ineven<=in;
inodd<=in;
end
else
begin
ineven<= in[7:0];
inodd<=in[15:8];
end
end
//-----------------------------------------------
//for out signals of indicidual memories
always @(*)
begin
if(ir14 ==1'b1)
begin
out[15:8]<=outodd;
out[7:0]<=outeven;
end
else
if(addreg[0]==0)
begin
out<= {{8{outeven[7]}},outeven[7:0]};
end
else
begin
out<= {{8{outodd[7]}},outodd[7:0]};
end
end
//-------------------------------------------------
//for write signal
always @(*)
begin
if(ir14==0&&addreg[0]==1'b1)
begin
wreven<=1'b1;
end
else
begin
wreven<=write;
end
end
always @(*)
begin
if(ir14==0&&addreg[0]==1'b0)
begin
wrodd<=1'b1;
end
else
begin
wrodd<=write;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbdblpriarb.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This should almost be identical to the priority arbiter, save
// for a simple diffence: it allows the arbitration of two
// separate wishbone buses. The purpose of this is to push the address
// resolution back one cycle, so that by the first clock visible to this
// core, it is known which of two parts of the bus the desired address
// will be on, save that we still use the arbiter since the underlying
// device doesn't know that there are two wishbone buses.
//
// So at this point we've deviated from the WB spec somewhat, by allowing
// two CYC and two STB lines. Everything else is the same. This allows
// (in this case the Zip CPU) to determine whether or not the access
// will be to the local ZipSystem bus or the external WB bus on the clock
// before the local bus access, otherwise peripherals were needing to do
// multiple device selection comparisons/test within a clock: 1) is this
// for the local or external bus, and 2) is this referencing me as a
// peripheral. This then caused the ZipCPU to fail all timing specs.
// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the
// determination of local vs external can be made one clock earlier
// where there's still time for the logic, and the second comparison
// now has time to complete.
//
// So let me try to explain this again. To use this arbiter, one of the
// two masters sets CYC and STB before, only the master determines which
// of two address spaces the CYC and STB apply to before the clock and
// only sets the appropriate CYC and STB lines. Then, on the clock tick,
// the arbiter determines who gets *both* busses, as they both share every
// other WB line. Thus, only one of CYC_A and CYC_B going out will ever
// be high at a given time.
//
// Hopefully this makes more sense than it sounds. If not, check out the
// code below for a better explanation.
//
// 20150919 -- Added supported for the WB error signal.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbdblpriarb(i_clk, i_rst,
// Bus A
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
// Bus B
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
// Both buses
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel,
i_ack, i_stall, i_err);
parameter DW=32, AW=32;
// Wishbone doesn't use an i_ce signal. While it could, they dislike
// what it would (might) do to the synchronous reset signal, i_rst.
input wire i_clk, i_rst;
// Bus A
input wire i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
input wire [(AW-1):0] i_a_adr;
input wire [(DW-1):0] i_a_dat;
input wire [(DW/8-1):0] i_a_sel;
output wire o_a_ack, o_a_stall, o_a_err;
// Bus B
input wire i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
input wire [(AW-1):0] i_b_adr;
input wire [(DW-1):0] i_b_dat;
input wire [(DW/8-1):0] i_b_sel;
output wire o_b_ack, o_b_stall, o_b_err;
//
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
output wire [(AW-1):0] o_adr;
output wire [(DW-1):0] o_dat;
output wire [(DW/8-1):0] o_sel;
input wire i_ack, i_stall, i_err;
// All of our logic is really captured in the 'r_a_owner' register.
// This register determines who owns the bus. If no one is requesting
// the bus, ownership goes to A on the next clock. Otherwise, if B is
// requesting the bus and A is not, then ownership goes to not A on
// the next clock. (Sounds simple ...)
//
// The CYC logic is here to make certain that, by the time we determine
// who the bus owner is, we can do so based upon determined criteria.
reg r_a_owner;
assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
initial r_a_owner = 1'b1;
always @(posedge i_clk)
if (i_rst)
r_a_owner <= 1'b1;
/*
// Remain with the "last owner" until 1) the other bus requests
// access, and 2) the last owner no longer wants it. This
// logic "idles" on the last owner.
//
// This is an alternating bus owner strategy
//
else if ((!o_cyc_a)&&(!o_cyc_b))
r_a_owner <= ((i_b_stb_a)||(i_b_stb_b))? 1'b0:1'b1;
//
// Expanding this out
//
// else if ((r_a_owner)&&((i_a_cyc_a)||(i_a_cyc_b)))
// r_a_owner <= 1'b1;
// else if ((!r_a_owner)&&((i_b_cyc_a)||(i_b_cyc_b)))
// r_a_owner <= 1'b0;
// else if ((r_a_owner)&&((i_b_stb_a)||(i_b_stb_b)))
// r_a_owner <= 1'b0;
// else if ((!r_a_owner)&&((i_a_stb_a)||(i_a_stb_b)))
// r_a_owner <= 1'b0;
//
// Logic required:
//
// Reset line
// + 9 inputs (data)
// + 9 inputs (CE)
// Could be done with three LUTs
// First two evaluate o_cyc_a and o_cyc_b (above)
*/
// Option 2:
//
// "Idle" on A as the owner.
// If a request is made from B, AND A is idle, THEN
// switch. Otherwise, if B is ever idle, revert back to A
// regardless of whether A wants it or not.
else if ((!i_b_cyc_a)&&(!i_b_cyc_b))
r_a_owner <= 1'b1;
else if ((!i_a_cyc_a)&&(!i_a_cyc_b)
&&((i_b_stb_a)||(i_b_stb_b)))
r_a_owner <= 1'b0;
assign o_we = (r_a_owner) ? i_a_we : i_b_we;
`ifdef ZERO_ON_IDLE
//
// ZERO_ON_IDLE uses more logic than the alternative. It should be
// useful for reducing power, as these circuits tend to drive wires
// all the way across the design, but it may also slow down the master
// clock. I've used it as an option when using VERILATOR, 'cause
// zeroing things on idle can make them stand out all the more when
// staring at wires and dumps and such.
//
wire o_cyc, o_stb;
assign o_cyc = ((o_cyc_a)||(o_cyc_b));
assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b));
assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a);
assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b);
assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0;
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0;
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0;
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
`else
// Realistically, if neither master owns the bus, the output is a
// don't care. Thus we trigger off whether or not 'A' owns the bus.
// If 'B' owns it all we care is that 'A' does not. Likewise, if
// neither owns the bus than the values on these various lines are
// irrelevant.
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
// We cannot allow the return acknowledgement to ever go high if
// the master in question does not own the bus. Hence we force it
// low if the particular master doesn't own the bus.
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
// Stall must be asserted on the same cycle the input master asserts
// the bus, if the bus isn't granted to him.
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
//
// These error lines will be implemented soon, as soon as the rest of
// the Zip CPU is ready to support them.
//
assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
`endif
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:66777216 ) using namespace std; static unsigned rnd() { static int second = 124612741; second ^= second << 13; second ^= second >> 17; return second ^= second << 5; } inline int fpow(int a, int st, int mod) { int ans = 1; while (st) { if (st % 2) ans = (long long)ans * a % mod; a = (long long)a * a % mod; st /= 2; } return ans; } int invmod(int first, int second) { int a = 1, b = 0, k; for (; second; swap(first, second), swap(a, b)) { k = first / second; first -= second * k; a -= b * k; } return a + max(b, 0); } inline int calcBits(int a) { return __builtin_popcount(a); } struct Hash { Hash() : x1(0), x2(0) {} Hash(const int& x1, const int& x2) : x1(x1), x2(x2) {} int x1, x2; static int mod1, mod2; static int p1, p2; static int invp1, invp2; static bool initCalled; static const Hash ONE, ZERO, INVALID; static Hash UNIT, INV_UNIT; static bool prime(int a) { if (a == 1) return 0; for (int i = 2; i * i <= a; ++i) { if (a % i == 0) return false; } return true; } static int pickModHelper(int start, int bad) { int mn = 1000000000, best = -1; for (int _n(start + 10000), i(start); i <= _n; i++) { if (i == bad || !prime(i)) continue; int cur = calcBits(i); if (cur < mn) { mn = cur; best = i; } } return best; } static void init() { if (initCalled) return; initCalled = true; mod1 = pickModHelper(1000000000 + rnd() % 10000000, -1); while (!prime(mod1)) ++mod1; mod2 = pickModHelper(1000000000 + rnd() % 10000000, mod1); invp1 = fpow(p1, mod1 - 2, mod1); invp2 = fpow(p2, mod2 - 2, mod2); INV_UNIT = Hash(invp1, invp2); } inline Hash& operator+=(const Hash& other) { x1 += other.x1; if (x1 >= Hash::mod1) x1 -= Hash::mod1; x2 += other.x2; if (x2 >= Hash::mod2) x2 -= Hash::mod2; return *this; } inline Hash& operator-=(const Hash& other) { x1 -= other.x1; if (x1 < 0) x1 += Hash::mod1; x2 -= other.x2; if (x2 < 0) x2 += Hash::mod2; return *this; } inline Hash& operator*=(const Hash& other) { x1 = (long long)x1 * other.x1 % Hash::mod1; x2 = (long long)x2 * other.x2 % Hash::mod2; return *this; } inline Hash& operator*=(const int& other) { x1 = (long long)x1 * other % Hash::mod1; x2 = (long long)x2 * other % Hash::mod2; return *this; } inline Hash& operator^=(const int& power) { int st = power; Hash ans(1, 1); while (st) { if (st % 2) ans *= *this; x1 = (long long)x1 * x1 % Hash::mod1; x2 = (long long)x2 * x2 % Hash::mod2; st /= 2; } return *this; } inline bool operator==(const Hash& other) const { return x1 == other.x1 && x2 == other.x2; } }; bool Hash::initCalled = false; int Hash::mod1 = 0; int Hash::mod2 = 0; int Hash::p1 = 23561; int Hash::p2 = 10000019; int Hash::invp1 = -1; int Hash::invp2 = -1; const Hash Hash::ONE(1, 1); const Hash Hash::ZERO(0, 0); const Hash Hash::INVALID(-1, -1); Hash Hash::UNIT(Hash::p1, Hash::p2); Hash Hash::INV_UNIT(-1, -1); inline Hash operator+(const Hash& a, const Hash& b) { Hash ans(a.x1 + b.x1, a.x2 + b.x2); if (ans.x1 >= Hash::mod1) ans.x1 -= Hash::mod1; if (ans.x2 >= Hash::mod2) ans.x2 -= Hash::mod2; return ans; } inline Hash operator-(const Hash& a, const Hash& b) { Hash ans(a.x1 - b.x1, a.x2 - b.x2); if (ans.x1 < 0) ans.x1 += Hash::mod1; if (ans.x2 < 0) ans.x2 += Hash::mod2; return ans; } inline Hash operator*(const Hash& a, const Hash& b) { return Hash((long long)a.x1 * b.x1 % Hash::mod1, (long long)a.x2 * b.x2 % Hash::mod2); } inline Hash operator*(const Hash& a, const int& b) { return Hash((long long)a.x1 * b % Hash::mod1, (long long)a.x2 * b % Hash::mod2); } inline Hash operator^(const Hash& a, const int& power) { int st = power; Hash ans(1, 1), cur(a); while (st) { if (st % 2) ans *= cur; cur *= cur; st /= 2; } return ans; } inline Hash fpow(const Hash& a, const int& power) { return a ^ power; } inline Hash invmod(const Hash& a) { return Hash(invmod(a.x1, Hash::mod1), invmod(a.x2, Hash::mod2)); } template <class H> struct HashString : public string { HashString() : string() { precalc(0); } HashString(const HashString& other) : string(other) { precalc(size()); } HashString(HashString&& other) : hh(std::move(other.hh)), string(std::move(other)) { precalc(size()); } HashString(const string& other) : string(other) { precalc(size()); build(); } HashString(string&& other) : string(std::move(other)) { precalc(size()); build(); } HashString(const char* other) : string(other) { precalc(size()); build(); } inline void clear() { hh.clear(); string::clear(); } inline static H getPow(int p) { if (p < haveN) { return pp[p]; } else { return fpow(H::UNIT, p); } } inline static H getInvPow(size_t p) { if (p < invpp.size()) { return invpp[p]; } else { return fpow(H::INV_UNIT, p); } } inline H getInvRegister(const H& p) const { if (p == register_) { return registerValue_; } else { register_ = p; return registerValue_ = invmod(p); } } static void precalc(int N = 0) { Hash::init(); if (haveN >= N) return; pp.resize(N); invpp.resize(N); if (!haveN) { pp[0] = H::ONE; invpp[0] = H::ONE; haveN = 1; } for (int i = haveN; i < N; ++i) { pp[i] = pp[i - 1] * H::UNIT; invpp[i] = invpp[i - 1] * H::INV_UNIT; } haveN = N; } inline void build() { int curSize = size(); if (haveN <= curSize) { precalc(curSize); } for (int i = hh.size(); i < curSize; ++i) { H pr = i ? hh.back() : H::ZERO; hh.push_back(pr + getPow(i) * (*this)[i]); } } inline H getHash(int pos, int len) const { if (len <= 0) return H::ZERO; const int S = size(); if (pos + len - 1 < S) { H ans = hh[pos + len - 1]; if (pos) { ans -= hh[pos - 1]; ans *= getInvPow(pos); } return ans; } else { H head = hh.back(); if (pos) { head -= hh[pos - 1]; head *= getInvPow(pos); } int full = -1, en = -1; H mid = H::ZERO; int midlen = 0; if (len <= S) { en = pos + len - 1 - S; H tail = hh[en]; full = 0; return head + tail * getPow(S - pos); } else { en = (pos + len - 1) % S; H tail = hh[en]; full = (len - (S - pos) - (en + 1)) / S; mid = hh.back() * (H::ONE - getInvPow(full * S)) * getInvRegister(H::ONE - getInvPow(S)); return head + mid * getPow(S - pos) + tail * getPow(len - (en + 1)); } } } inline HashString& operator+=(const char& ch) { string::operator+=(ch); build(); return *this; } inline HashString& operator+=(const HashString& other) { string::operator+=(other); build(); return *this; } inline bool operator==(const HashString& other) const { return hh.back() == other.hh.back(); } inline bool operator<(const HashString& other) const { int s1 = size(); int s2 = other.size(); const int S = min(s1, s2); int l = 0, r = S + 1; while (r - l > 1) { int xx = (r + l) / 2; if (getHash(0, xx) == other.getHash(0, xx)) l = xx; else r = xx; } char c1 = 0, c2 = 0; if (l < s1) c1 = (*this)[l]; if (l < s2) c2 = other[l]; return c1 < c2; } inline bool operator<=(const HashString& other) const { return (*this == other) || (*this < other); } inline bool operator>(const HashString& other) const { return !(*this == other) && !(*this < other); } inline bool operator>=(const HashString& other) const { return !(*this < other); } inline bool operator!=(const HashString& other) const { return !(*this == other); } inline void reserve(int N) { hh.reserve(N); string::reserve(N); } vector<H> hh; static vector<H> pp, invpp; private: mutable H register_, registerValue_; static int haveN; }; template <> int HashString<Hash>::haveN = 0; template <> vector<Hash> HashString<Hash>::pp = vector<Hash>(); template <> vector<Hash> HashString<Hash>::invpp = vector<Hash>(); template <class H, bool cyclic = true> struct HashStringPiece { explicit HashStringPiece(const HashString<H>& s, int pos, int len) : s(s), pos(pos), len(len), hash(H::INVALID) {} inline H getHash() const { if (hash == H::INVALID) hash = s.getHash(pos, len); return hash; } inline H getPartialHash(int needLen) const { return s.getHash(pos, needLen); } inline char getChar(int i) const { i += pos; const int S = s.size(); if (i < S) return s[i]; if (!cyclic) return 0; i -= S; if (i < S) return s[i]; return s[i % S]; } const HashString<H>& s; const int pos, len; mutable H hash; }; template <class H, class T> char getHSPRangeChar(T beg, T en, int pos) { for (T it = beg; it != en; ++it) { if (pos < it->len) { return it->getChar(pos); } pos -= it->len; } return 0; } template <class H, class T> H getHSPRangeHash(T beg, T en, int len) { H ans = H::ZERO; int cur = 0; for (T it = beg; it != en; ++it) { if (len >= it->len) { ans += it->getHash() * it->s.getPow(cur); cur += it->len; len -= it->len; } else { ans += it->getPartialHash(len) * it->s.getPow(cur); break; } } return ans; } int TB, IT; template <class H, class T> inline int compareHSPRanges(T beg1, T en1, int len1, T beg2, T en2, int len2) { if (beg1 == en1 && beg2 == en2) return 0; if (beg1 == en1) return -1; if (beg2 == en2) return 1; int l = 0, r = min(len1, len2) + 1; while (r - l > 1) { int xx = (r + l) / 2; auto h1 = getHSPRangeHash<H, T>(beg1, en1, xx); auto h2 = getHSPRangeHash<H, T>(beg2, en2, xx); if (h1 == h2) l = xx; else r = xx; } char c1 = getHSPRangeChar<H, T>(beg1, en1, l); char c2 = getHSPRangeChar<H, T>(beg2, en2, l); if (c1 < c2) return -1; else if (c1 == c2) return 0; else return 1; } template <class H, class T> inline int compareHSPRanges(T beg1, T en1, T beg2, T en2) { int len1 = 0; for (T it = beg1; it != en1; ++it) { len1 += it->len; } int len2 = 0; for (T it = beg2; it != en2; ++it) { len2 += it->len; } return compareHSPRanges<H, T>(beg1, en1, len1, beg2, en2, len2); } int a, b, c, d, n, m, k; char str[1000002]; int bal[2000002]; HashString<Hash> s; inline string build(pair<pair<int, int>, int> a) { string ans = ; for (int _n((a.first.first) - 1), i(0); i <= _n; i++) ans += ( ; for (int _n((n)-1), i(0); i <= _n; i++) { int cur = a.second + i; if (cur >= n) cur -= n; ans += str[cur]; } for (int _n((a.first.second) - 1), i(0); i <= _n; i++) ans += ) ; return ans; } HashString<Hash> op, cl; inline bool better(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b, const HashString<Hash>& s) { HashStringPiece<Hash> A[3] = {HashStringPiece<Hash>(op, 0, a.first.first), HashStringPiece<Hash>(s, a.second, n), HashStringPiece<Hash>(cl, 0, a.first.second)}; HashStringPiece<Hash> B[3] = {HashStringPiece<Hash>(op, 0, b.first.first), HashStringPiece<Hash>(s, b.second, n), HashStringPiece<Hash>(cl, 0, b.first.second)}; int t = compareHSPRanges<Hash>(A, A + 3, B, B + 3); if (t == -1) return 1; else return 0; } int main() { gets(str); n = (int)strlen(str); HashString<Hash> s(str); HashString<Hash>::precalc(2 * n + 1); op.reserve(n + 1); cl.reserve(n + 1); for (int _n((n)-1), i(0); i <= _n; i++) { op += ( ; cl += ) ; } c = 0; for (int _n((n)-1), i(0); i <= _n; i++) { if (str[i] == ( ) ++c; else --c; } bal[0] = 0; for (int _n((2 * n) - 1), i(0); i <= _n; i++) { if (i) bal[i] = bal[i - 1]; int cur = i; if (i >= n) cur = i - n; if (str[cur] == ( ) ++bal[i]; else --bal[i]; } int blen = 1000000000; pair<pair<int, int>, int> best = make_pair(make_pair(0, 0), 0); stack<pair<int, int> > s1, s2; for (int _n((n)-1), i(0); i <= _n; i++) { int new_element = bal[i]; int minima = s1.empty() ? new_element : min(new_element, s1.top().second); s1.push(make_pair(new_element, minima)); } for (int _n((n)-1), cyc(0); cyc <= _n; cyc++) { int current_minimum = -1000000000; if (s1.empty() || s2.empty()) current_minimum = s1.empty() ? s2.top().second : s1.top().second; else current_minimum = min(s1.top().second, s2.top().second); int p = 0; if (cyc) p = bal[cyc - 1]; int mn = current_minimum - p; int beg = max(0, -mn); int en = c + beg; int len = beg + en + n; if (len < blen || (len == blen && better(make_pair(make_pair(beg, en), cyc), best, s))) { blen = len; best = make_pair(make_pair(beg, en), cyc); } if (s2.empty()) { while (!s1.empty()) { int element = s1.top().first; s1.pop(); int minima = s2.empty() ? element : min(element, s2.top().second); s2.push(make_pair(element, minima)); } } s2.pop(); int new_element = bal[cyc + n]; int minima = s1.empty() ? new_element : min(new_element, s1.top().second); s1.push(make_pair(new_element, minima)); } string ans = build(best); printf( %s n , ans.c_str()); }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, lim = 1e7 + 10, key = 1010; int v[lim], r[lim], d[lim]; int main() { int n, m, q; scanf( %d%d%d , &n, &m, &q); for (long long i = 1, _b = (n); i <= _b; i++) for (long long j = 1, _b = (m); j <= _b; j++) scanf( %d , v + key * i + j); for (long long i = 0, _b = (n); i <= _b; i++) for (long long j = 0, _b = (m); j <= _b; j++) { r[key * i + j] = key * i + (j + 1); d[key * i + j] = key * (i + 1) + j; } int _a, _b, _c, _d, h, w; int x, y, x0, y0; for (long long i = 0, _n = (q); i < _n; i++) { scanf( %d%d%d%d%d%d , &_a, &_b, &_c, &_d, &h, &w); x0 = 0; while (--_a) x0 = d[x0]; while (--_b) x0 = r[x0]; y0 = 0; while (--_c) y0 = d[y0]; while (--_d) y0 = r[y0]; x = x0, y = y0; for (long long j = 0, _n = (h); j < _n; j++) x = d[x], y = d[y], swap(r[x], r[y]); for (long long j = 0, _n = (w); j < _n; j++) x = r[x], y = r[y], swap(d[x], d[y]); x = x0, y = y0; for (long long j = 0, _n = (w); j < _n; j++) x = r[x], y = r[y], swap(d[x], d[y]); for (long long j = 0, _n = (h); j < _n; j++) x = d[x], y = d[y], swap(r[x], r[y]); } x0 = 0; for (long long i = 0, _n = (n); i < _n; i++) { x0 = d[x0]; x = x0; for (long long j = 0, _n = (m); j < _n; j++) x = r[x], printf( %d , v[x]); putchar( n ); } return 0; }
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#include <bits/stdc++.h> const long long N = 2e5 + 7; const long long M = 2e4 + 5; const double eps = 1e-8; const long long mod = 1e9 + 7; const long long inf = 0x7fffffff; const double pi = 3.1415926; using namespace std; vector<long long> v[N], num; long long n; long long dfs(long long x, long long fa) { long long sum = 1; for (long long i = 0; i < v[x].size(); i++) { if (v[x][i] == fa) continue; sum += dfs(v[x][i], x); } if (x != 1) num.push_back((n - sum) * sum); return sum; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { cin >> n; for (long long i = 0; i <= n; i++) v[i].clear(); num.clear(); for (long long i = 1; i < n; i++) { long long x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } long long m; cin >> m; vector<long long> p; for (long long i = 0; i < m; i++) { long long c; cin >> c; p.push_back(c); } dfs(1, -1); if (m < n - 1) { for (long long i = 0; i < n - 1 - m; i++) p.push_back(1); } sort(num.begin(), num.end()); sort(p.begin(), p.end()); long long ans = 0; if (m <= n - 1) { for (long long i = 0; i < n - 1; i++) { ans += (num[i] * p[i]) % mod; ans %= mod; } } else { for (long long i = 0; i < n - 2; i++) { ans += (num[i] * p[i]) % mod; ans %= mod; } long long add = 1; for (long long i = n - 2; i < m; i++) { add = (add * p[i]) % mod; } ans += (add * num[n - 2]) % mod; ans %= mod; } cout << ans << endl; } return 0; }
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/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module clock_generator (
// inputs
CLOCK2_50,
reset,
// outputs
AUD_XCK
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_CLK_MULT = 14;
parameter AUD_CLK_DIV = 31;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK2_50;
input reset;
// Outputs
output AUD_XCK;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire audio_clk_locked;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_Audio (
.inclk ({1'b0, CLOCK2_50}),
.clk (AUD_XCK),
.locked (audio_clk_locked),
.activeclock (),
.areset (reset),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_Audio.clk0_divide_by = AUD_CLK_DIV,
DE_Clock_Generator_Audio.clk0_duty_cycle = 50,
DE_Clock_Generator_Audio.clk0_multiply_by = AUD_CLK_MULT,
DE_Clock_Generator_Audio.clk0_phase_shift = "0",
DE_Clock_Generator_Audio.compensate_clock = "CLK0",
DE_Clock_Generator_Audio.gate_lock_signal = "NO",
DE_Clock_Generator_Audio.inclk0_input_frequency = 37037,
DE_Clock_Generator_Audio.intended_device_family = "Cyclone II",
DE_Clock_Generator_Audio.invalid_lock_multiplier = 5,
DE_Clock_Generator_Audio.lpm_type = "altpll",
DE_Clock_Generator_Audio.operation_mode = "NORMAL",
DE_Clock_Generator_Audio.pll_type = "FAST",
DE_Clock_Generator_Audio.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_areset = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_inclk0 = "PORT_USED",
DE_Clock_Generator_Audio.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_locked = "PORT_USED",
DE_Clock_Generator_Audio.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk0 = "PORT_USED",
DE_Clock_Generator_Audio.port_clk1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_Audio.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_Audio.valid_lock_multiplier = 1;
endmodule
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// Benchmark "mult4" written by ABC on Tue Jan 13 21:29:40 2015
module mult4 (
a0, a1, a2, a3, b0, b1, b2, b3,
z0, z1, z2, z3, z4, z5, z6, z7 );
input a0, a1, a2, a3, b0, b1, b2, b3;
output z0, z1, z2, z3, z4, z5, z6, z7;
wire n18, n19, n20, n21, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32,
n33, n34, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n125, n126, n127, n128;
assign z0 = a0 & b0;
assign n18 = a1 & b0;
assign n19 = a0 & b1;
assign n20 = ~n18 & n19;
assign n21 = n18 & ~n19;
assign z1 = n20 | n21;
assign n23 = n18 & n19;
assign n24 = a1 & b2;
assign n25 = a0 & b2;
assign n26 = ~n24 & n25;
assign n27 = n24 & ~n25;
assign n28 = ~n26 & ~n27;
assign n29 = n23 & n28;
assign n30 = ~n23 & ~n28;
assign n31 = ~n29 & ~n30;
assign n32 = a2 & b0;
assign n33 = n31 & n32;
assign n34 = ~n31 & ~n32;
assign z2 = n33 | n34;
assign n36 = n24 & n25;
assign n37 = n23 & n24;
assign n38 = ~n36 & ~n37;
assign n39 = n23 & n25;
assign n40 = n38 & ~n39;
assign n41 = a0 & b3;
assign n42 = ~n24 & n41;
assign n43 = n24 & ~n41;
assign n44 = ~n42 & ~n43;
assign n45 = ~n40 & n44;
assign n46 = n40 & ~n44;
assign n47 = ~n45 & ~n46;
assign n48 = ~n31 & n32;
assign n49 = a2 & b1;
assign n50 = n47 & n49;
assign n51 = ~n47 & ~n49;
assign n52 = ~n50 & ~n51;
assign n53 = n48 & n52;
assign n54 = ~n48 & ~n52;
assign n55 = ~n53 & ~n54;
assign n56 = a3 & b0;
assign n57 = n55 & n56;
assign n58 = ~n55 & ~n56;
assign z3 = n57 | n58;
assign n60 = n24 & n41;
assign n61 = n24 & ~n40;
assign n62 = ~n60 & ~n61;
assign n63 = ~n40 & n41;
assign n64 = n62 & ~n63;
assign n65 = a1 & b3;
assign n66 = ~n64 & ~n65;
assign n67 = n64 & n65;
assign n68 = ~n66 & ~n67;
assign n69 = n49 & n68;
assign n70 = ~n49 & ~n68;
assign n71 = ~n69 & ~n70;
assign n72 = n48 & n71;
assign n73 = ~n48 & ~n71;
assign n74 = ~n72 & ~n73;
assign n75 = ~n55 & n56;
assign n76 = a3 & b1;
assign n77 = n74 & n76;
assign n78 = ~n74 & ~n76;
assign n79 = ~n77 & ~n78;
assign n80 = n75 & n79;
assign n81 = ~n75 & ~n79;
assign z4 = n80 | n81;
assign n83 = ~n64 & n65;
assign n84 = n48 & n49;
assign n85 = n49 & ~n68;
assign n86 = n48 & ~n68;
assign n87 = ~n85 & ~n86;
assign n88 = ~n84 & n87;
assign n89 = a2 & b3;
assign n90 = ~n83 & n89;
assign n91 = n83 & ~n89;
assign n92 = ~n90 & ~n91;
assign n93 = ~n88 & n92;
assign n94 = n88 & ~n92;
assign n95 = ~n93 & ~n94;
assign n96 = n75 & n76;
assign n97 = ~n74 & n76;
assign n98 = ~n74 & n75;
assign n99 = ~n97 & ~n98;
assign n100 = ~n96 & n99;
assign n101 = a3 & b2;
assign n102 = n95 & n101;
assign n103 = ~n95 & ~n101;
assign n104 = ~n102 & ~n103;
assign n105 = ~n100 & n104;
assign n106 = n100 & ~n104;
assign z5 = n105 | n106;
assign n108 = ~n88 & n89;
assign n109 = n83 & n89;
assign n110 = n83 & ~n88;
assign n111 = ~n109 & ~n110;
assign n112 = ~n108 & n111;
assign n113 = ~n100 & n101;
assign n114 = ~n95 & n101;
assign n115 = ~n95 & ~n100;
assign n116 = ~n114 & ~n115;
assign n117 = ~n113 & n116;
assign n118 = a3 & b3;
assign n119 = n112 & n118;
assign n120 = ~n112 & ~n118;
assign n121 = ~n119 & ~n120;
assign n122 = ~n117 & n121;
assign n123 = n117 & ~n121;
assign z6 = n122 | n123;
assign n125 = ~n117 & n118;
assign n126 = ~n112 & n118;
assign n127 = ~n112 & ~n117;
assign n128 = ~n126 & ~n127;
assign z7 = n125 | ~n128;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n, m, *a, *b, times, i, day; while (cin >> n >> m) { a = new int[m]; b = new int[m]; times = 1; for (i = 0; i < m; i++) cin >> a[i] >> b[i]; for (i = 0; i < m - 1; i++) { if (b[i] != a[i + 1] - 1) break; } if (i + 1 == m && b[i] == n) cout << OK << endl; else { if (a[0] != 1) { day = 1; times--; } else if (b[i] == a[i + 1]) { day = b[i]; while (b[i] == a[i + 1] && b[i] == day) { times++; i++; } } else { day = b[i] + 1; times--; } cout << day << << times << endl; } delete[] a; delete[] b; } return 0; }
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#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; const int mx = 2e5 + 9; int game[2][mx]; int f_occ[2][mx]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); x--; game[x][i]++; } memset(f_occ, -1, sizeof f_occ); for (auto x : {0, 1}) { for (int i = 1; i <= n; i++) { game[x][i] += game[x][i - 1]; if (f_occ[x][game[x][i]] != -1) continue; f_occ[x][game[x][i]] = i; } } vector<pii> ans; for (int t = 1; t <= n; t++) { int s = 0; int last[] = {0, 0}; int win[] = {0, 0}; int idx = 0; int latest = -1; while (true) { int next[] = {0, 0}; for (auto x : {0, 1}) next[x] = last[x] + t; int f[] = {0, 0}; for (auto x : {0, 1}) f[x] = f_occ[x][next[x]]; if (f[0] == -1 and f[1] == -1) break; if (f[0] == -1) { last[0] = game[0][f[1]]; last[1] = game[1][f[1]]; idx = f[1]; win[1]++; latest = 1; continue; } if (f[1] == -1) { last[0] = game[0][f[0]]; last[1] = game[1][f[0]]; idx = f[0]; win[0]++; latest = 0; continue; } if (f[0] < f[1]) { last[0] = game[0][f[0]]; last[1] = game[1][f[0]]; idx = f[0]; win[0]++; latest = 0; } else { last[0] = game[0][f[1]]; last[1] = game[1][f[1]]; idx = f[1]; win[1]++; latest = 1; } } if (idx != n) continue; if (win[0] == win[1]) continue; if (win[latest] < win[1 - latest]) continue; s = win[latest]; ans.emplace_back(s, t); } sort(ans.begin(), ans.end()); printf( %d n , (int)ans.size()); for (auto [s, t] : ans) { printf( %d %d n , s, t); } }
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#include <bits/stdc++.h> using namespace std; void addmod(int &a, long long b) { a = (a + b); if (a >= 1000000007) a -= 1000000007; } void mulmod(int &a, long long b) { a = (a * b) % 1000000007; } int gi() { int a; scanf( %d , &a); return a; } long long gll() { long long a; scanf( %lld , &a); return a; } class rangesum { vector<long long> s; public: rangesum(const vector<int> &inp, const int &n) { s.resize(n + 1); for (int i = 0; i < n; i++) s[i + 1] = s[i] + inp[i]; } long long get(int x, int y) { return s[y + 1] - s[x]; } }; int main() { int n = gi(), l, u; vector<int> a(n); for (auto i = 0; i < n; i++) { a[i] = gi(); } rangesum rs(a, n); set<int> rm; multiset<long long, greater<long long>> v; rm.insert(-1); rm.insert(n); v.insert(rs.get(0, n - 1)); for (int i = 0; i < n; i++) { int ix = gi() - 1; auto it = rm.upper_bound(ix); u = (*it) - 1; it--; l = (*it) + 1; auto mit = v.find(rs.get(l, u)); assert(mit != v.end()); v.erase(mit); if (ix > l) v.insert(rs.get(l, ix - 1)); if (ix < u) v.insert(rs.get(ix + 1, u)); rm.insert(ix); printf( %lld n , (v.size() ? *v.begin() : 0)); } return 0; }
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#include <bits/stdc++.h> using namespace std; #define ll long long #define ld long double #define vi vector<int> #define pi pair<int,int> #define F first #define S second #define pb push_back #define mp make_pair #define FOR for(int i=a;i<b;++i) #define sq(a) (a)*(a) #define vll vector<long long> const int inf=INT_MAX; const ll INF=LLONG_MAX; const int MOD=1000000007; //char-48 int dp[100000]; int main(){ ios::sync_with_stdio(0); cin.tie(0); ll t; cin >> t; while(t--){ ll n, ans=0; cin >> n; vector<ll> v; for(ll i=0;i<n;++i){ ll u; cin >> u; v.pb(u); ans=max(ans,u); } sort(v.begin(), v.end()); ll b=v.size()-1; ll g=b; for(ll i=0; i<b; ++i){ ans+=(v[i]-v[i+1])*(g*(i+1)); --g; } cout << ans << n ; } } //Erase reps // sort(v.begin(), v.end() ); // v.erase(unique(v.begin(), v.end() ), v.end()); //Find something to eliminate // auto i = find(begin(s), end(s), { ); // s.erase(i);
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#include <bits/stdc++.h> using namespace std; int n, m, k, ans, x, y, sum, res, day1, day2, moun1, moun2, year1, year2; bool l; char a[100]; string s, s1, s2; vector<int> v; int main() { cin >> n; if (!(n & 1)) { cout << -1; return 0; } for (int i = 0; i < n; i++) printf( %d , i); cout << endl; for (int i = 0; i < n; i++) printf( %d , i); cout << endl; for (int i = 0; i < n; i++) printf( %d , (i + i) % n); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 200010; const int oo = 1e9; int xm, ym, zm, n, m, k, xmn, xmx, ymn, ymx, zmn, zmx; struct point { int x, y, z, idx; bool operator<(const point &rhs) const { return x < rhs.x; } void print() { cout << x << << y << << z << endl; } }; point pnt[N], q[N], org[N]; set<int> seg[4 * N]; vector<int> f[2]; int l, r, x, y, at, val, ans[N]; void update(int n, int s, int e) { if (s > at || e < at) return; seg[n].insert(val); if (s == e) return; update(2 * n, s, (s + e) / 2); update(2 * n + 1, (s + e) / 2 + 1, e); } bool get(int n, int s, int e) { if (s > r || e < l) return 0; if (s >= l && e <= r) { return seg[n].lower_bound(x) != seg[n].end() && *seg[n].lower_bound(x) <= y; } return get(2 * n, s, (s + e) / 2) || get(2 * n + 1, (s + e) / 2 + 1, e); } void clear() { for (int i = 0; i < 4 * N; ++i) seg[i].clear(); } pair<point, point> nw(int a, int b, int c) { point f1, f2; f1.x = xmn, f1.y = ymn, f1.z = zmn; f2.x = xmx, f2.y = ymx, f2.z = zmx; f1.x = min(f1.x, a), f2.x = max(f2.x, a); f1.y = min(f1.y, b), f2.y = max(f2.y, b); f1.z = min(f1.z, c), f2.z = max(f2.z, c); return make_pair(f1, f2); } bool inside(point c) { return c.x >= xmn && c.x <= xmx && c.y >= ymn && c.y <= ymx && c.z >= zmn && c.z <= zmx; } int main() { cin >> xm >> ym >> zm >> n >> m >> k; for (int a, b, c, i = 0; i < n; ++i) { scanf( %d%d%d , &a, &b, &c); if (!i) xmn = xmx = a, ymn = ymx = b, zmn = zmx = c; xmn = min(xmn, a), xmx = max(xmx, a); ymn = min(ymn, b), ymx = max(ymx, b); zmn = min(zmn, c), zmx = max(zmx, c); } for (int i = 0; i < m; ++i) { scanf( %d%d%d , &pnt[i].x, &pnt[i].y, &pnt[i].z); if (inside(pnt[i])) { puts( INCORRECT ); return 0; } } puts( CORRECT ); sort(pnt, pnt + m); for (int i = 0; i < k; ++i) { scanf( %d%d%d , &q[i].x, &q[i].y, &q[i].z); q[i].idx = i; org[i] = q[i]; } sort(q, q + k); for (int i = 0; i < k; ++i) { if (q[i].x < xmn) { f[0].push_back(i); } else { f[1].push_back(i); } } int idx = 0; while (idx < m && pnt[idx].x < xmn) ++idx; for (int i = 0; i < f[1].size(); ++i) { int cur = f[1][i]; pair<point, point> w = nw(q[cur].x, q[cur].y, q[cur].z); l = w.first.y, r = w.second.y; x = w.first.z, y = w.second.z; while (idx < m && pnt[idx].x <= w.second.x) { at = pnt[idx].y; val = pnt[idx].z; update(1, 1, ym); idx++; } bool res = get(1, 1, ym); if (res) { ans[q[cur].idx] = 1; } else { ans[q[cur].idx] = 2; ; } } clear(); idx = m - 1; while (idx >= 0 && pnt[idx].x > xmx) --idx; for (int i = f[0].size() - 1; i >= 0; --i) { int cur = f[0][i]; pair<point, point> w = nw(q[cur].x, q[cur].y, q[cur].z); l = w.first.y, r = w.second.y; x = w.first.z, y = w.second.z; while (idx >= 0 && pnt[idx].x >= w.first.x) { at = pnt[idx].y; val = pnt[idx].z; update(1, 1, ym); idx--; } bool res = get(1, 1, ym); if (res) { ans[q[cur].idx] = 1; } else { ans[q[cur].idx] = 2; ; } } for (int i = 0; i < k; ++i) { if (inside(org[i])) { puts( OPEN ); } else { assert(ans[i] != 0); if (ans[i] == 1) { puts( CLOSED ); } else { puts( UNKNOWN ); } } } return 0; }
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#include <bits/stdc++.h> using namespace std; bool prime[1000009]; vector<long long> pri; void SieveOfEratosthenes() { memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= 1000000; p++) { if (prime[p] == true) { for (long long i = p * p; i <= 1000000; i += p) prime[i] = false; } } for (long long i = 2; i <= 1000000; i++) { if (prime[i]) { pri.push_back(i); } } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; SieveOfEratosthenes(); while (t--) { long long n; cin >> n; long long counter = 0; int i = 0; long long sz = pri.size(); long long st = 0; long long end = sz - 1; long long idx; if (n == 1) { printf( 1 n ); continue; } while (st < end) { long long md = st + (end - st) / 2; if (pri[md] * pri[md] > n) { end = md; idx = md; } else { st = md + 1; } } st = 0; end = sz - 1; long long id = upper_bound(pri.begin(), pri.end(), n) - pri.begin(); id--; long long ans = id - idx + 2; printf( %lld n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100010; long long int A[N]; vector<int> g[N]; long long int dfs(int x, int p) { A[x] = 1; for (int i = 0; i < g[x].size(); ++i) { int y = g[x][i]; if (y == p) continue; A[x] += dfs(y, x); } return A[x]; } long double E[N]; void solve(int x, int p) { long long int n = (long long int)g[x].size(); for (int i = 0; i < g[x].size(); ++i) { int y = g[x][i]; if (y == p) continue; E[y] = E[x] + 1; long double med = (A[x] - 1 - A[y]) / (long double)(n - 1); if (g[x].size() != 1) { E[y] += (med * (n - 1)) / (2.0); } solve(y, x); } } int main(void) { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 2; i <= n; ++i) { int x; cin >> x; g[x].push_back(i); g[i].push_back(x); } E[1] = 1.0; dfs(1, -1); solve(1, -1); cout.precision(10); for (int i = 1; i <= n; ++i) { cout << fixed << E[i] << ; } cout << endl; }
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#include <bits/stdc++.h> using namespace std; void fr(int &a, bool f = 0, char ch = getchar()) { for (a = 0; ch < 0 || ch > 9 ; ch = getchar()) ch == - ? f = 1 : 0; for (; ch >= 0 && ch <= 9 ; ch = getchar()) a = a * 10 + ch - 0 ; a = f ? -a : a; } int fr() { int a; return fr(a), a; } const int N = 12; int arr[(1 << N) + 10], a[(1 << N) + 10], ans[(1 << N) + 10], p[(1 << N) + 10]; int tmp[(1 << N) + 10]; bool visval[(1 << N) + 10], vispos[(1 << N) + 10]; struct OI { int RP, score; } CSPS2021, NOIP2021; int main() { CSPS2021.RP++, CSPS2021.score++, NOIP2021.RP++, NOIP2021.score++, 392699; srand(time(0)); int n = fr(), xsum = 0, tot = 1 << n; for (int i = 0; i < (1 << n); i++) fr(a[i]), xsum ^= a[i], arr[i] = i; if (xsum) return puts( Fou ), 0; puts( Shi ); for (int i = 0; i < (1 << n); i++) { int pos = rand() % tot, arrpos = arr[pos]; if (pos != tot - 1) arr[pos] = arr[tot - 1]; tot--, tmp[0] = 0; bool flag = 0; for (int j = 0; j < (1 << n); j++) if (vispos[j] == 0 && visval[arrpos ^ a[j]] == 0) { flag = visval[arrpos ^ a[j]] = vispos[j] = 1, ans[j] = arrpos, p[arrpos ^ a[j]] = j; break; } else if (vispos[j] == 0) tmp[++tmp[0]] = j; if (flag == 0) { int j = tmp[rand() % tmp[0] + 1]; vispos[p[arrpos ^ a[j]]] = 0; arr[tot++] = ans[p[arrpos ^ a[j]]], ans[j] = arrpos; vispos[j] = 1; visval[ans[j] ^ a[j]] = 1; p[ans[j] ^ a[j]] = j; i--; } } for (int i = 0; i < (1 << n); i++) printf( %d , ans[i] ^ a[i]); puts( ); for (int i = 0; i < (1 << n); i++) printf( %d , ans[i]); puts( ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 400005; vector<int> adj[N]; vector<int> st; int cTime = 1; int in[N]; int low[N]; vector<vector<int>> comps; map<array<int, 2>, int> edgeToI; array<int, 2> res[N]; int edgeToIndex(int a, int b) { return edgeToI[{min(a, b), max(a, b)}]; } void addRes(int a, int b) { res[edgeToIndex(a, b)] = {a, b}; } void dfs(int node, int par) { in[node] = cTime++; low[node] = in[node]; st.push_back(node); for (int next : adj[node]) { if (next == par) continue; if (in[next]) { low[node] = min(low[next], low[node]); } else { dfs(next, node); low[node] = min(low[node], low[next]); } } if (in[node] == low[node]) { vector<int> cur; while (true) { int last = st.back(); st.pop_back(); cur.push_back(last); if (last == node) break; } comps.push_back(cur); } } bool onCircle[N]; bool vis[N]; void getEdges(int node) { vis[node] = true; for (int next : adj[node]) { if (res[edgeToIndex(node, next)][0] != 0) continue; addRes(next, node); if (!vis[next]) getEdges(next); } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); edgeToI[{min(a, b), max(a, b)}] = i; } dfs(1, -1); vector<int> best; for (auto comp : comps) { if (comp.size() > best.size()) best = comp; } for (int i : best) onCircle[i] = true; vector<array<int, 2>> edges; cout << best.size() << n ; if (best.size() != 1) { } getEdges(best[0]); for (int i = 0; i < m; i++) { cout << res[i][0] << << res[i][1] << n ; } }
|
module prefab_alu_rf;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
//reg [31:0] A,B; //Rn Rm
reg [4:0] OP;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,Rm, OP, FLAGS, in,FLAGS_OUT,S,ALU_OUT);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17; FLAGS=0; S=1;ALU_OUT=1;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0 /* Rn */ ; #1 RSLCT[7:4] = 0 /* Rm */; #1 RSLCT[11:8] = 0 /* Rs */; #1 RSLCT[15:12] = 0 /* Rd */; #1 RSLCT[19:16] = 0 /* Rn */ ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;
//Clk 0 (Falling Edge)Send CU signals
#2 Pcin = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0 /* Rn */ ; #2 RSLCT[7:4] = 0 /* Rm */; #2 RSLCT[11:8] = 0 /* Rs */; #2 RSLCT[15:12] = 0 /* Rd */; #2 RSLCT[19:16] = 0 /* Rn */ ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;
//Clk 1 (Rising Edge
#3 RESET = 0 ; #3 Pcin = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0 /* Rn */ ; #3 RSLCT[7:4] = 0 /* Rm */; #3 RSLCT[11:8] = 0 /* Rs */; #3 RSLCT[15:12] = 0 /* Rd */; #3 RSLCT[19:16] = 0 /* Rn */ ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;
//Clk 0 (Falling Edge) Send CU signals
#4 Pcin = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0 /* Rn */ ; #4 RSLCT[7:4] = 0 /* Rm */; #4 RSLCT[11:8] = 0 /* Rs */; #4 RSLCT[15:12] = 1 /* Rd */; #4 RSLCT[19:16] = 0 /* Rn */ ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("prefab_alu_rf.vcd");
$dumpvars(0,prefab_alu_rf);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_ALU.v prefab_alu_rf.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sync_pulse_synchronizer.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// Synchronizer without reset for use in cluster_header_sync.
// For simulation only.
module sync_pulse_synchronizer (/*AUTOARG*/
// Outputs
sync_out, so,
// Inputs
async_in, gclk, rclk, si, se
);
output sync_out;
output so;
input async_in;
input gclk;
input rclk;
input si;
input se;
wire pre_sync_out;
wire so_rptr;
wire so_lockup;
// Flop drive strengths to be adjusted as necessary
bw_u1_soff_8x repeater (
.q (pre_sync_out),
.so (so_rptr),
.ck (gclk),
.d (async_in),
.se (se),
.sd (si)
);
bw_u1_scanl_2x lockup (
.so (so_lockup),
.sd (so_rptr),
.ck (gclk)
);
bw_u1_soff_8x syncff (
.q (sync_out),
.so (so),
.ck (rclk),
.d (pre_sync_out),
.se (se),
.sd (so_lockup)
);
endmodule // sync_pulse_synchronizer
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 2; int a[N], b[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < (int)n; i++) cin >> a[i], b[i + 1] += b[i] + a[i]; int t = 0; for (int i = 0; i < (int)n; i++) { for (int j = 0; j < (int)i + 1; j++) { if (b[i + 1] - b[j] > 100 * (i - j + 1)) t = max(t, i - j + 1); } } cout << t << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_1_V
|
#include <bits/stdc++.h> using namespace std; int mostFrequent(int arr[], int n) { sort(arr, arr + n); int max_count = 1, res = arr[0], curr_count = 1; for (int i = 1; i < n; i++) { if (arr[i] == arr[i - 1]) curr_count++; else { if (curr_count > max_count) { max_count = curr_count; res = arr[i - 1]; } curr_count = 1; } } if (curr_count > max_count) { max_count = curr_count; res = arr[n - 1]; } return res; } unsigned int countDivisors(unsigned int n) { int cnt = 0; for (int i = 1; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) cnt++; else cnt = cnt + 2; } } return cnt; } int main() { int n, a; long long int back = 0, biceps = 0, chest = 0; cin >> n; for (int i = 1; i <= (n); ++i) { cin >> a; if (i % 3 == 0) { back += a; } else if (i % 3 == 1) { chest += a; } else if (i % 3 == 2) { biceps += a; } } long long int maxi = max(back, max(biceps, chest)); if (maxi == back) cout << back ; else if (maxi == biceps) cout << biceps ; else if (maxi == chest) cout << chest ; return 0; }
|
//----------------------------------------------------------------------------
//-- Memoria ROM de 16 x 4
//------------------------------------------
//-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- La memoria estΓ‘ inicializada con los valores para sacar por los leds
//-- y generar una secuencia de luces
//----------------------------------------------------------------------------
module rom16x4 (input clk,
input wire [3:0] addr,
output reg [3:0] data);
//-- Memoria
reg [3:0] rom [0:31];
always @(negedge clk) begin
data <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
rom[0] = 4'h1;
rom[1] = 4'h2;
rom[2] = 4'h4;
rom[3] = 4'h8;
rom[4] = 4'h1;
rom[5] = 4'h8;
rom[6] = 4'h4;
rom[7] = 4'h2;
rom[8] = 4'h1;
rom[9] = 4'hF;
rom[10] = 4'h0;
rom[11] = 4'hF;
rom[12] = 4'hC;
rom[13] = 4'h3;
rom[14] = 4'hC;
rom[15] = 4'h3;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void action() { string s; cin >> s; reverse(s.begin(), s.end()); long long c = 0, f = 0, j; for (long long i = 0; i < s.length(); i++) { if (s[i] == 1 ) { f++; } if (i % 2 == 0) c++; } if (f > 1) cout << c; else { if ((s.length()) % 2 == 0) cout << c; else cout << c - 1; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); action(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int digit[10] = {2, 7, 2, 3, 3, 4, 2, 5, 1, 2}; string n; cin >> n; int a = digit[(n[1] - 48)]; int b = digit[(n[0] - 48)]; cout << a * b; return 0; }
|
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