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#include <bits/stdc++.h> long long p[16]; void F() { p[1] = 10; for (int i = 2; i <= 14; i++) p[i] = p[i - 1] * 10; } using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); F(); long long n, ans = 0; cin >> n; if (n < 10) { cout << n; return 0; } for (int i = 1; i <= 14; i++) { if (n / p[i] == 0) { long long a = p[i - 1] - 1; long long b = n - a; ostringstream str1, str2; str1 << a; str2 << b; string sa = str1.str(); string sb = str2.str(); for (auto x : sa) ans += x - 0 ; for (auto x : sb) ans += x - 0 ; cout << ans; return 0; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC target( sse,sse2,sse3,sse3,sse4,popcnt,abm,mmx ) using namespace std; const int mod = 1e9 + 7; const int N = 2e5 + 4; int a[N], v[N], s[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { cin >> a[i]; v[i] = 1; } sort(a, a + n); int j = 0; int res = 0; int cur = 0; for (int i = 0; i < n; i++) { while (j < n && a[j] - a[i] < m) { cur += v[j]; s[j] = cur; if (cur >= k && v[j] == 1) { v[j] = 0; res++; cur--; } j++; } if (v[i]) cur--; } cout << res << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, howMany[N]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n; vector<pair<int, int> > beacons; for (int i = 0; i < n; i++) { int x, p; cin >> x >> p; beacons.push_back({x, p}); } sort(beacons.begin(), beacons.end()); howMany[0] = 0; auto it = beacons.begin(); for (int i = 1; i < n; i++) { int now = beacons[i].first, power = beacons[i].second; auto it = lower_bound(beacons.begin(), beacons.end(), make_pair(now - power, -1)); int idx = it - beacons.begin(); if (idx == 0) { howMany[i] = i; } else { howMany[i] = howMany[idx - 1] + (i - idx); } } int ans = n; for (int i = 0; i < n; i++) { ans = min(ans, howMany[i] + (n - i - 1)); } cout << ans << n ; }
|
/* Verilog for cell 'FTC{sch}' from library 'wordlib8' */
/* Created on Fri Oct 25, 2013 21:56:14 */
/* Last revised on Fri Oct 25, 2013 22:27:32 */
/* Written on Tue Oct 29, 2013 15:50:09 by Electric VLSI Design System, version 8.06 */
module muddlib07__a2o1_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_0, net_11, net_19;
tranif1 nmos_0(gnd, net_19, a);
tranif1 nmos_1(net_19, net_0, b);
tranif1 nmos_2(gnd, net_0, c);
tranif1 nmos_3(gnd, y, net_0);
tranif0 pmos_0(net_0, net_11, c);
tranif0 pmos_1(net_11, vdd, b);
tranif0 pmos_2(net_11, vdd, a);
tranif0 pmos_3(y, vdd, net_0);
endmodule /* muddlib07__a2o1_1x */
module muddlib07__nand2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_5;
tranif1 nmos_0(net_5, y, b);
tranif1 nmos_1(gnd, net_5, a);
tranif0 pmos_0(y, vdd, b);
tranif0 pmos_1(y, vdd, a);
endmodule /* muddlib07__nand2_1x */
module muddlib07__o2a1i_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_35, net_7;
tranif1 nmos_0(gnd, net_7, a);
tranif1 nmos_1(gnd, net_7, b);
tranif1 nmos_2(net_7, y, c);
tranif0 pmos_0(y, net_35, b);
tranif0 pmos_1(net_35, vdd, a);
tranif0 pmos_3(y, vdd, c);
endmodule /* muddlib07__o2a1i_1x */
module muddlib07__o22a2i_1x(a, b, c, d, y);
input a;
input b;
input c;
input d;
output y;
supply1 vdd;
supply0 gnd;
wire net_34, net_35, net_7;
tranif1 nmos_0(gnd, net_7, a);
tranif1 nmos_1(gnd, net_7, b);
tranif1 nmos_2(net_7, y, c);
tranif1 nmos_3(net_7, y, d);
tranif0 pmos_0(y, net_35, b);
tranif0 pmos_1(net_35, vdd, a);
tranif0 pmos_2(y, net_34, d);
tranif0 pmos_3(net_34, vdd, c);
endmodule /* muddlib07__o22a2i_1x */
module muddlib07__xor2_2x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire ab, bb, net_3, net_4, net_5, net_7, net_8;
tranif1 nmos_0(gnd, net_3, a);
tranif1 nmos_1(gnd, net_4, ab);
tranif1 nmos_2(net_3, net_5, bb);
tranif1 nmos_3(net_4, net_5, b);
tranif1 nmos_4(gnd, bb, b);
tranif1 nmos_5(gnd, ab, a);
tranif1 nmos_6(gnd, y, net_5);
tranif0 pmos_0(net_5, net_7, b);
tranif0 pmos_1(net_7, vdd, a);
tranif0 pmos_2(net_5, net_8, bb);
tranif0 pmos_3(net_8, vdd, ab);
tranif0 pmos_4(bb, vdd, b);
tranif0 pmos_5(ab, vdd, a);
tranif0 pmos_6(y, vdd, net_5);
endmodule /* muddlib07__xor2_2x */
module FTC(Cin, I1, I2, I3, I4, C, Cout, S);
input Cin;
input I1;
input I2;
input I3;
input I4;
output C;
output Cout;
output S;
supply1 vdd;
supply0 gnd;
wire net_2, net_35, net_37, net_4, net_49, net_56;
muddlib07__a2o1_1x a2o1_1x_0(.a(net_49), .b(Cin), .c(net_56), .y(C));
muddlib07__nand2_1x nand2_1x_0(.a(I1), .b(I2), .y(net_4));
muddlib07__nand2_1x nand2_1x_1(.a(I3), .b(I4), .y(net_2));
muddlib07__nand2_1x nand2_1x_2(.a(net_4), .b(net_2), .y(Cout));
muddlib07__o2a1i_1x o2a1i_1x_0(.a(I4), .b(I3), .c(net_2), .y(net_37));
muddlib07__o2a1i_1x o2a1i_1x_1(.a(I2), .b(I1), .c(net_4), .y(net_35));
muddlib07__o22a2i_1x o22a2i_1_0(.a(net_2), .b(net_4), .c(net_35), .d(net_37),
.y(net_56));
muddlib07__xor2_2x xor2_2x_0(.a(net_37), .b(net_35), .y(net_49));
muddlib07__xor2_2x xor2_2x_1(.a(net_49), .b(Cin), .y(S));
endmodule /* FTC */
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_ls__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_ls__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; bool visited[100005]; vector<long long> arr[100005]; int main() { std::ios::sync_with_stdio(false); long long n, x; cin >> n; vector<pair<long long, long long> > ans; for (long long i = 0; i < n; i++) { cin >> x; arr[x].push_back(i); } for (long long i = 0; i < 100005; i++) { if (arr[i].size() == 1) { ans.push_back(make_pair(i, 0)); } else if (arr[i].size() >= 2) { bool good = 1; long long dif = arr[i][1] - arr[i][0]; for (long long j = 1; j < arr[i].size(); j++) { if (arr[i][j] != arr[i][j - 1] + dif) good = 0; } if (good) { ans.push_back(make_pair(i, dif)); } } } cout << ans.size() << endl; for (long long i = 0; i < ans.size(); i++) cout << ans[i].first << << ans[i].second << endl; return 0; }
|
// bsg_rp_clk_gen_coarse_delay_element
//
// (o is inverting on even start_tap_p
// worst_o is non-inverting)
//
// o contains controllably delayed signal
// worst_o contains worst-case delayed signal (for delay matching)
//
//
// we use sed to substitute parameters because the netlist reader
// does not like them, and we need the netlist reader for rp_groups
//
// module bsg_clk_gen_coarse_delay_element #(parameter `BSG_INV_PARAM(start_tap_p))
//
module bsg_rp_clk_gen_coarse_delay_tuner
(input i
, input [1:0] sel_i
, input we_i
, input async_reset_neg_i
, output o
, output we_o
);
wire [1:0] sel_r;
wire [8:0] signal;
assign signal[0] = i;
// synopsys rp_group (bsg_clk_gen_cdt)
// synopsys rp_fill (0 0 RX)
CKND2BWP I1 (.I(signal[0]), .ZN(signal[1]) );
CKND2BWP I2 (.I(signal[1]), .ZN(signal[2]) );
CKND4BWP I2a (.I(signal[1]), .ZN() );
CKND2BWP I3 (.I(signal[2]), .ZN(signal[3]) );
CKND2BWP I4 (.I(signal[3]), .ZN(signal[4]) );
CKND4BWP I4a (.I(signal[3]), .ZN() );
CKND2BWP I5 (.I(signal[4]), .ZN(signal[5]) );
CKND2BWP I6 (.I(signal[5]), .ZN(signal[6]) );
CKND4BWP I6a (.I(signal[5]), .ZN() );
CKND2BWP I7 (.I(signal[6]), .ZN(signal[7]) );
CKND2BWP I8 (.I(signal[7]), .ZN(signal[8]) );
// synopsys rp_fill (0 1 RX)
MUX4ND4BWP M1 ( .I0(signal[6]) // start_tap_p + 6
,.I1(signal[4]) // start_tap_p + 4
,.I2(signal[2]) // start_tap_p + 2
,.I3(signal[0]) // start_tap_p + 0
,.S0(sel_r[0])
,.S1(sel_r[1])
,.ZN (o )
);
wire [1:0] mux_lo;
// synopsys rp_fill (0 2 RX)
DFNCND4BWP sel_r_reg_0 (.D(mux_lo[0]), .CPN(o), .CDN(async_reset_neg_i), .Q(sel_r[0]), .QN());
MUX2D1BWP MX1 (.I0(sel_r[0]),.I1(sel_i[0]),.S(we_i), .Z(mux_lo[0]));
// synopsys rp_fill (0 3 RX)
DFNCND4BWP sel_r_reg_1 (.D(mux_lo[1]), .CPN(o), .CDN(async_reset_neg_i), .Q(sel_r[1]), .QN());
MUX2D1BWP MX2 (.I0(sel_r[1]),.I1(sel_i[1]),.S(we_i), .Z(mux_lo[1]));
// synopsys rp_fill (0 4 RX)
BUFFD4BWP we_o_buf (.I(we_i), .Z(we_o));
// synopsys rp_endgroup (bsg_clk_gen_cdt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_coarse_delay_tuner)
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test uses the level sensitive wait to notice the scheduling of
* the expression evaluation. The FAILED message detects cases where
* the value of test is true, even when the value of a is set to
* false.
*/
module main;
reg a;
wire test = a == 1'b1;
always #1 wait (test) begin
if (a !== 1'b1) begin
$display("FAILED -- a == %b, test == %b", a, test);
$finish;
end
a = 1'b0;
end
initial begin
a = 0;
#10 a = 1;
#10 a = 0;
#10 $display("PASSED");
end
endmodule // main
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
//Date : Tue Jan 27 10:02:38 2015
//Host : Dtysky running 64-bit major release (build 9200)
//Command : generate_target MIPS_CPU_wrapper.bd
//Design : MIPS_CPU_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module MIPS_CPU_wrapper
(alu_pinout,
clk,
data_pinout,
inst_pinout,
pc_pinout,
restet);
output [31:0]alu_pinout;
input clk;
output [31:0]data_pinout;
output [31:0]inst_pinout;
output [31:0]pc_pinout;
input restet;
wire [31:0]alu_pinout;
wire clk;
wire [31:0]data_pinout;
wire [31:0]inst_pinout;
wire [31:0]pc_pinout;
wire restet;
MIPS_CPU MIPS_CPU_i
(.alu_pinout(alu_pinout),
.clk(clk),
.data_pinout(data_pinout),
.inst_pinout(inst_pinout),
.pc_pinout(pc_pinout),
.restet(restet));
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT6.v,v 1.11 2007/06/05 00:00:54 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 6-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT6.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Replace premitive with function; Remove buf.
// 01/07/06 - Add LOC Parameter (CR 222733)
// 06/04/07 - Add wire declaration to internal signal.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT6 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2, I3, I4, I5;
wire a0, a1, a2, a3, a4, a5;
wire o_out_tmp;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
buf b3 (a3, I3);
buf b4 (a4, I4);
buf b5 (a5, I5);
buf b6 (O, o_out_tmp);
reg o_out;
reg tmp;
assign o_out_tmp = o_out;
always @( a5 or a4 or a3 or a2 or a1 or a0 ) begin
tmp = a0 ^ a1 ^ a2 ^ a3 ^ a4 ^ a5;
if ( tmp == 0 || tmp == 1)
o_out = INIT[{a5, a4, a3, a2, a1, a0}];
else
o_out = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {a2, a1, a0}),
lut6_mux8 ( INIT[55:48], {a2, a1, a0}),
lut6_mux8 ( INIT[47:40], {a2, a1, a0}),
lut6_mux8 ( INIT[39:32], {a2, a1, a0}),
lut6_mux8 ( INIT[31:24], {a2, a1, a0}),
lut6_mux8 ( INIT[23:16], {a2, a1, a0}),
lut6_mux8 ( INIT[15:8], {a2, a1, a0}),
lut6_mux8 ( INIT[7:0], {a2, a1, a0}) }, {a5, a4, a3});
end
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
(I3 => O) = (0:0:0, 0:0:0);
(I4 => O) = (0:0:0, 0:0:0);
(I5 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
function lut6_mux8;
input [7:0] d;
input [2:0] s;
begin
if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0))
lut6_mux8 = d[s];
else
if ( ~(|d))
lut6_mux8 = 1'b0;
else if ((&d))
lut6_mux8 = 1'b1;
else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}]))
lut6_mux8 = d[{1'b0,s[1:0]}];
else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}]))
lut6_mux8 = d[{s[2],1'b0,s[0]}];
else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}]))
lut6_mux8 = d[{s[2],s[1],1'b0}];
else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) &&
(d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}]))
lut6_mux8 = d[{1'b0,1'b0,s[0]}];
else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) &&
(d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}]))
lut6_mux8 = d[{1'b0,s[1],1'b0}];
else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) &&
(d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}]))
lut6_mux8 = d[{s[2],1'b0,1'b0}];
else
lut6_mux8 = 1'bx;
end
endfunction
endmodule
`endcelldefine
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sd_bram_block_dp #(
parameter DATA = 32,
parameter ADDR = 7
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk) begin
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end else
a_dout <= mem[a_addr];
end
always @(posedge b_clk) begin
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end else
b_dout <= mem[b_addr];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, r; cin >> n >> r; vector<double> a(1 << n); double sum = 0, div = (double)(1 << n); for (int i = 0; i < (1 << n); i++) { int x; cin >> x; a[i] = (double)x; sum += a[i]; } double ans = sum / div; cout << setprecision(7) << fixed << ans << n ; while (r--) { int z, g; cin >> z >> g; double gg = (double)g; sum += (gg - a[z]); a[z] = gg; ans = sum / div; cout << setprecision(7) << fixed << ans << n ; } return 0; }
|
`define ADDER_WIDTH 096
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 9; int arr[maxn], ar[maxn]; int main() { int a, b, c, d, e, f, g, h; while (cin >> a) { cin >> e >> f; for (int i = 1; i <= a; i++) { cin >> arr[i]; } for (int i = 1; i <= a; i++) { cin >> ar[i]; } g = 1; for (int i = 1; i < e; i++) { if (arr[i] != ar[i]) { g = 0; break; } } for (int i = f + 1; i <= a; i++) { if (arr[i] != ar[i]) { g = 0; break; } } map<int, int> ma1, ma2; for (int i = e; i <= f; i++) { ma1[arr[i]]++; ma2[ar[i]]++; } if (ma1 != ma2) g = 0; if (!g) { cout << LIE << endl; } else { cout << TRUTH << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__XOR3_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string ch, t; int n, s, i; bool ok1 = 0, ok2 = 0; scanf( %d %d , &n, &s); if (9 * n >= s) { if (n == 1 && s == 0) { cout << 0 << << 0 << endl; } else if (s == 0) { cout << -1 << << -1 << endl; } else { while (n--) { ch += min(9, s) + 0 ; t = ch; s -= 9; if (s < 0) s = 0; } reverse(t.begin(), t.end()); if (t[0] == 0 ) { t[0] = 1 ; for (i = 1; i < t.size(); i++) { if (t[i] > 0 ) { t[i] = t[i] - 1; break; } } } cout << t << << ch << endl; } } else { cout << -1 << << -1 << endl; } return 0; }
|
`timescale 1ns / 1ps
module select_efect(
input [6:0]efect,
output reg efect0,
output reg efect1,
output reg efect2,
output reg efect3,
output reg efect4,
output reg efect5 /*output efect6,*/
);
always @(efect) begin
case(efect)
7'd48: begin
efect0 =1'b1;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b0;
end
7'd49: begin
efect0 =1'b0;
efect1 =1'b1;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b0;
end
7'd50: begin
efect0 =1'b0;
efect1 =1'b0;
efect2 =1'b1;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b0;
end
7'd51: begin
efect0 =1'b0;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b1;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b0;
end
7'd52: begin
efect0 =1'b0;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b1;
efect5 =1'b0;
//efect6 =1'b0;
end
7'd53: begin
efect0 =1'b0;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b1;
//efect6 =1'b0;
end
/*7'd54: begin
efect0 =1'b0;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b1;
end*/
default:
begin
efect0 =1'b1;
efect1 =1'b0;
efect2 =1'b0;
efect3 =1'b0;
efect4 =1'b0;
efect5 =1'b0;
//efect6 =1'b0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e3 + 10, oo = maxn; int n, m; char s[maxn], t[maxn]; int a[maxn]; int dp[maxn][maxn]; void myMax(int &a, int b) { if (a < b) { a = b; } } int main() { int i, j, k, x, y; scanf( %s , s + 1); n = strlen(s + 1); scanf( %s , t + 1); m = strlen(t + 1); for (i = n; i >= m; i--) { for (j = i, k = 0; j; j--) { if (s[j] == t[m - k] && ++k == m) { break; } } a[i] = k == m ? i - j + 1 : oo; } for (; i; i--) { a[i] = oo; } dp[0][0] = 0; for (i = (1); i <= (n); i++) { for (j = (0); j <= (i); j++) { dp[i][j] = 0; if (j < i) { dp[i][j] = dp[i - 1][j]; } if (j) { myMax(dp[i][j], dp[i - 1][j - 1]); } if (a[i] != oo && (y = j - a[i] + m) >= 0 && (x = i - a[i]) >= y) { myMax(dp[i][j], dp[x][y] + 1); } } } for (i = (0); i <= (n); i++) { printf( %d%c , dp[n][i], n [i == n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; bool check(long long l, long long r) { for (long long i = l; i < (r + l) / 2; i++) { if (s[i] != s[r - i - 1]) { return false; } } return true; } long long sulganlox(long long l, long long r) { if (r - l == 1) { if (s[l] == s[l + 1]) { cout << Impossible << endl; exit(0); } return 2; } if ((r - l) % 2 == 0) { if (check(l, (r + l) / 2)) { return sulganlox(l, (r + l) / 2); } else { return 1; } } else { if (check(l, (r + l) / 2)) { return sulganlox(l, (r + l) / 2); } else { return 2; } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s; long long n = s.size(); if (n == 1) { cout << Impossible << endl; return 0; } cout << sulganlox(0, n) << endl; return 0; }
|
module buf_manage(
input clk,
input reset,
//cut pkt
input pkt_metadata_cut_out_valid,
input [359:0] pkt_metadata_cut_out,
input [138:0] pkt_cut_data,
input pkt_cut_data_valid,
output [7:0] pkt_cut_data_usedw,
input [10:0] ram_rd_addr,
input ram_rd,
output [138:0] ram_data_q,
input [3:0] pkt_out_recycle_addr,
input pkt_out_recycle_addr_wr,
//no cut pkt
input pkt_metadata_nocut_out_valid,
input [359:0] pkt_metadata_nocut_out,
input [138:0] pkt_nocut_data,
input pkt_nocut_data_valid,
output [7:0] pkt_nocut_data_usedw,
input [10:0] nocut_pkt_ram_rd_addr,
input nocut_pkt_ram_rd,
output [138:0] nocut_pkt_ram_data_q,
input [3:0] nocutpkt_out_recycle_addr,
input nocutpkt_out_recycle_addr_wr,
//result
output [4:0] pkt_addr, //[4] == cutpkt 0 nocut pkt
output pkt_addr_wr,
output [63:0] metadata_data,
output metadata_data_wr,
output p2k_valid,
output [7:0] p2k_ingress,
output [127:0] p2k_rloc_src,
output [127:0] p2k_eid_dst,
output [71:0] p2k_metadata
);
wire [3:0] aging_recycle_addr;
wire aging_recycle_addr_wr;
wire buf_addr_wr;
wire [3:0] buf_addr;
wire [339:0] pkt_metadata_nocut;
wire pkt_metadata_nocut_valid;
wire [339:0] pkt_metadata_out;
wire pkt_metadata_out_valid;
wire nocutbuf_addr_wr;
wire [3:0] nocutbuf_addr;
pkt_recomb pkt_recomb(
.clk (clk),
.reset (reset),
.pkt_metadata_cut_out_valid (pkt_metadata_cut_out_valid),
.pkt_metadata_cut_out (pkt_metadata_cut_out),
.pkt_cut_data (pkt_cut_data),
.pkt_cut_data_valid (pkt_cut_data_valid),
.pkt_cut_data_usedw (pkt_cut_data_usedw),
.buf_addr_wr (buf_addr_wr),
.buf_addr (buf_addr),
.aging_recycle_addr (aging_recycle_addr),
.aging_recycle_addr_wr (aging_recycle_addr_wr),
.pkt_metadata_out (pkt_metadata_out), //[339:336]==pkt_addr,[335:0]
.pkt_metadata_out_valid (pkt_metadata_out_valid),
.ram_rd_addr (ram_rd_addr),
.ram_rd (ram_rd),
.ram_data_q (ram_data_q));
buf_add_manage cutpkt_buf_add_manage(
.clk (clk),
.reset (reset),
.aging_recycle_addr (aging_recycle_addr),
.aging_recycle_addr_wr (aging_recycle_addr_wr),
.pkt_out_recycle_addr (pkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (pkt_out_recycle_addr_wr),
.buf_addr_wr (buf_addr_wr),
.buf_addr (buf_addr));
pkt_mux pkt_mux(
.clk (clk),
.reset (reset),
.pkt_metadata_nocut (pkt_metadata_nocut),
.pkt_metadata_nocut_valid (pkt_metadata_nocut_valid),
.pkt_metadata_out (pkt_metadata_out), //[349:336]==pkt_addr,[335:0]
.pkt_metadata_out_valid (pkt_metadata_out_valid),
.pkt_addr (pkt_addr),
.pkt_addr_wr (pkt_addr_wr),
.metadata_data (metadata_data),
.metadata_data_wr (metadata_data_wr),
.p2k_valid (p2k_valid),
.p2k_ingress (p2k_ingress),
.p2k_rloc_src (p2k_rloc_src),
.p2k_eid_dst (p2k_eid_dst),
.p2k_metadata (p2k_metadata));
pkt_in_buf pkt_in_buf(
.clk (clk),
.reset (reset),
.pkt_metadata_nocut_out_valid (pkt_metadata_nocut_out_valid),
.pkt_metadata_nocut_out (pkt_metadata_nocut_out),
.pkt_nocut_data (pkt_nocut_data),
.pkt_nocut_data_valid (pkt_nocut_data_valid),
.pkt_nocut_data_usedw (pkt_nocut_data_usedw),
.buf_addr_wr (nocutbuf_addr_wr),
.buf_addr (nocutbuf_addr),
.pkt_metadata_nocut (pkt_metadata_nocut),
.pkt_metadata_nocut_valid (pkt_metadata_nocut_valid),
.nocut_pkt_ram_rd_addr (nocut_pkt_ram_rd_addr),
.nocut_pkt_ram_rd (nocut_pkt_ram_rd),
.nocut_pkt_ram_data_q (nocut_pkt_ram_data_q));
buf_add_manage nocutpkt_buf_add_manage(
.clk (clk),
.reset (reset),
.aging_recycle_addr (4'b0),
.aging_recycle_addr_wr (1'b0),
.pkt_out_recycle_addr (nocutpkt_out_recycle_addr),
.pkt_out_recycle_addr_wr (nocutpkt_out_recycle_addr_wr),
.buf_addr_wr (nocutbuf_addr_wr),
.buf_addr (nocutbuf_addr));
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_even_parity_assert #(
.width(width))
assert_even_parity_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_even_parity_assume #(
.width(width))
assert_even_parity_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_even_parity_cover #(
.width(width),
.OVL_COVER_SANITY_ON(OVL_COVER_SANITY_ON))
assert_even_parity_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_even_parity.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_even_parity_assert (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_even_parity_assume (clk, reset_n, test_expr, xzcheck_enable);
parameter width = 1;
input clk, reset_n;
input [width-1:0] test_expr;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_even_parity_cover (clk, reset_n, test_expr);
parameter width = 1;
parameter OVL_COVER_SANITY_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int b, l, k = 0, p, m; cin >> b >> l; int n[l]; for (int i = 0; i < l; i++) { n[i] = 0; } for (int i = 0; i < b; i++) { cin >> p; for (int j = 0; j < p; j++) { cin >> m; n[m - 1]++; } } for (int i = 0; i < l; i++) { if (n[i] == 0) { k++; } } if (k > 0) { cout << NO ; } else { cout << YES ; } }
|
#include <bits/stdc++.h> using namespace std; long long int trash = 0; long long int a[50], c[50]; long long int value2power[50]; long long int n, m; priority_queue<long long int> mainPQ; vector<long long int> queueArray; bool test(priority_queue<long long int> &PQ, long long int *b, long long int n) { for (long long int i = n; i >= 1; i--) { for (long long int j = 1; j <= b[i]; j++) { if (PQ.empty()) { return true; } long long int top = PQ.top(); PQ.pop(); if (top >= value2power[i + 1]) { return false; } } } if (PQ.empty()) { return true; } else { return false; } } bool cutoffRemain(long long int num, long long int n) { priority_queue<long long int> auxiliaryPQ; long long int size = queueArray.size(); for (long long int i = 1; i <= size; i++) { auxiliaryPQ.push(queueArray[i - 1]); } for (long long int i = 1; i <= n; i++) { c[i] = a[i]; } for (long long int i = 1; i <= n; i++) { if (c[i] > num) { for (long long int j = 1; j <= c[i] - num; j++) { auxiliaryPQ.push(value2power[i]); } c[i] = num; } } long long int temp = c[n]; for (long long int i = n; i >= 2; i--) { c[i] = c[i - 1] - c[i]; } for (long long int i = 1; i <= n - 1; i++) { c[i] = c[i + 1]; } c[n] = temp; return test(auxiliaryPQ, c, n); } int main() { value2power[1] = 1; for (long long int i = 2; i <= 49; i++) { value2power[i] = 2 * value2power[i - 1]; } long long int temp; cin >> m; for (long long int i = 1; i <= m; i++) { scanf( %lld , &temp); bool mark = true; for (long long int j = 1; j <= 49; j++) { if (temp == value2power[j]) { a[j]++; mark = false; break; } } if (mark) { queueArray.push_back(temp); mainPQ.push(temp); } } long long int n = 0; for (long long int i = 1; i <= 40; i++) { if (a[i] < a[i + 1]) { for (long long int j = 1; j <= a[i + 1] - a[i]; j++) { queueArray.push_back(value2power[i + 1]); mainPQ.push(value2power[i + 1]); } a[i + 1] = a[i]; } } for (long long int i = 40; i >= 1; i--) { if (a[i] != 0) { n = i; break; } } if (mainPQ.size() > a[1]) { cout << -1; } else { bool v = cutoffRemain(a[1], n); if (v == false) { cout << -1; } else { long long int minremain = 0; long long int maxremain = a[1]; while (minremain < maxremain) { long long int mid = (minremain + maxremain) / 2; if (cutoffRemain(mid, n)) { maxremain = mid; } else { minremain = mid + 1; } } for (long long int i = minremain; i <= a[1]; i++) { printf( %lld , i); } } } }
|
`timescale 1ps / 1ps
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`include "firmware/src/mmc3_eth_core.v"
`include "gpio/gpio.v"
`include "bram_fifo/bram_fifo.v"
`include "bram_fifo/bram_fifo_core.v"
`include "utils/reset_gen.v"
`include "utils/fifo_32_to_8.v"
`include "utils/generic_fifo.v"
`include "utils/clock_multiplier.v"
`include "utils/clock_divider.v"
`include "utils/rbcp_to_bus.v"
`include "utils/bus_to_ip.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
localparam RESET_DELAY = 5000;
/*
localparam CLOCKPERIOD_CLKIN1 = 10*1000;
reg CLKIN1;
initial CLKIN1 = 1'b0;
always #(CLOCKPERIOD_CLKIN1 / 2) CLKIN1 = !CLKIN1;
*/
// ----- Clock (mimics a PLL) -----
localparam PLL_MUL = 5;
localparam PLL_DIV_BUS_CLK = 7;
localparam PLL_DIV_CLK250 = 4;
localparam PLL_DIV_CLK125TX = 8;
localparam PLL_DIV_CLK125TX90 = 8;
localparam PLL_DIV_CLK125RX = 8;
localparam PLL_LOCK_DELAY = 1000*1000;
wire PLL_VCO, CLK250, CLK125TX, CLK125TX90, CLK125RX;
clock_multiplier #( .MULTIPLIER(PLL_MUL) ) i_clock_multiplier( .CLK(BUS_CLK), .CLOCK(PLL_VCO) );
//clock_divider #(.DIVISOR(PLL_DIV_BUS_CLK) ) i_clock_divisor_1 ( .CLK(PLL_VCO), .RESET(1'b0), .CE(), .CLOCK(BUS_CLK) );
clock_divider #(.DIVISOR(PLL_DIV_CLK250) ) i_clock_divisor_2 ( .CLK(PLL_VCO), .RESET(1'b0), .CE(), .CLOCK(CLK250) );
clock_divider #(.DIVISOR(PLL_DIV_CLK125TX)) i_clock_divisor_3 ( .CLK(PLL_VCO), .RESET(1'b0), .CE(), .CLOCK(CLK125TX) );
clock_divider #(.DIVISOR(PLL_DIV_CLK125RX)) i_clock_divisor_4 ( .CLK(PLL_VCO), .RESET(1'b0), .CE(), .CLOCK(CLK125RX) );
reg LOCKED;
initial begin
LOCKED = 1'b0;
#(PLL_LOCK_DELAY) LOCKED = 1'b1;
end
// -------------------------
// ------- RESET/CLOCK ------- //
//wire BUS_RST;
//reset_gen ireset_gen(.CLK(BUS_CLK), .RST(BUS_RST));
reg RESET_N;
initial begin
RESET_N = 1'b0;
#(RESET_DELAY) RESET_N = 1'b1;
end
// ------- USER MODULES ------- //
wire FIFO_FULL, FIFO_READ, FIFO_NOT_EMPTY, FIFO_WRITE;
wire [31:0] FIFO_DATA;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(32)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(!FIFO_WRITE),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
wire [7:0] GPIO;
wire ENABLE;
assign ENABLE = GPIO[0];
mmc3_eth_core i_mmc3_eth_core(
.RESET_N(RESET_N),
// clocks from PLL
.BUS_CLK(BUS_CLK), .CLK125TX(CLK125TX), .CLK125TX90(CLK125TX90), .CLK125RX(CLK125RX),
.PLL_LOCKED(LOCKED),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_BYTE_ACCESS(BUS_BYTE_ACCESS),
.fifo_empty(!FIFO_NOT_EMPTY),
.fifo_full(FIFO_FULL),
.FIFO_NEXT(!FIFO_FULL && ENABLE),
.FIFO_DATA(FIFO_DATA),
.FIFO_WRITE(FIFO_WRITE),
.GPIO(GPIO)
);
initial begin
$dumpfile("/tmp/mmc3_eth.vcd");
$dumpvars(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int d[262144][4]; map<int, int> comp; int r[262144], R, pr[262144]; vector<int> vec; bool cmp(int a, int b) { return d[a][1] > d[b][1]; } struct BIT { int m[262144 * 2]; vector<int> v[262144]; void init() { int i; for (i = 0; i < n; i++) v[comp[d[i][0]]].push_back(i); for (i = 0; i < 262144; i++) { if (v[i].size()) { sort(v[i].begin(), v[i].end(), cmp); m[262144 + i] = d[v[i].back()][1]; } else m[262144 + i] = 2147483647; } for (i = 262144 - 1; i >= 1; i--) m[i] = m[i * 2] < m[i * 2 + 1] ? m[i * 2] : m[i * 2 + 1]; } void gohelp(int p, int i) { if (m[p] > d[i][3]) return; if (p < 262144) { gohelp(p * 2, i); gohelp(p * 2 + 1, i); } else { while (v[p - 262144].size()) { int j = v[p - 262144].back(); if (d[j][1] <= d[i][3]) { vec.push_back(j); r[j] = R; pr[j] = i; v[p - 262144].pop_back(); } else break; } if (v[p - 262144].size()) m[p] = d[v[p - 262144].back()][1]; else m[p] = 2147483647; for (p /= 2; p; p /= 2) m[p] = m[p * 2] < m[p * 2 + 1] ? m[p * 2] : m[p * 2 + 1]; } } void go(int p, int i) { p += 262144; gohelp(p, i); for (; p > 1; p /= 2) { if (p & 1) gohelp(p - 1, i); } } } bit; int main() { int i; scanf( %d , &n); comp[0] = 1; for (i = 0; i < n; i++) { scanf( %d%d%d%d , &d[i][0], &d[i][1], &d[i][2], &d[i][3]); comp[d[i][0]] = comp[d[i][2]] = 1; } i = 0; for (auto& it : comp) it.second = i++; bit.init(); memset(r, -1, sizeof(r)); vector<int> vecpr; vecpr.push_back(n); while (vecpr.size()) { vec.clear(); R++; for (int i : vecpr) bit.go(comp[d[i][2]], i); vecpr = vec; } printf( %d n , r[n - 1]); if (r[n - 1] != -1) { vector<int> path; for (i = n - 1; r[i] > 1; i = pr[i]) path.push_back(i); path.push_back(i); for (i = path.size() - 1; i >= 0; i--) printf( %d , path[i] + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int mynum(int x, int y) { int temp; stringstream ss; ss << (s.substr(x, y - x)); ss >> temp; if (temp > 1000000 || (y - x != 1 && s[x] == 0 ) || x == y) return -1; return temp; } int main() { int mx = -1, x, y, z; cin >> s; for (int i = 0; i < s.length(); i++) { for (int j = i + 1; j < s.length(); j++) { x = mynum(0, i); y = mynum(i, j); z = mynum(j, s.length()); if (x != -1 && y != -1 && z != -1 && x + y + z > mx) mx = x + y + z; } } cout << mx; return 0; }
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 13.1 cbx_altiobuf_out 2013:11:26:18:14:54:SJ cbx_mgl 2013:11:26:18:15:59:SJ cbx_stratixiii 2013:11:26:18:14:54:SJ cbx_stratixv 2013:11:26:18:14:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; const int MAX = 200005; map<int, int> Map; struct Node { int au, sub; } node[MAX]; int n, temp, m; int main() { cin >> n; for (int i = 1; i <= n; i++) { scanf( %d , &temp); Map[temp]++; } int m; scanf( %d , &m); for (int i = 1; i <= m; i++) { scanf( %d , &node[i].au); } int Max1, Max2; Max1 = Max2 = 0; int id = 1; for (int i = 1; i <= m; i++) { scanf( %d , &node[i].sub); if (Map[node[i].au] > Max1 || (Map[node[i].au] == Max1 && Map[node[i].sub] > Max2)) { Max1 = Map[node[i].au]; Max2 = Map[node[i].sub]; id = i; } } cout << id << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0; char ch = getchar(); bool f = 0; for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = 1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return f ? -x : x; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); puts( ); } void writep(long long x) { write(x); putchar( ); } const int N = 1000005; int n, cnt; struct info { long long x, y, z; int id; } a[N], b[N]; bool cmp(info a, info b) { if (a.x != b.x) return a.x < b.x; if (a.y != b.y) return a.y < b.y; return a.z < b.z; } void solve(bool d) { cnt = 0; sort(a + 1, a + n + 1, cmp); for (int i = 1, j = 1; i <= n; i = j + 1) { j = i; if (d) { while (j + 1 <= n && a[j + 1].x == a[j].x && a[j + 1].y == a[j].y) j++; } else while (j + 1 <= n && a[j + 1].x == a[j].x) j++; for (int k = i; k <= j; k += 2) { if (k + 1 > j) break; writep(a[k].id); writeln(a[k + 1].id); } if ((j - i + 1) % 2) b[++cnt] = a[j]; } if (cnt == 0) exit(0); n = cnt; for (int i = (int)(1); i <= (int)(n); i++) a[i] = b[i]; } int main() { n = read(); for (int i = (int)(1); i <= (int)(n); i++) a[i].x = read(), a[i].y = read(), a[i].z = read(), a[i].id = i; solve(1); solve(0); for (int i = 1; i <= n; i += 2) writep(a[i].id), writeln(a[i + 1].id); }
|
#include <bits/stdc++.h> using namespace std; int const N = int(2e5) + 7; int const mod = int(1e9) + 7; int a[N]; int ra[N], le[N]; int raB[N][31], leB[N][31]; int main() { ios_base::sync_with_stdio(false); ifstream in( input.txt ); int n; cin >> n; vector<int> st; for (int i = 1; i <= n; ++i) { cin >> a[i]; while (st.size() > 0 && a[st.back()] <= a[i]) { int ind = st.back(); st.pop_back(); int ll = 0; if (st.size() > 0) { ll = st.back(); } le[ind] = ll; ra[ind] = i; } st.push_back(i); for (int j = 0; j <= 30; ++j) { if (a[i] & (1 << j)) { leB[i][j] = i; } else { leB[i][j] = leB[i - 1][j]; } } } while (st.size() > 0) { int ind = st.back(); st.pop_back(); int ll = 0; if (st.size() > 0) { ll = st.back(); } le[ind] = ll; ra[ind] = n + 1; } for (int i = n; i >= 0; --i) { for (int j = 0; j <= 30; ++j) { if (a[i] & (1 << j)) { raB[i][j] = i; } else { raB[i][j] = raB[i + 1][j]; } } } long long ans = 0; for (int i = 1; i <= n; ++i) { int indl = 0, indr = n + 1; for (int j = 30; j >= 0; --j) { if (!(a[i] & (1 << j)) && (leB[i - 1][j])) { indl = max(indl, leB[i - 1][j]); } } for (int j = 30; j >= 0; --j) { if (!(a[i] & (1 << j)) && (raB[i + 1][j])) { indr = min(indr, raB[i + 1][j]); } } long long am1 = max(0, indl - le[i]); long long am2 = max(0, i - max(indl, le[i])); long long am3 = max(0, min(ra[i], indr) - i); long long am4 = max(0, ra[i] - indr); long long del = am1 * (am3 + am4) + am2 * am4; ans += am1 * (am3 + am4) + am2 * am4; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int OO = INT_MAX; const int N = 2e5 + 2; const int MOD = 1e9 + 7; double ebs = 1e-6; const int INF = 0x3f3f3f3f; int in[N]; map<int, int> mp; int main() { ios::sync_with_stdio(0); int t; cin >> t; while (t--) { mp.clear(); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> in[i]; mp[in[i]]++; } long long res = 0, m = 0; for (auto it = mp.begin(); it != mp.end(); it++) { it->second += m; res += it->second / it->first; m = it->second % it->first; } cout << res << endl; } }
|
#include <bits/stdc++.h> using namespace std; int dp[2][316 + 1][316 + 2]; int addmod(int x, int y) { int sum = x + y; if (sum >= 1000000007) sum -= 1000000007; return sum; } int mulmod(int x, int y, int p) { long long prod = x; prod = (prod * y) % p; return (int)prod; } void add_to_mod(int &x, int y) { x = addmod(x, y); } int run_dp(int n, int m, int x) { int result = 0; if (n > m) return result; int next = 0; dp[next][0][0] = 1; for (int i = 1; i <= m; i++) { int prev = next; next ^= 1; for (int j = n; j > 0; j--) for (int k = j; k >= 0; k--) { dp[next][j][k] = addmod(dp[prev][j - 1][k], dp[next][j][k + 1]); if (m - i != x - k) { int s = dp[prev][j][k]; if (k > 0) add_to_mod(s, dp[next][j - 1][k - 1]); add_to_mod(dp[next][j][k], s); } } dp[next][0][0] = (m - i) > x; } result = dp[next][n][0]; for (int i = 2; i <= n; i++) result = mulmod(result, i, 1000000007); return result; } int solve_problem() { int n, m, x; if (scanf( %d %d %d , &n, &m, &x) != 3) return 1; --x; int result = run_dp(n, m, x); printf( %d n , result); return 0; } int main() { solve_problem(); return 0; }
|
#include <bits/stdc++.h> using namespace std; using lli = long long int; int main() { int n; cin >> n; if (n == 2) { cout << 1 << endl << 1 << << 1 << endl; return 0; } else if (n == 3) { cout << 0 n2 1 2 n ; } else if (n == 4) { cout << 0 n2 1 4 n ; } else { vector<int> v; vector<int> c; lli sum_v = 0, sum_c = 0; for (lli i = n; i >= 1; i--) { if (abs(sum_v + i - sum_c) < abs(sum_c + i - sum_v)) { sum_v += i; v.push_back(i); } else { sum_c += i; c.push_back(i); } } cout << abs(sum_v - sum_c) << endl; cout << c.size() << ; int in = c.size(); for (lli i = 0; i < (in); i++) { cout << c[i]; if (i == in - 1) cout << endl; else cout << ; } } }
|
/* sigma-delta modulator bench */
`timescale 1ns/10ps
`define CLK_HPER 17.8571
module sdm_tb();
// variables
reg clk;
real lsum=0, rsum=0;
real lmean=0, rmean=0;
reg [14:0] ldata_in;
reg [14:0] rdata_in;
wire ldata_out;
wire rdata_out;
// constants
real ifactor = 128;
integer steps = 4096;
// integrator function
function integrate;
input real mean;
input real in;
begin
integrate = mean - mean/ifactor + in/ifactor;
end
endfunction
// sdm_convert task
task sdm_convert;
input signed [14:0] val;
begin
$display("Testing %d", val);
ldata_in = val;
rdata_in = val;
lsum = 0;
rsum = 0;
repeat(steps) @ (posedge clk) begin
lsum = lsum + ldata_out-0.5;
rsum = rsum + rdata_out-0.5;
lmean = lmean - lmean/ifactor + (ldata_out-0.5)/ifactor;
rmean = rmean - rmean/ifactor + (rdata_out-0.5)/ifactor;
end
$display("Average lout (0) = %f", lsum/steps);
$display("Average rout (0) = %f", rsum/steps);
end
endtask
////////////////////////////////////////
// clock
initial begin
clk = 1'b0;
forever #`CLK_HPER clk = ~clk;
end
// testbench
initial begin
$display("SDM bench starting ...");
// 0
sdm_convert(0);
// 1
sdm_convert({1'b0, {14{1'b1}}});
// -1
sdm_convert({1'b1, {14{1'b0}}});
// 1
sdm_convert({1'b0, {14{1'b1}}});
// -0.5
sdm_convert(15'h6000);
// 0.5
sdm_convert(15'h1fff);
// 0
sdm_convert(0);
$display("SDM bench stopping ...");
$finish;
end
// dut
sdm sdm (
.clk (clk),
.ldatasum (ldata_in),
.rdatasum (rdata_in),
.left (ldata_out),
.right (rdata_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void Read(T &x) { char c; bool f(0); while (c = getchar(), c != EOF) { if (c == - ) f = 1; else if (c >= 0 && c <= 9 ) { x = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) x = x * 10 + c - 0 ; ungetc(c, stdin); if (f) x = -x; return; } } } struct point { int x, y; inline point() {} inline point(int x, int y) : x(x), y(y) {} inline point operator-(const point &b) const { return point(x - b.x, y - b.y); } inline bool operator<(const point &b) const { if (x == b.x) return y < b.y; return x < b.x; } inline bool operator>(const point &b) const { if (x == b.x) return y > b.y; return x > b.x; } inline bool operator==(const point &b) const { return x == b.x && y == b.y; } } a[100000 + 10]; int Q; set<point> s; set<point, greater<point> > s2; inline long long cross(const point &a, const point &b) { return 1ll * a.x * b.y - 1ll * a.y * b.x; } template <class T> void insert(T &s, const point &a) { auto i = s.lower_bound(a); if (i != s.end() && *i == a) return; auto j = i; if (j != s.begin()) { j--; while (j != s.begin()) { auto k = j--; if (cross(*k - *j, a - *k) > 0) break; s.erase(k); } } if (i != s.end()) { auto k = i; while (++i != s.end()) { if (cross(*k - a, *i - a) > 0) break; s.erase(k); k = i; } } i = s.lower_bound(a); if (i == s.end() || i == s.begin()) s.insert(a); else { auto j = i--; if (cross(a - *i, *j - *i) > 0) s.insert(a); } } template <class T> bool check(const T &s, const point &a) { auto i = s.lower_bound(a); if (*i == a) return 1; if (i == s.begin() || i == s.end()) return 0; auto j = i--; return cross(a - *i, *j - *i) <= 0; } int main() { Read(Q); int p, x, y; while (Q--) { Read(p), Read(x), Read(y); if (p == 1) { insert(s, point(x, y)); insert(s2, point(x, y)); } else puts(check(s, point(x, y)) && check(s2, point(x, y)) ? YES : NO ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y; cin >> x >> y; int m = 0; while (x * 100 + y * 10 >= 220) { int kx, ky; if (m % 2 == 0) { kx = min(2, x); x -= kx; ky = (220 - 100 * kx) / 10; y -= ky; if (y < 0) break; } else { if (y >= 22) ky = 22; else if (y >= 12) ky = 12; else ky = 2; y -= ky; if (y < 0) break; kx = (220 - ky * 10) / 100; x -= kx; if (x < 0) break; } m++; } if (m % 2 == 1) { cout << Ciel n ; } else cout << Hanako n ; return 0; }
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#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long a, long b) { return ((a * b) / gcd(a, b)); } long long a[100000]; int main() { long long i, j, k, l, m, n, maxx = 0, g = 0; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (i = 0; i < n; i++) { while (a[i] % 2 == 0) { a[i] /= 2; } while (a[i] % 3 == 0) { a[i] /= 3; } } sort(a, a + n); if (a[0] == a[n - 1]) cout << Yes << endl; else cout << NO << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1111; int n; string a[N], b[N]; int t[N]; int d; std::set<pair<string, string> > res; int main() { cin >> n >> d; for (int i = 0; i < n; i++) cin >> a[i] >> b[i] >> t[i]; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { if (!(a[i] == b[j] && a[j] == b[i])) continue; int m = min(t[i], t[j]); int M = max(t[i], t[j]); if (M - m <= 0 || M - m > d) continue; res.insert(make_pair(a[i], b[i])); res.insert(make_pair(b[i], a[i])); } cout << res.size() / 2 << endl; for (set<pair<string, string> >::iterator it = res.begin(); it != res.end(); ++it) { string s1 = it->first, s2 = it->second; if (s1 < s2) cout << s1 << << s2 << endl; } }
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#include <bits/stdc++.h> using namespace std; struct group { int sz; vector<int> worst, best; group(vector<int>& a) : sz(1), worst(a.begin(), a.end()), best(a.begin(), a.end()) {} bool operator<(const group& a) const { for (int i = 0; i < best.size(); i++) if (best[i] >= a.worst[i]) return false; return true; } struct group& operator+=(const group& a) { sz += a.sz; for (int i = 0; i < best.size(); i++) { best[i] = max(best[i], a.best[i]); worst[i] = min(worst[i], a.worst[i]); } return *this; } }; set<group> positions; int main() { int n, k; scanf( %d %d , &n, &k); while (n--) { vector<int> skills(k, 0); for (int i = 0; i < k; i++) scanf( %d , &skills[i]); group player = group(skills); auto f = positions.lower_bound(player), l = positions.upper_bound(player); while (f != l) { player += *f; f = positions.erase(f); } positions.insert(f, player); printf( %d n , positions.rbegin()->sz); } return 0; }
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// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for registers.
module Registers_Test;
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=16;
reg clk; // System clock
reg reset; // System reset
reg en; // Access enable
reg rd; // Read enable
reg wr; // Write enable
reg byte_lo; // Low byte enable
reg byte_hi; // High byte enable
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
Registers #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
registers(.reset(reset),
.en(en),
.rd(rd),
.wr(wr),
.be({byte_hi, byte_lo}),
.addr(addr),
.data_in(data_in),
.data_out(data_out));
// Generate clock.
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
rd = 0;
wr = 0;
// Reset
#5 reset = 1;
#1 reset = 0;
#5 stage = 1;
#1 read_test();
#1 addr = 'bx;
// Test some writes
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
// Test some reads
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
// Test some byte writes
#5 stage = 4;
for (i = 0; i < 15; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
// Test some reads
#5 stage = 5;
#1 read_test();
end
// Task to write a word.
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = data_arg;
#1 en = 1; rd = 0; wr = 1; byte_lo = 1; byte_hi = 1;
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
// Task to write a byte.
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH/2-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = {data_arg, data_arg};
#1 en = 1; rd = 0; wr = 1; byte_lo = ~addr_arg[0]; byte_hi = addr_arg[0];
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
// Task to read a word.
task read;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg >> 1;
data_in = 'bz;
#1 en = 1; rd = 1; wr = 0;
#3 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0;
end
endtask
// Readback test for the register
task read_test;
begin
// Test some reads
#5 read(0);
#1 read(2);
#1 read(4);
#1 read(8);
#1 read(16);
#1 read(17);
#1 read(18);
#1 read(19);
#1 read(24);
#1 read(25);
#1 read(26);
#1 read(27);
end
endtask
endmodule
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#include <bits/stdc++.h> using namespace std; using namespace std; int main() { string s; cin >> s; vector<string> v(10); for (int i = 0; i < 10; i++) { cin >> v[i]; } string res = ; for (int i = 0; i <= 70; i += 10) { string find = s.substr(i, 10); for (int j = 0; j < 10; j++) { if (v[j] == find) { res.push_back(j + 0 ); break; } } } cout << res << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m, K, w[N]; inline char nc() { static char buf[100000], *p1 = buf, *p2 = buf; if (p1 == p2) { p2 = (p1 = buf) + fread(buf, 1, 100000, stdin); if (p1 == p2) return EOF; } return *p1++; } inline void read(int& x) { char tr = nc(), b = 1; for (; tr < 0 || tr > 9 ; tr = nc()) if (tr == - ) b = -1; for (x = 0; tr >= 0 && tr <= 9 ; x = (x << 3) + (x << 1) + tr - 48, tr = nc()) ; x *= b; } inline int count() { int ret = 0, x; for (int i = 0; i < n - 1; i++) for (int j = 0; j < m - 1; j++) x = i * m + j, ret += (w[x] & w[x + m] & w[x + 1]) + (w[x + m + 1] & w[x + m] & w[x + 1]) + (w[x] & w[x + m] & w[x + m + 1]) + (w[x] & w[x + 1] & w[x + m + 1]); return ret; } int Q[N], l, r, ins[N]; const int dx[6] = {0, 0, 1, -1}; const int dy[6] = {1, -1, 0, 0}; inline int pd() { l = r = -1; for (int i = 0; i < n * m; i++) ins[i] = 0; for (int i = 0; i < n * m; i++) if (w[i]) { Q[++r] = i; break; } while (l < r) { ++l; int x = Q[l] / m, y = Q[l] % m; for (int k = 0; k < 4; k++) { int sx = x + dx[k], sy = y + dy[k]; if (sx < 0 || sy < 0 || sx >= n || sy >= m || ins[sx * m + sy] || !w[sx * m + sy]) continue; Q[++r] = sx * m + sy; ins[sx * m + sy] = 1; } } for (int i = 0; i < n * m; i++) if (w[i] && !ins[i]) return 0; return 1; } inline int check(int mid) { for (int i = 0; i < n * m; i++) w[i] = (i <= mid); return count(); } inline int Solve() { int C = 4 * (n - 1) * (m - 1), L = -1, R = n * m, MID; if (K > C) return 0; if (n == 3 || m == 3) { if (K == C - 1 || K == C - 2 || K == C - 4 || K == C - 5) return 0; } else { if (K == C - 1 || K == C - 2 || K == C - 4 || K == C - 5 || K == C - 8) return 0; } while (L + 1 < R) if (check(MID = (L + R) >> 1) >= K) R = MID; else L = MID; int cur = check(R); if (cur == K) return 1; vector<int> bl, em; for (int i = 0; i < n * m; i++) if (min(i / m, abs(i / m - R / m)) <= 1) w[i] ? bl.push_back(i) : em.push_back(i); int x, p; while (cur != K) { if (cur < K) { x = em[p = rand() % ((int)em.size())]; w[x] = 1; if (!pd()) { w[x] = 0; continue; } em.erase(em.begin() + p); bl.push_back(x); cur = count(); } else { x = bl[p = rand() % ((int)bl.size())]; w[x] = 0; if (!pd()) { w[x] = 1; continue; } bl.erase(bl.begin() + p); em.push_back(x); cur = count(); } } return 1; } int main() { int T; read(T); while (T--) { read(n); read(m); read(K); int flag = 0; if (n < m) swap(n, m), flag = 1; if (Solve()) { if (!flag) { for (int i = 0; i < n; i++, putchar( n )) for (int j = 0; j < m; j++) putchar(w[i * m + j] ? * : . ); } else { for (int j = 0; j < m; j++, putchar( n )) for (int i = 0; i < n; i++) putchar(w[i * m + j] ? * : . ); } putchar( n ); } else printf( -1 n n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long long INF = 1e18; const int MAXN = 1e5 + 5; long long i, j, m, n, k, t, d; long long ans; long long x[MAXN]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> d; for (i = 1; i <= n; i++) { cin >> x[i]; } for (i = 1; i <= n; i++) { long long low = i + 2, high = n, mid, ok = -1; while (low <= high) { mid = (low + high) / 2; if (x[mid] - x[i] <= d) { ok = mid; low = mid + 1; } else { high = mid - 1; } } if (ok == -1) continue; ans += (ok - i) * (ok - i - 1) / 2; } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int V[102][102], M2[2][102]; int main() { int n, a; scanf( %d , &n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { scanf( %d , &a); M2[0][i] += a; M2[1][j] += a; } int cnt = 0; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (M2[0][i] < M2[1][j]) cnt++; cout << cnt << endl; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// 3 3 4
reg [71:0] memw [2:0][1:3][5:2];
reg [7:0] memn [2:0][1:3][5:2];
// verilator lint_on BLKANDNBLK
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [71:0] wide;
reg [7:0] narrow;
reg [1:0] index0;
reg [1:0] index1;
reg [2:0] index2;
integer i0,i1,i2;
integer imem[2:0][1:3];
reg [2:0] cstyle[2];
initial begin
for (i0=0; i0<3; i0=i0+1) begin
for (i1=1; i1<4; i1=i1+1) begin
imem[i0[1:0]] [i1[1:0]] = i1;
for (i2=2; i2<6; i2=i2+1) begin
memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]};
memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001;
end
end
end
end
reg [71:0] wread;
reg wreadb;
always @ (posedge clk) begin
//$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
narrow <= 8'h0;
wide <= 72'h0;
index0 <= 2'b0;
index1 <= 2'b0;
index2 <= 3'b0;
end
else if (cyc<90) begin
index0 <= crc[1:0];
index1 <= crc[3:2];
index2 <= crc[6:4];
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
// We never read past bounds, or get unspecific results
// We also never read lowest indexes, as writing outside of range may corrupt them
if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin
narrow <= ({narrow[6:0], narrow[7]^narrow[0]}
^ {memn[index0][index1][index2]});
wread = memw[index0][index1][index2];
wreadb = memw[index0][index1][index2][2];
wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread);
//$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread);
end
// We may write past bounds of memory
memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0];
memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
memw[index0][index1][index2] <= {~crc[7:0],crc};
//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
cstyle[cyc[0]] <= cyc[2:0];
if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop;
end
else if (cyc==90) begin
memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
end
else if (cyc==91) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide);
if (crc != 64'h65e3bddcd9bc2750) $stop;
if (narrow != 8'hca) $stop;
if (wide != 72'h4edafed31ba6873f73) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [7:0] array [2:0][1:3];
integer cyc; initial cyc=0;
integer i0,i1,i2;
genvar g0,g1,g2;
generate
for (g0=0; g0<3; g0=g0+1) begin
for (g1=1; g1<4; g1=g1+1) begin
inst inst (.q(array[g0[1:0]] [g1[1:0]]),
.cyc(cyc),
.i0(g0[1:0]),
.i1(g1[1:0]));
end
end
endgenerate
always @ (posedge clk) begin
//$write("cyc==%0d\n",cyc);
cyc <= cyc + 1;
if (cyc==2) begin
if (array[2][1] !== 8'h92) $stop;
for (i0=0; i0<3; i0=i0+1) begin
for (i1=1; i1<4; i1=i1+1) begin
//$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]);
if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop;
end
end
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module inst (/*AUTOARG*/
// Outputs
q,
// Inputs
cyc, i0, i1
);
output reg [7:0] q;
input [31:0] cyc;
input [1:0] i0;
input [1:0] i1;
inst2 inst2 (/*AUTOINST*/
// Inputs
.cyc (cyc[31:0]),
.i0 (i0[1:0]),
.i1 (i1[1:0]));
always @* begin
q = {i0, i1, cyc[3:0]};
end
endmodule
module inst2 (/*AUTOARG*/
// Inputs
cyc, i0, i1
);
/*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining
input [31:0] cyc;
input [1:0] i0;
input [1:0] i1;
initial begin
if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1);
end
endmodule
|
#include<bits/stdc++.h> #define N 200100 #define ll long long using namespace std; const ll inf=9223372036854775807; ll n,m; ll T; ll a[N]; ll maxx=-inf; ll ans; ll anss; int main(){ cin>>T; while(T--){ ans=0; maxx=-inf; cin>>n; scanf( %lld ,&a[1]); for(int i=2;i<=n;i++){ scanf( %lld ,&a[i]); //maxx=max(maxx,abs(a[i]-a[i-1])); ans+=abs(a[i]-a[i-1]); } anss=ans; anss=min(anss,ans-abs(a[2]-a[1])); anss=min(anss,ans-abs(a[n]-a[n-1])); for(int i=2;i<=n-1;i++){ anss=min(anss,ans-abs(a[i+1]-a[i])-abs(a[i-1]-a[i])+abs(a[i-1]-a[i+1])); //anss=min(anss,ans-abs(a[i-1]-a[i])+abs(a[i-1]-a[i+1])); } cout<<anss<<endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; double xx[10], yy[10]; int main() { double px, py, vx, vy, a, b, c, d; cin >> px >> py >> vx >> vy >> a >> b >> c >> d; double x = vx / sqrt(vx * vx + vy * vy); double y = vy / sqrt(vx * vx + vy * vy); xx[1] = b * x + px; yy[1] = b * y + py; xx[2] = px - (y * a / 2); yy[2] = py + (x * a / 2); xx[3] = px - (y * c / 2); yy[3] = py + (x * c / 2); xx[4] = xx[3] - (d * x); yy[4] = yy[3] - (d * y); xx[6] = px + (y * c / 2); yy[6] = py - (x * c / 2); xx[5] = xx[6] - (x * d); yy[5] = yy[6] - (d * y); xx[7] = px + (y * a / 2); yy[7] = py - (x * a / 2); cout.precision(20); for (int i = 1; i <= 7; i++) cout << xx[i] << << yy[i] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int INF = 1000000001; const long long LINF = 1000000000000000001LL; struct ConvexHullTrick { struct line { int a; long long b; long long eval(int x) { return (long long)a * x + b; } }; bool incrSlope, incrQueries, queryMax; ConvexHullTrick(bool incrSlope, bool incrQueries, bool queryMax) : incrSlope(incrSlope), incrQueries(incrQueries), queryMax(queryMax) { assert(incrSlope xor incrQueries xor queryMax); } deque<line> lines; long long overtakes(const line &p, const line &q) { long long x = p.b - q.b; int y = p.a - q.a; return (x >= 0 ? x : x - y + 1) / y; } bool redundantTop(const line &l) { int s = lines.size(); if (l.a == lines[s - 1].a) { return true; } else { return overtakes(l, lines[s - 1]) >= overtakes(lines[s - 1], lines[s - 2]); } } void add(int a, long long b) { if (!(incrSlope xor incrQueries xor queryMax)) a *= -1; if (queryMax) b *= -1; if (!lines.empty() && a == lines.back().a && b >= lines.back().b) { return; } line l = {a, b}; while (lines.size() >= 2 && redundantTop(l)) { lines.pop_back(); } lines.push_back(l); } long long query(int x) { if (!(incrSlope xor incrQueries)) x *= -1; while (lines.size() >= 2 && lines[0].eval(x) > lines[1].eval(x)) { lines.pop_front(); } return lines.front().eval(x) * (queryMax ? -1 : 1); } }; int main() { ios_base::sync_with_stdio(false); ConvexHullTrick hull(false, false, true); auto add = [&](long long dpValue, int x) { hull.add(-x, dpValue); }; int n; cin >> n; struct rect { int x, y; long long a; }; vector<rect> rects(n); for (auto &e : rects) { cin >> e.x >> e.y >> e.a; } sort(rects.begin(), rects.end(), [&](const rect &a, const rect &b) { return a.x < b.x; }); vector<long long> dp(n + 1, 0); add(0, 0); for (int i = (1); i <= (n); i++) { auto r = rects[i - 1]; dp[i] = (long long)r.x * r.y - r.a + hull.query(r.y); add(dp[i], r.x); } long long ans = *max_element(dp.begin(), dp.end()); cout << ans; return 0; }
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//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//COPY ME, CUSTOMIZE ME...
//The following module is used to re-write receive packets to the host.
//This module provides a packet-based ram interface for manipulating packets.
//The user writes a custom engine (state machine) to read the input packet,
//and to produce a new output packet.
//By default, this entire module is a simple pass-through.
module custom_engine_rx
#(
//buffer size for ram interface engine
parameter BUF_SIZE = 10
)
(
//control signals
input clock, input reset, input clear,
//user settings bus, controlled through user setting regs API
input set_stb, input [7:0] set_addr, input [31:0] set_data,
//ram interface for engine
output access_we,
output access_stb,
input access_ok,
output access_done,
output access_skip_read,
output [BUF_SIZE-1:0] access_adr,
input [BUF_SIZE-1:0] access_len,
output [35:0] access_dat_o,
input [35:0] access_dat_i
);
assign access_done = access_ok;
endmodule //custom_engine_rx
|
#include <bits/stdc++.h> using namespace std; struct node { int u, v, w; } arr[300010]; bool cmp(node a, node b) { return (a.w < b.w); } int n, m; int f[300010], f2[300010]; int main() { scanf( %d , &n); ; scanf( %d , &m); ; for (int i = 0; i < m; i++) { scanf( %d , &arr[i].u); ; scanf( %d , &arr[i].v); ; scanf( %d , &arr[i].w); ; } sort(arr, arr + m, cmp); int ans = 0; for (int i = 0, j = 0; i < m; i = j) { while (j < m && arr[i].w == arr[j].w) j++; for (int k = i; k < j; k++) f2[arr[k].v] = f[arr[k].v]; for (int k = i; k < j; k++) f2[arr[k].v] = max(f2[arr[k].v], 1 + f[arr[k].u]); for (int k = i; k < j; k++) f[arr[k].v] = f2[arr[k].v]; for (int k = i; k < j; k++) ans = max(ans, f[arr[k].v]); } cout << ans; }
|
module PS_flops_EX_WB_alu (
in_wfid,
in_instr_pc,
in_vgpr_dest_addr,
in_sgpr_dest_addr,
in_instr_done,
in_vgpr_wr_en,
in_sgpr_wr_en,
in_vcc_wr_en,
out_wfid,
out_instr_pc,
out_vgpr_dest_addr,
out_sgpr_dest_addr,
out_instr_done,
out_vgpr_dest_wr_en,
out_sgpr_dest_wr_en,
out_vcc_wr_en,
clk,
rst
);
input [5:0] in_wfid;
input [31:0] in_instr_pc;
input [9:0] in_vgpr_dest_addr;
input [8:0] in_sgpr_dest_addr;
input in_instr_done;
input in_vgpr_wr_en;
input in_sgpr_wr_en;
input in_vcc_wr_en;
output [5:0] out_wfid;
output [31:0] out_instr_pc;
output [9:0] out_vgpr_dest_addr;
output [8:0] out_sgpr_dest_addr;
output out_instr_done;
output out_vgpr_dest_wr_en;
output out_sgpr_dest_wr_en;
output out_vcc_wr_en;
input clk;
input rst;
dff flop_wfid[5:0] (.q(out_wfid), .d(in_wfid), .clk(clk), .rst(rst));
dff flop_instr_pc[31:0] (.q(out_instr_pc), .d(in_instr_pc), .clk(clk), .rst(rst));
dff flop_vgpr_dest_addr[9:0] (.q(out_vgpr_dest_addr), .d(in_vgpr_dest_addr), .clk(clk), .rst(rst));
dff flop_sgpr_dest_addr[8:0] (.q(out_sgpr_dest_addr), .d(in_sgpr_dest_addr), .clk(clk), .rst(rst));
dff flop_instr_done (.q(out_instr_done), .d(in_instr_done), .clk(clk), .rst(rst));
dff flop_vgpr_wr_en (.q(out_vgpr_dest_wr_en), .d(in_vgpr_wr_en), .clk(clk), .rst(rst));
dff flop_sgpr_wr_en (.q(out_sgpr_dest_wr_en), .d(in_sgpr_wr_en), .clk(clk), .rst(rst));
dff flop_vcc_wr_en (.q(out_vcc_wr_en), .d(in_vcc_wr_en), .clk(clk), .rst(rst));
endmodule
|
module ISP1362_IF( // HOST Side
iDATA,
oDATA,
iADDR,
iRD_N,
iWR_N,
iCS_N,
iRST_N,
iCLK,
oINT0_N,
oINT1_N,
// ISP1362 Side
OTG_DATA,
OTG_ADDR,
OTG_RD_N,
OTG_WR_N,
OTG_CS_N,
OTG_RST_N,
OTG_INT0,
OTG_INT1 );
// HOST Side
input [15:0] iDATA;
input [1:0] iADDR;
input iRD_N;
input iWR_N;
input iCS_N;
input iRST_N;
input iCLK;
output [15:0] oDATA;
output oINT0_N;
output oINT1_N;
// ISP1362 Side
inout [15:0] OTG_DATA;
output [1:0] OTG_ADDR;
output OTG_RD_N;
output OTG_WR_N;
output OTG_CS_N;
output OTG_RST_N;
input OTG_INT0;
input OTG_INT1;
reg [1:0] OTG_ADDR;
reg OTG_RD_N;
reg OTG_WR_N;
reg OTG_CS_N;
reg [15:0] TMP_DATA;
reg [15:0] oDATA;
reg oINT0_N;
reg oINT1_N;
assign OTG_DATA = OTG_WR_N ? 16'hzzzz : TMP_DATA ;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
TMP_DATA <= 0;
OTG_ADDR <= 0;
OTG_RD_N <= 1;
OTG_WR_N <= 1;
OTG_CS_N <= 1;
TMP_DATA <= 0;
oDATA <= 0;
oINT0_N <= 1;
oINT1_N <= 1;
end
else
begin
oDATA <= OTG_DATA;
oINT0_N <= OTG_INT0;
oINT1_N <= OTG_INT1;
TMP_DATA <= iDATA;
OTG_ADDR <= iADDR;
OTG_RD_N <= iRD_N;
OTG_WR_N <= iWR_N;
OTG_CS_N <= iCS_N;
end
end
assign OTG_RST_N = iRST_N;
endmodule
|
#include <bits/stdc++.h> int main() { int n, m, k; while (scanf( %d%d , &n, &m) != EOF) { int ans = n / m; k = n % m; for (int i = 1; i <= m; i++) { if (i <= m - k) { printf( %d , ans); } else { printf( %d , ans + 1); } if (i != m) { printf( ); } else { printf( n ); } } } }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; int n, k; double h; struct lms { int i, m, v; } a[100005]; int pos[100005]; inline int put(double t) { int ptr = 1; for (int i = 0; i < n; ++i) { if ((double)ptr <= t * a[i].v) { pos[ptr] = a[i].i; ++ptr; } } return ptr - 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k >> h; for (int i = 0; i < n; ++i) a[i].i = i + 1; for (int i = 0; i < n; ++i) cin >> a[i].m; for (int i = 0; i < n; ++i) cin >> a[i].v; sort(a, a + n, [](const lms &a, const lms &b) { return a.m == b.m ? a.v < b.v : a.m < b.m; }); double L = 0, R = 1e9, A = R; int t = 90; while (t--) { double M = (L + R) / 2; if (put(M) >= k) R = A = M; else L = M; } put(A); for (int i = 1; i <= k; ++i) cout << pos[i] << ; cout << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_BEHAVIORAL_PP_V
|
// sram.v
// This file was auto-generated as part of a generation operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module sram (
input wire iCLK, // clk.clk
inout wire [15:0] SRAM_DQ, // avalon_slave_0_export.export
output wire [17:0] SRAM_ADDR, // .export
output wire SRAM_UB_N, // .export
output wire SRAM_LB_N, // .export
output wire SRAM_WE_N, // .export
output wire SRAM_CE_N, // .export
output wire SRAM_OE_N, // .export
input wire [15:0] iDATA, // avalon_slave_0.writedata
output wire [15:0] oDATA, // .readdata
input wire [17:0] iADDR, // .address
input wire iWE_N, // .write_n
input wire iOE_N, // .read_n
input wire iCE_N, // .chipselect_n
input wire [1:0] iBE_N, // .byteenable_n
input wire iRST_N // reset_n.reset_n
);
SRAM_16Bit_512K sram (
.iCLK (iCLK), // clk.clk
.SRAM_DQ (SRAM_DQ), // avalon_slave_0_export.export
.SRAM_ADDR (SRAM_ADDR), // .export
.SRAM_UB_N (SRAM_UB_N), // .export
.SRAM_LB_N (SRAM_LB_N), // .export
.SRAM_WE_N (SRAM_WE_N), // .export
.SRAM_CE_N (SRAM_CE_N), // .export
.SRAM_OE_N (SRAM_OE_N), // .export
.iDATA (iDATA), // avalon_slave_0.writedata
.oDATA (oDATA), // .readdata
.iADDR (iADDR), // .address
.iWE_N (iWE_N), // .write_n
.iOE_N (iOE_N), // .read_n
.iCE_N (iCE_N), // .chipselect_n
.iBE_N (iBE_N), // .byteenable_n
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
module PushButton_Debouncer(
input clk,
input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= ~PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [15:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk)
if(PB_idle)
PB_cnt <= 0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int z = 0; z < t; z++) { int n; cin >> n; string s; cin >> s; bool found = false; for (int i = 0; i <= n - 11; i++) { if (s[i] == 8 ) { cout << YES << endl; found = true; break; } } if (found) { continue; } cout << NO << endl; } }
|
#include <bits/stdc++.h> using namespace std; int x; void dfsUtil(int node, int count, bool visited[], int& maxCount, vector<vector<int> >& adj) { visited[node] = true; count++; for (auto& i : adj[node]) { if (!visited[i]) { if (count >= maxCount) { maxCount = count; x = i; } dfsUtil(i, count, visited, maxCount, adj); } } } void dfs(int node, int n, vector<vector<int> >& adj, int& maxCount) { bool visited[n]; int count = 0; for (int i = 0; i < n; ++i) visited[i] = false; dfsUtil(node, 1, visited, maxCount, adj); } int diameter(vector<vector<int> >& adj, int n) { int maxCount = INT_MIN; dfs(0, n, adj, maxCount); dfs(x, n, adj, maxCount); return maxCount; } bool vis[100010]; int dist[100010]; void dfs1(int v, int p, vector<vector<int> >& adj) { if (vis[v]) return; vis[v] = true; if (p == -1) dist[v] = 0; else dist[v] = dist[p] + 1; for (auto& u : adj[v]) { dfs1(u, v, adj); } } void solve() { int n, a, b, da, db; cin >> n >> a >> b >> da >> db; a--; b--; vector<vector<int> > adj(n); for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; u--; v--; adj[u].push_back(v); adj[v].push_back(u); } if (db <= 2 * da) { cout << Alice << endl; return; } for (int i = 0; i < n; i++) { vis[i] = false; } dfs1(a, -1, adj); if (dist[b] <= da) { cout << Alice << endl; return; } if (diameter(adj, n) - 1 >= 2 * da + 1) { cout << Bob << endl; } else { cout << Alice << endl; } } int main() { ios::sync_with_stdio(0); cin.tie(0); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int t; cin >> t; while (t--) { solve(); } }
|
#include<bits/stdc++.h> #define ls i<<1 #define rs i<<1|1 #define fi first #define se second #define pb push_back #define mp make_pair using namespace std; typedef long long ll; typedef vector<int> vct; typedef pair<int,int> pii; const int N=2E5+1; const int inf=1<<30; ll read() { ll a=0; char b=1,c; do if((c=getchar())==45)b=-1;while(c<48||c>57); do a=(a<<3)+(a<<1)+(c&15);while((c=getchar())>47&&c<58); return a*b; } void write(ll x,char c) { if(x<0)putchar(45),x=-x; char a[20],s=0; do a[++s]=x%10|48;while(x/=10); do putchar(a[s]);while(--s); putchar(c); } const int p=1E9+7; int n,l,r; int fac[N],inv[N]; vct a,ans; int solve(int u,int v) { for(int i=0;i<n;++i) { int y=u-max(l+a[i]-1,0),z=v-max(n-r+a[i],0); if(y<0||z<0)ans[i]=0; else ans[i]=(fac[y+z]*1LL*inv[y]%p*inv[z]%p); } int res=0; for(int i=0;i<n;++i)res=(res+(ans[i]-ans[i+1]+p)*1LL*a[i])%p; return res; } int main() { fac[0]=fac[1]=inv[0]=inv[1]=1; for(int i=2;i<N;++i)inv[i]=(p-p/i)*1LL*inv[p%i]%p; for(int i=2;i<N;++i) { fac[i]=fac[i-1]*1LL*i%p; inv[i]=inv[i-1]*1LL*inv[i]%p; } for(int x=read();x--;) { n=read(),l=read(),r=read(); a.resize(n); ans.resize(n); ans.pb(0); iota(a.begin(),a.end(),min(1-l,r-n)); int m=n>>1; if(n&1)write((solve(m,n-m)+solve(n-m,m))%p, n ); else write(solve(m,m), n ); } }
|
`timescale 10ns/10ns
module alu_tb();
// Declare inputs as regs and outputs as wires
reg [15:0] x;
reg [15:0] y;
reg zx, nx, zy, ny, f, no;
wire [15:0] out;
wire zr, ng;
alu alu_DUT(
.x(x),
.y(y),
.zx(zx),
.nx(nx),
.zy(zy),
.ny(ny),
.f(f),
.no(no),
.out(out),
.zr(zr),
.ng(ng)
);
// Initialize all variables
initial begin
$monitor ("%b %b %b %b %b %b %b %b %b %b %b",
x, y, zx, nx, zy, ny, f, no, out, zr, ng);
$display("x, y, zx, nx, zy, ny, f, no, out, zr, ng");
x = 16'B0000000000000000;
y = 16'B1111111111111111;
// Compute 0
zx = 1;
nx = 0;
zy = 1;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute 1
zx = 1;
nx = 1;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute -1
zx = 1;
nx = 1;
zy = 1;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 0;
no = 0;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 0;
no = 0;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute !x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 0;
no = 1;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute !y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 0;
no = 1;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute -x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute -y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute x + 1
zx = 0;
nx = 1;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute y + 1
zx = 1;
nx = 1;
zy = 0;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute x - 1
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 1;
no = 0;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute y - 1
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b1111111111111110, 1'b0, 1'b1);
// Compute x + y
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute x - y
zx = 0;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute y - x
zx = 0;
nx = 0;
zy = 0;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute x & y
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 0;
no = 0;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute x | y
zx = 0;
nx = 1;
zy = 0;
ny = 1;
f = 0;
no = 1;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
x = 16'B000000000010001;
y = 16'B000000000000011;
// Compute 0
zx = 1;
nx = 0;
zy = 1;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b0000000000000000, 1'b1, 1'b0);
// Compute 1
zx = 1;
nx = 1;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute -1
zx = 1;
nx = 1;
zy = 1;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b1111111111111111, 1'b0, 1'b1);
// Compute x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 0;
no = 0;
#2 assert_alu(16'b0000000000010001, 1'b0, 1'b0);
// Compute y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 0;
no = 0;
#2 assert_alu(16'b0000000000000011, 1'b0, 1'b0);
// Compute !x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 0;
no = 1;
#2 assert_alu(16'b1111111111101110, 1'b0, 1'b1);
// Compute !y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 0;
no = 1;
#2 assert_alu(16'b1111111111111100, 1'b0, 1'b1);
// Compute -x
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b1111111111101111, 1'b0, 1'b1);
// Compute -y
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
#2 assert_alu(16'b1111111111111101, 1'b0, 1'b1);
// Compute x + 1
zx = 0;
nx = 1;
zy = 1;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000010010, 1'b0, 1'b0);
// Compute y + 1
zx = 1;
nx = 1;
zy = 0;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000000100, 1'b0, 1'b0);
// Compute x - 1
zx = 0;
nx = 0;
zy = 1;
ny = 1;
f = 1;
no = 0;
#2 assert_alu(16'b0000000000010000, 1'b0, 1'b0);
// Compute y - 1
zx = 1;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b0000000000000010, 1'b0, 1'b0);
// Compute x + y
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 1;
no = 0;
#2 assert_alu(16'b0000000000010100, 1'b0, 1'b0);
// Compute x - y
zx = 0;
nx = 1;
zy = 0;
ny = 0;
f = 1;
no = 1;
#2 assert_alu(16'b0000000000001110, 1'b0, 1'b0);
// Compute y - x
zx = 0;
nx = 0;
zy = 0;
ny = 1;
f = 1;
no = 1;
#2 assert_alu(16'b1111111111110010, 1'b0, 1'b1);
// Compute x & y
zx = 0;
nx = 0;
zy = 0;
ny = 0;
f = 0;
no = 0;
#2 assert_alu(16'b0000000000000001, 1'b0, 1'b0);
// Compute x | y
zx = 0;
nx = 1;
zy = 0;
ny = 1;
f = 0;
no = 1;
#2 assert_alu(16'b0000000000010011, 1'b0, 1'b0);
end
task assert_alu;
input [15:0] i_out;
input i_zr, i_ng;
begin
if (out != i_out
|| zr != i_zr
|| ng != i_ng) begin
$display ("%b %b %b : assert failed",
out, zr, ng);
$display ("%b %b %b <- should be this",
i_out, i_zr, i_ng);
end
end
endtask
task assert;
input [15:0] x, y;
begin
if(x != y)
$display( "%t ---------- assert failed %b != %b\n", $time, x, y );
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, temp, i, x = 0, arr[100] = {0}; map<long long, long long> inx; cin >> n; for (i = 0; i < n; i++) { cin >> temp; inx[temp] = i; } for (map<long long int, long long int>::iterator it = inx.begin(); it != inx.end(); ++it) { arr[it->second] = it->first; } cout << inx.size() << endl; for (i = 0; i < n; i++) { if (arr[i] != 0) cout << arr[i] << ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int a[maxn], b[maxn]; bool v[maxn]; int main() { int n; cin >> n; a[0] = -1; for (int i = 1; i <= n; ++i) { cin >> a[i]; v[a[i]] = 1; if (a[i] > a[i - 1]) b[i] = a[i - 1]; else b[i] = -1; } int c = 0; for (int i = 1; i <= n; ++i) { if (b[i] == -1) { while (v[c]) c++; b[i] = c++; } } for (int i = 1; i <= n; ++i) cout << b[i] << ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_FUNCTIONAL_V
|
//
// usb 3.0 data scrambling lfsr
//
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
module usb3_lfsr (
input wire clock,
input wire reset_n,
input wire [31:0] data_in,
input wire scram_en,
input wire scram_rst,
input wire [15:0] scram_init,
output reg [31:0] data_out,
output reg [31:0] data_out_reg
);
reg [15:0] lfsr_q, lfsr_c;
reg [31:0] data_c;
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10];
lfsr_c[1] = lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[11];
lfsr_c[2] = lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[12];
lfsr_c[3] = lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13];
lfsr_c[4] = lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14];
lfsr_c[5] = lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15];
lfsr_c[6] = lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ lfsr_q[14];
lfsr_c[7] = lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[15];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13];
lfsr_c[10] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14];
lfsr_c[11] = lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15];
lfsr_c[12] = lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14];
lfsr_c[13] = lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[14] = lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[15] = lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[15];
data_c[0] = data_in[0] ^ lfsr_q[15];
data_c[1] = data_in[1] ^ lfsr_q[14];
data_c[2] = data_in[2] ^ lfsr_q[13];
data_c[3] = data_in[3] ^ lfsr_q[12];
data_c[4] = data_in[4] ^ lfsr_q[11];
data_c[5] = data_in[5] ^ lfsr_q[10];
data_c[6] = data_in[6] ^ lfsr_q[9];
data_c[7] = data_in[7] ^ lfsr_q[8];
data_c[8] = data_in[8] ^ lfsr_q[7];
data_c[9] = data_in[9] ^ lfsr_q[6];
data_c[10] = data_in[10] ^ lfsr_q[5];
data_c[11] = data_in[11] ^ lfsr_q[4] ^ lfsr_q[15];
data_c[12] = data_in[12] ^ lfsr_q[3] ^ lfsr_q[14] ^ lfsr_q[15];
data_c[13] = data_in[13] ^ lfsr_q[2] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15];
data_c[14] = data_in[14] ^ lfsr_q[1] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14];
data_c[15] = data_in[15] ^ lfsr_q[0] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13];
data_c[16] = data_in[16] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[15];
data_c[17] = data_in[17] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[14];
data_c[18] = data_in[18] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[13];
data_c[19] = data_in[19] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12];
data_c[20] = data_in[20] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11];
data_c[21] = data_in[21] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[10];
data_c[22] = data_in[22] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[9] ^ lfsr_q[15];
data_c[23] = data_in[23] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[14];
data_c[24] = data_in[24] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[7] ^ lfsr_q[13] ^ lfsr_q[15];
data_c[25] = data_in[25] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[12] ^ lfsr_q[14];
data_c[26] = data_in[26] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[5] ^ lfsr_q[11] ^ lfsr_q[13] ^ lfsr_q[15];
data_c[27] = data_in[27] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[14];
data_c[28] = data_in[28] ^ lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[13];
data_c[29] = data_in[29] ^ lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[12];
data_c[30] = data_in[30] ^ lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[11];
data_c[31] = data_in[31] ^ lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10];
//data_out = scram_en ? data_c : data_out;
data_out = data_c;
end
always @(posedge clock) begin
if(~reset_n) begin
lfsr_q <= scram_init;
data_out_reg <= 32'h0;
end else begin
lfsr_q <= scram_rst ? scram_init : scram_en ? lfsr_c : lfsr_q;
data_out_reg <= scram_en ? data_c : data_out_reg;
end
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
module test_table_lookup;
// Inputs
reg clk;
reg [31:0] state;
// Outputs
wire [31:0] p0;
wire [31:0] p1;
wire [31:0] p2;
wire [31:0] p3;
// Instantiate the Unit Under Test (UUT)
table_lookup uut (
.clk(clk),
.state(state),
.p0(p0),
.p1(p1),
.p2(p2),
.p3(p3)
);
initial begin
clk = 0;
state = 0;
#100;
state = 31'h193de3be;
#10;
if (p0 !== 32'hb3_d4_d4_67) begin $display("E"); $finish; end
if (p1 !== 32'h69_4e_27_27) begin $display("E"); $finish; end
if (p2 !== 32'h11_33_22_11) begin $display("E"); $finish; end
if (p3 !== 32'hae_ae_e9_47) begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; class Graph { long long int v; list<pair<long long int, long long int>> *adj; public: Graph(long long int v) : v(v) { adj = new list<pair<long long int, long long int>>[v]; } void addEdge(long long int u, long long int v, long long int w, bool bidir = true) { adj[u].push_back(make_pair(v, w)); if (bidir) adj[v].push_back(make_pair(u, w)); } void dijkstra() { vector<long long int> distance(v, LONG_MAX); priority_queue<pair<long long int, long long int>, vector<pair<long long int, long long int>>, greater<pair<long long int, long long int>>> pq; pq.push(make_pair(0, 0)); distance[0] = 0; while (!pq.empty()) { auto ele = pq.top(); pq.pop(); for (auto itr = adj[ele.second].begin(); itr != adj[ele.second].end(); itr++) { long long int v = itr->first; long long int weight = itr->second; if (distance[ele.second] != LONG_MAX && distance[ele.second] + weight < distance[v]) { distance[v] = distance[ele.second] + weight; pq.push(make_pair(distance[v], v)); } } } for (auto ele : distance) cout << ele << ; } }; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long int n; cin >> n; vector<long long int> v(n); for (long long int i = 0; i < n; i++) cin >> v[i]; Graph g(n); for (long long int i = 0; i < n - 1; i++) g.addEdge(i, i + 1, 1); for (long long int i = 0; i < n; i++) if (i != v[i] - 1) g.addEdge(i, v[i] - 1, 1, false); g.dijkstra(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e3 + 5; char g1[N][N]; int dp1[N][N]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); int n = 0, m = 0, ans1 = 0; cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> g1[i]; for (int i = 1; i <= n; ++i) { for (int j = 0; j < m; ++j) { dp1[i][j] = 1; if (i > 2 && j > 0 && j < m - 1 && g1[i][j] == g1[i - 1][j] && g1[i][j] == g1[i - 2][j] && g1[i][j] == g1[i - 1][j - 1] && g1[i][j] == g1[i - 1][j + 1]) { dp1[i][j] += min(min(dp1[i - 1][j - 1], dp1[i - 1][j + 1]), dp1[i - 2][j]); } ans1 += dp1[i][j]; } } cout << ans1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(NULL); ios::sync_with_stdio(false); long long int n, m, i, j, k, ans = 0; cin >> n >> m; long long int A[n], B[m]; string str(500, 0 ); for (i = 0; i < n; i++) cin >> A[i]; for (i = 0; i < m; i++) { cin >> k; k--; B[i] = k; } for (i = 0; i < m; i++) { j = i - 1; str = string(500, 0 ); while (j >= 0 && B[j] != B[i]) { if (str[B[j]] != 1 ) { ans += A[B[j]]; str[B[j]] = 1 ; } j--; } } cout << ans << endl; return 0; }
|
`timescale 1ns/1ns
module Score_tb();
reg RESET;
reg [11:0] SCORE;
wire [6:0] DISP_SU;
wire [6:0] DISP_SD;
wire [6:0] DISP_SC;
wire [6:0] DISP_SM;
Score sc_tb(
.RESET(RESET),
.SCORE(SCORE),
.DISP_SU(DISP_SU),
.DISP_SD(DISP_SD),
.DISP_SC(DISP_SC),
.DISP_SM(DISP_SM)
);
initial begin
RESET=0;
SCORE=0;
$display("==================================//\\\\==================================");
$display("| Testbench Modulo Score |");
$display("==================================\\\\//==================================");
$display("\tTEMPO: %0t // SCORE = 0\n", $time);
#5 RESET=1;
#10 RESET=0;
$display("\tTEMPO: %0t // RESET foi ativado por 10ns\n", $time);
#5 SCORE=9;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=56;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=703;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=2590;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10 SCORE=4095;
#1 $display("\tTEMPO: %0t // SCORE alterado para %d\n\t\tDISP_SM = %b,\n\t\tDISP_SC = %b,\n\t\tDISP_SD = %b,\n\t\tDISP_SU = %b\n", $time, SCORE, DISP_SM, DISP_SC, DISP_SD, DISP_SU);
#10
$display("==================================//\\\\==================================");
$display("| Fim do Testbench |");
$display("==================================\\\\//==================================");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<int> start(m); vector<int> ending(m); vector<int> time(m); vector<int> prize(m); int money = 0; for (int i = 0; i < m; i++) { cin >> start[i] >> ending[i] >> time[i] >> prize[i]; } int mn = 9000; int currprize; for (int j = 1; j <= n; j++) { mn = 9000; currprize = 0; for (int i = 0; i < m; i++) { if (start[i] <= j && ending[i] >= j && time[i] < mn) { mn = time[i]; currprize = prize[i]; } } money += currprize; } cout << money << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_BEHAVIORAL_PP_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream Ethernet FCS Generator
*/
module axis_eth_fcs #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* FCS output
*/
output wire [31:0] output_fcs,
output wire output_fcs_valid
);
// bus width assertions
initial begin
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
$finish;
end
end
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] fcs_reg = 32'h00000000;
reg fcs_valid_reg = 1'b0;
wire [31:0] crc_next[KEEP_WIDTH-1:0];
assign s_axis_tready = 1;
assign output_fcs = fcs_reg;
assign output_fcs_valid = fcs_valid_reg;
generate
genvar n;
for (n = 0; n < KEEP_WIDTH; n = n + 1) begin : crc
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH/KEEP_WIDTH*(n+1)),
.STYLE("AUTO")
)
eth_crc_inst (
.data_in(s_axis_tdata[DATA_WIDTH/KEEP_WIDTH*(n+1)-1:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next[n])
);
end
endgenerate
integer i;
always @(posedge clk) begin
fcs_valid_reg <= 1'b0;
if (s_axis_tvalid) begin
crc_state <= crc_next[KEEP_WIDTH-1];
if (s_axis_tlast) begin
crc_state <= 32'hFFFFFFFF;
if (KEEP_ENABLE) begin
fcs_reg <= ~crc_next[0];
for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
if (s_axis_tkeep[i]) begin
fcs_reg <= ~crc_next[i];
end
end
end else begin
fcs_reg <= ~crc_next[KEEP_WIDTH-1];
end
fcs_valid_reg <= 1'b1;
end
end
if (rst) begin
crc_state <= 32'hFFFFFFFF;
fcs_valid_reg <= 1'b0;
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:16 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zynq_design_1_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 50; char str[maxn]; int pre[30], now[30]; int l, r, len, cnt; void sov() { scanf( %s , str); len = strlen(str); cnt = 1; l = 0, r = 0; memset(now, 0, sizeof(now)); int i = 1; while (i < len) { if (str[i] == str[i - 1]) cnt++; else break; i++; } if (cnt == len) return; l = cnt; cnt = 1; int j = len - 2; while (j >= 0) { if (str[j] == str[j + 1]) cnt++; else break; j--; } r = cnt; if (cnt + l == len) return; cnt = 1; for (++i; i <= j + 1; i++) { if (str[i] != str[i - 1]) { now[str[i - 1] - a ] = max(now[str[i - 1] - a ], cnt); cnt = 1; } else if (str[i] == str[i - 1]) cnt++; } } int main() { int n; scanf( %d , &n); for (int j = 0; j < n; j++) { if (j == 3) int ok = 1; sov(); if (cnt == len) { int t = str[0] - a ; pre[t] = pre[t] + (pre[t] + 1) * len; for (int i = 0; i < 26; i++) if (i != t) { if (pre[i]) pre[i] = 1; else pre[i] = 0; } } else if (str[0] == str[len - 1]) { int t = str[0] - a ; if (pre[t]) pre[t] = max(now[t], l + r + 1); else pre[t] = max(max(l, r), now[t]); for (int i = 0; i < 26; i++) if (i != t) { if (pre[i]) pre[i] = max(1, now[i]); else pre[i] = now[i]; } } else { int t = str[0] - a ; if (pre[t]) pre[t] = max(1 + l, now[t]); else pre[t] = max(l, now[t]); t = str[len - 1] - a ; if (pre[t]) pre[t] = max(1 + r, now[t]); else pre[t] = max(r, now[t]); for (int i = 0; i < 26; i++) if (i != str[0] - a && i != str[len - 1] - a ) { if (pre[i]) pre[i] = max(1, now[i]); else pre[i] = now[i]; } } } int anss = -1; for (int i = 0; i < 26; i++) anss = max(anss, pre[i]); printf( %d n , anss); return 0; }
|
`timescale 1ns / 1ps
//Test comparador de 32 bits con signo
module TestComparador;
reg [31:0] a;
reg [31:0] b;
wire lt;
wire gt;
wire eq;
Comparador uut(
.a(a),
.b(b),
.lt(lt),
.gt(gt),
.eq(eq)
);
initial begin
a = 32'b0;
b = 32'b0;
#100;
a = 32'h0; b = 32'h0; //a = 0, b = 0
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h0; b = 32'h80000000; //a = 0, b = -0
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h80000000; b = 32'h0; //a = -0, b = 0
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h400; b = 32'h400; //a = 1, b = 1
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h400; b = 32'h80000400; //a = 1, b = -1
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h80000400; b = 32'h80000400; //a = -1, b = -1
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h200; b = 32'h0; //a = .1, b = 0
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h508; b = 32'h989680; //a = 1., b = 10011000100101.101
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'hA8D99763; b = 32'hDE6D23E4; //a = -10100011011001100101., b = -101111001101101001000.11111001
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h28D99763; b = 32'h5E6D23E4; //a = 10100011011001100101., b = 101111001101101001000.11111001
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'hB2EF5901; b = 32'h35905D0E; //a = -11001011101111010110., b = 11010110010000010111.010000111
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h14C7DBC7; b = 32'h8DFAE342; //a = 1010011000111110110., b = -110111111010111000.110100001
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
a = 32'h94C7DBC7; b = 32'hDFAE342; //a = -1010011000111110110., b = 110111111010111000.110100001
#50;
$display("a = %b %0b.%b, b = %b %0b.%b, lt = %b, gt = %b, eq = %b", a[31], a[30:10], a[9:0], b[31], b[30:10], b[9:0], lt, gt, eq);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_SYMBOL_V
`define SKY130_FD_SC_LP__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_SYMBOL_V
|
`include "../src/fifo/fifo_fwft.v"
module fifo_fwft_tb # (
parameter depth_width = 4
);
localparam dw = 16;
reg clk = 1'b1;
reg rst = 1'b1;
always #10 clk <= ~clk;
initial #100 rst <= 0;
reg [dw-1:0] wr_data;
wire wr_en;
wire [dw-1:0] rd_data;
wire rd_en;
wire full;
wire empty;
fifo_fwft # (
.DEPTH_WIDTH (depth_width),
.DATA_WIDTH (dw)
) dut (
.clk (clk),
.rst (rst),
.din (wr_data),
.wr_en (wr_en & !full),
.full (full),
.dout (rd_data),
.rd_en (rd_en),
.empty (empty)
);
reg random_write;
always @ (posedge clk) begin
if (rst)
random_write <= 0;
else
random_write <= ({$random} % 2 == 0);
end
assign wr_en = random_write && ~full;
always @ (posedge clk) begin
if (rst)
wr_data <= 0;
else if (wr_en)
wr_data <= wr_data + 1;
end
reg random_read;
always @ (posedge clk) begin
if (rst)
random_read <= 0;
else
random_read <= ({$random} % 4 == 0);
end
assign rd_en = ~rst && ~empty && random_read;
endmodule
|
`default_nettype none
`include "processor.h"
module interrupt_control(
//System
input wire iCLOCK,
input wire inRESET,
//Interrupt Configlation Table
input wire iICT_VALID,
input wire [5:0] iICT_ENTRY,
input wire iICT_CONF_MASK,
input wire iICT_CONF_VALID,
input wire [1:0] iICT_CONF_LEVEL,
//Core Info
input wire [31:0] iSYSREGINFO_PSR,
//External
input wire iEXT_ACTIVE,
input wire [5:0] iEXT_NUM,
output wire oEXT_ACK,
//output oEXT_BUSY,
//Core-ALU
input wire iFAULT_ACTIVE,
input wire [6:0] iFAULT_NUM,
input wire [31:0] iFAULT_FI0R,
input wire [31:0] iFAULT_FI1R,
///To Exception Manager
input wire iEXCEPTION_LOCK,
output wire oEXCEPTION_ACTIVE,
output wire [6:0] oEXCEPTION_IRQ_NUM,
output wire [31:0] oEXCEPTION_IRQ_FI0R,
output wire [31:0] oEXCEPTION_IRQ_FI1R,
input wire iEXCEPTION_IRQ_ACK
);
localparam STT_IDLE = 2'h0;
localparam STT_COMP_WAIT = 2'h1;
/****************************************************
Register and Wire
***************************************************/
//Interrupt Valid
wire software_interrupt_valid;
wire hardware_interrupt_valid;
//Interrupt Config Table
reg ict_conf_mask[0:63];
reg ict_conf_valid[0:63];
reg [1:0] ict_conf_level[0:63];
//Instruction State
reg [1:0] b_state;
reg [6:0] b_irq_num;
reg b_irq_type;
reg b_irq_ack;
reg [31:0] b_irq_fi0r;
reg [31:0] b_irq_fi1r;
//Generate
integer i;
/****************************************************
Instruction Config Table
***************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_valid [i] = 1'b0;
end
if(`PROCESSOR_DATA_RESET_EN)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_mask [i] = 1'b0;
ict_conf_level [i] = 2'h0;
end
end
end
else begin
if(iICT_VALID)begin
ict_conf_mask [iICT_ENTRY] <= iICT_CONF_MASK;
ict_conf_valid [iICT_ENTRY] <= iICT_CONF_VALID;
ict_conf_level [iICT_ENTRY] <= iICT_CONF_LEVEL;
end
end
end
assign software_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iFAULT_ACTIVE;
assign hardware_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM]));
//Hardware Irq Latch
reg b_hw_irq_valid;
reg [6:0] b_hw_irq_num;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_hw_irq_valid <= 1'b0;
b_hw_irq_num <= 7'h0;
end
else begin
if(!b_hw_irq_valid)begin
if(iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM])))begin
b_hw_irq_valid <= 1'b1;
b_hw_irq_num <= {1'b0, iEXT_NUM};
end
end
else begin
if(!software_interrupt_valid && b_state == STT_IDLE && !iEXCEPTION_LOCK)begin
b_hw_irq_valid <= 1'b0;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= STT_IDLE;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b1;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b1;
b_irq_ack <= 1'b1;
end
end
STT_COMP_WAIT :
begin
b_irq_ack <= 1'b0;
if(iEXCEPTION_IRQ_ACK)begin
b_state <= STT_IDLE;
end
end
default :
begin
b_state <= STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_num <= {7{1'b0}};
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_irq_num <= iFAULT_NUM;
b_irq_fi0r <= iFAULT_FI0R;
b_irq_fi1r <= iFAULT_FI1R;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_irq_num <= b_hw_irq_num;
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
end
default :
begin
b_irq_num <= b_irq_num;
b_irq_fi0r <= b_irq_fi0r;
b_irq_fi1r <= b_irq_fi1r;
end
endcase
end
end
assign oEXT_ACK = b_irq_ack && b_irq_type;//(b_state == `STT_COMP_WAIT && !software_interrupt_valid)? hardware_interrupt_valid : 1'b0;
assign oEXCEPTION_ACTIVE = (b_state == STT_COMP_WAIT)? !iEXCEPTION_IRQ_ACK : software_interrupt_valid || hardware_interrupt_valid || b_hw_irq_valid;//(b_state == `STT_COMP_WAIT)? !iFREE_IRQ_SETCONDITION : software_interrupt_valid || hardware_interrupt_valid;
assign oEXCEPTION_IRQ_NUM = (b_state == STT_COMP_WAIT)? b_irq_num : ((software_interrupt_valid)? iFAULT_NUM : {1'b0, iEXT_NUM});
assign oEXCEPTION_IRQ_FI0R = b_irq_fi0r;
assign oEXCEPTION_IRQ_FI1R = b_irq_fi1r;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; string q; string d; int b; void f(string s, int p) { char a = 0; int c = 0; if (s.size() <= p) return; for (int i = p; i < s.size(); i++) { if (s[i] > a) { a = s[i]; b = i; c = 1; } else if (s[i] == a) { b = i; c++; } } for (int i = 0; i < c; i++) cout << a; f(s, b + 1); } int main() { cin >> q; f(q, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } const string dom[2][7] = {{ ......... , ....O.... , O.......O , O...O...O , O.O...O.O , O.O.O.O.O , OOO...OOO }, { ......... , ....O.... , ..O...O.. , ..O.O.O.. , O.O...O.O , O.O.O.O.O , O.OO.OO.O }}; const int mod = 1000000007; int n; int m; char w[1002][1002]; int g[250][250]; int can[250], can2[250]; int cnt[251], res[251]; int get(int i, int j) { string s = ; for (int p = 0; p < 3; p++) for (int q = 0; q < 3; q++) s += w[i + p][j + q]; int res = 0; for (int p = 0; p < 2; p++) for (int q = 0; q < 7; q++) if (s == dom[p][q]) res |= (p + 1); return res; } int main() { scanf( %d%d , &n, &m); gets(w[0]); for (int i = 0; i < 4 * n + 1; i++) gets(w[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) g[i][j] = get(4 * i + 1, 4 * j + 1); for (int j = 0; j < m; j++) { can[j] = int(n % 2 == 0); for (int i = 0; i < n; i++) can[j] &= int((g[i][j] & 2) != 0); } for (int j = 0; j + 1 < m; j++) { memset(cnt, 0, sizeof(cnt)); cnt[0] = 1; for (int i = 0; i < n; i++) { if (g[i][j] & g[i][j + 1] & 1) cnt[i + 1] = (cnt[i + 1] + cnt[i]) % mod; if (i + 1 < n && int(g[i][j] & g[i + 1][j] & g[i][j + 1] & g[i + 1][j + 1] & 2)) cnt[i + 2] = (cnt[i + 2] + cnt[i]) % mod; } can2[j] = (cnt[n] - can[j] * can[j + 1] + mod) % mod; } memset(res, 0, sizeof(res)); res[0] = 1; for (int j = 0; j < m; j++) { if (can[j]) res[j + 1] = (res[j + 1] + res[j]) % mod; if (j + 1 < m) res[j + 2] = (res[j + 2] + (long long)res[j] * can2[j]) % mod; } printf( %d n , res[m]); return 0; }
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// Copyright (C) 2017-2020 The Project X-Ray Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC
`default_nettype none
`timescale 1ns / 1ps
`include "../src/error_counter.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 150)
$finish;
// ============================================================================
//re i_stb = (cycle_cnt == 10);
//re [32*2-1:0] i_dat = 64'h01234567_ABCD4321;
wire o_stb;
wire [4*8-1:0] o_dat;
error_counter #
(
.COUNT_WIDTH (8),
.DELAY_TAPS (4)
)
dut
(
.CLK (CLK),
.RST (RST),
.O_STB (o_stb),
.O_DAT (o_dat)
);
always @(posedge CLK)
if (o_stb)
$display("%X", o_dat);
endmodule
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//
// calculate_countid module
//
// bv2.0_programmable
//
// Created by LiJunnan on 16/9/23.
// Copyright (c) 2016year LiJunnan. All rights reserved.
//
`timescale 1ns/1ps
module calculate_countid(
clk,
reset,
bv_in_valid,
bv_in,
countid_valid,
countid
);
parameter width_bv_and = 64;
parameter width_count = 6;
input clk;
input reset;
input bv_in_valid;
input [width_bv_and-1:0] bv_in;
output wire countid_valid;
output wire [width_count-1:0] countid;
wire [width_count-1:0] count_out[0:width_count];
wire [width_count-1:0] count[0:width_count];
wire bv_valid[0:width_count];
wire [width_bv_and-1:0] bv[0:width_count];
wire bv_out_valid[0:width_count];
wire [width_bv_and-1:0] bv_out[0:width_count];
assign count[width_count] = {width_count{1'b0}};
assign bv_valid[width_count] = bv_in_valid;
assign bv[width_count] = bv_in;
generate
genvar i;
for(i=2; i<= width_count; i=i+1) begin : bv_count
bv_count bv_c
(
.reset(reset),
.clk(clk),
.bv_valid(bv_valid[i]),
.bv(bv[i]),
.count(count[i]),
.bv_out_valid(bv_valid[i-1]),
.bv_out(bv[i-1]),
.count_out(count[i-1])
);
defparam
/*
bv_count[i].bv_c.width = width_bv_and,
bv_count[i].bv_c.width_count= width_count,
bv_count[i].bv_c.stage = i,
bv_count[i].bv_c.range_end = 1<<(i-1);
*/
bv_c.width = width_bv_and,
bv_c.width_count= width_count,
bv_c.stage = i,
bv_c.range_end = 1<<(i-1);
end
endgenerate
bv_count bv_count_1(
.reset(reset),
.clk(clk),
.bv_valid(bv_valid[1]),
.bv(bv[1]),
.count(count[1]),
.bv_out_valid(countid_valid),
.bv_out(bv[0]),
.count_out(countid)
);
endmodule
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_BLACKBOX_V
`define SKY130_FD_SC_LS__AND2B_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const double Pi = 3.1415926535897932; const int dir[4][2] = {-1, 0, 0, -1, 1, 0, 0, 1}; const int maxn = 1e4 + 5; struct EDGE { int a, b; int A, B; } edge[maxn]; int n, m; int last[maxn]; vector<int> G[maxn], tree[maxn]; int d[maxn]; int A[maxn], B[maxn]; bool vis[maxn]; vector<int> ans; int in[maxn]; void dfs_tree(int a, int fa) { vis[a] = true; for (int i = 0; i < G[a].size(); i++) { int p = G[a][i]; if (p == last[a]) continue; int b = edge[p].a ^ edge[p].b ^ a; if (!vis[b]) { tree[a].push_back(p); in[p] = true; d[b] = d[a] + 1; last[b] = p; dfs_tree(b, a); } else if (d[a] > d[b]) { if (d[a] - d[b] + 1 & 1) { ans.push_back(p); B[a]++; B[b]--; } else { A[a]++; A[b]--; } } } } void dfs(int a) { vis[a] = true; for (int i = 0; i < tree[a].size(); i++) { int p = tree[a][i]; int b = edge[p].a ^ edge[p].b ^ a; if (!vis[b]) dfs(b); A[a] += A[b]; B[a] += B[b]; } edge[last[a]].A = A[a]; edge[last[a]].B = B[a]; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); edge[i] = EDGE{a, b}; G[a].push_back(i); G[b].push_back(i); } for (int i = 1; i <= n; i++) { if (!vis[i]) dfs_tree(i, -1); } memset(vis, false, sizeof(vis)); for (int i = 1; i <= n; i++) { if (!vis[i]) dfs(i); } if (ans.size() == 0) { for (int i = 1; i <= m; i++) ans.push_back(i); } else if (ans.size() == 1) { for (int i = 1; i <= m; i++) if (in[i]) { if (edge[i].A == 0 && edge[i].B) ans.push_back(i); } } else { int t = ans.size(); ans.clear(); for (int i = 1; i <= m; i++) if (in[i]) { if (edge[i].B) { if (edge[i].B == t && edge[i].A == 0) ans.push_back(i); } } } sort(ans.begin(), ans.end()); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]), putchar(i == ans.size() - 1 ? n : ); return 0; }
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#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > score; map<pair<int, int>, int> freq; bool compare(const pair<int, int> a, const pair<int, int> b) { if (a.first == b.first) return a.second < b.second; return a.first > b.first; } void solve() { int n, k; cin >> n >> k; for (int(i) = (0); (i) < (n); ++(i)) { int x, y; cin >> x >> y; pair<int, int> curr = make_pair(x, y); score.push_back(curr); ++freq[curr]; } sort((score).begin(), (score).end(), compare); cout << freq[score[k - 1]]; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); cout << n ; } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_V
|
module io1_sub (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [w-1:0] pin; // To/From MD31_pad of autoinst_lopaz_srpad.v
wire [2*w-1:0] pin_in; // From MD31_pad of autoinst_lopaz_srpad.v, ...
wire templated; // To/From MD31_pad of autoinst_lopaz_srpad.v
// End of automatics
autoinst_lopaz_srpad MD31_pad
(.*,
.foo (touch_this_not_my_pretty));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
); */
autoinst_lopaz_srpad MD31_pad
(.*);
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin (templated));
*/
autoinst_lopaz_srpad MD31_pad
(.*,
// Outputs
// Inouts
.pin (templated) // Templated
);
// And .name with auto inst
autoinst_lopaz_srpad MD31_pad22
(.pin,
.clk,
/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inputs
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
always @(posedge clk) begin
$display ("This .* shouldn't expand.\n");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int T; cin >> T; while (T--) { long long int x, y, z; cin >> x >> y >> z; long long int ans = 0; if (x == y || x == z || y == z) { if (x == y && z == y) { cout << YES << n << x << << x << << x << n ; ans = 1; } else if (x == z && y < x) { cout << YES << n << x << << y << << 1 << n ; ans = 1; } else if (y == z && x < y) { cout << YES << n << x << << 1 << << y << n ; ans = 1; } else if (x == y && z < x) { cout << YES << n << x << << z << << 1 << n ; ans = 1; } else if (ans == 0) cout << NO << n ; } else cout << NO << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, g[505][505], f[505][505], tot[505], ans[505][505]; int main() { scanf( %d%d , &n, &m); memset(g, 0x3f, sizeof(g)); memset(f, 0x3f, sizeof(f)); for (int i = 1; i <= n; i++) f[i][i] = 0; for (int i = 1; i <= m; i++) { int u, v, w; scanf( %d%d%d , &u, &v, &w); g[u][v] = g[v][u] = f[u][v] = f[v][u] = min(g[u][v], w); } for (int k = 1; k <= n; k++) for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = f[j][i] = min(f[i][j], f[i][k] + f[k][j]); for (int i = 1; i <= n; i++) { memset(tot, 0, sizeof(tot)); for (int j = 1; j <= n; j++) for (int k = 1; k <= n; k++) if (f[i][k] + g[k][j] == f[i][j]) tot[j]++; for (int j = 1; j <= n; j++) for (int k = 1; k <= n; k++) if (f[i][k] + f[k][j] == f[i][j]) ans[i][j] += tot[k]; } for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { if (i == j) continue; if (f[i][j] >= 0x3f3f3f3f - 100) ans[i][j] = 0; printf( %d , ans[i][j]); } printf( n ); }
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#include <bits/stdc++.h> using namespace std; template <typename T> T inverse(T a, T m) { T u = 0, v = 1; while (a != 0) { T t = m / a; m -= t * a; swap(a, m); u -= t * v; swap(u, v); } assert(m == 1); return u; } template <typename T> class Modular { public: using Type = typename decay<decltype(T::value)>::type; constexpr Modular() : value() {} template <typename U> Modular(const U& x) { value = normalize(x); } template <typename U> static Type normalize(const U& x) { Type v; if (-mod() <= x && x < mod()) v = static_cast<Type>(x); else v = static_cast<Type>(x % mod()); if (v < 0) v += mod(); return v; } const Type& operator()() const { return value; } template <typename U> explicit operator U() const { return static_cast<U>(value); } constexpr static Type mod() { return T::value; } Modular& operator+=(const Modular& other) { if ((value += other.value) >= mod()) value -= mod(); return *this; } Modular& operator-=(const Modular& other) { if ((value -= other.value) < 0) value += mod(); return *this; } template <typename U> Modular& operator+=(const U& other) { return *this += Modular(other); } template <typename U> Modular& operator-=(const U& other) { return *this -= Modular(other); } Modular& operator++() { return *this += 1; } Modular& operator--() { return *this -= 1; } Modular operator++(int) { Modular result(*this); *this += 1; return result; } Modular operator--(int) { Modular result(*this); *this -= 1; return result; } Modular operator-() const { return Modular(-value); } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(static_cast<int64_t>(value) * static_cast<int64_t>(rhs.value)); return *this; } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int64_t>::value, Modular>::type& operator*=(const Modular& rhs) { int64_t q = static_cast<int64_t>(static_cast<long double>(value) * rhs.value / mod()); value = normalize(value * rhs.value - q * mod()); return *this; } template <typename U = T> typename enable_if<!is_integral<typename Modular<U>::Type>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(value * rhs.value); return *this; } Modular& operator/=(const Modular& other) { return *this *= Modular(inverse(other.value, mod())); } template <typename U> friend bool operator==(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend bool operator<(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend std::istream& operator>>(std::istream& stream, Modular<U>& number); private: Type value; }; template <typename T> bool operator==(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value == rhs.value; } template <typename T, typename U> bool operator==(const Modular<T>& lhs, U rhs) { return lhs == Modular<T>(rhs); } template <typename T, typename U> bool operator==(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) == rhs; } template <typename T> bool operator!=(const Modular<T>& lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(const Modular<T>& lhs, U rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(U lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T> bool operator<(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value < rhs.value; } template <typename T> Modular<T> operator+(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T> Modular<T> operator-(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T> Modular<T> operator*(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T> Modular<T> operator/(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> powmod(const Modular<T>& a, const U& b) { assert(b >= 0); Modular<T> x = a, res = 1; U p = b; while (p > 0) { if (p & 1) res *= x; x *= x; p >>= 1; } return res; } template <typename T> string to_string(const Modular<T>& number) { return to_string(number()); } template <typename T> std::ostream& operator<<(std::ostream& stream, const Modular<T>& number) { return stream << number(); } template <typename T> std::istream& operator>>(std::istream& stream, Modular<T>& number) { typename common_type<typename Modular<T>::Type, int64_t>::type x; stream >> x; number.value = Modular<T>::normalize(x); return stream; } constexpr int md = 998244353; using Mint = Modular<std::integral_constant<decay<decltype(md)>::type, md>>; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); Mint m, n; cin >> n >> m; Mint res = 0, pre = 1; for (int i = 1; i <= (int)n + 1; i++) { Mint tmp = i / (n + m - i + 1); if (i > 1) pre *= (n - i + 2) / (n + m - i + 2); tmp *= pre; res += tmp; } res *= m; Mint h = 0; for (Mint i = 1; i != (n + 1); i++) h += 1 / i; h = h * m + 1; cout << res * h; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MAXN = 500; const long long INF = 1e9; const long long BITS = 64; const long double EPS = 1e-9; void bye() { cout << n ; exit(0); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long all = 0; vector<string> g(n); vector<int> pref(n); for (int i = 0; i < n; i++) { cin >> g[i]; all += (long long)(g[i]).size(); pref[i] = (i) ? pref[i - 1] + (long long)(g[i]).size() + 1 : (long long)(g[i]).size(); } all += n - 1; vector<vector<bool> > eq(n, vector<bool>(n)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { eq[i][j] = g[i] == g[j]; } } vector<vector<int> > dp(n, vector<int>(n)); for (int i = n - 1; i >= 0; i--) { for (int j = n - 1; j >= 0; j--) { if (eq[i][j]) { if (i + 1 < n && j + 1 < n) { dp[i][j] = dp[i + 1][j + 1] + 1; } else { dp[i][j] = 1; } } } } long long ans = all; for (int i = 0; i < n; i++) { for (int k = 0; i + k < n; k++) { long long now = (pref[i + k] - ((i) ? pref[i - 1] + 1 : 0)); long long cnt = 1; for (int j = i + k + 1; j + k < n; j++) { if (dp[i][j] > k) { cnt++; j += k; } } if (cnt > 1) { ans = min(ans, all + cnt * (k + 1) - now * cnt); } } } cout << ans; bye(); }
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#include <bits/stdc++.h> using namespace std; int main() { int i, j, len; char s[105]; cin >> s; len = strlen(s); for (i = 0; i < len; i++) { for (j = 0; j < len - i - 2; j += 2) { if (s[j] > s[j + 2]) { swap(s[j], s[j + 2]); } } } printf( %s , s); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/06/2017 08:43:21 AM
// Design Name:
// Module Name: MULTIPLEXER_2_TO_1
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MULTIPLEXER_2_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
1'b0:
begin
out_reg = IN1;
end
1'b1:
begin
out_reg = IN2;
end
endcase
end
assign OUT = out_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; int read(); int n; int a[200005], b[200005], c[200005], bk[200005]; int hd[200005], nx[400005], to[400005], cnt; void add(int f, int t) { nx[++cnt] = hd[f], hd[f] = cnt, to[cnt] = t; } int fa[200005], dep[200005]; void dfs1(int u) { for (int i = hd[u], v; i; i = nx[i]) if ((v = to[i]) != fa[u]) dep[v] = dep[fa[v] = u] + 1, dfs1(v); } bool check1() { for (int i = 1; i <= n; ++i) c[i] = b[i]; int u = a[1]; while (fa[u]) swap(c[u], c[fa[u]]), u = fa[u]; for (int i = 1; i <= n; ++i) if (c[i] != i) return 0; return 1; } vector<int> st[2]; int idcnt; void fail() { puts( -1 ), exit(0); } void get(int u, int id) { if (id >= 2 || (id == 1 && fa[st[0][0]] != fa[u])) fail(); st[id].push_back(u); while (1) { int v = 0; for (int i = hd[u]; i; i = nx[i]) if (to[i] != fa[u] && c[to[i]] != to[i]) v ? fail() : (v = to[i], void()); if (!v) break; st[id].push_back(u = v); } } void dfs2(int u) { for (int i = hd[u], v; i; i = nx[i]) if ((v = to[i]) != fa[u]) (c[v] != v) ? get(v, idcnt++) : dfs2(v); } int p[200005], q[200005], len; int M(int x) { return x >= len ? x - len : x; } int getdis(int u, int v) { int rt = 0; while (u != v) (dep[u] < dep[v]) ? swap(u, v) : void(), ++rt, u = fa[u]; return rt; } void work() { for (int i = 1; i <= n; ++i) q[i] = -1; for (int i = 0; i < st[0].size(); ++i) p[len] = c[st[0][i]], q[st[0][i]] = len, ++len; int ru = st[0].back(), rv = fa[st[0].front()], rw = rv; if (st[1].size()) { rv = st[1].back(); for (int i = st[1].size() - 1; i >= 0; --i) p[len] = c[st[1][i]], q[st[1][i]] = len, ++len; } if ((ru = bk[ru]) > (rv = bk[rv])) swap(ru, rv); long long dis = q[p[0]]; for (int i = 1; i < len; ++i) if (M(q[p[i]] - i + len) != dis) fail(); for (int i = 1; i <= n; ++i) if (c[i] != i && q[i] == -1) fail(); int t = a[1]; while (q[t] == -1 && t != 1) t = fa[t]; if (t == 1) { dis = min(dis, len - dis) * (len + 1); printf( %d %d %lld n , ru, rv, dis + getdis(a[1], rw) + dep[rw]); return; } dis = q[t] >= st[0].size() ? min((dis - 1) * (len + 1) + (q[t] + 1), 1ll * M(len - dis) * (len + 1) + (len - q[t])) : min(dis * (len + 1) + (q[t] + 1), (len - dis - 1) * (len + 1) + (len - q[t])); printf( %d %d %lld n , ru, rv, dis + dep[rw] + getdis(a[1], t)); } int main() { n = read(); for (int i = 1; i <= n; ++i) bk[a[i] = read() + 1] = i; for (int i = 1; i <= n; ++i) b[a[i]] = read() + 1; for (int i = 1, u, v; i < n; ++i) u = a[read()], v = a[read()], add(u, v), add(v, u); for (int i = 1; i <= n; ++i) a[b[i]] = i; dfs1(1); if (check1()) return printf( 0 %d n , dep[a[1]]), 0; dfs2(1), work(); return 0; } const int _SIZE = 1 << 22; char ibuf[_SIZE], *iS = ibuf, *iT = ibuf; int read() { int x = 0, f = 1; char c = (iS == iT ? iT = ((iS = ibuf) + fread(ibuf, 1, _SIZE, stdin)), (iS == iT ? EOF : *iS++) : *iS++); while (!isdigit(c)) f = (c == - ) ? -1 : f, c = (iS == iT ? iT = ((iS = ibuf) + fread(ibuf, 1, _SIZE, stdin)), (iS == iT ? EOF : *iS++) : *iS++); while (isdigit(c)) x = x * 10 + c - 0 , c = (iS == iT ? iT = ((iS = ibuf) + fread(ibuf, 1, _SIZE, stdin)), (iS == iT ? EOF : *iS++) : *iS++); return x * f; }
|
/*
File: emesh_split.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eMesh Splitter
########################################################################
This block takes one eMesh input (104-bit transactions) and
copies it to two outputs. The wait signals are taken only from the
first slave port.
This block will hopefully be removed once I figure out how to get
Vivado to allow multiple slaves on one interface!
*/
module emesh_split (/*AUTOARG*/
// Outputs
ems_rd_wait, ems_wr_wait, emm0_access, emm0_write, emm0_datamode,
emm0_ctrlmode, emm0_dstaddr, emm0_srcaddr, emm0_data, emm1_access,
emm1_write, emm1_datamode, emm1_ctrlmode, emm1_dstaddr,
emm1_srcaddr, emm1_data,
// Inputs
ems_access, ems_write, ems_datamode, ems_ctrlmode, ems_dstaddr,
ems_srcaddr, ems_data, emm0_rd_wait, emm0_wr_wait
);
// Slave port
input ems_access;
input ems_write;
input [1:0] ems_datamode;
input [3:0] ems_ctrlmode;
input [31:0] ems_dstaddr;
input [31:0] ems_srcaddr;
input [31:0] ems_data;
output ems_rd_wait;
output ems_wr_wait;
// Master port #0 (with wait inputs)
output emm0_access;
output emm0_write;
output [1:0] emm0_datamode;
output [3:0] emm0_ctrlmode;
output [31:0] emm0_dstaddr;
output [31:0] emm0_srcaddr;
output [31:0] emm0_data;
input emm0_rd_wait;
input emm0_wr_wait;
// Master port #1 (NO wait inputs)
output emm1_access;
output emm1_write;
output [1:0] emm1_datamode;
output [3:0] emm1_ctrlmode;
output [31:0] emm1_dstaddr;
output [31:0] emm1_srcaddr;
output [31:0] emm1_data;
//############
//# Duplicate all slave->master signals
//############
wire emm0_access = ems_access;
wire emm0_write = ems_write;
wire [1:0] emm0_datamode = ems_datamode;
wire [3:0] emm0_ctrlmode = ems_ctrlmode;
wire [31:0] emm0_dstaddr = ems_dstaddr;
wire [31:0] emm0_srcaddr = ems_srcaddr;
wire [31:0] emm0_data = ems_data;
// Master port #1 (NO wait inputs)
wire emm1_access = ems_access;
wire emm1_write = ems_write;
wire [1:0] emm1_datamode = ems_datamode;
wire [3:0] emm1_ctrlmode = ems_ctrlmode;
wire [31:0] emm1_dstaddr = ems_dstaddr;
wire [31:0] emm1_srcaddr = ems_srcaddr;
wire [31:0] emm1_data = ems_data;
//#############################
//# Wait signal passthroughs, port 0 only
//#############################
wire ems_rd_wait = emm0_rd_wait;
wire ems_wr_wait = emm0_wr_wait;
endmodule // emesh_split
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int x, long long int y) { if (y == 0) return x; return gcd(y, x % y); } long long exp(long long a, long long b) { if (b == 0) return 1; long long res = exp(a, b / 2); if (b % 2) return res * res * a; else return res * res; } int prime(long long x) { if (x % 2 == 0) return 0; else { for (int i = 3; i * i <= x; i += 2) { if (x % i == 0) return 0; } } return 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n, m, k; map<int, int> ma; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; cin >> m; int brr[m]; for (int i = 0; i < m; i++) cin >> brr[i]; for (int i = 0; i < n; i++) { for (int j = m - 1; j >= 0; j--) { if (brr[j] % arr[i] == 0) { k = brr[j] / arr[i]; if (ma.find(k) == ma.end()) ma.insert({k, 1}); else ma[k]++; } } } map<int, int>::iterator it; it = ma.end(); it--; cout << it->second << n ; return 0; }
|
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