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`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/06/2013 07:10:19 PM
// Design Name:
// Module Name: main_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main_sim();
reg clk = 0;
always begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#10; // Wait for 1 time unit
clk = 1; // Set clk to 1
#10; // Wait 1 time unit
end
wire clk_recv;
wire data;
wire cmd;
wire reset;
main tb(.clk_in(clk), .sclk(clk_recv), .sdata(data), .scmd(cmd), .reset(reset));
reg [7 : 0] data_recv = 0;
reg [2 : 0] data_cnt = 7;
always @ (posedge clk_recv) begin
data_recv[data_cnt] = data;
data_cnt = data_cnt - 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 330, INF = 1000010000; int n, m, u, x, y, z, I, ans; int r[N], l[N], X[N], W[N], a[N], b[N], f[N], g[N][N], h[N][N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d , &X[i], &W[i]); b[++m] = X[i], b[++m] = X[i] + W[i]; b[++m] = X[i] - W[i]; } sort(b + 1, b + m + 1); m = unique(b + 1, b + m + 1) - b - 1; for (int i = 1; i <= n; i++) { r[i] = lower_bound(b + 1, b + m + 1, X[i] + W[i]) - b; l[i] = lower_bound(b + 1, b + m + 1, X[i] - W[i]) - b; a[X[i] = lower_bound(b + 1, b + m + 1, X[i]) - b] = i; } for (int i = 1; i <= m; i++) { int L = i; for (int j = i; j <= m; j++) { h[i][j] = L; g[i][j] = L == i ? i : g[L][j]; if (a[j]) L = min(L, l[a[j]]); } } for (int i = 1; i <= m; i++) { f[i] = f[i - 1]; for (int j = 1; j <= i - 1; j++) if (r[a[j]] >= i) { if (j < i - 1 && h[j + 1][i] < j) { int x = g[h[j + 1][i]][j]; f[i] = (f[i] > (f[x] + b[i] - b[x]) ? f[i] : (f[x] + b[i] - b[x])); } else f[i] = (f[i] > (f[j] + b[i] - b[j]) ? f[i] : (f[j] + b[i] - b[j])); } if (u = a[i - 1]) f[i] = (f[i] > (f[g[l[u]][i]] + b[i - 1] - b[g[l[u]][i]]) ? f[i] : (f[g[l[u]][i]] + b[i - 1] - b[g[l[u]][i]])); } cout << f[m] << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x, y; cin >> n >> m >> x >> y; int vis[105][105]; int i, j; for (i = 0; i < 105; i++) for (j = 0; j < 105; j++) vis[i][j] = 0; vis[x][y] = 1; cout << x << << y << endl; cout << x << << m << endl; for (i = x - 1; i >= 1; i--) cout << i << << m << endl; for (i = x + 1; i <= n; i++) cout << i << << m << endl; int flag = 1; for (i = m - 1; i >= 1; i--) { if (flag) { for (j = n; j >= 1; j--) { if (vis[j][i] == 0) { cout << j << << i << endl; vis[j][i] = 1; } } flag = !flag; } else { for (j = 1; j <= n; j++) { if (vis[j][i] == 0) { cout << j << << i << endl; vis[j][i] = 1; } } flag = !flag; } } }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_ms__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ms__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX4_BEHAVIORAL_PP_V
|
module adio_codec (
output oAUD_DATA,
output oAUD_LRCK,
output reg oAUD_BCK,
input key1_on,
input [1:0] iSrc_Select,
input iCLK_18_4,
input iRST_N,
input [15:0] sound1
);
parameter REF_CLK = 18432000; // 18.432 MHz
parameter SAMPLE_RATE = 48000; // 48 KHz
parameter DATA_WIDTH = 16; // 16 Bits
parameter CHANNEL_NUM = 2; // Dual Channel
parameter SIN_SAMPLE_DATA = 48;
//////////// Input Source Number //////////////
parameter SIN_SANPLE = 0;
//////////////////////////////////////////////////
// Internal Registers and Wires
reg [3:0] BCK_DIV;
reg [8:0] LRCK_1X_DIV;
reg [7:0] LRCK_2X_DIV;
reg [6:0] LRCK_4X_DIV;
reg [3:0] SEL_Cont;
//////// DATA Counter ////////
reg [5:0] SIN_Cont;
////////////////////////////////////
reg LRCK_1X;
reg LRCK_2X;
reg LRCK_4X;
//////////// AUD_BCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
BCK_DIV <= 0;
oAUD_BCK <= 0;
end
else
begin
if(BCK_DIV >= REF_CLK/(SAMPLE_RATE*DATA_WIDTH*CHANNEL_NUM*2)-1 )
begin
BCK_DIV <= 0;
oAUD_BCK <= ~oAUD_BCK;
end
else
BCK_DIV <= BCK_DIV+1;
end
end
//////////////////////////////////////////////////
//////////// AUD_LRCK Generator //////////////
always@(posedge iCLK_18_4 or negedge iRST_N)
begin
if(!iRST_N)
begin
LRCK_1X_DIV <= 0;
LRCK_2X_DIV <= 0;
LRCK_4X_DIV <= 0;
LRCK_1X <= 0;
LRCK_2X <= 0;
LRCK_4X <= 0;
end
else
begin
// LRCK 1X
if(LRCK_1X_DIV >= REF_CLK/(SAMPLE_RATE*2)-1 )
begin
LRCK_1X_DIV <= 0;
LRCK_1X <= ~LRCK_1X;
end
else
LRCK_1X_DIV <= LRCK_1X_DIV+1;
// LRCK 2X
if(LRCK_2X_DIV >= REF_CLK/(SAMPLE_RATE*4)-1 )
begin
LRCK_2X_DIV <= 0;
LRCK_2X <= ~LRCK_2X;
end
else
LRCK_2X_DIV <= LRCK_2X_DIV+1;
// LRCK 4X
if(LRCK_4X_DIV >= REF_CLK/(SAMPLE_RATE*8)-1 )
begin
LRCK_4X_DIV <= 0;
LRCK_4X <= ~LRCK_4X;
end
else
LRCK_4X_DIV <= LRCK_4X_DIV+1;
end
end
assign oAUD_LRCK = LRCK_1X;
//////////////////////////////////////////////////
////////// Sin LUT ADDR Generator //////////////
always@(negedge LRCK_1X or negedge iRST_N)
begin
if(!iRST_N)
SIN_Cont <= 0;
else
begin
if(SIN_Cont < SIN_SAMPLE_DATA-1 )
SIN_Cont <= SIN_Cont+1;
else
SIN_Cont <= 0;
end
end
///////////////////Wave-Source generate////////////////
////////////Timbre selection & SoundOut///////////////
wire [15:0]music1_ramp;
wire [15:0]music1=music1_ramp;
wire [15:0]sound_o;
assign sound_o=music1;
always@(negedge oAUD_BCK or negedge iRST_N)begin
if(!iRST_N)
SEL_Cont <= 0;
else
SEL_Cont <= SEL_Cont+1;
end
assign oAUD_DATA = ((key1_on) && (iSrc_Select==SIN_SANPLE)) ? sound_o[~SEL_Cont] :0;
//////////Ramp address generater//////////////
reg [15:0]ramp1;
wire [15:0]ramp_max=60000;
//////CH1 Ramp//////
always@(negedge key1_on or negedge LRCK_1X)begin
if (!key1_on)
ramp1=0;
else if (ramp1>ramp_max) ramp1=0;
else ramp1=ramp1+sound1;
end
////////////Ramp address assign//////////////
wire [5:0] ramp1_ramp=ramp1[15:10];
////////String-wave Timbre///////
wave_gen_string r1(
.ramp(ramp1_ramp),
.music_o(music1_ramp)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 505; const int MAXQ = 5000005; int n, m, X1[MAXQ], X2[MAXQ], Y1[MAXQ], Y2[MAXQ]; bool ans[MAXQ]; bitset<MAXN> dp1[MAXN][MAXN], dp2[MAXN][MAXN], temp; char board[MAXN][MAXN]; void dnc(int r1, int r2, vector<int> &que) { if (que.empty() || r1 > r2) return; int mid = (r1 + r2) / 2; for (int i = r1; i <= r2; ++i) { for (int j = 1; j <= m; ++j) { dp1[i][j].reset(); dp2[i][j].reset(); } } for (int i = mid; i >= r1; --i) { for (int j = m; j >= 1; --j) { if (board[i][j] == # ) continue; if (i == mid) dp1[i][j].set(j); else dp1[i][j] |= dp1[i + 1][j]; if (j < m) dp1[i][j] |= dp1[i][j + 1]; } } for (int i = mid; i <= r2; ++i) { for (int j = 1; j <= m; ++j) { if (board[i][j] == # ) continue; if (i == mid) dp2[i][j].set(j); else dp2[i][j] |= dp2[i - 1][j]; if (j > 1) dp2[i][j] |= dp2[i][j - 1]; } } vector<int> q1, q2; for (int i = 0; i < que.size(); ++i) { int pos = que[i]; if (X1[pos] <= mid && X2[pos] >= mid) { temp = (dp1[X1[pos]][Y1[pos]] & dp2[X2[pos]][Y2[pos]]); ans[pos] = temp.any(); } else if (X2[pos] < mid) q1.push_back(pos); else q2.push_back(pos); } dnc(r1, mid - 1, q1); dnc(mid + 1, r2, q2); } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %s , board[i] + 1); int q; vector<int> que; scanf( %d , &q); for (int i = 0; i < q; ++i) { scanf( %d %d %d %d , &X1[i], &Y1[i], &X2[i], &Y2[i]); que.push_back(i); } dnc(1, n, que); for (int i = 0; i < q; ++i) { if (ans[i]) printf( Yes n ); else printf( No n ); } return 0; }
|
module mandlebrot(
input clk,
input [WIDTH - 1 : 0] re_i,
input [WIDTH - 1 : 0] im_i,
input [WIDTH - 1 : 0] re_c,
input [WIDTH - 1 : 0] im_c,
output [WIDTH - 1 : 0] re_o,
output [WIDTH - 1 : 0] im_o,
output escaped,
input valid_i,
output valid_o
);
parameter WIDTH = 8;
parameter DIVERGENCE = 1 << 2 * WIDTH;
localparam MAX_SQUARE = 1 << WIDTH;
localparam VALID_DELAY = 2 * WIDTH + 4;
reg [VALID_DELAY - 1 : 0] valid_pipe = 0;
reg signed [WIDTH - 1 : 0] re_c_pipe [WIDTH + 1 : 0];
reg signed [WIDTH - 1 : 0] im_c_pipe [WIDTH + 1: 0];
always @(*)
begin
valid_pipe[0] <= valid_i;
end
always @(posedge clk)
begin
valid_pipe[VALID_DELAY - 1 : 1] <= valid_pipe[VALID_DELAY - 2 : 0];
end
assign valid_o = valid_pipe[VALID_DELAY - 1];
// Can reduce the number of multiplications
// zn+1 = z^2
// = (x + iy)^2
// = x^2 - y^2 + 2*xyi
// = (x + y)*(x - y) + (x + x)*yi
wire signed [WIDTH : 0] x_signed;
wire signed [WIDTH : 0] y_signed;
// Extend width by one to fit multipliers after addition
assign x_signed = {re_i[WIDTH - 1], re_i};
assign y_signed = {im_i[WIDTH - 1], im_i};
reg signed [WIDTH : 0] x_p_y;
reg signed [WIDTH : 0] x_m_y;
reg signed [WIDTH : 0] double_x;
reg signed [WIDTH : 0] y_d;
wire signed [(WIDTH + 1) * 2 - 1 : 0] re;
wire signed [(WIDTH + 1) * 2 - 1 : 0] im;
always @(posedge clk)
begin
x_p_y <= x_signed + y_signed;
x_m_y <= x_signed - y_signed;
double_x <= re_i << 1; // BUG: Double a negative
y_d <= y_signed;
end
multiplier#(
.WIDTH(WIDTH + 1) // (x + y) * (x - y)
) mult_1(
.clk(clk),
.a(x_p_y),
.b(x_m_y),
.c(re)
);
multiplier#(
.WIDTH(WIDTH + 1) // (x + x) * y
) mult_2(
.clk(clk),
.a(double_x),
.b(y_d),
.c(im)
);
// Now find the magnitude
reg [WIDTH - 1 : 0] im_pipe [WIDTH : 0];
reg [WIDTH - 1 : 0] re_pipe [WIDTH : 0];
reg [WIDTH : 0] escaped_i;
wire [WIDTH * 2 - 1 : 0] im_squared;
wire [WIDTH * 2 - 1 : 0] re_squared;
wire [WIDTH - 1 : 0] im_d;
wire [WIDTH - 1 : 0] re_d;
always @(posedge clk)
begin
re_c_pipe[0] <= re_c;
im_c_pipe[0] <= im_c;
// Check width after addition
re_pipe[0] <= re[WIDTH - 1 : 0] + re_c_pipe[WIDTH + 1];
im_pipe[0] <= im[WIDTH - 1 : 0] + im_c_pipe[WIDTH + 1];
escaped_i[0] <= ((im + im_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((im + im_c_pipe[WIDTH + 1]) < -MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) > MAX_SQUARE)
|| ((re + re_c_pipe[WIDTH + 1]) < -MAX_SQUARE);
escaped_i[WIDTH : 1] <= escaped_i[WIDTH - 1 : 0];
end
genvar i;
generate
for (i = 1; i < WIDTH + 1; i = i + 1)
begin
always @(posedge clk)
begin
re_pipe[i] <= re_pipe[i - 1];
im_pipe[i] <= im_pipe[i - 1];
re_c_pipe[i] <= re_c_pipe[i - 1];
im_c_pipe[i] <= im_c_pipe[i - 1];
end
end
endgenerate
always @(posedge clk)
begin
re_c_pipe[WIDTH + 1] <= re_c_pipe[WIDTH];
im_c_pipe[WIDTH + 1] <= im_c_pipe[WIDTH];
end
assign re_d = re_pipe[0];
assign im_d = im_pipe[0];
assign re_o = re_pipe[WIDTH];
assign im_o = im_pipe[WIDTH];
multiplier#(
.WIDTH(WIDTH)
) square_im(
.clk(clk),
.a(im_d),
.b(im_d),
.c(im_squared)
);
multiplier#(
.WIDTH(WIDTH)
) square_re(
.clk(clk),
.a(re_d),
.b(re_d),
.c(re_squared)
);
assign escaped = ( (re_squared + im_squared) > DIVERGENCE ) || escaped_i[WIDTH];
// assign escaped = valid_pipe[VALID_DELAY - 1] &&im_squared[2];
integer k;
initial
begin
$dumpfile("./build/iverilog/mandlebrot.vcd");
for (k = 0; k < WIDTH + 1; k = k + 1)
begin
$dumpvars(0, re_pipe[k]);
$dumpvars(0, im_pipe[k]);
$dumpvars(0, im_c_pipe[k]);
$dumpvars(0, re_c_pipe[k]);
end
$dumpvars(0, im_c_pipe[10]);
$dumpvars(0, re_c_pipe[10]);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char str[105]; int main() { int n; scanf( %d , &n); scanf( %s , str); vector<int> g; int sum = 0; for (int i = 0; i < n; i++) { if (str[i] == B ) { sum++; } else { if (sum) g.push_back(sum); sum = 0; } } if (sum) g.push_back(sum); printf( %d n , g.size()); for (int i = 0; i < g.size(); i++) { printf( %d , g[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } typedef vector<vector<int> > VVI; inline int mult(int x, int y) { return ((long long)x * y) % 1000000007; } int power(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = mult(ret, x); x = mult(x, x); y = y / 2; } return ret; } int gcd(int a, int b) { if (b) return gcd(b, a % b); return a; } vector<int> prime; void generateprime(int n) { int i, j; vector<int> num(n + 5); num[1] = 1; for (i = 4; i < n; i = i + 2) num[i] = 1; for (i = 3; i < n; i++) { if (num[i] == 0) { for (j = 3 * i; j < n; j = j + 2 * i) num[j] = 1; } } num[0] = 0; for (i = 2; i < n; i++) { if (num[i] == 0) prime.push_back(i); num.clear(); } } int main() { int count1, n, i, temp; scanf( %d , &n); if (n == 1) { scanf( %d , &temp); if (temp == 1) printf( YES n ); if (temp == 0) printf( NO n ); } else { count1 = 0; for (i = 0; i < n; i++) { scanf( %d , &temp); if (temp == 1) count1++; } if (count1 == n - 1) printf( YES n ); else printf( NO n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int n, m; char ch[20][120]; int l[20], r[20], visit[20], dp[20][2]; int main() { while (~scanf( %d%d , &n, &m)) { memset(visit, 0, sizeof visit); memset(r, 0, sizeof r); memset(l, 0, sizeof l); for (int i = n; i >= 1; i--) { scanf( %s , ch[i] + 1); for (int j = 2; j <= m + 1; j++) if (ch[i][j] == 1 ) { l[i] = j; visit[i] = 1; break; } for (int j = m + 1; j >= 2; j--) if (ch[i][j] == 1 ) { r[i] = j; break; } } int x = n; while (!visit[x--] && x >= 1) n--; if (n == 1) { printf( %d n , r[1] ? r[1] - 1 : 0); continue; } memset(dp, INF, sizeof dp); dp[1][0] = r[1] ? (r[1] - 1) * 2 : 0, dp[1][1] = m + 1; for (int i = 2; i < n; i++) { if (!visit[i]) { dp[i][0] = dp[i - 1][0] + 1; dp[i][1] = dp[i - 1][1] + 1; continue; } dp[i][0] = min(dp[i - 1][0] + 2 * (r[i] - 1) + 1, dp[i][0]); dp[i][0] = min(dp[i - 1][1] + m + 1 + 1, dp[i][0]); dp[i][1] = min(dp[i - 1][1] + 2 * (m + 2 - l[i]) + 1, dp[i][1]); dp[i][1] = min(dp[i - 1][0] + m + 1 + 1, dp[i][1]); } int ans = min(dp[n - 1][0] + r[n], dp[n - 1][1] + 1 + m + 2 - l[n]); printf( %d n , ans); } return 0; }
|
//#############################################################################
//# Function: Clock synchronizer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_dsync #(parameter PS = 2, // number of sync stages
parameter DELAY = 0 // random delay
)
(
input clk, // clock
input nreset, // clock
input din, // input data
output dout // synchronized data
);
localparam ASIC = `CFG_ASIC; // use asic library
generate
if(ASIC)
begin : g0
asic_dsync asic_dsync (.clk(clk),
.nreset(nreset),
.din(din),
.dout(dout));
end
else
begin : g0
reg [PS:0] sync_pipe;
always @ (posedge clk or negedge nreset)
if(!nreset)
sync_pipe[PS:0] <= 1'b0;
else
sync_pipe[PS:0] <= {sync_pipe[PS-1:0],din};
// drive randomize delay from testbench
assign dout = (DELAY & sync_pipe[PS]) | //extra cycle
(~DELAY & sync_pipe[PS-1]); //default
end
endgenerate
endmodule // oh_dsync
|
#include <bits/stdc++.h> using namespace std; int c1; struct state { int h1, a1, h2, a2, level; int laststate; state() {} state(int a, int b, int c, int d, int e, int f) : h1(a), a1(b), h2(c), a2(d), level(e), laststate(f) {} }; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int N; cin >> N; vector<unsigned long long> a(N); for (int i = 0; i < N; ++i) { cin >> a[i]; } unsigned long long prfx = 0; map<int, unsigned long long> removals; map<int, unsigned long long> rcount; unsigned long long nans = 0, pans = 0; for (int i; i < N; ++i) { unsigned long long tp = ((unsigned long long)a[i]) * i; if (tp > prfx) pans += tp - prfx; else nans += prfx - tp; if (removals.count(a[i]) != 0) { unsigned long long ot = ((unsigned long long)a[i]) * rcount[a[i]]; unsigned long long rmls = removals[a[i]]; if (ot > rmls) nans += ot - rmls; else pans += rmls - ot; } prfx += a[i]; if (rcount.count(a[i] - 1) == 0) rcount[a[i] - 1] = 0; if (rcount.count(a[i] + 1) == 0) rcount[a[i] + 1] = 0; if (rcount.count(a[i]) == 0) rcount[a[i]] = 0; if (removals.count(a[i] - 1) == 0) removals[a[i] - 1] = 0; if (removals.count(a[i] + 1) == 0) removals[a[i] + 1] = 0; if (removals.count(a[i]) == 0) removals[a[i]] = 0; removals[a[i] - 1] += a[i]; removals[a[i] + 1] += a[i]; removals[a[i]] += a[i]; ++rcount[a[i] + 1]; ++rcount[a[i] - 1]; ++rcount[a[i]]; if (pans > nans) { pans -= nans; nans = 0; } else { nans -= pans; pans = 0; } } if (pans > 0 || (pans == 0 && nans == 0)) cout << pans << endl; else cout << - << nans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, c[23][23], d[23], u[23]; int main() { scanf( %d%d , &n, &m); for (int xt, yt, i = 1; i <= m; ++i) { scanf( %d%d , &xt, &yt); if (c[xt][yt] || xt == yt) continue; ++d[xt], ++d[yt]; c[xt][yt] = c[yt][xt] = 1; } for (int j, co, p, mint, i = 1; i <= n; ++i) { fill(u, u + n + 1, 0); co = 0; for (j = i; !u[j]; j = p) { mint = n + n; p = j; u[j] = 1; ++co; for (int k = 1; k <= n; ++k) if (!u[k] && c[j][k] && (d[k] < mint || d[k] == mint && k < p)) p = k, mint = d[k]; } if (co == n) { puts( Yes ); return 0; } } puts( No ); }
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#include <bits/stdc++.h> using namespace std; const int N = 4010; const int T = 20010; int n, p, q, c[N], h[N], t[N], cs[T], cd[T], b[T], rez[T]; int d[10010][N]; vector<int> v[T], v2[T], v3[T]; void sol(int pozs) { int pozd = min(T - 1, pozs + 2 * p), mid = pozs + p; vector<int>::iterator it; int i, j; for (i = pozs; i <= mid; ++i) memset(d[i - pozs], 0, sizeof(d[i - pozs])); int din[N]; memset(din, 0, sizeof(din)); for (i = mid - 1; i >= pozs; --i) { for (it = v[i].begin(); it != v[i].end(); ++it) for (j = N - 1; j >= c[*it]; --j) din[j] = max(din[j], din[j - c[*it]] + h[*it]); memcpy(d[i - pozs], din, sizeof(din)); } memset(din, 0, sizeof(din)); for (i = mid; i <= pozd; ++i) { for (it = v[i].begin(); it != v[i].end(); ++it) for (j = N - 1; j >= c[*it]; --j) din[j] = max(din[j], din[j - c[*it]] + h[*it]); for (it = v2[i - p].begin(); it != v2[i - p].end(); ++it) for (j = 0; j <= b[*it]; ++j) rez[*it] = max(rez[*it], d[i - p - pozs][j] + din[b[*it] - j]); } } void sol1() { int i, j; int din[N]; memset(din, 0, sizeof(din)); vector<int>::iterator it; for (i = 1; i <= p + 1; ++i) { for (it = v[i].begin(); it != v[i].end(); ++it) for (j = N - 1; j >= c[*it]; --j) din[j] = max(din[j], din[j - c[*it]] + h[*it]); for (it = v3[i].begin(); it != v3[i].end(); ++it) rez[*it] = din[b[*it]]; } } int main() { int i, j, k; cin >> n >> p; --p; for (i = 1; i <= n; ++i) { cin >> c[i] >> h[i] >> t[i]; v[t[i]].push_back(i); } cin >> q; for (i = 1; i <= q; ++i) { cin >> cd[i] >> b[i]; cs[i] = max(1, cd[i] - p); if (cs[i] == 1) { v3[cd[i]].push_back(i); continue; } v2[cs[i]].push_back(i); } sol1(); for (int t = 0; t + p < T; t += p) sol(t); for (i = 1; i <= q; ++i) cout << rez[i] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; template <class T> T sq(T x) { return x * x; } const long long inf = 2147383647; const double pi = 2 * acos(0.0); const double eps = 1e-9; const long long maxint = 2147483647; const long long minint = -2147483648; int n, m; long long arr[100010], brr[100010]; long long dp1[100010], dp2[100010]; void input() { int i; for (i = 0; i < n; i++) { scanf( %I64d , &arr[i]); } for (i = 0; i < m; i++) { scanf( %I64d , &brr[i]); } sort(arr, arr + n); sort(brr, brr + m); } void dpcalc() { dp1[0] = 0; int i; for (i = 1; i < n; i++) { dp1[i] = dp1[i - 1]; dp1[i] += i * (arr[i] - arr[i - 1]); } dp2[m - 1] = 0; for (i = m - 2; i >= 0; i--) { dp2[i] = dp2[i + 1]; int e = m - i - 1; dp2[i] += e * (brr[i + 1] - brr[i]); } } long long findCost(long long x) { long long res = 0; long long pos = upper_bound(arr, arr + n, x) - arr; if (pos > 0) { pos--; res += dp1[pos]; res += (pos + 1) * (x - arr[pos]); } pos = lower_bound(brr, brr + m, x) - brr; if (pos < m) { res += dp2[pos]; res += (m - pos) * (brr[pos] - x); } return res; } int main() { scanf( %d %d , &n, &m); int i, j; input(); dpcalc(); long long low = 1, high = 1000000000; long long res = -1; while (high - low > 5) { long long m1 = (2 * low + high) / 3; long long m2 = (low + 2 * high) / 3; long long u = findCost(m1); long long v = findCost(m2); if (res == -1) res = u; res = min(res, u); res = min(res, v); if (u > v) { low = m1 + 1; } else { high = m2 - 1; } } while (low <= high) { res = min(res, findCost(low)); low++; } printf( %I64d n , res); return 0; }
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#include <bits/stdc++.h> using namespace std; bool changed[222222]; pair<int, int> edges[222222]; set<pair<int, int> > adj[111111]; bool visited[111111]; deque<pair<int, int> > to_connect; vector<int> Harry; char outbuf[12000000]; char* out = outbuf; int moves = 0; void flush_harry() { out += sprintf(out, %d , Harry.size()); for (int v : Harry) { out += sprintf(out, %d , v); } out += sprintf(out, n ); Harry.clear(); } void move_stairs(int id, int u, int v) { ++moves; flush_harry(); adj[edges[id].first].erase(pair<int, int>(edges[id].second, id)); adj[edges[id].second].erase(pair<int, int>(edges[id].first, id)); edges[id].first = u, edges[id].second = v; adj[u].insert(pair<int, int>(v, id)); adj[v].insert(pair<int, int>(u, id)); out += sprintf(out, %d %d %d n , id, u, v); changed[id] = true; } vector<int> in_component; bool dfs1(int v, int parent_edge, bool connected_to_one) { visited[v] = true; in_component.push_back(v); int edge_to_move = -1; for (auto& p : adj[v]) { if (!connected_to_one && visited[p.first] && parent_edge != p.second) { edge_to_move = p.second; connected_to_one = true; } else if (!visited[p.first]) { connected_to_one = dfs1(p.first, p.second, connected_to_one); } } if (edge_to_move != -1) { move_stairs(edge_to_move, v, 1); } return connected_to_one; } void dfs2(int v, int parent_edge) { if (v != 1) Harry.push_back(v); visited[v] = true; for (auto& p : adj[v]) if (!visited[p.first]) { dfs2(p.first, p.second); Harry.push_back(v); } vector<pair<int, int> > to_change; for (auto& p : adj[v]) if (p.second != parent_edge && !to_connect.empty() && !changed[p.second]) { to_change.push_back(pair<int, int>(p.second, to_connect.back().second)); to_connect.pop_back(); } for (auto& p : to_change) { move_stairs(p.first, v, p.second); dfs2(p.second, p.first); Harry.push_back(v); } } int main() { int N, M; scanf( %d%d , &N, &M); for (int i = (0); i < (M); ++i) { int a, b; scanf( %d%d , &a, &b); adj[a].insert(pair<int, int>(b, i + 1)); adj[b].insert(pair<int, int>(a, i + 1)); edges[i + 1].first = a, edges[i + 1].second = b; } Harry.push_back(1); for (int i = (1); i < (N + 1); ++i) if (!visited[i]) { bool connected_to_one = dfs1(i, -1, i == 1); if (!connected_to_one) { for (int& v : in_component) if (adj[v].size() <= 1) { to_connect.push_back(pair<int, int>(in_component.size(), v)); break; } } in_component.clear(); } sort(to_connect.begin(), to_connect.end()); for (int i = (1); i < (N + 1); ++i) visited[i] = false; dfs2(1, -1); while (!to_connect.empty() && to_connect.back().first > 1) { int v = to_connect.back().second; to_connect.push_front(pair<int, int>(1, v)); to_connect.pop_back(); pair<int, int> n = *adj[v].begin(); move_stairs(n.second, 1, n.first); dfs2(n.first, n.second); Harry.push_back(1); } flush_harry(); if (!to_connect.empty()) { printf( NO n ); return 0; } printf( YES n%d n , moves); printf( %s n , outbuf); }
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#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 5; vector<long long> adj[N]; vector<pair<long long, long long> > lol[N]; long long x[N], y[N], z[N], vis[N], tin[N], low[N], bridge[N], comp[N], artificat[N], depth[N], par[N], path[N], timer, cur; void dfs1(long long node, long long prvId) { vis[node] = 1; tin[node] = low[node] = ++timer; for (auto &id : adj[node]) { if (id == prvId) continue; long long v = x[id] ^ y[id] ^ node; if (!vis[v]) dfs1(v, id), low[node] = min(low[node], low[v]); else low[node] = min(low[node], tin[v]); if (low[v] > tin[node]) bridge[id] = 1; } } void dfs2(long long node) { comp[node] = cur; vis[node] = 1; for (auto &id : adj[node]) { if (bridge[id]) continue; if (z[id]) artificat[cur] = 1; long long v = x[id] ^ y[id] ^ node; if (!vis[v]) dfs2(v); } } void dfs3(long long node, long long pr) { depth[node] = depth[pr] + 1; par[node] = pr; for (auto &ele : lol[node]) if (ele.first != pr) path[ele.first] = ele.second, dfs3(ele.first, node); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m; cin >> n >> m; for (long long i = 1; i <= m; i++) { cin >> x[i] >> y[i] >> z[i]; adj[x[i]].push_back(i); adj[y[i]].push_back(i); } dfs1(1, 0); for (long long i = 1; i <= n; i++) vis[i] = 0; for (long long i = 1; i <= n; i++) if (!vis[i]) cur++, dfs2(i); for (long long i = 1; i <= m; i++) { if (bridge[i]) { lol[comp[x[i]]].push_back({comp[y[i]], z[i]}); lol[comp[y[i]]].push_back({comp[x[i]], z[i]}); } } dfs3(1, 0); long long s, t; cin >> s >> t; s = comp[s], t = comp[t]; while (s != t) { if (depth[s] < depth[t]) swap(s, t); if (artificat[s] || path[s]) return cout << YES , 0; s = par[s]; } cout << (artificat[s] ? YES : NO ); }
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#include <bits/stdc++.h> using namespace std; const int N = 6e6 + 500; int pt[N << 1], tn, m; pair<int, pair<int, int> > seg1[N], seg2[N]; int n1, n2; int getdep(const pair<int, int> &u) { return u.first + u.second; } int lowbit(const int &x) { if (!x) return 1 << 30; return x & -x; } pair<int, int> getfa(const pair<int, int> &u) { if (!u.first || !u.second) return make_pair(0, 0); return lowbit(u.first) < lowbit(u.second) ? make_pair(u.first - 1, u.second) : make_pair(u.first, u.second - 1); } pair<int, int> gettop(const pair<int, int> &u) { if (!u.first || !u.second) return make_pair((u.first != 0), (u.second != 0)); if (lowbit(u.first) < lowbit(u.second)) { return make_pair(1 + (u.first & (~(lowbit(u.second) - 1))), u.second); } else { return make_pair(u.first, 1 + (u.second & (~(lowbit(u.first) - 1)))); } } void ins(pair<int, int> u, pair<int, int> v) { pair<int, int> tpu, tpv; while ((tpu = gettop(u)) != (tpv = gettop(v))) { if (getdep(tpu) > getdep(tpv)) { if (lowbit(u.second) < lowbit(u.first)) seg1[++n1] = make_pair(u.first, make_pair(tpu.second, u.second)); else seg2[++n2] = make_pair(u.second, make_pair(tpu.first, u.first)); u = getfa(tpu); } else { if (lowbit(v.second) < lowbit(v.first)) seg1[++n1] = make_pair(v.first, make_pair(tpv.second, v.second)); else seg2[++n2] = make_pair(v.second, make_pair(tpv.first, v.first)); v = getfa(tpv); } } if (getdep(u) > getdep(v)) swap(u, v); if (lowbit(u.second) < lowbit(u.first)) seg1[++n1] = make_pair(u.first, make_pair(u.second, v.second)); else seg2[++n2] = make_pair(u.second, make_pair(u.first, v.first)); } int main() { scanf( %d , &m); for (int i = 1; i <= m; i++) { pair<int, int> u, v; scanf( %d%d%d%d , &u.first, &u.second, &v.first, &v.second); ins(u, v); } sort(seg1 + 1, seg1 + n1 + 1), sort(seg2 + 1, seg2 + n2 + 1); for (int i = 1, j; i <= n1; i = j + 1) { j = i; while (j + 1 <= n1 && seg1[j + 1].first == seg1[j].first) ++j; int l = seg1[i].second.first, r = seg1[i].second.second; for (int k = i + 1; k <= j; k++) { int tl = seg1[k].second.first, tr = seg1[k].second.second; if (tl <= r + 1) r = max(r, tr); else pt[++tn] = l + seg1[i].first, pt[++tn] = r + seg1[i].first + 1, l = tl, r = tr; } pt[++tn] = l + seg1[i].first, pt[++tn] = r + seg1[i].first + 1; } for (int i = 1, j; i <= n2; i = j + 1) { j = i; while (j + 1 <= n2 && seg2[j + 1].first == seg2[j].first) ++j; int l = seg2[i].second.first, r = seg2[i].second.second; for (int k = i + 1; k <= j; k++) { int tl = seg2[k].second.first, tr = seg2[k].second.second; if (tl <= r + 1) r = max(r, tr); else pt[++tn] = l + seg2[i].first, pt[++tn] = r + seg2[i].first + 1, l = tl, r = tr; } pt[++tn] = l + seg2[i].first, pt[++tn] = r + seg2[i].first + 1; } sort(pt + 1, pt + tn + 1); int ans = 0; for (int i = 1, j; i <= tn; i = j + 1) { j = i; if (!pt[i]) continue; while (j + 1 <= tn && pt[j + 1] == pt[i]) ++j; if (((j - i + 1) & 1)) ++ans; } cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; long long n, i, j, k, l, sum = 0, flag = 0, t, a[200005], ans = 0; vector<int> tree[800005]; void build(int node, int low, int high) { if (low == high) { tree[node].push_back(a[low]); return; } int mid = (low + high) / 2; build(2 * node, low, mid); build(2 * node + 1, mid + 1, high); merge((tree[2 * node]).begin(), (tree[2 * node]).end(), (tree[2 * node + 1]).begin(), (tree[2 * node + 1]).end(), back_inserter(tree[node])); return; } int query(int node, int low, int high, int l, int r, int val) { if (l > r) return 0; if (low > r || high < l) return 0; if (l <= low && high <= r) return tree[node].end() - lower_bound((tree[node]).begin(), (tree[node]).end(), val); int mid = (low + high) / 2; return query(2 * node, low, mid, l, r, val) + query(2 * node + 1, mid + 1, high, l, r, val); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; build(1, 1, n); for (i = 1; i <= n; i++) { ans += query(1, 1, n, i + 1, min(a[i], n), i); } cout << ans << n ; return 0; }
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/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test catches the case where the operands of the ?: operator
* have different sizes.
*/
module main;
reg [3:0] r;
reg [3:0] a;
reg [4:0] b;
reg f;
initial begin
a = 4'b1010;
b = 5'b10101;
f = 1;
r = f? a : b;
if (r !== 4'b1010) begin
$display("FAILED: r === %b", r);
$finish;
end
f = 0;
r = f? a : b;
if (r !== 4'b0101) begin
$display("FAILED: r === %b", r);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg [60:0] qq4;
reg [60:0] rq4;
reg [60:0] qq5;
reg [60:0] rq5;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qq4 = a[60:0] / 4; // Check power-of-two constification
rq4 = a[60:0] % 4;
qq5 = a[60:0] / 5; // Non power-of-two
rq5 = a[60:0] % 5;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc > 1) begin
if (qq4 != {2'b0, a[60:2]}) $stop;
if (rq4 != {59'h0, a[1:0]}) $stop;
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
if (qq4 != 61'h01247cf6851f9fc9) $stop;
if (rq4 != 61'h0000000000000002) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
if (qq4 != 61'h0292380e727ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
if (qq4 != 61'h07482923803ce56e) $stop;
if (rq4 != 61'h0000000000000000) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//======================================================================
//
// sha1.v
// ------
// Top level wrapper for the SHA-1 hash function providing
// a simple memory like interface with 32 bit data access.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013 Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha1(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam STATUS_VALID_BIT = 1;
localparam ADDR_BLOCK0 = 8'h10;
localparam ADDR_BLOCK15 = 8'h1f;
localparam ADDR_DIGEST0 = 8'h20;
localparam ADDR_DIGEST4 = 8'h24;
localparam CORE_NAME0 = 32'h73686131; // "sha1"
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3630; // "0.60"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
reg init_new;
reg next_reg;
reg next_new;
reg ready_reg;
reg [31 : 0] block_reg [0 : 15];
reg block_we;
reg [159 : 0] digest_reg;
reg digest_valid_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire core_ready;
wire [511 : 0] core_block;
wire [159 : 0] core_digest;
wire core_digest_valid;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign core_block = {block_reg[00], block_reg[01], block_reg[02], block_reg[03],
block_reg[04], block_reg[05], block_reg[06], block_reg[07],
block_reg[08], block_reg[09], block_reg[10], block_reg[11],
block_reg[12], block_reg[13], block_reg[14], block_reg[15]};
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
sha1_core core(
.clk(clk),
.reset_n(reset_n),
.init(init_reg),
.next(next_reg),
.block(core_block),
.ready(core_ready),
.digest(core_digest),
.digest_valid(core_digest_valid)
);
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
init_reg <= 1'h0;
next_reg <= 1'h0;
ready_reg <= 1'h0;
digest_reg <= 160'h0;
digest_valid_reg <= 1'h0;
for (i = 0 ; i < 16 ; i = i + 1)
block_reg[i] <= 32'h0;
end
else
begin
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
init_reg <= init_new;
next_reg <= next_new;
if (block_we)
block_reg[address[3 : 0]] <= write_data;
if (core_digest_valid)
digest_reg <= core_digest;
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
init_new = 1'h0;
next_new = 1'h0;
block_we = 1'h0;
tmp_read_data = 32'h0;
tmp_error = 1'h0;
if (cs)
begin
if (we)
begin
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
block_we = 1'h1;
if (address == ADDR_CTRL)
begin
init_new = write_data[CTRL_INIT_BIT];
next_new = write_data[CTRL_NEXT_BIT];
end
end // if (write_read)
else
begin
if ((address >= ADDR_BLOCK0) && (address <= ADDR_BLOCK15))
tmp_read_data = block_reg[address[3 : 0]];
if ((address >= ADDR_DIGEST0) && (address <= ADDR_DIGEST4))
tmp_read_data = digest_reg[(4 - (address - ADDR_DIGEST0)) * 32 +: 32];
case (address)
// Read operations.
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {30'h0, next_reg, init_reg};
ADDR_STATUS:
tmp_read_data = {30'h0, digest_valid_reg, ready_reg};
default:
begin
tmp_error = 1'h1;
end
endcase // case (addr)
end
end
end // addr_decoder
endmodule // sha1
//======================================================================
// EOF sha1.v
//======================================================================
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 2, p = 1e9 + 7; int siz[N], f[N]; int n, m, x, y, z, i, c; inline void read(int &x) { c = getchar(); while ((c < 48) || (c > 57)) c = getchar(); x = c ^ 48; c = getchar(); while ((c >= 48) && (c <= 57)) { x = x * 10 + (c ^ 48); c = getchar(); } } int getf(register int x) { if (f[x] == x) return f[x]; f[x] = getf(f[x]); siz[f[x]] += siz[x]; siz[x] = 0; return f[x]; } inline int ksm(register int x, register int y) { register int r = 1; while (y) { if (y & 1) r = (long long)r * x % p; x = (long long)x * x % p; y >>= 1; } return r; } int main() { read(n); read(m); for (i = 1; i <= n; i++) siz[f[i] = i] = 1; for (i = 1; i < n; i++) { read(x); read(y); read(z); if (z == 0) { siz[getf(y)] += siz[getf(x)]; siz[f[x]] = 0; f[f[x]] = f[y]; } } c = ksm(n, m); for (i = 1; i <= n; i++) if (siz[i]) c = (c - ksm(siz[i], m) + p) % p; printf( %d , c); }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long inf = 0x3f3f3f3f3f3f3f3f; const int maxn = 1005; int main() { int N; cin >> N; cout << 2 * N - 1 << << 2 << endl; cout << 1 << << 2 << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_PP_BLACKBOX_V
|
`timescale 1 ns / 100 ps
`include "sm_cpu.vh"
module sm_testbench;
// simulation options
parameter Tt = 20;
parameter Ncycle = 120;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
// ***** DUT start ************************
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
//cpu core
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( regAddr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData )
);
// ***** DUT end ************************
`ifdef ICARUS
//iverilog memory dump init workaround
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_cpu.rf.rf[k]);
end
`endif
// simulation init
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
//register file reset
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_SPEC, `F_SRLV } : $write ("srlv $%1d, $%1d, $%1d", cmdRd, cmdRt, cmdRs);
{ `C_BGEZ, `F_ANY } : $write ("bgez $%1d, %1d", cmdRt, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_SPEC, `F_NOR } : $write ("nor $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
//simulation debug output
integer cycle; initial cycle = 0;
initial regAddr = 0; // get PC
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_cpu.instr, sm_cpu.rf.rf[2]);
disasmInstr(sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > Ncycle)
begin
$display ("Timeout");
$stop;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool essentiallyEqual(float a, float b) { return fabs(a - b) <= ((fabs(a) > fabs(b) ? fabs(b) : fabs(a)) * 1e-6); } struct TVector { long long x, y; TVector operator+(TVector q) const { return {x + q.x, y + q.y}; } TVector operator-(TVector q) const { return {x - q.x, y - q.y}; } TVector operator*(int t) const { return {x * t, y * t}; } long long operator*(TVector q) const { return {x * q.x + y * q.y}; } long long operator^(TVector q) const { return {x * q.y - q.x * y}; } long double operator~() const { return {hypot(x, y)}; } long double disPointLine(TVector p, TVector q) { TVector r = *this; if (((r - p) * (q - p) >= 0) && ((r - q) * (p - q) >= 0)) { return abs((q - p) ^ (r - p)) / ~(p - q); } else { return min(~(r - p), ~(r - q)); } } bool onLine(TVector p, TVector q) { TVector r = *this; long double dis = r.disPointLine(p, q); return essentiallyEqual(dis, 0); } long double sqrdDist(TVector p) { return (x - p.x) * (x - p.x) + (y - p.y) * (y - p.y); } int orientation(TVector b, TVector c) { TVector a = *this; int val = (c - a) ^ (b - a); return val; } int orientationV2(TVector b, TVector c) { TVector a = *this; int val = (c - a) ^ (b - a); if (val == 0) return 0; return (val > 0) ? 1 : 2; } void imprimePonto() { printf( %lld %lld , x, y); } }; vector<TVector> stormtroopers; vector<int> isShot; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, x0, y0; cin >> n >> x0 >> y0; TVector gun; gun.x = x0; gun.y = y0; for (int i = 0; i < n; ++i) { int x, y; cin >> x >> y; stormtroopers.push_back({x, y}); isShot.push_back(0); } int tiros = 0; for (int i = 0; i < n; ++i) { if (!isShot[i]) { tiros++; for (int j = i + 1; j < n; ++j) { if (!isShot[j]) { if (!gun.orientationV2(stormtroopers[i], stormtroopers[j])) isShot[j] = 1; } } } } cout << tiros << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; void readi(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readll(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readc(char &x) { char c; while ((c = getchar()) == ) ; x = c; } void writes(string s) { puts(s.c_str()); } void writeln() { writes( ); } void writei(int x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } void writell(long long x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } inline long long inc(int &x) { return ++x; } inline long long inc(long long &x) { return ++x; } inline long long inc(int &x, long long y) { return x += y; } inline long long inc(long long &x, long long y) { return x += y; } inline double inc(double &x, double y) { return x += y; } inline long long dec(int &x) { return --x; } inline long long dec(long long &x) { return --x; } inline long long dec(int &x, long long y) { return x -= y; } inline long long dec(long long &x, long long y) { return x -= y; } inline double dec(double &x, double y) { return x -= y; } inline long long mul(int &x) { return x = ((long long)x) * x; } inline long long mul(long long &x) { return x = x * x; } inline long long mul(int &x, long long y) { return x *= y; } inline long long mul(long long &x, long long y) { return x *= y; } inline double mul(double &x, double y) { return x *= y; } inline long long divi(int &x) { return x = sqrt(x); } inline long long divi(long long &x) { return x = sqrt(x); } inline long long divi(int &x, long long y) { return x /= y; } inline long long divi(long long &x, long long y) { return x /= y; } inline double divi(double &x, double y) { return x /= y; } inline long long mod(int &x, long long y) { return x %= y; } inline long long mod(long long &x, long long y) { return x %= y; } long long n, m, i, j, ans = 0; string s; int main() { cin >> n >> s; if (n == 1) { if (s == ? ) { cout << Yes ; return 0; } else { cout << No ; return 0; }; } s = + s + ; for (i = 1; i + 1 < s.size(); i++) { if (s[i] != ? && s[i] == s[i - 1]) { cout << No ; return 0; }; } s[0] = s[2]; s[s.size() - 1] = s[s.size() - 3]; for (i = 1; i + 1 < s.size(); i++) { if (s[i] == ? ) { if (s[i - 1] != s[i + 1] && s[i - 1] != ? && s[i + 1] != ? ) ans++; else { cout << Yes ; return 0; }; } } { cout << No ; return 0; }; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = (int)2e9; const long long INFL = (long long)9e18; const int MAXINT = ((~0) ^ (1 << 31)); const long long MAXLL = ((~0) ^ ((long long)1 << 63)); template <class T> inline T pow2(T a) { return a * a; } template <class T> inline bool mineq(T& a, T b) { return (a > b) ? (a = b, true) : false; } template <class T> inline bool maxeq(T& a, T b) { return (a < b) ? (a = b, true) : false; } const int maxn = 2e5 + 100; long long n, m, d, lt, a, b, t; long long dp[2 * maxn]; long long rmq[2 * maxn]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m >> d; for (int i = 0; i < (int)(m); i++) { cin >> a >> b >> t; t = t - lt; lt = lt + t; long long gap = min(n, t * d); deque<int> stk; for (int i = 0; i < (int)(2 * n); i++) { while (!stk.empty() && dp[stk.back()] <= dp[i]) stk.pop_back(); if (!stk.empty() && stk.front() == i - 2 * gap - 1) stk.pop_front(); stk.push_back(i); rmq[i] = dp[stk.front()]; } for (int i = 0; i < (int)(n); i++) { dp[i] = rmq[i + gap] + b - abs(a - i - 1); } for (int i = n; i < (int)(2 * n); i++) dp[i] = -INF / 2; } cout << *max_element(dp, dp + n) << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e6 + 5; long long n, m, i, t, j, k, l, x, y, z, s, e, p, q; long long dg(long long s, long long e) { if (e % 2) return 1 - s % 2; if (s > e / 2) return s % 2; if (s > e / 4) return 1; return dg(s, e / 4); } int main() { scanf( %lld , &n); p = 0; q = 1; for (int i = 1; i <= n; i++) { scanf( %lld%lld , &s, &e); x = dg(s, e); if (s > e / 2) y = 1; else y = dg(s, e / 2); if (p + q != 1) continue; else if (p) p = 1 - x, q = 1 - y; else p = x, q = y; } printf( %lld %lld n , p, q); }
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// This module to implement the Conditional Branch Instructions,
// which is mostly share the datapath with ALU adder to resolve the comparasion
// result to save gatecount to mininum
//
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_alu_bjp(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input bjp_i_valid, // Handshake valid
output bjp_i_ready, // Handshake ready
input [`E203_XLEN-1:0] bjp_i_rs1,
input [`E203_XLEN-1:0] bjp_i_rs2,
input [`E203_XLEN-1:0] bjp_i_imm,
input [`E203_PC_SIZE-1:0] bjp_i_pc,
input [`E203_DECINFO_BJP_WIDTH-1:0] bjp_i_info,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The BJP Commit Interface
output bjp_o_valid, // Handshake valid
input bjp_o_ready, // Handshake ready
// The Write-Back Result for JAL and JALR
output [`E203_XLEN-1:0] bjp_o_wbck_wdat,
output bjp_o_wbck_err,
// The Commit Result for BJP
output bjp_o_cmt_bjp,
output bjp_o_cmt_mret,
output bjp_o_cmt_dret,
output bjp_o_cmt_fencei,
output bjp_o_cmt_prdt,// The predicted ture/false
output bjp_o_cmt_rslv,// The resolved ture/false
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath
//
// The operands and info to ALU
output [`E203_XLEN-1:0] bjp_req_alu_op1,
output [`E203_XLEN-1:0] bjp_req_alu_op2,
output bjp_req_alu_cmp_eq ,
output bjp_req_alu_cmp_ne ,
output bjp_req_alu_cmp_lt ,
output bjp_req_alu_cmp_gt ,
output bjp_req_alu_cmp_ltu,
output bjp_req_alu_cmp_gtu,
output bjp_req_alu_add,
input bjp_req_alu_cmp_res,
input [`E203_XLEN-1:0] bjp_req_alu_add_res,
input clk,
input rst_n
);
wire mret = bjp_i_info [`E203_DECINFO_BJP_MRET ];
wire dret = bjp_i_info [`E203_DECINFO_BJP_DRET ];
wire fencei = bjp_i_info [`E203_DECINFO_BJP_FENCEI ];
wire bxx = bjp_i_info [`E203_DECINFO_BJP_BXX ];
wire jump = bjp_i_info [`E203_DECINFO_BJP_JUMP ];
wire rv32 = bjp_i_info [`E203_DECINFO_RV32];
wire wbck_link = jump;
wire bjp_i_bprdt = bjp_i_info [`E203_DECINFO_BJP_BPRDT ];
assign bjp_req_alu_op1 = wbck_link ?
bjp_i_pc
: bjp_i_rs1;
assign bjp_req_alu_op2 = wbck_link ?
(rv32 ? `E203_XLEN'd4 : `E203_XLEN'd2)
: bjp_i_rs2;
assign bjp_o_cmt_bjp = bxx | jump;
assign bjp_o_cmt_mret = mret;
assign bjp_o_cmt_dret = dret;
assign bjp_o_cmt_fencei = fencei;
assign bjp_req_alu_cmp_eq = bjp_i_info [`E203_DECINFO_BJP_BEQ ];
assign bjp_req_alu_cmp_ne = bjp_i_info [`E203_DECINFO_BJP_BNE ];
assign bjp_req_alu_cmp_lt = bjp_i_info [`E203_DECINFO_BJP_BLT ];
assign bjp_req_alu_cmp_gt = bjp_i_info [`E203_DECINFO_BJP_BGT ];
assign bjp_req_alu_cmp_ltu = bjp_i_info [`E203_DECINFO_BJP_BLTU ];
assign bjp_req_alu_cmp_gtu = bjp_i_info [`E203_DECINFO_BJP_BGTU ];
assign bjp_req_alu_add = wbck_link;
assign bjp_o_valid = bjp_i_valid;
assign bjp_i_ready = bjp_o_ready;
assign bjp_o_cmt_prdt = bjp_i_bprdt;
assign bjp_o_cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res;
assign bjp_o_wbck_wdat = bjp_req_alu_add_res;
assign bjp_o_wbck_err = 1'b0;
endmodule
|
module io1_sub(
/*AUTOARG*/
// Outputs
sec_out, lower_out,
// Inouts
sec_io, lower_io,
// Inputs
sec_ina, lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To instio of instio.v
input sec_ina; // To instio of instio.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout lower_io; // To/From instio of instio.v
inout sec_io; // To/From instio of instio.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From instio of instio.v
output sec_out; // From instio of instio.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
.sec_out (sec_out),
// Inouts
.lower_io (lower_io),
.sec_io (sec_io),
// Inputs
.lower_ina (lower_ina),
.sec_ina (sec_ina));
endmodule
module instio (/*AUTOARG*/
// Outputs
lower_out, sec_out,
// Inouts
lower_io, sec_io,
// Inputs
lower_ina, sec_ina
);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
|
#include <bits/stdc++.h> using namespace std; int Max = INT_MIN, Min = INT_MAX; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n, m, mx = 0; cin >> n >> m; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { if ((a[i] - a[i + 1] - m) > mx) { mx = (a[i] - a[i + 1] - m); } } cout << ((mx > 0) ? mx : 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[200]; vector<pair<int, int> > v; int main() { scanf( %s , s); int len = strlen(s); pair<int, int> cur(0, 0); v.push_back(cur); for (int i = 0; i < len; i++) { if (s[i] == L ) { cur.first--; } else if (s[i] == R ) { cur.first++; } else if (s[i] == U ) { cur.second++; } else if (s[i] == D ) { cur.second--; } v.push_back(cur); } bool res = false; len = v.size(); for (int i = 0; i < len; i++) { for (int j = i + 2; j < len; j++) { if (abs(v[i].first - v[j].first) + abs(v[i].second - v[j].second) <= 1) { res = true; goto zzz; } } } zzz: if (res) { printf( BUG ); } else { printf( OK ); } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:30:26 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_1_0_sim_netlist.v
// Design : system_buffer_register_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_buffer_register_1_0_buffer_register
(val_out,
val_in,
clk);
output [31:0]val_out;
input [31:0]val_in;
input clk;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
FDRE \val_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(val_in[0]),
.Q(val_out[0]),
.R(1'b0));
FDRE \val_out_reg[10]
(.C(clk),
.CE(1'b1),
.D(val_in[10]),
.Q(val_out[10]),
.R(1'b0));
FDRE \val_out_reg[11]
(.C(clk),
.CE(1'b1),
.D(val_in[11]),
.Q(val_out[11]),
.R(1'b0));
FDRE \val_out_reg[12]
(.C(clk),
.CE(1'b1),
.D(val_in[12]),
.Q(val_out[12]),
.R(1'b0));
FDRE \val_out_reg[13]
(.C(clk),
.CE(1'b1),
.D(val_in[13]),
.Q(val_out[13]),
.R(1'b0));
FDRE \val_out_reg[14]
(.C(clk),
.CE(1'b1),
.D(val_in[14]),
.Q(val_out[14]),
.R(1'b0));
FDRE \val_out_reg[15]
(.C(clk),
.CE(1'b1),
.D(val_in[15]),
.Q(val_out[15]),
.R(1'b0));
FDRE \val_out_reg[16]
(.C(clk),
.CE(1'b1),
.D(val_in[16]),
.Q(val_out[16]),
.R(1'b0));
FDRE \val_out_reg[17]
(.C(clk),
.CE(1'b1),
.D(val_in[17]),
.Q(val_out[17]),
.R(1'b0));
FDRE \val_out_reg[18]
(.C(clk),
.CE(1'b1),
.D(val_in[18]),
.Q(val_out[18]),
.R(1'b0));
FDRE \val_out_reg[19]
(.C(clk),
.CE(1'b1),
.D(val_in[19]),
.Q(val_out[19]),
.R(1'b0));
FDRE \val_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(val_in[1]),
.Q(val_out[1]),
.R(1'b0));
FDRE \val_out_reg[20]
(.C(clk),
.CE(1'b1),
.D(val_in[20]),
.Q(val_out[20]),
.R(1'b0));
FDRE \val_out_reg[21]
(.C(clk),
.CE(1'b1),
.D(val_in[21]),
.Q(val_out[21]),
.R(1'b0));
FDRE \val_out_reg[22]
(.C(clk),
.CE(1'b1),
.D(val_in[22]),
.Q(val_out[22]),
.R(1'b0));
FDRE \val_out_reg[23]
(.C(clk),
.CE(1'b1),
.D(val_in[23]),
.Q(val_out[23]),
.R(1'b0));
FDRE \val_out_reg[24]
(.C(clk),
.CE(1'b1),
.D(val_in[24]),
.Q(val_out[24]),
.R(1'b0));
FDRE \val_out_reg[25]
(.C(clk),
.CE(1'b1),
.D(val_in[25]),
.Q(val_out[25]),
.R(1'b0));
FDRE \val_out_reg[26]
(.C(clk),
.CE(1'b1),
.D(val_in[26]),
.Q(val_out[26]),
.R(1'b0));
FDRE \val_out_reg[27]
(.C(clk),
.CE(1'b1),
.D(val_in[27]),
.Q(val_out[27]),
.R(1'b0));
FDRE \val_out_reg[28]
(.C(clk),
.CE(1'b1),
.D(val_in[28]),
.Q(val_out[28]),
.R(1'b0));
FDRE \val_out_reg[29]
(.C(clk),
.CE(1'b1),
.D(val_in[29]),
.Q(val_out[29]),
.R(1'b0));
FDRE \val_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(val_in[2]),
.Q(val_out[2]),
.R(1'b0));
FDRE \val_out_reg[30]
(.C(clk),
.CE(1'b1),
.D(val_in[30]),
.Q(val_out[30]),
.R(1'b0));
FDRE \val_out_reg[31]
(.C(clk),
.CE(1'b1),
.D(val_in[31]),
.Q(val_out[31]),
.R(1'b0));
FDRE \val_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(val_in[3]),
.Q(val_out[3]),
.R(1'b0));
FDRE \val_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(val_in[4]),
.Q(val_out[4]),
.R(1'b0));
FDRE \val_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(val_in[5]),
.Q(val_out[5]),
.R(1'b0));
FDRE \val_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(val_in[6]),
.Q(val_out[6]),
.R(1'b0));
FDRE \val_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(val_in[7]),
.Q(val_out[7]),
.R(1'b0));
FDRE \val_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(val_in[8]),
.Q(val_out[8]),
.R(1'b0));
FDRE \val_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(val_in[9]),
.Q(val_out[9]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_buffer_register_1_0,buffer_register,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "buffer_register,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_buffer_register_1_0
(clk,
val_in,
val_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [31:0]val_in;
output [31:0]val_out;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
system_buffer_register_1_0_buffer_register U0
(.clk(clk),
.val_in(val_in),
.val_out(val_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] i;
wire [255:0] q;
assign q = {
i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039],
i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048],
i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234],
i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122],
i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034],
i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174],
i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110],
i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183],
i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128],
i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139],
i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173],
i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142],
i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119],
i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035],
i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149],
i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144],
i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070],
i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017],
i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084],
i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118],
i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171],
i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112],
i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179],
i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002],
i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161],
i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151],
i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098],
i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013],
i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050],
i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219],
i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029],
i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093]
};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q, i);
`endif
if (cyc==1) begin
i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop;
end
if (cyc==3) begin
if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module ram0(
// Read port
input rdclk,
input [8:0] rdaddr,
output reg [63:0] do);
(* ram_style = "block" *) reg [63:0] ram[0:511];
genvar i;
generate
for (i=0; i<512; i=i+1)
begin
initial begin
ram[i] <= i | i << 16 | i << 32 | i << 48;
end
end
endgenerate
always @ (posedge rdclk) begin
do <= ram[rdaddr];
end
endmodule
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [8:0] read_address;
wire [63:0] read_data;
wire [8:0] rom_read_address;
reg [63:0] rom_read_data;
always @(posedge clk) rom_read_data <= {4{7'd0, rom_read_address}};
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [8:0] error_address;
wire [63:0] expected_data;
wire [63:0] actual_data;
ROM_TEST #(
.ADDR_WIDTH(9),
.DATA_WIDTH(64),
.ADDRESS_STEP(1),
.MAX_ADDRESS(511)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.read_address(read_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
) bram (
// Read port
.rdclk(clk),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(64),
.ADDR_WIDTH(9)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
#include <bits/stdc++.h> using std::sort; struct Edge { int v, w, next; } e[200002]; int ecnt, h[100002]; inline void add_edge(int u, int v, int w) { e[++ecnt] = {v, w, h[u]}; h[u] = ecnt; e[++ecnt] = {u, w, h[v]}; h[v] = ecnt; } int size[100002], dis1[100002], dis2[100002], dp[100002]; int L, W; int node[100002], cnt; bool vis[100002]; inline int max(int x, int y) { return x > y ? x : y; } void get_root(int u, int fa, int s, int &cur) { size[u] = 1, dp[u] = 0; for (int i = h[u]; i; i = e[i].next) if (!vis[e[i].v] && e[i].v != fa) get_root(e[i].v, u, s, cur), size[u] += size[e[i].v], dp[u] = max(dp[u], size[e[i].v]); dp[u] = max(dp[u], s - size[u]); if (dp[u] < dp[cur]) cur = u; } void fill(int u, int fa, int w) { size[u] = 1; dis1[u] = dis1[fa] + w; dis2[u] = dis2[fa] + 1; for (int i = h[u]; i; i = e[i].next) if (!vis[e[i].v] && e[i].v != fa) fill(e[i].v, u, e[i].w), size[u] += size[e[i].v]; } void get_node(int u, int fa) { node[++cnt] = u; for (int i = h[u]; i; i = e[i].next) if (!vis[e[i].v] && e[i].v != fa) get_node(e[i].v, u); } inline bool cmp(int u, int v) { return dis1[u] < dis1[v]; } int c[100002]; inline void add(int x, int v) { x++; for (; x <= 100000; x += ((x) & -(x))) c[x] += v; } inline int sum(int x) { x++; if (x <= 0) return 0; int ans = 0; for (; x > 0; x -= ((x) & -(x))) ans += c[x]; return ans; } long long Ans; inline long long solve() { long long ans = 0; sort(node + 1, node + cnt + 1, cmp); for (int i = 1; i <= cnt; i++) add(dis2[node[i]], 1); int j = cnt; for (int i = 1; i < j; i++) { while (i < j && dis1[node[i]] + dis1[node[j]] > W) add(dis2[node[j]], -1), j--; if (i >= j) break; add(dis2[node[i]], -1); ans += sum(L - dis2[node[i]]); } add(dis2[node[j]], -1); return ans; } inline void clear() { cnt = 0; } void dfs(int u) { dis1[u] = dis2[u] = 0; fill(u, 0, 0); for (int i = h[u]; i; i = e[i].next) if (!vis[e[i].v]) get_node(e[i].v, u), Ans -= solve(), clear(); get_node(u, 0), Ans += solve(), clear(); vis[u] = 1; for (int i = h[u]; i; i = e[i].next) if (!vis[e[i].v]) { int rt = 0; get_root(e[i].v, 0, size[e[i].v], rt); dfs(rt); } } int main() { int n, tu, tw; dp[0] = 114514; dis2[0] = -1; scanf( %d%d%d , &n, &L, &W); for (int i = 2; i <= n; i++) scanf( %d%d , &tu, &tw), add_edge(i, tu, tw); int rt = 0; get_root(1, 0, n, rt); dfs(rt); printf( %I64d , Ans); return 0; }
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#include <bits/stdc++.h> template <class T> T abs(T x) { return (x > 0) ? x : (-x); } template <class T> T ceil(T a, T b) { return a / b + (a % b != 0); } int n, t[125][5], cnt[5], l, r, mid; int a[6] = {1, 2, 4, 8, 16, 32}; std::set<int> s; int score(int x, int y) { int s = y / x, i; for (i = 0; i < 6 && s >= a[i]; ++i) ; return 500 * i; } bool cal(int m) { int x = 0, y = 0; for (int i = 0, j; i < 5; ++i) { if (t[0][i] >= 0 && t[1][i] < 0) x += score(cnt[i], n + m) / 250 * (250 - t[0][i]); else if (t[0][i] >= 0 && t[1][i] >= 0) { if (t[0][i] < t[1][i]) j = score(cnt[i], n + m); else j = score(cnt[i] + m, n + m); x += j / 250 * (250 - t[0][i]), y += j / 250 * (250 - t[1][i]); } else if (t[0][i] < 0 && t[1][i] >= 0) y += score(cnt[i], n + m) / 250 * (250 - t[1][i]); } return x > y; } int main() { scanf( %d n , &n); for (int i = 0; i < n; ++i) { for (int j = 0; j < 5; ++j) { scanf( %d , &t[i][j]); if (t[i][j] >= 0) ++cnt[j]; } } s.insert(0); s.insert(1000000007 + 1); for (int i = 0; i < 5; ++i) if (t[0][i] < 0 && t[1][i] >= 0) for (int j = 0; j < 6; ++j) s.insert(std::max(0, cnt[i] * a[j] - n)); for (std::set<int>::iterator it = s.begin(); it != s.end();) { for (l = *it, r = *(++it); l < r;) { mid = (l + r) >> 1; if (cal(mid)) r = mid; else l = mid + 1; } if (l < *it) break; } if (l <= 1000000007) printf( %d n , l); else printf( -1 n ); return 0; }
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:64000000 ) template <class T> inline T sqr(T x) { return x * x; } int n, k; int a[1 << 17]; map<int, int> d; set<pair<int, int> > s; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); for (int i = 0; i < k; ++i) ++d[a[i]]; for (int i = 0; i < k; ++i) s.insert(make_pair(d[a[i]], -a[i])); for (int i = 0; i + k - 1 < n; ++i) { if (s.begin()->first == 1) printf( %d n , -s.begin()->second); else puts( Nothing ); if (i + k == n) continue; pair<int, int> cur(d[a[i]], -a[i]); s.erase(cur); if (--d[a[i]] == 0) d.erase(a[i]); else { --cur.first; s.insert(cur); } cur = make_pair(d[a[i + k]], -a[i + k]); s.erase(cur); ++d[a[i + k]]; ++cur.first; s.insert(cur); } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> class fenwick_tree { private: int n; vector<T> fenw; public: fenwick_tree(int _n) : n(_n) { fenw.resize(n); } size_t size() { return n; } void update(int x, T val) { while (x < n) { fenw[x] += val; x |= (x + 1); } } void update(int x, int y, T val) { update(x, +val); update(y + 1, -val); } T query(int x) { T ans = 0; while (x >= 0) { ans += fenw[x]; x = (x & (x + 1)) - 1; } return ans; } }; struct station { int x, r, f; }; int n, k, cur = 0; vector<station> stations, sorted_stations; map<int, int> mp; fenwick_tree<int> fenw(0); long long solve(int l, int r) { if (l == r) { return 0; } int mid = (l + r) / 2; long long ans = solve(l, mid) + solve(mid + 1, r); int i = l, j = l; for (int t = mid + 1; t <= r; t++) { while (j <= mid && stations[j].f <= stations[t].f + k) { fenw.update(mp[stations[j].x - stations[j].r], mp[stations[j].x + stations[j].r], +1); j++; } while (i < j && stations[i].f < stations[t].f - k) { fenw.update(mp[stations[i].x - stations[i].r], mp[stations[i].x + stations[i].r], -1); i++; } ans += fenw.query(mp[stations[t].x]); } for (int t = i; t < j; t++) { fenw.update(mp[stations[t].x - stations[t].r], mp[stations[t].x + stations[t].r], -1); } int t = l; i = l; j = mid + 1; while (i <= mid || j <= r) { if (i > mid) { sorted_stations[t++] = stations[j++]; } else if (j > r) { sorted_stations[t++] = stations[i++]; } else if (stations[i].f < stations[j].f) { sorted_stations[t++] = stations[i++]; } else { sorted_stations[t++] = stations[j++]; } } for (int t = l; t <= r; t++) { stations[t] = sorted_stations[t]; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; set<int> st; for (int i = 0; i < n; i++) { int x, r, f; cin >> x >> r >> f; stations.push_back({x, r, f}); st.insert(x); st.insert(x - r); st.insert(x + r); } for (auto &x : st) { mp[x] = cur++; } sort(stations.begin(), stations.end(), [](const station &a, const station &b) { return a.r < b.r; }); sorted_stations.resize(n); fenw = fenwick_tree<int>(cur); cout << solve(0, n - 1) << n ; return 0; }
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`include "MU/Register.v" //`
module Register32(Bus_out,clk,reset,R_in,R_out,Bus_in);
input [31:0] Bus_in;
input clk,reset;
input R_in;
input R_out;
output [31:0] Bus_out;
reg [31:0] Temp_Bus_out;
Register R1(Bus_in[0],clk, reset,R_in, R_out, Bus_out[0]);
Register R2(Bus_in[1],clk, reset,R_in, R_out, Bus_out[1]);
Register R3(Bus_in[2],clk, reset,R_in, R_out, Bus_out[2]);
Register R4(Bus_in[3],clk, reset,R_in, R_out, Bus_out[3]);
Register R5(Bus_in[4],clk, reset,R_in, R_out, Bus_out[4]);
Register R6(Bus_in[5],clk, reset,R_in, R_out, Bus_out[5]);
Register R7(Bus_in[6],clk, reset,R_in, R_out, Bus_out[6]);
Register R8(Bus_in[7],clk, reset,R_in, R_out, Bus_out[7]);
Register R9(Bus_in[8],clk, reset,R_in, R_out, Bus_out[8]);
Register R10(Bus_in[9],clk, reset,R_in, R_out, Bus_out[9]);
Register R11(Bus_in[10],clk,reset,R_in, R_out, Bus_out[10]);
Register R12(Bus_in[11],clk,reset,R_in, R_out, Bus_out[11]);
Register R13(Bus_in[12],clk,reset,R_in, R_out, Bus_out[12]);
Register R14(Bus_in[13],clk,reset,R_in, R_out, Bus_out[13]);
Register R15(Bus_in[14],clk,reset,R_in, R_out, Bus_out[14]);
Register R16(Bus_in[15],clk,reset,R_in, R_out, Bus_out[15]);
Register R17(Bus_in[16],clk,reset,R_in, R_out, Bus_out[16]);
Register R18(Bus_in[17],clk,reset,R_in, R_out, Bus_out[17]);
Register R19(Bus_in[18],clk,reset,R_in, R_out, Bus_out[18]);
Register R20(Bus_in[19],clk,reset,R_in, R_out, Bus_out[19]);
Register R21(Bus_in[20],clk,reset,R_in, R_out, Bus_out[20]);
Register R22(Bus_in[21],clk,reset,R_in, R_out, Bus_out[21]);
Register R23(Bus_in[22],clk,reset,R_in, R_out, Bus_out[22]);
Register R24(Bus_in[23],clk,reset,R_in, R_out, Bus_out[23]);
Register R25(Bus_in[24],clk,reset,R_in, R_out, Bus_out[24]);
Register R26(Bus_in[25],clk,reset,R_in, R_out, Bus_out[25]);
Register R27(Bus_in[26],clk,reset,R_in, R_out, Bus_out[26]);
Register R28(Bus_in[27],clk,reset,R_in, R_out, Bus_out[27]);
Register R29(Bus_in[28],clk,reset,R_in, R_out, Bus_out[28]);
Register R30(Bus_in[29],clk,reset,R_in, R_out, Bus_out[29]);
Register R31(Bus_in[30],clk,reset,R_in, R_out, Bus_out[30]);
Register R32(Bus_in[31],clk,reset,R_in, R_out, Bus_out[31]);
endmodule
/*
module RegisterTest;
Register32 r1(Bus_out, clk, reset, r_in, r_out, Bus_in);
reg [31: 0] Bus_in;
reg clk, reset, r_in, r_out;
output [31: 0] Bus_out;
initial
begin
$display("\t\t %5s | %5s | %5s |----| %5s | %5s |", "RESET", "RIN", "ROUT", "BUSIN", "BOUT");
$monitor($time, ": %5d | %5d | %5d |----| %5d | %5d |", reset, r_in, r_out, Bus_in, Bus_out);
reset = 1; clk = 1;
#10 r_in = 0; r_out = 0; Bus_in = 32'd21; reset = 0; //No Stroring and no retrieval'
#10 r_in = 1; r_out = 0; Bus_in = 32'd21; //Storing But no Retreival'
#10 r_in = 0; r_out = 1; Bus_in = 32'd21; //No Storing But Retrieval'
#10 r_in = 1; r_out = 1; Bus_in = 32'd9; //Storing and Retreival'
$finish();
end
always
begin: CLOCKGEN
#5 clk = ~clk;
end
endmodule
*/
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#include <bits/stdc++.h> using namespace std; int main() { int n = 0, m = 0, temp = 0; cin >> n >> m; int arr[n + 1]; fill(arr, arr + n + 1, -1); for (int i = 1; i <= m; i++) { cin >> temp; int k = temp; while (k <= n && arr[k] == -1) { arr[k] = temp; k++; } } for (int j = 1; j <= n; j++) cout << arr[j] << ; return 0; }
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#include <bits/stdc++.h> using namespace std; char a[300099]; char ans[300099]; int c[200000]; int b; int main() { while (~scanf( %s , a)) { memset(c, 0, sizeof(c)); scanf( %d , &b); int len = strlen(a); for (int i = 0; i < b; i++) { int pt; scanf( %d , &pt); pt--; c[pt]++; } for (int i = 0; i < len / 2; i++) { if (i == 0) { if (c[i] % 2) ans[i] = a[len - 1 - i], ans[len - 1 - i] = a[i]; else ans[i] = a[i], ans[len - 1 - i] = a[len - 1 - i]; } else { c[i] += c[i - 1]; if (c[i] % 2) ans[i] = a[len - 1 - i], ans[len - 1 - i] = a[i]; else ans[i] = a[i], ans[len - 1 - i] = a[len - 1 - i]; } } if (len % 2) ans[len / 2] = a[len / 2]; ans[len] = 0 ; printf( %s n , ans); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 9e2 + 1; int n, m, g[maxn], G, o1[maxn], o2[maxn], deg[maxn]; vector<int> e[maxn], e_s[maxn], r_e_s[maxn], topo, ans, wow[maxn]; vector<pair<int, int> > edge, res; bool mark[maxn]; map<int, int> is[maxn]; void dfs(int v) { mark[v] = 1; for (auto u : e[v]) { if (is[v][u] == 0) { e_s[v].push_back(u); r_e_s[u].push_back(v); is[v][u] = 1; is[u][v] = 1; } if (mark[u] == 0) { dfs(u); } } } void topol(int v) { mark[v] = 1; for (auto u : e_s[v]) { if (mark[u] == 0) { topol(u); } } topo.push_back(v); } void col(int v) { mark[v] = 1; g[v] = G; o2[G] = v; for (auto u : r_e_s[v]) { if (mark[u] == 0) { col(u); } } return; } void Last_one(int v) { mark[v] = 1; for (auto u : wow[v]) { if (mark[u] == 0) { Last_one(u); } } if (deg[v] == 1) { ans.push_back(v); } return; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; if (n == 2) { cout << -1 << endl; return 0; } for (int i = 0; i < m; i++) { int t1, t2; cin >> t1 >> t2; e[t1].push_back(t2); e[t2].push_back(t1); edge.push_back({t1, t2}); } dfs(1); for (int i = 1; i <= n; i++) { mark[i] = 0; } topol(1); for (int i = 1; i <= n; i++) { mark[i] = 0; } reverse(topo.begin(), topo.end()); G = 1; for (auto u : topo) { if (mark[u] == 0) { o1[G] = u; col(u); G++; } } for (auto tmp : edge) { if (g[tmp.first] != g[tmp.second]) { deg[g[tmp.first]]++; deg[g[tmp.second]]++; wow[g[tmp.first]].push_back(g[tmp.second]); wow[g[tmp.second]].push_back(g[tmp.first]); } } if (G == 3) { ans.push_back(1); ans.push_back(2); } else { for (int i = 1; i <= n; i++) { mark[i] = 0; } for (int i = 1; i < G; i++) { if (deg[i] >= 2) { Last_one(i); break; } } } for (int i = 0; i < ((int)ans.size() + 1) / 2; i++) { int t1 = ans[i]; int t2 = ans[i + (ans.size()) / 2]; if (is[o1[t1]][o1[t2]] == 0) { res.push_back({o1[t1], o1[t2]}); } else { res.push_back({o2[t1], o2[t2]}); } } cout << res.size() << endl; for (auto u : res) { cout << u.first << << u.second << endl; } return 0; }
|
// $File: //acds/rel/14.1/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_dcfifo_synchronizer_bundle(
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin : sync
altera_std_synchronizer_nocut #(.depth(DEPTH))
u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
|
module rx_sm #(
parameter STATE_IDLE = 3'h0,
parameter STATE_PREAMBLE = 3'h1,
parameter STATE_DATA = 3'h2,
parameter STATE_OK = 3'h3,
parameter STATE_DROP = 3'h4,
parameter STATE_ERROR = 3'h5,
parameter FIFO_DEPTH = 12
)(
input reset,
input clock,
input rx_data_valid,
input [7:0] rx_data,
input rx_error,
// OUT PORT
output wire [7:0] data_out,
input wire data_out_clock,
input wire data_out_enable,
output wire data_out_start,
output wire data_out_end,
output wire [FIFO_DEPTH-1:0] data_out_address,
input wire data_out_reset,
input wire [FIFO_DEPTH-1:0] data_out_reset_address,
output reg data_available,
output wire fifo_full
);
localparam CRC_RESIDUE = 32'hC704DD7B;
localparam CRC_POLYNOMIAL = 32'h04C11DB7;
localparam CRC_SEED = 32'hFFFFFFFF;
localparam MAX_SIZE = 1518;
localparam MIN_SIZE = 64;
wire [FIFO_DEPTH:0] fifo_count;
wire [FIFO_DEPTH-1:0] data_in_address;
reg [FIFO_DEPTH-1:0] data_in_reset_address;
reg start_of_frame;
reg end_of_frame;
reg error;
reg [2:0] state;
reg [2:0] next_state;
reg [15:0] frame_length_counter;
reg [15:0] data_counter;
reg data_write_enable;
reg too_long;
reg too_short;
reg crc_init;
reg data_enable;
wire [31:0] crc_out;
reg [39:0] data;
// RX State Machine
always @ (posedge reset or posedge clock)
if (reset)
state <= STATE_IDLE;
else
state <= next_state;
always @ (*)
case (state)
STATE_IDLE:
if (rx_data_valid && rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_IDLE;
STATE_PREAMBLE:
if (!rx_data_valid)
next_state = STATE_ERROR;
else if (rx_error)
next_state = STATE_DROP;
else if (rx_data == 8'hd5)
next_state = STATE_DATA;
else if (rx_data == 8'h55)
next_state = STATE_PREAMBLE;
else
next_state = STATE_DROP;
STATE_DATA:
if (!rx_data_valid && !too_short && !too_long && crc_out == CRC_RESIDUE)
next_state = STATE_OK;
else if ((!rx_data_valid && (too_short || too_long)) || (!rx_data_valid && crc_out != CRC_RESIDUE))
next_state = STATE_ERROR;
else if (fifo_full)
next_state = STATE_DROP;
else if (rx_error || too_long)
next_state = STATE_DROP;
else
next_state = STATE_DATA;
STATE_DROP:
if (!rx_data_valid)
next_state = STATE_ERROR;
else
next_state = STATE_DROP;
STATE_OK:
next_state = STATE_IDLE;
STATE_ERROR:
next_state = STATE_IDLE;
default:
next_state = STATE_IDLE;
endcase
always @(posedge clock or posedge reset)
begin
if (reset)
begin
data <= 32'h00000000;
end
else if (state == STATE_IDLE)
begin
data <= 32'h00000000;
end
else
begin
data[39-:8] <= data[31-:8];
data[31-:8] <= data[23-:8];
data[23-:8] <= data[15-:8];
data[15-:8] <= data[7-:8];
data[7-:8] <= rx_data;
end
end
always @ ( state or fifo_count )
begin
if (fifo_count && state == STATE_OK)
begin
data_available <= 1;
end
else if (!fifo_count)
begin
data_available <= 0;
end
end
always @ (posedge clock or posedge reset)
if (reset)
data_counter <= 0;
else if (state == STATE_DATA)
data_counter = data_counter + 1;
else
data_counter = 0;
always @ (data_counter or state)
if (data_counter > 4 && state == STATE_DATA && next_state == STATE_DATA)
data_write_enable = 1;
else
data_write_enable = 0;
always @(data_counter)
if (data_counter == 5)
start_of_frame = 1;
else
start_of_frame = 0;
always @(state or next_state)
if (state == STATE_DATA && next_state != STATE_DATA)
end_of_frame = 1;
else
end_of_frame = 0;
always @(state)
if (state == STATE_ERROR)
error = 1;
else
error = 0;
// CRC Interface
always @(state)
if (state == STATE_DATA)
data_enable = 1;
else
data_enable = 0;
always @(state or next_state)
if (state == STATE_PREAMBLE && next_state == STATE_DATA)
begin
crc_init <= 1;
data_in_reset_address <= data_in_address;
end
else
crc_init = 0;
always @ (posedge clock or posedge reset)
if (reset)
frame_length_counter <= 0;
else if (state == STATE_DATA)
frame_length_counter = frame_length_counter + 1;
else
frame_length_counter = 0;
always @ (frame_length_counter)
if (frame_length_counter < MIN_SIZE)
too_short = 1;
else
too_short = 0;
always @ (frame_length_counter)
if (frame_length_counter > MAX_SIZE)
too_long = 1;
else
too_long = 0;
// CRC
crc #( .POLYNOMIAL(CRC_POLYNOMIAL),
.DATA_WIDTH(8),
.CRC_WIDTH(32),
.SEED(CRC_SEED))
U_crc(
.reset(reset),
.clock(clock),
.init(crc_init),
.data(rx_data),
.data_enable(data_enable),
.crc_out(crc_out)
);
// FIFO
fifo #(
.DATA_WIDTH (8),
.FIFO_DEPTH (FIFO_DEPTH)
)
U_fifo (
.reset(reset),
.count(fifo_count),
.full(fifo_full),
// IN PORT
.data_in(data[39-:8]),
.data_in_start(start_of_frame),
.data_in_end(end_of_frame),
.data_in_clock(clock),
.data_in_enable(data_write_enable),
.data_in_address(data_in_address),
.data_in_reset(error),
.data_in_reset_address(data_in_reset_address),
// OUT PORT
.data_out(data_out),
.data_out_start(data_out_start),
.data_out_end(data_out_end),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_address(data_out_address),
.data_out_reset(data_out_reset),
.data_out_reset_address(data_out_reset_address)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, S, L, A[100009]; int c[100009], dp[100009]; deque<pair<int, int>> s, t, u; int main() { scanf( %d%d%d , &N, &S, &L); for (int i = 1; i <= N; i++) dp[i] = 1e6; for (int i = 1, ptr = 1; i <= N; i++) { scanf( %d , &A[i]); while (s.size() && s.back().first >= A[i]) s.pop_back(); s.push_back({A[i], i}); while (t.size() && t.back().first <= A[i]) t.pop_back(); t.push_back({A[i], i}); while (ptr < i && t.front().first - s.front().first > S) { ptr++; while (s.front().second < ptr) s.pop_front(); while (t.front().second < ptr) t.pop_front(); } c[i] = ptr - 1; } for (int i = 1; i <= N; i++) c[i] = min(c[i], i - L + 1); for (int i = 1, ptr = 0; i <= N; i++) { if (i >= L) { while (u.size() && u.back().first >= dp[i - L]) u.pop_back(); u.push_back({dp[i - L], i - L}); } for (; ptr < c[i]; ptr++) { while (u.size() && u.front().second <= ptr) u.pop_front(); } if (u.size()) dp[i] = u.front().first + 1; } printf( %d n , dp[N] >= 1e6 ? -1 : dp[N]); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:37:11 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_stub.v
// Design : design_1_axi_intc_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_intc,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, irq)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[0:0],irq" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [0:0]intr;
output irq;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool notis[30] = {false}, mayis[30] = {false}; string str; int main() { int n, flag = 0, cnt = 0, tem, i, j; char p; std::ios::sync_with_stdio(false); cin >> n; for (i = 0; i < n; i++) { cin >> p >> str; if (flag && (p == ! || p == ? )) cnt++; else { tem = str.length(); if (p == ! ) { for (j = 0; j < tem; j++) mayis[str[j] - a ] = true; for (j = 0; j < 26; j++) { if (!mayis[j]) notis[j] = true; mayis[j] = false; } } else for (j = 0; j < tem; j++) notis[str[j] - a ] = true; for (tem = j = 0; j < 26; j++) if (!notis[j]) tem++; if (tem == 1) flag = 1; } } printf( %d , cnt > 0 ? (cnt - 1) : 0); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_3_V
`define SKY130_FD_SC_HDLL__DECAP_3_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 3 units (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_3 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_3 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_3_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int n; cin >> n; vector<int> dem(1000); int maxx = INT_MIN; for (int i = 0; i < n; ++i) { int u; cin >> u; dem[--u]++; maxx = max(maxx, dem[u]); } if (n - maxx < maxx - 1) cout << NO ; else cout << YES ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_TB_V
`define SKY130_FD_SC_LS__O22AI_TB_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_ls__o22ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_TB_V
|
#include <bits/stdc++.h> using namespace std; long long a[101][101]; long long b[101]; int main() { int m, n; cin >> m >> n; for (int i = 0; i < m; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; for (int i = 0; i < m; i++) { long long minn = 100000000000000; for (int j = 0; j < n; j++) { if (a[i][j] < minn) minn = a[i][j]; } b[i] = minn; } long long maxx = 0; for (int i = 0; i < m; i++) { if (b[i] > maxx) maxx = b[i]; } cout << maxx; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline const int getint() { int r = 0, k = 1; char c = getchar(); for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) k = -1; for (; c >= 0 && c <= 9 ; c = getchar()) r = r * 10 + c - 0 ; return k * r; } long long ans, a1, b1, a2, b2, t1, t2; int main() { cin >> a1 >> b1 >> a2 >> b2; long long a = a1 * b1, b = a2 * b2; while (a % 3 == 0) ++t1, a /= 3; while (b % 3 == 0) ++t2, b /= 3; ans += abs(t1 - t2); while (t1 > t2 && a1 % 3 == 0) a1 -= a1 / 3, --t1; while (t1 > t2 && b1 % 3 == 0) b1 -= b1 / 3, --t1; while (t1 < t2 && a2 % 3 == 0) a2 -= a2 / 3, --t2; while (t1 < t2 && b2 % 3 == 0) b2 -= b2 / 3, --t2; a = a1 * b1, b = a2 * b2; t1 = t2 = 0; while (a % 2 == 0) ++t1, a /= 2; while (b % 2 == 0) ++t2, b /= 2; ans += abs(t1 - t2); while (t1 > t2 && a1 % 2 == 0) a1 -= a1 / 2, --t1; while (t1 > t2 && b1 % 2 == 0) b1 -= b1 / 2, --t1; while (t1 < t2 && a2 % 2 == 0) a2 -= a2 / 2, --t2; while (t1 < t2 && b2 % 2 == 0) b2 -= b2 / 2, --t2; if (a1 * b1 != a2 * b2) { puts( -1 ); return 0; } cout << ans << endl << a1 << << b1 << endl << a2 << << b2; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; void solve() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (auto i : a) { cout << i << ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); { solve(); } return 0; }
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="pointer_basic,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=211,HLS_SYN_LUT=228,HLS_VERSION=2018_2}" *)
module pointer_basic (
ap_clk,
ap_rst_n,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP,
interrupt
);
parameter ap_ST_fsm_state1 = 3'd1;
parameter ap_ST_fsm_state2 = 3'd2;
parameter ap_ST_fsm_state3 = 3'd4;
parameter C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH = 32;
parameter C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH = 5;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
input s_axi_pointer_basic_io_AWVALID;
output s_axi_pointer_basic_io_AWREADY;
input [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_AWADDR;
input s_axi_pointer_basic_io_WVALID;
output s_axi_pointer_basic_io_WREADY;
input [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_WDATA;
input [C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH - 1:0] s_axi_pointer_basic_io_WSTRB;
input s_axi_pointer_basic_io_ARVALID;
output s_axi_pointer_basic_io_ARREADY;
input [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_ARADDR;
output s_axi_pointer_basic_io_RVALID;
input s_axi_pointer_basic_io_RREADY;
output [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_RDATA;
output [1:0] s_axi_pointer_basic_io_RRESP;
output s_axi_pointer_basic_io_BVALID;
input s_axi_pointer_basic_io_BREADY;
output [1:0] s_axi_pointer_basic_io_BRESP;
output interrupt;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_ready;
wire [31:0] d_i;
reg d_o_ap_vld;
reg [31:0] acc;
reg [31:0] d_read_reg_52;
wire [31:0] acc_assign_fu_41_p2;
reg [31:0] acc_assign_reg_57;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_state3;
reg [2:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 3'd1;
#0 acc = 32'd0;
end
pointer_basic_pointer_basic_io_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH ))
pointer_basic_pointer_basic_io_s_axi_U(
.AWVALID(s_axi_pointer_basic_io_AWVALID),
.AWREADY(s_axi_pointer_basic_io_AWREADY),
.AWADDR(s_axi_pointer_basic_io_AWADDR),
.WVALID(s_axi_pointer_basic_io_WVALID),
.WREADY(s_axi_pointer_basic_io_WREADY),
.WDATA(s_axi_pointer_basic_io_WDATA),
.WSTRB(s_axi_pointer_basic_io_WSTRB),
.ARVALID(s_axi_pointer_basic_io_ARVALID),
.ARREADY(s_axi_pointer_basic_io_ARREADY),
.ARADDR(s_axi_pointer_basic_io_ARADDR),
.RVALID(s_axi_pointer_basic_io_RVALID),
.RREADY(s_axi_pointer_basic_io_RREADY),
.RDATA(s_axi_pointer_basic_io_RDATA),
.RRESP(s_axi_pointer_basic_io_RRESP),
.BVALID(s_axi_pointer_basic_io_BVALID),
.BREADY(s_axi_pointer_basic_io_BREADY),
.BRESP(s_axi_pointer_basic_io_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle),
.d_o(acc_assign_reg_57),
.d_o_ap_vld(d_o_ap_vld),
.d_i(d_i)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
acc <= acc_assign_fu_41_p2;
acc_assign_reg_57 <= acc_assign_fu_41_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
d_read_reg_52 <= d_i;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_ap_vld = 1'b1;
end else begin
d_o_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign acc_assign_fu_41_p2 = (acc + d_read_reg_52);
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
endmodule //pointer_basic
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 1; const int MOD = 1e9 + 7; class Problem { public: int N, Q, t, k, d; char ch; string S; void solve(std::istream& input, std::ostream& output); }; void Problem::solve(std::istream& input, std::ostream& output) { input >> N; for (int i = sqrt(N); i >= 1; i--) { if (N % i == 0) { output << i << << N / i; exit(0); } } } int main() { ios_base::sync_with_stdio(false); std::istream& input(std::cin); std::ostream& output(std::cout); input.tie(0); Problem _A; _A.solve(input, output); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_FUNCTIONAL_PP_V
|
`define OVL_ASSERT_ON
`define OVL_INIT_MSG
`include "assert_always.vlib"
module four_phase_assertion(/*AUTOARG*/
// Inputs
req, ack, rstn
);
input req;
input ack;
input rstn;
assert_always #(
`OVL_ERROR , // severity_level
`OVL_ASSERT , // property_type
"ack_is_zero_when_posedge_req", // msg
`OVL_COVER_NONE // coverage_level
) A1 (
.clk (req),
.reset_n (rstn),
.test_expr (!ack)
);
assert_always #(
`OVL_ERROR , // severity_level
`OVL_ASSERT , // property_type
"ack_is_one_when_negedge_req", // msg
`OVL_COVER_NONE // coverage_level
) A2 (
.clk (~req),
.reset_n (rstn),
.test_expr (ack)
);
assert_always #(
`OVL_ERROR , // severity_level
`OVL_ASSERT , // property_type
"req_is_one_when_posedge_ack", // msg
`OVL_COVER_NONE // coverage_level
) A3 (
.clk (ack),
.reset_n (rstn),
.test_expr (req)
);
assert_always #(
`OVL_ERROR , // severity_level
`OVL_ASSERT , // property_type
"req_is_zero_when_negedge_ack", // msg
`OVL_COVER_NONE // coverage_level
) A4 (
.clk (~ack),
.reset_n (rstn),
.test_expr (~req)
);
endmodule // four_phase_asssertion
|
#include <bits/stdc++.h> using namespace std; int a, b, maxa; void use_battery(int s) { if (s == 1) a = min(a + 1, maxa); --b; } void use_accum() { --a; } int main() { int ans = 0; int n; cin >> n >> b >> a; maxa = a; vector<int> s(n); for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) { if (a == 0 && b == 0) break; else if (a == 0) use_battery(s[i]); else if (b == 0) use_accum(); else if (s[i] == 1 && a < maxa) use_battery(s[i]); else use_accum(); ans++; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; double tick() { static clock_t oldt, newt = clock(); double diff = 1.0 * (newt - oldt) / CLOCKS_PER_SEC; oldt = newt; return diff; } inline long long int read() { long long int f = 1, x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } long long int fastExpo(long long int a, long long int n) { long long int res = 1; while (n) { if (n % 2) res = res * a; n /= 2; a = a * a; } return res; } int dx[] = {-1, 0, 1, 0}; int dy[] = {0, 1, 0, -1}; vector<int> v[200010]; int col[200010]; vector<int> l, r; void dfs(int n, int c) { col[n] = c; for (int j : v[n]) { if (col[j] == -1) dfs(j, 1 - c); } } int main() { int t = read(); while (t--) { int n = read(), m = read(); while (m--) { int a, b; cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } for (int i = 1; i <= n; i++) col[i] = -1; dfs(1, 0); long long int c1 = 0, c2 = 0; for (int i = 1; i <= n; i++) { if (col[i]) c1++; else c2++; } if (c1 <= n / 2) { cout << c1 << endl; for (int i = 1; i <= n; i++) if (col[i]) cout << i << ; } else { cout << c2 << endl; for (int i = 1; i <= n; i++) if (!col[i]) cout << i << ; } cout << endl; for (int i = 1; i <= n; i++) v[i].clear(), col[i] = -1; } cerr << execution time is: << tick() << n ; }
|
#include <bits/stdc++.h> using namespace std; int a[101]; int main() { bool f = false; int n, counter = 1; long long ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 0 && f) counter++; if (a[i] == 1 && !f) f = true, ans = 1; else if (a[i] == 1 && f) ans *= counter, counter = 1; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, c, p, y, k, x, h, t, q; string s; vector<long long> v; map<long long, long long> ma; void input() {} struct node { map<string, node*> child; map<string, long long> ispresent; string name; bool isfile = 0; }; pair<long long, long long> dfs(node* root) { pair<long long, long long> p = {0, 0}; if (root->isfile == 1) { p = {0, 1}; return p; } pair<long long, long long> res = {0, 0}; for (auto i : root->child) { p = dfs(i.second); res.first += p.first; res.second += p.second; } res.first++; return res; } void solve() { string s; map<char, node*> roots; roots[ C ] = new node(); roots[ D ] = new node(); roots[ E ] = new node(); roots[ F ] = new node(); roots[ G ] = new node(); while (cin >> s) { long long n = s.size(); char disk = s[0]; node* temp = roots[disk]; for (long long i = 3; i < n; i++) { long long j; string names = ; bool file = 0; for (j = i; s[j] != && j < n; j++) { names += s[j]; if (s[j] == . ) file = 1; } i = j; if (temp->ispresent[names] != 0) { temp = temp->child[names]; } else { node* newnode = new node(); if (file == 1) { newnode->isfile = true; } newnode->name = names; temp->child[names] = newnode; temp->ispresent[names]++; temp = temp->child[names]; } } } long long maxfiles = 0; long long maxfolder = 0; for (auto i : roots[ C ]->child) { pair<long long, long long> p = dfs(i.second); maxfolder = max(maxfolder, p.first); maxfiles = max(maxfiles, p.second); } for (auto i : roots[ D ]->child) { pair<long long, long long> p = dfs(i.second); maxfolder = max(maxfolder, p.first); maxfiles = max(maxfiles, p.second); } for (auto i : roots[ E ]->child) { pair<long long, long long> p = dfs(i.second); maxfolder = max(maxfolder, p.first); maxfiles = max(maxfiles, p.second); } for (auto i : roots[ F ]->child) { pair<long long, long long> p = dfs(i.second); maxfolder = max(maxfolder, p.first); maxfiles = max(maxfiles, p.second); } for (auto i : roots[ G ]->child) { pair<long long, long long> p = dfs(i.second); maxfolder = max(maxfolder, p.first); maxfiles = max(maxfiles, p.second); } cout << maxfolder - 1 << << maxfiles; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long T = 1; while (T--) { input(); solve(); } }
|
#include <bits/stdc++.h> using namespace std; long long arr[200005]; long long n; map<long long, long long> ans; bool debug = false; long long rec(long long node) { if (debug) cout << entering << node << endl; if (node == 1) return 1000000000000; if (node <= 0 || node > n) return 0; if (ans.count(node) && ans[node] == -1000000000000) return ans[node] = 1000000000000; if (ans.count(node)) { if (debug) cout << already computed for << node << endl; return ans[node]; } ans[node] = -1000000000000; long long val = 0; long long n1 = node + arr[node]; val += arr[node]; if (n1 <= 0 || n1 > n) return ans[node] = val; long long n2 = n1 - arr[n1]; val += arr[n1]; return ans[node] = val + rec(n2); } int main() { scanf( %lld , &n); for (__typeof(n - 1) i = 0; i < n - 1; i++) scanf( %lld , &arr[i + 2]); long long k; for (__typeof(n) i = 2; i <= n; i++) { long long val = i - 1; long long nex = i - arr[i]; val += arr[i]; k = rec(nex) + val; if (k >= 1000000000000) cout << -1 << endl; else cout << k << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_4_V
`define SKY130_FD_SC_HDLL__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_4_V
|
#include <bits/stdc++.h> using namespace std; class Solution { public: void solve(std::istream& in, std::ostream& out) { int T; in >> T; for (int _t = 0; _t < (int)(T); ++_t) { int n, s, t; in >> n >> s >> t; int res = n - min(s, t) + 1; out << res << endl; } } }; void solve(std::istream& in, std::ostream& out) { out << std::setprecision(12); Solution solution; solution.solve(in, out); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); istream& in = cin; ostream& out = cout; solve(in, out); return 0; }
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; const int maxn=200010; int a[maxn],f[maxn]; int main(){ ios::sync_with_stdio(false); cin.tie(nullptr); int t,n; cin>>t; while(t--){ memset(f,0,sizeof(f)); cin>>n; for(int i=0;i<n;i++)cin>>a[i]; sort(a,a+n); f[a[0]]=1; for(int i=1;i<n;i++){ for(int j=1;j*j<=a[i];j++){ if(a[i]%j)continue; f[a[i]]=max({f[a[i]],f[j]+1,f[a[i]/j]+1}); } } int ans=0; for(int i=1;i<=200000;i++)ans=max(ans,f[i]); cout<<n-ans<< n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { cout << fixed; double d, L, v1, v2; cin >> d >> L >> v1 >> v2; cout << setprecision(8) << (L - d) / (v1 + v2) << endl; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2017 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] in = crc[3:0];
wire clken = crc[4];
wire rstn = !(cyc < 20 || (crc[11:8]==0));
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ff_out; // From test of Test.v
wire [3:0] fg_out; // From test of Test.v
wire [3:0] fh_out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_out (ff_out[3:0]),
.fg_out (fg_out[3:0]),
.fh_out (fh_out[3:0]),
// Inputs
.clk (clk),
.clken (clken),
.rstn (rstn),
.in (in[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, ff_out, fg_out, fh_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h77979747fd1b3a5a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(/*AUTOARG*/
// Outputs
ff_out, fg_out, fh_out,
// Inputs
clk, clken, rstn, in
);
input clk;
input clken;
input rstn;
input [3:0] in;
output reg [3:0] ff_out;
reg [3:0] ff_10;
reg [3:0] ff_11;
reg [3:0] ff_12;
reg [3:0] ff_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
ff_10 <= 0;
ff_11 <= 0;
ff_12 <= 0;
ff_13 <= 0;
end
else begin
ff_10 <= in;
ff_11 <= ff_10;
ff_12 <= ff_11;
ff_13 <= ff_12;
ff_out <= ff_13;
end
end
output reg [3:0] fg_out;
reg [3:0] fg_10;
reg [3:0] fg_11;
reg [3:0] fg_12;
reg [3:0] fg_13;
always @(posedge clk) begin
if (clken) begin
if ((rstn == 0)) begin
fg_10 <= 0;
fg_11 <= 0;
fg_12 <= 0;
fg_13 <= 0;
end
else begin
fg_10 <= in;
fg_11 <= fg_10;
fg_12 <= fg_11;
fg_13 <= fg_12;
fg_out <= fg_13;
end
end
end
output reg [3:0] fh_out;
reg [3:0] fh_10;
reg [3:0] fh_11;
reg [3:0] fh_12;
reg [3:0] fh_13;
always @(posedge clk) begin
if ((rstn == 0)) begin
fh_10 <= 0;
fh_11 <= 0;
fh_12 <= 0;
fh_13 <= 0;
end
else begin
if (clken) begin
fh_10 <= in;
fh_11 <= fh_10;
fh_12 <= fh_11;
fh_13[3:1] <= fh_12[3:1];
fh_13[0] <= fh_12[0];
fh_out <= fh_13;
end
end
end
endmodule
|
module RegisterFile(Read1, Read2, Writedata, Raddr1, Raddr2, Waddr, RegWr, CLK, RESET);
output [31:0] Read1;
output [31:0] Read2;
input [31:0] Writedata;
input [4:0] Raddr1, Raddr2, Waddr;
input RegWr, CLK, RESET;
reg [31:0] registers [0:31];
always @(posedge RESET)
begin
registers[0]=0;
registers[1]=0;
registers[2]=0;
registers[3]=0;
registers[4]=0;
registers[5]=0;
registers[6]=0;
registers[7]=0;
registers[8]=0;
registers[9]=0;
registers[10]=0;
registers[11]=0;
registers[12]=0;
registers[13]=0;
registers[14]=0;
registers[15]=0;
registers[16]=0;
registers[17]=0;
registers[18]=0;
registers[19]=0;
registers[20]=0;
registers[21]=0;
registers[22]=0;
registers[23]=0;
registers[24]=0;
registers[25]=0;
registers[26]=0;
registers[27]=0;
registers[28]=0;
registers[29]=0;
registers[30]=0;
registers[31]=0;
end
assign Read1 =registers[Raddr1];
assign Read2 =registers[Raddr2];
always @(negedge CLK)
begin
if(RegWr==1)
begin
registers[Waddr] = Writedata;
$display("----------------------------------\nREGWRITE Reg %d current %d new %d\n----------------------------------" ,Waddr, registers[Waddr], Writedata );
end
end
/*
always @ (CLK)
begin
$display("----------------------------------------------\n");
$display("time %0d\t \n", $time);
$display("Reg10 %d " ,registers[10] );
$display("Reg11 %d " ,registers[11] );
$display("Reg12 %d " ,registers[12] );
$display("Reg13 %d " ,registers[13] );
$display("Reg14 %d " ,registers[14] );
$display("Reg15 %d " ,registers[15] );
$display("Reg16 %d " ,registers[16] );
end
*/
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// just DOS signal control
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zdos(
input wire fclk,
input wire rst_n,
input wire dos_turn_on,
input wire dos_turn_off,
input wire cpm_n,
output reg dos
);
always @(posedge fclk, negedge rst_n)
if( !rst_n )
begin
dos = 1'b1;
end
else // posedge fclk
begin
if( !cpm_n )
dos <= 1'b1;
else if( dos_turn_off )
dos <= 1'b0;
else if( dos_turn_on )
dos <= 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[100010], ans; bool vis[100010]; bool c[100010]; void find(int v) { vis[v] = true; bool del = true; for (int u : adj[v]) { del &= c[u]; if (!vis[u]) find(u); } if (c[v] && del) ans.push_back(v); } int main() { int n; cin >> n; int root; for (int i = 1; i <= n; i++) { int p; cin >> p >> c[i]; if (p != -1) adj[p].push_back(i); else root = i; } find(root); sort(ans.begin(), ans.end()); if (ans.empty()) cout << -1 ; for (int v : ans) cout << v << ; cout << endl; return 0; }
|
// date:2016/3/16
// engineer:ZhaiShaoMin
// project:multicore ring based project
// module function: testbench for ic_download
`timescale 1ns/1ps
//`include "constants.v"
module tb_ic_download();
//inputs
reg clk;
reg rst;
reg [15:0] rep_flit_ic;
reg v_rep_flit_ic;
reg [1:0] rep_ctrl_ic;
reg [127:0] mem_flits_ic;
reg v_mem_flits_ic;
//outputs
wire ic_download_state;
wire inst_word_ic;
wire v_inst_word;
//instantiate the uut
ic_download uut(//input
.clk(clk),
.rst(rst),
.rep_flit_ic(rep_flit_ic),
.v_rep_flit_ic(v_rep_flit_ic),
.rep_ctrl_ic(rep_ctrl_ic),
.mem_flits_ic(mem_flits_ic),
.v_mem_flits_ic(v_mem_flits_ic),
//output
.ic_download_state(ic_download_state),
.inst_word_ic(inst_word_ic),
.v_inst_word(v_inst_word)
);
integer i,j;
integer log_file;
// Initialize Inputs
initial begin
clk = 0;
rst = 0;
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b0;
rep_ctrl_ic=2'b00;
mem_flits_ic=128'h12345678123456781234567812345678;
v_mem_flits_ic=1'b0;
end
always #20 clk=~clk;
`define step #40;
initial begin
/////// ic_download test /////////
// First reset all //
$display("(%t) Initializing...", $time);
$fdisplay(log_file, "(%t) Initializing...", $time);
rst=1;
`step
rst=0;
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////REP MSG FROM LOCAL MEM/////////////////////////////////////////////////////////////
//here we assume that m_i_areg send a rep msg to test datapath from mem to inst cache
mem_flits_ic=128'h12345678123456781234567812345678;
v_mem_flits_ic=1'b1;
`step
$display("(%t)inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t) inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
`step
`step
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////REP MSG FROM IN_REP_FIFO//////////////////////////////////////////////////////////////////////
//after a few cycles ,another rep msg from IN_local_rep fifo come and ic_download should be ready to receive the flits
// note : because head flit of inst_rep is useless for inst cache ,first flit will be droped by ic_download
//first flit
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b01;
//note :the 2nd to 9th are the flits which includes actual inst word betys
`step
// second flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
`step
// 3rd flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
`step
// 4th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
// JUST a test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
$display("(%t)just test ERROR:inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t)just test ERROR: inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
`step
// 5th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
`step
// 6th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
// just test that whether ic_download only output inst word to inst cache when it has receiverd all flits taht required!
`step
// 7th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
`step
// 8th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b10;
`step
// 9th flit comes and is usefull for ic_download
rep_flit_ic=16'h1234;
v_rep_flit_ic=1'b1;
rep_ctrl_ic=2'b11;
`step
//at this time, inst cache is ready to receive inst word and all inst words have been recceived by ic_download
$display("(%t)inst word sent to inst cache is valid:%d inst:%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$fdisplay(logfile,"(%t) inst word sent to inst cache is :%h and ic_download_state is :%b",$time,v_inst_word_ic,inst_word_ic,ic_download_state);
$stop;
end
endmodule
|
#include <bits/stdc++.h> long long max(long long a, long long b) { return a > b ? a : b; } long long min(long long a, long long b) { return a < b ? a : b; } void swap(long long &a, long long &b) { long long tmp = a; a = b; b = tmp; } long long lowbit(long long &x) { return x & (-x); } void read(long long &x) { x = 0; char ch = getchar(), c = ch; while (ch < 0 || ch > 9 ) c = ch, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 0 , ch = getchar(); if (c == - ) x = -x; } const long long INF = 0x3f3f3f3f3f3f3f3f; const long long MAXN = 300000 + 10; const long long MAXM = 10; long long dp[MAXN][MAXM + 10], n, m, k, a[MAXN]; int main() { read(n), read(m), read(k); long long ans = 0; for (long long i = 1; i <= n; ++i) read(a[i]); for (int i = 0; i <= n; ++i) for (int j = 0; j < m; ++j) dp[i][j] = -INF; dp[0][m - 1] = 0; for (long long i = 1; i <= n; ++i) for (long long j = 0; j < m; ++j) { if (j == 0) dp[i][j] = max(dp[i - 1][m - 1] + a[i], a[i]) - k; else dp[i][j] = dp[i - 1][j - 1] + a[i]; ans = max(ans, dp[i][j]); } printf( %I64d , ans); return 0; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module convolve_kernel_adEe_DSP48_0(
input [5 - 1:0] in0,
input [2 - 1:0] in1,
input [6 - 1:0] in2,
output [9 - 1:0] dout);
wire signed [18 - 1:0] b;
wire signed [25 - 1:0] a;
wire signed [25 - 1:0] d;
wire signed [43 - 1:0] m;
wire signed [25 - 1:0] ad;
assign a = $signed(in0);
assign d = $unsigned(in1);
assign b = $unsigned(in2);
assign ad = a + d;
assign m = ad * b;
assign dout = m;
endmodule
`timescale 1 ns / 1 ps
module convolve_kernel_adEe(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
convolve_kernel_adEe_DSP48_0 convolve_kernel_adEe_DSP48_0_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_mem (/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_write, wr_data, wr_addr, rd_addr
);
parameter DW = 104;
parameter AW = 2;
localparam MD = 1<<AW;
//#########
//# INPUTS
//#########
input wr_clk; //write clock
input wr_write;
input [DW-1:0] wr_data;
input [AW-1:0] wr_addr;
input [AW-1:0] rd_addr;
//##########
//# OUTPUTS
//##########
output [DW-1:0] rd_data;
//########
//# REGS
//########
reg [DW-1:0] mem[MD-1:0];
//Write
always @(posedge wr_clk)
if(wr_write)
mem[wr_addr[AW-1:0]] <= wr_data[DW-1:0];
//Read
assign rd_data[DW-1:0] = mem[rd_addr[AW-1:0]];
endmodule // fifo_mem
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int n, m, grid[N][N]; int val[N][N]; bool vis[105][105]; int a[105]; int b[105]; int dp[105][105]; int tot; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , a + i), tot ^= a[i]; int tmp = 0; for (int i = 0; i < m; i++) scanf( %d , b + i), tmp ^= b[i]; if (tot != tmp) return puts( NO ); for (int x = 0; x < 31; x++) { for (int i = 0; i < n; i++) { if (a[i] >> x & 1) { bool f = false; for (int j = 0; j < m; j++) if (b[j] >> x & 1) { grid[i][j] ^= (1 << x); b[j] ^= (1 << x); a[i] ^= (1 << x); break; } } } int cnt = 0; for (int j = 0; j < m; j++) cnt += (b[j] >> x & 1); if (cnt & 1) return puts( NO ); for (int j = 0; j < m; j++) if (b[j] >> x & 1) grid[0][j] ^= (1 << x), b[j] ^= (1 << x); } for (int x = 0; x < 31; x++) { for (int j = 0; j < m; j++) { if (b[j] >> x & 1) { bool f = false; for (int i = 0; i < n; i++) if (a[i] >> x & 1) { grid[i][j] ^= (1 << x); b[j] ^= (1 << x); a[i] ^= (1 << x); break; } } } int cnt = 0; for (int i = 0; i < n; i++) cnt += (a[i] >> x & 1); if (cnt & 1) return puts( NO ); for (int i = 0; i < n; i++) if (a[i] >> x & 1) grid[i][0] ^= (1 << x), a[i] ^= (1 << x); } puts( YES ); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << grid[i][j] << ; cout << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_4_V
`define SKY130_FD_SC_MS__SEDFXTP_4_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_4_V
|
//////////////////////////////////////////////////////////////////////////////////
// d_partial_FFM_gate_6b.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_partial_FFM_gate_6b
// File Name: d_partial_FFM_gate_6b.v
//
// Version: v1.0.1-6b
//
// Description:
// - parallel Finite Field Multiplier (FFM) module
// - 2 polynomial form input, 1 polynomial form output
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_partial_FFM_gate_6b
(
input wire [5:0] i_a, // input term A
input wire [5:0] i_b, // input term B
output wire [10:0] o_r // output term result
);
///////////////////////////////////////////////////////////
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
// //
// ONLY FOR 6 BIT POLYNOMIAL MULTIPLICATION //
// //
// CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! CAUTION! //
///////////////////////////////////////////////////////////
// multiplication
assign o_r[10] = (i_a[5]&i_b[5]);
assign o_r[ 9] = (i_a[4]&i_b[5]) ^ (i_a[5]&i_b[4]);
assign o_r[ 8] = (i_a[3]&i_b[5]) ^ (i_a[4]&i_b[4]) ^ (i_a[5]&i_b[3]);
assign o_r[ 7] = (i_a[2]&i_b[5]) ^ (i_a[3]&i_b[4]) ^ (i_a[4]&i_b[3]) ^ (i_a[5]&i_b[2]);
assign o_r[ 6] = (i_a[1]&i_b[5]) ^ (i_a[2]&i_b[4]) ^ (i_a[3]&i_b[3]) ^ (i_a[4]&i_b[2]) ^ (i_a[5]&i_b[1]);
assign o_r[ 5] = (i_a[0]&i_b[5]) ^ (i_a[1]&i_b[4]) ^ (i_a[2]&i_b[3]) ^ (i_a[3]&i_b[2]) ^ (i_a[4]&i_b[1]) ^ (i_a[5]&i_b[0]);
assign o_r[ 4] = (i_a[0]&i_b[4]) ^ (i_a[1]&i_b[3]) ^ (i_a[2]&i_b[2]) ^ (i_a[3]&i_b[1]) ^ (i_a[4]&i_b[0]);
assign o_r[ 3] = (i_a[0]&i_b[3]) ^ (i_a[1]&i_b[2]) ^ (i_a[2]&i_b[1]) ^ (i_a[3]&i_b[0]);
assign o_r[ 2] = (i_a[0]&i_b[2]) ^ (i_a[1]&i_b[1]) ^ (i_a[2]&i_b[0]);
assign o_r[ 1] = (i_a[0]&i_b[1]) ^ (i_a[1]&i_b[0]);
assign o_r[ 0] = (i_a[0]&i_b[0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_4_V
`define SKY130_FD_SC_LP__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_4_V
|
(* abc9_box, lib_whitebox *)
module \$__ICE40_CARRY_WRAPPER (
(* abc9_carry *)
output CO,
output O,
input A, B,
(* abc9_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
parameter I3_IS_CI = 0;
wire I3_OR_CI = I3_IS_CI ? CI : I3;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3_OR_CI),
.O(O)
);
`ifdef ICE40_HX
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
(CI => CO) = (126, 105);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
(I0 => O) = (449, 386);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
(A => CO) = (259, 245);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
(A => O) = (400, 379);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
(B => CO) = (231, 133);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
(B => O) = (379, 351);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
(I3 => O) = (316, 288);
(CI => O) = (316, 288);
endspecify
`endif
`ifdef ICE40_LP
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
(CI => CO) = (186, 155);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
(I0 => O) = (662, 569);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
(A => CO) = (382, 362);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
(A => O) = (589, 558);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
(B => CO) = (341, 196);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
(B => O) = (558, 517);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
(I3 => O) = (465, 423);
(CI => O) = (465, 423);
endspecify
`endif
`ifdef ICE40_U
specify
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
(CI => CO) = (278, 278);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
(I0 => O) = (1245, 1285);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
(A => CO) = (675, 662);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
(A => O) = (1179, 1232);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
(B => CO) = (609, 358);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
(B => O) = (1179, 1205);
// https://github.com/YosysHQ/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
(I3 => O) = (861, 874);
(CI => O) = (861, 874);
endspecify
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> t; while (t--) { cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int mx, x; mx = 0; for (int i = 1; i < n; i++) { if (arr[i] < arr[i - 1]) { x = arr[i - 1] - arr[i]; if (x > mx) { mx = x; } arr[i] = arr[i - 1]; } } int ans = 0; while (mx != 0) { mx = mx / 2; ans++; } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e15; long long l, r; void Input() { cin >> l >> r; } void Solve() { if (r <= 10) { long long Res = 0; for (long long a = l; a <= r; ++a) { for (long long b = l; b <= a; ++b) Res = max(Res, a % b); } cout << Res; } else { long long m = max(r / 2 + 1, l); cout << max(r % l, r % m); } cout << n ; } int main() { if (fopen( trash.inp , r )) freopen( trash.inp , r , stdin), freopen( trash.out , w , stdout); ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int Test; cin >> Test; while (Test--) { Input(); Solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n{0}, a{0}, m{0}, s{0}; cin >> n; for (long long int i = 1; i <= n; i++) { cin >> a; s += a; m = max(m, a); } if (s % 2 == 1 || s < 2 * m) { cout << NO ; return 0; } cout << YES ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long inf = 0x3f3f3f3f; const long long llinf = 1e18; const long long nax = 0; int n, m, batas; vector<pair<int, int>> shift; set<char> simpen; map<char, bool> sabi; int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n >> m >> batas; char arr[n + 5][m + 5]; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> arr[i][j]; if (arr[i][j] == S ) { shift.push_back({i, j}); } else { simpen.insert(arr[i][j]); } } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { for (auto x : shift) { int x1 = i, x2 = x.first, y1 = j, y2 = x.second; int hitung = ceil(sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1))); if (hitung <= batas) { sabi[arr[i][j]] = 1; } } } } int q, ans = 0; cin >> q; string s; cin >> s; for (int k = 0; k < q; ++k) { if (s[k] >= 97) { if (!simpen.count(s[k])) { cout << -1 << n ; return 0; } else continue; } else { if (shift.empty()) { cout << -1 << n ; return 0; } bool ok = 0, ada = 0; if (!simpen.count(s[k] + 32)) { cout << -1 << n ; return 0; } else { if (sabi[s[k] + 32]) continue; else ans++; } } } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; if (n == 5) { cout << 2 << << 4 << n ; } else cout << 2 << << n / 2 << n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_BLACKBOX_V
`define SKY130_FD_SC_LP__DECAP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int const maxn = 1e5 + 5; int ans[maxn], used[maxn]; inline int oks(vector<int> a) { for (int i = 0; i < (int)a.size(); ++i) if (a[i] == i + 1 || (a[i] & (i + 1)) == 0) return 0; return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, cnt = 1, N; cin >> n; N = n; if (n % 2 == 1) { cout << NO << n ; } else { cout << YES << n ; while (n > 0) { int x = 1; while (x * 2 <= n) x *= 2; for (int w = x; w <= n; ++w) { ans[w] = x - (w - x) - 1; ans[x - (w - x) - 1] = w; } n -= 2 * (n - x + 1); } for (int i = 1; i <= N; ++i) cout << ans[i] << ; cout << n ; } n = N; if (n <= 5) { cout << NO << n ; exit(0); } while (n > 0) { int x = 1; while (x * 2 <= n) x *= 2; if (x == n) { cout << NO << n ; exit(0); } if (n == 6) { ans[1] = 3, ans[2] = 6, ans[3] = 2, ans[4] = 5, ans[5] = 1, ans[6] = 4; n = 0; break; } if ((n - x + 1) % 2 == 1) { int R = n, cur = (n - x) / 2 + 1; for (int i = x; cur > 0; ++i, cur--) { if (i == x + 1) continue; ans[i] = R; ans[R] = i; R--; } ans[x + 1] = x - 1; ans[x - 1] = x + 1; n = x - 2; } else { while (n > 7) { ans[n] = n - 1; ans[n - 1] = n; n -= 2; } ans[1] = 3, ans[2] = 6, ans[3] = 1, ans[4] = 5, ans[5] = 4, ans[6] = 7, ans[7] = 2; n = 0; } } cout << YES << n ; for (int i = 1; i <= N; ++i) cout << ans[i] << ; cout << n ; return 0; }
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____25.000______0.000______50.0______175.402_____98.575
// CLK_OUT3___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2011 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(*i $Id: NStrongRec.v 13323 2010-07-24 15:57:30Z herbelin $ i*)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Module NStrongRecPropFunct (Import N : NAxiomsSig').
Include NSubPropFunct N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
(** We need a result similar to [f_equal], but for setoid equalities. *)
Lemma f_equiv : forall f g x y,
(N.eq==>Aeq)%signature f g -> N.eq x y -> Aeq (f x) (g y).
Proof.
auto.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0.
repeat red; intros.
apply f_equiv; auto.
apply recursion_wd; try red; auto.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt.
apply strong_rec0_wd; auto.
now rewrite Enn'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
apply f_equiv; auto with *.
rewrite recursion_succ; try (repeat red; auto with *; fail).
apply f_wd.
apply recursion_wd; try red; auto with *.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ.
apply f_wd; auto with *.
red; intros; rewrite strong_rec0_0; auto with *.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
apply f_wd; auto with *.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Implicit Arguments strong_rec [A].
End NStrongRecPropFunct.
|
module top;
lower #(1, 2, 3) dut();
endmodule
module lower;
parameter one = 1; // This should be 'sd1
parameter two = 2; // This should be 'sd2
parameter three = 0; // This should be 'sd3
parameter local1 = one - two; // This should be -'sd1
parameter local_lt0 = local1 < 0; // This should be 'd1
parameter local_le0 = local1 <= 0; // This should be 'd1
parameter local_gt0 = local1 > 0; // This should be 'd0
parameter local_ge0 = local1 >= 0; // This should be 'd0
parameter local_0lt = 0 < local1; // This should be 'd1
parameter local_0le = 0 <= local1; // This should be 'd1
parameter local_0gt = 0 > local1; // This should be 'd0
parameter local_0ge = 0 >= local1; // This should be 'd0
reg err;
initial begin
err = 0;
if (!local_lt0) err = 1;
if (!local_le0) err = 1;
if ( local_gt0) err = 1;
if ( local_ge0) err = 1;
if ( local_0lt) err = 1;
if ( local_0le) err = 1;
if (!local_0gt) err = 1;
if (!local_0ge) err = 1;
if (err == 0) $display("PASSED");
else $display("FAILED");
end
endmodule
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#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int maxn = 2200; LL a[maxn * 2], b[maxn * 2]; using PII = pair<int, int>; constexpr int inf = 1000000000; struct SSPA { struct Edge { int u, v, f, c; }; int n, s, t; vector<Edge> edges; vector<vector<int>> adj; vector<int> h, d, p, done; SSPA(int n, int s, int t) : n(n), s(s), t(t) { adj.resize(n); h.resize(n); d.resize(n); p.resize(n); done.resize(n); } void add(int u, int v, int f, int c) { adj[u].push_back(edges.size()); edges.push_back({u, v, f, c}); adj[v].push_back(edges.size()); edges.push_back({v, u, 0, -c}); } bool dijkstra() { fill(d.begin(), d.end(), inf); fill(p.begin(), p.end(), -1); fill(done.begin(), done.end(), 0); priority_queue<PII, vector<PII>, greater<PII>> q; q.push({d[s] = 0, s}); while (not q.empty()) { int u = q.top().second; q.pop(); if (done[u]) continue; done[u] = 1; for (int i : adj[u]) { if (auto& e = edges[i]; e.f and d[e.v] > d[e.u] + e.c + h[u] - h[e.v]) { p[e.v] = i; q.push({d[e.v] = d[e.u] + e.c + h[u] - h[e.v], e.v}); } } } return ~p[t]; } int min_cost_flow() { int flow = 0, cost = 0; while (dijkstra()) { for (int i = 0; i < n; i += 1) h[i] += d[i]; int f = inf; for (int u = t; u != s; u = edges[p[u]].u) f = min(f, edges[p[u]].f); flow += f; cost += f * h[t]; for (int u = t; u != s; u = edges[p[u]].u) { edges[p[u]].f -= f; edges[p[u] ^ 1].f += f; } } return cost; } }; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; for (int i = 0; i < 2 * n; i += 1) cin >> a[i] >> b[i]; LL L = 0, R = 1000000000 + 1; vector<int> u; for (int i = 0; i < 2 * n; i += 1) u.push_back(i); sort(u.begin(), u.end(), [&](const int& x, const int& y) { if (b[x] != b[y]) return b[x] < b[y]; return a[x] > a[y]; }); while (L < R) { LL M = (L + R) >> 1; vector<LL> v, w; LL m = 0; for (int i : u) { m = max(m, a[i] * M + b[i]); if (i < n) v.push_back(m); else w.push_back(a[i] * M + b[i]); } int ok = 1; sort(w.begin(), w.end()); for (int i = 0; i < n; i += 1) ok &= v[i] >= w[i]; if (ok) R = M; else L = M + 1; } if (L == 1000000000 + 1) { cout << -1 ; return 0; } cout << L << ; int s = 0, t = 8 * n + 1; SSPA SSPA(t + 1, s, t); for (int i = 0; i < n; i += 1) SSPA.add(s, i + 1, 1, 0); for (int i = n; i < 2 * n; i += 1) SSPA.add(4 * n + i + 1, t, 1, 0); for (int i = 0; i < 2 * n; i += 1) { SSPA.add(2 * n + i + 1, i + 1, inf, 0); SSPA.add(i + 1, 2 * n + i + 1, inf, 1); SSPA.add(6 * n + i + 1, 4 * n + i + 1, inf, 0); SSPA.add(4 * n + i + 1, 6 * n + i + 1, inf, 1); SSPA.add(i + 1, 4 * n + i + 1, inf, 0); } for (int i = 1; i < 2 * n; i += 1) { SSPA.add(2 * n + u[i] + 1, 2 * n + u[i - 1] + 1, inf, 0); if (b[u[i]] == b[u[i - 1]]) SSPA.add(2 * n + u[i - 1] + 1, 2 * n + u[i] + 1, inf, 0); } sort(u.begin(), u.end(), [&](const int& x, const int& y) { return a[x] * L + b[x] < a[y] * L + b[y]; }); for (int i = 1; i < 2 * n; i += 1) { SSPA.add(6 * n + u[i] + 1, 6 * n + u[i - 1] + 1, inf, 0); if (a[u[i]] * L + b[u[i]] == a[u[i - 1]] * L + b[u[i - 1]]) SSPA.add(6 * n + u[i - 1] + 1, 6 * n + u[i] + 1, inf, 0); } cout << SSPA.min_cost_flow(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n; const int N = 2e5; int dep[N], fa[N], cnt[N], ans; int main() { ios ::sync_with_stdio(0); cin >> n; ans = 1; for (int i = 2; i <= n; ++i) { cin >> fa[i]; dep[i] = dep[fa[i]] + 1; cnt[dep[i]] ^= 1; } for (int i = 1; i <= n; ++i) ans += cnt[i]; cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int AL = 26; const int N = (int)1e6 + 9; int powr(int n, int k) { if (k == 0) return 1; int v = powr(n, k / 2); v = (v * 1ll * v) % MOD; if (k & 1) v = (v * 1ll * n) % MOD; return v; } int cnt[AL]; int f[N]; int inv[N]; int C(int a, int b) { if (b == 0) return 1; int v = f[a]; v = (v * 1ll * inv[b]) % MOD; v = (v * 1ll * inv[a - b]) % MOD; return v; } int ways(string a, string b) { for (int j = 0; j < AL; j++) cnt[j] = 0; for (auto x : a) { cnt[x - a ]++; } int answ = 0; int mlt; int sz = a.size(); int nsz; int y; bool ok; for (int i = 0; i < b.size(); i++) { nsz = sz - 1; y = b[i] - a ; ok = false; for (int t = 0; t < y; t++) { if (cnt[t] > 0) ok = true; } if (ok) { mlt = 1; for (int r = AL - 1; r >= 0; r--) { mlt = (mlt * 1ll * C(nsz, cnt[r])) % MOD; nsz -= cnt[r]; nsz += (r == y); } answ = (answ + mlt) % MOD; } cnt[b[i] - a ]--; if (cnt[b[i] - a ] < 0) break; sz--; } return answ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; f[0] = 1; inv[0] = 1; for (int i = 1; i < N; i++) { f[i] = (1ll * i * f[i - 1]) % MOD; inv[i] = powr(f[i], MOD - 2); } string a, b; cin >> a >> b; cout << (ways(a, b) - ways(a, a) + MOD - 1) % MOD << n ; return 0; }
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