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// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_one_cold (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter inactive = `OVL_INACTIVE_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ONE_COLD";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_one_cold_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_one_cold_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_one_cold_psl_logic.v"
`else
`endmodule // ovl_one_cold
`endif
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:33 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_processing_system7_0_2 -prefix
// design_1_processing_system7_0_2_ design_1_processing_system7_0_2_stub.v
// Design : design_1_processing_system7_0_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module design_1_processing_system7_0_2(USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 400007; int n, I, cnt = 0, ret = -1; int a[maxn], s[maxn]; int ck() { int ans = 1; for (int i = 1; i <= 8 * I / n; ++i) { ans *= 2; if (ans > cnt) return -1; } return ans; } int main() { scanf( %d%d , &n, &I); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } memset(s, 0, sizeof(s)); sort(a + 1, a + n + 1); for (int i = 1; i <= n; ++i) { if (a[i] != ret) { ret = a[i], cnt++; } s[cnt]++; } for (int i = 1; i <= cnt; ++i) { s[i] += s[i - 1]; } int pI = ck(); if (pI == -1) { printf( %d n , 0); return 0; } int ans = 0; for (int i = pI; i <= cnt; ++i) { ans = max(ans, s[i] - s[i - pI]); } printf( %d n , n - ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; int sum = 0; for (int i = 0; i < n; i++) { int a; cin >> a; sum += a; } if (sum == m) { cout << YES << endl; } else { cout << NO << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n >> x; if (n == 3) { cout << >vv << endl << ^<. << endl << ^.< << endl; cout << 1 << << 3; } if (n == 5) { cout << >...v << endl << v.<.. << endl << ..^.. << endl << >.... << endl << ..^.< << endl; cout << 1 << << 1; } if (n == 100) { cout << >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.>.>.>.>.>.>.>.> .>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.v << endl; for (int i = 0; i < 49; i++) { cout << ^v.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<<<<<<<<<<< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< << endl; cout << ^>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>.>.>.>.>.>.>.> .>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.>.v << endl; } cout << ^<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<.<<<<<<<<<<<<< <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< << endl; cout << 1 << << 1; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_V
|
module adc_interface ( input CLK,
input CLK_1M,
//processor interface
input [31:0] DATA_IN,
output [31:0] DATA_OUT,
input WR,
//device interface
output CS,
output SCLK,
output SDO,
input SDI );
wire DEV_BUSY;
reg [1:0] state = 0, nextstate = 0;
reg [2:0] channel;
reg [11:0] saved_data;
wire [11:0] conv_result;
wire request = (state == 2'd1);
wire busy = (state != 2'd0);
always@ (*)
case(state)
2'd0: if (WR) nextstate = 1; //wait for request
else nextstate = 0;
2'd1: if (DEV_BUSY) nextstate = 2; //wait for device to start
else nextstate = 1;
2'd2: if (!DEV_BUSY) nextstate = 3; //wait for device to stop
else nextstate = 2;
default: nextstate = 0;
endcase
always@ (posedge CLK)
begin
state <= nextstate;
if(WR) channel <= DATA_IN[2:0];
if(state == 3) saved_data <= conv_result;
end
assign DATA_OUT = {busy, 19'd0, saved_data};
spi4 spi4_m( .CLK ( CLK_1M ),
.CHANNEL ( channel ),
.CONV_RESULT ( conv_result ),
.REQUEST ( request ),
.BUSY ( DEV_BUSY ),
.CS ( CS ),
.SCLK ( SCLK ),
.SDO ( SDO ),
.SDI ( SDI ));
endmodule
module spi4( input CLK,
//host interface
input [ 2:0] CHANNEL,
output [11:0] CONV_RESULT,
input REQUEST,
output BUSY,
//device interface
output CS,
output SCLK,
output SDO,
input SDI );
reg [ 4:0] tx_sreg = 0;
reg [15:0] rx_sreg = 0;
reg [11:0] saved_data = 0;
reg [4:0] bit_cnt = 0;
always @(negedge CLK)
begin
if(BUSY)
begin
if(bit_cnt < 16) bit_cnt <= bit_cnt + 5'd1;
else
begin
saved_data <= rx_sreg[11:0];
bit_cnt <= 0;
end
tx_sreg[4:1] <= tx_sreg[3:0];
tx_sreg[0] <= 0;
end
else
begin
if(REQUEST)
begin
bit_cnt <= 1;
tx_sreg <= {2'b0, CHANNEL};
end
end
end
always@(posedge CLK)
begin
if(BUSY)
begin
rx_sreg[0] <= SDI;
rx_sreg[15:1] <= rx_sreg[14:0];
end
end
//-----------------------------------------------
assign BUSY = (bit_cnt != 5'd0);
assign CS = ~BUSY;
assign SDO = tx_sreg[4];
assign SCLK = BUSY & CLK;
assign CONV_RESULT = saved_data;
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact:
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_ram
*
*/
`default_nettype none
module openhmc_ram #(
parameter DATASIZE = 78, // Memory data word width
parameter ADDRSIZE = 9, // Number of memory address bits
parameter PIPELINED = 0
) (
//----------------------------------
//----SYSTEM INTERFACE
//----------------------------------
input wire clk,
//----------------------------------
//----Signals
//----------------------------------
input wire wen,
input wire [DATASIZE-1:0] wdata,
input wire [ADDRSIZE-1:0] waddr,
input wire ren,
input wire [ADDRSIZE-1:0] raddr,
output wire [DATASIZE-1:0] rdata
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire [DATASIZE-1:0] rdata_ram;
generate
if (PIPELINED == 0)
begin
assign rdata = rdata_ram;
end
else
begin
reg [DATASIZE-1:0] rdata_dly;
reg ren_dly;
assign rdata = rdata_dly;
always @(posedge clk)
begin
ren_dly <= ren;
if (ren_dly)
rdata_dly <= rdata_ram;
end
end
endgenerate
reg [DATASIZE-1:0] MEM [0:(2**ADDRSIZE)-1];
reg [DATASIZE-1:0] data_out;
assign rdata_ram = data_out;
always @(posedge clk)
begin
if (wen)
MEM[waddr] <= wdata;
end
always @(posedge clk)
begin
if (ren)
data_out <= MEM[raddr];
end
endmodule
`default_nettype wire
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_mult2(
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output [25:0] p
);
DSP48 #(
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
.B_INPUT("DIRECT"), // B input DIRECT from fabric or CASCADE from another DSP48
.CARRYINREG(0), // Number of pipeline registers for the CARRYIN input, 0 or 1
.CARRYINSELREG(0), // Number of pipeline registers for the CARRYINSEL, 0 or 1
.CREG(0), // Number of pipeline registers on the C input, 0 or 1
.LEGACY_MODE("MULT18X18"), // Backward compatibility, NONE, MULT18X18 or MULT18X18S
.MREG(0), // Number of multiplier pipeline registers, 0 or 1
.OPMODEREG(0), // Number of pipeline regsiters on OPMODE input, 0 or 1
.PREG(1), // Number of pipeline registers on the P output, 0 or 1
.SUBTRACTREG(0) // Number of pipeline registers on the SUBTRACT input, 0 or 1
) DSP48_inst (
.BCOUT(), // 18-bit B cascade output
.P(p), // 48-bit product output
.PCOUT(), // 48-bit cascade output
.A(a), // 18-bit A data input
.B(b), // 18-bit B data input
.BCIN(18'd0), // 18-bit B cascade input
.C(48'd0), // 48-bit cascade input
.CARRYIN(1'b0), // Carry input signal
.CARRYINSEL(2'd0), // 2-bit carry input select
.CEA(ce), // A data clock enable input
.CEB(ce), // B data clock enable input
.CEC(1'b1), // C data clock enable input
.CECARRYIN(1'b1), // CARRYIN clock enable input
.CECINSUB(1'b1), // CINSUB clock enable input
.CECTRL(1'b1), // Clock Enable input for CTRL regsiters
.CEM(1'b1), // Clock Enable input for multiplier regsiters
.CEP(ce), // Clock Enable input for P regsiters
.CLK(sys_clk), // Clock input
.OPMODE(7'h35), // 7-bit operation mode input
.PCIN(48'd0), // 48-bit PCIN input
.RSTA(1'b0), // Reset input for A pipeline registers
.RSTB(1'b0), // Reset input for B pipeline registers
.RSTC(1'b0), // Reset input for C pipeline registers
.RSTCARRYIN(1'b0), // Reset input for CARRYIN registers
.RSTCTRL(1'b0), // Reset input for CTRL registers
.RSTM(1'b0), // Reset input for multiplier registers
.RSTP(1'b0), // Reset input for P pipeline registers
.SUBTRACT(1'b0) // SUBTRACT input
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_12_0,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_12_0,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=32,DIN_FROM=29,DIN_TO=6}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_12_0 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(29),
.DIN_TO(6)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_ioslave_dl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Unit Name: bw_iodll (delay-locked loop -> Slave Delay line)
// Block Name: bw_ioslave_dl
// Files that must be included: none
//
module bw_ioslave_dl(
// inputs in alphabetical order
dqs_in,
lpf_out,
se,
si,
strobe,
//outputs in alphabetical order
dqs_out,
so );
input dqs_in;
input [4:0] lpf_out;
input se;
input si;
input strobe;
output dqs_out;
output so;
parameter DELAY = 1250;
reg dqs_out;
// 1/4 cycle delay line.
always @(dqs_in)
begin
dqs_out <= #DELAY dqs_in;
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg a;
integer i;
initial begin
vec = 4'b0000;
a = 0;
if (vec !== 4'b0000) begin
$display("FAILED -- initialized vec to %b", vec);
$finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
{ a, vec[i] } = i;
end
if (vec !== 4'b1010) begin
$display("FAILED == vec (%b) is not 1010", vec);
$finish;
end
if (a !== 1'b1) begin
$display("FAILED -- a (%b) is not 1", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { int n, k; scanf( %d %d , &n, &k); if (k > n * 3) { printf( %d , 0); } else { printf( %d , 3 * n - k); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long double PI = acosl(-1); bool compare_int(int a, int b) { return (a > b); } bool compare_string(string a, string b) { return a.size() < b.size(); } bool compare_pair(const pair<int, int> &a, const pair<int, int> &b) { if (a.second == b.second) return a.first > b.first; else return (a.second > b.second); } long long int fact(long long int n) { if (n == 0 || n == 1) return 1; else return n * fact(n - 1); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s, st; long long int x = 0, temp = 0, ans = 0; cin >> s; if (s.size() == 1) { cout << s << endl; return 0; } for (int i = 1; i < s.size(); i++) st += 9 ; stringstream ss(s); ss >> x; stringstream sm(st); sm >> temp; long long int te = x - temp; while (te) { ans += (te % 10); te /= 10; } cout << ans + (s.size() - 1) * 9 << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, counter, a, b, c; cin >> t; while (t--) { cin >> a >> b >> c; counter = 0; while (++counter) { (a < b) ? a += b : b += a; if (max(a, b) > c) break; } cout << counter << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; cout << (a + b + c) * (a + b + c) - (a * a + c * c + e * e); }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long long MX = 1e9; const long long INF = 1e9; void solve() { string s; cin >> s; int n = s.length(), mx[n + 1], c = 0; for (int i = 0; i < s.length(); ++i) { if (s[i] == 1 ) ++c; else if (c) --c; mx[i] = c; } mx[n + 1] = c; for (int i = n - 1; i >= 0; --i) mx[i] = min(mx[i], mx[i + 1]); int nz = 0; for (int i = 0; i < n; ++i) { if (s[i] == 1 ) { if (nz < mx[i + 1]) { s[i] = 0 ; ++nz; } } } cout << s << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_BEHAVIORAL_PP_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module fifo_pacer
(input clk,
input reset,
input [7:0] rate,
input enable,
input src1_rdy_i, output dst1_rdy_o,
output src2_rdy_o, input dst2_rdy_i,
output underrun, overrun);
wire strobe;
cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
wire all_ready = src1_rdy_i & dst2_rdy_i;
assign dst1_rdy_o = all_ready & strobe;
assign src2_rdy_o = dst1_rdy_o;
assign underrun = strobe & ~src1_rdy_i;
assign overrun = strobe & ~dst2_rdy_i;
endmodule // fifo_pacer
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, k; cin >> n >> k; int ans = n; if (k >= n) { cout << 1; } else { for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { if (i <= k) { ans = min(ans, n / i); } if (n / i <= k) { ans = min(ans, i); } } } cout << ans; } } int main() { ios::sync_with_stdio(0); cin.tie(0); int test; cin >> test; for (int i = 1; i <= test; i++) { solve(); cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k, l, mx = 0, m, i, j, s = 0; cin >> n >> k; long long int a[n], t[n], sum[n], dv[n]; for (i = 0; i < n; i++) { cin >> a[i]; s += a[i]; dv[i] = s; } s = 0; for (i = 0; i < n; i++) { cin >> t[i]; if (t[i] == 1) s += a[i]; sum[i] = s; } l = n - k + 1; for (i = 0; i < l; i++) { m = 0; if (i > 0) m += dv[i + k - 1] - dv[i - 1]; else m += dv[i + k - 1]; if (i > 0) m += sum[i - 1]; m += sum[n - 1] - sum[i + k - 1]; if (m > mx) mx = m; } cout << mx << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 == 0) { cout << -1; } else { for (int i = 0; i < n; i++) { cout << (2 * i) % n << ; } cout << endl; cout << 0 << ; for (int i = n - 1; i > 0; i--) { cout << i << ; } cout << endl; for (int i = 0; i < n; i++) { cout << i << ; } } }
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.0/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_fifo64to256 #(
parameter depth = 2 /* < log2 of the capacity, in 256-bit words */
) (
input sys_clk,
input sys_rst,
output w8avail,
input we,
input [63:0] wd,
output ravail,
input re,
output [255:0] rd
);
reg [63:0] storage1[0:(1 << depth)-1];
reg [63:0] storage2[0:(1 << depth)-1];
reg [63:0] storage3[0:(1 << depth)-1];
reg [63:0] storage4[0:(1 << depth)-1];
reg [depth+2:0] level;
reg [depth+1:0] produce;
reg [depth-1:0] consume;
wire wavail = ~level[depth+2];
assign w8avail = level < ((1 << (depth + 2)) - 8);
assign ravail = |(level[depth+2:2]);
wire read = re & ravail;
wire write = we & wavail;
always @(posedge sys_clk) begin
if(sys_rst) begin
level <= 0;
produce <= 0;
consume <= 0;
end else begin
if(read)
consume <= consume + 1;
if(write) begin
produce <= produce + 1;
case(produce[1:0])
2'd0: storage1[produce[depth+1:2]] <= wd;
2'd1: storage2[produce[depth+1:2]] <= wd;
2'd2: storage3[produce[depth+1:2]] <= wd;
2'd3: storage4[produce[depth+1:2]] <= wd;
endcase
end
case({read, write})
2'b10: level <= level - 4;
2'b01: level <= level + 1;
2'b11: level <= level - 3;
endcase
end
end
assign rd = {storage1[consume], storage2[consume], storage3[consume], storage4[consume]};
endmodule
|
module compressor2(a,b,s,c);
parameter width = 0;
input [width-1:0] a;
input [width-1:0] b;
output [width-1:0] s;
output [width-1:0] c;
assign s = a ^ b;
assign c = a & b;
endmodule // compressor2
module counter(clk,ld,nb,dn);
parameter width = 0;
input clk;
input ld;
input [width-1:0] nb;
output dn;
reg [width-2:0] sp;
reg [width-1:0] cp;
reg dp;
wire [width-2:0] sq;
wire [width-1:0] cq;
wire dq;
wire [width-2:0] sr;
wire [width-1:0] cr;
compressor2
#(.width (width-1))
advance
(.a (sp),
.b (cp[width-2:0]),
.s (sq),
.c (cq[width-1:1]));
assign cq[0] = ~cp[0];
assign dq = dp | cp[width-1];
assign sr = ld ? nb[width-1:1] : sq;
assign cr[0] = ld ? nb[0] : cq[0];
assign cr[width-1:1] = ld ? {(width-1) {1'b0}} : cq[width-1:1];
assign dn = ld ? 1'b0 : dq;
always @(posedge clk)
begin
sp <= sr;
cp <= cr;
dp <= dn;
end
endmodule // counter
module main;
parameter delay = 10;
parameter width = 5;
reg clk;
reg inp;
reg [width-1:0] nb;
wire out;
counter
#(.width (width))
root
(.clk (clk),
.ld (inp),
.nb (nb),
.dn (out));
initial
begin
$display("+------------------------+");
$display("| Test bench for counter |");
$display("+------------------------+");
$monitor("ld = %b, sr = %d, cr = %d, dn = %b",
root.ld, root.sr, root.cr, root.dn);
clk = 0;
repeat(10) @(posedge clk);
nb = {width {1'b0}} - (delay + 1 - width);
inp = 1;
@(posedge clk);
inp = 0;
repeat(delay-1) @(posedge clk);
if (out)
begin
$display("ERROR: counter finished too soon");
end
@(posedge clk);
if (!out)
begin
$display("ERROR: counter did not finish on time");
end
repeat(5) @(posedge clk);
$monitoroff;
$display("Test complete at time %0t.", $time);
$finish;
end
always
#5 clk = !clk;
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { long long t, i = 0, j, k, x, y, z, count = 0, p, flag = 0, ans = 0, sum = 0, l, n, m, max1, min1, pos, tmp, q; t = 1; while (t--) { long long n, r; scanf( %lld%lld , &n, &r); long double x[1005], y[1005]; for (i = 0; i < n; i++) { scanf( %Lf , &x[i]); } for (i = 0; i < n; i++) { y[i] = -1.0 * 1000000000; for (j = 0; j < i; j++) { double p = abs(x[i] - x[j]); if (p <= 2 * r) { double q = y[j] + sqrtl(4 * r * r - p * p); if (q > y[i]) y[i] = q; } } if (y[i] == -1.0 * 1000000000) y[i] = 1.0 * r; printf( %.15Lf , y[i]); } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_SYMBOL_V
`define SKY130_FD_SC_HVL__DECAP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long paw[30]; void pw() { paw[0] = 1; for (int i = 1; i < 20; i++) paw[i] = 10 * paw[i - 1]; } long long rev(long long a) { long long ret = 0; vector<int> v; while (a > 0) { v.push_back(a % 10); a /= 10; } for (int i = 0; i < v.size(); i++) ret += (v[i] * paw[v.size() - i - 1]); return ret; } int main() { long long a1, a2; cin >> a1 >> a2; pw(); cout << a1 + rev(a2) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 8e4 + 10; const long long mod = 998244353, modg = 3, modi = 332748118; int a[maxn], b[maxn]; int pow_mod(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = (long long)ans * a % mod; a = (long long)a * a % mod, b >>= 1; } return ans; } int add(int a, int b) { a += b; if (a > mod) return a - mod; return a; } int sub(int a, int b) { a -= b; if (a < 0) return a + mod; return a; } class nubmer { public: int rev[maxn], len, pw; long long wt[2][maxn]; void init_0() { int len = 1; while (len <= maxn / 2) len <<= 1; for (int mid = 1; mid < len; mid <<= 1) { long long wn1 = pow_mod(modg, (mod - 1) / (mid << 1)); long long wn2 = pow_mod(modi, (mod - 1) / (mid << 1)); wt[0][mid] = wt[1][mid] = 1; long long wt1 = wn1, wt2 = wn2; for (int j = 1; j <= mid; ++j) { wt[0][mid + j] = wt1; wt1 = wt1 * wn1 % mod; wt[1][mid + j] = wt2; wt2 = wt2 * wn2 % mod; } } } void init(int n) { len = 1; pw = 0; while (len <= n) len <<= 1, pw++; for (int i = 0; i <= len - 1; ++i) rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (pw - 1)); } void transform(int *a, int flag) { int f = flag == 1 ? 0 : 1; for (int i = 0; i <= len - 1; ++i) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int mid = 1; mid < len; mid <<= 1) { for (int r = mid << 1, j = 0; j < len; j += r) { long long *p = wt[f] + mid; int *p1 = a + j, *p2 = a + j + mid; for (int k = 0; k < mid; ++k, ++p, ++p1, ++p2) { int x = *p1, y = (*p) * (*p2) % mod; *p1 = add(x, y), *p2 = sub(x, y); } } } if (flag == -1) { long long inv = pow_mod(len, mod - 2); for (int i = 0; i <= len; i++) { a[i] = a[i] * inv % mod; if (a[i] < 0) a[i] += mod; } } } } ntt; int n, k; int s1[maxn], s2[maxn]; vector<int> solve(int l, int r) { if (l == r) { return vector<int>{1, s2[l]}; } int mid = (l + r) >> 1; vector<int> x = solve(l, mid), y = solve(mid + 1, r); ntt.init(x.size() + y.size()); for (int i = 0; i <= ntt.len + 5; i++) a[i] = 0, b[i] = 0; for (int i = 0; i < x.size(); i++) a[i] = x[i]; for (int i = 0; i < y.size(); i++) b[i] = y[i]; ntt.transform(a, 1); ntt.transform(b, 1); for (int i = 0; i < ntt.len; i++) a[i] = (long long)a[i] * b[i] % mod; ntt.transform(a, -1); int len = x.size() + y.size(); int mi = min(ntt.len, min(k + 1, len)); vector<int> ans(mi); for (int i = 0; i < mi; i++) { ans[i] = a[i]; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ntt.init_0(); cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> s1[i]; } int T; cin >> T; vector<int> tmp; while (T--) { int flag; cin >> flag; if (flag == 1) { int q, i, d; cin >> q >> i >> d; for (int j = 1; j <= n; j++) s2[j] = sub(q, s1[j]); s2[i] = sub(q, d); tmp = solve(1, n); cout << tmp[k] << n ; } else { int q, l, r, d; cin >> q >> l >> r >> d; for (int j = 1; j <= n; j++) { if (j >= l && j <= r) s2[j] = sub(sub(q, s1[j]), d); else s2[j] = sub(q, s1[j]); } tmp = solve(1, n); cout << tmp[k] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-11; long long n, k; bool solveIt(long long d1, long long d2) { if ((k - d1 + d2) % 3 != 0) return false; long long Y = (k - d1 + d2) / 3; long long X = d1 + Y; long long Z = Y - d2; if (X >= 0 && Y >= 0 && Z >= 0 && X <= k && Y <= k && Z <= k && X <= (n / 3) && Y <= (n / 3) && Z <= (n / 3) && abs(X - Y) == abs(d1) && abs(Y - Z) == abs(d2)) return true; return false; } int main() { std::ios_base::sync_with_stdio(0); long long t, d2, d1; cin >> t; while (t--) { bool flg = false; cin >> n >> k >> d1 >> d2; if (n % 3 != 0) { cout << no << endl; continue; } if (solveIt(d1, d2)) flg = true; if (solveIt(d1, -d2)) flg = true; if (solveIt(-d1, d2)) flg = true; if (solveIt(-d1, -d2)) flg = true; if (flg) cout << yes << endl; else cout << no << endl; } return 0; }
|
#include <bits/stdc++.h> int main() { int n(0); scanf( %d , &n); char first = x , last = y ; int count(0); if (n % 2 == 0) { for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + a , (count) % 2 + a ); ++count; }; puts( ); for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + c , (count) % 2 + c ); ++count; }; puts( ); printf( %c , first); for (int k = 0; k < n / 2 - 1; k++) { printf( %c%c , (count) % 2 + f , (count) % 2 + f ); ++count; }; printf( %c n , last); printf( %c , first); for (int k = 0; k < n / 2 - 1; k++) { printf( %c%c , (count) % 2 + m , (count) % 2 + m ); ++count; }; printf( %c n , last); } else if (n % 2 == 1) { char count = b ; printf( %c , first); for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + a , (count) % 2 + a ); ++count; }; puts( ); printf( %c , first); for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + c , (count) % 2 + c ); ++count; }; puts( ); for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + f , (count) % 2 + f ); ++count; }; printf( %c n , last); for (int k = 0; k < n / 2; k++) { printf( %c%c , (count) % 2 + m , (count) % 2 + m ); ++count; }; printf( %c n , last); } return 0; }
|
//
// Copyright 2011, Kevin Lindsey
// See LICENSE file for licensing information
//
module pram_sram_top(
input wire clk,
input wire button,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire [6:0] a_to_g2,
output wire [3:0] an2,
output reg good,
output reg bad,
output wire [1:0] hi_addr,
output wire [18:0] addr,
inout wire [15:0] data,
output wire ce,
output wire be,
output wire we,
output wire oe
);
wire clr, en, dclk, bclk, fclk;
wire [15:0] dataio, din1;
wire [17:0] sram_addr;
wire [5:0] pattern;
wire button_d;
assign clr = button_d;
assign ce = 0;
assign be = 0;
assign oe = en;
assign data = dataio;
assign addr = {1'b0, sram_addr};
assign hi_addr = sram_addr[17:16];
// custom clock
dcm_clock main_clock (
.CLKIN_IN(clk),
.RST_IN(clr),
.CLKFX_OUT(fclk)
//.CLKIN_IBUFG_OUT(),
//.CLK0_OUT(CLK0_OUT)
);
// controller
pram_sram_ctrl sram_ctrl (
.clk(fclk),
.clr(clr),
.go(bclk),
.halt(bad),
.we(we),
.sram_addr(sram_addr),
.pattern(pattern),
.en(en)
);
// ROM
pattern_rom pattern_rom (
.clk(fclk),
.addr(pattern),
.data(din1)
);
tristate_generic #(.N(16))
data_tristate (
.in(din1),
.en(en),
.out(dataio)
);
// button input
clock_divider clock_divider(
.clk(fclk),
.clr(clr),
.clk6(bclk),
.clk17(dclk)
);
debounce_generic button_debouncer(
.in(button),
.clk(dclk),
.clr(clr),
.out(button_d)
);
// address and value display
hex_7_segment data_display(
.x(data),
.clk(fclk),
.clr(clr),
.a_to_g(a_to_g),
.an(an)
);
hex_7_segment addr_display(
.x(addr[15:0]),
.clk(fclk),
.clr(clr),
.a_to_g(a_to_g2),
.an(an2)
);
always @*
if (data == din1)
begin
bad <= 0;
good <= 1;
end
else
begin
bad <= 1;
good <= 0;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON32_NEXT 6'b00_0001
`define S_TXPORTMON32_EVT_2 6'b00_0010
`define S_TXPORTMON32_TXN 6'b00_0100
`define S_TXPORTMON32_READ 6'b00_1000
`define S_TXPORTMON32_END_0 6'b01_0000
`define S_TXPORTMON32_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [31:0] rReadOffLast=0, _rReadOffLast=0;
reg [31:0] rReadLen=0, _rReadLen=0;
reg rReadCount=0, _rReadCount=0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE1Lo=0, _rLenLE1Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON32_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData;
assign TXN = rState[2]; // S_TXPORTMON32_TXN
assign LAST = rReadOffLast[0];
assign OFF = rReadOffLast[31:1];
assign LEN = rReadLen;
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON32_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
end
`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON32_END_0;
end
`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
end
`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_NEXT;
end
default: begin
_rState = `S_TXPORTMON32_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadOffLast <= #1 _rReadOffLast;
rReadLen <= #1 _rReadLen;
rReadCount <= #1 (RST ? 1'd0 : _rReadCount);
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE1Lo <= #1 _rLenLE1Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData) begin
_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);
_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);
_rReadCount = rReadCount + 1'd1;
end
else begin
_rReadOffLast = rReadOffLast;
_rReadLen = rReadLen;
_rReadCount = rReadCount;
end
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 1, we want to trigger the almost all received flag
_rLenLE1Lo = (LEN[15:0] <= 16'd1);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int a[n]; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } int temp1, temp2, flag = 0; for (int i = 0; i < n; ++i) { temp1 = a[i] - 1; temp2 = a[temp1] - 1; if (a[temp2] - 1 == i) { flag = 1; printf( YES n ); break; } } if (flag == 0) { printf( NO n ); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortRead.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaReadPort(
input wire reset,
input wire port_enable, //Enables/Disable port writing.
input wire rd_clk, // Clock read input..
input wire rd_en, // Enables reading.
output wire [31:0] rd_out, // Read Data output.
output wire empty, // Active high indicates buffer is empty.
output wire full, // Active high indicates buffer is full.
output wire prog_empty, // Active high indicates buffer is almost empty (at or below 160 samples).
output wire prog_full, // Active high indicates buffer is almost full (at or above 352 samples).
//Port Controller interface.
inout [31:0] pifData, // 32 bit port interface data bus.
input wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
output wire [1:0] portCmd // Port Command ID
);
parameter ADDR_PORT = 0;
parameter NBITS_ADDR = 2;
wire isAddr = (ADDR_PORT == portCtrl[NBITS_ADDR+2:3]);
wire wr_en = isAddr & portCtrl[2];
assign portCmd = (isAddr ) ? ((prog_empty & port_enable) ? `PIFCMD_READ : `PIFCMD_IDLE) : 2'bz;
FiFo512Core32W32R fifo512 (
.rst(reset), // input rst
.wr_clk(portCtrl[0]), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(pifData), // input [31 : 0] din
.wr_en(wr_en), // input wr_en
.rd_en(rd_en & port_enable), // input rd_en
.dout(rd_out), // output [31 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.prog_full(prog_full), // output prog_full threhold at 388 DWORDS
.prog_empty(prog_empty) // output prog_empty threshold at 256 DWORDS
);
endmodule
|
//bug906
import gmcupkg::*;
module gminstdecode
(
output instClassType instClass
/*blah blah blah*/);
always_comb begin
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
end
end
always_comb begin
instClass = '{default:0}; // #1 (see below)
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.iFunc = IFUNC_ADD; // #2
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.isBool = 1'b1;
instClass.iFunc = IFUNC_BOOL;
end
end
always_comb begin
instClass.sub = '0;
instClass.sub2 = '0;
/*AUTORESET*/
if (ldBitFromIo | stBitToIo) begin
instClass.sub.bool = 1'b1;
instClass.sub2.sub3.bool = 1'b1;
instClass.sub3.sub4.bool = 1'b1;
end
end
endmodule
// Local Variables:
// verilog-auto-reset-widths: unbased
// verilog-typedef-regexp: "Type$"
// End:
|
#include <bits/stdc++.h> using namespace std; long long dp[1 << 18][100], d, f[20]; int main() { int m, l, n, i, j, k, c[10]; char a[20]; memset(c, 0, sizeof(c)); for (f[0] = 1, i = 1; i < 20; i++) f[i] = f[i - 1] * i; scanf( %s%d , a, &m); l = strlen(a), n = 1 << l; for (i = 0; i < l; i++) c[a[i] -= 0 ]++; for (d = 1, i = 0; i < 10; i++) d *= f[c[i]]; dp[0][0] = 1; for (i = 0; i < n; i++) for (j = 0; j < l; j++) if (!(i & 1 << j)) for (k = 0; k < m; k++) if (!(i == 0 && a[j] == 0)) dp[i | 1 << j][(k * 10 + a[j]) % m] += dp[i][k]; printf( %I64d n , dp[n - 1][0] / d); return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { long long n, i, s = 0; cin >> n; long long a[n]; for (i = 0; i < n; i++) { cin >> a[i]; } s = s + a[0]; for (i = 1; i < n; i++) { if (a[i] != 1) { s = s + i * (a[i] - 1) + a[i]; } else { s = s + 1; } } cout << s << endl; } int main() { long long t = 1; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { long long n, i, j = 0, x; cin >> n; string s = ; stack<long long> q; deque<long long> d; for (i = 0; i < (n); i++) { cin >> x; d.push_back(x); } q.push(0); while (!d.empty()) { if (d.front() >= q.top() && (d.front() < d.back() || d.back() < q.top())) { q.push(d.front()); s += L ; d.pop_front(); } else if (d.back() >= q.top() && (d.front() >= d.back() || d.front() < q.top())) { q.push(d.back()); s += R ; d.pop_back(); } else break; } cout << q.size() - 1 << n ; cout << s; } }
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.4.1 (win64) Build Tue Jan 30 15:32:00 MST 2018
//Date : Thu Apr 5 01:26:30 2018
//Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &x) { x = 0; char ch = getchar(); long long fh = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) fh = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); x *= fh; } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } template <typename T> void writeln(T x) { write(x); puts( ); } long long qpow(long long a, long long b) { if (b == -1) return 0; long long res = 1; while (b) { if (b & 1) res = res * a % 998244353; a = a * a % 998244353; b >>= 1; } return res; } long long n; long long a[1000005], ans; signed main() { read(n); for (long long i = 1; i <= n; ++i) read(a[i]); for (long long i = 1; i <= n; ++i) { ans += a[i] * qpow(2, n - i) % 998244353; ans %= 998244353; ans += a[i] * qpow(2, n - i - 1) % 998244353 * (n - i) % 998244353; ans %= 998244353; } writeln(ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; void fnc() { int n; cin >> n; cout << n << endl; for (int i = 0; i < n; i++) cout << i + 1 << ; cout << endl; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) fnc(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
divSqrtRecF16_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output outValid,
output [16:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(5, 11, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b0,
a,
b,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF32_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output outValid,
output [32:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(8, 24, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b0,
a,
b,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF64_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output outValid,
output [64:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(11, 53, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b0,
a,
b,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF128_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output outValid,
output [128:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(15, 113, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b0,
a,
b,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF16_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [16:0] a,
input [2:0] roundingMode,
output outValid,
output [16:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(5, 11, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b1,
a,
17'b0,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF32_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [32:0] a,
input [2:0] roundingMode,
output outValid,
output [32:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(8, 24, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b1,
a,
33'b0,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF64_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [64:0] a,
input [2:0] roundingMode,
output outValid,
output [64:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(11, 53, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b1,
a,
65'b0,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
module
divSqrtRecF128_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [128:0] a,
input [2:0] roundingMode,
output outValid,
output [128:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_small#(15, 113, 0)
divSqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b1,
a,
129'b0,
roundingMode,
outValid,
sqrtOpOut,
out,
exceptionFlags
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename flow_t, typename cost_t> struct min_cost_flow { const cost_t COST_INF = numeric_limits<cost_t>::max() / 2; struct edge { int node, rev; flow_t capacity; cost_t cost; edge() {} edge(int _node, int _rev, flow_t _capacity, cost_t _cost) : node(_node), rev(_rev), capacity(_capacity), cost(_cost) {} }; int V = -1, E = 0; vector<vector<edge>> adj; vector<cost_t> dist; vector<int> prev; vector<edge *> prev_edge; bool too_many_bellman_ford_iterations = false; min_cost_flow(int vertices = -1) { if (vertices >= 0) init(vertices); } void init(int vertices) { V = vertices; E = 0; adj.assign(V, {}); dist.resize(V); prev.resize(V); prev_edge.resize(V); too_many_bellman_ford_iterations = false; } void add_directional_edge(int u, int v, flow_t capacity, cost_t cost) { assert(0 <= u && u < V && 0 <= v && v < V); edge uv_edge(v, adj[v].size() + (u == v ? 1 : 0), capacity, cost); edge vu_edge(u, adj[u].size(), 0, -cost); adj[u].push_back(uv_edge); adj[v].push_back(vu_edge); E++; } edge &reverse_edge(const edge &e) { return adj[e.node][e.rev]; } bool bellman_ford(int source, int sink) { for (int i = 0; i < V; i++) { dist[i] = COST_INF; prev[i] = -1; prev_edge[i] = nullptr; } long long work = 0; vector<int> last_seen(V, -1); vector<int> nodes = {source}, next_nodes; dist[source] = 0; for (int iteration = 0; iteration < V; iteration++) { next_nodes.clear(); for (int node : nodes) { for (edge &e : adj[node]) if (e.capacity > 0 && dist[node] + e.cost < dist[e.node]) { dist[e.node] = dist[node] + e.cost; prev[e.node] = node; prev_edge[e.node] = &e; if (last_seen[e.node] != iteration) { last_seen[e.node] = iteration; next_nodes.push_back(e.node); } } work += adj[node].size(); } swap(nodes, next_nodes); } if (work > 1.75 * E * (32 - __builtin_clz(V)) + 100) too_many_bellman_ford_iterations = true; return prev[sink] != -1; } struct dijkstra_state { cost_t dist; int node; dijkstra_state() {} dijkstra_state(cost_t _dist, int _node) : dist(_dist), node(_node) {} bool operator<(const dijkstra_state &other) const { return dist > other.dist; } }; void dijkstra_check(int node, cost_t potential_dist, int previous, edge *previous_edge, priority_queue<dijkstra_state> &pq) { if (potential_dist < dist[node]) { dist[node] = potential_dist; prev[node] = previous; prev_edge[node] = previous_edge; pq.emplace(dist[node], node); } } bool dijkstra(int source, int sink) { dist.assign(V, COST_INF); prev.assign(V, -1); prev_edge.assign(V, nullptr); priority_queue<dijkstra_state> pq; dijkstra_check(source, 0, -1, nullptr, pq); while (!pq.empty()) { dijkstra_state top = pq.top(); pq.pop(); if (top.dist > dist[top.node]) continue; for (edge &e : adj[top.node]) if (e.capacity > 0) dijkstra_check(e.node, top.dist + e.cost, top.node, &e, pq); } return prev[sink] != -1; } void reduce_cost() { for (int i = 0; i < V; i++) for (edge &e : adj[i]) if (dist[i] < COST_INF && dist[e.node] < COST_INF) e.cost += dist[i] - dist[e.node]; } vector<pair<flow_t, cost_t>> options; pair<flow_t, cost_t> solve_min_cost_flow( int source, int sink, flow_t flow_goal = numeric_limits<flow_t>::max()) { assert(V >= 0); flow_t total_flow = 0; cost_t total_cost = 0; while (total_flow < flow_goal && bellman_ford(source, sink)) { if (too_many_bellman_ford_iterations) break; flow_t path_cap = flow_goal - total_flow; cost_t cost_sum = 0; for (int node = sink; prev[node] != -1; node = prev[node]) path_cap = min(path_cap, prev_edge[node]->capacity); for (int node = sink; prev[node] != -1; node = prev[node]) { edge *e = prev_edge[node]; e->capacity -= path_cap; reverse_edge(*e).capacity += path_cap; cost_sum += e->cost; } total_flow += path_cap; total_cost += cost_sum * path_cap; options.emplace_back(total_flow, total_cost); } if (too_many_bellman_ford_iterations) { cost_t reduce_sum = 0; do { reduce_cost(); reduce_sum += dist[sink]; flow_t path_cap = flow_goal - total_flow; for (int node = sink; prev[node] != -1; node = prev[node]) path_cap = min(path_cap, prev_edge[node]->capacity); for (int node = sink; prev[node] != -1; node = prev[node]) { edge *e = prev_edge[node]; assert(e->cost == 0); e->capacity -= path_cap; reverse_edge(*e).capacity += path_cap; } total_flow += path_cap; total_cost += reduce_sum * path_cap; options.emplace_back(total_flow, total_cost); } while (total_flow < flow_goal && dijkstra(source, sink)); } return make_pair(total_flow, total_cost); } }; int main() { int N, M; scanf( %d %d , &N, &M); min_cost_flow<int, long long> graph(N); for (int i = 0; i < M; i++) { int u, v, weight; scanf( %d %d %d , &u, &v, &weight); u--; v--; graph.add_directional_edge(u, v, 1, weight); } graph.solve_min_cost_flow(0, N - 1); int Q; scanf( %d , &Q); for (int q = 0; q < Q; q++) { int x; scanf( %d , &x); double answer = 1e100; for (auto &option : graph.options) answer = min(answer, (double)(option.second + x) / option.first); printf( %.7lg n , answer); } }
|
#include <bits/stdc++.h> #pragma hdrstop using namespace std; void rot(int n, int *x, int *y, int rx, int ry); int xy2d(int n, int x, int y) { int rx, ry, s, d = 0; for (s = n / 2; s > 0; s /= 2) { rx = (x & s) > 0; ry = (y & s) > 0; d += s * s * ((3 * rx) ^ ry); rot(s, &x, &y, rx, ry); } return d; } void d2xy(int n, int d, int *x, int *y) { int rx, ry, s, t = d; *x = *y = 0; for (s = 1; s < n; s *= 2) { rx = 1 & (t / 2); ry = 1 & (t ^ rx); rot(s, x, y, rx, ry); *x += s * rx; *y += s * ry; t /= 4; } } void rot(int n, int *x, int *y, int rx, int ry) { int t; if (ry == 0) { if (rx == 1) { *x = n - 1 - *x; *y = n - 1 - *y; } t = *x; *x = *y; *y = t; } } #pragma argsused int main(int argc, char *argv[]) { int a, b; cin >> a >> b; int x, y; d2xy(1 << a, b, &x, &y); cout << x << << y << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A31O_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; int gcd(int n, int m) { if (m == 0) return n; return gcd(m, n % m); } int lcm(int n, int m) { return n * m / gcd(n, m); } ll fact(ll n) { if (n == 1 or n == 0) return 1; else return ((n % 1000000007) * (fact(n - 1) % 1000000007)) % 1000000007; } template <typename T> T modpow(T base, T exp) { base %= 1000000007; T result = 1; while (exp > 0) { if (exp & 1) (result *= base) %= 1000000007; (base *= base) %= 1000000007; exp >>= 1; } return result; } int bin_search(vector<int>& a, int ele) { int lo = 0, hi = a.size() - 1; while (lo <= hi) { int mid = lo + (hi - lo) / 2; if (mid == 0 or mid == a.size() - 1) return mid; else if (a[mid] >= ele and a[mid - 1] < ele) return mid; else if (a[mid] >= ele) hi = mid - 1; else lo = mid + 1; } } bool ifPrime(int n) { for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) return 0; } return 1; } void solve(int testno) { string s; cin >> s; string orig = s; bool no = 1; for (char& c : s) { if (c == 9 and no) { no = 0; continue; } no = 0; if (c - 0 >= 5) { c = 0 + ( 9 - c); } } cout << s; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin.exceptions(ios::badbit | ios::failbit); int t = 1; for (int i = 1; i <= t; i++) { solve(i); } return 0; }
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for min_max_tracker
`include "min_max_tracker.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
module min_max_tracker_tb;
integer fin;
integer fout_min, fout_max;
integer r;
reg clk;
reg [7:0] adc_d;
wire [7:0] min;
wire [7:0] max;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t min: %x, max: %x", $time, min, max);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
end
// module to test
min_max_tracker tracker(clk, adc_d, 8'd127, min, max);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; const long long INF = 1e9 + 5; const long long mod = 1e9 + 7; const double pi = 3.1415926536; int main() { ios::sync_with_stdio(0); cin.tie(0); ios_base::sync_with_stdio(0); ; int n, m; cin >> n >> m; bool valid = false; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int x; cin >> x; if (x == 1 && (i == 0 || j == 0 || i == (n - 1) || j == (m - 1))) valid = true; } } if (valid) cout << 2 n ; else cout << 4 n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class T> inline T sqr(T x) { return x * x; } const double EPS = 1e-10; const double PI = acos(-1.0); const int dx[] = {-1, 1, 0, 0}; const int dy[] = {0, 0, 1, -1}; int n, k, ret; bool us[11]; int main() { cin >> n >> k; for (int i = (0); i < (n); ++i) { string s; bool f = true; cin >> s; for (int j = (0); j < (10); ++j) us[j] = false; for (int j = (0); j < (s.size()); ++j) us[s[j] - 0 ] = true; for (int j = (0); j < (k + 1); ++j) if (!us[j]) f = false; ret += f; } cout << ret << endl; return 0; }
|
module DecodeUnitRegisterOne(
input CLK, One_A_IN, One_B_IN, Two_A_IN, Two_B_IN, MW_One_IN, MW_Two_IN,
input input_IN, wren_IN,
input [2:0] writeAd_IN,
input ADR_MUX_IN, write_IN, PC_load_IN,
input SPR_w_IN, SPR_i_IN, SPR_d_IN,
input [2:0] cond_IN, op2_IN,
input SW_IN, MAD_MUX_IN, FLAG_WRITE_IN, AR_IN, BR_IN,
input [3:0] ALU_IN,
input SPC_MUX_IN, MX_MUX_IN, AB_MUX_IN,
output One_A_OUT, One_B_OUT, Two_A_OUT, Two_B_OUT, MW_One_OUT, MW_Two_OUT,
output input_OUT, wren_OUT,
output [2:0] writeAd_OUT,
output ADR_MUX_OUT, write_OUT, PC_load_OUT,
output SPR_w_OUT, SPR_i_OUT, SPR_d_OUT,
output [2:0] cond_OUT, op2_OUT,
output SW_OUT, MAD_MUX_OUT, FLAG_WRITE_OUT, AR_OUT, BR_OUT,
output [3:0] ALU_OUT,
output SPC_MUX_OUT, MX_MUX_OUT, AB_MUX_OUT);
reg oa, ob, ta, tb;
reg ar, br;
reg [3:0] alu;
reg in, wren;
reg [2:0] writeAd;
reg adrmux, write, pcload;
reg [2:0] cond, opera2;
reg sprw,spri,sprd;
reg sw, mad, flw;
reg spc, mx, ab;
reg mwo, mwt;
always @ (posedge CLK) begin
mwo <= MW_One_IN;
mwt <= MW_Two_IN;
oa <= One_A_IN;
ob <= One_B_IN;
ta <= Two_A_IN;
tb <= Two_B_IN;
ar <= AR_IN;
br <= BR_IN;
alu <= ALU_IN;
in <= input_IN;
wren <= wren_IN;
writeAd <= writeAd_IN;
adrmux <= ADR_MUX_IN;
write <= write_IN;
pcload <= PC_load_IN;
cond <= cond_IN;
opera2 <= op2_IN;
sprw <= SPR_w_IN;
spri <= SPR_i_IN;
sprd <= SPR_d_IN;
sw <= SW_IN;
mad <= MAD_MUX_IN;
spc <= SPC_MUX_IN;
mx <= MX_MUX_IN;
ab <= AB_MUX_IN;
flw <= FLAG_WRITE_IN;
end // always @ (posedge CLK)
assign MW_One_OUT = mwo;
assign MW_Two_OUT = mwt;
assign One_A_OUT = oa;
assign One_B_OUT = ob;
assign Two_A_OUT = ta;
assign Two_B_OUT = tb;
assign AR_OUT = ar;
assign BR_OUT = br;
assign ALU_OUT = alu;
assign input_OUT = in;
assign wren_OUT = wren;
assign writeAd_OUT = writeAd;
assign ADR_MUX_OUT = adrmux;
assign write_OUT = write;
assign PC_load_OUT = pcload;
assign cond_OUT = cond;
assign op2_OUT = opera2;
assign SPR_w_OUT = sprw;
assign SPR_i_OUT = spri;
assign SPR_d_OUT = sprd;
assign SW_OUT = sw;
assign MAD_MUX_OUT = mad;
assign FLAG_WRITE_OUT = flw;
assign SPC_MUX_OUT = spc;
assign MX_MUX_OUT = mx;
assign AB_MUX_OUT = ab;
endmodule // DecodeUnitRegisterOne
|
/*
* Arithmetic Logic Unit for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module zet_alu (
input [31:0] x,
input [15:0] y,
output [31:0] out,
input [ 2:0] t,
input [ 2:0] func,
input [15:0] iflags,
output [ 8:0] oflags,
input word_op,
input [15:0] seg,
input [15:0] off,
input clk,
output div_exc
);
// Net declarations
wire [15:0] add, log, rot;
wire [15:0] arl;
wire [8:0] othflags;
wire [19:0] oth;
wire [31:0] cnv, mul;
wire af_add, af_cnv, af_arl;
wire cf_cnv, cf_add, cf_mul, cf_log, cf_arl, cf_rot;
wire of_cnv, of_add, of_mul, of_log, of_arl, of_rot;
wire ofi, sfi, zfi, afi, pfi, cfi;
wire ofo, sfo, zfo, afo, pfo, cfo;
wire flags_unchanged;
wire dexc;
// Module instances
zet_addsub addsub (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
zet_conv conv (
.x (x[15:0]),
.func (func),
.out (cnv),
.iflags ({afi, cfi}),
.oflags ({af_cnv, of_cnv, cf_cnv})
);
zet_muldiv muldiv (
.x (x),
.y (y),
.o (mul),
.f (func),
.word_op (word_op),
.cfo (cf_mul),
.ofo (of_mul),
.clk (clk),
.exc (dexc)
);
zet_bitlog bitlog (
.x (x[15:0]),
.o (log),
.cfo (cf_log),
.ofo (of_log)
);
zet_arlog arlog (
.x (x[15:0]),
.y (y),
.f (func),
.o (arl),
.word_op (word_op),
.cfi (cfi),
.cfo (cf_arl),
.afo (af_arl),
.ofo (of_arl)
);
zet_shrot shrot (
.x (x[15:0]),
.y (y[7:0]),
.out (rot),
.func (func),
.word_op (word_op),
.cfi (cfi),
.ofi (ofi),
.cfo (cf_rot),
.ofo (of_rot)
);
zet_othop othop (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
zet_mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
mul[15:0], log, arl, rot, oth[15:0], out[15:0]);
zet_mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
zet_mux8_1 a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_arl, cf_rot, 1'b0, cfo);
zet_mux8_1 a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, af_arl, afi, 1'b0, afo);
zet_mux8_1 a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_arl, of_rot, 1'b0, ofo);
// Flags
assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
assign zfo = flags_unchanged ? zfi
: ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
assign sfo = flags_unchanged ? sfi
: ((word_op && (t!=3'd2)) ? out[15] : out[7]);
assign oflags = (t == 3'd7) ? othflags
: { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
assign ofi = iflags[11];
assign sfi = iflags[7];
assign zfi = iflags[6];
assign afi = iflags[4];
assign pfi = iflags[2];
assign cfi = iflags[0];
assign flags_unchanged = (t == 3'd4
|| t == 3'd6 && (!func[2] || func[2]&&y[4:0]==5'h0));
assign div_exc = func[1] && (t==3'd3) && dexc;
endmodule
|
module rfa(/*AUTOARG*/
// Outputs
simd0_queue_entry_serviced, simd1_queue_entry_serviced,
simd2_queue_entry_serviced, simd3_queue_entry_serviced,
simf0_queue_entry_serviced, simf1_queue_entry_serviced,
simf2_queue_entry_serviced, simf3_queue_entry_serviced,
execvgprsgpr_select_fu,
//**CHANGE [PSP]
//add req_sat_output and lsu_wait signal
lsu_wait, //
// Inputs
clk, rst, simd0_queue_entry_valid, simd1_queue_entry_valid,
simd2_queue_entry_valid, simd3_queue_entry_valid,
simf0_queue_entry_valid, simf1_queue_entry_valid,
simf2_queue_entry_valid, simf3_queue_entry_valid, lsu_dest_wr_req,
//**CHANGE [PSP]
//add salu_req input
salu_req
);
input clk;
input rst;
//**CHANGE [PSP]
input salu_req;
output lsu_wait;
//**
input simd0_queue_entry_valid, simd1_queue_entry_valid, simd2_queue_entry_valid,
simd3_queue_entry_valid, simf0_queue_entry_valid, simf1_queue_entry_valid,
simf2_queue_entry_valid, simf3_queue_entry_valid, lsu_dest_wr_req;
output simd0_queue_entry_serviced, simd1_queue_entry_serviced, simd2_queue_entry_serviced,
simd3_queue_entry_serviced, simf0_queue_entry_serviced, simf1_queue_entry_serviced,
simf2_queue_entry_serviced, simf3_queue_entry_serviced;
output [15:0] execvgprsgpr_select_fu;
wire [15:0] entry_valid;
wire [15:0] entry_serviced;
wire [15:0] shifted_valid;
wire [3:0] highest_priority, next_highest_priority;
wire [3:0] cur_priority;
wire [31:0] dummy_entry_serviced;
wire [31:0] dummy_next_highest_priority;
//**change [psp]
wire lsu_wait;
wire lsu_wr_req_lp;
// If lsu requests writes, it bypasses the priority encoder
// but if salu request writes, it bypasses both
assign entry_valid = salu_req ? {8'd0, simf3_queue_entry_valid, simf2_queue_entry_valid,
simf1_queue_entry_valid, simf0_queue_entry_valid,
simd3_queue_entry_valid, simd2_queue_entry_valid,
simd1_queue_entry_valid, simd0_queue_entry_valid} &
{16{~salu_req}}:{8'd0, simf3_queue_entry_valid, simf2_queue_entry_valid,
simf1_queue_entry_valid, simf0_queue_entry_valid,
simd3_queue_entry_valid, simd2_queue_entry_valid,
simd1_queue_entry_valid, simd0_queue_entry_valid} &
{16{~lsu_dest_wr_req}}
;
assign lsu_wr_req_lp = salu_req ? 1'b0:lsu_dest_wr_req;
assign lsu_wait = salu_req;
//**
assign {simf3_queue_entry_serviced, simf2_queue_entry_serviced,
simf1_queue_entry_serviced, simf0_queue_entry_serviced,
simd3_queue_entry_serviced, simd2_queue_entry_serviced,
simd1_queue_entry_serviced, simd0_queue_entry_serviced}
= entry_serviced[7:0];
//**CHANGE lsu_dest_wr_req to lsu_wr_req_lp
//and add in the salu_req signal
// If lsu requested, then entry_serviced will be 0
assign execvgprsgpr_select_fu = { {6{1'b0}}, salu_req, lsu_wr_req_lp, entry_serviced[7:0]};
//**
dff_en high_pr_flop[3:0]
(highest_priority,
next_highest_priority,
|entry_valid,
clk, rst);
circular_shift circ_shift (
.out(shifted_valid),
.in(entry_valid),
.shift_amount(highest_priority)
);
priority_encoder_16_to_4 priority_encoder (
.out(cur_priority),
.in(shifted_valid),
.enable(1'b1)
);
assign dummy_entry_serviced = cur_priority + highest_priority;
assign dummy_next_highest_priority = dummy_entry_serviced + 1;
assign next_highest_priority = dummy_next_highest_priority[3:0];
decoder_param_en
#(.BITS(4), .SIZE(16))
entry_serviced_decoder
(.out(entry_serviced), .
in(dummy_entry_serviced[3:0]),
.en(|entry_valid));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long T, n, k; cin >> T; for (int i = 0; i < T; i++) { cin >> n >> k; cout << k * 2 << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n, k, l = 9999, j = 9999, s, i; cin >> n >> m >> k; int a[n + 3]; for (i = 1; i <= n; i++) cin >> a[i]; for (i = m + 1; i <= n; i++) { if (a[i] != 0 && a[i] <= k) { l = (i - m); break; } } for (i = m - 1; i >= 1; i--) { if (a[i] != 0 && a[i] <= k) { j = (m - i); break; } } s = min(j, l); cout << s * 10; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_PP_V
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "lo_read.v"
`include "lo_passthru.v"
`include "lo_edge_detect.v"
`include "hi_read_tx.v"
`include "hi_read_rx_xcorr.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "util.v"
module fpga(
spck, miso, mosi, ncs,
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spck, mosi, ncs;
output miso;
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
//assign pck0 = pck0i;
// IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
// .O(pck0),
// .I(pck0i)
// );
//assign spck = spcki;
// IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(
// .O(spck),
// .I(spcki)
// );
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [7:0] divisor;
reg [7:0] conf_word;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire [2:0] major_mode;
assign major_mode = conf_word[7:5];
// For the low-frequency configuration:
wire lo_is_125khz;
assign lo_is_125khz = conf_word[3];
// For the high-frequency transmit configuration: modulation depth, either
// 100% (just quite driving antenna, steady LOW), or shallower (tri-state
// some fraction of the buffers)
wire hi_read_tx_shallow_modulation;
assign hi_read_tx_shallow_modulation = conf_word[0];
// For the high-frequency receive correlator: frequency against which to
// correlate.
wire hi_read_rx_xcorr_848;
assign hi_read_rx_xcorr_848 = conf_word[0];
// and whether to drive the coil (reader) or just short it (snooper)
wire hi_read_rx_xcorr_snoop;
assign hi_read_rx_xcorr_snoop = conf_word[1];
// Divide the expected subcarrier frequency for hi_read_rx_xcorr by 4
wire hi_read_rx_xcorr_quarter;
assign hi_read_rx_xcorr_quarter = conf_word[2];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
// For the high-frequency simulated tag: what kind of modulation to use.
wire lf_field;
assign lf_field = conf_word[0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
lo_read lr(
pck0, ck_1356meg, ck_1356megb,
lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
adc_d, lr_adc_clk,
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
cross_hi, cross_lo,
lr_dbg,
lo_is_125khz, divisor
);
lo_passthru lp(
pck0, ck_1356meg, ck_1356megb,
lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,
adc_d, lp_adc_clk,
lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,
cross_hi, cross_lo,
lp_dbg, divisor
);
lo_edge_detect ls(
pck0, ck_1356meg, ck_1356megb,
ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
adc_d, ls_adc_clk,
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
cross_hi, cross_lo,
ls_dbg, divisor,
lf_field
);
hi_read_tx ht(
pck0, ck_1356meg, ck_1356megb,
ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
adc_d, ht_adc_clk,
ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
cross_hi, cross_lo,
ht_dbg,
hi_read_tx_shallow_modulation
);
hi_read_rx_xcorr hrxc(
pck0, ck_1356meg, ck_1356megb,
hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
adc_d, hrxc_adc_clk,
hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
cross_hi, cross_lo,
hrxc_dbg,
hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop, hi_read_rx_xcorr_quarter
);
hi_simulate hs(
pck0, ck_1356meg, ck_1356megb,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
cross_hi, cross_lo,
hs_dbg,
hi_simulate_mod_type
);
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
hisn_dbg,
hi_simulate_mod_type
);
// Major modes:
// 000 -- LF reader (generic)
// 001 -- LF simulated tag (generic)
// 010 -- HF reader, transmitting to tag; modulation depth selectable
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
// 100 -- HF simulated tag
// 101 -- HF ISO14443-A
// 110 -- LF passthrough
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);
mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[100005]; int main() { int n; while (cin >> n) { scanf( %s , s); int ct = 1, n = strlen(s); bool ok = false; int cant = 0, ans = 0; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) ct++; else { if (ct >= 3) ok = true; if (ct >= 2) cant++; ans++; ct = 1; } } ans++; if (ct >= 3) ok = true; if (ct >= 2) cant++; if (ok) ans += 2; else { if (cant >= 2) ans += 2; else if (cant == 1) ans++; } cout << ans << endl; } }
|
module barrel
#(parameter width=16)
(input [width-1:0] in,
input [$clog2(width)-1:0] ct,
input dir,
input [1:0] type,
output [width-1:0] out);
/* direct inputs = f */
/* shifted inputs = g */
/* mux outputs = h */
wire [width-1:0] f[$clog2(width)-1:0], g[$clog2(width)-1:0], h[$clog2(width):0];
assign h[0] = in;
assign out = h[$clog2(width)-1];
generate
genvar i;
for(i = 0; i < $clog2(width) - 1; i = i+1) begin : a
magic#(.width(width), .shift(2**i)) v(h[i], type, left, g[i]);
mux2 #(.width(width)) u(h[i], g[i], ct[$clog2(width)-i-1], h[i+1]);
end
endgenerate
endmodule
module magic
#(parameter width = 16,
parameter shift = $clog2(width))
(input [width-1:0]h,
input [1:0]type,
input left,
output reg [width-1:0]z);
localparam NS=0, LO=1, AR=2, RO=3;
always @(*) if (left) begin
case(type)
NS: z <= h;
LO: z <= h << shift;
AR: z <= h <<< shift;
RO: z <= { h[width-1-shift:0], h[width-1:width-1-shift-1] };
endcase
end else begin
case(type)
NS: z <= h;
LO: z <= h >> shift;
AR: z <= h >>> shift;
RO: z <= { h[width-1:width-1-shift-1], h[width-1-shift:0] };
endcase
end
endmodule
module mux2
#(parameter width=16)
(input [width-1:0] A, B,
input sel,
output [width-1:0] out);
assign out = sel ? A : B;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 12963 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w128,
w385,
w1028,
w643,
w12320,
w12963;
assign w1 = i_data0;
assign w1028 = w257 << 2;
assign w12320 = w385 << 5;
assign w128 = w1 << 7;
assign w12963 = w643 + w12320;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w385 = w257 + w128;
assign w643 = w1028 - w385;
assign o_data0 = w12963;
//multiplier_block area estimate = 7304.77445403088;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_4_V
`define SKY130_FD_SC_LP__BUFLP_4_V
/**
* buflp: Buffer, Low Power.
*
* Verilog wrapper for buflp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buflp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buflp_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buflp base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_N_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBN_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave_b2b
* this module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b256(
clk,sck,mosi,miso,ssel,rst_n,recived_status,spi_sel
);
input clk;
input rst_n;
input sck,mosi,ssel;
input spi_sel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
reg [7:0] first_byte;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
if(spi_sel)
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
else begin
if((bytecnt == 'h0 && byte_data_received == 'h2) || first_byte == 8'h2)
received_memory <= (byte_data_received == bytecnt + 'h2) ? (received_memory + 1'b1) : received_memory;
else
received_memory <= (byte_data_received == bytecnt + 'h1) ? (received_memory + 1'b1) : received_memory;
end
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
first_byte <= 'h0;
else if(bytecnt == 'h0 && byte_data_received == 'h2)
first_byte <= byte_data_received;
else
first_byte <= first_byte;
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h1;
else begin
if((first_byte == 8'h2) && (!recived_status))
cnt<= 8'h2;
else if(byte_received && recived_status)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
reg [7:0] byte_data_sent_reg;
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
byte_data_sent <= 8'hff;
byte_data_sent_reg <= 8'hff;
end
else begin
byte_data_sent <= spi_sel ? 8'hff : 8'h0;
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)begin
byte_data_sent <= spi_sel ? byte_data_sent_reg - 1'b1 : cnt; // after that, we send 0s
byte_data_sent_reg <= byte_data_sent_reg - 1'b1;
end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else begin
if(spi_sel)
recived_status <= (received_memory == 8'd256) ? 1'b1 : 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[5000]; int main() { int n, k, l, r, s, sk; cin >> n >> k >> l >> r >> s >> sk; int d = s - sk; for (int i = 1; i <= k; i++) { a[i] = sk / k; if (sk % k != 0) { a[i]++; sk--; } } if (k != n) { for (int i = k + 1; i <= n; i++) { a[i] = d / (n - k); if (d % (n - k) != 0) { a[i]++; d--; } } } for (int i = 1; i <= n; i++) cout << a[i] << ; cout << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int steps, count, i, n; char str[500]; char pc; scanf( %s , str); steps = count = 0; n = strlen(str); if (n == 0) { printf( 0 n ); return 0; } pc = str[0]; count = 1; for (i = 1; i < n; i++) { if (count == 5) { count = 1; steps++; pc = str[i]; continue; } if (pc == str[i]) count++; else { count = 1; steps++; pc = str[i]; } } if (count > 0) steps++; printf( %d n , steps); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[1002][20002]; int main() { ios_base::sync_with_stdio; int n, m, x, y, i, j, a; cin >> n; long long ans = 0; for (i = 1; i <= n; i++) { cin >> a; for (j = 0; j < a; j++) { dp[i][j] = dp[i - 1][j + a]; } for (j = 20000; j > 20000 - a; j--) { dp[i][j] = dp[i - 1][j - a]; } for (j = a; j <= 20000 - a; j++) { dp[i][j] = (dp[i - 1][j - a] + dp[i - 1][j + a]) % 1000000007; } dp[i][10000 + a] = (dp[i][10000 + a] + 1) % 1000000007; ; dp[i][10000 - a] = (dp[i][10000 - a] + 1) % 1000000007; ans = (ans + dp[i][10000]) % 1000000007; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int read() { int s = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) s = s * 10 + ch - 0 , ch = getchar(); return s; } inline char getch() { char ch = getchar(); while (!islower(ch)) ch = getchar(); return ch; } const int N = 20005; int n, m, u, v, x, y, c1, c2, ans; int dfn[N], dep[N], fa[N], dfn_t, pos[N], ab[N]; int tag[N], len[N], type[N]; char s[N], t[N], fw[N]; vector<pair<int, char> > G[N]; void dfs(int u, int f) { dep[u] = dep[f] + 1, fa[u] = f; dfn[u] = ++dfn_t, pos[dfn_t] = u; ab[dfn[u]] = dfn[f]; for (auto v : G[u]) { if (v.first == f) continue; fw[v.first] = v.second; dfs(v.first, u); } } int main() { n = read(), m = read(); for (int i = 1; i < n; i++) { u = read(), v = read(); char c = getch(); G[u].emplace_back(v, c); G[v].emplace_back(u, c); } dfs(1, 0); for (int T = 1; T <= m; T++) { memset(s + 1, 0, n * sizeof(char)); u = x = read(), v = y = read(); c1 = c2 = 0; while (u != v) dep[u] > dep[v] ? (s[++c1] = fw[u], u = fa[u]) : (t[++c2] = fw[v], v = fa[v]); for (; c2;) s[++c1] = t[c2--]; type[dfn[x]] = len[dfn[x]] = 0, tag[dfn[x]] = T; ans = 0; for (int i = dfn[x]; ab[i];) { tag[ab[i]] = T, len[ab[i]] = len[i] + 1; type[ab[i]] = (type[i] ? type[i] : ((fw[pos[i]] > s[len[ab[i]]]) - (fw[pos[i]] < s[len[ab[i]]]))); i = ab[i]; if (type[i] == -1 || (!type[i] && len[i] < c1)) ++ans; } for (int i = 2; i <= n; i++) { if (tag[i] != T) { len[i] = len[ab[i]] + 1; type[i] = (type[ab[i]] ? type[ab[i]] : ((fw[pos[i]] > s[len[i]]) - (fw[pos[i]] < s[len[i]]))); if (type[i] == -1 || (!type[i] && len[i] < c1)) ++ans; } } printf( %d n , ans); } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Hex display driver
//
// File: display_16hex.v
// Date: 24-Sep-05
//
// Created: April 27, 2004
// Author: Nathan Ickes
//
// 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear
// 28-Nov-06 CJT: fixed race condition between CE and RS (thanks Javier!)
//
// This verilog module drives the labkit hex dot matrix displays, and puts
// up 16 hexadecimal digits (8 bytes). These are passed to the module
// through a 64 bit wire ("data"), asynchronously.
//
///////////////////////////////////////////////////////////////////////////////
module display_16hex (reset, clock_27mhz, data,
disp_blank, disp_clock, disp_rs, disp_ce_b,
disp_reset_b, disp_data_out);
input reset, clock_27mhz; // clock and reset (active high reset)
input [63:0] data; // 16 hex nibbles to display
output disp_blank, disp_clock, disp_data_out, disp_rs, disp_ce_b,
disp_reset_b;
reg disp_data_out, disp_rs, disp_ce_b, disp_reset_b;
////////////////////////////////////////////////////////////////////////////
//
// Display Clock
//
// Generate a 500kHz clock for driving the displays.
//
////////////////////////////////////////////////////////////////////////////
reg [4:0] count;
reg [7:0] reset_count;
reg clock;
wire dreset;
always @(posedge clock_27mhz)
begin
if (reset)
begin
count = 0;
clock = 0;
end
else if (count == 26)
begin
clock = ~clock;
count = 5'h00;
end
else
count = count+1;
end
always @(posedge clock_27mhz)
if (reset)
reset_count <= 100;
else
reset_count <= (reset_count==0) ? 0 : reset_count-1;
assign dreset = (reset_count != 0);
assign disp_clock = ~clock;
////////////////////////////////////////////////////////////////////////////
//
// Display State Machine
//
////////////////////////////////////////////////////////////////////////////
reg [7:0] state; // FSM state
reg [9:0] dot_index; // index to current dot being clocked out
reg [31:0] control; // control register
reg [3:0] char_index; // index of current character
reg [39:0] dots; // dots for a single digit
reg [3:0] nibble; // hex nibble of current character
assign disp_blank = 1'b0; // low <= not blanked
always @(posedge clock)
if (dreset)
begin
state <= 0;
dot_index <= 0;
control <= 32'h7F7F7F7F;
end
else
casex (state)
8'h00:
begin
// Reset displays
disp_data_out <= 1'b0;
disp_rs <= 1'b0; // dot register
disp_ce_b <= 1'b1;
disp_reset_b <= 1'b0;
dot_index <= 0;
state <= state+1;
end
8'h01:
begin
// End reset
disp_reset_b <= 1'b1;
state <= state+1;
end
8'h02:
begin
// Initialize dot register (set all dots to zero)
disp_ce_b <= 1'b0;
disp_data_out <= 1'b0; // dot_index[0];
if (dot_index == 639)
state <= state+1;
else
dot_index <= dot_index+1;
end
8'h03:
begin
// Latch dot data
disp_ce_b <= 1'b1;
dot_index <= 31; // re-purpose to init ctrl reg
disp_rs <= 1'b1; // Select the control register
state <= state+1;
end
8'h04:
begin
// Setup the control register
disp_ce_b <= 1'b0;
disp_data_out <= control[31];
control <= {control[30:0], 1'b0}; // shift left
if (dot_index == 0)
state <= state+1;
else
dot_index <= dot_index-1;
end
8'h05:
begin
// Latch the control register data / dot data
disp_ce_b <= 1'b1;
dot_index <= 39; // init for single char
char_index <= 15; // start with MS char
state <= state+1;
disp_rs <= 1'b0; // Select the dot register
end
8'h06:
begin
// Load the user's dot data into the dot reg, char by char
disp_ce_b <= 1'b0;
disp_data_out <= dots[dot_index]; // dot data from msb
if (dot_index == 0)
if (char_index == 0)
state <= 5; // all done, latch data
else
begin
char_index <= char_index - 1; // goto next char
dot_index <= 39;
end
else
dot_index <= dot_index-1; // else loop thru all dots
end
endcase
always @ (data or char_index)
case (char_index)
4'h0: nibble <= data[3:0];
4'h1: nibble <= data[7:4];
4'h2: nibble <= data[11:8];
4'h3: nibble <= data[15:12];
4'h4: nibble <= data[19:16];
4'h5: nibble <= data[23:20];
4'h6: nibble <= data[27:24];
4'h7: nibble <= data[31:28];
4'h8: nibble <= data[35:32];
4'h9: nibble <= data[39:36];
4'hA: nibble <= data[43:40];
4'hB: nibble <= data[47:44];
4'hC: nibble <= data[51:48];
4'hD: nibble <= data[55:52];
4'hE: nibble <= data[59:56];
4'hF: nibble <= data[63:60];
endcase
always @(nibble)
case (nibble)
4'h0: dots <= 40'b00111110_01010001_01001001_01000101_00111110;
4'h1: dots <= 40'b00000000_01000010_01111111_01000000_00000000;
4'h2: dots <= 40'b01100010_01010001_01001001_01001001_01000110;
4'h3: dots <= 40'b00100010_01000001_01001001_01001001_00110110;
4'h4: dots <= 40'b00011000_00010100_00010010_01111111_00010000;
4'h5: dots <= 40'b00100111_01000101_01000101_01000101_00111001;
4'h6: dots <= 40'b00111100_01001010_01001001_01001001_00110000;
4'h7: dots <= 40'b00000001_01110001_00001001_00000101_00000011;
4'h8: dots <= 40'b00110110_01001001_01001001_01001001_00110110;
4'h9: dots <= 40'b00000110_01001001_01001001_00101001_00011110;
4'hA: dots <= 40'b01111110_00001001_00001001_00001001_01111110;
4'hB: dots <= 40'b01111111_01001001_01001001_01001001_00110110;
4'hC: dots <= 40'b00111110_01000001_01000001_01000001_00100010;
4'hD: dots <= 40'b01111111_01000001_01000001_01000001_00111110;
4'hE: dots <= 40'b01111111_01001001_01001001_01001001_01000001;
4'hF: dots <= 40'b01111111_00001001_00001001_00001001_00000001;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXBN_PP_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, n, t, r = 0; cin >> a >> b >> c >> n; for (int i = 0; i < n; i++) { cin >> t; if (t > b && t < c) r++; } cout << r << endl; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 7; const double eps = 1e-9; int a[maxn]; int main() { std::ios::sync_with_stdio(false); int n, sum = 0; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i], sum += a[i]; sort(a, a + n); int ans = 0; while (fabs(round(1.0 * sum / n) - 5.0) > eps) { sum += 5 - a[0]; ++ans; a[0] = 5; sort(a, a + n); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 8; int main() { char r1, r2; int x1, x2; while (4 == scanf( %c%d %c%d , &r1, &x1, &r2, &x2)) { int y1 = r1 - a ; int y2 = r2 - a ; --x1; --x2; int ans = 0; for (int y = 0; y < (int)(N); y++) for (int x = 0; x < (int)(N); x++) { if (y1 == y || x1 == x) continue; int dx1 = abs(x1 - x), dy1 = abs(y1 - y); int dx2 = abs(x2 - x), dy2 = abs(y2 - y); if (dx1 > dy1) swap(dx1, dy1); if (dx2 > dy2) swap(dx2, dy2); if (dx1 == 1 && dy1 == 2) continue; if (dx2 == 1 && dy2 == 2) continue; if (dx2 == 0 && dy2 == 0) continue; ++ans; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxval = 2e6 + 6; int b[maxval]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); b[a] = a; } for (int i = 0; i < maxval; i++) if (!b[i]) b[i] = b[i - 1]; int ans = 0; for (int i = 2; i < maxval / 2; i++) { if (b[i] == i) { for (int j = i - 1; j < maxval; j += i) { if (j < maxval && i <= b[j] && ans < b[j] % i) ans = b[j] % i; } } } printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool dbg = 0; int main() { int N, K; cin >> N >> K; long long Count = 0; int x, y; for (int n = 0; n < N; ++n) { scanf( %d%d , &x, &y); Count += (long long)(y - x + 1); } cout << (K - Count % K) % K << endl; return 0; }
|
#include <bits/stdc++.h> const int MAXN = 200010; const int mod = 1000000007; void reduce(int& x) { x += x >> 31 & mod; } int mul(int a, int b) { return (long long)a * b % mod; } int remod(long long x) { x %= mod; return x + (x >> 63 & mod); } int n; int A[MAXN], W[MAXN]; long long rt[MAXN]; void mdfc(int x, int v) { for (; x <= n; x += x & -x) rt[x] += v; } long long qry(int x) { long long res = 0; for (; x; x &= x - 1) res += rt[x]; return res; } long long qry(int l, int r) { return qry(r) - qry(l - 1); } int tr[MAXN]; void mdfv(int x, int v) { for (v -= mod; x <= n; x += x & -x) reduce(tr[x] += v); } int qryv(int x) { int res = 0; for (; x; x &= x - 1) reduce(res += tr[x] - mod); return res; } int qryv(int l, int r) { int x = qryv(r) - qryv(l - 1); return x + (x >> 31 & mod); } void add(int x, int v) { mdfc(x, v), mdfv(x, remod(mul(A[x], v))); } int main() { std::ios_base::sync_with_stdio(false), std::cin.tie(0); int T; std::cin >> n >> T; for (int i = 1; i <= n; ++i) std::cin >> A[i], A[i] -= i; for (int i = 1; i <= n; ++i) std::cin >> W[i], add(i, W[i]); while (T-- > 0) { int x, y; std::cin >> x >> y; if (x < 0) x = -x, add(x, y - W[x]), W[x] = y; else { int l = x, r = y, at = -1; long long sm = qry(l, r); while (l <= r) { int mid = l + r >> 1; if (qry(x, mid) * 2 >= sm) at = mid, r = mid - 1; else l = mid + 1; } l = x, r = y; int X = A[at]; long long ans = qry(l, at) % mod * X - qryv(l, at); ans += qryv(at + 1, r) - qry(at + 1, r) % mod * X; std::cout << remod(ans) << n ; } } return 0; }
|
// dtb_daq.v
`timescale 1 ns / 1 ps
module dtb_daq
(
input clk_daq,
input clk_sys,
input [7:0]sclk,
input reset,
input sync,
// control
input [1:0]ctrl_adc_address,
input ctrl_adc_write,
input [15:0]ctrl_adc_writedata,
input ctrl_adc_read,
output [15:0]ctrl_adc_readdata,
input [3:0]ctrl_deser160,
// pattern generator
input [5:0]pg,
input i2c_trigger,
input tin,
input tout,
// soft TBM
input tbm_write,
input [15:0]tbm_data,
// adc input port
input [11:0]adc_data,
input adc_or,
// data channel 1
input sdata1,
// data simulator
input evsim_enable,
input evsim_write,
input [15:0]evsim_data,
// data output channel 1
output reg daq0_write,
output reg [15:0]daq0_writedata,
input daq0_running,
output [5:0]TP
);
// pattern generator signals
wire pg_trigger; // trigger signal for probe
wire pg_rest; // TBM reset
wire pg_res; // ROC reset
wire pg_cal; // calibrate
wire pg_trg; // trigger
wire pg_tok; // token in
assign {pg_trigger, pg_rest, pg_res, pg_cal, pg_trg, pg_tok} = pg;
wire write_ana;
wire [15:0]data_ana;
wire write_roc;
wire [15:0]data_roc;
adc_readout adc_in
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.avs_ctrl_address(ctrl_adc_address),
.avs_ctrl_write(ctrl_adc_write),
.avs_ctrl_writedata(ctrl_adc_writedata),
.avs_ctrl_read(ctrl_adc_read),
.avs_ctrl_readdata(ctrl_adc_readdata),
.run(daq0_running),
.trig1(pg_trigger),
.trig2(i2c_trigger),
.tin(tin),
.tout(tout),
.adc_data(adc_data),
.adc_or(adc_or),
.write(write_ana),
.writedata(data_ana),
.TP(TP)
);
deser160 channel1_roc
(
.clk(clk_daq),
.sync(sync),
.reset(reset),
.sclk0(sclk[0]),
.sclk180(sclk[4]),
.ctrl(ctrl_deser160),
.sdata(sdata1),
.tin(tin),
.tout(tout),
.run(daq0_running),
.write(write_roc),
.data(data_roc)
);
always @(*)
begin
if (evsim_enable)
begin
daq0_write <= evsim_write;
daq0_writedata <= evsim_data;
end
else if (tbm_write)
begin
daq0_write <= tbm_write;
daq0_writedata <= tbm_data;
end
else if (write_ana)
begin
daq0_write <= write_ana;
daq0_writedata <= data_ana;
end
else
begin
daq0_write <= write_roc;
daq0_writedata <= data_roc;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)3e5 + 50; struct node { int sum, suf; void add(int val) { sum += val; suf = max(sum, 0); } }; node merge(node L, node R) { return {L.sum + R.sum, max(R.sum + L.suf, R.suf)}; } struct Tree { node dat[4 * N]; void init(int n) { fill(dat, dat + 4 * n, node{0, 0}); } void update(int pos, int x, int l, int r, int val) { if (l == r) { dat[x].add(val); return; } int mid = (l + r) / 2; if (pos <= mid) update(pos, 2 * x + 1, l, mid, val); else update(pos, 2 * x + 2, mid + 1, r, val); dat[x] = merge(dat[2 * x + 1], dat[2 * x + 2]); } } tree; int n; int loc[N]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n; tree.init(n); for (int i = 0; i < n; i++) { int x; cin >> x; x--; loc[x] = i; } int cur = n - 1; for (int i = 0; i < n; i++) { while (cur >= 0 && tree.dat[0].suf == 0) { tree.update(loc[cur--], 0, 0, n - 1, 1); } cout << cur + 2 << ; int q; cin >> q; q--; tree.update(q, 0, 0, n - 1, -1); } }
|
module spi_trx (
input wire clk,
input wire sck,
output wire miso,
input wire mosi,
input wire ss,
output wire rst_o,
output wire [7:0] data_o,
output wire ack_pop_o,
input wire [7:0] data_i,
input wire ack_i);
// detect sck posedge
reg [1:0] sck_hist_ff;
always @(posedge clk) begin
sck_hist_ff <= {sck_hist_ff[0], sck};
end
// detect ss negedge
reg [1:0] ss_hist_ff;
always @(posedge clk) begin
ss_hist_ff <= {ss_hist_ff[0], ss};
end
wire ss_negedge = ss_hist_ff[1:0] == 2'b10;
wire ss_enabled = ~ss_hist_ff[0];
wire sck_posedge = ss_enabled && sck_hist_ff[1:0] == 2'b01;
wire sck_negedge = ss_enabled && sck_hist_ff[1:0] == 2'b10;
assign rst_o = ss_negedge;
// mosi -> shiftreg_i
reg mosi_hist_ff;
always @(posedge clk) begin
mosi_hist_ff <= mosi;
end
reg [7:0] shiftreg_i;
always @(posedge clk) begin
if (sck_posedge)
shiftreg_i <= {shiftreg_i[6:0], mosi_hist_ff};
end
// count 8 posedge -> posedge8
reg [2:0] posedge_counter;
always @(posedge clk) begin
if(ss_negedge)
posedge_counter <= 0;
else if(sck_posedge)
posedge_counter <= posedge_counter + 1;
end
wire posedge8 = sck_posedge & (posedge_counter == 3'd7);
reg posedge8_delayed;
always @(posedge clk)
posedge8_delayed <= posedge8;
// rx data -> {data_o, ack_pop_o}
reg ack_o_ff;
reg [7:0] data_o_ff;
always @(posedge clk) begin
ack_o_ff <= 0;
if (posedge8_delayed) begin
ack_o_ff <= 1;
data_o_ff <= shiftreg_i;
end
end
assign ack_pop_o = ack_o_ff;
assign data_o = data_o_ff;
// count 8 negedge -> negedge8
reg [2:0] negedge_counter;
always @(posedge clk) begin
if (ss_negedge)
negedge_counter <= 0;
else if(sck_negedge)
negedge_counter <= negedge_counter + 1;
end
wire negedge8 = sck_negedge & (negedge_counter == 3'd7);
// {data_i, ack_i} -> tx data
reg [7:0] data_o_latchff;
always @(posedge clk)
if(ack_i)
data_o_latchff <= data_i;
reg [7:0] shiftreg_o;
always @(posedge clk) begin
if(negedge8 || ss_negedge) begin
shiftreg_o <= data_o_latchff;
end else if(sck_negedge) begin
shiftreg_o <= {shiftreg_o[6:0], 1'b0};
end
end
assign miso = shiftreg_o[7];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, k; while (cin >> n >> k) { int r = n, l = 1; cout << l; l++; for (int i = 1; i < k; i++) if (i % 2) { cout << << r; r--; } else { cout << << l; l++; } if (k % 2) for (int i = k; i < n; i++, l++) cout << << l; else for (int i = k; i < n; i++, r--) cout << << r; cout << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_BLACKBOX_V
`define SKY130_FD_SC_MS__FAHCON_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_BLACKBOX_V
|
#include <bits/stdc++.h> const int inf = int(1e9); const int mod = inf + 7; const double PI = acos(-1.0); using namespace std; const int N = 1e5 + 155; void solve() { int n, k, s = 0; cin >> n >> k; for (int i = 0; i < n; ++i) { int x; cin >> x; s += x; } for (int ans = 0;; ans++) { int a = 2 * (s + ans * k); int b = (2 * k - 1) * (ans + n); if (a >= b) { cout << ans; return; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, i, j, A[200005], s = 1; cin >> n; for (long long(i) = 0; (i) < (n); (i) = (i + 1)) { cin >> A[i]; if (A[i] == n) { k = i; } } for (j = k; j < n - 1; j++) { if (A[j] < A[j + 1]) { s = 0; break; } } if (s != 0) { for (j = k; j > 0; j--) { if (A[j] < A[j - 1]) { s = 0; break; } } s == 0 ? cout << NO : cout << YES ; } else { cout << NO ; } return 0; }
|
module jt12_imp(
input rst,
input clk,
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
input limiter_en,
output busy,
output flag_B,
output flag_A,
// combined output
/*
output [11:0] snd_right,
output [11:0] snd_left,
output sample,
*/
// multiplexed output
output syn_left,
output syn_right,
output mux_sample,
output irq_n
);
wire syn_clk, cpu_clk,locked;
syn_clk_gen u_pll(
.areset(rst),
.inclk0(clk),
.c0(syn_clk),
.c1(cpu_clk),
.locked(locked));
wire [7:0] dout;
assign busy = dout[7];
assign flag_B = dout[1];
assign flag_A = dout[0];
jt12_top uut(
.rst ( rst ),
.cpu_clk ( cpu_clk),
.cpu_din ( din ),
.cpu_addr ( addr ),
.cpu_cs_n ( cs_n ),
.cpu_wr_n ( wr_n ),
.cpu_limiter_en( limiter_en ),
.cpu_dout ( dout ),
.cpu_irq_n ( irq_n ),
// Synthesizer clock domain
.syn_clk ( syn_clk ),
// FIR filters clock
.fir_clk ( clk ),
.fir_volume ( 3'd7 ),
// 1 bit output per channel at 1.3MHz
.syn_left ( syn_left ),
.syn_right ( syn_right )
);
endmodule
|
`timescale 1 ns / 1 ps
module elink_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire done;
wire error;
// Create an instance of the example tb
elink_testbench dut
(.aclk(aclk),
.aresetn(aresetn),
.csysreq(csysreq),
.done(done),
.error(error),
.start(start));
// Reset Generator
initial begin
aresetn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge aclk);
aresetn = 1'b1;
end
// Clock Generator
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Drive the BFM
initial begin
start = 1'b0;
// Wait for end of reset
wait(aresetn === 0) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
#500 start = 1'b1;
$display("=== TB Started");
wait( done == 1'b1);
$display("=== TEST_FINISHED");
if ( error ) begin
$display("===_TEST: FAILED!");
end else begin
$display("=== TEST: PASSED!");
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_SYMBOL_V
`define SKY130_FD_SC_HS__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_BEHAVIORAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd3 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTN_PP_BLACKBOX_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Delay Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (m0 , SCE_GATE, clkn, , VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_FUNCTIONAL_PP_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_change (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter num_cks = 1;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_change_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_change_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_change_psl_logic.v"
`else
`endmodule // ovl_change
`endif
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_cnt_nfl_en.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This is the error counter module for tracking the outstanding
completion. When overflow or underflow occurs, it remains at either
full scale (overflow) or zero (underflow) instead of rolling over.
***********************************************************************/
module cmm_errman_cnt_nfl_en (
count, // Outputs
index, // Inputs
inc_dec_b,
enable,
rst,
clk
);
output count;
input index; // ftl_num, nfl_num or cor_num
input inc_dec_b; // 1 = increment, 0 = decrement
input enable; // err_*_en
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter FFD = 1; // clock to out delay model
//******************************************************************//
// There are 2 pipeline stages to help timing. //
// Stage 1: a simple add/subtract accumulator with no overflow or //
// underflow check. //
// Stage 2: underflow, overflow and counter enable are handled. //
//******************************************************************//
// Stage 1: count up or count down
reg reg_cnt;
reg reg_extra;
reg reg_inc_dec_b;
reg reg_uflow;
wire cnt;
wire oflow;
wire uflow;
always @(posedge clk or posedge rst)
begin
if (rst) {reg_extra, reg_cnt} <= #FFD 2'b00;
else if (~enable) {reg_extra, reg_cnt} <= #FFD 2'b00;
else if (inc_dec_b) {reg_extra, reg_cnt} <= #FFD cnt + index;
else {reg_extra, reg_cnt} <= #FFD cnt - index;
end
assign cnt = oflow ? 1'b1 : (uflow ? 1'b0 : reg_cnt);
always @(posedge clk or posedge rst)
begin
if (rst) reg_inc_dec_b <= #FFD 1'b0;
else reg_inc_dec_b <= #FFD inc_dec_b;
end
assign oflow = reg_extra & reg_inc_dec_b;
always @(posedge clk or posedge rst)
begin
if (rst)
reg_uflow <= 1'b0;
else
reg_uflow <= #FFD ~count & index & ~inc_dec_b;
end
assign uflow = reg_uflow;
// Stage 2: if overflow occurs, the counter is set to full scale;
// if underflow occurs, it is set to zero.
// if counter is not enable, it is set to zero.
reg reg_count;
always @(posedge clk or posedge rst)
begin
if (rst) reg_count <= #FFD 1'b0;
else if (~enable) reg_count <= #FFD 1'b0;
else if (oflow) reg_count <= #FFD 1'b1;
else if (uflow) reg_count <= #FFD 1'b0;
else reg_count <= #FFD cnt;
end
assign count = reg_count;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
#include <bits/stdc++.h> using namespace std; string S; int ans; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); for (int i = 1; i <= 3; i++) { getline(cin, S); ans = 0; for (int j = 0; j < S.length(); j++) { if (S[j] == a || S[j] == i || S[j] == u || S[j] == e || S[j] == o ) ans++; } if (ans == 5 && i == 2) { cout << NO n ; return 0; } else if (ans == 7 && i % 2 == 1) { cout << NO n ; return 0; } else if (ans != 5 && ans != 7) { cout << NO n ; return 0; } } cout << YES n ; }
|
#include <bits/stdc++.h> using namespace std; int t, n; int a[1000005]; vector<int> x; void solve() { int sum = 0, ans; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; } int l = 1, r = 1e7; while (l <= r) { int mid = (l + r) >> 1; if (mid * n >= sum) { r = mid - 1; ans = mid; } else { l = mid + 1; } } x.push_back(ans); } int main() { cin >> t; while (t--) solve(); for (int i = 0; i < x.size(); i++) { cout << x[i] << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 10, INF = 1e9; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -f; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 48; ch = getchar(); } return x * f; } int n, l[N], r[N], a[N], b[N], c[N]; int ans, sum, pos, cnt, tot; int t1, t2; signed main() { n = read(); for (int i = 1; i <= n; i++) { l[i] = read(); r[i] = read(); a[++cnt] = l[i]; a[++cnt] = r[i]; } sort(a + 1, a + cnt + 1); for (int i = 1; i <= cnt; i++) if (i == 1 || a[i] != a[i - 1]) a[++tot] = a[i]; for (int i = 1; i <= n; i++) { t1 = lower_bound(a + 1, a + tot + 1, l[i]) - a; t2 = lower_bound(a + 1, a + tot + 1, r[i]) - a; c[t1] = l[i], c[t2] = r[i]; b[t1]++, b[t2]--; } for (int i = 1; i <= tot; i++) { sum += b[i]; if (sum > ans) ans = sum, pos = c[i]; } printf( %d %d , pos, ans); return 0; }
|
#include <bits/stdc++.h> const int maxn = 100100; const int bl = 512; static const int N = 600; int n, k, q; int s[maxn]; struct block { int pop[N], c0; int push[N], c1; int ok; } o[maxn / bl + 10]; inline int eql(const int *a, const int *b, const int len) { for (int i = 0; i < len; ++i) { if (a[i] != b[i]) return 0; } return 1; } inline bool ask(int l, int r) { static int st[maxn]; int top = 0; for (; l % bl && l <= r; ++l) if (s[l] > 0) { st[++top] = s[l]; } else { if (!top || st[top] != -s[l]) return 0; --top; }; for (; l + bl - 1 <= r; l += bl) { block &o = ::o[l / bl]; if (!o.ok) return 0; if (top < o.c0) return 0; if (!eql(st + top - o.c0 + 1, o.pop + N - o.c0, o.c0)) return 0; top -= o.c0; memcpy(st + top + 1, o.push + 1, o.c1 << 2); top += o.c1; } for (; l <= r; ++l) if (s[l] > 0) { st[++top] = s[l]; } else { if (!top || st[top] != -s[l]) return 0; --top; }; return top == 0; } inline void init(int id) { block &o = ::o[id]; o.c0 = o.c1 = 0; o.ok = 1; int top = 0; const int L = id * bl, R = std::min(n - 1, id * bl + bl - 1); for (int i = L; i <= R; ++i) { if (s[i] > 0) { o.push[++top] = s[i]; } else { if (top && o.push[top] != -s[i]) { o.ok = 0; return; } else { if (top) { --top; } else { o.pop[N - ++o.c0] = -s[i]; } } } } o.c1 = top; } int main() { std::ios::sync_with_stdio(false), std::cin.tie(0); std::cin >> n >> k; for (int i = 0; i < n; ++i) { std::cin >> s[i]; } for (int i = 0; i <= (n - 1) / bl; ++i) init(i); std::cin >> q; for (int i = 0; i < q; ++i) { int opt, pos, v, l, r; std::cin >> opt; if (opt == 1) { std::cin >> pos; --pos; std::cin >> s[pos]; init(pos / bl); } else { std::cin >> l >> r; std::cout << (ask(l - 1, r - 1) ? Yes : No ) << n ; } } }
|
//==================================================================================================
// Filename : antares_reg_file.v
// Created On : Tue Sep 1 10:29:48 2015
// Last Modified : Sat Nov 07 12:15:25 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : 32 General Purpose Registers (GPR)
// WARNING: This register file DO NOT HAVE A RESET.
//==================================================================================================
module antares_reg_file (
input clk,
input [4:0] gpr_ra_a,
input [4:0] gpr_ra_b,
input [4:0] gpr_wa,
input [31:0] gpr_wd,
input gpr_we,
output [31:0] gpr_rd_a,
output [31:0] gpr_rd_b
);
// Register file of 32 32-bit registers. Register 0 is always 0
reg [31:0] registers [1:31];
// Clocked write
always @ ( posedge clk ) begin
if(gpr_wa != 5'b0)
registers[gpr_wa] <= (gpr_we) ? gpr_wd : registers[gpr_wa];
end
// Combinatorial read (no delay). Register 0 is read as 0 always.
assign gpr_rd_a = (gpr_ra_a == 5'b0) ? 32'b0 : registers[gpr_ra_a];
assign gpr_rd_b = (gpr_ra_b == 5'b0) ? 32'b0 : registers[gpr_ra_b];
endmodule // antares_reg_file
|
#include <bits/stdc++.h> using namespace std; int const N = 2005; long long f(long long x, long long n) { long long t = (x % 2 == 1 ? 1 : 2); long long h = 1; long long res = 0; while (true) { if ((x * h) > n) return res; res += (t - (x * h + t - 1 - min(x * h + t - 1, n))); t <<= 1; h <<= 1; } return res; } long long bs(long long t, long long n, long long k) { long long l = (t ? t : 2), r = (n % 2 == t ? n : n - 1); long long res = 0; while (l <= r) { long long md = (l + r) / 2; md = (md % 2 == t ? md : md - 1); long long x = f(md, n); if (x >= k) { res = max(res, md); l = md + 2; } else r = md - 2; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; cout << max(bs(0, n, k), bs(1, n, k)) << endl; return 0; }
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified by: Ye-sheng Kuo <>
* 05/25 '15: Add double latch for DIN
*
* 04/08 '13: Added glitch reset
* */
`include "include/mbus_def.v"
module mbus_ctrl(
input CLK_EXT,
input RESETn,
input CLKIN,
output CLKOUT,
input DIN,
output reg DOUT,
input [`WATCH_DOG_WIDTH-1:0] THRESHOLD
);
`include "include/mbus_func.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg clk_en, next_clk_en;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`WATCH_DOG_WIDTH-1:0] threshold_cnt, next_threshold_cnt;
reg din_dly_1, din_dly_2;
always @(posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_dly_1 <= 1'b1;
din_dly_2 <= 1'b1;
end
else begin
din_dly_1 <= DIN;
din_dly_2 <= din_dly_1;
end
end
assign CLKOUT = (clk_en)? CLK_EXT : 1'b1;
wire [1:0] CONTROL_BITS = `CONTROL_SEQ; // EOM?, ~ACK?
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
bus_state <= BUS_IDLE;
start_cycle_cnt <= START_CYCLES - 1'b1;
clk_en <= 0;
bus_interrupt_cnt <= BUS_INTERRUPT_COUNTER - 1'b1;
threshold_cnt <= 0;
end
else
begin
bus_state <= next_bus_state;
start_cycle_cnt <= next_start_cycle_cnt;
clk_en <= next_clk_en;
bus_interrupt_cnt <= next_bus_interrupt_cnt;
threshold_cnt <= next_threshold_cnt;
end
end
always @ *
begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_threshold_cnt = threshold_cnt;
case (bus_state)
BUS_IDLE:
begin
if (~din_dly_2)
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
BUS_WAIT_START:
begin
next_threshold_cnt = 0;
if (start_cycle_cnt)
next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else
begin
if (~din_dly_2)
begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else
next_bus_state = BUS_IDLE;
end
end
BUS_START:
begin
next_bus_state = BUS_ARBITRATE;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
// Glitch, reset bus immediately
if (DIN)
next_threshold_cnt = THRESHOLD;
end
BUS_PRIO:
begin
next_bus_state = BUS_ACTIVE;
end
BUS_ACTIVE:
begin
if ((threshold_cnt<THRESHOLD)&&(~clkin_sampled))
next_threshold_cnt = threshold_cnt + 1'b1;
else
begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT:
begin
if (bus_interrupt_cnt)
next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else
begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000)
begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE:
begin
next_bus_state = BUS_CONTROL0;
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
end
BUS_BACK_TO_IDLE:
begin
if (~DIN)
begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else
begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_neg <= 0;
bus_state_neg <= BUS_IDLE;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_neg <= {din_sampled_neg[1:0], DIN};
bus_state_neg <= bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_pos <= 0;
clkin_sampled <= 0;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_pos <= {din_sampled_pos[1:0], DIN};
clkin_sampled <= CLKIN;
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: begin DOUT = 1; end
BUS_WAIT_START: begin DOUT = 1; end
BUS_START: begin DOUT = 1; end
BUS_INTERRUPT: begin DOUT = CLK_EXT; end
BUS_CONTROL0: begin if (threshold_cnt==THRESHOLD) DOUT = (~CONTROL_BITS[1]); end
BUS_BACK_TO_IDLE: begin DOUT = 1; end
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_core_axi_basic_tx.v
// Version : 1.10
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_core_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_core_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
pcie_core_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
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