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#include <bits/stdc++.h> using namespace std; inline char gc() { static char buf[1 << 16], *S, *T; if (S == T) { T = (S = buf) + fread(buf, 1, 1 << 16, stdin); if (T == S) return EOF; } return *S++; } inline long long read() { long long x = 0, f = 1; char ch = gc(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = gc(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = gc(); return x * f; } int m, k, n, a[1000010], dp[1000010], ans = 0; long long l; pair<int, int> c[1000010]; int main() { m = read(); l = read(); k = read(); n = m * k; for (int i = 0; i < m; ++i) a[i] = read(); for (int i = 0; i < n; ++i) c[i].first = a[i % m], c[i].second = i; sort(c, c + n); long long tot = l / m; int yu = l % m; ans = l % 1000000007; for (int i = 0; i < n; ++i) { int id = c[i].second; if (id / m + 1 == 1) { dp[id / m + 1]++; continue; } dp[id / m + 1] += dp[id / m + 1 - 1], dp[id / m + 1] %= 1000000007; if (id >= l) continue; long long cnt = tot - (id / m + 1) + 1; if (id % m <= yu - 1) cnt++; ans += cnt % 1000000007 * dp[id / m + 1 - 1] % 1000000007; ans %= 1000000007; } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int32_t mod = 1e9 + 7; const long long inf = 1e18; set<long long> S; void doq() { for (long long i = 0; i < 40; i++) { for (long long j = 0; j < 40; j++) { long long a = 3 * i + 7 * j; if (a <= 100) S.insert(a); } } } void solve() { long long n; cin >> n; if (S.find(n) != S.end()) cout << YES n ; else cout << NO n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); doq(); long long tcs = 1; cin >> tcs; while (tcs--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 9; long long n, k; long long a[N]; long long ans; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cerr << ; cin >> n >> k; for (int i = 0; i < (n); i++) cin >> a[i], a[i]--; sort(a, a + n, greater<long long>()); long long i = 0; while (i < n) ans += a[i] * 2, i += k; cout << ans << endl; }
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#include <bits/stdc++.h> using namespace std; long long GCD(long long u, long long v) { long long r; while (v) { r = u % v; u = v; v = r; } return u; } long long modpow(long long a, long long p, long long mod) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a) % mod; a = (a * a) % mod; p /= 2; } return ret; } long long power(long long a, long long p) { long long ret = 1; while (p) { if (p & 1) ret = (ret * a); a = (a * a); p /= 2; } return ret; } int a[51]; int main() { int i, j, tmp; ios_base::sync_with_stdio(0); cin.tie(NULL); int n, k; cin >> n >> k; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); if (k > n) cout << -1 << endl; else cout << a[n - k] << << a[n - k] << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[2500000]; int main() { int all; scanf( %d , &all); for (int i = 1; i <= all; i++) { scanf( %I64d , &a[i]); } sort(a + 1, a + all + 1); reverse(a + 1, a + all + 1); long long sum = 0; for (int fro = 1; fro <= all; fro = fro << 2) { for (int p = 1; p <= fro; p++) { sum += a[p]; } } long long temp = 0, area = 1; printf( %I64d , sum); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); double s, x, y, z; cin >> s >> x >> y >> z; if ((x == y) && (y == z) && (z == 0.0)) { cout << 0 0 << s << endl; return 0; } double k = x + y + z, x0 = x * s / k, y0 = y * s / k, z0 = z * s / k; if (x0 + y0 + z0 >= s) z0 -= (x0 + y0 + z0 - s); cout << setprecision(14) << x0 << << y0 << << z0 << endl; return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_hvl__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; int vis[2000007]; string s; int main() { int n, k, i, j, l, x, len = 0, pos; string in; cin >> n; for (i = 0; i < 2000007; i++) s += a ; for (i = 0; i < n; i++) { cin >> in >> k; pos = -(int)in.length(); for (j = 1; j <= k; j++) { cin >> x; len = max(len, x + (int)in.length()); for (l = max(0, pos + (int)in.length() - x); l < in.length(); l++) s[l + x] = in[l]; pos = x; } } for (i = 1; i < len; i++) cout << s[i]; cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int a[100005]; bool vis1[100005], vis2[100005]; vector<int> e1[100005], e2[100005]; queue<int> q1, q2; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); e1[x].push_back(y); e2[y].push_back(x); } for (int i = 1; i <= n; i++) { if (a[i] == 1) { vis1[i] = 1; q1.push(i); } } while (!q1.empty()) { int now = q1.front(); q1.pop(); for (int i = 0; i < e1[now].size(); i++) { int v = e1[now][i]; if (a[v] == 1 || vis1[v]) continue; vis1[v] = 1; q1.push(v); } } for (int i = 1; i <= n; i++) { if (a[i] == 2) { vis2[i] = 1; q2.push(i); } } while (!q2.empty()) { int now = q2.front(); q2.pop(); for (int i = 0; i < e2[now].size(); i++) { int v = e2[now][i]; if (a[v] == 1) vis2[v] = 1; if (a[v] == 1 || vis2[v]) continue; vis2[v] = 1; q2.push(v); } } for (int i = 1; i <= n; i++) if (vis1[i] && vis2[i]) printf( 1 n ); else printf( 0 n ); return 0; }
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#include <bits/stdc++.h> using namespace std; #define INF 1000000009 int get(int i){ cout << ? << i+1 << endl; cout.flush(); int a; cin >> a; int b; if(i == 0) b = INF; else{ cout << ? << i << endl; cout.flush(); cin >> b; } return b-a; } int main(){ // freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; if(n == 1){ cout << ! << 1 << endl; cout.flush(); return 0; } if(get(1) < 0){ cout << ! << 1 << endl; cout.flush(); return 0; } if(get(n-1) > 0){ cout << ! << n << endl; cout.flush(); return 0; } int lo = 0, hi = n-1; while(lo < hi){ int mid = lo+(hi-lo)/2; if(get(mid) > 0) lo = mid+1; else hi = mid; } cout << ! << lo << endl; cout.flush(); }
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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int mod2 = 1e9 + 9; const int maxN = 5e5 + 100; const int INF = 1e9 + 7; const int maxedge = 1e6 + 100; const long long LL_INF = 1e18 + 11; using namespace std; long long n, ans; map<long long, long long> ma; void file() { freopen( pluses.in , r , stdin); freopen( pluses.out , w , stdout); } void boost() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int main() { cin >> n; for (int long long i = 1; i * i <= n; i++) { if (n % i == 0) { if (ma[i] == 0) { ans++; ma[i]++; } if (ma[n / i] == 0) { ans++; ma[n / i]++; } } } cout << ans; }
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/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY wrapper
*/
module eth_xcvr_phy_wrapper #
(
parameter HAS_COMMON = 1,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL out
*/
input wire xcvr_gtrefclk00_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0outclk_out,
output wire xcvr_qpll0outrefclk_out,
/*
* PLL in
*/
input wire xcvr_qpll0lock_in,
output wire xcvr_qpll0reset_out,
input wire xcvr_qpll0clk_in,
input wire xcvr_qpll0refclk_in,
/*
* Serial data
*/
output wire xcvr_txp,
output wire xcvr_txn,
input wire xcvr_rxp,
input wire xcvr_rxn,
/*
* PHY connections
*/
output wire phy_tx_clk,
output wire phy_tx_rst,
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
output wire phy_rx_clk,
output wire phy_rx_rst,
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
output wire phy_tx_bad_block,
output wire [6:0] phy_rx_error_count,
output wire phy_rx_bad_block,
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
);
wire phy_rx_reset_req;
wire gt_reset_tx_datapath = 1'b0;
wire gt_reset_rx_datapath = phy_rx_reset_req;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
generate
if (HAS_COMMON) begin : xcvr
eth_xcvr_gt_full
eth_xcvr_gt_full_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtrefclk00_in(xcvr_gtrefclk00_in),
.qpll0lock_out(xcvr_qpll0lock_out),
.qpll0outclk_out(xcvr_qpll0outclk_out),
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end else begin : xcvr
eth_xcvr_gt_channel
eth_xcvr_gt_channel_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
.qpll0clk_in(xcvr_qpll0clk_in),
.qpll0refclk_in(xcvr_qpll0refclk_in),
.qpll1clk_in(1'b0),
.qpll1refclk_in(1'b0),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end
endgenerate
sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(phy_tx_clk),
.rst(!gt_reset_tx_done),
.out(phy_tx_rst)
);
sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(phy_rx_clk),
.rst(!gt_reset_rx_done),
.out(phy_rx_rst)
);
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(1),
.SCRAMBLER_DISABLE(0),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
phy_inst (
.tx_clk(phy_tx_clk),
.tx_rst(phy_tx_rst),
.rx_clk(phy_rx_clk),
.rx_rst(phy_rx_rst),
.xgmii_txd(phy_xgmii_txd),
.xgmii_txc(phy_xgmii_txc),
.xgmii_rxd(phy_xgmii_rxd),
.xgmii_rxc(phy_xgmii_rxc),
.serdes_tx_data(gt_txdata),
.serdes_tx_hdr(gt_txheader),
.serdes_rx_data(gt_rxdata),
.serdes_rx_hdr(gt_rxheader),
.serdes_rx_bitslip(gt_rxgearboxslip),
.serdes_rx_reset_req(phy_rx_reset_req),
.tx_bad_block(phy_tx_bad_block),
.rx_error_count(phy_rx_error_count),
.rx_bad_block(phy_rx_bad_block),
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
);
endmodule
`resetall
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#include <bits/stdc++.h> using namespace std; long long int powerMod(long long int x, unsigned long long int y) { if (y == 0) return 1; long long int p = powerMod(x, y / 2) % 1000000007; p = (p * p) % 1000000007; return (y % 2 == 0) ? p : (x * p) % 1000000007; } long long int power(long long int x, unsigned long long int y) { if (y == 0) return 1; long long int p = power(x, y / 2); p = (p * p); return (y % 2 == 0) ? p : (x * p); } int main() { cin.tie(0)->sync_with_stdio(0); int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> arr(n); for (int i = 0; i < n; ++i) cin >> arr[i]; if (n % 2 == 0) cout << YES n ; else { bool ok = true; for (int i = 0; i < n - 1; ++i) { if (arr[i + 1] <= arr[i]) { ok = false; break; } } if (!ok) cout << YES n ; else cout << NO n ; } } }
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#include <bits/stdc++.h> using namespace std; const long long N = 200000 + 10; const long long M = 1000000 + 10; const long long INF = (long long)1e9 + 10; long long n, m; long long tl[N], tr[N]; map<long long, long long> toX; pair<long long, long long> a[N]; pair<pair<long long, long long>, pair<long long, int> > b[N]; long long preMax[M], sufMin[M], midMax[M]; long long queryMax(long long *c, long long p) { long long ret = 0; for (p++; p; p -= p & -p) { ret = max(ret, c[p]); } return ret; } long long queryMin(long long p) { long long ret = INF; for (p++; p; p -= p & -p) { ret = min(ret, sufMin[p]); } return ret; } void addMax(long long *c, long long p, long long value) { for (p++; p < M; p += p & -p) { c[p] = max(c[p], value); } } void addMin(long long p, long long value) { for (p++; p < M; p += p & -p) { sufMin[p] = min(sufMin[p], value); } } void solve() { cin >> n >> m; vector<long long> values; for (long long i = 0; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); tl[i] = x; tr[i] = y; a[i].first = x; a[i].second = y; values.push_back(a[i].first); values.push_back(a[i].second); } for (long long i = 0; i < m; ++i) { int x, y, d; scanf( %d%d%d , &x, &y, &d); b[i].first.first = x; b[i].first.second = y; b[i].second.first = d; b[i].second.second = i; values.push_back(b[i].first.first); values.push_back(b[i].first.second); } sort(values.begin(), values.end()); values.erase(unique(values.begin(), values.end()), values.end()); for (long long i = 0; i < values.size(); ++i) { toX[values[i]] = i; } fill(preMax, preMax + M, -1); fill(sufMin, sufMin + M, INF); fill(midMax, midMax + M, 0); for (long long i = 0; i < n; ++i) { long long l = toX[a[i].first]; long long r = toX[a[i].second]; addMax(preMax, l, a[i].second); addMin(M - r - 100, a[i].first); } sort(a, a + n); sort(b, b + m); long long ret = 0; long long ptr = n - 1; int rc = -1, rcc; for (long long i = m - 1; i >= 0; --i) { for (; ptr >= 0 && a[ptr].first >= b[i].first.first; ptr--) { addMax(midMax, toX[a[ptr].second], a[ptr].second - a[ptr].first); } long long maxLen = 0; maxLen = queryMax(midMax, toX[b[i].first.second]); maxLen = max(maxLen, queryMax(preMax, toX[b[i].first.first]) - b[i].first.first); maxLen = max( maxLen, b[i].first.second - queryMin(M - toX[b[i].first.second] - 100)); maxLen = min(maxLen, b[i].first.second - b[i].first.first); if (ret < maxLen * b[i].second.first) { ret = maxLen * b[i].second.first; rc = b[i].second.second; rcc = i; } } cout << ret << endl; if (ret == 0) { return; } for (int i = 0; i < n; ++i) { long long nl = max(tl[i], b[rcc].first.first); long long nr = min(tr[i], b[rcc].first.second); if (nl > nr) continue; if ((nr - nl) * b[rcc].second.first == ret) { cout << i + 1 << << rc + 1 << endl; return; } } } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m; int main() { scanf( %d %d , &n, &m); if (m > n) { printf( -1 ); return 0; } m -= 2; if (n == 1) { printf( a ); return 0; } if (n > 1 && m < 0) { printf( -1 ); return 0; } for (int i = 1; i <= n - m; i++) if (i % 2 == 1) printf( a ); else printf( b ); for (int i = 1; i <= m; i++) printf( %c , char(i + 98)); printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 5; bool isPrime[N], vst[N]; int frq[26]; vector<int> adj[N]; vector<int> cc; vector<vector<int>> vcc; void dfs(int u) { cc.push_back(u); vst[u] = 1; for (auto v : adj[u]) { if (!vst[v]) dfs(v); } } bool cmp(vector<int> s, vector<int> f) { return (int)(s.size()) > (int)(f.size()); } int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); string s; cin >> s; for (auto i : s) { frq[i - a ]++; } isPrime[0] = isPrime[1] = 1; for (int i = 2; i <= (int)(s.size()); i++) { if (isPrime[i]) continue; for (int j = 2 * i; j <= (int)(s.size()); j += i) { isPrime[j] = 1; adj[i].push_back(j); adj[j].push_back(i); } } for (int i = 1; i <= (int)(s.size()); i++) { if (!isPrime[i] && !vst[i]) { cc.clear(); dfs(i); vcc.push_back(cc); } } vector<char> out((int)(s.size()) + 2); for (auto i : vcc) { int siz = (int)(i.size()); int mn = (int)(s.size()) + 1; int ch = 26; for (int j = 0; j < 26; j++) { if (frq[j] >= siz && frq[j] < mn) { mn = frq[j]; ch = j; } } if (ch == 26) { return cout << NO n , 0; } frq[ch] -= siz; for (auto j : i) { out[j] = ch + a ; } } for (int i = 1; i <= (int)(s.size()); i++) { for (int j = 0; j < 26; j++) { if (frq[j]) { frq[j]--; out[i] = j + a ; break; } } } cout << YES n ; for (int i = 1; i <= (int)(s.size()); i++) cout << out[i]; }
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//-----------------------------------------------------------------------------
// File : clock_generator.v
// Creation date : 26.04.2017
// Creation time : 16:30:51
// Description : A clock source for simulations. Will also assert and deassert reset and terminate the simulation after WAIT_TIME has passed since the deassertion.
// Created by : TermosPullo
// Tool : Kactus2 3.4.74 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:testBench:clock_generator:1.1
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/testBench/clock_generator/1.1/clock_generator.1.1.xml
//-----------------------------------------------------------------------------
module clock_generator(
// Interface: wb_system
output reg clk_o, // The mandatory clock, as this is synchronous logic.
output reg rst_o // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
initial begin
clk_o = 1'b0;
rst_o = 1'b1; // assert reset
repeat(4) #5 clk_o = ~clk_o;
rst_o = 1'b0; // deassert reset
forever #5 clk_o = ~clk_o; // generate a clock
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m; int l[100500]; int r[100500]; int val[100500]; int t[400500]; int t2[400500]; int mas[100500]; int INF = 0; void build(int v, int tl, int tr) { if (tl == tr) t[v] = 0; else { int mid = (tl + tr) >> 1; build(v << 1, tl, mid); build((v << 1) + 1, mid + 1, tr); t[v] = 0; } } void update(int v, int tl, int tr, int ql, int qr, int nval) { if (ql > qr) return; if (tl == ql && tr == qr) { t[v] = t[v] | nval; } else { int mid = (tl + tr) >> 1; update(v << 1, tl, mid, ql, min(qr, mid), nval); update((v << 1) + 1, mid + 1, tr, max(ql, mid + 1), qr, nval); } } void dfs(int v, int tl, int tr, int curr) { if (tl == tr) { mas[tl] = curr | t[v]; } else { int mid = (tl + tr) >> 1; dfs(v << 1, tl, mid, curr | t[v]); dfs((v << 1) + 1, mid + 1, tr, curr | t[v]); } } void build2(int v, int tl, int tr) { if (tl == tr) { t[v] = mas[tl]; } else { int mid = (tl + tr) >> 1; build2(v << 1, tl, mid); build2((v << 1) + 1, mid + 1, tr); t[v] = t[v << 1] & t[(v << 1) + 1]; } } int query(int v, int tl, int tr, int ql, int qr) { if (ql > qr) return INF; if (tl == ql && tr == qr) { return t[v]; } else { int mid = (tl + tr) >> 1; return query(v << 1, tl, mid, ql, min(qr, mid)) & query((v << 1) + 1, mid + 1, tr, max(ql, mid + 1), qr); } } int main() { for (int i = 29; i >= 0; i--) { INF += (1 << i); } cin >> n >> m; build(1, 1, n); for (int i = 0; i < m; i++) { cin >> l[i] >> r[i] >> val[i]; update(1, 1, n, l[i], r[i], val[i]); } dfs(1, 1, n, 0); build2(1, 1, n); for (int i = 0; i < m; i++) { if (query(1, 1, n, l[i], r[i]) != val[i]) { cout << NO ; return 0; } } cout << YES n ; for (int i = 1; i <= n; i++) cout << mas[i] << ; return 0; }
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//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW: Instantiation of Modules:
//
// D: Instantiate two versions of a module containing a single
// D: resetable f/f. Reset both - then feed 1 module with a clock
// D: and validate that the output toggles. Feed the 2nd module
// D: with a clock and validate that the 2nd output toggles.
//
//
module test_mod (reset,clka,out);
input reset;
input clka;
output out;
reg out;
always @(posedge clka or posedge reset)
if(reset)
out = 0;
else
begin
out = ~out;
$display("saw a clk at %d, out is %b\n",$time,out);
end
endmodule
module main();
reg reset,clk_0,clk_1;
wire out_0,out_1;
test_mod module_1 (reset,clk_0,out_0);
test_mod module_2 (reset,clk_1,out_1);
initial
begin
clk_0 = 0;
clk_1 = 0;
#1 reset = 1;
# 2;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
clk_1,out_0,out_1);
// Validate that both out_0 and out_1 are reset
if(out_0)
begin
$display("FAILED - out_0 not reset\n");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 not reset\n");
$finish ;
end
reset = 0;
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
clk_1,out_0,out_1);
# 2;
clk_0 = 1;
# 2; // Wait so we don't worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_0)
begin
$display("FAILED - out_0 didn't set on clk_0\n");
$finish ;
end
if(out_1)
begin
$display("FAILED - out_1 set on wrong clk!\n");
$finish ;
end
clk_1 = 1;
# 2; // Wait so we don't worry about races.
$display("time %d r=%b, c0=%b, c1=%b, o0=%b,o1=%b\n",$time,reset,clk_0,
clk_1,out_0,out_1);
if(!out_1)
begin
$display("FAILED - out_1 didn't set on clk_1\n");
$finish ;
end
if(!out_0)
begin
$display("FAILED - out_0 changed due to clk_0\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
typedef enum integer {UP=0, UW=1'b1} UNSIZED;
// verilator lint_on WIDTH
localparam LEN = 3;
localparam COL = 4;
localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
bit [59:0] SE2 = {N, E, W, P
,S, E, W, P
,S, N, W, P
,S, N, E, P
,S, N, E, W};
initial begin
if (SEQ != 60'o32104210431043204321) $stop;
if (SE2 != 60'o32104210431043204321) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
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#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; int n, m, ans, flag; bool vis[10]; string fac[7] = { 1869 , 1968 , 1689 , 6198 , 8691 , 8916 , 1896 }; string s, ss, anss, xx = 0000 ; int main() { int i, j, t, pos, x, y, u, v, w; while (cin >> s) { memset(vis, 0, sizeof(vis)); ss = ; for (i = 0; i < s.length(); i++) { if (s[i] == 1 ) { if (!vis[1]) vis[1] = 1; else ss += s[i]; } else if (s[i] == 6 ) { if (!vis[6]) vis[6] = 1; else ss += s[i]; } else if (s[i] == 8 ) { if (!vis[8]) vis[8] = 1; else ss += s[i]; } else if (s[i] == 9 ) { if (!vis[9]) vis[9] = 1; else ss += s[i]; } else ss += s[i]; } flag = 0; for (i = 0; i < ss.length(); i++) { if (ss[i] != 0 ) { flag = 1; char c = ss[i]; ss[i] = ss[0]; ss[0] = c; } } if (!flag) { cout << 1869 << ss << endl; } else { t = 0; for (i = 0; i < ss.length(); i++) { t = (t * 10 + ss[i] - 0 ) % 7; } for (i = 0; i < 4; i++) { t = (t * 10 + xx[i] - 0 ) % 7; } if (t) t = 7 - t; cout << ss << fac[t] << endl; } } return 0; }
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming encoder
*/
module ham_15_11_encoder (d,c);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 11-bit input
input [10:0] d;
// Declare "reg" signals...
// Parity bits for Hamming encoding
reg [3:0] p;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
// Determine for each parity bit, what data bits is it made of
//p[0]=((d[0]^d[1])^(d[3]^d[4]))^((d[6]^d[8])^d[10]);
p[0]=d[0]^d[1]^d[3]^d[4]^d[6]^d[8]^d[10];
// assign p[0]=d[0];
//p{0}=d{0};
//p(0)=d(0);
p[1]=((d[0]^d[2])^(d[3]^d[5]))^((d[6]^d[9])^d[10]);
p[2]=((d[1]^d[2])^(d[3]^d[7]))^((d[8]^d[9])^d[10]);
p[3]=((d[4]^d[5])^(d[6]^d[7]))^((d[8]^d[9])^d[10]);
// Assign the encoded signal bits to data bits...
c[2]=d[0];
c[4]=d[1];
c[5]=d[2];
c[6]=d[3];
c[8]=d[4];
c[9]=d[5];
c[10]=d[6];
c[11]=d[7];
c[12]=d[8];
c[13]=d[9];
c[14]=d[10];
// Introduce parity bits to encode signal values
c[0]=p[0];
c[1]=p[1];
c[3]=p[2];
c[7]=p[3];
end
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// generates horizontal vga sync, double the rate of TV horizontal sync
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module video_vga_sync_h(
input wire clk,
input wire [1:0] modes_raster,
output reg vga_hsync,
output reg scanout_start,
input wire hsync_start
);
localparam HSYNC_END = 10'd106;
localparam SCANOUT_BEG = 10'd156;
localparam HPERIOD_224 = 10'd896;
localparam HPERIOD_228 = 10'd912;
reg [9:0] hcount;
initial
begin
hcount = 9'd0;
vga_hsync = 1'b0;
end
always @(posedge clk)
begin
if( hsync_start )
hcount <= 10'd2;
else if ( hcount==( (modes_raster==2'b11) ? (HPERIOD_228-10'd1) : (HPERIOD_224-10'd1) ) )
hcount <= 10'd0;
else
hcount <= hcount + 9'd1;
end
always @(posedge clk)
begin
if( !hcount )
vga_hsync <= 1'b1;
else if( hcount==HSYNC_END )
vga_hsync <= 1'b0;
end
always @(posedge clk)
begin
if( hcount==SCANOUT_BEG )
scanout_start <= 1'b1;
else
scanout_start <= 1'b0;
end
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top (
IO_CLK,
IO_RST_N,
LED
);
input IO_CLK;
input IO_RST_N;
output [3:0] LED;
parameter signed [31:0] MEM_SIZE = 65536;
parameter [31:0] MEM_START = 32'h00000000;
parameter [31:0] MEM_MASK = (MEM_SIZE - 1);
wire clk_sys;
wire rst_sys_n;
wire instr_req;
reg instr_gnt;
wire instr_rvalid;
wire [31:0] instr_addr;
wire [31:0] instr_rdata;
wire data_req;
reg data_gnt;
reg data_rvalid;
wire data_we;
wire [3:0] data_be;
wire [31:0] data_addr;
wire [31:0] data_wdata;
wire [31:0] data_rdata;
reg [31:0] mem_addr;
reg mem_req;
reg mem_write;
reg [3:0] mem_be;
reg [31:0] mem_wdata;
wire mem_rvalid;
wire [31:0] mem_rdata;
ibex_core #(
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000)
) u_core(
.clk_i(clk_sys),
.rst_ni(rst_sys_n),
.test_en_i('b0),
.hart_id_i(32'b0),
.boot_addr_i(32'h00000000),
.instr_req_o(instr_req),
.instr_gnt_i(instr_gnt),
.instr_rvalid_i(instr_rvalid),
.instr_addr_o(instr_addr),
.instr_rdata_i(instr_rdata),
.instr_err_i('b0),
.data_req_o(data_req),
.data_gnt_i(data_gnt),
.data_rvalid_i(data_rvalid),
.data_we_o(data_we),
.data_be_o(data_be),
.data_addr_o(data_addr),
.data_wdata_o(data_wdata),
.data_rdata_i(data_rdata),
.data_err_i('b0),
.irq_software_i(1'b0),
.irq_timer_i(1'b0),
.irq_external_i(1'b0),
.irq_fast_i(15'b0),
.irq_nm_i(1'b0),
.debug_req_i('b0),
.fetch_enable_i('b1),
.core_sleep_o()
);
always @(*) begin
mem_req = 1'b0;
mem_addr = 32'b0;
mem_write = 1'b0;
mem_be = 4'b0;
mem_wdata = 32'b0;
if (instr_req) begin
mem_req = ((instr_addr & ~MEM_MASK) == MEM_START);
mem_addr = instr_addr;
end
else if (data_req) begin
mem_req = ((data_addr & ~MEM_MASK) == MEM_START);
mem_write = data_we;
mem_be = data_be;
mem_addr = data_addr;
mem_wdata = data_wdata;
end
end
ram_1p #(.Depth((MEM_SIZE / 4))) u_ram(
.clk_i(clk_sys),
.rst_ni(rst_sys_n),
.req_i(mem_req),
.we_i(mem_write),
.be_i(mem_be),
.addr_i(mem_addr),
.wdata_i(mem_wdata),
.rvalid_o(mem_rvalid),
.rdata_o(mem_rdata)
);
assign instr_rdata = mem_rdata;
assign data_rdata = mem_rdata;
assign instr_rvalid = mem_rvalid;
always @(posedge clk_sys or negedge rst_sys_n)
if (!rst_sys_n) begin
instr_gnt <= 'b0;
data_gnt <= 'b0;
data_rvalid <= 'b0;
end
else begin
instr_gnt <= (instr_req && mem_req);
data_gnt <= ((~instr_req && data_req) && mem_req);
data_rvalid <= ((~instr_req && data_req) && mem_req);
end
reg [3:0] leds;
always @(posedge clk_sys or negedge rst_sys_n)
if (!rst_sys_n)
leds <= 4'b0;
else if (((mem_req && data_req) && data_we)) begin : sv2v_autoblock_1
reg signed [31:0] i;
for (i = 0; (i < 4); i = (i + 1))
if ((data_be[i] == 1'b1))
leds <= data_wdata[(i * 8)+:4];
end
assign LED = leds;
clkgen_xil7series clkgen(
.IO_CLK(IO_CLK),
.IO_RST_N(IO_RST_N),
.clk_sys(clk_sys),
.rst_sys_n(rst_sys_n)
);
endmodule
|
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_router
import bsg_wormhole_router_pkg::StrictXY;
import bsg_wormhole_router_pkg::StrictX;
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter dims_p = 2 // 1
,parameter dirs_lp = dims_p*2+1
// this list determines the range of bit values used to determine each dimension in the N-D router
// cord_dims_p is normally the same as dims_p. However, the override allows users to pass
// a larger cord array than necessary, useful for parameterizing between 1d/nd networks
,parameter cord_dims_p = dims_p
,parameter int cord_markers_pos_p[cord_dims_p:0] = '{ 5, 4, 0 } // '{5,0} //
,parameter bit [1:0][dirs_lp-1:0][dirs_lp-1:0] routing_matrix_p = (dims_p == 2) ? StrictXY : StrictX
,parameter reverse_order_p = 0
,parameter `BSG_INV_PARAM(len_width_p)
,parameter debug_lp = 0
)
(input clk_i
,input reset_i
// Traffics
,input [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_i
,output [dirs_lp-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] link_o
// My coordinate data
,input [cord_markers_pos_p[dims_p]-1:0] my_cord_i
);
localparam input_dirs_lp = dirs_lp;
localparam output_dirs_lp = dirs_lp;
// FIXME: move to bsg_wormhole_router.vh
`declare_bsg_wormhole_router_header_s(cord_markers_pos_p[dims_p], len_width_p, bsg_wormhole_router_header_s);
`ifndef SYNTHESIS
wire [dirs_lp-1:0][dirs_lp-1:0] matrix_out_in_transpose;
bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) tr (.i(routing_matrix_p[0])
,.o(matrix_out_in_transpose)
);
always_ff @(negedge reset_i)
begin
assert (routing_matrix_p[1] == matrix_out_in_transpose)
else $error("inconsistent matrixes");
end
`endif
// we collect the information for each FIFO here
wire [input_dirs_lp-1:0][flit_width_p-1:0] fifo_data_lo;
wire [input_dirs_lp-1:0] fifo_valid_lo;
// one for each input channel; it broadcasts that it is finished to all of the outputs
wire [dirs_lp-1:0] releases;
// from each input to each output
wire [dirs_lp-1:0][dirs_lp-1:0] reqs, reqs_transpose;
// from each output to each input
wire [dirs_lp-1:0][dirs_lp-1:0] yumis, yumis_transpose;
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [dirs_lp-1:0] link_i_cast, link_o_cast;
assign link_i_cast = link_i;
assign link_o = link_o_cast;
genvar i,j;
for (i = 0; i < input_dirs_lp; i=i+1)
begin: in_ch
localparam output_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[0][i]);
// live decoding of output dirs from header
wire [output_dirs_lp-1:0] decoded_dest_lo;
wire [output_dirs_sparse_lp-1:0] decoded_dest_sparse_lo;
wire [output_dirs_sparse_lp-1:0] reqs_lo, yumis_li;
bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc
(.i(yumis_transpose[i])
,.o(yumis_li)
);
wire any_yumi = | yumis_li;
bsg_two_fifo #(.width_p(flit_width_p)) twofer
(.clk_i
,.reset_i
,.ready_o(link_o_cast[i].ready_and_rev)
,.data_i (link_i_cast[i].data)
,.v_i (link_i_cast[i].v)
,.v_o (fifo_valid_lo[i])
,.data_o (fifo_data_lo [i])
,.yumi_i (any_yumi)
);
bsg_wormhole_router_header_s hdr;
assign hdr = fifo_data_lo[i][$bits(bsg_wormhole_router_header_s)-1:0];
`ifndef SYNTHESIS
if (debug_lp)
begin
logic release_r;
always_ff @(posedge clk_i)
release_r <= releases[i];
always_ff @(negedge clk_i)
begin
if (releases[i] & ~release_r)
$display("%m in ch%2d: packet finished last cycle",i);
if ((reset_i === 1'b0) && link_i_cast[i].v && !link_o_cast[i].ready_and_rev)
$display("%m in ch%2d: nacking packet %h",i,link_i_cast[i].data);
else
if ((reset_i === 1'b0) && link_i_cast[i].v && link_o_cast[i].ready_and_rev)
$display("%m in ch%2d: accepting packet %h",i,link_i_cast[i].data);
if ((reset_i === 1'b0) && any_yumi)
begin
assert (fifo_valid_lo[i]) else $error("Error dequeing when data not available");
if (reqs_lo)
$display("%m in ch%2d: dequeing header %h (outch=%b,len=%b,dest=%b)",i,fifo_data_lo[i],reqs_lo,hdr.len,hdr.cord);
else
$display ("%m in ch%2d: dequeing packet %h",i, fifo_data_lo[i]);
end
end // always_ff @
end
`endif
bsg_wormhole_router_decoder_dor #(.dims_p(dims_p)
,.cord_dims_p(cord_dims_p)
,.reverse_order_p(reverse_order_p)
,.cord_markers_pos_p(cord_markers_pos_p)
) dor
(.target_cord_i(hdr.cord)
,.my_cord_i
,.req_o(decoded_dest_lo)
);
bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) conc_dec
(.i(decoded_dest_lo)
,.o(decoded_dest_sparse_lo)
);
// fixme: add assertions for stubbed out parameters
wire detected_header_lo;
bsg_wormhole_router_input_control #(.output_dirs_p(output_dirs_sparse_lp), .payload_len_bits_p($bits(hdr.len))) wic
(.clk_i
,.reset_i
,.fifo_v_i (fifo_valid_lo[i])
,.fifo_yumi_i (any_yumi)
,.fifo_decoded_dest_i(decoded_dest_sparse_lo)
,.fifo_payload_len_i (hdr.len)
,.reqs_o (reqs_lo)
,.release_o (releases[i]) // broadcast to all
,.detected_header_o (detected_header_lo)
);
// switch to dense matrix form
bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[0][i])) unc
(.i (reqs_lo)
,.o (reqs[i]) // unicast
);
`ifndef SYNTHESIS
always_ff @(negedge clk_i)
if (debug_lp)
assert (detected_header_lo!==1'b1 || !(decoded_dest_lo & ~ routing_matrix_p[0][i]))
else $error("%m input port %d request to route in direction not supported by router %b %b",i,decoded_dest_lo, routing_matrix_p[0][i]);
`endif
end
// flip signal wires from input-indexed to output-indexed
// this is swizzling the wires that connect input ports and output ports
bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) reqs_trans
(.i(reqs)
,.o(reqs_transpose)
);
// iterate through each output channel
for (i = 0; i < output_dirs_lp; i=i+1)
begin: out_ch
localparam input_dirs_sparse_lp = `BSG_COUNTONES_SYNTH(routing_matrix_p[1][i]);
wire [input_dirs_sparse_lp-1:0] reqs_li, release_li, valids_li, yumis_lo, data_sel_lo;
wire [input_dirs_sparse_lp-1:0][flit_width_p-1:0] fifo_data_sparse_lo;
bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc
(.i(reqs_transpose[i]),.o(reqs_li));
bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc2
(.i(releases),.o(release_li));
bsg_concentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) conc3
(.i(fifo_valid_lo),.o(valids_li));
bsg_array_concentrate_static #(.width_p(flit_width_p), .pattern_els_p(routing_matrix_p[1][i])) conc4
(.i(fifo_data_lo),.o(fifo_data_sparse_lo));
bsg_wormhole_router_output_control #(.input_dirs_p(input_dirs_sparse_lp)) woc
(.clk_i
,.reset_i
,.reqs_i (reqs_li )
,.release_i (release_li)
,.valid_i (valids_li )
,.yumi_o (yumis_lo )
,.ready_i (link_i_cast[i].ready_and_rev)
,.valid_o (link_o_cast[i].v)
,.data_sel_o(data_sel_lo)
);
`ifndef SYNTHESIS
always_ff @(negedge clk_i)
begin
if (debug_lp)
begin
if ((reset_i === 1'b0) && link_o_cast[i].v)
begin
if (link_i_cast[i].ready_and_rev)
begin
$display("%m out ch%2d: sending packet %h",i,link_o_cast[i].data);
end
end
end
end
`endif
bsg_mux_one_hot #(.width_p(flit_width_p)
,.els_p(input_dirs_sparse_lp)
) data_mux
(.data_i(fifo_data_sparse_lo)
,.sel_one_hot_i(data_sel_lo)
,.data_o(link_o_cast[i].data)
);
bsg_unconcentrate_static #(.pattern_els_p(routing_matrix_p[1][i])) unc1
(.i (yumis_lo)
,.o (yumis[i])
);
end
// flip signal wires from output-indexed to input-indexed
// this is swizzling the wires that connect input ports and output ports
bsg_transpose #(.width_p(dirs_lp),.els_p(dirs_lp)) yumis_trans
(.i(yumis)
,.o(yumis_transpose)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_router)
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE;
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n, a, b; cin >> n >> a >> b; vector<int> c(n); for (int i = 0; i < n; ++i) { cin >> c[i]; } int i = 0, j = n - 1; int ans = 0; while (i < j) { if (c[i] == c[j] && c[i] != 2) { ++i; --j; } else if (c[i] != c[j] && c[i] != 2 && c[j] != 2) { cout << -1; return 0; } else if (c[i] == 2 && c[j] != 2) { if (c[j] == 0) ans += a; else if (c[j] == 1) ans += b; ++i; --j; } else if (c[j] == 2 && c[i] != 2) { if (c[i] == 0) ans += a; else if (c[i] == 1) ans += b; ++i; --j; } else if (c[i] == c[j] && c[i] == 2) { ans += 2 * min(a, b); ++i; --j; } } if (n % 2 && c[i] == 2) { ans += min(a, b); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int n, k; long long s[211111], mx[211111]; int a[211111], bg[211111]; long long hf, ans; int bhf, aa, bb; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); s[i] = s[i - 1] + a[i]; } for (int i = k; i <= n; ++i) { if (s[i] - s[i - k] > mx[i - 1]) { mx[i] = s[i] - s[i - k]; bg[i] = i - k + 1; } else mx[i] = mx[i - 1], bg[i] = bg[i - 1]; } hf = 0; for (int i = n - k + 1; i >= 1; --i) { if (mx[i] + hf >= ans) { long long tmp = ans; ans = mx[i] + hf; if (tmp < ans) aa = bg[i], bb = bhf; if (bg[i] < aa || (bg[i] == aa && bhf < bb)) { aa = bg[i], bb = bhf; } } if (s[i + k - 1] - s[i - 1] >= hf) { hf = s[i + k - 1] - s[i - 1]; bhf = i; } } cout << aa << << bb << endl; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- Tristate powergating support
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 09/20/11 - CR 625564 -- Fixed Tristate powergating polarity
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_INTERMDISABLE (O, IO, I, IBUFDISABLE, INTERMDISABLE, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter SLEW = "SLOW";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
inout IO;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
input T;
wire ts,out_val;
wire T_OR_IBUFDISABLE;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
// buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE")) begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on IOBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are 7SERIES or ULTRASCALE.",SIM_DEVICE);
$finish;
end
end // initial begin
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
"ULTRASCALE" : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign T_OR_IBUFDISABLE = ~T || IBUFDISABLE;
assign O = (T_OR_IBUFDISABLE == 1'b1) ? out_val : (T_OR_IBUFDISABLE == 1'b0) ? IO : 1'bx;
end
"FALSE" : begin
assign O = IO;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => IO) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => IO) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* PTP tag insert module
*/
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 17:25:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.v
// Design : system_vga_sync_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
module system_vga_sync_reset_0_0(clk, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
//[Disclaimer] Integrated Silicon Solutions Inc. ("ISSI") hereby grants the
// user of this model a non-exclusive, nontransferable
// license to use this model under the following terms.
// The user is granted this license only to use the model
// and is not granted rights to sell, copy (except as needed to
// run the model), rent, lease or sub-license the model
// in whole or in part, or in modified form to anyone.
// The User may modify the model to suit its specific
// applications, but rights to derivative works and such
// modifications shall belong to ISSI.
//
// This model is provided on an "AS IS" basis and ISSI
// makes absolutely no warranty with respect to the information
// contained herein. ISSI DISCLAIMS AND CUSTOMER WAIVES ALL
// WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
// ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE
// USER ACCORDINGLY, IN NO EVENT SHALL ISSI BE LIABLE
// FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN CONTRACT OR
// TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,
// CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF
// THE USE OR APPLICATION OF THE model. Further, ISSI
// reserves the right to make changes without notice to any
// product herein to improve reliability, function, or design.
// ISSI does not convey any license under patent rights or
// any other intellectual property rights, including those of
// third parties. ISSI is not obligated to provide maintenance
// or support for the licensed model.
// IS61LV6416L Asynchronous SRAM, 64K x 16 = 1M; speed: 10ns. File: ASRAM.8130.1
// Please include "+define+ OEb" in running script if you want to check
// timing in the case of OE_ being set.
//`define OEb
`timescale 1ns/10ps
module IS61LV6416L (A, IO, CE_, OE_, WE_, LB_, UB_);
parameter dqbits = 16;
parameter memdepth = 65535;
parameter addbits = 16;
parameter Taa = 10;
parameter Toha = 3;
parameter Thzce = 4;
parameter Tsa = 0;
parameter Thzwe = 5;
input wire CE_, OE_, WE_, LB_, UB_;
input wire [(addbits - 1) : 0] A;
inout wire [(dqbits - 1) : 0] IO;
wire [(dqbits - 1) : 0] dout;
reg [(dqbits/2 - 1) : 0] bank0 [0 : memdepth];
reg [(dqbits/2 - 1) : 0] bank1 [0 : memdepth];
// wire [(dqbits - 1) : 0] memprobe = {bank1[A], bank0[A]};
wire r_en = WE_ & (~CE_) & (~OE_);
wire w_en = (~WE_) & (~CE_) & ((~LB_) | (~UB_));
assign #(r_en ? Taa : Thzce) IO = r_en ? dout : 16'bz;
assign dout [(dqbits/2 - 1) : 0] = LB_ ? 8'bz : bank0[A];
assign dout [(dqbits - 1) : (dqbits/2)] = UB_ ? 8'bz : bank1[A];
always @(A or w_en)
begin
#Tsa
if (w_en)
#Thzwe
begin
bank0[A] = LB_ ? bank0[A] : IO [(dqbits/2 - 1) : 0];
bank1[A] = UB_ ? bank1[A] : IO [(dqbits - 1) : (dqbits/2)];
end
end
specify
specparam
tSA = 0,
tAW = 8,
tSCE = 8,
tSD = 6,
tPWE2 = 10,
tPWE1 = 8,
tPBW = 8;
$setup (A, negedge CE_, tSA);
$setup (A, posedge CE_, tAW);
$setup (IO, posedge CE_, tSD);
$setup (A, negedge WE_, tSA);
$setup (IO, posedge WE_, tSD);
$setup (A, negedge LB_, tSA);
$setup (A, negedge UB_, tSA);
$width (negedge CE_, tSCE);
$width (negedge LB_, tPBW);
$width (negedge UB_, tPBW);
`ifdef OEb
$width (negedge WE_, tPWE1);
`else
$width (negedge WE_, tPWE2);
`endif
endspecify
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; int main() { int n, k; scanf( %d , &n), scanf( %d , &k); if (k % 2 == 0) { int ans = 0; while (n--) { int x; scanf( %d , &x); if (x == 1) ans ^= 1; if (x == 2) ans ^= 2; if (x > 2) ans ^= !(x % 2); } if (ans) printf( Kevin n ); else printf( Nicky n ); return 0; } function<int(int)> f = [&f](int i) { if (i == 0) return 0; if (i == 1) return 1; if (i == 2) return 0; if (i == 3) return 1; if (i == 4) return 2; if (i == 5) return 0; if (i % 2 == 1) return 0; set<int> second; second.insert(f(i - 1)); second.insert(f(i / 2)); int ret = 0; while (second.count(ret)) ret++; return ret; }; int ans = 0; while (n--) { int x; scanf( %d , &x); ans ^= f(x); } if (ans) printf( Kevin n ); else printf( Nicky n ); exit(0); }
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_arb_mux_64_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_0_axis_tdata = 0;
reg [7:0] input_0_axis_tkeep = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [63:0] input_1_axis_tdata = 0;
reg [7:0] input_1_axis_tkeep = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [63:0] input_2_axis_tdata = 0;
reg [7:0] input_2_axis_tkeep = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [63:0] input_3_axis_tdata = 0;
reg [7:0] input_3_axis_tkeep = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [63:0] output_axis_tdata;
wire [7:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tkeep,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tkeep,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tkeep,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tkeep,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tkeep,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_arb_mux_64_4.lxt");
$dumpvars(0, test_axis_arb_mux_64_4);
end
axis_arb_mux_64_4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tkeep(input_0_axis_tkeep),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tkeep(input_1_axis_tkeep),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tkeep(input_2_axis_tkeep),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tkeep(input_3_axis_tkeep),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 2, M = 6e5 + 2, O = 1.2e6 + 2; long long len1[M], len2[M], v[N], g[N][4], ans[M]; long long lx, ly; int lj[M], nxt[M], fir[N], f[N], qlj[O], qnxt[O], qfir[N], xw[O][3]; int flj[M], fnxt[M], ffir[N]; int n, q, i, x, y, c, bs, qs, fs; bool ed[N]; inline void read(int &x) { c = getchar(); while ((c < 48) || (c > 57)) c = getchar(); x = c ^ 48; c = getchar(); while ((c >= 48) && (c <= 57)) { x = x * 10 + (c ^ 48); c = getchar(); } } inline void read(long long &x) { c = getchar(); while ((c < 48) || (c > 57)) c = getchar(); x = c ^ 48; c = getchar(); while ((c >= 48) && (c <= 57)) { x = x * 10 + (c ^ 48); c = getchar(); } } inline void add() { lj[++bs] = y; len1[bs] = lx; len2[bs] = ly; nxt[bs] = fir[x]; fir[x] = bs; lj[++bs] = x; len1[bs] = lx; len2[bs] = ly; nxt[bs] = fir[y]; fir[y] = bs; } inline void fadd(int x, int y) { flj[++fs] = y; fnxt[fs] = ffir[x]; ffir[x] = fs; } inline void qadd(int x, int y, int i) { qlj[++qs] = i; qnxt[qs] = qfir[x]; qfir[x] = qs; } void dfs1(int x) { ed[x] = 1; for (int i = fir[x]; i; i = nxt[i]) if (!ed[lj[i]]) { dfs1(lj[i]); v[x] = min(v[x], v[lj[i]] + len1[i] + len2[i]); } ed[x] = 0; } void dfs2(int x) { ed[x] = 1; for (int i = fir[x]; i; i = nxt[i]) if (!ed[lj[i]]) { v[lj[i]] = min(v[lj[i]], v[x] + len1[i] + len2[i]); dfs2(lj[i]); } ed[x] = 0; } void dfs3(int x) { ed[x] = 1; for (int i = fir[x]; i; i = nxt[i]) if (!ed[lj[i]]) { g[lj[i]][0] = min(len2[i], v[x] + v[lj[i]] + len1[i]); g[lj[i]][1] = min(len2[i] + v[lj[i]], len1[i] + v[x]); g[lj[i]][2] = min(len1[i] + v[lj[i]], len2[i] + v[x]); g[lj[i]][3] = min(len1[i], v[x] + v[lj[i]] + len2[i]); dfs3(lj[i]); } ed[x] = 0; } void getf(register int x) { if (f[f[x]] == f[x]) return; getf(f[x]); g[0][0] = min(g[x][0] + g[f[x]][0], g[x][2] + g[f[x]][1]); g[0][1] = min(g[x][1] + g[f[x]][0], g[x][3] + g[f[x]][1]); g[0][2] = min(g[x][0] + g[f[x]][2], g[x][2] + g[f[x]][3]); g[0][3] = min(g[x][1] + g[f[x]][2], g[x][3] + g[f[x]][3]); memcpy(g[x], g[0], 32); f[x] = f[f[x]]; } void dfs4(int x) { ed[x] = 1; int i; for (i = qfir[x]; i; i = qnxt[i]) if (ed[y = xw[qlj[i]][2]]) { getf(y); fadd(f[y], qlj[i]); } for (i = fir[x]; i; i = nxt[i]) if (!ed[lj[i]]) { dfs4(lj[i]); f[lj[i]] = x; } for (i = ffir[x]; i; i = fnxt[i]) { y = flj[i]; if (y > q) c = y - q; else c = y; if (xw[y][2] != x) { qs = xw[y][0] >> 1 & 1; bs = xw[y][0] & 1; getf(xw[y][1]); getf(xw[y][2]); ans[c] = min(g[xw[y][1]][bs] + g[xw[y][2]][qs], g[xw[y][1]][bs | 2] + g[xw[y][2]][qs | 2]); } else { getf(xw[y][1]); ans[c] = g[xw[y][1]][xw[y][0]]; } } } int main() { read(n); for (i = 1; i <= n; i++) read(v[i]); for (i = 1; i < n; i++) { read(x); read(y); read(lx); read(ly); add(); f[i] = i; } dfs1(1); dfs2(1); dfs3(1); read(q); for (i = 1; i <= q; i++) { read(x); read(y); if (x + 1 >> 1 == y + 1 >> 1) { if (x != y) ans[i] = v[x + 1 >> 1]; continue; } xw[i][0] = (x & 1) | (y & 1) << 1; xw[i + q][0] = (y & 1) | (x & 1) << 1; qadd(xw[i][1] = xw[i + q][2] = x = x + 1 >> 1, xw[i][2] = xw[i + q][1] = y = y + 1 >> 1, i); qadd(y, x, i + q); } dfs4(1); for (i = 1; i <= q; i++) printf( %lld n , ans[i]); }
|
#include <bits/stdc++.h> using namespace std; inline char getc() { static char buf[1 << 20], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> void rd(T& x) { int f = 0, c; while (!isdigit(c = getc())) f ^= !(c ^ 45); x = (c & 15); while (isdigit(c = getc())) x = x * 10 + (c & 15); if (f) x = -x; } template <typename T> void pt(T x, int c = -1) { if (x < 0) putchar( - ), x = -x; if (x > 9) pt(x / 10); putchar(x % 10 + 48); if (c != -1) putchar(c); } const int N = 200005; int n, m, Q, dp[N]; long long a[N]; namespace xay1 { void sol() { while (Q--) { int t; rd(t); if (t == 1) { int l, r, d; rd(l), rd(r), rd(d); if (d & 1) for (int i = (l); i <= (r); ++i) a[i] ^= 1; } else { int l, r; rd(l), rd(r); int s = 0; for (int i = (r); i >= (l); --i) { dp[i] = a[i] & 1; if (s) dp[i] = 0; s = (s << 1 | dp[i]) & ((1 << m) - 1); } if (dp[l]) puts( 2 ); else puts( 1 ); } } } } // namespace xay1 namespace xay2 { struct node { int w[22], len; } t[N * 4][2]; int tg[N * 4]; void pst(int k1) { tg[k1] ^= 1, swap(t[k1][0], t[k1][1]); } void psd(int k1) { if (tg[k1]) { pst(k1 * 2); pst(k1 * 2 + 1); tg[k1] = 0; } } node mer(const node& k1, const node& k2) { node k3; k3.len = k1.len + k2.len; for (int i = (1); i <= (m + 1); ++i) { if (k2.w[i] == -1) { if (k1.w[min(m + 1, i + k2.len)] == -1) { k3.w[i] = -1; } else k3.w[i] = k1.w[min(m + 1, i + k2.len)]; } else { if (k1.w[k2.w[i]] == -1) { k3.w[i] = min(m + 1, k1.len + k2.w[i]); } else k3.w[i] = k1.w[k2.w[i]]; } } return k3; } void upd(int k1) { t[k1][0] = mer(t[k1 * 2][0], t[k1 * 2 + 1][0]); t[k1][1] = mer(t[k1 * 2][1], t[k1 * 2 + 1][1]); } void bud(int k1, int k2, int k3) { if (k2 == k3) { t[k1][0].len = t[k1][1].len = 1; if (a[k2] & 1) { for (int i = (1); i <= (m); ++i) t[k1][0].w[i] = -1; t[k1][0].w[m + 1] = 1; for (int i = (1); i <= (m + 1); ++i) t[k1][1].w[i] = -1; } else { for (int i = (1); i <= (m); ++i) t[k1][1].w[i] = -1; t[k1][1].w[m + 1] = 1; for (int i = (1); i <= (m + 1); ++i) t[k1][0].w[i] = -1; } return; } psd(k1); int mid = (k2 + k3) >> 1; bud(k1 * 2, k2, mid), bud(k1 * 2 + 1, mid + 1, k3); upd(k1); } void mdf(int k1, int k2, int k3, int k4, int k5) { if (k2 > k5 || k3 < k4) return; if (k4 <= k2 && k3 <= k5) { pst(k1); return; } psd(k1); int mid = (k2 + k3) >> 1; mdf(k1 * 2, k2, mid, k4, k5), mdf(k1 * 2 + 1, mid + 1, k3, k4, k5); upd(k1); } int res; void ask(int k1, int k2, int k3, int k4, int k5) { if (k2 > k5 || k3 < k4) return; if (k4 <= k2 && k3 <= k5) { if (t[k1][0].w[res] == -1) { res = min(m + 1, res + t[k1][0].len); } else { res = t[k1][0].w[res]; } return; } psd(k1); int mid = (k2 + k3) >> 1; ask(k1 * 2 + 1, mid + 1, k3, k4, k5); ask(k1 * 2, k2, mid, k4, k5); } void sol() { bud(1, 1, n); while (Q--) { int t; rd(t); if (t == 1) { int l, r; long long d; rd(l), rd(r), rd(d); if (d & 1) { mdf(1, 1, n, l, r); } } else { int l, r; rd(l), rd(r); res = m + 1; ask(1, 1, n, l, r); if (res == 1) puts( 2 ); else puts( 1 ); } } } } // namespace xay2 int main() { rd(n), rd(m), rd(Q); for (int i = (1); i <= (n); ++i) rd(a[i]), a[i] &= 1; if (n <= 5000 && m <= 5000) { xay1::sol(); } else { xay2::sol(); } return 0; }
|
module ADD_SUB(A, B, value_result_tens, value_result_units, sign_result, KEY_IN, clk, reset_n, operator);
output [3:0] value_result_tens;
output [3:0] value_result_units;
output [3:0] A;
output [3:0] B;
output sign_result;
input [1:0] operator;
input [3:0] KEY_IN;
input reset_n;
input clk;
/*
reg [3:0] A, B, value_result_tens, value_result_units;
reg sign_result;
wire [3:0] next_A, next_B, next_ten, next_unit, next_In;
wire next_sign;
*/
reg [3:0] next_A, next_B, next_ten, next_unit;
reg slt;
reg next_sign;
reg tmpIn;
// add your design here
always @(posedge clk) begin
if (!reset_n) begin
next_A <= 0;
next_B <= 0;
next_ten <= 0;
next_unit <= 0;
next_sign <= 0;
slt <= 0;
end else begin
if (KEY_IN == 4'hA) begin
slt <= 0;
end else if (KEY_IN == 4'hB) begin
slt <= 1;
end else begin
if (slt == 0) begin
next_A <= KEY_IN;
end else begin
next_B <= KEY_IN;
end
end
if (operator[0] == 0) begin
if (A+B >= 10) begin
next_ten <= 1;
next_unit <= A + B - 10;
end else begin
next_ten <= 0;
next_unit <= A + B;
end
next_sign <= 0;
end else if (operator[1] == 0) begin
if (A > B || A == B) begin
{next_ten, next_unit} <= A - B;
next_sign <= 0;
end else begin
{next_ten, next_unit} <= B - A;
next_sign <= 1;
end
end else begin
{next_ten, next_unit} <= {next_ten, next_unit};
end
end
end
assign A = next_A;
assign B = next_B;
assign value_result_tens = next_ten;
assign value_result_units = next_unit;
assign sign_result = next_sign;
/*
always @(posedge clk) begin
if (!reset_n) begin
A <= 0;
B <= 0;
value_result_tens <= 0;
value_result_units <= 0;
sign_result <= 0;
tmpIn <= 0;
end else begin
A <= next_A;
B <= next_B;
value_result_tens <= next_ten;
value_result_units <= next_unit;
sign_result <= next_sign;
tmpIn <= next_In;
end
end
*/
/*
assign next_In = (!reset_n)?(0):(KEY_IN);
assign next_A = (!reset_n)?
(0): // !reset_n
( // reset_n
(tmpIn == 4'hA)?
(KEY_IN): // tmpIn == 4'hA
(A) // tmpIn != 4'hA
);
assign next_B = (!reset_n)?
(0): // !reset_n
( // reset_n
(tmpIn == 4'hB)?
(KEY_IN): // tmpIn == 4'hB
(B) // tmpIn != 4'hB
);
assign {next_ten, next_unit} = (!reset_n)?
(0): // !reset_n
( // reset_n
(operator[0] == 0)?
( // add
A + B
):
( // do not add
(operator[1] == 0)?
( // sub
(A >= B)?
( // A >= B
A - B
):
( // A < B
B - A
)
):
( // do not add and sub
{value_result_tens, value_result_units}
)
)
);
assign next_sign = (!reset_n)?
(0): // !reset_n
( // reset_n
(operator[0] == 0)?
( // add
0
):
( // do not add
(operator[1] == 0)?
( // sub
(A >= B)?
( // A >= B
0
):
( // A < B
1
)
):
( // do not add and sub
sign_result
)
)
);
*/
/*
if (!reset_n) begin
assign next_A = 0;
assign next_B = 0;
assign next_ten = 0;
assign next_unit = 0;
assign next_sign = 0;
assign next_In = 0;
end else begin
assign next_In = KEY_IN;
if (tmpIn == 4'hA) begin
assign next_A = KEY_IN;
assign next_B = B;
end else if (tmpIn == 4'hB) begin
assign next_A = A;
assign next_B = KEY_IN;
end else begin
assign next_A = A;
assign next_B = B;
end
if (operator[0] == 0) begin
assign {next_ten, next_unit} = A + B;
assign next_sign = 0;
end else if (operator[1] == 0) begin
if (A >= B) begin
assign {next_ten, next_unit} = A - B;
assign next_sign = 0;
end else begin
assign {next_ten, next_unit} = B - A;
assign next_sign = 1;
end
end else begin
assign next_ten = value_result_tens;
assign next_unit = value_result_units;
assign next_sign = sign_result;
end
end // end of reset_n block
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100100]; int main() { int i, n; scanf( %d , &n); for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); int sign = 1; for (i = 0; i < n; i++) { if (a[i] >= sign) { a[i] = sign; sign++; } } printf( %d n , sign); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int b, w; cin >> w >> b; if (w == 0) cout << 0.000000000 << endl; else if (b == 0) cout << 1.000000000 << endl; else if (b == 1) printf( %.9f n , double(w) / (w + 1)); else if (b == 2) printf( %.9f n , double(w * (w + 1) + 2) / ((w + 1) * (w + 2))); else { double p[w + 1][b + 1]; if (b >= 2 * w) { for (int col = b - 2 * w; col >= 0; col -= 3) p[0][col] = 0.0; int startcol, endcol; for (int row = 1; row <= w; row++) { startcol = (b + w - row) % 3; endcol = b - 2 * (w - row); if (startcol == 0) p[row][startcol] = 1.0; else if (startcol == 1) p[row][startcol] = double(row) / (row + 1); else p[row][startcol] = double(row * (row + 1) + 2) / ((row + 1) * (row + 2)); for (int col = startcol + 3; col <= endcol; col += 3) { p[row][col] = double(row) / (row + col) + (p[row][col - 3] * (col - 2) + p[row - 1][col - 2] * row) * col * (col - 1) / (row + col) / (row + col - 1) / (row + col - 2); } } } else { int startcol, endcol; int firstrow = w - b / 2; for (int row = firstrow; row <= w; row++) { startcol = (b + w - row) % 3; endcol = b - 2 * (w - row); if (startcol == 0) p[row][startcol] = 1.0; else if (startcol == 1) p[row][startcol] = double(row) / (row + 1); else p[row][startcol] = double(row * (row + 1) + 2) / ((row + 1) * (row + 2)); for (int col = startcol + 3; col <= endcol; col += 3) { p[row][col] = double(row) / (row + col) + (p[row][col - 3] * (col - 2) + p[row - 1][col - 2] * row) * col * (col - 1) / (row + col) / (row + col - 1) / (row + col - 2); } } } printf( %.9f n , p[w][b]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct ln { long long m, k; ln(long long mm, long long kk) { m = mm; k = kk; } }; deque<ln> cvt; long long dp[100010][2]; long long sw[100010]; long long wt[100010]; long long hilldist[100010]; long long cs(long long x, int ci) { return x * cvt[ci].m + cvt[ci].k; } bool ex(long long m, long long k) { long long m1 = cvt[cvt.size() - 2].m; long long k1 = cvt[cvt.size() - 2].k; long long m2 = cvt[cvt.size() - 1].m; long long k2 = cvt[cvt.size() - 1].k; return (k1 - k2) * (m - m1) >= (k1 - k) * (m2 - m1); } int main() { int n, m, p; int d, h, t; scanf( %d%d%d , &n, &m, &p); for (int i = 2; i <= n; i++) { scanf( %d , &d); hilldist[i] = hilldist[i - 1] + d; } for (int i = 1; i <= m; i++) { scanf( %d%d , &h, &t); wt[i] = t - hilldist[h]; } sort(wt + 1, wt + m + 1); for (int i = 1; i <= m; i++) sw[i] = sw[i - 1] + wt[i]; int nx = 1, nw = 0; for (int i = 1; i <= m; i++) { dp[i][0] = wt[i] * i - sw[i]; } int k1; for (int k = 2; k <= p; k++) { cvt.clear(); k1 = k - 1; cvt.push_back(ln(-k1, sw[k1] + dp[k1][nw])); for (int i = 0; i <= m; i++) dp[i][nx] = 0; for (int i = k; i <= m; i++) { while (cvt.size() > 1 && cs(wt[i], 0) >= cs(wt[i], 1)) cvt.pop_front(); dp[i][nx] = cs(wt[i], 0) + wt[i] * (i)-sw[i]; while (cvt.size() > 1 && ex(-i, sw[i] + dp[i][nw])) cvt.pop_back(); cvt.push_back(ln(-i, sw[i] + dp[i][nw])); } swap(nx, nw); } cout << dp[m][nw]; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int> > data; vector<bool> used; vector<int> cycle; void dfs(int vertex, int last, vector<int> &path) { used[vertex] = true; path.push_back(vertex); for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (to == last) continue; if (used[to]) { if (!cycle.size()) { int index = path.size() - 1; while (path[index] != to) { cycle.push_back(path[index--]); } cycle.push_back(path[index]); } continue; } dfs(to, vertex, path); } path.pop_back(); } vector<bool> if_cycle; vector<int> sz, tree_ans, ans, szs; int dfs2(int vertex, int last, int number) { sz[number]++; szs[vertex] = 1; int tut = 1; for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (if_cycle[to] || to == last) continue; tut += dfs2(to, vertex, number); szs[vertex] += szs[to]; } tree_ans[number] += tut; return tut; } int n; void dfs3(int vertex, int last, int number, int cur) { ans[number] = max(ans[number], cur); for (int i = 0; i < data[vertex].size(); ++i) { int to = data[vertex][i]; if (if_cycle[to] || to == last) continue; dfs3(to, vertex, number, cur + n - 2 * szs[to]); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; data.assign(n, {}); for (int i = 0; i < n; ++i) { int u, v; cin >> u >> v; data[u].push_back(v), data[v].push_back(u); } used.assign(n, false); vector<int> p; dfs(0, -1, p); if_cycle.assign(n, false); for (int i = 0; i < cycle.size(); ++i) { if_cycle[cycle[i]] = true; } int S = cycle.size(); sz.assign(S, 0); tree_ans.assign(S, 0); szs.assign(n, 0); for (int i = 0; i < cycle.size(); ++i) { tree_ans[i] -= dfs2(cycle[i], -1, i); } ans.assign(S, 0); for (int i = 0; i < cycle.size(); ++i) { dfs3(cycle[i], -1, i, tree_ans[i] + n); } int dp[S], dp2[S], sums[S]; for (int i = 0; i < S; ++i) dp[i] = ans[i]; for (int len = 2; len <= S; len++) { sums[0] = 0; for (int i = 0; i < len - 1; ++i) sums[0] += sz[i]; int B = len - 1; for (int i = 1; i < S; ++i) { sums[i] = sums[i - 1] - sz[i - 1] + sz[B++]; if (B == S) B = 0; } int A = len - 1; for (int i = 0; i < S - 1; ++i) { dp2[i] = max(dp[i] + tree_ans[A++] + n - sums[i], tree_ans[i] + dp[i + 1] + n - sums[i + 1]); if (A == S) A = 0; } dp2[S - 1] = max(dp[S - 1] + tree_ans[A], tree_ans[S - 1] + dp[0] + n - sums[0]); for (int i = 0; i < S; ++i) { dp[i] = dp2[i]; } } int A = 0; for (int i = 0; i < S; ++i) A = max(A, dp[i]); cout << A; }
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Saturating counter branch predictor
This is FSM with 4 states: strongly not taken, weakly not taken,
weakly taken, strongly taken.
Fsm changes it state upon real(not predicted) flag.
If flag was "true" and instruction was bf or flag was "false" and
instruction was bnf fsm changes its state towards "taken". And vice versa
otherwise.
We predict flag on current fsm state and current branch type.
If we are in any "taken" state and current instruction is bf,
we predict flag to be "true". Or we're in any "not taken" state and
current instruction is bnf, we predict flag to be "true".
Copyright (C) 2016 Alexey Baturo <>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_branch_predictor_saturation_counter
(
input clk,
input rst,
// Signals belonging to the stage where the branch is predicted.
output predicted_flag_o, //result of predictor
input execute_op_bf_i, // prev insn was bf
input execute_op_bnf_i, // prev insn was bnf
input op_bf_i, // cur insn is bf
input op_bnf_i, // cur insn is bnf
input padv_decode_i, // pipeline is moved
input flag_i, // prev predicted flag
// Signals belonging to the stage where the branch is resolved.
input prev_op_brcond_i, // prev op was cond brn
input branch_mispredict_i // prev brn was mispredicted
);
localparam [1:0]
STATE_STRONGLY_NOT_TAKEN = 2'b00,
STATE_WEAKLY_NOT_TAKEN = 2'b01,
STATE_WEAKLY_TAKEN = 2'b10,
STATE_STRONGLY_TAKEN = 2'b11;
reg [1:0] state = STATE_WEAKLY_TAKEN;
assign predicted_flag_o = (state[1] && op_bf_i) || (!state[1] && op_bnf_i);
wire brn_taken = (execute_op_bf_i && flag_i) || (execute_op_bnf_i && !flag_i);
always @(posedge clk) begin
if (rst) begin
state <= STATE_WEAKLY_TAKEN;
end else begin
if (prev_op_brcond_i && padv_decode_i) begin
if (!brn_taken) begin
// change fsm state:
// STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
// STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
case (state)
STATE_STRONGLY_TAKEN:
state <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state <= STATE_STRONGLY_NOT_TAKEN;
STATE_STRONGLY_NOT_TAKEN:
state <= STATE_STRONGLY_NOT_TAKEN;
endcase
end else begin
// change fsm state:
// STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
// STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
// STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
// STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
case (state)
STATE_STRONGLY_NOT_TAKEN:
state <= STATE_WEAKLY_NOT_TAKEN;
STATE_WEAKLY_NOT_TAKEN:
state <= STATE_WEAKLY_TAKEN;
STATE_WEAKLY_TAKEN:
state <= STATE_STRONGLY_TAKEN;
STATE_STRONGLY_TAKEN:
state <= STATE_STRONGLY_TAKEN;
endcase
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod(long long v, long long k, long long p) { long long res = 1; for (long long i = 0; i < 4; i++) res *= v, res %= p; res -= ((k * v) % p); if (res < 0) res += p; return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, p, k; cin >> n >> p >> k; long long Array[n]; for (long long i = 0; i < n; i++) cin >> Array[i]; long long B[n]; for (long long i = 0; i < n; i++) B[i] = mod(Array[i], k, p); vector<long long> out; sort(B, B + n); long long cnt = 1; for (long long i = 0; i < n - 1; i++) { if (B[i + 1] != B[i] and cnt != 1) out.push_back(cnt), cnt = 1; else if (B[i + 1] == B[i]) cnt++; } if (cnt != 1) out.push_back(cnt); long long sum = 0; for (long long i = 0; i < out.size(); i++) sum += ((out[i] * (out[i] - 1)) / 2); cout << sum << n ; return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: two_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module two_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/two_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/two_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/two_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_1_V
`define SKY130_FD_SC_LS__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Write-back Mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// CPU's write-back stage of the pipeline ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_wbmux.v,v $
// Revision 1.3 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_wbmux(
// Clock and reset
clk, rst,
// Internal i/f
wb_freeze, rfwb_op,
muxin_a, muxin_b, muxin_c, muxin_d,
muxout, muxreg, muxreg_valid
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Internal i/f
//
input wb_freeze;
input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
input [width-1:0] muxin_a;
input [width-1:0] muxin_b;
input [width-1:0] muxin_c;
input [width-1:0] muxin_d;
output [width-1:0] muxout;
output [width-1:0] muxreg;
output muxreg_valid;
//
// Internal wires and regs
//
reg [width-1:0] muxout;
reg [width-1:0] muxreg;
reg muxreg_valid;
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or posedge rst) begin
if (rst) begin
muxreg <= #1 32'd0;
muxreg_valid <= #1 1'b0;
end
else if (!wb_freeze) begin
muxreg <= #1 muxout;
muxreg_valid <= #1 rfwb_op[0];
end
end
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
2'b00: muxout = muxin_a;
2'b01: begin
muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
end
2'b10: begin
muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
end
2'b11: begin
muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
end
endcase
end
//
// Abstruct the signal we are interested in
//
//always @(posedge clk or posedge rst)
// $show_signal_value(or1200_wbmux, muxreg_valid);
endmodule
|
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 50;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 100;
//// Clock Buffer
`ifndef SIM
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
`endif
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [30:0] nonce = 31'd254, nonce2 = 31'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Dual-Hasher
wire [255:0] hash0, hash1;
wire [31:0] hash2_w0, hash2_w1;
dual_sha256_transform first_hash_blk (
.clk (hash_clk),
.rx_state (midstate),
.rx_nonce (nonce),
.rx_input (data),
.tx_hash0 (hash0),
.tx_hash1 (hash1)
);
second_sha256_transform second_hash0_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash0}),
.tx_hash (hash2_w0)
);
second_sha256_transform second_hash1_blk (
.clk (hash_clk),
.rx_input ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash1}),
.tx_hash (hash2_w1)
);
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~254 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 31'd127;
nonce2 <= 31'd0;
end
else
begin
nonce <= nonce + 31'd1;
nonce2 <= nonce2 + 31'd1;
end
`ifndef SIM
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
`endif
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 31'h7FFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
if (hash2_w0 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b0, nonce2};
end
else if (hash2_w1 == 32'hA41F32E7)
begin
is_golden_ticket <= 1'b1;
golden_nonce <= {1'b1, nonce2};
end
else
is_golden_ticket <= 1'b0;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_1_V
`define SKY130_FD_SC_MS__FAHCIN_1_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog wrapper for fahcin with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fahcin.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcin_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fahcin base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_1_V
|
// $Id: c_select_mofn.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic multi-hot select gate
//==============================================================================
module c_select_mofn
(select, data_in, data_out);
`include "c_constants.v"
// number of input ports
parameter num_ports = 4;
// width of each port
parameter width = 32;
// multiplication operator
parameter prod_op = `BINARY_OP_AND;
// addition operator
parameter sum_op = `BINARY_OP_OR;
// control signal to select active port
input [0:num_ports-1] select;
// vector of inputs
input [0:num_ports*width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:width_loop
wire [0:num_ports-1] port_bits;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:ports_loop
c_binary_op
#(.num_ports(2),
.width(1),
.op(prod_op))
prod
(.data_in({data_in[i+j*width], select[j]}),
.data_out(port_bits[j]));
end
c_binary_op
#(.num_ports(num_ports),
.width(1),
.op(sum_op))
sum
(.data_in(port_bits),
.data_out(data_out[i]));
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, M[2002][2002]; bool V[2002]; vector<int> L, L_; void dfs(int inicial, vector<int> &Li) { Li.push_back(inicial); V[inicial] = 1; for (int i = 0; i < n; ++i) if (!V[i] && M[inicial][i]) dfs(i, Li); } bool Conexo() { dfs(0, L); for (int i = 0; i < n; ++i) for (int j = 0; j <= i; ++j) swap(M[i][j], M[j][i]); memset(V, 0, sizeof V); dfs(0, L_); return L.size() == n && L_.size() == n; } int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) scanf( %d , &M[i][j]); if (Conexo()) printf( YES n ); else printf( NO n ); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(3), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(10), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_BLACKBOX_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long maxm = 2e5 + 5; vector<long long> g[maxm]; long long mark[maxm]; long long p[maxm]; long long c[maxm]; long long ans; long long n; void solve(long long x) { vector<long long> s; while (!mark[x]) { s.push_back(x); mark[x] = 1; x = p[x]; } long long len = s.size(); for (long long i = 1; i <= len; i++) { if (len % i == 0) { for (long long j = 0; j < i; j++) { long long ok = 1; for (long long k = j; k + i < len; k += i) { if (c[s[k]] != c[s[k + i]]) { ok = 0; break; } } if (ok) { ans = min(ans, i); return; } } } } } signed main() { long long T; cin >> T; while (T--) { cin >> n; ans = n; for (long long i = 1; i <= n; i++) cin >> p[i]; for (long long i = 1; i <= n; i++) cin >> c[i]; for (long long i = 1; i <= n; i++) mark[i] = 0; for (long long i = 1; i <= n; i++) if (!mark[i]) solve(i); cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; char _buf[100000], *_p1 = _buf, *_p2 = _buf; inline int gi() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return (f == 1) ? x : -x; } const int maxn = 2e5 + 5, inf = 1e9, mod = 1e9 + 7; int n, k, a[maxn]; vector<pair<int, int>> e[maxn]; int siz[maxn], maxv[maxn], rt, dis[maxn]; long long val[maxn], ans; vector<int> now; struct segmentree { static const int maxn = 8e5 + 5; long long sum[maxn]; inline void pushup(int u) { sum[u] = sum[u << 1] + sum[u << 1 | 1]; } inline void update(int u, int l, int r, int x, long long v) { if (l == r) return sum[u] += v, void(); int mid = (l + r) >> 1; if (x <= mid) update(u << 1, l, mid, x, v); else update(u << 1 | 1, mid + 1, r, x, v); pushup(u); } inline long long query(int u, int l, int r, int x, int y) { if (x <= l && y >= r) return sum[u]; int mid = (l + r) >> 1; long long ret = 0; if (x <= mid) ret = query(u << 1, l, mid, x, y); if (y > mid) ret += query(u << 1 | 1, mid + 1, r, x, y); return ret; } } tree[2], T[2]; inline void init() {} inline void input() { n = gi(), k = gi(); for (int i = 1; i <= n; ++i) a[i] = gi(); for (int i = 1; i <= n - 1; ++i) { int u = gi(), v = gi(), w = gi(); e[u].push_back({v, w}); e[v].push_back({u, w}); } } bool vis[maxn]; int sum; inline void getrt(int u, int fa) { now.push_back(u); siz[u] = 1; maxv[u] = 0; for (auto x : e[u]) { int v = x.first; if (v == fa || vis[v]) continue; getrt(v, u); siz[u] += siz[v]; maxv[u] = max(maxv[u], siz[v]); } maxv[u] = max(maxv[u], sum - siz[u]); if (maxv[u] < maxv[rt]) rt = u; } inline void getdis(int u, int fa, int nowc) { now.push_back(u); for (auto x : e[u]) { int v = x.first, w = x.second; if (v == fa || vis[v]) continue; val[v] = val[u] + a[v], dis[v] = dis[u] + (nowc != w); getdis(v, u, w); } } inline void count(int u) { vector<pair<int, int>> temp; dis[u] = 0, val[u] = 0; ans = (ans + a[u]) % mod; for (auto x : e[u]) { now.clear(); int v = x.first, w = x.second; if (vis[v]) continue; dis[v] = 0, val[v] = a[v]; getdis(v, u, w); for (int x : now) temp.push_back({w, x}); for (int x : now) if (dis[x] <= k) ans = (ans + val[x] + a[u]) % mod; for (int x : now) { if (dis[x] > k) continue; long long sum = tree[w].query(1, 0, n, 0, k - dis[x]) + 1ll * T[w].query(1, 0, n, 0, k - dis[x]) * val[x]; if (dis[x] < k) sum += tree[w ^ 1].query(1, 0, n, 0, k - dis[x] - 1) + 1ll * T[w ^ 1].query(1, 0, n, 0, k - dis[x] - 1) * val[x]; ans = (ans + sum) % mod; } for (int x : now) if (dis[x] <= k) tree[w].update(1, 0, n, dis[x], val[x] + a[u]), T[w].update(1, 0, n, dis[x], 1); } for (auto x : temp) { int w = x.first, v = x.second; if (dis[v] > k) continue; tree[w].update(1, 0, n, dis[v], -val[v] - a[u]); T[w].update(1, 0, n, dis[v], -1); } } inline void Divide(int u) { vis[u] = 1; count(u); for (auto x : e[u]) { int v = x.first; if (vis[v]) continue; maxv[rt = 0] = inf; sum = siz[v]; getrt(v, u); Divide(rt); } } inline void solve() { maxv[rt = 0] = inf; sum = n; getrt(1, 0); Divide(rt); printf( %lld n , ans); } int main() { int T = 1; while (T--) { init(); input(); solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, cnt = INT_MAX, c = 0; cin >> n >> k; string s, temp = ; cin >> s; int freq[26]; memset(freq, 0, sizeof(freq)); for (int i = 0; i < n; i++) freq[s[i] - A ]++; for (int i = 0; i < k; i++) { if (!freq[i]) return cout << 0 << endl, 0; cnt = min(cnt, freq[i]); } cout << cnt * k << endl; }
|
// bsg_nonsynth_clock_gen_plusarg
//
// This module is a basic non-synthesizable clock generator. This module is
// designed to be used with VCS and can be changed at runtime rather than
// compile time. To set the speed of the clock, add the following flag when
// executing the simulation binary:
//
// ./simv +clock-period=<period>
//
// If no flag is added to the simulation, the clock period will default to the
// value of default_clk_per_p.
//
`include "bsg_defines.v"
module bsg_nonsynth_clock_gen_plusarg #( parameter `BSG_INV_PARAM(default_clk_per_p) )
(
output logic o
);
`ifndef VERILATOR
// We start logic hi so the first pos-edge occurs at T=<clk_per>. The first
// negative edge will occur at T=<clk_per>/2.
logic clk_lo = 1'b1;
initial begin
// Here we grab the clock_period from the command line plusarg and generate
// the clock signal. If the plusarg doesn't exist, the value is unchanged
// and no error/warning is issued.
integer clock_period = default_clk_per_p;
$value$plusargs("clock-period=%d", clock_period);
$display("[INFO - %L]: Clock Period = %d", clock_period);
forever #(clock_period/2.0) clk_lo = ~clk_lo;
end
// Assign clock to output port
assign o = clk_lo;
`else
initial begin
$error("bsg_nonsynth_clock_gen_plusarg is not supported in Verilator due to delay statement (#)");
end
`endif
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_clock_gen_plusarg)
|
#include <bits/stdc++.h> const int MAXN = 100010, inf = 2147483233; using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, q, tot, nxt[MAXN << 1], to[MAXN << 1], fst[MAXN], cnt; int fa[MAXN], hsh[MAXN], dep[MAXN], f[MAXN][25], HSH[MAXN], size[MAXN]; int mx[MAXN << 2][2], mn[MAXN << 2][2], mx1, mx2, mn1, mn2; namespace hh { using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -f; for (; isdigit(ch); ch = getchar()) x = 10 * x + ch - 0 ; return x * f; } const int maxn = 500010; int n, m, lastans; int first[maxn], to[maxn << 1], nx[maxn << 1], cnt; inline void add(int u, int v) { to[++cnt] = v; nx[cnt] = first[u]; first[u] = cnt; } inline void ins(int u, int v) { add(u, v); add(v, u); } namespace LCA { int dep[maxn], bl[maxn], fa[maxn], size[maxn]; inline void dfs1(int x) { size[x] = 1; for (int i = first[x]; i; i = nx[i]) { if (to[i] == fa[x]) continue; fa[to[i]] = x; dep[to[i]] = dep[x] + 1; dfs1(to[i]); size[x] += size[to[i]]; } } inline void dfs2(int x, int col) { int k = 0; bl[x] = col; for (int i = first[x]; i; i = nx[i]) if (dep[to[i]] > dep[x] && size[to[i]] > size[k]) k = to[i]; if (!k) return; dfs2(k, col); for (int i = first[x]; i; i = nx[i]) if (dep[to[i]] > dep[x] && to[i] != k) dfs2(to[i], to[i]); } inline int lca(int x, int y) { while (bl[x] != bl[y]) { if (dep[bl[x]] < dep[bl[y]]) swap(x, y); x = fa[bl[x]]; } return dep[x] > dep[y] ? y : x; } } // namespace LCA namespace SEG { int root[maxn][2], ls[maxn << 4], rs[maxn << 4], val[maxn << 4], size; inline void Insert(int &x, int l, int r, int pos, int va) { if (!x) x = ++size; val[x] += va; if (l == r) return; int mid = (l + r) >> 1; if (pos <= mid) Insert(ls[x], l, mid, pos, va); else Insert(rs[x], mid + 1, r, pos, va); } inline int query(int x, int l, int r, int L, int R) { if (!x) return 0; if (L <= l && r <= R) return val[x]; int mid = (l + r) >> 1, ans = 0; if (L <= mid) ans += query(ls[x], l, mid, L, R); if (R > mid) ans += query(rs[x], mid + 1, r, L, R); return ans; } } // namespace SEG inline int q_dis(int x, int y) { return LCA::dep[x] + LCA::dep[y] - (LCA::dep[LCA::lca(x, y)] << 1); } int size[maxn], f[maxn], vis[maxn], d[maxn], v[maxn], son, root; int nfa[maxn]; inline void solve(int rt, int type, int x, int fa) { SEG::Insert(SEG::root[rt][type], 0, n, d[x], v[x]); for (int i = first[x]; i; i = nx[i]) { if (to[i] == fa || vis[to[i]]) continue; d[to[i]] = d[x] + 1; solve(rt, type, to[i], x); } } inline void getroot(int x, int fa) { size[x] = 1, f[x] = 0; for (int i = first[x]; i; i = nx[i]) { if (to[i] == fa || vis[to[i]]) continue; getroot(to[i], x); size[x] += size[to[i]]; f[x] = max(f[x], size[to[i]]); } f[x] = max(f[x], son - size[x]); if (f[x] < f[root]) root = x; } inline void work(int x) { vis[x] = 1; d[x] = 0; solve(x, 0, x, 0); for (int i = first[x]; i; i = nx[i]) { if (vis[to[i]]) continue; son = size[to[i]]; root = 0; d[to[i]] = 1; getroot(to[i], 0); solve(root, 1, to[i], x); nfa[root] = x; work(root); } } inline int query(int x, int k) { int ret = SEG::query(SEG::root[x][0], 0, n, 0, k); for (int i = x; nfa[i]; i = nfa[i]) { int du = q_dis(x, nfa[i]); ret += SEG::query(SEG::root[nfa[i]][0], 0, n, 0, k - du); ret -= SEG::query(SEG::root[i][1], 0, n, 0, k - du); } return ret; } inline void update(int x, int k) { int delt = k - SEG::query(SEG::root[x][0], 0, n, 0, 0); SEG::Insert(SEG::root[x][0], 0, n, 0, delt); for (int i = x; nfa[i]; i = nfa[i]) { int du = q_dis(x, nfa[i]); SEG::Insert(SEG::root[nfa[i]][0], 0, n, du, delt); SEG::Insert(SEG::root[i][1], 0, n, du, delt); } } int main() { n = read(), m = read(); for (int i = 1; i <= n; i++) v[i] = read(); for (int i = 2; i <= n; i++) { int u = read(), v = read(); ins(u, v); } LCA::dfs1(1); LCA::dfs2(1, 1); f[0] = son = n; getroot(1, 0); work(root); while (m--) { int opt = read(), x = read() ^ lastans, y = read() ^ lastans; if (opt) update(x, y); else printf( %d n , lastans = query(x, y)); } } } // namespace hh void dfs(int x) { hsh[x] = ++tot, HSH[tot] = x; dep[x] = dep[f[x][0]] + 1; for (int i = 1; i <= 23; i++) f[x][i] = f[f[x][i - 1]][i - 1]; for (int i = fst[x]; i; i = nxt[i]) dfs(to[i]); } int lca(int u, int v) { if (dep[u] < dep[v]) swap(u, v); int t = dep[u] - dep[v]; for (int i = 23; i >= 0; i--) if ((1 << i) & t) u = f[u][i]; if (u == v) return u; for (int i = 23; i >= 0; i--) if (f[u][i] != f[v][i]) u = f[u][i], v = f[v][i]; return f[u][0]; } void pushup(int x) { mx[x][0] = max(mx[(x << 1)][0], mx[((x << 1) | 1)][0]); mx[x][1] = max(min(mx[(x << 1)][0], mx[((x << 1) | 1)][0]), max(mx[(x << 1)][1], mx[((x << 1) | 1)][1])); mn[x][0] = min(mn[(x << 1)][0], mn[((x << 1) | 1)][0]); mn[x][1] = min(max(mn[(x << 1)][0], mn[((x << 1) | 1)][0]), min(mn[(x << 1)][1], mn[((x << 1) | 1)][1])); } void build(int x, int l, int r) { if (l == r) { mx[x][1] = 0; mn[x][1] = inf; mx[x][0] = mn[x][0] = hsh[l]; return; } int mid = l + r >> 1; build((x << 1), l, mid); build(((x << 1) | 1), mid + 1, r); pushup(x); } void query(int x, int l, int r, int a, int b) { if (a <= l && r <= b) { if (mx[x][0] > mx1) mx2 = mx1, mx1 = mx[x][0]; else if (mx[x][0] > mx2) mx2 = mx[x][0]; if (mx[x][1] > mx2) mx2 = mx[x][1]; if (mn[x][0] < mn1) mn2 = mn1, mn1 = mn[x][0]; else if (mn[x][0] < mn2) mn2 = mn[x][0]; if (mn[x][1] < mn2) mn2 = mn[x][1]; return; } int mid = l + r >> 1; if (a <= mid) query((x << 1), l, mid, a, b); if (b > mid) query(((x << 1) | 1), mid + 1, r, a, b); } void init() { cin >> n >> q; for (int i = 2; i <= n; i++) { f[i][0] = read(); to[++cnt] = i, nxt[cnt] = fst[f[i][0]], fst[f[i][0]] = cnt; } } void work() { dfs(1); build(1, 1, n); } int a, b; void gogo() { mx1 = mx2 = 0; mn1 = mn2 = inf; query(1, 1, n, a, b); } void print() { while (q--) { int l1, l2; cin >> a >> b; gogo(); l1 = lca(HSH[mx1], HSH[mn2]); l2 = lca(HSH[mx2], HSH[mn1]); if (dep[l1] > dep[l2]) printf( %d %d n , HSH[mn1], dep[l1] - 1); else printf( %d %d n , HSH[mx1], dep[l2] - 1); } } int main() { init(); work(); print(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:19 05/27/2016
// Design Name:
// Module Name: prueba_lectura_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prueba_lectura_rtc_2
(
input wire clk, reset,
input wire sw,
inout [7:0]dato,
output wire AD, CS, WR, RD,
output [7:0] RGB,
output hsync, vsync
);
//Conexiones internas
reg [7:0]in_port;
wire [7:0]out_port;
wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
// conexiones banco de registros a VGA
wire [7:0]out_seg_hora,out_min_hora,out_hora_hora;
wire [7:0]out_dia_fecha,out_mes_fecha,out_jahr_fecha;
wire [7:0]out_seg_timer,out_min_timer,out_hora_timer;
///////////////////////////// hold's
wire hold_seg_hora;
wire hold_min_hora;
wire hold_hora_hora;
wire hold_dia_fecha;
wire hold_mes_fecha;
wire hold_jahr_fecha;
wire hold_dia_semana;
wire hold_seg_timer;
wire hold_min_timer;
wire hold_hora_timer;
// wire hold_banderas_config;
//////////////////////
//Conexiones de controlador RTC
wire fin_lectura_escritura;
wire [7:0] out_dato;
assign interrupt = 1'b0;
wire wire_sw;
assign wire_sw = {7'b0,sw};
microcontrolador instancia_microcontrolador
(
.clk(clk),
.reset(reset),
.interrupt(interrupt),
.in_port(in_port),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt_ack(),
.port_id(port_id),
.out_port(out_port)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clk),
.reset(reset),
.digit0_HH(out_hora_hora[3:0]), .digit1_HH(out_hora_hora[7:4]), .digit0_MM(out_min_hora[3:0]), .digit1_MM(out_min_hora[7:4]), .digit0_SS(out_seg_hora[3:0]), .digit1_SS(out_seg_hora[7:4]),//
.digit0_DAY(out_dia_fecha[3:0]), .digit1_DAY(out_dia_fecha[7:4]), .digit0_MES(out_mes_fecha[3:0]), .digit1_MES(out_mes_fecha[7:4]), .digit0_YEAR(out_jahr_fecha[3:0]), .digit1_YEAR(out_jahr_fecha[7:4]),//
.digit0_HH_T(out_hora_timer[3:0]), .digit1_HH_T(out_hora_timer[7:4]), .digit0_MM_T(out_min_timer[3:0]), .digit1_MM_T(out_min_timer[7:4]), .digit0_SS_T(out_seg_timer[3:0]), .digit1_SS_T(out_seg_timer[7:4]),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(1'b0),
.config_mode(2'b0),
.cursor_location(2'b0),
.formato_hora(1'b1),
.estado_alarma(1'b0),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
memoria_registros_VGA instancia_memoria_registros_VGA
(
.clk(clk),
.reset(reset),
.cs_seg_hora(1'b0),
.cs_min_hora(1'b0),
.cs_hora_hora(1'b0),
.cs_dia_fecha(1'b0),
.cs_mes_fecha(1'b0),
.cs_jahr_fecha(1'b0),
.cs_seg_timer(1'b0),
.cs_min_timer(1'b0),
.cs_hora_timer(1'b0),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer),
.hold_banderas_config(1'b1),
.data_PicoBlaze(out_port),
.count_seg_hora(8'b0),
.count_min_hora(8'b0),
.count_hora_hora(8'b0),
.count_dia_fecha(8'b0),
.count_mes_fecha(8'b0),
.count_jahr_fecha(8'b0),
.count_seg_timer(8'b0),
.count_min_timer(8'b0),
.count_hora_timer(8'b0),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.out_banderas_config()
);
deco_hold_registros instancia_deco_hold_registros (
.write_strobe(write_strobe),
.port_id(port_id),
.hold_seg_hora(hold_seg_hora),
.hold_min_hora(hold_min_hora),
.hold_hora_hora(hold_hora_hora),
.hold_dia_fecha(hold_dia_fecha),
.hold_mes_fecha(hold_mes_fecha),
.hold_jahr_fecha(hold_jahr_fecha),
.hold_seg_timer(hold_seg_timer),
.hold_min_timer(hold_min_timer),
.hold_hora_timer(hold_hora_timer)
);
escritor_lector_rtc_2 instancia_escritor_lector_rtc_2 (
.clk(clk),
.reset(reset),
.in_dato(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.reg_a_d(AD),
.reg_cs(CS),
.reg_rd(RD),
.reg_wr(WR),
.out_dato(out_dato),
.flag_done(fin_lectura_escritura),
.dato(dato)
);
//Decodificación del puerto de entrada del microcontrolador
always@(posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= out_dato;
8'h02 : in_port <= wire_sw;
default : in_port <= 8'bXXXXXXXX;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_1_V
`define SKY130_FD_SC_MS__A222O_1_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_1 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_1_V
|
#include <bits/stdc++.h> using namespace std; vector<int> g[300005]; int cnt[300005]; int vis[300005]; int ans[300001][26]; int res = 0; int main() { queue<int> q; int n, m; cin >> n >> m; string s; cin >> s; int x, y; while (m--) { scanf( %d%d , &x, &y); x--, y--; g[x].push_back(y); cnt[y]++; } for (int i = 0; i < s.size(); i++) { ans[i][s[i] - a ]++; if (!cnt[i]) q.push(i); } while (!q.empty()) { int i = q.front(); q.pop(); for (auto v : g[i]) { cnt[v]--; for (int j = 0; j < 26; j++) { ans[v][j] = max(ans[v][j], ans[i][j] + (s[v] == j + a )); res = max(res, ans[v][j]); } if (!cnt[v]) q.push(v); } } if (*max_element(cnt, cnt + s.size())) return cout << -1, 0; cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int gr[1005][1005], n, m, a[1005], x, y; long long g[1005]; bool vis[1005]; int main() { scanf( %d , &n), scanf( %d , &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } int mi = 100000100, l1 = 0; int ans = 0; for (int i = 0; i < m; i++) { scanf( %d , &x), scanf( %d , &y); ans += min(a[x], a[y]); } cout << ans << endl; return 0; }
|
/*
File: fifo_mem.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module fifo_mem (/*AUTOARG*/
// Outputs
rd_data,
// Inputs
wr_clk, wr_write, wr_data, wr_addr, rd_addr
);
parameter DW = 104;
parameter AW = 2;
localparam MD = 1<<AW;
//#########
//# INPUTS
//#########
input wr_clk; //write clock
input wr_write;
input [DW-1:0] wr_data;
input [AW-1:0] wr_addr;
input [AW-1:0] rd_addr;
//##########
//# OUTPUTS
//##########
output [DW-1:0] rd_data;
//########
//# REGS
//########
reg [DW-1:0] mem[MD-1:0];
//Write
always @(posedge wr_clk)
if(wr_write)
mem[wr_addr[AW-1:0]] <= wr_data[DW-1:0];
//Read
assign rd_data[DW-1:0] = mem[rd_addr[AW-1:0]];
endmodule // fifo_mem
|
#include <bits/stdc++.h> using namespace std; const int MAX = 205; const int INF = 0x3f3f3f3f; string a, b; int dp[MAX][MAX][405]; int call(int x, int y, int s) { if (x >= a.size() and y >= b.size()) return s; if (dp[x][y][s] != -1) return dp[x][y][s]; int ret = INF; if (x < a.size() and y < b.size() and a[x] == b[y]) { if (a[x] == ( ) { ret = min(ret, 1 + call(x + 1, y + 1, s + 1)); } else { if (s) { ret = min(ret, 1 + call(x + 1, y + 1, s - 1)); } else { ret = min(ret, 2 + call(x + 1, y + 1, s)); } } } else { if (x < a.size()) { if (a[x] == ( ) { ret = min(ret, 1 + call(x + 1, y, s + 1)); } else { if (s) { ret = min(ret, 1 + call(x + 1, y, s - 1)); } else { ret = min(ret, 2 + call(x + 1, y, s)); } } } if (y < b.size()) { if (b[y] == ( ) { ret = min(ret, 1 + call(x, y + 1, s + 1)); } else { if (s) { ret = min(ret, 1 + call(x, y + 1, s - 1)); } else { ret = min(ret, 2 + call(x, y + 1, s)); } } } } return dp[x][y][s] = ret; } void go(int x, int y, int s) { if (x >= a.size() and y >= b.size()) { for (int i = 0; i < s; i++) cout << ) ; cout << endl; return; } int ret = call(x, y, s); if (x < a.size() and y < b.size() and a[x] == b[y]) { if (a[x] == ( ) { if (ret == 1 + call(x + 1, y + 1, s + 1)) { cout << ( ; go(x + 1, y + 1, s + 1); return; } } else { if (s) { if (ret == 1 + call(x + 1, y + 1, s - 1)) { cout << ) ; go(x + 1, y + 1, s - 1); return; } } else { if (ret == 2 + call(x + 1, y + 1, s)) { cout << () ; go(x + 1, y + 1, s); return; } } } } else { if (x < a.size()) { if (a[x] == ( ) { if (ret == 1 + call(x + 1, y, s + 1)) { cout << ( ; go(x + 1, y, s + 1); return; } } else { if (s) { if (ret == 1 + call(x + 1, y, s - 1)) { cout << ) ; go(x + 1, y, s - 1); return; } } else { if (ret == 2 + call(x + 1, y, s)) { cout << () ; go(x + 1, y, s); return; } } } } if (y < b.size()) { if (b[y] == ( ) { if (ret == 1 + call(x, y + 1, s + 1)) { cout << ( ; go(x, y + 1, s + 1); return; } } else { if (s) { if (ret == 1 + call(x, y + 1, s - 1)) { cout << ) ; go(x, y + 1, s - 1); return; } } else { if (ret == 2 + call(x, y + 1, s)) { cout << () ; go(x, y + 1, s); return; } } } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> a >> b; memset(dp, -1, sizeof(dp)); go(0, 0, 0); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int M = 1e6 + 10; const long long INF = 0x3f3f3f3f3f3f3f; const int inf = 0x3f3f3f; const double esp = 1e-6; long long read() { long long x = 0; long long k = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) k = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + (c - 0 ); c = getchar(); } return x * k; } int n; int a[N]; int main() { int t; cin >> t; while (t--) { int a, b; cin >> a >> b; if (a == 1) { if (b <= 1) { cout << YES << endl; } else cout << NO << endl; } else if (a == 2) { if (b <= 3) { cout << YES << endl; } else cout << NO << endl; } else if (a == 3) { if (b <= 3) { cout << YES << endl; } else cout << NO << endl; } else cout << YES << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, i, j, r = 1; cin >> n; int a[n][n]; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (i % 2 == 0) { a[i][j] = r; r++; } else { a[i][n - j - 1] = r; r++; } } } for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { cout << a[j][i] << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = n / 2, y = (n / 2) + 1, prime1 = 0, prime2 = 0; if (n % 2 == 0) { x = (n / 2); y = n / 2; } for (int i = 1; i <= n; i++) { for (int j = 2; j < x; j++) { if (x % j == 0) { prime1++; break; } else if (j == x - 1) { prime1 = 0; break; } } for (int j = 2; j < y; j++) { if (y % j == 0) { prime2++; break; } else if (j == y - 1) { prime1 = 0; prime2 = 0; } } if (prime1 >= 1 && prime2 >= 1) break; else { x--; y++; } } cout << x << << y; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_1_V
`define SKY130_FD_SC_LP__A311O_1_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_1_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using vi = vector<int>; const int N = 3e5 + 3; const int mod = 1e9 + 7; int n; ll a[N]; template <class T> struct FT { vector<T> tree; int sz; FT(int n) { sz = n, tree.resize(n + 1); } T get(int i) { if (i <= 0 || i > sz) return T(0); T sum = T(0); for (; i; i -= (i & -i)) sum += tree[i]; return sum; } void upd(int i, T val) { for (; i <= sz; i += (i & -i)) tree[i] += val; } void init(T *arr, int n) { sz = n; for (int i = 1; i <= n; i++) upd(i, arr[i - 1]); } }; ll ans[N]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } FT<ll> tree1(N); FT<ll> tree2(N); ll sum = 0; for (int i = 0; i < n; i++) { ans[i] = 1ll * i * a[i] + sum; ans[i] -= tree1.get(a[i]); sum += a[i]; int mul = a[i]; while (mul < N) { tree1.upd(mul, 1ll * a[i]); mul += a[i]; } mul = (300000 / a[i]) * a[i]; ll cnt = 0; while (mul != 0) { ll cur = i - tree2.get(mul - 1); ll how_many = cur - cnt; ans[i] -= 1ll * mul * how_many; cnt = cur; mul -= a[i]; } tree2.upd(a[i], 1ll); } for (int i = 0; i < n; i++) { printf( %lld , ans[i]); ans[i + 1] += ans[i]; } return 0; }
|
`timescale 1 ns / 100 ps
module bench
(
);
reg clk;
reg rst;
// ORLINK interface
reg ifclk_in;
reg fifoData_wr;
reg [7:0] fifoData_out;
wire [7:0] fifoData_io;
reg gotData_in;
reg gotRoom_in;
output sloe_out;
output slrd_out;
output slwr_out;
output [1:0] fifoAddr_out;
output pktEnd_out;
wire [7:0] led;
assign fifoData_io = fifoData_wr ? fifoData_out : 8'bz;
orlink dut
(
.wb_rst(rst),
.wb_clk(clk),
.ifclk_in(ifclk_in),
.fifoData_io(fifoData_io),
.gotData_in(gotData_in),
.gotRoom_in(gotRoom_in),
.sloe_out(sloe_out),
.slrd_out(slrd_out),
.slwr_out(slwr_out),
.fifoAddr_out(fifoAddr_out),
.pktEnd_out(pktEnd_out)
);
initial
begin
gotData_in = 0;
gotRoom_in = 0;
fifoData_wr = 0;
fifoData_out = 8'b0;
end
// write single byte
task com_write;
input [7:0] address;
input [7:0] data;
integer i;
begin
wait(slrd_out==0);
@(posedge ifclk_in); #1;
fifoData_wr = 1;
fifoData_out = address & 8'b01111111;
gotData_in = 1;
@(posedge ifclk_in); #1;
fifoData_out = 0;
@(posedge ifclk_in); #1;
fifoData_out = 0;
@(posedge ifclk_in); #1;
fifoData_out = 0;
@(posedge ifclk_in); #1;
fifoData_out = 1;
@(posedge ifclk_in); #1;
fifoData_out = data;
wait(slrd_out==0);
@(posedge ifclk_in); #1;
gotData_in = 0;
fifoData_wr = 0;
fifoData_out = 0;
end
endtask
task com_write_file;
input [7:0] address;
input [31:0] count;
reg [7:0] data[0:10];
integer i;
begin
$readmemh("writedata.txt", data);
wait(slrd_out==0);
@(posedge ifclk_in); #1;
fifoData_wr = 1;
fifoData_out = address & 8'b01111111;
gotData_in = 1;
@(posedge ifclk_in); #1;
fifoData_out = count[31:24];
@(posedge ifclk_in); #1;
fifoData_out = count[23:16];
@(posedge ifclk_in); #1;
fifoData_out = count[15:8];
@(posedge ifclk_in); #1;
fifoData_out = count[7:0];
@(posedge ifclk_in); #1;
i=0;
while (i<count) begin
fifoData_out = data[i];
@(posedge ifclk_in);
if (slrd_out==0)
i=i+1;
#1;
end
gotData_in = 0;
fifoData_wr = 0;
fifoData_out = 0;
@(posedge ifclk_in); #1;
end
endtask
task com_read;
input [7:0] address;
input [31:0] count;
integer i;
begin
@(posedge ifclk_in); #1;
fifoData_wr = 1;
fifoData_out = address | 8'b10000000;
gotData_in = 1;
@(posedge ifclk_in); #1;
fifoData_out = count[31:24];
@(posedge ifclk_in); #1;
fifoData_out = count[23:16];
@(posedge ifclk_in); #1;
fifoData_out = count[15:8];
@(posedge ifclk_in); #1;
fifoData_out = count[7:0];
@(posedge ifclk_in); #1;
fifoData_wr = 0;
gotData_in = 0;
gotRoom_in = 1;
i=0;
while (i<count) begin
@(posedge ifclk_in);
if (slwr_out==0) begin
$display("%h", fifoData_io);
i=i+1;
end
#1;
end
gotRoom_in = 0;
gotData_in = 0;
fifoData_wr = 0;
fifoData_out = 0;
@(posedge ifclk_in); #1;
end
endtask
// -- Clock Gen --
always
#20 clk = ~clk;
always
#10 ifclk_in = ~ifclk_in;
// -- Timeout --
initial
begin
# $display("Timeout!");
$finish;
end
/* reg [7:0] test_data [256];
test_data = {{8'b0, 8'b1}};*/
/* wire [31:0] mem_extract0 = dut.xilinx_ddr2_0.ram_wb_b3_0.mem[0];
wire [31:0] mem_extract1 = dut.xilinx_ddr2_0.ram_wb_b3_0.mem[1];
*/
// -- Simulation Program --
initial
begin
// -- Setup --
$display("-- Simulation --");
$dumpfile("output.vcd");
$dumpvars;
ifclk_in = 0;
clk = 0;
rst = 0;
#40 rst = 1;
#40 rst = 0;
#40;
// -- Program --
com_write(8'h00, 8'h13);
com_read(8'h00, 1);
/* com_write(8'h01, 8'h00);
com_write(8'h02, 8'h00);
com_write(8'h03, 8'h00);
com_write(8'h04, 8'h00);
com_write_file(8'h05, 10);
com_write(8'h01, 8'h00);
com_write(8'h02, 8'h00);
com_write(8'h03, 8'h00);
com_write(8'h04, 8'h00);
com_read(8'h06, 10);*/
#40;
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, j; while (~scanf( %d%d , &n, &k)) { if (n <= 2 * k) { printf( -1 n ); continue; } else { printf( %d n , n * k); for (i = 1; i <= n; i++) { for (j = 1; j <= k; j++) { if (i == n) printf( %d %d n , i, j); else if (i + j > n) printf( %d %d n , i, i + j - n); else printf( %d %d n , i, i + j); } } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 2e5 + 5; const long long MOD = 1e9 + 7; const long long INF = 1e18; mt19937 rnd(time(0)); signed main() { long long q; cin >> q; while (q--) { long long d, mod; cin >> d >> mod; long long c = 1; long long lg = 0; while ((1ll << lg) <= d) { c = (c * (min(d, (1ll << (lg + 1)) - 1) - (1ll << lg) + 2ll)) % mod; lg++; } c--; if (c < 0) { c += mod; } cout << c << n ; } return 0; }
|
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* *
* Altera products are protected under numerous U.S. and foreign patents, *
* maskwork rights, copyrights and other intellectual property laws. *
* *
* This reference design file, and your use thereof, is subject to and *
* governed by the terms and conditions of the applicable Altera Reference *
* Design License Agreement (either as signed by you, agreed by you upon *
* download or as a "click-through" agreement upon installation andor found *
* at www.altera.com). By using this reference design file, you indicate your *
* acceptance of such terms and conditions between you and Altera Corporation. *
* In the event that you do not agree with such terms and conditions, you may *
* not use the reference design file and please promptly destroy any copies *
* you have made. *
* *
* This reference design file is being provided on an "as-is" basis and as an *
* accommodation and therefore all warranties, representations or guarantees *
* of any kind (whether express, implied or statutory) including, without *
* limitation, warranties of merchantability, non-infringement, or fitness for *
* a particular purpose, are specifically disclaimed. By making this refer- *
* ence design file available, Altera expressly does not recommend, suggest *
* or require that this reference design file be used in combination with any *
* other product not provided by Altera. *
* *
* Module Name: erase_ram File Name: erase_ram.v *
* *
* Module Function: This module implements the SP RAM for storing keys the *
* basic CAM section. When storing a key location, the key *
* is written into the Erase RAM so that it can be erased *
* at a later time. *
* *
* Modules Used: *
* altsyncram Stratix IV Memory ATOM *
* *
* Parameters and Defines Used: *
* FAMILY Cyclone III/IV, or Stratix III/IV *
* S_KEY Section KEY *
* ENTRIES Total Entries in CAM *
* INDEX log 2 (ENTRIES) *
* CEIL_ENTRY 2**INDEX *
* *
* Created by: Jim Schwalbe Created on: 10/05/2009 *
* *
* REVISION HISTORY: *
* * Revision 1.0 10/05/2009 Jim Schwalbe *
* - Initial Revision *
* *
******************************************************************************/
module erase_ram (
address,
clock,
data,
wren,
q
);
// Target FPGA Family
parameter FAMILY = "Stratix IV";
// Section KEY
parameter S_KEY = 8; // Default (8)
// CAM ENTRIES
parameter ENTRIES = 416;
localparam INDEX = log2(ENTRIES); // Default (9)
localparam CEIL_ENTRY = 2**INDEX; // Default (512)
input [INDEX-1:0] address;
input clock;
input [S_KEY-1:0] data;
input wren;
output [S_KEY-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [S_KEY-1:0] sub_wire0;
wire [S_KEY-1:0] q = sub_wire0;
altsyncram altsyncram_component (
.wren_a ( wren ),
.clock0 ( clock ),
.address_a ( address ),
.data_a ( data ),
.q_a ( sub_wire0 ),
.aclr0 ( 1'b0 ),
.aclr1 ( 1'b0 ),
.address_b ( 1'b1 ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_a ( 1'b1 ),
.byteena_b ( 1'b1 ),
.clock1 ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.data_b ( 1'b1 ),
.eccstatus ( ),
.q_b ( ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ),
.wren_b ( 1'b0 )
);
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "erase_ram.rif"
`else
altsyncram_component.init_file = "erase_ram.hex"
`endif
,
altsyncram_component.intended_device_family = FAMILY,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = CEIL_ENTRY,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = INDEX,
altsyncram_component.width_a = S_KEY,
altsyncram_component.width_byteena_a = 1;
function integer log2;
input [32:0] bits;
integer k;
begin
log2 = 1;
for (k=0; 2**k < bits; k=k+1)
log2 = k + 1;
end
endfunction // log2
endmodule // erase_ram
|
#include <bits/stdc++.h> using namespace std; int main() { long long k, m = 9, x; long long r = 1, n, j, d = 0; cin >> k; while (k - m * r > 0) { k -= m * r; ++r; m = m * 10; } n = (k - 1) / r; j = (k - 1) % r; x = pow(10, r - 1) + n; for (long i = 0; i < r - j - 1; ++i) x /= 10; d = x % 10; cout << d << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class X> void temfunc(const X a) { for (auto it = a.begin(); it != a.end(); it++) cout << *it << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; int t, l, r; cin >> t; while (t--) { cin >> l >> r; if (l == r) cout << 0 << n ; else { int temp; if (r & 1) { int temp = r / 2; if (temp >= l) cout << temp << n ; else { cout << r % l << n ; } } else { temp = r / 2; if (temp >= l) cout << temp - 1 << n ; else cout << r % l << n ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, a[301][301], dp[301][301][301]; int solve(int i, int j, int k) { if (i == n && j == n && k == 0) return a[n][n]; int x = i + k, y = j - k; if (x < 1 || y < 1 || x > n || y > n || i < 1 || j < 1 || i > n || j > n || k < 0) return -1e9; if (dp[i][j][k] != -2.1e9) return dp[i][j][k]; return dp[i][j][k] = a[i][j] + (k != 0) * a[x][y] + max(max(solve(i + 1, j, k), solve(i + 1, j, k - 1)), max(solve(i, j + 1, k + 1), solve(i, j + 1, k))); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) cin >> a[i][j]; for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) for (int k = 0; k <= n; ++k) dp[i][j][k] = -2.1e9; cout << solve(1, 1, 0); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long x1, y1, z1; long long x2, y2, z2; cin >> x1 >> y1 >> z1; cin >> x2 >> y2 >> z2; long long sum = 0; if (z2 > x1) { z2 -= x1; if (z2 > z1) { z2 -= z1; sum -= (2 * z2); } else { z1 -= z2; sum += 2 * min(z1, y2); } } else { sum += 2 * min(z1, y2); } cout << sum << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:04:06 03/25/2011
// Design Name:
// Module Name: debounce
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Debounce Pushbutton: Filters out mechanical switch bounce for around 40Ms
module debounce(pb_debounced, pb, clk);
//push_button_debounced, push_button, clock
output pb_debounced; // signal of push button after debounced
input pb; // signal from push button of the FPGA board
input clk; // 100hz clock
reg [3:0] shift_reg; // use shift_reg to filter push button bounce
//when positive edge clock, shift the signal of pb to shift_reg[0]
always @(posedge clk) begin
shift_reg[3:1] <= shift_reg[2:0];
shift_reg[0] <= pb;
end
//if pb remain 0 at 4 positive edge clock, then pb_debounced = 0
assign pb_debounced = ((shift_reg == 4'b0000) ? 1'b0 : 1'b1);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_SUM_IN_SQUARED.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module FIFO_SUM_IN_SQUARED (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [25:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [25:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL "data[25..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL "q[25..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_SUM_IN_SQUARED_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_sample_multi_next_buckets_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_sample_multi_next_buckets(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
nfa_accept_sample_multi_next_buckets_ram nfa_accept_sample_multi_next_buckets_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
////
reg [255:0] state = 0;
reg [127:0] data = 0;
reg [31:0] nonce = 32'h0;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLK_IN1(CLK_100MHZ), .CLK_OUT1(hash_clk));
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Hashers
wire [255:0] hash, hash2;
sha256_transform #(.NUM_ROUNDS(64)) uut (
.clk(hash_clk),
.rx_state(state),
.rx_input({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, data}),
.tx_hash(hash)
);
sha256_transform #(.NUM_ROUNDS(61)) uut2 (
.clk(hash_clk),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg old_is_golden_ticket = 1'b0;
reg [31:0] golden_nonce = 0;
`ifndef SIM
comm comm_test_blk (
.hash_clk (hash_clk),
.rx_new_nonce (old_is_golden_ticket),
.rx_golden_nonce (golden_nonce),
.tx_midstate(comm_midstate),
.tx_data(comm_data)
);
`endif
//// Control Unit
reg is_golden_ticket = 1'b0;
wire [31:0] nonce_next;
assign nonce_next = nonce + 32'd1;
//assign hash2[159:128] = state[31:0] ^ state[63:32] ^ state[95:64] ^ state[127:96] ^ state[159:128] ^ state[191:160] ^ state[223:192] ^ state[255:224] ^ data[31:0] ^ data[63:32] ^ data[95:64] ^ data[127:96];
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
//midstate_buf <= midstate_vw;
//data_buf <= data2_vw;
`endif
// Give new data to the hasher
state <= comm_midstate;
data <= {nonce_next, comm_data[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[159:128] + 32'h5be0cd19 == 32'h00000000);
old_is_golden_ticket <= is_golden_ticket;
if(is_golden_ticket)
golden_nonce <= nonce - 32'd130;
end
endmodule
|
//#####################################################################
//# This module converts the packet interface to a 64bit wide format
//# suitable for sending out to a parallel to serial shift register.
//# The frame signal is sent along together with the data making.
//# The goal is to minimize the amount of logic done on the high speed
//# domain.
//#####################################################################
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, etx_wait, tx_burst, tx_access,
tx_data_slow, tx_frame_slow,
// Inputs
nreset, clk, etx_access, etx_packet, tx_enable, burst_enable,
gpio_data, gpio_enable, ctrlmode_bypass, ctrlmode, tx_rd_wait,
tx_wr_wait
);
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h000;
//Clock/reset
input nreset;
input clk;
//System side
input etx_access;
input [PW-1:0] etx_packet;
//Pushback signals
output etx_rd_wait;
output etx_wr_wait;
output etx_wait;
//Config interface
input tx_enable; //transmit enable
input burst_enable; //Enables bursting
input [8:0] gpio_data; //TODO
input gpio_enable; //TODO
output tx_burst; //for TXSTATUS
output tx_access; //for TXMON
//ctrlmode for rd/wr transactions
input ctrlmode_bypass;
input [3:0] ctrlmode;
//Interface to IO
output [63:0] tx_data_slow;
output [3:0] tx_frame_slow;
input tx_rd_wait;
input tx_wr_wait;
//################################################################
//# Local regs & wires
//################################################################
reg [2:0] tx_state;
reg [PW-1:0] tx_packet;
reg tx_burst_reg;
wire [1:0] etx_datamode;
wire [4:0] etx_ctrlmode;
wire [AW-1:0] etx_dstaddr;
wire [DW-1:0] etx_data;
wire [1:0] tx_datamode;
wire [4:0] tx_ctrlmode;
wire [AW-1:0] tx_dstaddr;
wire [DW-1:0] tx_data;
wire [AW-1:0] tx_srcaddr;
wire [3:0] ctrlmode_mux;
//##############################################################
//# Packet Pipeline
//##############################################################
packet2emesh #(.AW(AW))
p2m0 (
.write_in (etx_write),
.datamode_in (etx_datamode[1:0]),
.ctrlmode_in (etx_ctrlmode[4:0]),
.dstaddr_in (etx_dstaddr[31:0]),
.data_in (),
.srcaddr_in (),
.packet_in (etx_packet[PW-1:0]));//input
//ctrlmode bypass
assign ctrlmode_mux[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
etx_ctrlmode[3:0];
//Hold transaction while waiting
always @ (posedge clk)
if(~etx_wait)
tx_packet[PW-1:0] <= {etx_packet[PW-1:8],
1'b0,
ctrlmode_mux[3:0],
etx_packet[2:0]};
//the IO pipeline flushes out
packet2emesh #(.AW(AW))
p2m1 (
.write_in (tx_write),
.datamode_in (tx_datamode[1:0]),
.ctrlmode_in (tx_ctrlmode[4:0]),
.dstaddr_in (tx_dstaddr[31:0]),
.data_in (tx_data[31:0]),
.srcaddr_in (tx_srcaddr[31:0]),
.packet_in (tx_packet[PW-1:0]));//input
//#############################
//# Burst Detection
//#############################
assign burst_addr_match = ((tx_dstaddr[31:0]+32'h8) == etx_dstaddr[31:0]);
assign current_match = tx_access &
tx_write &
(tx_datamode[1:0]==2'b11) &
(tx_ctrlmode[3:0]==4'b0000);
assign next_match = etx_access & //BUG: should be valid?
etx_write &
(etx_datamode[1:0]==2'b11) &
(etx_ctrlmode[3:0]==4'b0000);
assign tx_burst = burst_enable &
~tx_wait &
current_match &
next_match &
burst_addr_match;
always @ (posedge clk)
tx_burst_reg <=tx_burst;
//############################################################
//# TRANSMIT STATE MACHINE
//#############################################################
assign etx_valid = tx_enable &
etx_access &
~tx_wait;
`define TX_IDLE 3'b000
`define TX_START 3'b001
`define TX_ACK 3'b010
`define TX_BURST 3'b011
`define TX_WAIT 3'b100
always @ (posedge clk)
if(!nreset)
tx_state[2:0] <= `TX_IDLE;
else
case (tx_state[2:0])
`TX_IDLE: tx_state[2:0] <= etx_valid ? `TX_START :
`TX_IDLE;
`TX_START: tx_state[2:0] <= `TX_ACK;
`TX_ACK: tx_state[2:0] <= tx_burst ? `TX_BURST :
etx_valid ? `TX_START :
`TX_IDLE;
`TX_BURST: tx_state[2:0] <= tx_burst ? `TX_BURST :
`TX_IDLE;
endcase // case (tx_state[2:0])
assign tx_ack_wait = (tx_state[2:0]==`TX_START);
assign tx_access = (tx_state[2:0]==`TX_START) |
(tx_state[2:0]==`TX_BURST);
//#######################################
//# Wait propagation circuit backwards
//########################################
wire [63:0] tx_cycle1;
wire [63:0] tx_cycle2;
assign tx_frame_slow[3:0] = (tx_state[1:0]==`TX_START) ? 4'b0111 :
(tx_state[1:0]!=`TX_IDLE) ? 4'b1111 :
4'b0000;
assign tx_cycle1[63:0] = {tx_dstaddr[11:0],tx_datamode[1:0],tx_write,tx_access, //47:32
tx_dstaddr[27:12], //31:16
~tx_write,5'b0,tx_burst_reg,1'b0, //8-15
tx_ctrlmode[3:0],tx_dstaddr[31:28], //0-7
16'b0 //garbage
};
assign tx_cycle2[63:0] = {tx_srcaddr[15:0], //48-63
tx_srcaddr[31:16], //32-47
tx_data[15:0], //16-31
tx_data[31:16] //0-15
};
assign tx_data_slow[63:0] = (tx_state[2:0]==`TX_START) ? tx_cycle1[63:0] :
tx_cycle2[63:0];
//#######################################
//# Wait propagation circuit backwards
//########################################
//immediate wait for state machine
assign tx_wait = tx_wr_wait | tx_rd_wait;
//wait for data
assign etx_wr_wait = (tx_wr_wait | tx_ack_wait );
assign etx_rd_wait = (tx_rd_wait | tx_ack_wait );
assign etx_wait = etx_wr_wait | etx_rd_wait;
endmodule // etx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
VPWR,
VGND,
Q ,
Q_N ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg `UNIT_DELAY u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: maximum
*******************************************************************/
`timescale 1ns/1ns
module maximum
#(parameter
C_CNT_BW = 32,
C_RETRY_DELAY = 16
)
(
input clk ,
input rstn ,
//-- to/from producer/consumer ----
output p_prdy ,
input p_crdy ,
input p_cerr ,
output [31:0] p_data ,
input c_prdy ,
output c_crdy ,
output c_cerr ,
input [31:0] c_data ,
//-- to/from reconfiguration controller----
input rc_reqn ,
output rc_ackn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
/* main data register: data1,2 */
wire data1_wr_en, data2_wr_en;
wire is_data_1; wire is_data_2;
reg [31:0] data1,data2;
/* retry & timeout counter */
reg [7:0] retrycnt; wire is_retry;
reg [3:0] tocnt;
/* main fsm */
reg [3:0] state_c, state_n;
localparam [3:0]
S_Rd1 = 4'd0,
S_Rd2 = 4'd1,
S_Wr = 4'd2,
S_ReTry = 4'd3,
S_IDLE = 4'd15;
//-------------------------------------------------------------------
// Datapath Registers
//-------------------------------------------------------------------
/* the retry & timeout counter */
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
retrycnt <= 8'h0;
end else begin
if (state_c == S_ReTry) retrycnt <= retrycnt+1'b1;
else if (state_c == S_Wr) retrycnt <= 'b0;
end
end
assign is_retry = (retrycnt == C_RETRY_DELAY-1);
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
tocnt <= 4'h0;
end else begin
if (c_prdy && ~c_crdy) tocnt <= tocnt + 'h1;
else tocnt <= 4'h0;
end
end
assign c_cerr = (tocnt == 4'hf) & (~c_crdy);
/* the data1,2 register */
assign data1_wr_en = c_prdy & c_crdy & is_data_1;
assign data2_wr_en = c_prdy & c_crdy & is_data_2;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
data1 <= 32'h0;
data2 <= 32'h0;
end else begin
if (data1_wr_en) data1 <= c_data;
if (data2_wr_en) data2 <= c_data;
end
end
/* assigning the output signals */
assign p_data = (data1 > data2)? data1: data2;
/* instantiate the stastical counter */
stat_cnt #(C_CNT_BW) stat_0(
.clk(clk),
.rstn(rstn),
//-- to/from the datapath to be monitored----
.din(c_data),
.din_valid(c_prdy & c_crdy),
.dout(p_data),
.dout_valid(p_prdy & p_crdy)
);
//-------------------------------------------------------------------
// Main FSM - Maximum fsm
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= S_IDLE;
else
state_c <= state_n;
end
always @(*) begin
case (state_c)
S_IDLE:begin state_n = (c_prdy)? S_Rd1:S_IDLE; end
S_Rd1:begin state_n = (c_prdy)? S_Rd2:S_Rd1; end
S_Rd2:begin state_n = (c_prdy)? S_Wr:S_Rd2; end
S_Wr: begin state_n = (p_crdy)? S_IDLE: (p_cerr)? S_ReTry:S_Wr; end
S_ReTry: begin state_n = (is_retry)? S_Wr: S_ReTry; end
default: begin state_n = S_IDLE; end
endcase
end
assign p_prdy = (state_c == S_Wr);
assign c_crdy = (state_c == S_Rd1) || (state_c == S_Rd2);
assign is_data_1 = (state_c == S_Rd1);
assign is_data_2 = (state_c == S_Rd2);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(*) begin
if (state_c==S_Rd1) state_ascii <= "RD1";
else if (state_c==S_Rd2) state_ascii <= "RD2";
else if (state_c==S_Wr) state_ascii <= "WR";
else if (state_c==S_ReTry) state_ascii <= "RETRY";
else if (state_c==S_IDLE) state_ascii <= "IDLE";
else state_ascii <= "ERROR";
end
// synthesis translate_on
//-------------------------------------------------------------------
// InternSync
//-------------------------------------------------------------------
/* intern_sync: synchronize by monitoring the internal idle signal */
wire rc_is_idle;
assign rc_is_idle = (state_c == S_IDLE);
/* instantiate the reconfiguration add-on: intern_sync */
intern_sync sync_0(
.clk(clk),
.rstn(rstn),
//-- to/from core----
.rc_is_idle(rc_is_idle),
//-- to/from reconfiguration controller----
.rc_reqn(rc_reqn),
.rc_ackn(rc_ackn)
);
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module system1_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\Update_Count_From_AB.v
// Created: 2014-09-08 14:12:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Update_Count_From_AB
// Source Path: controllerPeripheralHdlAdi/Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Update_Count_From_AB
(
CLK_IN,
reset,
enb,
A,
B,
index,
count_max,
count
);
input CLK_IN;
input reset;
input enb;
input A;
input B;
input index;
input signed [15:0] count_max; // int16
output signed [15:0] count; // int16
parameter IN_NO_ACTIVE_CHILD = 0, IN_A0_B0 = 1, IN_A0_B1 = 2, IN_A1_B0 = 3, IN_A1_B1 = 4;
parameter IN_INDEX = 0, IN_INIT = 1;
reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB; // uint8
reg [2:0] is_INDEX; // uint8
reg signed [15:0] count_reg; // int16
reg [1:0] is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next; // enumerated type (2 enums)
reg [2:0] is_INDEX_next; // enumerated type (5 enums)
reg signed [15:0] count_reg_next; // int16
always @(posedge CLK_IN)
begin : libEncoderPeripheralHdl_c7_Update_Count_From_AB_process
if (reset == 1'b1) begin
is_INDEX <= IN_NO_ACTIVE_CHILD;
count_reg <= 16'sd0;
//Entry: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//Entry Internal: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//Transition: '<S9>:30'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= IN_INIT;
end
else if (enb) begin
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB <= is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next;
is_INDEX <= is_INDEX_next;
count_reg <= count_reg_next;
end
end
always @(is_libEncoderPeripheralHdl_c7_Update_Count_From_AB, is_INDEX, A, B, index,
count_max, count_reg) begin
count_reg_next = count_reg;
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = is_libEncoderPeripheralHdl_c7_Update_Count_From_AB;
is_INDEX_next = is_INDEX;
//Gateway: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
//During: Encoder_Peripheral_Hardware_Specification/Update_Count_From_AB
case ( is_libEncoderPeripheralHdl_c7_Update_Count_From_AB)
IN_INDEX :
begin
//During 'INDEX': '<S9>:29'
if (index == 1'b1) begin
//Transition: '<S9>:34'
//Transition: '<S9>:35'
count_reg_next = 16'sd0;
//Transition: '<S9>:37'
//Exit Internal 'INDEX': '<S9>:29'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX;
is_INDEX_next = IN_A0_B0;
end
else begin
case ( is_INDEX)
IN_A0_B0 :
begin
//During 'A0_B0': '<S9>:1'
if (A && ( ~ B)) begin
//Transition: '<S9>:14'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
//Transition: '<S9>:13'
is_INDEX_next = IN_A1_B0;
end
else if (( ~ A) && B) begin
//Transition: '<S9>:8'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A0_B1;
end
end
IN_A0_B1 :
begin
//During 'A0_B1': '<S9>:5'
if (A && B) begin
//Transition: '<S9>:10'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A1_B1;
end
else begin
//Transition: '<S9>:16'
if (( ~ A) && ( ~ B)) begin
//Transition: '<S9>:17'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
is_INDEX_next = IN_A0_B0;
end
end
end
IN_A1_B0 :
begin
//During 'A1_B0': '<S9>:2'
if (( ~ A) && ( ~ B)) begin
//Transition: '<S9>:7'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A0_B0;
end
else begin
//Transition: '<S9>:24'
if (A && B) begin
//Transition: '<S9>:25'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
is_INDEX_next = IN_A1_B1;
end
end
end
default :
begin
//During 'A1_B1': '<S9>:4'
if (( ~ A) && B) begin
//Transition: '<S9>:19'
//Graphical Function 'incrementCount': '<S9>:42'
//Transition: '<S9>:44'
count_reg_next = count_reg + 1;
if ((count_reg + 16'sd1) > count_max) begin
//Transition: '<S9>:46'
//Transition: '<S9>:48'
count_reg_next = 16'sd0;
//Transition: '<S9>:51'
end
else begin
//Transition: '<S9>:50'
end
//Transition: '<S9>:21'
is_INDEX_next = IN_A0_B1;
end
else if (A && ( ~ B)) begin
//Transition: '<S9>:22'
//Graphical Function 'decrementCount': '<S9>:55'
//Transition: '<S9>:60'
count_reg_next = count_reg - 1;
if ((count_reg - 16'sd1) < 16'sb0000000000000000) begin
//Transition: '<S9>:61'
//Transition: '<S9>:63'
count_reg_next = count_max;
//Transition: '<S9>:64'
end
else begin
//Transition: '<S9>:62'
end
is_INDEX_next = IN_A1_B0;
end
end
endcase
end
end
default :
begin
//During 'INIT': '<S9>:68'
//Transition: '<S9>:70'
//Transition: '<S9>:35'
count_reg_next = 16'sd0;
//Transition: '<S9>:37'
is_libEncoderPeripheralHdl_c7_Update_Count_From_AB_next = IN_INDEX;
is_INDEX_next = IN_A0_B0;
end
endcase
end
assign count = count_reg_next;
endmodule // Update_Count_From_AB
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_1_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_1_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog wrapper for dlygate4sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S25_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire GATE ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (GATE , GATE_N_delayed );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1061109567; const int MAXN = 510005; int dp[MAXN]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(20); int n, d; cin >> n >> d; memset(dp, 0, sizeof dp); dp[0] = 1; int items[n]; for (int i = 0; i < n; i++) cin >> items[i]; for (int j = 0; j < n; j++) { for (int i = MAXN - items[j]; i >= 0; i--) if (dp[i]) dp[i + items[j]] = 1; } int itCount = 0; int i = 0; while (i < 500000) { bool flag = false; for (int j = i + d; j >= i + 1; j--) { if (dp[j]) { itCount++; i = j; flag = true; break; } } if (!flag) break; } cout << i << << itCount << endl; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; long long seg[5000000]; long long scn[5000000]; void update(long long pos, long long x, long long l = 0, long long r = 300000, long long ind = 1) { if (l == r && l == pos) seg[ind] = x, scn[ind] = x > 0; else if (l > pos || r < pos) return; else if (l != r) { update(pos, x, l, (l + r) / 2, ind * 2); update(pos, x, (l + r) / 2 + 1, r, ind * 2 + 1); seg[ind] = seg[ind * 2] + seg[ind * 2 + 1]; scn[ind] = scn[ind * 2] + scn[ind * 2 + 1]; } } long long query(long long light, long long l = 0, long long r = 300000, long long ind = 1) { if (l == r || scn[ind] == light) return seg[ind]; if (scn[ind * 2] >= light) return query(light, l, (l + r) / 2, ind * 2); else return seg[ind * 2] + query(light - scn[ind * 2], (l + r) / 2 + 1, r, ind * 2 + 1); } int main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; pair<long long, long long> a[n]; set<long long> all; for (long long i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; if (a[i].second > 0) { all.insert(-a[i].second); } } map<long long, long long> mapper; long long cnt = 1; for (auto v : all) { mapper[-v] = cnt++; } cnt = 0; set<long long> light; for (long long i = 0; i < n; i++) { if (a[i].first && a[i].second > 0) light.insert(a[i].second); else if (a[i].first && a[i].second < 0) light.erase(-a[i].second); if (a[i].second > 0) update(mapper[a[i].second], a[i].second), cnt++; else if (a[i].second < 0) update(mapper[-a[i].second], 0), cnt--; long long ans = seg[1]; if (light.size()) update(mapper[(*light.begin())], 0); if (cnt == (long long)light.size()) ans += query((long long)light.size() - 1); else ans += query(light.size()); if (light.size()) update(mapper[(*light.begin())], (*light.begin())); cout << ans << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_PP_BLACKBOX_V
|
// file: MIPS_CPU_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "MIPS_CPU_clk_wiz_0_0,clk_wiz_v5_1,{component_name=MIPS_CPU_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module MIPS_CPU_clk_wiz_0_0
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
MIPS_CPU_clk_wiz_0_0_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, d, x, y, javab1, javab2, ans[1000]; cin >> t; for (int i = 0; i < t; i++) { cin >> n >> x >> y >> d; javab1 = javab2 = n; if ((y - x) % d == 0) { ans[i] = ((abs(y - x)) / d); } else if ((y - 1) % d == 0 || (n - y) % d == 0) { if ((n - y) % d == 0) { javab1 = (n - x + d - 1) / d; javab1 += (n - y) / d; } if ((y - 1) % d == 0) { javab2 = (x - 1 + d - 1) / d; javab2 += (y - 1) / d; } ans[i] = (min(javab2, javab1)); } else { ans[i] = -1; } } for (int i = 0; i < t; i++) { cout << ans[i] << endl; } return 0; }
|
module avlst_n_to_1 #(
parameter N = 8,
parameter DATA_W = 16,
)(
input csi_clk,
input rsi_reset,
output asi_ready,
input asi_valid,
input [N*DATA_W-1:0] asi_data,
input aso_ready,
output aso_valid,
output [DATA_W-1:0] aso_data
);
reg ready;
reg valid;
reg [DATA_W-1:0] data;
reg [DATA_W-1:0] buffer [0:N-1];
assign asi_ready = read;
assign aso_valid = valid;
assign aso_data = data;
reg fval;
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
fval <= 1'b0;
else
if(asi_valid == 1'b1)
fval <= 1'b1;
if(cnt == 3'h7)
end
genvar i;
generate
for(i=0; i<N; i++) begin : main
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
buffer[i] <= {DATA_W{1'b0}};
else begin
if(asi_valid == 1'b1)
buffer[i] <= asi_data[(i+1)*DATA_W-1:i*DATA_W];
end
end
end
endgenerate
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1) begin
valid <= 1'b0;
end
valid <= fval &
end
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1) begin
data <= {DATA_W{1'b0}};
end
data <= buffer[cnt];
end
reg [2:0] cnt;
always@(posedge csi_clk, posedge rsi_reset) begin
if(rsi_reset == 1'b1)
cnt <= 3'h0;
else begin
if(aso_ready == 1'b1 && src_valid == 1'b1)
cnt <= cnt+3'h1;
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master and slave (combined) interface - one cycle read delay.
*
*/
module rcn_master_slave
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [1:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [1:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data,
output slave_cs,
output slave_wr,
output [3:0] slave_mask,
output [23:0] slave_addr,
output [31:0] slave_wdata,
input [31:0] slave_rdata
);
parameter MASTER_ID = 0;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] rin;
reg [68:0] rin_d1;
reg [68:0] rout;
assign rcn_out = rout;
wire [5:0] my_id = MASTER_ID;
wire [23:0] my_mask = ADDR_MASK;
wire [23:0] my_base = ADDR_BASE;
wire my_resp = rin_d1[68] && !rin_d1[67] && (rin_d1[65:60] == my_id);
wire my_req = rin[68] && rin[67] && ((rin[55:34] & my_mask[23:2]) == my_base[23:2]);
reg my_req_d1;
wire [68:0] resp;
wire req_valid;
wire [68:0] req;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rin_d1 <= 69'd0;
my_req_d1 <= 1'b0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rin_d1 <= rin;
my_req_d1 <= my_req;
rout <= (my_req_d1) ? resp : (req_valid) ? req : (my_resp) ? 69'd0 : rin_d1;
end
assign busy = rin_d1[68] && !my_resp;
assign req_valid = cs && !(rin_d1[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, mask, addr[23:2], seq, wdata};
assign rdone = my_resp && !rin_d1[66];
assign wdone = my_resp && rin_d1[66];
assign rsp_seq = rin_d1[33:32];
assign rsp_mask = rin_d1[59:56];
assign rsp_addr = {rin_d1[55:34], 2'd0};
assign rsp_data = rin_d1[31:0];
assign slave_cs = my_req;
assign slave_wr = rin[66];
assign slave_mask = rin[59:56];
assign slave_addr = {rin[55:34], 2'd0};
assign slave_wdata = rin[31:0];
assign resp = {1'b1, 1'b0, rin_d1[66:32], slave_rdata};
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int n, S = 0; char x[2], s[MAXN]; int viv[MAXN]; bool use[MAXN]; int cqf() { int l = -1, r = -1; int ans = MAXN, sum = 0; while (true) { while (r <= n && sum < S) { r++; if (!viv[s[r]] && use[s[r]]) sum++; viv[s[r]]++; } if (sum < S) break; ans = min(ans, r - l + 1); if (viv[s[l]] == 1 && use[s[l]]) sum--; viv[s[l]]--; l++; } return ans; } int main() { memset(viv, 0, sizeof(viv)); memset(use, 0, sizeof(use)); scanf( %d , &n); gets(x); gets(s); for (int i = 0; i < n; i++) { if (use[s[i]] == false) S++; use[s[i]] = true; } printf( %d n , cqf()); return 0; }
|
/***********************************************
Module Name: CORDIC_sqrt_test
Feature: Testbench for CORDIC (mode 3)
An example for the GEM Projects
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
reset: reset flag
------------------------------------------------------
History:
06-27-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
`define MODE 3
`define LENGTH 65536
`define WIDTH 16 + 7
`define ORDER 12
`define CNTR_WIDTH 16
//Insert the modules
module CORDIC_sqrt_test;
//defination for Variables
reg clk;
reg reset;
reg[`CNTR_WIDTH - 1:0] cntr;
//loop for test vectors
reg signed[(`WIDTH-2):0] test_vector_a[(`LENGTH-1):0];
reg signed[(`WIDTH-2):0] test_vector_b[(`LENGTH-1):0];
reg signed[(`WIDTH-2):0] test_vector_sqrt[(`LENGTH-1):0];
//Test Vector Value
wire signed[(`WIDTH-1):0] sqrt_value;
//middle signals
wire signed[(`WIDTH-1):0] sqrt_adj;
wire signed[(`WIDTH-1):0] comp_sqrt;
//Results right? Comparision results
wire[(`WIDTH*2 + 14 -1):0] op;
wire[(`WIDTH*2 + 14 -1):0] res;
wire signed[(`WIDTH-1):0] res_sqrt;
wire [`CNTR_WIDTH - 1:0] index;
assign res_sqrt = res[`WIDTH - 1 + 7: 0];
assign op = { test_vector_a[cntr], test_vector_b[cntr]};
assign index = (cntr - 1 - `ORDER) % `LENGTH;
assign sqrt_value = test_vector_sqrt[index];
assign sqrt_adj = res_sqrt;
assign comp_sqrt = sqrt_value - sqrt_adj;
//Connection to the modules
CORDIC #(.MODE(`MODE))
//CORDIC Mode
C (
.CLK(clk), .RESET_n(reset),
.operand(op), .results(res)
);
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Load the test vectors
initial
begin
$readmemh("a_test_vector.txt", test_vector_a);
$readmemh("b_test_vector.txt", test_vector_b);
$readmemh("sqrt_test_vector.txt", test_vector_sqrt);
end
//Load the input of 0 order element
//Comparision
always @(posedge clk or negedge reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= `CNTR_WIDTH'h00;
end
else
begin
cntr <= cntr + `CNTR_WIDTH'h01;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const int maxm = 1e5 + 10; const int INF = 0x3f3f3f3f; const long long LINF = 3e17 + 1; const int mod = 998244353; int n, m, eid, sz; inline int read() { register int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return (f == 1) ? x : -x; } int a[maxn]; int main() { ; ios::sync_with_stdio(0); cin.tie(0); ; int r; cin >> n >> r; for (int i = 1; i <= n; i++) cin >> a[i]; int cur = 1, res = 0; while (cur <= n) { int idx = 0; for (int i = 1; i <= n; i++) { if (a[i]) { if (cur >= i - r + 1 && cur <= i + r - 1) { idx = i; } } } if (idx == 0) { cout << -1 << endl; return 0; } res++; cur = idx + r; } cout << res << endl; return 0; }
|
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