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#include <bits/stdc++.h> #pragma GCC optimize( Ofast,unroll-loops,no-stack-protector,fast-math,inline ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2 ) using namespace std; using ll = long long; using vvi = vector<vector<int>>; using vi = vector<int>; using vvll = vector<vector<long long>>; using vll = vector<long long>; using vd = vector<double>; using vvd = vector<vector<double>>; using pii = pair<int, int>; using vpii = vector<pair<int, int>>; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } ll MOD = 1e9 + 7; vvll multiply(vvll a, vvll b) { int x = a.size(); int y = b.size(); int z = b[0].size(); assert(y == a[0].size()); vvll ans(x, vll(z)); for (int i = 0; i < x; i++) { for (int j = 0; j < z; j++) { for (int k = 0; k < y; k++) { ans[i][j] += a[i][k] * b[k][j]; ans[i][j] %= MOD; } } } return ans; } vvll binexp(vvll m, ll b) { int n = m.size(); vvll ans(n, vll(n)); for (int i = 0; i < n; i++) { ans[i][i] = 1; } while (b) { if (b & 1) { ans = multiply(ans, m); } m = multiply(m, m); b >>= 1; } return ans; } void solve() { int n, k, m; cin >> n >> k >> m; int d = (k + 1) * (1 << m); vvll mat(d + 1, vll(d + 1)); mat[d][d] = 1; mat[0][d] = 1; for (int j = 1; j <= k; j++) { for (int mask = 0; mask < (1 << m); mask++) { int row = j * (1 << m) + mask; if (mask & 1) { for (int b = 0; b < 2; b++) { mat[row][(j - 1) * (1 << m) + ((b << (m - 1)) | (mask >> 1))] = (__builtin_popcount((b << (m - 1)) | (mask >> 1)) + 1); } } else { for (int b = 0; b < 2; b++) { mat[row][j * (1 << m) + ((b << (m - 1)) | (mask >> 1))] = 1; } } } }; vvll v(d + 1, vll(1)); v[0][0] = 1; v[d][0] = 1; ; vvll e = binexp(mat, n); ; vvll res = multiply(e, v); ; ll ans = 0; for (int mask = 0; mask < (1 << m); mask++) { ans += res[k * (1 << m) + mask][0]; } cout << ans % MOD << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; }
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//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_sharedram_wrap.v
// Version : v1.0
// Description: shared ram wrapper module. To store read data on received
// m_r_channel and write data for m_w_channel
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_sharedram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_RAMINIT_SRAM0_F = "NONE"
) (
input Clk ,
input rst_l ,
//mr
input [10:0] mram_waddr_ff ,
input [C_M_AXI_DATA_WIDTH/8-1:0] mram_we_ff ,
input [C_M_AXI_DATA_WIDTH-1:0] mram_write_data_ff ,
output [C_M_AXI_DATA_WIDTH-1:0] mram_out ,
//mw
input [15:0] maw_agen_addr ,
//sw
input [10:0] slvram_waddr_ff ,
input [7:0] slvram_we_ff ,
input [63:0] slvram_write_data_ff,
output [63:0] sram_rd_data_a ,
//sr
input [15:0] ar_agen_addr
);
// grahams : combining mstram+slvram into one structure.... shrink+functionality
//----------------CHANNEL A ---------------------------------
wire [7:0] sram_we_a ;
wire [9:0] sram_addr_a ;
generate
if(C_M_AXI_DATA_WIDTH == 32) begin: CHA_M_32
assign sram_addr_a = (mram_we_ff[C_M_AXI_DATA_WIDTH/8-1:0] != 0) ? mram_waddr_ff[10:1] : {ar_agen_addr[12:3]};
assign sram_we_a = mram_waddr_ff[0]? {mram_we_ff[C_M_AXI_DATA_WIDTH/8-1:0],4'h0} : {4'h0,mram_we_ff[C_M_AXI_DATA_WIDTH/8-1:0]};
end
endgenerate
generate
if(C_M_AXI_DATA_WIDTH >= 64) begin: CHA_M_G64
assign sram_addr_a = (mram_we_ff[C_M_AXI_DATA_WIDTH/8-1:0] != 0) ? mram_waddr_ff[10:1] : {ar_agen_addr[12:3]};
assign sram_we_a = mram_we_ff[C_M_AXI_DATA_WIDTH/8-1:0]; //use only lower enables for writing.
end
endgenerate
wire [63:0] sram_wr_data_a ;
generate
if( C_M_AXI_DATA_WIDTH == 32) begin: M_R_WR_32
assign sram_wr_data_a[63:0] = (mram_waddr_ff[0])?{
2{mram_write_data_ff[C_M_AXI_DATA_WIDTH-1:0]}}:
mram_write_data_ff;
end
if( C_M_AXI_DATA_WIDTH >= 64) begin: M_R_WR_G64 //store only 64-bit data for widths >= 64bit
assign sram_wr_data_a[63:0] = mram_write_data_ff[C_M_AXI_DATA_WIDTH-1:0];
end
endgenerate
//32-bit read to a 64-bit RAM
reg ar_agen_addr_bit2_ff;
wire [63:0] sram_rd_data_a_pre;
always @(posedge Clk) begin
ar_agen_addr_bit2_ff <= (rst_l) ? ar_agen_addr[2] : 1'b0;
end
generate
if( C_S_AXI_DATA_WIDTH == 32) begin: MRAM_RD_32
assign sram_rd_data_a[C_S_AXI_DATA_WIDTH-1:0] =
(ar_agen_addr_bit2_ff)?{
2{sram_rd_data_a_pre[63:32]}}:
sram_rd_data_a_pre;
end
if( C_S_AXI_DATA_WIDTH == 64) begin: MRAM_RD_64
assign sram_rd_data_a[C_S_AXI_DATA_WIDTH-1:0] = sram_rd_data_a_pre;
end
endgenerate
//----------------CHANNEL B ---------------------------------
wire [7:0] sram_we_b ;
wire [9:0] sram_addr_b ;
wire [9:0] sram_addr_s ;
generate
if(C_M_AXI_DATA_WIDTH == 32) begin: CHB_M_32
assign sram_addr_s = maw_agen_addr[12:3];
end
endgenerate
generate
if(C_M_AXI_DATA_WIDTH == 64) begin: CHB_M_64
assign sram_addr_s = maw_agen_addr[12:3];
end
endgenerate
generate
if(C_M_AXI_DATA_WIDTH == 128) begin: CHB_M_128
assign sram_addr_s = maw_agen_addr[13:4];
end
endgenerate
generate
if(C_M_AXI_DATA_WIDTH == 256) begin: CHB_M_256
assign sram_addr_s = maw_agen_addr[14:5];
end
endgenerate
generate
if(C_M_AXI_DATA_WIDTH == 512) begin: CHB_M_512
assign sram_addr_s = maw_agen_addr[15:6];
end
endgenerate
generate
if(C_S_AXI_DATA_WIDTH == 32 ) begin: CHB_S_32
assign sram_addr_b = (slvram_we_ff[7:0] != 0) ? slvram_waddr_ff[10:1] : sram_addr_s;
assign sram_we_b = slvram_waddr_ff[0]? {slvram_we_ff[3:0],4'h0} : {4'h0,slvram_we_ff[3:0]};
end
endgenerate
generate
if(C_S_AXI_DATA_WIDTH == 64 ) begin: CHB_S_64
assign sram_addr_b = (slvram_we_ff[7:0] != 0) ? slvram_waddr_ff[10:1] : sram_addr_s;
assign sram_we_b = slvram_we_ff[7:0];
end
endgenerate
wire [63:0] sram_wr_data_b = (slvram_we_ff[7:0] != 0) ? slvram_write_data_ff[63:0] : 64'h0;
wire [63:0] sram_rd_data_b;
reg maw_agen_addr_bit2_ff;
always @(posedge Clk) begin
maw_agen_addr_bit2_ff <= (rst_l) ? maw_agen_addr[2] : 1'b0;
end
generate
if( C_M_AXI_DATA_WIDTH == 32) begin: MRAM_WR_32
assign mram_out[C_M_AXI_DATA_WIDTH-1:0] =
(maw_agen_addr_bit2_ff)?{
2{sram_rd_data_b[63:32]}}:
sram_rd_data_b;
end
if( C_M_AXI_DATA_WIDTH == 64) begin: MRAM_WR_64
assign mram_out[C_M_AXI_DATA_WIDTH-1:0] = sram_rd_data_b;
end
//duplicate 64-bit data from SRAM to full axi-width programmed.
if( C_M_AXI_DATA_WIDTH == 128) begin: MRAM_WR_128
assign mram_out[C_M_AXI_DATA_WIDTH-1:0] = {2{sram_rd_data_b}};
end
if( C_M_AXI_DATA_WIDTH == 256) begin: MRAM_WR_256
assign mram_out[C_M_AXI_DATA_WIDTH-1:0] = {4{sram_rd_data_b}};
end
if( C_M_AXI_DATA_WIDTH == 512) begin: MRAM_WR_512
assign mram_out[C_M_AXI_DATA_WIDTH-1:0] = {8{sram_rd_data_b}};
end
endgenerate
axi_traffic_gen_v2_0_7_slvram_v7 #(
.C_FAMILY (C_FAMILY ),
.C_DATAWIDTH (64 ),
.C_SIZE (1024 ),
.C_ADDR_WIDTH(10 ),
//.C_INITRAM_F ("/home/kpolise/mst.mif")
.C_INITRAM_F (C_RAMINIT_SRAM0_F)
) sharedram (
.clk_a (Clk ),
.we_a (sram_we_a ),
.addr_a (sram_addr_a ),
.wr_data_a(sram_wr_data_a ),
.rd_data_a(sram_rd_data_a_pre),
.clk_b (Clk ),
.we_b (sram_we_b ),
.addr_b (sram_addr_b ),
.wr_data_b(sram_wr_data_b ),
.rd_data_b(sram_rd_data_b )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; double a[1 << 19]; double ans; int n, r, w; int main() { scanf( %d%d , &n, &r); w = 1 << n; for (register int i = 0; i < w; i++) { scanf( %lf , &a[i]); ans += a[i]; } printf( %.6lf n , ans / w); while (r--) { int pos; double x; scanf( %d%lf , &pos, &x); ans -= a[pos]; a[pos] = x; ans += a[pos]; printf( %.6lf n , ans / w); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int x; cin >> x; x = abs(x); int pos = 0; int i; for (i = 1; pos < x; i++) pos += i; int diff = pos - x; if (diff % 2 == 0) cout << (i - 1) << endl; else { if (i % 2 != 0) cout << i << endl; else cout << i + 1 << endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd2 (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_PP_SYMBOL_V
|
module test(
input keyon_now,
input keyoff_now,
input [2:0] state_in,
input [9:0] eg_in,
// envelope configuration
input [4:0] arate, // attack rate
input [4:0] rate1, // decay rate
input [4:0] rate2, // sustain rate
input [3:0] rrate,
input [3:0] sl, // sustain level
// SSG operation
input ssg_en,
input [2:0] ssg_eg,
// SSG output inversion
input ssg_inv_in,
output reg ssg_inv_out,
// SSG output hold
input ssg_lock_in,
output reg ssg_lock_out,
output reg [2:0] state_next,
output reg pg_rst,
///////////////////////////////////
// II
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
output cnt_lsb,
///////////////////////////////////
// III
output reg [9:0] pure_eg_out,
///////////////////////////////////
// IV
input [ 6:0] lfo_mod,
input amsen,
input [ 1:0] ams,
input [ 6:0] tl,
output reg [9:0] eg_out
);
wire ssg_inv_out, ssg_lock_out;
wire [4:0] base_rate;
wire attack = state_next[0];
wire step;
wire [5:0] step_rate_out;
jt12_eg_comb uut(
.keyon_now ( keyon_now ),
.keyoff_now ( keyoff_now ),
.state_in ( state_in ),
.eg_in ( eg_in ),
// envelope configuration
.arate ( arate ), // attack rate
.rate1 ( rate1 ), // decay rate
.rate2 ( rate2 ), // sustain rate
.rrate ( rrate ),
.sl ( sl ), // sustain level
// SSG operation
.ssg_en ( ssg_en ),
.ssg_eg ( ssg_eg ),
// SSG output inversion
.ssg_inv_in ( ssg_inv_in ),
.ssg_inv_out ( ssg_inv_out ),
.base_rate ( base_rate ),
.state_next ( state_next ),
.pg_rst ( pg_rst ),
///////////////////////////////////
// II
.step_attack ( attack ),
.step_rate_in ( base_rate ),
.keycode ( keycode ),
.eg_cnt ( eg_cnt ),
.cnt_in ( cnt_in ),
.ks ( ks ),
.cnt_lsb ( cnt_lsb ),
.step ( step ),
.step_rate_out ( step_rate_out ),
///////////////////////////////////
// III
.pure_attack ( attack ),
.pure_step ( step ) ,
.pure_rate (step_rate_out[5:1]),
.pure_ssg_en ( ssg_en ), // from I
.pure_eg_in ( eg_in ),
.pure_eg_out ( pure_eg_out ),
///////////////////////////////////
// IV
.lfo_mod ( lfo_mod ),
.amsen ( amsen ),
.ams ( ams ),
.tl ( tl ),
.final_ssg_inv ( ssg_inv_out ), // from I
.final_eg_in ( pure_eg_out ),
.final_eg_out ( eg_out )
);
endmodule // test
|
`timescale 1 ns / 1 ps
module axi_cfg_register #
(
parameter integer CFG_DATA_WIDTH = 1024,
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
// Configuration bits
output wire [CFG_DATA_WIDTH-1:0] cfg_data,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire [AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, // AXI4-Lite slave: Write strobe
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready // AXI4-Lite slave: Read data ready
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
localparam integer CFG_SIZE = CFG_DATA_WIDTH/AXI_DATA_WIDTH;
localparam integer CFG_WIDTH = CFG_SIZE > 1 ? clogb2(CFG_SIZE-1) : 1;
reg int_bvalid_reg, int_bvalid_next;
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
wire [AXI_DATA_WIDTH-1:0] int_data_mux [CFG_SIZE-1:0];
wire [CFG_DATA_WIDTH-1:0] int_data_wire;
wire [CFG_SIZE-1:0] int_ce_wire;
wire int_wvalid_wire;
genvar j, k;
assign int_wvalid_wire = s_axi_awvalid & s_axi_wvalid;
generate
for(j = 0; j < CFG_SIZE; j = j + 1)
begin : WORDS
assign int_data_mux[j] = int_data_wire[j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1:j*AXI_DATA_WIDTH];
assign int_ce_wire[j] = int_wvalid_wire & (s_axi_awaddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB] == j);
for(k = 0; k < AXI_DATA_WIDTH; k = k + 1)
begin : BITS
FDRE #(
.INIT(1'b0)
) FDRE_inst (
.CE(int_ce_wire[j] & s_axi_wstrb[k/8]),
.C(aclk),
.R(~aresetn),
.D(s_axi_wdata[k]),
.Q(int_data_wire[j*AXI_DATA_WIDTH + k])
);
end
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_bvalid_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
end
else
begin
int_bvalid_reg <= int_bvalid_next;
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_bvalid_next = int_bvalid_reg;
if(int_wvalid_wire)
begin
int_bvalid_next = 1'b1;
end
if(s_axi_bready & int_bvalid_reg)
begin
int_bvalid_next = 1'b0;
end
end
always @*
begin
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_rvalid_next = 1'b1;
int_rdata_next = int_data_mux[s_axi_araddr[ADDR_LSB+CFG_WIDTH-1:ADDR_LSB]];
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign cfg_data = int_data_wire;
assign s_axi_bresp = 2'd0;
assign s_axi_rresp = 2'd0;
assign s_axi_awready = int_wvalid_wire;
assign s_axi_wready = int_wvalid_wire;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = 1'b1;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxcounters.v,v $
// Revision 1.6 2005/02/21 11:00:57 igorm
// Delayed CRC fixed.
//
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
`include "timescale.v"
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= #Tp 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= #Tp 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= #Tp 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double a, b, mn = 1e12; cin >> a >> b; int n; cin >> n; while (n--) { double x, y, v, dis; cin >> x >> y >> v; dis = sqrt((a - x) * (a - x) + (b - y) * (b - y)); dis /= v; mn = min(mn, dis); } cout << fixed << setprecision(7) << mn << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100500; int n, m; char s[N]; int dp[N]; void solve() { scanf( %d%d%s , &n, &m, s); long long ans = (m - 1) * n; for (int i = 0; i < n; i++) { if (i - 1 >= 0 && s[i] != s[i - 1]) ans += (m - 1) * i; if (i + 1 < n && s[i] != s[i + 1]) ans += (m - 1) * (n - 1 - i); } for (int i = 0; i < n; i++) { dp[i] = 1; if (i - 1 >= 0 && s[i - 1] != s[i]) dp[i] = 2; if (i - 2 >= 0 && s[i - 1] != s[i] && s[i - 2] == s[i]) dp[i] = dp[i - 1] + 1; ans -= dp[i] - 1; } printf( %lld n , ans); } int main() { solve(); 0; return 0; }
|
module bcd_to_7seg #(parameter COUNT = 1)
(input wire[COUNT*4 - 1:0] bcd, input wire[COUNT - 1:0] dot,
output reg[COUNT*8 - 1:0] out);
genvar i;
generate
for(i = 0; i < COUNT; i = i + 1) begin: gen
always @(bcd[(i + 1) * 4 - 1 : i * 4] or dot[i]) begin
case(bcd[(i + 1) * 4 - 1 : i * 4])
4'b0000: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1111110, dot[i]};
4'b0001: out[(i + 1) * 8 - 1 : i * 8] <= {7'b0110000, dot[i]};
4'b0010: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1101101, dot[i]};
4'b0011: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1111001, dot[i]};
4'b0100: out[(i + 1) * 8 - 1 : i * 8] <= {7'b0110011, dot[i]};
4'b0101: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1011011, dot[i]};
4'b0110: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1011111, dot[i]};
4'b0111: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1110000, dot[i]};
4'b1000: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1111111, dot[i]};
4'b1001: out[(i + 1) * 8 - 1 : i * 8] <= {7'b1111011, dot[i]};
default: out[(i + 1) * 8 - 1 : i * 8] <= {7'b0000000, dot[i]};
endcase
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int com(const void* a, const void* b) { return *(int*)a - *(int*)b; } int main(void) { int n, k, i; cin >> n >> k; if (n / 2 > k) cout << -1; else if (n == 1 && k != 0) cout << -1; else { i = n / 2 - 1; int l = k - i; if (n > 1) { cout << l << << l * 2 << ; for (l = l * 2 + 1; i > 0; i--, l += 2) printf( %d %d , l, l + 1); } if (n % 2) printf( %d , l); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, res1, res2; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; res1 = a[0] ^ a[1]; vector<int> st; for (int i = 0; i < n; i++) { while (!st.empty() && st.back() < a[i]) st.pop_back(); st.push_back(a[i]); if (st.size() >= 2) res1 = max(res1, st[st.size() - 1] ^ st[st.size() - 2]); } res2 = a[n - 1] ^ a[n - 2]; vector<int> st1; for (int i = n - 1; i >= 0; i--) { while (!st1.empty() && st1.back() < a[i]) st1.pop_back(); st1.push_back(a[i]); if (st1.size() >= 2) res2 = max(res2, st1[st1.size() - 1] ^ st1[st1.size() - 2]); } cout << max(res1, res2); }
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<bool> is_important; vector<vector<int> > graph; vector<int> used; vector<int> res; bool dfs(int v) { used[v] = 1; bool f_p = is_important[v]; for (int u : graph[v]) { if (used[u] == 0) { f_p = dfs(u) || f_p; } else if (used[u] == 1) { cout << -1 << endl; exit(0); } } used[v] = 2; res.push_back(v); return f_p; } int main() { cin >> n >> k; is_important.assign(n, false); used.assign(n, 0); graph.resize(n); for (int i = 0; i < k; i++) { int x; cin >> x; is_important[x - 1] = true; } for (int i = 0; i < n; i++) { int m; cin >> m; for (int j = 0; j < m; j++) { int v; cin >> v; graph[i].push_back(v - 1); } } for (int i = 0; i < n; i++) { if (is_important[i] && used[i] == 0) dfs(i); } cout << res.size() << endl; for (int i = 0; i < res.size(); i++) { cout << res[i] + 1 << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_2_V
`define SKY130_FD_SC_LP__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_2_V
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : uart_tx.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl//uart/uart_tx.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "uart.h"
module uart_tx (
input wire clk,
input wire reset,
input wire tx_start,
input wire [`ByteDataBus] tx_data,
output wire tx_busy,
output reg tx_end,
output reg tx
);
reg [`UartStateBus] state;
reg [`UartDivCntBus] div_cnt;
reg [`UartBitCntBus] bit_cnt;
reg [`ByteDataBus] sh_reg;
assign tx_busy = (state == `UART_STATE_TX) ? `ENABLE : `DISABLE;
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
state <= #1 `UART_STATE_IDLE;
div_cnt <= #1 `UART_DIV_RATE;
bit_cnt <= #1 `UART_BIT_CNT_START;
sh_reg <= #1 `BYTE_DATA_W'h0;
tx_end <= #1 `DISABLE;
tx <= #1 `UART_STOP_BIT;
end else begin
case (state)
`UART_STATE_IDLE : begin
if (tx_start == `ENABLE) begin
state <= #1 `UART_STATE_TX;
sh_reg <= #1 tx_data;
tx <= #1 `UART_START_BIT;
end
tx_end <= #1 `DISABLE;
end
`UART_STATE_TX : begin
if (div_cnt == {`UART_DIV_CNT_W{1'b0}}) begin
case (bit_cnt)
`UART_BIT_CNT_MSB : begin
bit_cnt <= #1 `UART_BIT_CNT_STOP;
tx <= #1 `UART_STOP_BIT;
end
`UART_BIT_CNT_STOP : begin
state <= #1 `UART_STATE_IDLE;
bit_cnt <= #1 `UART_BIT_CNT_START;
tx_end <= #1 `ENABLE;
end
default : begin
bit_cnt <= #1 bit_cnt + 1'b1;
sh_reg <= #1 sh_reg >> 1'b1;
tx <= #1 sh_reg[`LSB];
end
endcase
div_cnt <= #1 `UART_DIV_RATE;
end else begin
div_cnt <= #1 div_cnt - 1'b1 ;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> volc[100000]; int main() { int n, m; scanf( %d , &n); scanf( %d , &m); for (int i = 0; i < m; i++) { scanf( %d , &volc[i].first); scanf( %d , &volc[i].second); } sort(volc, volc + m); int x = 0; vector<pair<int, int> > ints; ints.push_back(make_pair(1, 1)); int i = 0; while (i != m) { if (ints.empty()) break; if (volc[i].first > x + 1) { int f = ints[0].first; ints.clear(); ints.push_back(make_pair(f, n)); } x = volc[i].first; vector<pair<int, int> > ys; int last = 0; while (x == volc[i].first) { if ((volc[i].second - last - 1) > 0) ys.push_back(make_pair(last + 1, volc[i].second - 1)); last = volc[i].second; i++; } if ((n + 1 - last - 1) > 0) ys.push_back(make_pair(last + 1, n)); vector<pair<int, int> > nints; int k = 0; for (int j = 0; j < (int)(ints.size()); j++) { while (k < (int)(ys.size()) && ys[k].second < ints[j].first) k++; while (k < (int)(ys.size()) && ys[k].first <= ints[j].second) { nints.push_back( make_pair(max(ys[k].first, ints[j].first), ys[k].second)); k++; } } ints = nints; } if (ints.empty()) { cout << -1 << endl; return 0; } if (x != n || ints[(int)(ints.size()) - 1].second == n) cout << 2 * (n - 1) << endl; else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int N, M; int A[5002], B[5002]; int D[5002], E[5002], F[5002]; int result; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int getDif(int x) { int resnow = 0; for (int i = 1; i <= M; ++i) while (x % B[i] == 0) { --resnow; x /= B[i]; } for (int i = 2; i * i <= x; ++i) while (x % i == 0) { ++resnow; x /= i; } if (x != 1) ++resnow; return resnow; } int main() { cin.sync_with_stdio(false); cin >> N >> M; for (int i = 1; i <= N; ++i) cin >> A[i]; for (int i = 1; i <= M; ++i) cin >> B[i]; E[0] = 0; for (int i = 1; i <= N; ++i) { E[i] = gcd(E[i - 1], A[i]); F[i] = getDif(E[i]); } int base = 0; for (int i = 1; i <= N; ++i) base += getDif(A[i]); result = base; for (int i = N; i >= 1; --i) { D[i] = F[i] * i; for (int j = i + 1; j <= N; ++j) D[i] = min(D[i], D[j] + (F[i] - F[j]) * i); result = max(result, base - D[i]); } cout << result << n ; }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 4e18; const long long MAX = 1e5; const long long MV = 1e18; const long double PI = 3.14159265358979323846; long long MA = -INF, MI = INF; long long PO(long long x, long long y) { if (y == 0) return 1; long long ans = PO(x, y / 2); ans *= ans, ans %= MOD; if (y % 2 == 1) ans *= x, ans %= MOD; return ans % MOD; } void RE(long long x) { x %= MOD; if (x < 0) x += MOD; } long long fib[100], dp1[100], dp2[100], siz = 2; void cal() { fib[1] = 1, fib[2] = 2; while (true) { long long temp = fib[siz - 1] + fib[siz]; if (temp > MV) break; else fib[++siz] = temp; } } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0), cout << fixed << setprecision(10); cal(); long long t; cin >> t; deque<long long> rep; while (t--) { long long n; cin >> n; for (long long i = siz; i >= 1; i--) { if (n >= fib[i]) rep.push_back(i), n -= fib[i]; } reverse(rep.begin(), rep.end()); rep.push_front(0); long long len = rep.size(); dp1[0] = 1; dp2[0] = 0; for (long long i = 1; i < len; i++) { dp1[i] = dp1[i - 1] + dp2[i - 1]; dp2[i] = (dp1[i - 1] * ((rep[i] - rep[i - 1] - 1) / 2)) + (dp2[i - 1] * ((rep[i] - rep[i - 1]) / 2)); } cout << dp1[len - 1] + dp2[len - 1] << n ; rep.clear(); } return 0; }
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#include <bits/stdc++.h> using ll = int; const ll mod = 1e15 + 7; const ll N = 1e5 + 5; const int base = 400; using ull = unsigned long long; using namespace std; ll n, m, t, k, T, a[N], dp[N], lab[N], u, v, b[N], d[N], tong, cnt, q, fe[N], f[N][20], g[N][20], h[N], P[N][20]; ll ans; vector<ll> adj[N]; vector<pair<ll, ll> > kq; void add(ll id, ll val) { for (; id <= n; id += id & -id) fe[id] += val; } ll get(ll id) { ll total = 0; for (; id > 0; id -= id & -id) total += fe[id]; return total; } ll sum(ll l, ll r) { return get(r) - get(l - 1); } void hop(ll u, ll v) { lab[u] += lab[v]; lab[v] = u; } ll findp(ll u) { return lab[u] < 0 ? u : lab[u] = findp(lab[u]); } pair<ll, ll> p[N]; ll dis(pair<ll, ll> x, pair<ll, ll> y) { return (x.first - y.first) * (x.first - y.first) + (x.second - y.second) * (x.second - y.second); } ll getmn(ll l, ll r) { ll total = mod; for (int i = l; i < r; i++) { for (int j = i + 1; j <= r; j++) total = min(total, dis(p[i], p[j])); } ans = min(ans, total); return total; } void findmn(vector<pair<ll, ll> > pi) { sort(pi.begin(), pi.end()); for (int i = 0; i < pi.size(); i++) { for (int j = i + 1; j < pi.size(); j++) { if ((p[i].first - p[j].first) * (pi[i].first - pi[j].first) > ans) break; ans = min(ans, dis(pi[i], pi[j])); } } } ll cal(ll l, ll r) { if (r - l <= 3) return getmn(l, r); ll mid = (l + r) / 2; ll total = min(cal(l, mid), cal(mid, r)); kq.clear(); for (int i = l; i <= r; i++) { if ((p[i].first - p[mid].first) * (p[i].first - p[mid].first) <= ans) kq.push_back({p[i].second, p[i].first}); } findmn(kq); total = min(total, ans); return total; } void sol() { cin >> n; for (int i = 1; i <= n; i++) { cin >> P[i][0] >> t; P[i][0] = max(P[i][0], (ll)0); if (P[i][0]) h[i] = h[P[i][0]] + 1; if (t == 0) f[i][0] = 1; else if (t == 1) g[i][0] = 1; } for (int j = 1; j <= 18; j++) { for (int i = 1; i <= n; i++) { P[i][j] = P[P[i][j - 1]][j - 1]; f[i][j] = f[i][j - 1] & f[P[i][j - 1]][j - 1]; g[i][j] = g[i][j - 1] & g[P[i][j - 1]][j - 1]; } } cin >> m; while (m-- > 0) { cin >> q >> u >> v; int x = 1, y = 1, z = 1, ui = u, vi = v; for (int i = 18; i >= 0; i--) { if (h[v] >= h[u] + (1 << i)) { x &= f[v][i]; y &= g[v][i]; v = P[v][i]; } } for (int i = 18; i >= 0; i--) { if (h[u] >= h[v] + (1 << i)) { z &= f[u][i]; u = P[u][i]; } } if (u != v) { for (int i = 18; i >= 0; i--) { if (P[u][i] != 0 && P[u][i] != P[v][i]) { x &= f[v][i]; y &= g[v][i]; z &= f[u][i]; u = P[u][i]; v = P[v][i]; } } x &= f[v][0]; y &= g[v][0]; z &= f[u][0]; u = P[u][0]; v = P[v][0]; } if (q == 1) { if (ui != vi && ui == u && x) cout << YES << n ; else cout << NO << n ; } else { if (u != vi && z && y) cout << YES << n ; else cout << NO << n ; } } } int main() { if (fopen( pieaters .inp , r )) { freopen( pieaters .inp , r , stdin); freopen( pieaters .out , w , stdout); } ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int ntest; ntest = 1; while (ntest-- > 0) sol(); }
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#include <bits/stdc++.h> using namespace std; long long a[1 << 20], b[1 << 20], ans; char s[20][1 << 20]; int bit[1 << 20], now, k, n, m, i, N; void FWT(long long *a, int o) { for (int i = 1; i < N; i <<= 1) for (int j = 0; j < N; j += i << 1) for (int k = 0; k < i; k++) { long long x = a[j + k + i], y = a[j + k]; a[j + k] = y + x; a[j + k + i] = y - x; if (o) a[j + k] >>= 1, a[j + k + i] >>= 1; } } int main() { scanf( %d%d , &n, &m); N = 1 << n; for (i = 0; i < n; i++) scanf( %s , s[i]); for (k = 0; k < m; a[now]++, k++) for (i = now = 0; i < n; i++) now |= (1 << i) * (s[i][k] == 1 ); for (i = 0; i < N; i++) bit[i] = bit[i >> 1] + (i & 1); for (i = 0; i < N; i++) b[i] = min(bit[i], bit[(N - 1) ^ i]); FWT(a, 0); FWT(b, 0); for (i = 0; i < N; i++) a[i] *= b[i]; FWT(a, 1); ans = a[1]; for (i = 1; i < (1 << n); i++) ans = min(ans, a[i]); printf( %I64d n , ans); }
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#include <bits/stdc++.h> using namespace std; long long int fast_expo(long long int x, long long int p) { if (p == 0) return 1; else if (p % 2 == 0) { long long int t = fast_expo(x, p / 2) % 1000000007; return (t * t) % 1000000007; } else return (x * (fast_expo(x, p - 1)) % 1000000007) % 1000000007; } int main() { int q; cin >> q; while (q--) { int n; cin >> n; int a[n]; int i, c = 1, c1 = 1, ind; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == 1) ind = i; } i = ind; while (c != n) { if (a[i] == c) { c++; if (i == n - 1) i = 0; else i++; } else break; } i = ind; while (c1 != n) { if (a[i] == c1) { c1++; if (i == 0) i = n - 1; else i--; } else break; } if (c == n || c1 == n) cout << YES << endl; else cout << NO << endl; } }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler, Nick Desaulniers
//
// Create Date: 11:44:01 04/07/2011
// Design Name: execute
// Module Name: execute
// Project Name: omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: Execute stage of pipelined cpu
//
// Revision 0.01 - File Created
// Revision 1.00 - Complete, untested
// Revision 2.00 - Fixed b, removed v and c from alu, tested w/ ModelSim
// Revision 3.00 - Fixed spacing, header (CRC)
// Revision 4.00 - Modified cu_alu_opcode width
// Revision 5.00 - Removed cu_reg_dest and logic for ex_reg_waddr (CRC)
//
//////////////////////////////////////////////////////////////////////////////////
module execute(
input clk_n,
input rst_n,
input [6:0] id_next_addr,
input [15:0] id_register1_data,
input [15:0] id_register2_data,
input [6:0] id_sign_ext_addr,
input [2:0] id_dest_reg_addr,
input [10:0] cu_alu_opcode,
input cu_alu_sel_b,
output [6:0] ex_sign_ext_next_addr,
output ex_alu_z,
output [15:0] ex_alu_result,
output [15:0] ex_register2_data,
output [2:0] ex_reg_waddr
);
wire [15:0] b;
// Mux for second operand
// if( cu_alu_sel_b ){
// b <= id_sign_ext_addr;
// }else{
// b <= id_register2_data;
// }
assign b = cu_alu_sel_b ? id_sign_ext_addr : id_register2_data;
assign ex_reg_waddr = id_dest_reg_addr;
assign ex_sign_ext_next_addr = id_next_addr + id_sign_ext_addr;
assign ex_register2_data = id_register2_data;
alu i_alu(
.a(id_register1_data),
.b(b),
.opcode(cu_alu_opcode),
.rst_n(rst_n),
.clk_n(clk_n),
.out(ex_alu_result),
.z(ex_alu_z)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int k, l, i = 0, mod = 0; cin >> k; cin >> l; while (l > 1) { mod += l % k; l = l / k; i++; } if (mod > 0) cout << NO ; else cout << YES << endl << i - 1; return 0; }
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#include <bits/stdc++.h> namespace LYD { inline int read() { int x = 0, data = 1; char ch = getchar(); while ((ch > 9 || ch < 0 ) && ch != - ) ch = getchar(); if (ch == - ) { ch = getchar(); data = -1; } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * data; } } // namespace LYD int st[105], ans[105]; using namespace LYD; namespace solve {} using namespace solve; int main() { int n = read(), k = read(), tot = 0; for (int i = 1; i <= n; ++i) { int x = read(); if (st[x] == 0) { ++tot; st[x] = i; } } if (tot < k) { printf( NO ); return 0; } int num = 0, ans_num = 0; printf( YES n ); for (int i = 1; i <= k; ++i) { while (st[num] == 0) ++num; ++ans_num; ans[ans_num] = st[num]; ++num; } std ::sort(ans + 1, ans + ans_num + 1); for (int i = 1; i < ans_num; ++i) printf( %d , ans[i]); printf( %d , ans[ans_num]); return 0; }
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#include <bits/stdc++.h> using namespace std; bool DBG = 0; const int dbg = 0; using ii = pair<int, int>; using cd = int64_t; cd gcd(cd a, cd b) { return b ? gcd(b, a % b) : a; } using _LD = long double; struct ld { cd a, b; ld(cd a, cd b = 1) : a(a), b(b) { reduce(); } ld operator-() const { return {-a, b}; } ld& reduce() { if (a) { cd g = gcd(a < 0 ? -a : a, b); a /= g, b /= g; } else b = 1; return *this; } ld& operator+=(ld o) { a = a * o.b + b * o.a, b *= o.b; return reduce(); } ld& operator-=(ld o) { a = a * o.b - b * o.a, b *= o.b; return reduce(); } ld& operator*=(ld o) { a *= o.a, b *= o.b; return reduce(); } ld operator*(ld o) const { return o *= *this; } ld operator+(ld o) const { return o += *this; } ld operator-(ld o) const { ld t = *this; return t -= o; } bool operator==(ld o) const { return a * o.b == b * o.a; } bool operator<(ld o) const { return (_LD(a) / b) < (_LD(o.a) / o.b); } bool operator<=(ld o) const { return *this == o || *this < o; } bool operator>(ld o) const { return !(*this <= o); } bool operator>=(ld o) const { return !(*this < o); } operator _LD() const { return _LD(a) / b; } }; ld abs(ld a) { return {a.a < 0 ? -a.a : a.a, a.b}; } using cord = ld; using vi = vector<int>; using vii = vector<ii>; const ld eps = {0, 1}; struct po { cord X, Y; po operator-(po b) { return {X - b.X, Y - b.Y}; } po& operator-=(po b) { X -= b.X, Y -= b.Y; return *this; } po operator-() const { return {-X, -Y}; } ld cross(po b) const { return X * b.Y - Y * b.X; } bool operator<(const po& a) const { return (X == a.X) ? (Y < a.Y) : (X < a.X); } bool operator<=(const po& a) const { return (X == a.X) ? (Y <= a.Y) : (X <= a.X); } bool operator==(const po& a) const { return X == a.X && Y == a.Y; } operator complex<_LD>() const { return complex<_LD>(X, Y); } _LD arg() const { return ::arg(complex<_LD>(*this)); } }; const _LD _EPS = 1e-9; bool nb = 0; struct acmp { bool operator()(const po& a, const po& b) const { if (a == b) return 0; _LD A = a.arg(), B = b.arg(); return nb ? (A < B - _EPS) : (A < B); } } _acmp; bool argeq(po a, po b) { return (!_acmp(a, b)) && (!_acmp(b, a)); } using ms = map<po, int, acmp>; using poly = vector<po>; ld abs(po a) { return a.X * a.X + a.Y * a.Y; } using i64 = int64_t; ostream& operator<<(ostream& os, ld first) { ld t = first; t *= {1, 1}; return os << ( << i64(t.a) << / << i64(t.b) << ) ; } ostream& operator<<(ostream& os, po a) { return os << (arg(complex<_LD>(a)) * 180 / 3.14159265358979323846); } template <class T> ostream& operator<<(ostream& os, vector<T> v) { os << [ ; for (auto& V : v) os << V << , ; return os << b << ] ; } const ld ZERO = {0, 1}; int orient(po a, po b, po c) { cord r = (b - a).cross(c - a); return r == ZERO ? 0 : (r < ZERO ? -1 : 1); } const po Z = {0, 0}; int isfar(ms& m, ms::iterator it) { if (m.size() == 1) return 0; auto nx = it; ++nx; _LD theta = 0; if (nx == m.end()) nx = m.begin(), theta = 2 * 3.14159265358979323846; theta += nx->first.arg() - it->first.arg(); if (abs(theta - 3.14159265358979323846) <= 1e-8 || theta >= 3.14159265358979323846 + 1e-8) return 1; return 0; } ms::iterator prev(ms& m, ms::iterator it) { if (it == m.begin()) return --m.end(); return --it; } void insert(ms& m, po p, int& far) { if (!m.empty()) { auto it = m.find(p); if (it != m.end()) return void(++it->second); far -= isfar(m, prev(m, m.lower_bound(p))); ++m[p]; far += isfar(m, it = m.find(p)); far += isfar(m, prev(m, it)); if (far) far = 1; } else ++m[p], far = 1; } void remove(ms& m, po p, int& far) { if (m.size() == 1) { far = 1; if (!(--m[p])) m.erase(p); return; } auto it = prev(m.find(p)); far -= isfar(m, it); if (!(--m[p])) m.erase(m.find(p)); far |= isfar(m, prev(m, m.lower_bound(p))); if (far) far = 1; } struct S { int zcnt, far; int64_t ls; po z; map<po, int, acmp> ps; S(po z) : zcnt(0), far(1), ls(0), z(z) {} void insert(po p) { if (DBG) cout << inserting << p - z << endl; if ((p -= z) == Z) return void(++zcnt); auto it = ps.find(-p); if (it != ps.end()) { if (DBG) cout << ls receives << it->second << endl; ls += it->second; } else if (DBG) cout << ls receieves 0 n ; ::insert(ps, p, far); } void erase(po p) { if (DBG) cout << erasing << p - z << endl; if ((p -= z) == Z) return void(--zcnt); auto it = ps.find(-p); if (DBG) cout << ls -= ps.find( << -p << ) n ; if (it != ps.end()) { if (DBG) cout << ls loses << it->second << endl; ls -= it->second; } else if (DBG) cout << ls loses 0 n ; ::remove(ps, p, far); } int query() { if (DBG) cout << zcnt= << zcnt << ,ls= << ls << endl; if (zcnt) return 1; if (ls) return 2; int N = ps.size(); if (N < 3) return 0; return far ? 0 : 3; } }; po cnv(int s, int p, int g) { return {ld(s, s + p + g), ld(p, s + p + g)}; } int main() { if (dbg) freopen( inb.txt , r , stdin); else cin.tie(0)->sync_with_stdio(0); int s, p, g; cin >> s >> p >> g; S d(cnv(s, p, g)); int n; cin >> n; if (n <= 5000) nb = 1; char op; vector<tuple<int, int, int>> bs; for (auto i = 0; i != n; ++i) { if (DBG) cout << i= << i << endl; cin >> op; if (op == A ) { cin >> s >> p >> g; bs.emplace_back(s, p, g); d.insert(cnv(s, p, g)); } else { cin >> s; tie(s, p, g) = bs[s - 1]; d.erase(cnv(s, p, g)); } cout << d.query() << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int Ss[10005], Ee[10005]; int pre[10005 * 200][26]; char A[10005], s[10005], e[10005]; int main() { scanf( %s%s%s , A, s, e); int n = strlen(A); int lens = strlen(s); int lene = strlen(e); int i, j; memset(Ss, 0, sizeof(Ss)); memset(Ee, 0, sizeof(Ee)); memset(pre, -1, sizeof(pre)); for (i = 0; i <= n - lens; i++) { for (j = 0; j < lens; j++) if (A[i + j] != s[j]) break; if (j >= lens) Ss[i] = 1; } for (i = 0; i <= n - lene; i++) { for (j = 0; j < lene; j++) if (A[i + j] != e[j]) break; if (j >= lene) Ee[i + lene - 1] = 1; } int m = (lens > lene ? lens : lene); int cnt = 0; int alloc = 1; for (i = 0; i <= n - m; i++) { if (!Ss[i]) continue; int cur = 0; for (j = i; j < i + m - 1; j++) { if (pre[cur][A[j] - A ] == -1) pre[cur][A[j] - A ] = alloc++; cur = pre[cur][A[j] - A ]; } for (j = i + m - 1; j < n; j++) { if (Ee[j]) if (pre[cur][A[j] - A ] == -1) cnt++; if (pre[cur][A[j] - A ] == -1) pre[cur][A[j] - A ] = alloc++; cur = pre[cur][A[j] - A ]; } } printf( %d n , cnt); return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 200010; const int mod = 1e9 + 7; inline int cal(int x, int y) { int l = 0, r = 1e9; while (l < r) { int mid = l + r + 1 >> 1; if (3ll * mid + y <= x) l = mid; else r = mid - 1; } if (y > x) return 0; return l + 1; } int main() { int n, l, r; while (~scanf( %d%d%d , &n, &l, &r)) { int cnt[5] = {0}, dp[2][5] = {0}, t = 0; for (int i = 0; i < 3; i++) { cnt[i] = cal(r, i) - cal(l - 1, i); } dp[0][0] = 1; for (int i = 1; i <= n; i++) { t ^= 1; for (int j = 0; j < 3; j++) { dp[t][j] = 0; for (int k = 0; k < 3; k++) { dp[t][j] += 1ll * cnt[k] * dp[t ^ 1][(j - k + 3) % 3] % mod; if (dp[t][j] >= mod) dp[t][j] -= mod; } } } printf( %d n , dp[t][0]); } return 0; }
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#include <bits/stdc++.h> using namespace std; int l[100005], r[100005]; int main(int argc, char* argv[]) { std::ios::sync_with_stdio(false); int n, k; scanf( %d%d , &n, &k); int sum = 0; for (int i = 0; i < n; i++) { scanf( %d%d , &l[i], &r[i]); sum += r[i] - l[i] + 1; } int res = 0; while (sum % k != 0) { sum++; res++; } printf( %d n , res); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int a, b; cin >> a >> b; long long int x; x = a % b; if (x == 0) cout << x << endl; else { long long int r = a / b; long long int res = (r + 1) * b - a; cout << res << endl; } } }
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#include <bits/stdc++.h> using namespace std; long long A[200010], sz[200010], v[200010][11]; vector<long long> l[11]; class Timer { private: using clock_t = std::chrono::high_resolution_clock; using second_t = std::chrono::duration<double, std::ratio<1> >; std::chrono::time_point<clock_t> m_beg; public: Timer() : m_beg(clock_t::now()) {} void reset() { m_beg = clock_t::now(); } double elapsed() const { return std::chrono::duration_cast<second_t>(clock_t::now() - m_beg).count(); } } T; long long cnt(long long x) { long long r = 0; while (x) r++, x /= 10; return r; } void precompute(long long n, long long k) { for (long long i = 0; i < n; i++) { sz[i] = cnt(A[i]); long long x = A[i]; v[i][0] = x; for (long long j = 1; j < 11; j++) x = (x * 10) % k, v[i][j] = x; A[i] %= k; } } void put(long long i) { l[sz[i]].push_back(A[i]); return; } long long binary(long long T, long long mod) { long long L = 0, R = (long long)l[T].size() - 1, ans1 = -1; while (L <= R) { long long mid = (L + R) >> 1; if (l[T][mid] == mod) ans1 = mid, R = mid - 1; else if (l[T][mid] > mod) R = mid - 1; else L = mid + 1; } if (ans1 == -1) return 0; L = 0, R = (long long)l[T].size() - 1; long long ans2 = -1; while (L <= R) { long long mid = (L + R) >> 1; if (l[T][mid] == mod) ans2 = mid, L = mid + 1; else if (l[T][mid] > mod) R = mid - 1; else L = mid + 1; } return (ans2 - ans1 + 1); } long long get(long long idx, long long k) { long long ans = 0LL; for (long long i = 1; i < 11; i++) { long long x = v[idx][i]; ans += binary(i, (k - x) % k); if (i == sz[idx] && (v[idx][i] + A[idx]) % k == 0) ans--; } return ans; } signed main() { long long n, k; scanf( %I64d %I64d , &n, &k); for (long long i = 0; i < n; i++) scanf( %I64d , &A[i]); precompute(n, k); for (long long i = 0; i < n; i++) put(i); for (long long i = 1; i < 11; i++) sort(l[i].begin(), l[i].end()); long long ans = 0; for (long long i = 0; i < n; i++) ans += get(i, k); printf( %I64d n , ans); return 0; }
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#include <bits/stdc++.h> const long long mod = 1e8; using namespace std; bool in(int x, int l, int r) { return l <= x && x <= r; } void solve() { long long l, r; cin >> l >> r; vector<long long> v; long long p = -1; for (int i = 61; i >= 0; i--) { unsigned long long mask = 1ull << i; if (mask & r) { v.push_back(i); if (mask & l) { continue; } else { p = i; break; } } } long long ans = 0; if (v.size() == 0) { cout << l << n ; return; } int q = 0; for (int i = p - 1; i >= 0; i--) { unsigned long long mak = 1ull << i; if (mak & r) q++; } if (q == p) { cout << r << n ; return; } for (int i = 0; i < v.size(); i++) { if (v[i] != p) ans += pow(2, v[i]); } for (int i = p - 1; i >= 0; i--) ans += pow(2, i); cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2_PP_SYMBOL_V
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m4_n12_wrap.v ** //
// ** Project : ISAAC Newton / SMAP ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : February 9, 2009 ** //
// ** Description : Wrapper for Real and Imaginary FIR0 with frequency ** //
// ** tunning ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : FIR0_wrap.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Initial Release for SMAP demo ** //
// ** ** //
// ** File : firdecim_m4_n12_wrap.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : February , 2009 ** //
// ** FileName : ** //
// ** Notes : change for 12 taps ** //
// ** ** //
// ******************************************************************************* //
`timescale 1ns/100ps
module firdecim_m4_n12_wrap (/*AUTOARG*/
// Outputs
dsp_outr, dsp_outi, outValid,
// Inputs
dsp_in0, dsp_in1, dsp_in2, dsp_in3, freq, newFreq, clk, rst,
inValid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16;
parameter IWIDTH = 8;
parameter COEFWIDTH = 16;
// DATA TYPE - INPUTS AND OUTPUTS
output signed [(OWIDTH-1):0] dsp_outr;
output signed [(OWIDTH-1):0] dsp_outi;
output outValid;
input signed [(IWIDTH-1):0] dsp_in0;
input signed [(IWIDTH-1):0] dsp_in1;
input signed [(IWIDTH-1):0] dsp_in2;
input signed [(IWIDTH-1):0] dsp_in3;
input [6:0] freq;
input newFreq;
input clk;
input rst;
input inValid;
// DATA TYPE - WIRES
wire signed [(COEFWIDTH-1):0] er,ei;
wire new_e;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
firdecim_m4_n12_freqcalc firdecim_m4_n12_freqcalc
(.clk(clk),
.rst(rst),
.freq(freq),
.newFreq(newFreq),
.er(er),
.ei(ei),
.new_e(new_e)
);
firdecim_m4_n12 RealFIR0
(.clk(clk),
.rst(rst),
.inValid(inValid),
.dsp_in0(dsp_in0),
.dsp_in1(dsp_in1),
.dsp_in2(dsp_in2),
.dsp_in3(dsp_in3),
.ein(er),
.new_e(new_e),
.dsp_out(dsp_outr),
.outValid(outValid)
);
firdecim_m4_n12 ImagFIR0
(.clk(clk),
.rst(rst),
.inValid(inValid),
.dsp_in0(dsp_in0),
.dsp_in1(dsp_in1),
.dsp_in2(dsp_in2),
.dsp_in3(dsp_in3),
.ein(ei),
.new_e(new_e),
.dsp_out(dsp_outi)
);
endmodule // firdecim_m4_n12_wrap
|
#include <bits/stdc++.h> using namespace std; int main() { double r, x1, y1, x2, y2; cin >> r >> x1 >> y1 >> x2 >> y2; double distance = sqrt((x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1)); if (distance == 0) { cout << 0; return 0; } if (distance <= 2 * r) { cout << 1; return 0; } double midDistance = distance - (2 * r); double x = midDistance / (2 * r); int y = x; int z = ceil(x); if ((z - y) == 0) { cout << y + 1; return 0; } else { cout << y + 2; } return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef int matrix[130][130]; long long n; vector<int> v[130]; int k, q[30], d, f[30], h[130], len[30], r[30], ans; matrix a, b, t; char c; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } void mul(matrix a, matrix b) { for (int i = 0; i < len[0]; i++) for (int j = 0; j < len[0]; j++) { t[i][j] = 0; for (int k = 0; k < len[0]; k++) t[i][j] = (t[i][j] + a[i][k] * b[k][j]) % 12345; } for (int i = 0; i < len[0]; i++) for (int j = 0; j < len[0]; j++) a[i][j] = t[i][j]; } void pow(long long n) { for (int i = 0; i < len[0]; i++) a[i][i] = 1; for (int i = 0; n >> i; i++) { if ((n >> i) & 1) mul(a, b); mul(b, b); } } int main() { scanf( %I64d%d , &n, &k); for (int i = 0; i < 26; i++) q[i] = 1; for (int i = 0; i < k; i++) scanf( %c%d , &c, &d), c -= A , q[c] *= d / gcd(d, q[c]), f[c] = 1, v[c].push_back(d); len[26] = 1; for (int j = 25; j >= 0; j--) len[j] = len[j + 1] * q[j]; for (int j = 0; j < len[0]; j++) { for (int i = 0; i < 26; i++) r[i] = j / len[i + 1] % q[i]; h[j] = 1; for (int i = 0; i < 26; i++) if (v[i].size()) { bool fg = 0; for (int d : v[i]) fg |= (r[i] % d == 0); h[j] &= fg; } for (int i = 0; i < 26; i++) if (f[i]) b[j][(r[i] + 1 == q[i]) ? j + len[i + 1] - len[i] : j + len[i + 1]]++; } pow(n); for (int i = 0; i < len[0]; i++) ans += h[i] * a[0][i]; printf( %d n , ans % 12345); }
|
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); const double EPS = 1e-9; const int MOD = 1000000007; const int INF = 1000000000; const long long LINF = 1000000000000000000LL; int main() { int r, h, ret, m, x; scanf( %d %d , &r, &h); r *= 2, h *= 2, ret = h / r * 2, m = h % r, x = m + r / 2; if (m >= r / 2) ret += 2, x -= r; if ((0.5 * r * (sqrt(3.0) + 1.0) - 1.0 * x - 1.0 * r) < EPS) ret++; printf( %d n , ret); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:05:23 02/09/2017
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Display(
/* Inputs */
Value, clk,
/* Outputs */
seg, an
);
input clk; // 700 Hz
input [7:0] Value;
output reg [7:0] seg;
output reg [3:0] an;
wire [7:0] Minute0;
wire [7:0] Minute1;
wire [7:0] Second0;
wire [7:0] Second1;
reg [1:0] state;
reg [1:0] nextState;
wire [3:0] Digit1Input;
wire [3:0] Digit3Input;
wire [3:0] Digit4Input;
binary_to_BCD converter(
.A(Value),
.ONES(Digit3Input),
.TENS(Digit4Input),
.HUNDREDS(Digit1Input)
);
DisplayDigit min0 (
.clk(clk),
.Digit(Digit1Input),
.Display(Minute0)
);
DisplayDigit sec0 (
.clk(clk),
.Digit(Digit3Input),
.Display(Second0)
);
DisplayDigit sec1 (
.clk(clk),
.Digit(Digit4Input),
.Display(Second1)
);
always @(posedge clk) begin
case(state)
2'b00: begin
an = 4'b1110;
seg = Second0;
nextState = 2'b01;
end
2'b01: begin
an = 4'b1101;
seg = Second1;
nextState = 2'b10;
end
2'b10: begin
an = 4'b1011;
seg = Minute0;
nextState = 2'b11;
end
default: begin
an = 4'b0111;
seg = 8'b11111111;
nextState = 2'b00;
end
endcase
end
always @ (posedge clk) begin
state <= nextState;
end
endmodule
module DisplayDigit (
/* Input */
clk, Digit,
/* Output */
Display
);
input clk;//Clock,
input [3:0] Digit;
output reg [7:0] Display;
always @ (posedge clk) begin
case (Digit)
4'h0: Display = 8'b11000000;
4'h1: Display = 8'b11111001;
4'h2: Display = 8'b10100100;
4'h3: Display = 8'b10110000;
4'h4: Display = 8'b10011001;
4'h5: Display = 8'b10010010;
4'h6: Display = 8'b10000010;
4'h7: Display = 8'b11111000;
4'h8: Display = 8'b10000000;
4'h9: Display = 8'b10010000;
default: Display = 8'b11111111;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; map<long long, long long> pos, icon; void read() { cin >> n >> m >> k; for (long long i = 1; i <= n; i++) { long long temp; cin >> temp; pos[temp] = i; icon[i] = temp; } } void solve() { long long ans = 0; for (long long i = 1; i <= m; i++) { long long queri; cin >> queri; ans += -(pos[queri] % k == 0) + pos[queri] / k; long long temp = icon[pos[queri]]; if (pos[queri] != 1) icon[pos[queri]] = icon[pos[queri] - 1], icon[pos[queri] - 1] = temp, pos[icon[pos[queri]]] = pos[queri], pos[icon[pos[queri] - 1]] = pos[queri] - 1; } cout << ans + m; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); read(), solve(); }
|
#include <bits/stdc++.h> using namespace std; int n; int x[33333]; int C[33333]; int BB[33333]; int seen[33333]; int seena[33333]; int main() { scanf( %d , &n); int cc = 0; for (int i = 0; i < 2 * n; i++) { scanf( %d , &x[i]); C[x[i]]++; BB[x[i]]++; } int ca = 0, cb = 0; vector<int> res(2 * n, 0); for (int i = 0; i < 2 * n; i++) { if (C[x[i]] == 1) { cc++; if (cc % 2) { res[i] = 1; ca++; } else { res[i] = 2; cb++; } } else { if (seena[x[i]] == 0) { res[i] = 1; ca++; } else if (seena[x[i]] == 1) { res[i] = 2; cb++; } seena[x[i]]++; } } for (int i = 0; i < 2 * n; i++) { if (res[i] == 0) { if (ca < n) { res[i] = 1; ca++; } else res[i] = 2; } } int can = 0; vector<int> A, B; for (int i = 0; i < 2 * n; i++) { if (res[i] == 1) A.push_back(x[i]); else B.push_back(x[i]); } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { int nn = A[i] * 100 + B[j]; if (!seen[nn]) can++; seen[nn] = 1; } printf( %d n , can); printf( %d , res[0]); for (int i = 1; i < 2 * n; i++) { printf( %d , res[i]); } printf( n ); return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S4_altera (
address,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input clken;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
parameter init_file = "";
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire [3:0] q = sub_wire0[3:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.clocken0 (clken),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
//altsyncram_component.init_file = "./sources_ngnp_multicore/src/lr0_0.mif",
altsyncram_component.intended_device_family = "Stratix II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 4,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module title3 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("title3.mif"),
.C_INIT_FILE("title3.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(3725),
.C_READ_DEPTH_A(3725),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(3725),
.C_READ_DEPTH_B(3725),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.822999 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[1005], b[1005]; int main() { int n, i; scanf( %d , &n); scanf( %s , a + 1); scanf( %s , b + 1); int ans1 = n, ans2 = 0; sort(a + 1, a + 1 + n); sort(b + 1, b + 1 + n); int lab = 1, cnt = 1; while (lab <= n) { if (a[cnt] < b[lab]) { cnt++; ans2++; } lab++; } lab = cnt = n; while (lab >= 1) { if (b[cnt] >= a[lab]) { ans1--; cnt--; } lab--; } cout << ans1 << endl; cout << ans2 << endl; return 0; }
|
module I2CSlave(CLCK, SCL, SDA, CNTR1, CNTR2, CNTR3, CNTR4, CMD, TEND);
input CLCK;
input SCL;
inout SDA;
input[15:0] CNTR1;
input[15:0] CNTR2;
input[15:0] CNTR3;
input[15:0] CNTR4;
output[7:0] CMD;
output[1:0] TEND;
//Device's slave address
parameter slaveaddress = 7'b1110010;
//Count of bytes to be sent, 2 bytes per counter
reg[3:0] valuecnt = 4'b1000;
//Cached counts for period of I2C transaction if an address match happend
reg[15:0] CHCNTR [0:3];
//Synch SCL edge to the CPLD clock
reg [2:0] SCLSynch = 3'b000;
always @(posedge CLCK)
SCLSynch <= {SCLSynch[1:0], SCL};
wire SCL_posedge = (SCLSynch[2:1] == 2'b01);
wire SCL_negedge = (SCLSynch[2:1] == 2'b10);
//Synch SDA to the CPLD clock
reg [2:0] SDASynch = 3'b000;
always @(posedge CLCK)
SDASynch <= {SDASynch[1:0], SDA};
wire SDA_synched = SDASynch[0] & SDASynch[1] & SDASynch[2];
//Detect start and stop
reg start = 1'b0;
always @(negedge SDA)
start = SCL;
reg stop = 1'b0;
always @(posedge SDA)
stop = SCL;
//Set cycle state
reg incycle = 1'b0;
reg[1:0] TEND = 1'b0;
always @(posedge start or posedge stop)
if (start)
begin
if (incycle == 1'b0)
begin
incycle = 1'b1;
TEND = 1'b0;
CHCNTR[0] <= CNTR1;
CHCNTR[1] <= CNTR2;
CHCNTR[2] <= CNTR3;
CHCNTR[3] <= CNTR4;
end
end
else if (stop)
begin
if (incycle == 1'b1)
begin
incycle = 1'b0;
TEND = 1'b1;
end
end
//Address and incomming data handling
reg[7:0] bitcount = 8'b00000000;
reg[6:0] address = 7'b0000000;
reg[7:0] CMD = 8'b00000000;
reg[1:0] rw = 1'b0;
reg[1:0] addressmatch = 1'b0;
always @(posedge SCL_posedge or negedge incycle)
if (~incycle)
begin
//Reset the bit counter at the end of a sequence
bitcount = 0;
end
else
begin
bitcount = bitcount + 1'b1;
//Get the address
if (bitcount < 8)
address[7 - bitcount] = SDA_synched;
if (bitcount == 8)
begin
rw = SDA_synched;
addressmatch = (slaveaddress == address) ? 1'b1 : 1'b0;
end
if ((bitcount > 9) & (~rw))
//Receive data (currently only one byte)
CMD[17 - bitcount] = SDA_synched;
end
//ACK's and out going data
reg sdadata = 1'bz;
reg [3:0] currvalue = 4'b0000;
reg [3:0] byteindex = 4'b0000;
reg [7:0] bitindex = 8'b00000000;
always @(posedge SCL_negedge)
//ACK's
if (((bitcount == 8) | ((bitcount == 17) & ~rw)) & (addressmatch))
begin
sdadata = 1'b0;
currvalue = 4'b0000;
byteindex = currvalue / 2'b10;
bitindex = 4'b1111;
end
//Data
else if ((bitcount >= 9) & (rw) & (addressmatch) & (currvalue < valuecnt))
begin
//Send Data
if (((bitcount - 9) - (currvalue * 9)) == 8)
begin
//Release SDA so master can ACK/NAK
sdadata = 1'bz;
currvalue = currvalue + 1'b1;
byteindex = currvalue / 2'b10;
if (bitindex == 0)
bitindex = 4'b1111;
end
else
begin
sdadata = CHCNTR[byteindex][bitindex];
bitindex = bitindex - 1'b1;
end
end
//Nothing (cause nothing tastes like fresca)
else sdadata = 1'bz;
assign SDA = sdadata;
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
timer module
a simple 32-bit timer. Timer increments on every edge.
*/
module mod_timer(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, int);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
output int;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
reg [31:0] timer;
assign int = timer == 32'hffffffff;
assign ddata = timer;
/* all data bus activity is negative edge triggered */
always @(negedge clk) begin
timer = timer + 1;
if (drw[0] && de && !rst) timer = din;
else if (rst) timer = 0;
end
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Source
-- Description: Emulador de origen de paquetes para la red en-chip. El
modulo se encuentra descrito de manera comportamental.
Este modulo no es sintetizable, su uso se limita a fines
de validacion y pruebas de rendimiento.
-- Dependencies: -- system.vh
-- packet_type.vh
-- Parameters: -- Thold: Tiempo de retencion post - flanco
positivo de la señal de reloj. Tiempo
necesario para que un valor quede
registrado en un elemento de memoria
y sea valido a la salido del elemento.
-- CREDITS: Numero de creditos disponibles en el
router conectado a este modulo.
-- ID: Numero de identificacion de modulo
source. Es utilizado para a
identificacion de modulos individuales
cuando el diseño cuenta con varias
instancias de source.v.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
`include "system.vh"
`include "packet_type.vh"
module source #(
parameter Thold = 5,
parameter PORT = `X_NEG,
parameter CREDITS = 2,
parameter ID = 0
)
(
input wire clk,
// -- inputs ------------------------------------------------- >>>>>
input wire credit_in,
// -- outputs ------------------------------------------------ >>>>>
output reg [`CHANNEL_WIDTH-1:0] channel_out
);
// -- Parametros locales ----------------------------------------- >>>>>
/*
-- Descripcion: El modulo source puede crear log files para el
registro de paquetes inyectados a la red. el
parametro A_ASCII es utilizado como prefixo
para la creacion de varios archivos de manera
secuencial.
*/
localparam A_ASCII = 65;
// -- Variables Globales ----------------------------------------- >>>>>
/*
-- Descripcion:
-- creditos: Variable de registro de numero
de credios disponibles en el
router.
-- packet tick: Instante de tiempo de simulacion
en el cual salio el ultimo
paquete enviado a la red.
-- packet count:Numero de paquetes liberados por
el modulo source.
-- fp: Puntero a manejador de log file
*/
integer creditos;
integer packet_tick;
integer packet_count;
integer fp;
reg [12*8:0] file_name;
reg [4*8:0] port_name;
reg [7:0] file_id;
reg [17:0] extended_serial_field;
reg [11:0] field_serial;
reg [31:0] dato1_flit;
reg [31:0] dato2_flit;
reg [31:0] dato3_flit;
reg [31:0] dato4_flit;
// -- inicializacion de entorno ---------------------------------- >>>>>
initial
begin
fp = 0;
file_name = "";
file_id = A_ASCII + ID;
if (PORT == `X_NEG)
port_name = "XNEG";
else if (PORT == `X_POS)
port_name = "XPOS";
else if (PORT == `Y_NEG)
port_name = "YNEG";
else if (PORT == `Y_POS)
port_name = "YPOS";
else
port_name = "PE__";
channel_out = {`CHANNEL_WIDTH{1'b0}};
creditos = CREDITS;
extended_serial_field = 0;
field_serial = 0;
dato1_flit = 0;
dato2_flit = 0;
dato3_flit = 0;
dato4_flit = 0;
packet_tick = 0;
packet_count = 0;
end
// -- Manejador de creditos -------------------------------------- >>>>>
/*
-- Descripcion: Los creditos regresando al modulo "source" son
capturados de manera automatica por esta rutina. El
registro de ingreso de creditos se lleva a cabo de
manera sincrona.
La actualizacion de la variable "creditos" se lleva
a cabo en el siguiente flanco positivo para emular
el tiempo de procesamiento necesario para
actualizar esta variable en hardware.
*/
always @(posedge clk)
if (credit_in == 1)
begin
#(Thold);
creditos = creditos + 1;
end
// -- TASK: SEND_PACKET ------------------------------------------ >>>>>
/*
-- Descripcion: Metodo para el envio de paquetes a la red. La rutina
se encarga de recibir un dato tipo `PACKET_TYPE
(packet_type.vh) y transferirlo a la red.
Las variables "packet_count" y "packet_tick" se
actualizan durante la ejecucion de esta rutina.
*/
task send_packet;
input `PACKET_TYPE pkt;
integer i;
begin
packet_tick = $time();
// DBG: $display("Data 0: %h", pkt `DATA_0);
// DBG: $display("tiempo %t",$time());
extended_serial_field = pkt `EXTENDED_SERIAL;
dato1_flit = pkt `DATA_0;
dato2_flit = pkt `DATA_1;
dato3_flit = pkt `DATA_2;
dato4_flit = pkt `DATA_3;
$fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
// DBG: $fdisplay(fp, "%d, %d, %d, %d", extended_serial_field, packet_tick, pkt `DESTINO, pkt `PUERTA);
// DBG: "Solo campos de rendimiento" $fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
// DBG: "paquete completo" $fdisplay(fp, "%d, %d, %h, %h, %h, %h", extended_serial_field, packet_tick, dato1_flit, dato2_flit, dato3_flit, dato4_flit);
if (creditos < 1)
@(creditos > 0);
for (i = 0; i < 5; i = i+1)
begin
channel_out <= pkt[`CHANNEL_WIDTH-1:0];
@(posedge clk);
#(Thold);
if (i == 0)
creditos = creditos - 1;
pkt = pkt >> `CHANNEL_WIDTH;
end
packet_count = packet_count + 1;
channel_out = {`CHANNEL_WIDTH{1'bx}};
end
endtask : send_packet
// -- TASK:: OPEN OBSERVER --------------------------------------- >>>>>
/*
-- Descripcion: Tarea de apertura de log file para operaciones
llevadas a cabo por este modulo.
*/
task open_observer;
begin
file_name = {port_name, "_TX", file_id, ".dat"};
$display("%s", file_name);
fp = $fopen(file_name, "w");
if(!fp)
$display("Could not open %s", file_name);
else
$display("Success opening %s", file_name);
end
endtask : open_observer
// -- TASK:: CLOSE_OBSERVER -------------------------------------- >>>>>
/*
-- Descripcion: Cierre de log file.
*/
task close_observer;
begin
$fclose(fp);
$display("%s se cerro de manera exitosa", file_name);
end
endtask : close_observer
endmodule
|
module automatic_events3();
reg [1:0] Source;
initial begin
Source[0] = 1'b0;
forever begin
#20 Source[0] = 1'b1;
#20 Source[0] = 1'b0;
end
end
initial begin
Source[1] = 1'b0;
#15;
forever begin
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b1;
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b0;
end
end
task automatic ReportPosEdge0;
begin
@(posedge Source[0]);
$display("Time %t : Source[0] rise", $time);
end
endtask
task automatic ReportNegEdge0;
begin
@(negedge Source[0]);
$display("Time %t : Source[0] fall", $time);
end
endtask
task automatic ReportAnyEdge0;
time t;
begin
@(Source[0]) t = $time;
#1 $display("Time %t : Source[0] edge", t);
end
endtask
task automatic ReportPosEdge1;
begin
@(posedge Source[1]);
$display("Time %t : Source[1] rise", $time);
end
endtask
task automatic ReportNegEdge1;
begin
@(negedge Source[1]);
$display("Time %t : Source[1] fall", $time);
end
endtask
task automatic ReportAnyEdge1;
time t;
begin
@(Source[1]) t = $time;
#1 $display("Time %t : Source[1] edge", t);
end
endtask
initial begin
#1;
fork
repeat(2) ReportPosEdge0;
repeat(2) ReportNegEdge0;
repeat(4) ReportAnyEdge0;
repeat(4) ReportPosEdge1;
repeat(4) ReportNegEdge1;
repeat(8) ReportAnyEdge1;
join
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using pii = pair<int, int>; using pll = pair<ll, ll>; template <class T> inline bool Min(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> inline bool Max(T &a, T b) { return a < b ? (a = b, true) : false; } inline int ni() { int a; scanf( %d , &a); return a; } inline ll nl() { ll a; scanf( %lld , &a); return a; } inline double nd() { double a; scanf( %lf , &a); return a; } inline void pi(int a) { printf( %d , a); } inline void pl(ll a) { printf( %lld , a); } inline void pd(double a) { printf( %.12lf , a); } const int N = 1e5 + 10; using ld = long double; void solve() { ld x, y, z; cin >> x >> y >> z; ld ans[10]; ans[1] = log(x) * pow(y, z); ans[2] = log(x) * pow(z, y); ans[3] = log(x) * y * z; ans[4] = log(y) * pow(x, z); ans[5] = log(y) * pow(z, x); ans[6] = log(y) * x * z; ans[7] = log(z) * pow(x, y); ans[8] = log(z) * pow(y, x); ans[9] = log(z) * x * y; ans[0] = ans[1]; int t = 1; for (int i = 1; i <= 9; i++) if (Max(ans[0], ans[i])) t = i; if (t == 1) puts( x^y^z ); if (t == 2) puts( x^z^y ); if (t == 3) puts( (x^y)^z ); if (t == 4) puts( y^x^z ); if (t == 5) puts( y^z^x ); if (t == 6) puts( (y^x)^z ); if (t == 7) puts( z^x^y ); if (t == 8) puts( z^y^x ); if (t == 9) puts( (z^x)^y ); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long dp[15][1 << 15]; int n, m, q; struct NodeLCA { int a, b, c; }; vector<pair<int, int> > path; vector<NodeLCA> LCA; void readData() { cin >> n >> m >> q; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; u--; v--; path.push_back(make_pair(u, v)); } for (int i = 0; i < q; i++) { int u, v, w; cin >> u >> v >> w; u--; v--; w--; LCA.push_back({u, v, w}); } } int check(int root, int mask1, int child, int mask2) { for (int i = 0; i < path.size(); i++) { if (!(mask1 & (1 << path[i].first)) || !(mask1 & (1 << path[i].second))) continue; if (((mask2 & (1 << path[i].first)) > 0) == ((mask2 & (1 << path[i].second)) > 0)) continue; if (path[i].second == root) swap(path[i].first, path[i].second); if ((path[i].first != root) || (path[i].second != child)) return 0; } for (int i = 0; i < LCA.size(); i++) { if (!(mask1 & (1 << LCA[i].a)) || !(mask1 & (1 << LCA[i].b))) continue; if (((mask2 & (1 << LCA[i].a)) > 0) == ((mask2 & (1 << LCA[i].b)) > 0)) continue; if (LCA[i].c != root) return 0; } return 1; } void dynamicProgramming() { int mask, submask; for (int i = 0; i < n; i++) dp[i][1 << i] = 1; for (mask = 1; mask < (1 << n); mask++) for (int i = 0; i < n; i++) if (mask & (1 << i)) { int tmp = -1; for (int t = 0; t < n; t++) if (t != i && (mask & (1 << t))) tmp = t; if (tmp == -1) continue; for (submask = (mask - 1) & mask; submask > 0; submask = (submask - 1) & mask) if ((submask & (1 << tmp)) && !(submask & (1 << i))) for (int child = 0; child < n; child++) if (submask & (1 << child)) { if (check(i, mask, child, submask)) dp[i][mask] += dp[child][submask] * dp[i][mask - submask]; } } } void writeData() { cout << dp[0][(1 << n) - 1]; } int main() { readData(); for (int i = 0; i < LCA.size(); i++) if (LCA[i].a == LCA[i].b && LCA[i].a != LCA[i].c) { cout << 0; return 0; } dynamicProgramming(); writeData(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int M = 1000000007; const int MM = 998244353; const long double PI = acos(-1); long long power(long long b, long long e, long long m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long power(long long b, long long e) { if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } template <typename T, typename U> static inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> static inline void amax(T &x, U y) { if (x < y) x = y; } template <typename T, typename U> ostream &operator<<(ostream &os, const pair<T, U> &p) { return os << ( << p.first << , << p.second << ) ; } const int N = 500005; long long c[N]; map<long long, vector<pair<int, int>>> ed; struct DSU { vector<int> p, r; int n; int components; DSU(int _) : n(_), components(_) { p.resize(n + 1); r.resize(n + 1); for (int i = 0; i <= _; ++i) p[i] = i, r[i] = 0; } int parent(int i) { return p[i] = (p[i] == i) ? i : parent(p[i]); } void merge(int x, int y) { x = parent(x); y = parent(y); if (x == y) return; if (r[x] > r[y]) p[y] = x; else p[x] = y; if (r[x] == r[y]) ++r[y]; --components; } }; int _runtimeTerror_() { long long ans = 0; int n, m, k; cin >> n >> m >> k; for (int i = 1; i <= n; ++i) cin >> c[i]; ans += power(2, n, M) * ((1LL << k) % M) % M; for (int i = 1; i <= m; ++i) { int x, y; cin >> x >> y; ed[c[x] ^ c[y]].push_back({x, y}); } DSU dsu(n); for (auto &j : ed) { int cnt = 0; for (auto &k : j.second) dsu.p[k.first] = k.first, dsu.p[k.second] = k.second; dsu.components = n; for (auto &k : j.second) { dsu.merge(k.first, k.second); } ans -= power(2, n, M); ans %= M; ans += power(2, dsu.components, M); ans = (ans + M) % M; } cout << ans << n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) _runtimeTerror_(); return 0; }
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`default_nettype none
`include "irq.h"
/****
HOLD
0 START
1 MOVE_K2U
1 MOVE_UK
2 EMD
*/
module execute_exception_check_inst(
//Execute Module State
input wire iPREV_STATE_NORMAL,
//Previous Instruxtion
input wire iPREV_FAULT_PAGEFAULT,
input wire iPREV_FAULT_PRIVILEGE_ERROR,
input wire iPREV_FAULT_INVALID_INST,
input wire iPREV_FAULT_DIVIDE_ZERO,
//Output Exception
output wire oEXCEPT_VALID,
output wire [6:0] oEXCEPT_NUM
);
/**************************************************************************************************
General Instruction Exception
**************************************************************************************************/
function [7:0] func_exception_check;
input func_pagefault;
input func_privilege;
input func_invalid_inst;
input func_div_error;
begin
if(func_pagefault)begin
func_exception_check = {1'b1, `INT_NUM_PAGEFAULT};
end
else if(func_privilege)begin
func_exception_check = {1'b1, `INT_NUM_PRIVILEGE_ERRPR};
end
else if(func_invalid_inst)begin
func_exception_check = {1'b1, `INT_NUM_INSTRUCTION_INVALID};
end
else if(func_div_error)begin
func_exception_check = {1'b1, `INT_NUM_DIVIDER_ERROR};
end
else begin
func_exception_check = 8'h0;
end
end
endfunction
wire exception_valid;
wire [6:0] exception_num;
assign {exception_valid, exception_num} = func_exception_check(
iPREV_FAULT_PAGEFAULT,
iPREV_FAULT_PRIVILEGE_ERROR,
iPREV_FAULT_INVALID_INST,
iPREV_FAULT_DIVIDE_ZERO
);
assign oEXCEPT_VALID = exception_valid;
assign oEXCEPT_NUM = exception_num;
endmodule
`default_nettype wire
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#include <bits/stdc++.h> using namespace std; const int N = 2 * 1000 * 100 + 10; int to[N], nxt[N], idx[N], tot; int rnk[N], sz[N]; bool visited[N]; int minsz, center; void add_edge(int u, int v) { ++tot; to[tot] = v; nxt[tot] = idx[u]; idx[u] = tot; } int compute_size(int node, int parent) { int s = 1; for (int i = idx[node]; i != 0; i = nxt[i]) { if (!visited[to[i]] && parent != to[i]) { s += compute_size(to[i], node); } } return sz[node] = s; } void compute_center(int node, int parent, int totsz) { int upsz = totsz - sz[node]; int dnsz = -1; for (int i = idx[node]; i != 0; i = nxt[i]) { if (!visited[to[i]] && parent != to[i]) { compute_center(to[i], node, totsz); dnsz = max(dnsz, sz[to[i]]); } } if (max(upsz, dnsz) < minsz) { minsz = max(upsz, dnsz); center = node; } } void dfs(int node, int depth) { int totsz = compute_size(node, 0); minsz = INT_MAX; compute_center(node, 0, totsz); int c = center; rnk[c] = depth; visited[c] = true; for (int i = idx[c]; i != 0; i = nxt[i]) { if (!visited[to[i]]) { dfs(to[i], depth + 1); } } } int main() { ios_base::sync_with_stdio(false); tot = 0; memset(nxt, 0, sizeof(nxt)); memset(idx, 0, sizeof(idx)); memset(visited, false, sizeof(visited)); int n; cin >> n; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; add_edge(u, v); add_edge(v, u); } dfs(1, 0); for (int i = 1; i <= n; i++) { cout << static_cast<char>(rnk[i] + A ) << ; } cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 1e5; int a[100][100]; int main() { int n, i = 0; cin >> n; cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); cin >> a[i / n][i % n]; i++; a[i / n][i % n] = (i >= n * n ? INF : a[i / n][i % n]); i = 0; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[i / 10][i % 10] = ((i / 10 >= n || i % 10 >= n) ? INF : a[i / 10][i % 10]); i++; a[0][0] = min(a[0][0], a[0][0] + a[0][0]); a[0][1] = min(a[0][1], a[0][0] + a[0][1]); a[0][2] = min(a[0][2], a[0][0] + a[0][2]); a[0][3] = min(a[0][3], a[0][0] + a[0][3]); a[0][4] = min(a[0][4], a[0][0] + a[0][4]); a[0][5] = min(a[0][5], a[0][0] + a[0][5]); a[0][6] = min(a[0][6], a[0][0] + a[0][6]); a[0][7] = min(a[0][7], a[0][0] + a[0][7]); a[0][8] = min(a[0][8], a[0][0] + a[0][8]); a[0][9] = min(a[0][9], a[0][0] + a[0][9]); a[1][0] = min(a[1][0], a[1][0] + a[0][0]); a[1][1] = min(a[1][1], a[1][0] + a[0][1]); a[1][2] = min(a[1][2], a[1][0] + a[0][2]); a[1][3] = min(a[1][3], a[1][0] + a[0][3]); a[1][4] = min(a[1][4], a[1][0] + a[0][4]); a[1][5] = min(a[1][5], a[1][0] + a[0][5]); a[1][6] = min(a[1][6], a[1][0] + a[0][6]); a[1][7] = min(a[1][7], a[1][0] + a[0][7]); a[1][8] = min(a[1][8], a[1][0] + a[0][8]); a[1][9] = min(a[1][9], a[1][0] + a[0][9]); a[2][0] = min(a[2][0], a[2][0] + a[0][0]); a[2][1] = min(a[2][1], a[2][0] + a[0][1]); a[2][2] = min(a[2][2], a[2][0] + a[0][2]); a[2][3] = min(a[2][3], a[2][0] + a[0][3]); a[2][4] = min(a[2][4], a[2][0] + a[0][4]); a[2][5] = min(a[2][5], a[2][0] + a[0][5]); a[2][6] = min(a[2][6], a[2][0] + a[0][6]); a[2][7] = min(a[2][7], a[2][0] + a[0][7]); a[2][8] = min(a[2][8], a[2][0] + a[0][8]); a[2][9] = min(a[2][9], a[2][0] + a[0][9]); a[3][0] = min(a[3][0], a[3][0] + a[0][0]); a[3][1] = min(a[3][1], a[3][0] + a[0][1]); a[3][2] = min(a[3][2], a[3][0] + a[0][2]); a[3][3] = min(a[3][3], a[3][0] + a[0][3]); a[3][4] = min(a[3][4], a[3][0] + a[0][4]); a[3][5] = min(a[3][5], a[3][0] + a[0][5]); a[3][6] = min(a[3][6], a[3][0] + a[0][6]); a[3][7] = min(a[3][7], a[3][0] + a[0][7]); a[3][8] = min(a[3][8], a[3][0] + a[0][8]); a[3][9] = min(a[3][9], a[3][0] + a[0][9]); a[4][0] = min(a[4][0], a[4][0] + a[0][0]); a[4][1] = min(a[4][1], a[4][0] + a[0][1]); a[4][2] = min(a[4][2], a[4][0] + a[0][2]); a[4][3] = min(a[4][3], a[4][0] + a[0][3]); a[4][4] = min(a[4][4], a[4][0] + a[0][4]); a[4][5] = min(a[4][5], a[4][0] + a[0][5]); a[4][6] = min(a[4][6], a[4][0] + a[0][6]); a[4][7] = min(a[4][7], a[4][0] + a[0][7]); a[4][8] = min(a[4][8], a[4][0] + a[0][8]); a[4][9] = min(a[4][9], a[4][0] + a[0][9]); a[5][0] = min(a[5][0], a[5][0] + a[0][0]); a[5][1] = min(a[5][1], a[5][0] + a[0][1]); a[5][2] = min(a[5][2], a[5][0] + a[0][2]); a[5][3] = min(a[5][3], a[5][0] + a[0][3]); a[5][4] = min(a[5][4], a[5][0] + a[0][4]); a[5][5] = min(a[5][5], a[5][0] + a[0][5]); a[5][6] = min(a[5][6], a[5][0] + a[0][6]); a[5][7] = min(a[5][7], a[5][0] + a[0][7]); a[5][8] = min(a[5][8], a[5][0] + a[0][8]); a[5][9] = min(a[5][9], a[5][0] + a[0][9]); a[6][0] = min(a[6][0], a[6][0] + a[0][0]); a[6][1] = min(a[6][1], a[6][0] + a[0][1]); a[6][2] = min(a[6][2], a[6][0] + a[0][2]); a[6][3] = min(a[6][3], a[6][0] + a[0][3]); a[6][4] = min(a[6][4], a[6][0] + a[0][4]); a[6][5] = min(a[6][5], a[6][0] + a[0][5]); a[6][6] = min(a[6][6], a[6][0] + a[0][6]); a[6][7] = min(a[6][7], a[6][0] + a[0][7]); a[6][8] = min(a[6][8], a[6][0] + a[0][8]); a[6][9] = min(a[6][9], a[6][0] + a[0][9]); a[7][0] = min(a[7][0], a[7][0] + a[0][0]); a[7][1] = min(a[7][1], a[7][0] + a[0][1]); a[7][2] = min(a[7][2], a[7][0] + a[0][2]); a[7][3] = min(a[7][3], a[7][0] + a[0][3]); a[7][4] = min(a[7][4], a[7][0] + a[0][4]); a[7][5] = min(a[7][5], a[7][0] + a[0][5]); a[7][6] = min(a[7][6], a[7][0] + a[0][6]); a[7][7] = min(a[7][7], a[7][0] + a[0][7]); a[7][8] = min(a[7][8], a[7][0] + a[0][8]); a[7][9] = min(a[7][9], a[7][0] + a[0][9]); a[8][0] = min(a[8][0], a[8][0] + a[0][0]); a[8][1] = min(a[8][1], a[8][0] + a[0][1]); a[8][2] = min(a[8][2], a[8][0] + a[0][2]); a[8][3] = min(a[8][3], a[8][0] + a[0][3]); a[8][4] = min(a[8][4], a[8][0] + a[0][4]); a[8][5] = min(a[8][5], a[8][0] + a[0][5]); a[8][6] = min(a[8][6], a[8][0] + a[0][6]); a[8][7] = min(a[8][7], a[8][0] + a[0][7]); a[8][8] = min(a[8][8], a[8][0] + a[0][8]); a[8][9] = min(a[8][9], a[8][0] + a[0][9]); a[9][0] = min(a[9][0], a[9][0] + a[0][0]); a[9][1] = min(a[9][1], a[9][0] + a[0][1]); a[9][2] = min(a[9][2], a[9][0] + a[0][2]); a[9][3] = min(a[9][3], a[9][0] + a[0][3]); a[9][4] = min(a[9][4], a[9][0] + a[0][4]); a[9][5] = min(a[9][5], a[9][0] + a[0][5]); a[9][6] = min(a[9][6], a[9][0] + a[0][6]); a[9][7] = min(a[9][7], a[9][0] + a[0][7]); a[9][8] = min(a[9][8], a[9][0] + a[0][8]); a[9][9] = min(a[9][9], a[9][0] + a[0][9]); a[0][0] = min(a[0][0], a[0][1] + a[1][0]); a[0][1] = min(a[0][1], a[0][1] + a[1][1]); a[0][2] = min(a[0][2], a[0][1] + a[1][2]); a[0][3] = min(a[0][3], a[0][1] + a[1][3]); a[0][4] = min(a[0][4], a[0][1] + a[1][4]); a[0][5] = min(a[0][5], a[0][1] + a[1][5]); a[0][6] = min(a[0][6], a[0][1] + a[1][6]); a[0][7] = min(a[0][7], a[0][1] + a[1][7]); a[0][8] = min(a[0][8], a[0][1] + a[1][8]); a[0][9] = min(a[0][9], a[0][1] + a[1][9]); a[1][0] = min(a[1][0], a[1][1] + a[1][0]); a[1][1] = min(a[1][1], a[1][1] + a[1][1]); a[1][2] = min(a[1][2], a[1][1] + a[1][2]); a[1][3] = min(a[1][3], a[1][1] + a[1][3]); a[1][4] = min(a[1][4], a[1][1] + a[1][4]); a[1][5] = min(a[1][5], a[1][1] + a[1][5]); a[1][6] = min(a[1][6], a[1][1] + a[1][6]); a[1][7] = min(a[1][7], a[1][1] + a[1][7]); a[1][8] = min(a[1][8], a[1][1] + a[1][8]); a[1][9] = min(a[1][9], a[1][1] + a[1][9]); a[2][0] = min(a[2][0], a[2][1] + a[1][0]); a[2][1] = min(a[2][1], a[2][1] + a[1][1]); a[2][2] = min(a[2][2], a[2][1] + a[1][2]); a[2][3] = min(a[2][3], a[2][1] + a[1][3]); a[2][4] = min(a[2][4], a[2][1] + a[1][4]); a[2][5] = min(a[2][5], a[2][1] + a[1][5]); a[2][6] = min(a[2][6], a[2][1] + a[1][6]); a[2][7] = min(a[2][7], a[2][1] + a[1][7]); a[2][8] = min(a[2][8], a[2][1] + a[1][8]); a[2][9] = min(a[2][9], a[2][1] + a[1][9]); a[3][0] = min(a[3][0], a[3][1] + a[1][0]); a[3][1] = min(a[3][1], a[3][1] + a[1][1]); a[3][2] = min(a[3][2], a[3][1] + a[1][2]); a[3][3] = min(a[3][3], a[3][1] + a[1][3]); a[3][4] = min(a[3][4], a[3][1] + a[1][4]); a[3][5] = min(a[3][5], a[3][1] + a[1][5]); a[3][6] = min(a[3][6], a[3][1] + a[1][6]); a[3][7] = min(a[3][7], a[3][1] + a[1][7]); a[3][8] = min(a[3][8], a[3][1] + a[1][8]); a[3][9] = min(a[3][9], a[3][1] + a[1][9]); a[4][0] = min(a[4][0], a[4][1] + a[1][0]); a[4][1] = min(a[4][1], a[4][1] + a[1][1]); a[4][2] = min(a[4][2], a[4][1] + a[1][2]); a[4][3] = min(a[4][3], a[4][1] + a[1][3]); a[4][4] = min(a[4][4], a[4][1] + a[1][4]); a[4][5] = min(a[4][5], a[4][1] + a[1][5]); a[4][6] = min(a[4][6], a[4][1] + a[1][6]); a[4][7] = min(a[4][7], a[4][1] + a[1][7]); a[4][8] = min(a[4][8], a[4][1] + a[1][8]); a[4][9] = min(a[4][9], a[4][1] + a[1][9]); a[5][0] = min(a[5][0], a[5][1] + a[1][0]); a[5][1] = min(a[5][1], a[5][1] + a[1][1]); a[5][2] = min(a[5][2], a[5][1] + a[1][2]); a[5][3] = min(a[5][3], a[5][1] + a[1][3]); a[5][4] = min(a[5][4], a[5][1] + a[1][4]); a[5][5] = min(a[5][5], a[5][1] + a[1][5]); a[5][6] = min(a[5][6], a[5][1] + a[1][6]); a[5][7] = min(a[5][7], a[5][1] + a[1][7]); a[5][8] = min(a[5][8], a[5][1] + a[1][8]); a[5][9] = min(a[5][9], a[5][1] + a[1][9]); a[6][0] = min(a[6][0], a[6][1] + a[1][0]); a[6][1] = min(a[6][1], a[6][1] + a[1][1]); a[6][2] = min(a[6][2], a[6][1] + a[1][2]); a[6][3] = min(a[6][3], a[6][1] + a[1][3]); a[6][4] = min(a[6][4], a[6][1] + a[1][4]); a[6][5] = min(a[6][5], a[6][1] + a[1][5]); a[6][6] = min(a[6][6], a[6][1] + a[1][6]); a[6][7] = min(a[6][7], a[6][1] + a[1][7]); a[6][8] = min(a[6][8], a[6][1] + a[1][8]); a[6][9] = min(a[6][9], a[6][1] + a[1][9]); a[7][0] = min(a[7][0], a[7][1] + a[1][0]); a[7][1] = min(a[7][1], a[7][1] + a[1][1]); a[7][2] = min(a[7][2], a[7][1] + a[1][2]); a[7][3] = min(a[7][3], a[7][1] + a[1][3]); a[7][4] = min(a[7][4], a[7][1] + a[1][4]); a[7][5] = min(a[7][5], a[7][1] + a[1][5]); a[7][6] = min(a[7][6], a[7][1] + a[1][6]); a[7][7] = min(a[7][7], a[7][1] + a[1][7]); a[7][8] = min(a[7][8], a[7][1] + a[1][8]); a[7][9] = min(a[7][9], a[7][1] + a[1][9]); a[8][0] = min(a[8][0], a[8][1] + a[1][0]); a[8][1] = min(a[8][1], a[8][1] + a[1][1]); a[8][2] = min(a[8][2], a[8][1] + a[1][2]); a[8][3] = min(a[8][3], a[8][1] + a[1][3]); a[8][4] = min(a[8][4], a[8][1] + a[1][4]); a[8][5] = min(a[8][5], a[8][1] + a[1][5]); a[8][6] = min(a[8][6], a[8][1] + a[1][6]); a[8][7] = min(a[8][7], a[8][1] + a[1][7]); a[8][8] = min(a[8][8], a[8][1] + a[1][8]); a[8][9] = min(a[8][9], a[8][1] + a[1][9]); a[9][0] = min(a[9][0], a[9][1] + a[1][0]); a[9][1] = min(a[9][1], a[9][1] + a[1][1]); a[9][2] = min(a[9][2], a[9][1] + a[1][2]); a[9][3] = min(a[9][3], a[9][1] + a[1][3]); a[9][4] = min(a[9][4], a[9][1] + a[1][4]); a[9][5] = min(a[9][5], a[9][1] + a[1][5]); a[9][6] = min(a[9][6], a[9][1] + a[1][6]); a[9][7] = min(a[9][7], a[9][1] + a[1][7]); a[9][8] = min(a[9][8], a[9][1] + a[1][8]); a[9][9] = min(a[9][9], a[9][1] + a[1][9]); a[0][0] = min(a[0][0], a[0][2] + a[2][0]); a[0][1] = min(a[0][1], a[0][2] + a[2][1]); a[0][2] = min(a[0][2], a[0][2] + a[2][2]); a[0][3] = min(a[0][3], a[0][2] + a[2][3]); a[0][4] = min(a[0][4], a[0][2] + a[2][4]); a[0][5] = min(a[0][5], a[0][2] + a[2][5]); a[0][6] = min(a[0][6], a[0][2] + a[2][6]); a[0][7] = min(a[0][7], a[0][2] + a[2][7]); a[0][8] = min(a[0][8], a[0][2] + a[2][8]); a[0][9] = min(a[0][9], a[0][2] + a[2][9]); a[1][0] = min(a[1][0], a[1][2] + a[2][0]); a[1][1] = min(a[1][1], a[1][2] + a[2][1]); a[1][2] = min(a[1][2], a[1][2] + a[2][2]); a[1][3] = min(a[1][3], a[1][2] + a[2][3]); a[1][4] = min(a[1][4], a[1][2] + a[2][4]); a[1][5] = min(a[1][5], a[1][2] + a[2][5]); a[1][6] = min(a[1][6], a[1][2] + a[2][6]); a[1][7] = min(a[1][7], a[1][2] + a[2][7]); a[1][8] = min(a[1][8], a[1][2] + a[2][8]); a[1][9] = min(a[1][9], a[1][2] + a[2][9]); a[2][0] = min(a[2][0], a[2][2] + a[2][0]); a[2][1] = min(a[2][1], a[2][2] + a[2][1]); a[2][2] = min(a[2][2], a[2][2] + a[2][2]); a[2][3] = min(a[2][3], a[2][2] + a[2][3]); a[2][4] = min(a[2][4], a[2][2] + a[2][4]); a[2][5] = min(a[2][5], a[2][2] + a[2][5]); a[2][6] = min(a[2][6], a[2][2] + a[2][6]); a[2][7] = min(a[2][7], a[2][2] + a[2][7]); a[2][8] = min(a[2][8], a[2][2] + a[2][8]); a[2][9] = min(a[2][9], a[2][2] + a[2][9]); a[3][0] = min(a[3][0], a[3][2] + a[2][0]); a[3][1] = min(a[3][1], a[3][2] + a[2][1]); a[3][2] = min(a[3][2], a[3][2] + a[2][2]); a[3][3] = min(a[3][3], a[3][2] + a[2][3]); a[3][4] = min(a[3][4], a[3][2] + a[2][4]); a[3][5] = min(a[3][5], a[3][2] + a[2][5]); a[3][6] = min(a[3][6], a[3][2] + a[2][6]); a[3][7] = min(a[3][7], a[3][2] + a[2][7]); a[3][8] = min(a[3][8], a[3][2] + a[2][8]); a[3][9] = min(a[3][9], a[3][2] + a[2][9]); a[4][0] = min(a[4][0], a[4][2] + a[2][0]); a[4][1] = min(a[4][1], a[4][2] + a[2][1]); a[4][2] = min(a[4][2], a[4][2] + a[2][2]); a[4][3] = min(a[4][3], a[4][2] + a[2][3]); a[4][4] = min(a[4][4], a[4][2] + a[2][4]); a[4][5] = min(a[4][5], a[4][2] + a[2][5]); a[4][6] = min(a[4][6], a[4][2] + a[2][6]); a[4][7] = min(a[4][7], a[4][2] + a[2][7]); a[4][8] = min(a[4][8], a[4][2] + a[2][8]); a[4][9] = min(a[4][9], a[4][2] + a[2][9]); a[5][0] = min(a[5][0], a[5][2] + a[2][0]); a[5][1] = min(a[5][1], a[5][2] + a[2][1]); a[5][2] = min(a[5][2], a[5][2] + a[2][2]); a[5][3] = min(a[5][3], a[5][2] + a[2][3]); a[5][4] = min(a[5][4], a[5][2] + a[2][4]); a[5][5] = min(a[5][5], a[5][2] + a[2][5]); a[5][6] = min(a[5][6], a[5][2] + a[2][6]); a[5][7] = min(a[5][7], a[5][2] + a[2][7]); a[5][8] = min(a[5][8], a[5][2] + a[2][8]); a[5][9] = min(a[5][9], a[5][2] + a[2][9]); a[6][0] = min(a[6][0], a[6][2] + a[2][0]); a[6][1] = min(a[6][1], a[6][2] + a[2][1]); a[6][2] = min(a[6][2], a[6][2] + a[2][2]); a[6][3] = min(a[6][3], a[6][2] + a[2][3]); a[6][4] = min(a[6][4], a[6][2] + a[2][4]); a[6][5] = min(a[6][5], a[6][2] + a[2][5]); a[6][6] = min(a[6][6], a[6][2] + a[2][6]); a[6][7] = min(a[6][7], a[6][2] + a[2][7]); a[6][8] = min(a[6][8], a[6][2] + a[2][8]); a[6][9] = min(a[6][9], a[6][2] + a[2][9]); a[7][0] = min(a[7][0], a[7][2] + a[2][0]); a[7][1] = min(a[7][1], a[7][2] + a[2][1]); a[7][2] = min(a[7][2], a[7][2] + a[2][2]); a[7][3] = min(a[7][3], a[7][2] + a[2][3]); a[7][4] = min(a[7][4], a[7][2] + a[2][4]); a[7][5] = min(a[7][5], a[7][2] + a[2][5]); a[7][6] = min(a[7][6], a[7][2] + a[2][6]); a[7][7] = min(a[7][7], a[7][2] + a[2][7]); a[7][8] = min(a[7][8], a[7][2] + a[2][8]); a[7][9] = min(a[7][9], a[7][2] + a[2][9]); a[8][0] = min(a[8][0], a[8][2] + a[2][0]); a[8][1] = min(a[8][1], a[8][2] + a[2][1]); a[8][2] = min(a[8][2], a[8][2] + a[2][2]); a[8][3] = min(a[8][3], a[8][2] + a[2][3]); a[8][4] = min(a[8][4], a[8][2] + a[2][4]); a[8][5] = min(a[8][5], a[8][2] + a[2][5]); a[8][6] = min(a[8][6], a[8][2] + a[2][6]); a[8][7] = min(a[8][7], a[8][2] + a[2][7]); a[8][8] = min(a[8][8], a[8][2] + a[2][8]); a[8][9] = min(a[8][9], a[8][2] + a[2][9]); a[9][0] = min(a[9][0], a[9][2] + a[2][0]); a[9][1] = min(a[9][1], a[9][2] + a[2][1]); a[9][2] = min(a[9][2], a[9][2] + a[2][2]); a[9][3] = min(a[9][3], a[9][2] + a[2][3]); a[9][4] = min(a[9][4], a[9][2] + a[2][4]); a[9][5] = min(a[9][5], a[9][2] + a[2][5]); a[9][6] = min(a[9][6], a[9][2] + a[2][6]); a[9][7] = min(a[9][7], a[9][2] + a[2][7]); a[9][8] = min(a[9][8], a[9][2] + a[2][8]); a[9][9] = min(a[9][9], a[9][2] + a[2][9]); a[0][0] = min(a[0][0], a[0][3] + a[3][0]); a[0][1] = min(a[0][1], a[0][3] + a[3][1]); a[0][2] = min(a[0][2], a[0][3] + a[3][2]); a[0][3] = min(a[0][3], a[0][3] + a[3][3]); a[0][4] = min(a[0][4], a[0][3] + a[3][4]); a[0][5] = min(a[0][5], a[0][3] + a[3][5]); a[0][6] = min(a[0][6], a[0][3] + a[3][6]); a[0][7] = min(a[0][7], a[0][3] + a[3][7]); a[0][8] = min(a[0][8], a[0][3] + a[3][8]); a[0][9] = min(a[0][9], a[0][3] + a[3][9]); a[1][0] = min(a[1][0], a[1][3] + a[3][0]); a[1][1] = min(a[1][1], a[1][3] + a[3][1]); a[1][2] = min(a[1][2], a[1][3] + a[3][2]); a[1][3] = min(a[1][3], a[1][3] + a[3][3]); a[1][4] = min(a[1][4], a[1][3] + a[3][4]); a[1][5] = min(a[1][5], a[1][3] + a[3][5]); a[1][6] = min(a[1][6], a[1][3] + a[3][6]); a[1][7] = min(a[1][7], a[1][3] + a[3][7]); a[1][8] = min(a[1][8], a[1][3] + a[3][8]); a[1][9] = min(a[1][9], a[1][3] + a[3][9]); a[2][0] = min(a[2][0], a[2][3] + a[3][0]); a[2][1] = min(a[2][1], a[2][3] + a[3][1]); a[2][2] = min(a[2][2], a[2][3] + a[3][2]); a[2][3] = min(a[2][3], a[2][3] + a[3][3]); a[2][4] = min(a[2][4], a[2][3] + a[3][4]); a[2][5] = min(a[2][5], a[2][3] + a[3][5]); a[2][6] = min(a[2][6], a[2][3] + a[3][6]); a[2][7] = min(a[2][7], a[2][3] + a[3][7]); a[2][8] = min(a[2][8], a[2][3] + a[3][8]); a[2][9] = min(a[2][9], a[2][3] + a[3][9]); a[3][0] = min(a[3][0], a[3][3] + a[3][0]); a[3][1] = min(a[3][1], a[3][3] + a[3][1]); a[3][2] = min(a[3][2], a[3][3] + a[3][2]); a[3][3] = min(a[3][3], a[3][3] + a[3][3]); a[3][4] = min(a[3][4], a[3][3] + a[3][4]); a[3][5] = min(a[3][5], a[3][3] + a[3][5]); a[3][6] = min(a[3][6], a[3][3] + a[3][6]); a[3][7] = min(a[3][7], a[3][3] + a[3][7]); a[3][8] = min(a[3][8], a[3][3] + a[3][8]); a[3][9] = min(a[3][9], a[3][3] + a[3][9]); a[4][0] = min(a[4][0], a[4][3] + a[3][0]); a[4][1] = min(a[4][1], a[4][3] + a[3][1]); a[4][2] = min(a[4][2], a[4][3] + a[3][2]); a[4][3] = min(a[4][3], a[4][3] + a[3][3]); a[4][4] = min(a[4][4], a[4][3] + a[3][4]); a[4][5] = min(a[4][5], a[4][3] + a[3][5]); a[4][6] = min(a[4][6], a[4][3] + a[3][6]); a[4][7] = min(a[4][7], a[4][3] + a[3][7]); a[4][8] = min(a[4][8], a[4][3] + a[3][8]); a[4][9] = min(a[4][9], a[4][3] + a[3][9]); a[5][0] = min(a[5][0], a[5][3] + a[3][0]); a[5][1] = min(a[5][1], a[5][3] + a[3][1]); a[5][2] = min(a[5][2], a[5][3] + a[3][2]); a[5][3] = min(a[5][3], a[5][3] + a[3][3]); a[5][4] = min(a[5][4], a[5][3] + a[3][4]); a[5][5] = min(a[5][5], a[5][3] + a[3][5]); a[5][6] = min(a[5][6], a[5][3] + a[3][6]); a[5][7] = min(a[5][7], a[5][3] + a[3][7]); a[5][8] = min(a[5][8], a[5][3] + a[3][8]); a[5][9] = min(a[5][9], a[5][3] + a[3][9]); a[6][0] = min(a[6][0], a[6][3] + a[3][0]); a[6][1] = min(a[6][1], a[6][3] + a[3][1]); a[6][2] = min(a[6][2], a[6][3] + a[3][2]); a[6][3] = min(a[6][3], a[6][3] + a[3][3]); a[6][4] = min(a[6][4], a[6][3] + a[3][4]); a[6][5] = min(a[6][5], a[6][3] + a[3][5]); a[6][6] = min(a[6][6], a[6][3] + a[3][6]); a[6][7] = min(a[6][7], a[6][3] + a[3][7]); a[6][8] = min(a[6][8], a[6][3] + a[3][8]); a[6][9] = min(a[6][9], a[6][3] + a[3][9]); a[7][0] = min(a[7][0], a[7][3] + a[3][0]); a[7][1] = min(a[7][1], a[7][3] + a[3][1]); a[7][2] = min(a[7][2], a[7][3] + a[3][2]); a[7][3] = min(a[7][3], a[7][3] + a[3][3]); a[7][4] = min(a[7][4], a[7][3] + a[3][4]); a[7][5] = min(a[7][5], a[7][3] + a[3][5]); a[7][6] = min(a[7][6], a[7][3] + a[3][6]); a[7][7] = min(a[7][7], a[7][3] + a[3][7]); a[7][8] = min(a[7][8], a[7][3] + a[3][8]); a[7][9] = min(a[7][9], a[7][3] + a[3][9]); a[8][0] = min(a[8][0], a[8][3] + a[3][0]); a[8][1] = min(a[8][1], a[8][3] + a[3][1]); a[8][2] = min(a[8][2], a[8][3] + a[3][2]); a[8][3] = min(a[8][3], a[8][3] + a[3][3]); a[8][4] = min(a[8][4], a[8][3] + a[3][4]); a[8][5] = min(a[8][5], a[8][3] + a[3][5]); a[8][6] = min(a[8][6], a[8][3] + a[3][6]); a[8][7] = min(a[8][7], a[8][3] + a[3][7]); a[8][8] = min(a[8][8], a[8][3] + a[3][8]); a[8][9] = min(a[8][9], a[8][3] + a[3][9]); a[9][0] = min(a[9][0], a[9][3] + a[3][0]); a[9][1] = min(a[9][1], a[9][3] + a[3][1]); a[9][2] = min(a[9][2], a[9][3] + a[3][2]); a[9][3] = min(a[9][3], a[9][3] + a[3][3]); a[9][4] = min(a[9][4], a[9][3] + a[3][4]); a[9][5] = min(a[9][5], a[9][3] + a[3][5]); a[9][6] = min(a[9][6], a[9][3] + a[3][6]); a[9][7] = min(a[9][7], a[9][3] + a[3][7]); a[9][8] = min(a[9][8], a[9][3] + a[3][8]); a[9][9] = min(a[9][9], a[9][3] + a[3][9]); a[0][0] = min(a[0][0], a[0][4] + a[4][0]); a[0][1] = min(a[0][1], a[0][4] + a[4][1]); a[0][2] = min(a[0][2], a[0][4] + a[4][2]); a[0][3] = min(a[0][3], a[0][4] + a[4][3]); a[0][4] = min(a[0][4], a[0][4] + a[4][4]); a[0][5] = min(a[0][5], a[0][4] + a[4][5]); a[0][6] = min(a[0][6], a[0][4] + a[4][6]); a[0][7] = min(a[0][7], a[0][4] + a[4][7]); a[0][8] = min(a[0][8], a[0][4] + a[4][8]); a[0][9] = min(a[0][9], a[0][4] + a[4][9]); a[1][0] = min(a[1][0], a[1][4] + a[4][0]); a[1][1] = min(a[1][1], a[1][4] + a[4][1]); a[1][2] = min(a[1][2], a[1][4] + a[4][2]); a[1][3] = min(a[1][3], a[1][4] + a[4][3]); a[1][4] = min(a[1][4], a[1][4] + a[4][4]); a[1][5] = min(a[1][5], a[1][4] + a[4][5]); a[1][6] = min(a[1][6], a[1][4] + a[4][6]); a[1][7] = min(a[1][7], a[1][4] + a[4][7]); a[1][8] = min(a[1][8], a[1][4] + a[4][8]); a[1][9] = min(a[1][9], a[1][4] + a[4][9]); a[2][0] = min(a[2][0], a[2][4] + a[4][0]); a[2][1] = min(a[2][1], a[2][4] + a[4][1]); a[2][2] = min(a[2][2], a[2][4] + a[4][2]); a[2][3] = min(a[2][3], a[2][4] + a[4][3]); a[2][4] = min(a[2][4], a[2][4] + a[4][4]); a[2][5] = min(a[2][5], a[2][4] + a[4][5]); a[2][6] = min(a[2][6], a[2][4] + a[4][6]); a[2][7] = min(a[2][7], a[2][4] + a[4][7]); a[2][8] = min(a[2][8], a[2][4] + a[4][8]); a[2][9] = min(a[2][9], a[2][4] + a[4][9]); a[3][0] = min(a[3][0], a[3][4] + a[4][0]); a[3][1] = min(a[3][1], a[3][4] + a[4][1]); a[3][2] = min(a[3][2], a[3][4] + a[4][2]); a[3][3] = min(a[3][3], a[3][4] + a[4][3]); a[3][4] = min(a[3][4], a[3][4] + a[4][4]); a[3][5] = min(a[3][5], a[3][4] + a[4][5]); a[3][6] = min(a[3][6], a[3][4] + a[4][6]); a[3][7] = min(a[3][7], a[3][4] + a[4][7]); a[3][8] = min(a[3][8], a[3][4] + a[4][8]); a[3][9] = min(a[3][9], a[3][4] + a[4][9]); a[4][0] = min(a[4][0], a[4][4] + a[4][0]); a[4][1] = min(a[4][1], a[4][4] + a[4][1]); a[4][2] = min(a[4][2], a[4][4] + a[4][2]); a[4][3] = min(a[4][3], a[4][4] + a[4][3]); a[4][4] = min(a[4][4], a[4][4] + a[4][4]); a[4][5] = min(a[4][5], a[4][4] + a[4][5]); a[4][6] = min(a[4][6], a[4][4] + a[4][6]); a[4][7] = min(a[4][7], a[4][4] + a[4][7]); a[4][8] = min(a[4][8], a[4][4] + a[4][8]); a[4][9] = min(a[4][9], a[4][4] + a[4][9]); a[5][0] = min(a[5][0], a[5][4] + a[4][0]); a[5][1] = min(a[5][1], a[5][4] + a[4][1]); a[5][2] = min(a[5][2], a[5][4] + a[4][2]); a[5][3] = min(a[5][3], a[5][4] + a[4][3]); a[5][4] = min(a[5][4], a[5][4] + a[4][4]); a[5][5] = min(a[5][5], a[5][4] + a[4][5]); a[5][6] = min(a[5][6], a[5][4] + a[4][6]); a[5][7] = min(a[5][7], a[5][4] + a[4][7]); a[5][8] = min(a[5][8], a[5][4] + a[4][8]); a[5][9] = min(a[5][9], a[5][4] + a[4][9]); a[6][0] = min(a[6][0], a[6][4] + a[4][0]); a[6][1] = min(a[6][1], a[6][4] + a[4][1]); a[6][2] = min(a[6][2], a[6][4] + a[4][2]); a[6][3] = min(a[6][3], a[6][4] + a[4][3]); a[6][4] = min(a[6][4], a[6][4] + a[4][4]); a[6][5] = min(a[6][5], a[6][4] + a[4][5]); a[6][6] = min(a[6][6], a[6][4] + a[4][6]); a[6][7] = min(a[6][7], a[6][4] + a[4][7]); a[6][8] = min(a[6][8], a[6][4] + a[4][8]); a[6][9] = min(a[6][9], a[6][4] + a[4][9]); a[7][0] = min(a[7][0], a[7][4] + a[4][0]); a[7][1] = min(a[7][1], a[7][4] + a[4][1]); a[7][2] = min(a[7][2], a[7][4] + a[4][2]); a[7][3] = min(a[7][3], a[7][4] + a[4][3]); a[7][4] = min(a[7][4], a[7][4] + a[4][4]); a[7][5] = min(a[7][5], a[7][4] + a[4][5]); a[7][6] = min(a[7][6], a[7][4] + a[4][6]); a[7][7] = min(a[7][7], a[7][4] + a[4][7]); a[7][8] = min(a[7][8], a[7][4] + a[4][8]); a[7][9] = min(a[7][9], a[7][4] + a[4][9]); a[8][0] = min(a[8][0], a[8][4] + a[4][0]); a[8][1] = min(a[8][1], a[8][4] + a[4][1]); a[8][2] = min(a[8][2], a[8][4] + a[4][2]); a[8][3] = min(a[8][3], a[8][4] + a[4][3]); a[8][4] = min(a[8][4], a[8][4] + a[4][4]); a[8][5] = min(a[8][5], a[8][4] + a[4][5]); a[8][6] = min(a[8][6], a[8][4] + a[4][6]); a[8][7] = min(a[8][7], a[8][4] + a[4][7]); a[8][8] = min(a[8][8], a[8][4] + a[4][8]); a[8][9] = min(a[8][9], a[8][4] + a[4][9]); a[9][0] = min(a[9][0], a[9][4] + a[4][0]); a[9][1] = min(a[9][1], a[9][4] + a[4][1]); a[9][2] = min(a[9][2], a[9][4] + a[4][2]); a[9][3] = min(a[9][3], a[9][4] + a[4][3]); a[9][4] = min(a[9][4], a[9][4] + a[4][4]); a[9][5] = min(a[9][5], a[9][4] + a[4][5]); a[9][6] = min(a[9][6], a[9][4] + a[4][6]); a[9][7] = min(a[9][7], a[9][4] + a[4][7]); a[9][8] = min(a[9][8], a[9][4] + a[4][8]); a[9][9] = min(a[9][9], a[9][4] + a[4][9]); a[0][0] = min(a[0][0], a[0][5] + a[5][0]); a[0][1] = min(a[0][1], a[0][5] + a[5][1]); a[0][2] = min(a[0][2], a[0][5] + a[5][2]); a[0][3] = min(a[0][3], a[0][5] + a[5][3]); a[0][4] = min(a[0][4], a[0][5] + a[5][4]); a[0][5] = min(a[0][5], a[0][5] + a[5][5]); a[0][6] = min(a[0][6], a[0][5] + a[5][6]); a[0][7] = min(a[0][7], a[0][5] + a[5][7]); a[0][8] = min(a[0][8], a[0][5] + a[5][8]); a[0][9] = min(a[0][9], a[0][5] + a[5][9]); a[1][0] = min(a[1][0], a[1][5] + a[5][0]); a[1][1] = min(a[1][1], a[1][5] + a[5][1]); a[1][2] = min(a[1][2], a[1][5] + a[5][2]); a[1][3] = min(a[1][3], a[1][5] + a[5][3]); a[1][4] = min(a[1][4], a[1][5] + a[5][4]); a[1][5] = min(a[1][5], a[1][5] + a[5][5]); a[1][6] = min(a[1][6], a[1][5] + a[5][6]); a[1][7] = min(a[1][7], a[1][5] + a[5][7]); a[1][8] = min(a[1][8], a[1][5] + a[5][8]); a[1][9] = min(a[1][9], a[1][5] + a[5][9]); a[2][0] = min(a[2][0], a[2][5] + a[5][0]); a[2][1] = min(a[2][1], a[2][5] + a[5][1]); a[2][2] = min(a[2][2], a[2][5] + a[5][2]); a[2][3] = min(a[2][3], a[2][5] + a[5][3]); a[2][4] = min(a[2][4], a[2][5] + a[5][4]); a[2][5] = min(a[2][5], a[2][5] + a[5][5]); a[2][6] = min(a[2][6], a[2][5] + a[5][6]); a[2][7] = min(a[2][7], a[2][5] + a[5][7]); a[2][8] = min(a[2][8], a[2][5] + a[5][8]); a[2][9] = min(a[2][9], a[2][5] + a[5][9]); a[3][0] = min(a[3][0], a[3][5] + a[5][0]); a[3][1] = min(a[3][1], a[3][5] + a[5][1]); a[3][2] = min(a[3][2], a[3][5] + a[5][2]); a[3][3] = min(a[3][3], a[3][5] + a[5][3]); a[3][4] = min(a[3][4], a[3][5] + a[5][4]); a[3][5] = min(a[3][5], a[3][5] + a[5][5]); a[3][6] = min(a[3][6], a[3][5] + a[5][6]); a[3][7] = min(a[3][7], a[3][5] + a[5][7]); a[3][8] = min(a[3][8], a[3][5] + a[5][8]); a[3][9] = min(a[3][9], a[3][5] + a[5][9]); a[4][0] = min(a[4][0], a[4][5] + a[5][0]); a[4][1] = min(a[4][1], a[4][5] + a[5][1]); a[4][2] = min(a[4][2], a[4][5] + a[5][2]); a[4][3] = min(a[4][3], a[4][5] + a[5][3]); a[4][4] = min(a[4][4], a[4][5] + a[5][4]); a[4][5] = min(a[4][5], a[4][5] + a[5][5]); a[4][6] = min(a[4][6], a[4][5] + a[5][6]); a[4][7] = min(a[4][7], a[4][5] + a[5][7]); a[4][8] = min(a[4][8], a[4][5] + a[5][8]); a[4][9] = min(a[4][9], a[4][5] + a[5][9]); a[5][0] = min(a[5][0], a[5][5] + a[5][0]); a[5][1] = min(a[5][1], a[5][5] + a[5][1]); a[5][2] = min(a[5][2], a[5][5] + a[5][2]); a[5][3] = min(a[5][3], a[5][5] + a[5][3]); a[5][4] = min(a[5][4], a[5][5] + a[5][4]); a[5][5] = min(a[5][5], a[5][5] + a[5][5]); a[5][6] = min(a[5][6], a[5][5] + a[5][6]); a[5][7] = min(a[5][7], a[5][5] + a[5][7]); a[5][8] = min(a[5][8], a[5][5] + a[5][8]); a[5][9] = min(a[5][9], a[5][5] + a[5][9]); a[6][0] = min(a[6][0], a[6][5] + a[5][0]); a[6][1] = min(a[6][1], a[6][5] + a[5][1]); a[6][2] = min(a[6][2], a[6][5] + a[5][2]); a[6][3] = min(a[6][3], a[6][5] + a[5][3]); a[6][4] = min(a[6][4], a[6][5] + a[5][4]); a[6][5] = min(a[6][5], a[6][5] + a[5][5]); a[6][6] = min(a[6][6], a[6][5] + a[5][6]); a[6][7] = min(a[6][7], a[6][5] + a[5][7]); a[6][8] = min(a[6][8], a[6][5] + a[5][8]); a[6][9] = min(a[6][9], a[6][5] + a[5][9]); a[7][0] = min(a[7][0], a[7][5] + a[5][0]); a[7][1] = min(a[7][1], a[7][5] + a[5][1]); a[7][2] = min(a[7][2], a[7][5] + a[5][2]); a[7][3] = min(a[7][3], a[7][5] + a[5][3]); a[7][4] = min(a[7][4], a[7][5] + a[5][4]); a[7][5] = min(a[7][5], a[7][5] + a[5][5]); a[7][6] = min(a[7][6], a[7][5] + a[5][6]); a[7][7] = min(a[7][7], a[7][5] + a[5][7]); a[7][8] = min(a[7][8], a[7][5] + a[5][8]); a[7][9] = min(a[7][9], a[7][5] + a[5][9]); a[8][0] = min(a[8][0], a[8][5] + a[5][0]); a[8][1] = min(a[8][1], a[8][5] + a[5][1]); a[8][2] = min(a[8][2], a[8][5] + a[5][2]); a[8][3] = min(a[8][3], a[8][5] + a[5][3]); a[8][4] = min(a[8][4], a[8][5] + a[5][4]); a[8][5] = min(a[8][5], a[8][5] + a[5][5]); a[8][6] = min(a[8][6], a[8][5] + a[5][6]); a[8][7] = min(a[8][7], a[8][5] + a[5][7]); a[8][8] = min(a[8][8], a[8][5] + a[5][8]); a[8][9] = min(a[8][9], a[8][5] + a[5][9]); a[9][0] = min(a[9][0], a[9][5] + a[5][0]); a[9][1] = min(a[9][1], a[9][5] + a[5][1]); a[9][2] = min(a[9][2], a[9][5] + a[5][2]); a[9][3] = min(a[9][3], a[9][5] + a[5][3]); a[9][4] = min(a[9][4], a[9][5] + a[5][4]); a[9][5] = min(a[9][5], a[9][5] + a[5][5]); a[9][6] = min(a[9][6], a[9][5] + a[5][6]); a[9][7] = min(a[9][7], a[9][5] + a[5][7]); a[9][8] = min(a[9][8], a[9][5] + a[5][8]); a[9][9] = min(a[9][9], a[9][5] + a[5][9]); a[0][0] = min(a[0][0], a[0][6] + a[6][0]); a[0][1] = min(a[0][1], a[0][6] + a[6][1]); a[0][2] = min(a[0][2], a[0][6] + a[6][2]); a[0][3] = min(a[0][3], a[0][6] + a[6][3]); a[0][4] = min(a[0][4], a[0][6] + a[6][4]); a[0][5] = min(a[0][5], a[0][6] + a[6][5]); a[0][6] = min(a[0][6], a[0][6] + a[6][6]); a[0][7] = min(a[0][7], a[0][6] + a[6][7]); a[0][8] = min(a[0][8], a[0][6] + a[6][8]); a[0][9] = min(a[0][9], a[0][6] + a[6][9]); a[1][0] = min(a[1][0], a[1][6] + a[6][0]); a[1][1] = min(a[1][1], a[1][6] + a[6][1]); a[1][2] = min(a[1][2], a[1][6] + a[6][2]); a[1][3] = min(a[1][3], a[1][6] + a[6][3]); a[1][4] = min(a[1][4], a[1][6] + a[6][4]); a[1][5] = min(a[1][5], a[1][6] + a[6][5]); a[1][6] = min(a[1][6], a[1][6] + a[6][6]); a[1][7] = min(a[1][7], a[1][6] + a[6][7]); a[1][8] = min(a[1][8], a[1][6] + a[6][8]); a[1][9] = min(a[1][9], a[1][6] + a[6][9]); a[2][0] = min(a[2][0], a[2][6] + a[6][0]); a[2][1] = min(a[2][1], a[2][6] + a[6][1]); a[2][2] = min(a[2][2], a[2][6] + a[6][2]); a[2][3] = min(a[2][3], a[2][6] + a[6][3]); a[2][4] = min(a[2][4], a[2][6] + a[6][4]); a[2][5] = min(a[2][5], a[2][6] + a[6][5]); a[2][6] = min(a[2][6], a[2][6] + a[6][6]); a[2][7] = min(a[2][7], a[2][6] + a[6][7]); a[2][8] = min(a[2][8], a[2][6] + a[6][8]); a[2][9] = min(a[2][9], a[2][6] + a[6][9]); a[3][0] = min(a[3][0], a[3][6] + a[6][0]); a[3][1] = min(a[3][1], a[3][6] + a[6][1]); a[3][2] = min(a[3][2], a[3][6] + a[6][2]); a[3][3] = min(a[3][3], a[3][6] + a[6][3]); a[3][4] = min(a[3][4], a[3][6] + a[6][4]); a[3][5] = min(a[3][5], a[3][6] + a[6][5]); a[3][6] = min(a[3][6], a[3][6] + a[6][6]); a[3][7] = min(a[3][7], a[3][6] + a[6][7]); a[3][8] = min(a[3][8], a[3][6] + a[6][8]); a[3][9] = min(a[3][9], a[3][6] + a[6][9]); a[4][0] = min(a[4][0], a[4][6] + a[6][0]); a[4][1] = min(a[4][1], a[4][6] + a[6][1]); a[4][2] = min(a[4][2], a[4][6] + a[6][2]); a[4][3] = min(a[4][3], a[4][6] + a[6][3]); a[4][4] = min(a[4][4], a[4][6] + a[6][4]); a[4][5] = min(a[4][5], a[4][6] + a[6][5]); a[4][6] = min(a[4][6], a[4][6] + a[6][6]); a[4][7] = min(a[4][7], a[4][6] + a[6][7]); a[4][8] = min(a[4][8], a[4][6] + a[6][8]); a[4][9] = min(a[4][9], a[4][6] + a[6][9]); a[5][0] = min(a[5][0], a[5][6] + a[6][0]); a[5][1] = min(a[5][1], a[5][6] + a[6][1]); a[5][2] = min(a[5][2], a[5][6] + a[6][2]); a[5][3] = min(a[5][3], a[5][6] + a[6][3]); a[5][4] = min(a[5][4], a[5][6] + a[6][4]); a[5][5] = min(a[5][5], a[5][6] + a[6][5]); a[5][6] = min(a[5][6], a[5][6] + a[6][6]); a[5][7] = min(a[5][7], a[5][6] + a[6][7]); a[5][8] = min(a[5][8], a[5][6] + a[6][8]); a[5][9] = min(a[5][9], a[5][6] + a[6][9]); a[6][0] = min(a[6][0], a[6][6] + a[6][0]); a[6][1] = min(a[6][1], a[6][6] + a[6][1]); a[6][2] = min(a[6][2], a[6][6] + a[6][2]); a[6][3] = min(a[6][3], a[6][6] + a[6][3]); a[6][4] = min(a[6][4], a[6][6] + a[6][4]); a[6][5] = min(a[6][5], a[6][6] + a[6][5]); a[6][6] = min(a[6][6], a[6][6] + a[6][6]); a[6][7] = min(a[6][7], a[6][6] + a[6][7]); a[6][8] = min(a[6][8], a[6][6] + a[6][8]); a[6][9] = min(a[6][9], a[6][6] + a[6][9]); a[7][0] = min(a[7][0], a[7][6] + a[6][0]); a[7][1] = min(a[7][1], a[7][6] + a[6][1]); a[7][2] = min(a[7][2], a[7][6] + a[6][2]); a[7][3] = min(a[7][3], a[7][6] + a[6][3]); a[7][4] = min(a[7][4], a[7][6] + a[6][4]); a[7][5] = min(a[7][5], a[7][6] + a[6][5]); a[7][6] = min(a[7][6], a[7][6] + a[6][6]); a[7][7] = min(a[7][7], a[7][6] + a[6][7]); a[7][8] = min(a[7][8], a[7][6] + a[6][8]); a[7][9] = min(a[7][9], a[7][6] + a[6][9]); a[8][0] = min(a[8][0], a[8][6] + a[6][0]); a[8][1] = min(a[8][1], a[8][6] + a[6][1]); a[8][2] = min(a[8][2], a[8][6] + a[6][2]); a[8][3] = min(a[8][3], a[8][6] + a[6][3]); a[8][4] = min(a[8][4], a[8][6] + a[6][4]); a[8][5] = min(a[8][5], a[8][6] + a[6][5]); a[8][6] = min(a[8][6], a[8][6] + a[6][6]); a[8][7] = min(a[8][7], a[8][6] + a[6][7]); a[8][8] = min(a[8][8], a[8][6] + a[6][8]); a[8][9] = min(a[8][9], a[8][6] + a[6][9]); a[9][0] = min(a[9][0], a[9][6] + a[6][0]); a[9][1] = min(a[9][1], a[9][6] + a[6][1]); a[9][2] = min(a[9][2], a[9][6] + a[6][2]); a[9][3] = min(a[9][3], a[9][6] + a[6][3]); a[9][4] = min(a[9][4], a[9][6] + a[6][4]); a[9][5] = min(a[9][5], a[9][6] + a[6][5]); a[9][6] = min(a[9][6], a[9][6] + a[6][6]); a[9][7] = min(a[9][7], a[9][6] + a[6][7]); a[9][8] = min(a[9][8], a[9][6] + a[6][8]); a[9][9] = min(a[9][9], a[9][6] + a[6][9]); a[0][0] = min(a[0][0], a[0][7] + a[7][0]); a[0][1] = min(a[0][1], a[0][7] + a[7][1]); a[0][2] = min(a[0][2], a[0][7] + a[7][2]); a[0][3] = min(a[0][3], a[0][7] + a[7][3]); a[0][4] = min(a[0][4], a[0][7] + a[7][4]); a[0][5] = min(a[0][5], a[0][7] + a[7][5]); a[0][6] = min(a[0][6], a[0][7] + a[7][6]); a[0][7] = min(a[0][7], a[0][7] + a[7][7]); a[0][8] = min(a[0][8], a[0][7] + a[7][8]); a[0][9] = min(a[0][9], a[0][7] + a[7][9]); a[1][0] = min(a[1][0], a[1][7] + a[7][0]); a[1][1] = min(a[1][1], a[1][7] + a[7][1]); a[1][2] = min(a[1][2], a[1][7] + a[7][2]); a[1][3] = min(a[1][3], a[1][7] + a[7][3]); a[1][4] = min(a[1][4], a[1][7] + a[7][4]); a[1][5] = min(a[1][5], a[1][7] + a[7][5]); a[1][6] = min(a[1][6], a[1][7] + a[7][6]); a[1][7] = min(a[1][7], a[1][7] + a[7][7]); a[1][8] = min(a[1][8], a[1][7] + a[7][8]); a[1][9] = min(a[1][9], a[1][7] + a[7][9]); a[2][0] = min(a[2][0], a[2][7] + a[7][0]); a[2][1] = min(a[2][1], a[2][7] + a[7][1]); a[2][2] = min(a[2][2], a[2][7] + a[7][2]); a[2][3] = min(a[2][3], a[2][7] + a[7][3]); a[2][4] = min(a[2][4], a[2][7] + a[7][4]); a[2][5] = min(a[2][5], a[2][7] + a[7][5]); a[2][6] = min(a[2][6], a[2][7] + a[7][6]); a[2][7] = min(a[2][7], a[2][7] + a[7][7]); a[2][8] = min(a[2][8], a[2][7] + a[7][8]); a[2][9] = min(a[2][9], a[2][7] + a[7][9]); a[3][0] = min(a[3][0], a[3][7] + a[7][0]); a[3][1] = min(a[3][1], a[3][7] + a[7][1]); a[3][2] = min(a[3][2], a[3][7] + a[7][2]); a[3][3] = min(a[3][3], a[3][7] + a[7][3]); a[3][4] = min(a[3][4], a[3][7] + a[7][4]); a[3][5] = min(a[3][5], a[3][7] + a[7][5]); a[3][6] = min(a[3][6], a[3][7] + a[7][6]); a[3][7] = min(a[3][7], a[3][7] + a[7][7]); a[3][8] = min(a[3][8], a[3][7] + a[7][8]); a[3][9] = min(a[3][9], a[3][7] + a[7][9]); a[4][0] = min(a[4][0], a[4][7] + a[7][0]); a[4][1] = min(a[4][1], a[4][7] + a[7][1]); a[4][2] = min(a[4][2], a[4][7] + a[7][2]); a[4][3] = min(a[4][3], a[4][7] + a[7][3]); a[4][4] = min(a[4][4], a[4][7] + a[7][4]); a[4][5] = min(a[4][5], a[4][7] + a[7][5]); a[4][6] = min(a[4][6], a[4][7] + a[7][6]); a[4][7] = min(a[4][7], a[4][7] + a[7][7]); a[4][8] = min(a[4][8], a[4][7] + a[7][8]); a[4][9] = min(a[4][9], a[4][7] + a[7][9]); a[5][0] = min(a[5][0], a[5][7] + a[7][0]); a[5][1] = min(a[5][1], a[5][7] + a[7][1]); a[5][2] = min(a[5][2], a[5][7] + a[7][2]); a[5][3] = min(a[5][3], a[5][7] + a[7][3]); a[5][4] = min(a[5][4], a[5][7] + a[7][4]); a[5][5] = min(a[5][5], a[5][7] + a[7][5]); a[5][6] = min(a[5][6], a[5][7] + a[7][6]); a[5][7] = min(a[5][7], a[5][7] + a[7][7]); a[5][8] = min(a[5][8], a[5][7] + a[7][8]); a[5][9] = min(a[5][9], a[5][7] + a[7][9]); a[6][0] = min(a[6][0], a[6][7] + a[7][0]); a[6][1] = min(a[6][1], a[6][7] + a[7][1]); a[6][2] = min(a[6][2], a[6][7] + a[7][2]); a[6][3] = min(a[6][3], a[6][7] + a[7][3]); a[6][4] = min(a[6][4], a[6][7] + a[7][4]); a[6][5] = min(a[6][5], a[6][7] + a[7][5]); a[6][6] = min(a[6][6], a[6][7] + a[7][6]); a[6][7] = min(a[6][7], a[6][7] + a[7][7]); a[6][8] = min(a[6][8], a[6][7] + a[7][8]); a[6][9] = min(a[6][9], a[6][7] + a[7][9]); a[7][0] = min(a[7][0], a[7][7] + a[7][0]); a[7][1] = min(a[7][1], a[7][7] + a[7][1]); a[7][2] = min(a[7][2], a[7][7] + a[7][2]); a[7][3] = min(a[7][3], a[7][7] + a[7][3]); a[7][4] = min(a[7][4], a[7][7] + a[7][4]); a[7][5] = min(a[7][5], a[7][7] + a[7][5]); a[7][6] = min(a[7][6], a[7][7] + a[7][6]); a[7][7] = min(a[7][7], a[7][7] + a[7][7]); a[7][8] = min(a[7][8], a[7][7] + a[7][8]); a[7][9] = min(a[7][9], a[7][7] + a[7][9]); a[8][0] = min(a[8][0], a[8][7] + a[7][0]); a[8][1] = min(a[8][1], a[8][7] + a[7][1]); a[8][2] = min(a[8][2], a[8][7] + a[7][2]); a[8][3] = min(a[8][3], a[8][7] + a[7][3]); a[8][4] = min(a[8][4], a[8][7] + a[7][4]); a[8][5] = min(a[8][5], a[8][7] + a[7][5]); a[8][6] = min(a[8][6], a[8][7] + a[7][6]); a[8][7] = min(a[8][7], a[8][7] + a[7][7]); a[8][8] = min(a[8][8], a[8][7] + a[7][8]); a[8][9] = min(a[8][9], a[8][7] + a[7][9]); a[9][0] = min(a[9][0], a[9][7] + a[7][0]); a[9][1] = min(a[9][1], a[9][7] + a[7][1]); a[9][2] = min(a[9][2], a[9][7] + a[7][2]); a[9][3] = min(a[9][3], a[9][7] + a[7][3]); a[9][4] = min(a[9][4], a[9][7] + a[7][4]); a[9][5] = min(a[9][5], a[9][7] + a[7][5]); a[9][6] = min(a[9][6], a[9][7] + a[7][6]); a[9][7] = min(a[9][7], a[9][7] + a[7][7]); a[9][8] = min(a[9][8], a[9][7] + a[7][8]); a[9][9] = min(a[9][9], a[9][7] + a[7][9]); a[0][0] = min(a[0][0], a[0][8] + a[8][0]); a[0][1] = min(a[0][1], a[0][8] + a[8][1]); a[0][2] = min(a[0][2], a[0][8] + a[8][2]); a[0][3] = min(a[0][3], a[0][8] + a[8][3]); a[0][4] = min(a[0][4], a[0][8] + a[8][4]); a[0][5] = min(a[0][5], a[0][8] + a[8][5]); a[0][6] = min(a[0][6], a[0][8] + a[8][6]); a[0][7] = min(a[0][7], a[0][8] + a[8][7]); a[0][8] = min(a[0][8], a[0][8] + a[8][8]); a[0][9] = min(a[0][9], a[0][8] + a[8][9]); a[1][0] = min(a[1][0], a[1][8] + a[8][0]); a[1][1] = min(a[1][1], a[1][8] + a[8][1]); a[1][2] = min(a[1][2], a[1][8] + a[8][2]); a[1][3] = min(a[1][3], a[1][8] + a[8][3]); a[1][4] = min(a[1][4], a[1][8] + a[8][4]); a[1][5] = min(a[1][5], a[1][8] + a[8][5]); a[1][6] = min(a[1][6], a[1][8] + a[8][6]); a[1][7] = min(a[1][7], a[1][8] + a[8][7]); a[1][8] = min(a[1][8], a[1][8] + a[8][8]); a[1][9] = min(a[1][9], a[1][8] + a[8][9]); a[2][0] = min(a[2][0], a[2][8] + a[8][0]); a[2][1] = min(a[2][1], a[2][8] + a[8][1]); a[2][2] = min(a[2][2], a[2][8] + a[8][2]); a[2][3] = min(a[2][3], a[2][8] + a[8][3]); a[2][4] = min(a[2][4], a[2][8] + a[8][4]); a[2][5] = min(a[2][5], a[2][8] + a[8][5]); a[2][6] = min(a[2][6], a[2][8] + a[8][6]); a[2][7] = min(a[2][7], a[2][8] + a[8][7]); a[2][8] = min(a[2][8], a[2][8] + a[8][8]); a[2][9] = min(a[2][9], a[2][8] + a[8][9]); a[3][0] = min(a[3][0], a[3][8] + a[8][0]); a[3][1] = min(a[3][1], a[3][8] + a[8][1]); a[3][2] = min(a[3][2], a[3][8] + a[8][2]); a[3][3] = min(a[3][3], a[3][8] + a[8][3]); a[3][4] = min(a[3][4], a[3][8] + a[8][4]); a[3][5] = min(a[3][5], a[3][8] + a[8][5]); a[3][6] = min(a[3][6], a[3][8] + a[8][6]); a[3][7] = min(a[3][7], a[3][8] + a[8][7]); a[3][8] = min(a[3][8], a[3][8] + a[8][8]); a[3][9] = min(a[3][9], a[3][8] + a[8][9]); a[4][0] = min(a[4][0], a[4][8] + a[8][0]); a[4][1] = min(a[4][1], a[4][8] + a[8][1]); a[4][2] = min(a[4][2], a[4][8] + a[8][2]); a[4][3] = min(a[4][3], a[4][8] + a[8][3]); a[4][4] = min(a[4][4], a[4][8] + a[8][4]); a[4][5] = min(a[4][5], a[4][8] + a[8][5]); a[4][6] = min(a[4][6], a[4][8] + a[8][6]); a[4][7] = min(a[4][7], a[4][8] + a[8][7]); a[4][8] = min(a[4][8], a[4][8] + a[8][8]); a[4][9] = min(a[4][9], a[4][8] + a[8][9]); a[5][0] = min(a[5][0], a[5][8] + a[8][0]); a[5][1] = min(a[5][1], a[5][8] + a[8][1]); a[5][2] = min(a[5][2], a[5][8] + a[8][2]); a[5][3] = min(a[5][3], a[5][8] + a[8][3]); a[5][4] = min(a[5][4], a[5][8] + a[8][4]); a[5][5] = min(a[5][5], a[5][8] + a[8][5]); a[5][6] = min(a[5][6], a[5][8] + a[8][6]); a[5][7] = min(a[5][7], a[5][8] + a[8][7]); a[5][8] = min(a[5][8], a[5][8] + a[8][8]); a[5][9] = min(a[5][9], a[5][8] + a[8][9]); a[6][0] = min(a[6][0], a[6][8] + a[8][0]); a[6][1] = min(a[6][1], a[6][8] + a[8][1]); a[6][2] = min(a[6][2], a[6][8] + a[8][2]); a[6][3] = min(a[6][3], a[6][8] + a[8][3]); a[6][4] = min(a[6][4], a[6][8] + a[8][4]); a[6][5] = min(a[6][5], a[6][8] + a[8][5]); a[6][6] = min(a[6][6], a[6][8] + a[8][6]); a[6][7] = min(a[6][7], a[6][8] + a[8][7]); a[6][8] = min(a[6][8], a[6][8] + a[8][8]); a[6][9] = min(a[6][9], a[6][8] + a[8][9]); a[7][0] = min(a[7][0], a[7][8] + a[8][0]); a[7][1] = min(a[7][1], a[7][8] + a[8][1]); a[7][2] = min(a[7][2], a[7][8] + a[8][2]); a[7][3] = min(a[7][3], a[7][8] + a[8][3]); a[7][4] = min(a[7][4], a[7][8] + a[8][4]); a[7][5] = min(a[7][5], a[7][8] + a[8][5]); a[7][6] = min(a[7][6], a[7][8] + a[8][6]); a[7][7] = min(a[7][7], a[7][8] + a[8][7]); a[7][8] = min(a[7][8], a[7][8] + a[8][8]); a[7][9] = min(a[7][9], a[7][8] + a[8][9]); a[8][0] = min(a[8][0], a[8][8] + a[8][0]); a[8][1] = min(a[8][1], a[8][8] + a[8][1]); a[8][2] = min(a[8][2], a[8][8] + a[8][2]); a[8][3] = min(a[8][3], a[8][8] + a[8][3]); a[8][4] = min(a[8][4], a[8][8] + a[8][4]); a[8][5] = min(a[8][5], a[8][8] + a[8][5]); a[8][6] = min(a[8][6], a[8][8] + a[8][6]); a[8][7] = min(a[8][7], a[8][8] + a[8][7]); a[8][8] = min(a[8][8], a[8][8] + a[8][8]); a[8][9] = min(a[8][9], a[8][8] + a[8][9]); a[9][0] = min(a[9][0], a[9][8] + a[8][0]); a[9][1] = min(a[9][1], a[9][8] + a[8][1]); a[9][2] = min(a[9][2], a[9][8] + a[8][2]); a[9][3] = min(a[9][3], a[9][8] + a[8][3]); a[9][4] = min(a[9][4], a[9][8] + a[8][4]); a[9][5] = min(a[9][5], a[9][8] + a[8][5]); a[9][6] = min(a[9][6], a[9][8] + a[8][6]); a[9][7] = min(a[9][7], a[9][8] + a[8][7]); a[9][8] = min(a[9][8], a[9][8] + a[8][8]); a[9][9] = min(a[9][9], a[9][8] + a[8][9]); a[0][0] = min(a[0][0], a[0][9] + a[9][0]); a[0][1] = min(a[0][1], a[0][9] + a[9][1]); a[0][2] = min(a[0][2], a[0][9] + a[9][2]); a[0][3] = min(a[0][3], a[0][9] + a[9][3]); a[0][4] = min(a[0][4], a[0][9] + a[9][4]); a[0][5] = min(a[0][5], a[0][9] + a[9][5]); a[0][6] = min(a[0][6], a[0][9] + a[9][6]); a[0][7] = min(a[0][7], a[0][9] + a[9][7]); a[0][8] = min(a[0][8], a[0][9] + a[9][8]); a[0][9] = min(a[0][9], a[0][9] + a[9][9]); a[1][0] = min(a[1][0], a[1][9] + a[9][0]); a[1][1] = min(a[1][1], a[1][9] + a[9][1]); a[1][2] = min(a[1][2], a[1][9] + a[9][2]); a[1][3] = min(a[1][3], a[1][9] + a[9][3]); a[1][4] = min(a[1][4], a[1][9] + a[9][4]); a[1][5] = min(a[1][5], a[1][9] + a[9][5]); a[1][6] = min(a[1][6], a[1][9] + a[9][6]); a[1][7] = min(a[1][7], a[1][9] + a[9][7]); a[1][8] = min(a[1][8], a[1][9] + a[9][8]); a[1][9] = min(a[1][9], a[1][9] + a[9][9]); a[2][0] = min(a[2][0], a[2][9] + a[9][0]); a[2][1] = min(a[2][1], a[2][9] + a[9][1]); a[2][2] = min(a[2][2], a[2][9] + a[9][2]); a[2][3] = min(a[2][3], a[2][9] + a[9][3]); a[2][4] = min(a[2][4], a[2][9] + a[9][4]); a[2][5] = min(a[2][5], a[2][9] + a[9][5]); a[2][6] = min(a[2][6], a[2][9] + a[9][6]); a[2][7] = min(a[2][7], a[2][9] + a[9][7]); a[2][8] = min(a[2][8], a[2][9] + a[9][8]); a[2][9] = min(a[2][9], a[2][9] + a[9][9]); a[3][0] = min(a[3][0], a[3][9] + a[9][0]); a[3][1] = min(a[3][1], a[3][9] + a[9][1]); a[3][2] = min(a[3][2], a[3][9] + a[9][2]); a[3][3] = min(a[3][3], a[3][9] + a[9][3]); a[3][4] = min(a[3][4], a[3][9] + a[9][4]); a[3][5] = min(a[3][5], a[3][9] + a[9][5]); a[3][6] = min(a[3][6], a[3][9] + a[9][6]); a[3][7] = min(a[3][7], a[3][9] + a[9][7]); a[3][8] = min(a[3][8], a[3][9] + a[9][8]); a[3][9] = min(a[3][9], a[3][9] + a[9][9]); a[4][0] = min(a[4][0], a[4][9] + a[9][0]); a[4][1] = min(a[4][1], a[4][9] + a[9][1]); a[4][2] = min(a[4][2], a[4][9] + a[9][2]); a[4][3] = min(a[4][3], a[4][9] + a[9][3]); a[4][4] = min(a[4][4], a[4][9] + a[9][4]); a[4][5] = min(a[4][5], a[4][9] + a[9][5]); a[4][6] = min(a[4][6], a[4][9] + a[9][6]); a[4][7] = min(a[4][7], a[4][9] + a[9][7]); a[4][8] = min(a[4][8], a[4][9] + a[9][8]); a[4][9] = min(a[4][9], a[4][9] + a[9][9]); a[5][0] = min(a[5][0], a[5][9] + a[9][0]); a[5][1] = min(a[5][1], a[5][9] + a[9][1]); a[5][2] = min(a[5][2], a[5][9] + a[9][2]); a[5][3] = min(a[5][3], a[5][9] + a[9][3]); a[5][4] = min(a[5][4], a[5][9] + a[9][4]); a[5][5] = min(a[5][5], a[5][9] + a[9][5]); a[5][6] = min(a[5][6], a[5][9] + a[9][6]); a[5][7] = min(a[5][7], a[5][9] + a[9][7]); a[5][8] = min(a[5][8], a[5][9] + a[9][8]); a[5][9] = min(a[5][9], a[5][9] + a[9][9]); a[6][0] = min(a[6][0], a[6][9] + a[9][0]); a[6][1] = min(a[6][1], a[6][9] + a[9][1]); a[6][2] = min(a[6][2], a[6][9] + a[9][2]); a[6][3] = min(a[6][3], a[6][9] + a[9][3]); a[6][4] = min(a[6][4], a[6][9] + a[9][4]); a[6][5] = min(a[6][5], a[6][9] + a[9][5]); a[6][6] = min(a[6][6], a[6][9] + a[9][6]); a[6][7] = min(a[6][7], a[6][9] + a[9][7]); a[6][8] = min(a[6][8], a[6][9] + a[9][8]); a[6][9] = min(a[6][9], a[6][9] + a[9][9]); a[7][0] = min(a[7][0], a[7][9] + a[9][0]); a[7][1] = min(a[7][1], a[7][9] + a[9][1]); a[7][2] = min(a[7][2], a[7][9] + a[9][2]); a[7][3] = min(a[7][3], a[7][9] + a[9][3]); a[7][4] = min(a[7][4], a[7][9] + a[9][4]); a[7][5] = min(a[7][5], a[7][9] + a[9][5]); a[7][6] = min(a[7][6], a[7][9] + a[9][6]); a[7][7] = min(a[7][7], a[7][9] + a[9][7]); a[7][8] = min(a[7][8], a[7][9] + a[9][8]); a[7][9] = min(a[7][9], a[7][9] + a[9][9]); a[8][0] = min(a[8][0], a[8][9] + a[9][0]); a[8][1] = min(a[8][1], a[8][9] + a[9][1]); a[8][2] = min(a[8][2], a[8][9] + a[9][2]); a[8][3] = min(a[8][3], a[8][9] + a[9][3]); a[8][4] = min(a[8][4], a[8][9] + a[9][4]); a[8][5] = min(a[8][5], a[8][9] + a[9][5]); a[8][6] = min(a[8][6], a[8][9] + a[9][6]); a[8][7] = min(a[8][7], a[8][9] + a[9][7]); a[8][8] = min(a[8][8], a[8][9] + a[9][8]); a[8][9] = min(a[8][9], a[8][9] + a[9][9]); a[9][0] = min(a[9][0], a[9][9] + a[9][0]); a[9][1] = min(a[9][1], a[9][9] + a[9][1]); a[9][2] = min(a[9][2], a[9][9] + a[9][2]); a[9][3] = min(a[9][3], a[9][9] + a[9][3]); a[9][4] = min(a[9][4], a[9][9] + a[9][4]); a[9][5] = min(a[9][5], a[9][9] + a[9][5]); a[9][6] = min(a[9][6], a[9][9] + a[9][6]); a[9][7] = min(a[9][7], a[9][9] + a[9][7]); a[9][8] = min(a[9][8], a[9][9] + a[9][8]); a[9][9] = min(a[9][9], a[9][9] + a[9][9]); int ans = 0; ans = (0 < n && 0 < n ? max(ans, a[0][0]) : ans); ans = (0 < n && 1 < n ? max(ans, a[0][1]) : ans); ans = (0 < n && 2 < n ? max(ans, a[0][2]) : ans); ans = (0 < n && 3 < n ? max(ans, a[0][3]) : ans); ans = (0 < n && 4 < n ? max(ans, a[0][4]) : ans); ans = (0 < n && 5 < n ? max(ans, a[0][5]) : ans); ans = (0 < n && 6 < n ? max(ans, a[0][6]) : ans); ans = (0 < n && 7 < n ? max(ans, a[0][7]) : ans); ans = (0 < n && 8 < n ? max(ans, a[0][8]) : ans); ans = (0 < n && 9 < n ? max(ans, a[0][9]) : ans); ans = (1 < n && 0 < n ? max(ans, a[1][0]) : ans); ans = (1 < n && 1 < n ? max(ans, a[1][1]) : ans); ans = (1 < n && 2 < n ? max(ans, a[1][2]) : ans); ans = (1 < n && 3 < n ? max(ans, a[1][3]) : ans); ans = (1 < n && 4 < n ? max(ans, a[1][4]) : ans); ans = (1 < n && 5 < n ? max(ans, a[1][5]) : ans); ans = (1 < n && 6 < n ? max(ans, a[1][6]) : ans); ans = (1 < n && 7 < n ? max(ans, a[1][7]) : ans); ans = (1 < n && 8 < n ? max(ans, a[1][8]) : ans); ans = (1 < n && 9 < n ? max(ans, a[1][9]) : ans); ans = (2 < n && 0 < n ? max(ans, a[2][0]) : ans); ans = (2 < n && 1 < n ? max(ans, a[2][1]) : ans); ans = (2 < n && 2 < n ? max(ans, a[2][2]) : ans); ans = (2 < n && 3 < n ? max(ans, a[2][3]) : ans); ans = (2 < n && 4 < n ? max(ans, a[2][4]) : ans); ans = (2 < n && 5 < n ? max(ans, a[2][5]) : ans); ans = (2 < n && 6 < n ? max(ans, a[2][6]) : ans); ans = (2 < n && 7 < n ? max(ans, a[2][7]) : ans); ans = (2 < n && 8 < n ? max(ans, a[2][8]) : ans); ans = (2 < n && 9 < n ? max(ans, a[2][9]) : ans); ans = (3 < n && 0 < n ? max(ans, a[3][0]) : ans); ans = (3 < n && 1 < n ? max(ans, a[3][1]) : ans); ans = (3 < n && 2 < n ? max(ans, a[3][2]) : ans); ans = (3 < n && 3 < n ? max(ans, a[3][3]) : ans); ans = (3 < n && 4 < n ? max(ans, a[3][4]) : ans); ans = (3 < n && 5 < n ? max(ans, a[3][5]) : ans); ans = (3 < n && 6 < n ? max(ans, a[3][6]) : ans); ans = (3 < n && 7 < n ? max(ans, a[3][7]) : ans); ans = (3 < n && 8 < n ? max(ans, a[3][8]) : ans); ans = (3 < n && 9 < n ? max(ans, a[3][9]) : ans); ans = (4 < n && 0 < n ? max(ans, a[4][0]) : ans); ans = (4 < n && 1 < n ? max(ans, a[4][1]) : ans); ans = (4 < n && 2 < n ? max(ans, a[4][2]) : ans); ans = (4 < n && 3 < n ? max(ans, a[4][3]) : ans); ans = (4 < n && 4 < n ? max(ans, a[4][4]) : ans); ans = (4 < n && 5 < n ? max(ans, a[4][5]) : ans); ans = (4 < n && 6 < n ? max(ans, a[4][6]) : ans); ans = (4 < n && 7 < n ? max(ans, a[4][7]) : ans); ans = (4 < n && 8 < n ? max(ans, a[4][8]) : ans); ans = (4 < n && 9 < n ? max(ans, a[4][9]) : ans); ans = (5 < n && 0 < n ? max(ans, a[5][0]) : ans); ans = (5 < n && 1 < n ? max(ans, a[5][1]) : ans); ans = (5 < n && 2 < n ? max(ans, a[5][2]) : ans); ans = (5 < n && 3 < n ? max(ans, a[5][3]) : ans); ans = (5 < n && 4 < n ? max(ans, a[5][4]) : ans); ans = (5 < n && 5 < n ? max(ans, a[5][5]) : ans); ans = (5 < n && 6 < n ? max(ans, a[5][6]) : ans); ans = (5 < n && 7 < n ? max(ans, a[5][7]) : ans); ans = (5 < n && 8 < n ? max(ans, a[5][8]) : ans); ans = (5 < n && 9 < n ? max(ans, a[5][9]) : ans); ans = (6 < n && 0 < n ? max(ans, a[6][0]) : ans); ans = (6 < n && 1 < n ? max(ans, a[6][1]) : ans); ans = (6 < n && 2 < n ? max(ans, a[6][2]) : ans); ans = (6 < n && 3 < n ? max(ans, a[6][3]) : ans); ans = (6 < n && 4 < n ? max(ans, a[6][4]) : ans); ans = (6 < n && 5 < n ? max(ans, a[6][5]) : ans); ans = (6 < n && 6 < n ? max(ans, a[6][6]) : ans); ans = (6 < n && 7 < n ? max(ans, a[6][7]) : ans); ans = (6 < n && 8 < n ? max(ans, a[6][8]) : ans); ans = (6 < n && 9 < n ? max(ans, a[6][9]) : ans); ans = (7 < n && 0 < n ? max(ans, a[7][0]) : ans); ans = (7 < n && 1 < n ? max(ans, a[7][1]) : ans); ans = (7 < n && 2 < n ? max(ans, a[7][2]) : ans); ans = (7 < n && 3 < n ? max(ans, a[7][3]) : ans); ans = (7 < n && 4 < n ? max(ans, a[7][4]) : ans); ans = (7 < n && 5 < n ? max(ans, a[7][5]) : ans); ans = (7 < n && 6 < n ? max(ans, a[7][6]) : ans); ans = (7 < n && 7 < n ? max(ans, a[7][7]) : ans); ans = (7 < n && 8 < n ? max(ans, a[7][8]) : ans); ans = (7 < n && 9 < n ? max(ans, a[7][9]) : ans); ans = (8 < n && 0 < n ? max(ans, a[8][0]) : ans); ans = (8 < n && 1 < n ? max(ans, a[8][1]) : ans); ans = (8 < n && 2 < n ? max(ans, a[8][2]) : ans); ans = (8 < n && 3 < n ? max(ans, a[8][3]) : ans); ans = (8 < n && 4 < n ? max(ans, a[8][4]) : ans); ans = (8 < n && 5 < n ? max(ans, a[8][5]) : ans); ans = (8 < n && 6 < n ? max(ans, a[8][6]) : ans); ans = (8 < n && 7 < n ? max(ans, a[8][7]) : ans); ans = (8 < n && 8 < n ? max(ans, a[8][8]) : ans); ans = (8 < n && 9 < n ? max(ans, a[8][9]) : ans); ans = (9 < n && 0 < n ? max(ans, a[9][0]) : ans); ans = (9 < n && 1 < n ? max(ans, a[9][1]) : ans); ans = (9 < n && 2 < n ? max(ans, a[9][2]) : ans); ans = (9 < n && 3 < n ? max(ans, a[9][3]) : ans); ans = (9 < n && 4 < n ? max(ans, a[9][4]) : ans); ans = (9 < n && 5 < n ? max(ans, a[9][5]) : ans); ans = (9 < n && 6 < n ? max(ans, a[9][6]) : ans); ans = (9 < n && 7 < n ? max(ans, a[9][7]) : ans); ans = (9 < n && 8 < n ? max(ans, a[9][8]) : ans); ans = (9 < n && 9 < n ? max(ans, a[9][9]) : ans); cout << ans; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 11:02:56
// Design Name:
// Module Name: lab5_2_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab5_2_1(
input [1:0] ain,
input clk,reset,
output reg yout
);
reg [2:0] state,nextstate;
parameter S0 = 0,S1 = 1,S2 = 2,S3 = 3,S4 = 4,S5 = 5,S6 = 6;
always @(posedge clk or posedge reset)
if(reset)
begin
state <= S0;
yout <= 0;
end
else
state <= nextstate;
always @(state)
begin
case(state)
S0:yout = yout;
S1:yout = yout;
S2:yout = yout;
S3:yout = yout;
S4:yout = 0;
S5:yout = 1;
S6:yout = ~yout;
endcase
end
always @(state or ain)
begin
case(state)
S0:
begin
if(ain == 0)
nextstate = S0;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S1:
begin
if(ain == 0)
nextstate = S4;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S2:
begin
if(ain == 0)
nextstate = S5;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S3:
begin
if(ain == 0)
nextstate = S6;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S4:
begin
if(ain == 0)
nextstate = S0;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S5:
begin
if(ain == 0)
nextstate = S0;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
S6:
begin
if(ain == 0)
nextstate = S0;
else if(ain == 1)
nextstate = S1;
else if(ain == 3)
nextstate = S2;
else
nextstate = S3;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int T = clock(); long long int a, ta, b, tb; cin >> a >> ta >> b >> tb; string s; cin >> s; long long int i = 5 * 60, lim = 23 * 60 + 59; long long int st = stoi(s.substr(0, 2)) * 60 + stoi(s.substr(3)); long long int ed = st + ta; long long int ans = 0; while (i < ed && i <= lim) { if (i + tb > st) ans++; i += b; } cout << ans; cerr << n nTIME: << (long double)(clock() - T) / CLOCKS_PER_SEC << sec n ; T = clock(); return 0; }
|
#include <bits/stdc++.h> int num[10000]; int map[2000][2000]; int add(int a, int b, int c) { map[a][b] = 1, map[b][a] = 1; } int vis[2000][2]; int main() { int n; while (scanf( %d , &n) != EOF) { memset(map, 0, sizeof(map)); memset(vis, 0, sizeof(vis)); int i, j; int len = 0; int ans = 0; memset(map, 0, sizeof(map)); memset(num, 0, sizeof(num)); for (i = 0; i <= 30; i++) { if (n & (1 << i)) { num[i]++; len = i; } } int index = 3; for (i = 0; i <= 30; i++) { if (i != len) continue; int x, y; if (i == 0) { add(1, 2, 1); index = 3; continue; } for (j = 1; j <= i; j++) { if (j == 1) { add(1, index++, 3); add(1, index++, 4); x = index - 1; y = index - 2; } else { add(x, index, 5); index++; add(y, index, 6); index++; add(x, index - 1, 7); add(y, index - 2, 8); x = index - 1; y = index - 2; } vis[j][0] = x; vis[j][1] = y; } if (i == len) { add(x, 2, 1); add(y, 2, 1); continue; } } for (i = 0; i <= 30; i++) { if (num[i] && i != len) { int x = 1; for (j = 1; j <= len - i; j++) { add(x, index++, 1); x = index - 1; } if (i == 0) { add(x, 2, 1); continue; } add(x, vis[len - i + 1][0], 1); add(x, vis[len - i + 1][1], 1); } } printf( %d n , index - 1); for (i = 1; i < index; i++) { for (j = 1; j < index; j++) { if (map[i][j] == 1) printf( Y ); else printf( N ); } printf( n ); } } return 0; }
|
`timescale 1ns/1ns
`include "aluop_def.v"
module ShiftRight(
input signed [31:0] inp,
input [4:0] shamt,
input isSrl,
output [31:0] out
);
assign out = (isSrl)? $signed(inp>>shamt):
(inp>>>shamt);
endmodule
module alu (a,b,op,c,over);
input [31:0] a,b;
input [3:0] op;
output [31:0] c;
output over;
wire [31:0] tmp,slt_result;
wire [31:0] sr_result;
wire [32:0] sltu_result;
ShiftRight sr(b,a[4:0],op==`ALU_SRL,sr_result);
assign tmp=((op==`ALU_SUB)?~b+1:b);
assign slt_result=a-b;
assign sltu_result={1'b0,a}-{1'b0,b};
assign c=(op==`ALU_ADD)?a+b:
(op==`ALU_SUB)?a-b:
(op==`ALU_OR)?a|b:
(op==`ALU_AND)?a & b:
(op==`ALU_XOR)?a ^ b:
(op==`ALU_NOR)?~(a|b):
(op==`ALU_SLL)?b<<a[4:0]:
(op==`ALU_SRL||op==`ALU_SRA)?sr_result:
(op==`ALU_SLT)?{31'd0,slt_result[31]}:
(op==`ALU_SLTU)?{31'd0,sltu_result[32]}:
32'hBBAACCDD;//for debug
assign over=((op==`ALU_ADD || op==`ALU_SUB) &&
a[31]==tmp[31] && tmp[31]==~c[31]);
endmodule
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); if (n % 2 == 0) printf( Mahmoud ); else printf( Ehab ); }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll MOD = 1e9 + 7, N = 1e5 + 10; void test() { string s; cin >> s; vector<ll> cnt(26); for (auto c : s) { cnt[c - a ]++; } ll m; cin >> m; vector<ll> b(m); for (ll i = 0; i < m; i++) { cin >> b[i]; } ll n = s.length(); vector<ll> done(m); string res(m, . ); ll up = 25; for (ll i = 0; i < m; i++) { ll mx = 1e9; for (ll j = 0; j < m; j++) { if (done[j]) continue; mx = min(mx, b[j]); } if (mx == 1e9) break; vector<ll> pos; for (ll j = 0; j < m; j++) { if (done[j]) continue; if (mx == b[j]) { pos.push_back(j); } } ll v; for (ll j = up; j >= 0; --j) { if (cnt[j] >= pos.size()) { v = j; break; } } up = v - 1; for (auto &e : pos) { res[e] = char(v + a ); } for (auto &e : pos) { for (ll j = 0; j < m; j++) { if (!done[j]) { b[j] -= abs(j - e); } } } for (auto &e : pos) done[e] = 1; } cout << res << n ; return; } int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); ll tt = 1; cin >> tt; for (ll i = 0; i < tt; i++) test(); return 0; }
|
#include <bits/stdc++.h> const int MAXN = 4e5 + 5, MAXLOG = 20, MAXS = MAXN * 50; template <typename _T> void read(_T &x) { x = 0; char s = getchar(); int f = 1; while (s > 9 || s < 0 ) { if (s == - ) f = -1; s = getchar(); } while (s >= 0 && s <= 9 ) { x = (x << 3) + (x << 1) + (s - 0 ), s = getchar(); } x *= f; } template <typename _T> void write(_T x) { if (x < 0) { putchar( - ); x = (~x) + 1; } if (9 < x) { write(x / 10); } putchar(x % 10 + 0 ); } template <typename _T> _T MAX(const _T a, const _T b) { return a > b ? a : b; } template <typename _T> _T MIN(const _T a, const _T b) { return a < b ? a : b; } struct edge { int to, nxt; } Graph[MAXN << 1]; int f[MAXN][MAXLOG]; bool s[MAXS]; int lch[MAXS], rch[MAXS]; int dp[MAXN], seq[MAXN], ID; int ch[MAXN][26], fa[MAXN], mx[MAXN], head[MAXN], rot[MAXN], fir[MAXN]; int N, lg2, rt, lst, tot, cnt, siz; char S[MAXN]; void upt(const int x) { s[x] = s[lch[x]] | s[rch[x]]; } void copy(int a, int b) { fa[a] = fa[b], mx[a] = mx[b], memcpy(ch[a], ch[b], sizeof ch[b]); } void addEdge(const int from, const int to) { Graph[++cnt].to = to, Graph[cnt].nxt = head[from]; head[from] = cnt; } void expand(const char c) { int x = c - a , p = lst, cur = ++tot; mx[cur] = mx[lst] + 1, lst = cur; while (p && !ch[p][x]) ch[p][x] = cur, p = fa[p]; if (!p) { fa[cur] = rt; return; } int q = ch[p][x]; if (mx[q] == mx[p] + 1) { fa[cur] = q; return; } int nq = ++tot; copy(nq, q); mx[nq] = mx[p] + 1, fa[q] = fa[cur] = nq; while (p && ch[p][x] == q) ch[p][x] = nq, p = fa[p]; } void update(int &u, const int l, const int r, const int pos) { if (!u) u = ++siz; if (l == r) { s[u] = true; return; } int mid = l + r >> 1; if (pos <= mid) update(lch[u], l, mid, pos); else update(rch[u], mid + 1, r, pos); upt(u); } bool query(const int u, const int l, const int r, const int segL, const int segR) { if (!u) return false; if (segL <= l && r <= segR) return s[u]; int mid = l + r >> 1, ret = false; if (segL <= mid) ret |= query(lch[u], l, mid, segL, segR); if (mid < segR) ret |= query(rch[u], mid + 1, r, segL, segR); return ret; } int merg(int u, int v) { if (!u || !v) return u + v; int cur = ++siz; lch[cur] = merg(lch[u], lch[v]); rch[cur] = merg(rch[u], rch[v]); s[cur] = s[u] | s[v]; return cur; } void DFS(const int u) { seq[++ID] = u; for (int i = head[u], v; i; i = Graph[i].nxt) { DFS(v = Graph[i].to); rot[u] = merg(rot[u], rot[v]); fir[u] = MIN(fir[u], fir[v]); } } int main() { rt = lst = ++tot; memset(fir, 0x3f, sizeof fir); read(N), scanf( %s , S + 1); for (int i = 1; i <= N; i++) expand(S[i]), update(rot[lst], 1, N, i), fir[lst] = i; for (int i = 2; i <= tot; i++) addEdge(fa[i], i); DFS(rt); lg2 = log2(tot); for (int i = 1; i <= tot; i++) f[i][0] = fa[i]; for (int j = 1; j <= lg2; j++) for (int i = 1; i <= tot; i++) f[i][j] = f[f[i][j - 1]][j - 1]; for (int i = tot, u, p; i; i--) { u = p = seq[i]; for (int k = lg2; ~k; k--) if (f[p][k] > rt && !query(rot[f[p][k]], 1, N, fir[u] - mx[u] + mx[f[p][k]], fir[u] - 1)) p = f[p][k]; p = fa[p]; dp[p] = MAX(dp[p], dp[u] + 1); } write(dp[rt]), putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 56; int n, a[N]; int cnt(int x) { int ans = 0; for (int i = 1; i <= n; ++i) ans += (a[i] == x); return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; int k = *min_element(a + 1, a + n + 1); cout << (cnt(k) <= n / 2 ? Alice : Bob ); }
|
#include <bits/stdc++.h> using namespace std; const int N = 25, M = 300005; int n, a[N][N]; long long f[M], g[N][M], d[N][M], dp[N][M]; map<long long, long long> mp; string st; inline int bp(int x) { return __builtin_popcount(x); } void dfs(int p, int s, int x, long long m) { if (s == n) { long long w = 0; for (int i = 0; i < (1 << n); i++) { if ((n + bp(i)) & 1) w -= d[x][i]; else w += d[x][i]; } mp[m] = w; return; } if (s + p > n) return; for (int i = 0; i < (1 << n); i++) d[x + 1][i] = d[x][i] * g[p][i]; dfs(p, s + p, x + 1, m * 10 + p); dfs(p + 1, s, x, m); } long long ch(int x) { vector<int> v; int s = 0; for (int i = 0; i < n; i++) { if (x >> i & 1) s++; else { v.push_back(s + 1); s = 0; } } sort(v.begin(), v.end()); long long y = 0; for (auto i : v) y = y * 10 + i; return y; } int main() { ios::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { cin >> st; for (int j = 0; j < n; j++) a[i][j] = (st[j] == 1 ); } for (int i = 0; i < n; i++) dp[i][1 << i] = 1; for (int i = 1; i < (1 << n); i++) { for (int j = 0; j < n; j++) { if (dp[j][i]) { g[bp(i)][i] += dp[j][i]; for (int k = 0; k < n; k++) if (!(i >> k & 1) && a[j][k]) dp[k][i | (1 << k)] += dp[j][i]; } } } for (int i = 1; i <= n; i++) for (int j = 0; j < n; j++) for (int s = 0; s < (1 << n); s++) if (s >> j & 1) g[i][s] += g[i][s ^ (1 << j)]; for (int i = 0; i < (1 << n); i++) d[0][i] = 1; dfs(1, 0, 0, 0); for (int i = 0; i < (1 << (n - 1)); i++) f[i] = mp[ch(i)]; for (int i = 0; i < n - 1; i++) for (int j = 0; j < (1 << (n - 1)); j++) if (!(j >> i & 1)) f[j] -= f[j ^ (1 << i)]; for (int i = 0; i < (1 << (n - 1)); i++) printf( %lld , f[i]); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_2_V
`define SKY130_FD_SC_LP__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_2_V
|
module SigmaDeltaPhasedArray #(
parameter NUM_CH = 64, ///< Number of input channels
parameter ADDR_WIDTH = 8, ///< Depth of sample buffers
parameter OUT_WIDTH = 16, ///< Width of output signal
parameter OUT_DELAY = 3 ///< Specified delay between cmdIn/invertBit and dataOut
)
(
input clk,
input rst,
input sample,
input [NUM_CH-1:0] dataIn,
input [NUM_CH*ADDR_WIDTH-1:0] cmdIn, ///< Array of which sample to pull from each channel
input [NUM_CH-1:0] invertBit, ///< 1 to invert channel bit, 0 to not invert
output [OUT_WIDTH-1:0] outData
);
///////////////////////////////////////////////////////////////////////////
// PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////////
initial begin
if ((2**OUT_WIDTH-1) < NUM_CH) begin
$display("Attribute OUT_WIDTH on phaseDelay instance %m is %i. Must be at least %i (log2(NUM_CH+1)).", OUT_WIDTH, $log2(NUM_CH+1));
#1 $finish;
end
end
parameter SUM_DEPTH = $rtoi($ceil($log10(NUM_CH/3.0)/$log10(3.0)));
parameter NUM_SUMS = 3**SUM_DEPTH;
localparam NUM_128BUF = (ADDR_WIDTH > 7) ? (1 << (ADDR_WIDTH-7)) : 1;
localparam MUX_ADDR_WIDTH = (ADDR_WIDTH > 7) ? (ADDR_WIDTH-7) : 1;
///////////////////////////////////////////////////////////////////////////
// SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
genvar chIndex;
genvar bufIndex;
integer sumIndex;
integer addr128Index;
integer addrIndex;
integer muxIndex;
reg [NUM_SUMS*2-1:0] sumsReg;
reg [NUM_SUMS*2-1:0] sums;
reg [ADDR_WIDTH-1:0] bufAddr [NUM_CH-1:0];
reg [6:0] buf128Addr [NUM_CH-1:0];
reg [MUX_ADDR_WIDTH-1:0] muxAddr [NUM_CH-1:0];
wire [NUM_128BUF:0] shiftArray [NUM_CH-1:0];
reg [NUM_CH-1:0] invertBitBuf;
reg [NUM_CH-1:0] invertBitD1;
reg [NUM_128BUF-1:0] buf128Out [NUM_CH-1:0];
reg [NUM_CH-1:0] bufOut;
///////////////////////////////////////////////////////////////////////////
// BUFFERS & ADDRESS LOGIC
///////////////////////////////////////////////////////////////////////////
// Split up the inputs & optionally delay them
if (OUT_DELAY > SUM_DEPTH+2) begin
always @(posedge clk) begin
invertBitD1 <= invertBit;
for (addrIndex=0; addrIndex<NUM_CH; addrIndex=addrIndex+1) begin
bufAddr[addrIndex] <= cmdIn[(addrIndex*ADDR_WIDTH)+:ADDR_WIDTH];
end
end
end
else begin
always @(*) begin
invertBitD1 = invertBit;
for (addrIndex=0; addrIndex<NUM_CH; addrIndex=addrIndex+1) begin
bufAddr[addrIndex] = cmdIn[(addrIndex*ADDR_WIDTH)+:ADDR_WIDTH];
end
end
end
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) invertBitBuf <= invertBitD1;
end
else begin
always @(*) invertBitBuf = invertBitD1;
end
// Get the buf128 addresses
always @(*) begin
for (addr128Index=0; addr128Index<NUM_CH; addr128Index=addr128Index+1) begin
buf128Addr[addr128Index] = bufAddr[addr128Index];
end
end
// Generate the 128 sample deep buffers
generate
for (chIndex=0;chIndex<NUM_CH; chIndex=chIndex+1) begin
assign shiftArray[chIndex][0] = dataIn[chIndex];
for (bufIndex=0; bufIndex<NUM_128BUF; bufIndex=bufIndex+1) begin
SigmaDeltaPhasedArray128Buf sampleBuffer (
.clk(clk),
.sample(sample),
.shiftIn(shiftArray[chIndex][bufIndex]),
.addr(buf128Addr[chIndex]), ///< [6:0]
.shiftOut(shiftArray[chIndex][bufIndex+1]),
.dataOut(buf128Out[chIndex][bufIndex])
);
end
end
endgenerate
// Multiplexers to select from the sample buffers
if (NUM_128BUF == 1) begin
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][0];
end
end
end
else begin
always @(*) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][0];
end
end
end
end
else begin
if (OUT_DELAY > SUM_DEPTH+1) begin
always @(posedge clk) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][bufAddr[muxIndex][ADDR_WIDTH-1:7]];
end
end
end
else begin
always @(*) begin
for (muxIndex=0; muxIndex<NUM_CH; muxIndex=muxIndex+1) begin
bufOut[muxIndex] <= buf128Out[muxIndex][bufAddr[muxIndex][ADDR_WIDTH-1:7]];
end
end
end
end
///////////////////////////////////////////////////////////////////////////
// SUMMATION
///////////////////////////////////////////////////////////////////////////
// Sum 3 bits
always @(*) begin
sums = 'd0;
for (sumIndex=0; sumIndex<NUM_CH/3; sumIndex=sumIndex+1) begin
sums[sumIndex] = (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0])
^ (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1])
^ (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2]);
sums[sumIndex+1] = (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0]) & (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1])
| (invertBitBuf[sumIndex+1] ^ bufOut[sumIndex+1]) & (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2])
| (invertBitBuf[sumIndex+2] ^ bufOut[sumIndex+2]) & (invertBitBuf[sumIndex+0] ^ bufOut[sumIndex+0]);
end
if (NUM_CH % 3 == 1) begin
sums[(NUM_CH/3)*2-2] = (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
sums[(NUM_CH/3)*2-1] = 1'b0;
end
else if (NUM_CH % 3 == 2) begin
sums[(NUM_CH/3)*2-2] = (invertBitBuf[NUM_CH-2] ^ bufOut[NUM_CH-2])
^ (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
sums[(NUM_CH/3)*2-1] = (invertBitBuf[NUM_CH-2] ^ bufOut[NUM_CH-2])
& (invertBitBuf[NUM_CH-1] ^ bufOut[NUM_CH-1]);
end
end
// Register sums if necessary
if (OUT_DELAY > SUM_DEPTH) begin
always @(posedge clk) sumsReg <= sums;
end
else begin
always @(*) sumsReg = sums;
end
// Nested summations
if (SUM_DEPTH >= 1) begin
// At least 4 channels exist - sum them
reg [3:0] sum3 [NUM_SUMS/3-1:0];
integer sum3Index;
if (OUT_DELAY > SUM_DEPTH-1) begin
always @(posedge clk) begin
for (sum3Index=0; sum3Index<NUM_SUMS/3; sum3Index=sum3Index+1) begin
sum3[sum3Index] <= sumsReg[3*sum3Index+:2] + sumsReg[3*sum3Index+1+:2] + sumsReg[3*sum3Index+2+:2];
end
end
always @(*) begin
for (sum3Index=0; sum3Index<NUM_SUMS/3; sum3Index=sum3Index+1) begin
sum3[sum3Index] = sumsReg[3*sum3Index+:2] + sumsReg[3*sum3Index+1+:2] + sumsReg[3*sum3Index+2+:2];
end
end
end
// At least 10 channels exist - sum them
if (SUM_DEPTH >= 2) begin
reg [4:0] sum9 [NUM_SUMS/9-1:0];
integer sum9Index;
if (OUT_DELAY > SUM_DEPTH-2) begin
always @(posedge clk) begin
for (sum9Index=0; sum9Index<NUM_SUMS/9; sum9Index=sum9Index+1) begin
sum9[sum9Index] <= sum3[sum9Index] + sum3[sum9Index+1] + sum3[sum9Index+2];
end
end
end
else begin
always @(*) begin
for (sum9Index=0; sum9Index<NUM_SUMS/9; sum9Index=sum9Index+1) begin
sum9[sum9Index] = sum3[sum9Index] + sum3[sum9Index+1] + sum3[sum9Index+2];
end
end
end
// At least 28 channels exist - sum them
if (SUM_DEPTH >= 3) begin
reg [6:0] sum27 [NUM_SUMS/27-1:0];
integer sum27Index;
if (OUT_DELAY > SUM_DEPTH-3) begin
always @(posedge clk) begin
for (sum27Index=0; sum27Index<NUM_SUMS/27; sum27Index=sum27Index+1) begin
sum27[sum27Index] <= sum9[sum27Index] + sum9[sum27Index+1] + sum9[sum27Index+2];
end
end
end
else begin
always @(*) begin
for (sum27Index=0; sum27Index<NUM_SUMS/27; sum27Index=sum27Index+1) begin
sum27[sum27Index] = sum9[sum27Index] + sum9[sum27Index+1] + sum9[sum27Index+2];
end
end
end
// At least 82 channels exist - sum them
// This supports up to 243 channels
if (SUM_DEPTH >= 4) begin
reg [7:0] sum81;
if (OUT_DELAY >= 1) begin
always @(posedge clk) begin
sum81 <= sum27[0] + sum27[1] + sum27[2];
end
end
else begin
always @(*) begin
sum81 = sum27[0] + sum27[1] + sum27[2];
end
end
assign outData = sum81;
end
else begin
assign outData = sum27[0];
end
end
else begin
assign outData = sum9[0];
end
end
else begin
assign outData = sum3[0];
end
end
else begin
assign outData = sums[1:0];
end
endmodule
///////////////////////////////////////////////////////////////////////////
// BUFFER SUBMODULE
///////////////////////////////////////////////////////////////////////////
module SigmaDeltaPhasedArray128Buf (
input clk,
input sample,
input shiftIn,
input [6:0] addr,
output shiftOut,
output dataOut
);
reg [127:0] shiftReg;
assign dataOut = shiftReg[addr];
assign shiftOut = shiftReg[127];
always @(posedge clk) begin
if (sample) begin
shiftReg <= {shiftReg[126:0], shiftIn};
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MX = 1e5 + 9; long long par[MX], num[MX]; void MS(long long v) { par[v] = v, num[v] = 1; } long long FS(long long v) { if (par[v] == v) return v; return par[v] = FS(par[v]); } void US(long long a, long long b) { a = FS(a), b = FS(b); if (a == b) return; if (num[a] < num[b]) swap(a, b); par[b] = a; num[a] += num[b]; } bool lucky(string s) { for (long long i = 0; i < s.size(); i++) if (s[i] != 4 && s[i] != 7 ) return 0; return 1; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; for (long long i = 1; i <= n; i++) MS(i); for (long long i = 1; i < n; i++) { long long u, v; string s; cin >> u >> v >> s; if (!lucky(s)) US(u, v); } long long ans = 0; for (long long i = 1; i <= n; i++) { long long sz = n - num[FS(i)]; ans += sz * (sz - 1); } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__INVLP_PP_SYMBOL_V
/**
* invlp: Low Power Inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invlp (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long n, one = 0, z = 0; string s, s1; cin >> n >> s; if (n == 1) { cout << s << endl; continue; } for (long long i = 0; i < s.length(); i++) { if (s[i] == 1 ) one++; else { z++; } } if (z > one) { for (int i = 0; i < n; i++) { s1 += 0 ; } } else { for (int i = 0; i < n; i++) { s1 += 1 ; } } cout << s1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int fa[N], mx[N], n; vector<int> son[N]; vector<int> ans; bool cmp(const int x, const int y) { return mx[x] < mx[y]; } void dfs(int x) { int s = son[x].size(); for (int i = 0; i < s; ++i) { int& sn = son[x][i]; dfs(sn); mx[x] = max(mx[x], mx[sn] + 1); } sort(son[x].begin(), son[x].end(), cmp); } void DFS(int x) { printf( %d , x); for (int i = 0; i < son[x].size(); ++i) { int& sn = son[x][i]; DFS(sn); if (i == 0) continue; for (int j = 0; j <= mx[son[x][i - 1]]; ++j) ans.push_back(sn); } } int main() { scanf( %d , &n); for (int i = 1; i < n; ++i) { scanf( %d , &fa[i]); son[fa[i]].push_back(i); } dfs(0); DFS(0); int s = ans.size(); printf( n%d n , s); for (int i = 0; i < s; ++i) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a[120000]; void query(int L, int R) { int M = (L + R) / 2; printf( ? %d n , M); fflush(stdout); printf( ? %d n , n / 2 + M); fflush(stdout); scanf( %d %d , a + M, a + M + n / 2); if (a[M] == a[n / 2 + M]) { printf( ! %d n , M); fflush(stdout); return; } if (((a[M + n / 2] - a[M]) < 0) ^ ((a[L + n / 2] - a[L]) < 0)) query(L, M); else query(M, R); } int main() { scanf( %d , &n); if (n % 4) { printf( ! -1 n ); fflush(stdout); return 0; } printf( ? 1 n ); fflush(stdout); printf( ? %d n , n / 2 + 1); fflush(stdout); scanf( %d %d , a + 1, a + n / 2 + 1); if (a[1] == a[n / 2 + 1]) { printf( ! %d n , 1); fflush(stdout); return 0; } printf( ? %d n , n / 2); fflush(stdout); printf( ? %d n , n); fflush(stdout); scanf( %d %d , a + n / 2, a + n); if (a[n / 2] == a[n]) { printf( ! %d n , n / 2); fflush(stdout); return 0; } query(1, n / 2); }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; using ll = long long; using db = long double; using str = string; using pi = pair<int, int>; using pl = pair<ll, ll>; using pd = pair<db, db>; using vi = vector<int>; using vb = vector<bool>; using vl = vector<ll>; using vd = vector<db>; using vs = vector<str>; using vpi = vector<pi>; using vpl = vector<pl>; using vpd = vector<pd>; template <class T> using V = vector<T>; template <class T> using PR = pair<T, T>; template <class T, size_t SZ> using AR = array<T, SZ>; template <class T> using pqg = priority_queue<T, vector<T>, greater<T>>; const int MX = 2e5 + 5; const int MOD = 1e9 + 7; const ll INF = 1e18; const db PI = acos((db)-1); const int xdir[4] = {1, 0, -1, 0}, ydir[4] = {0, 1, 0, -1}; mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return x == 0 ? 0 : 31 - __builtin_clz(x); } ll cdiv(ll a, ll b) { return a / b + ((a ^ b) > 0 && a % b); } ll fdiv(ll a, ll b) { return a / b - ((a ^ b) < 0 && a % b); } template <class T> bool ckmin(T& a, const T& b) { return b < a ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } template <class T, class U> T fstTrue(T lo, T hi, U first) { hi++; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo) / 2; first(mid) ? hi = mid : lo = mid + 1; } return lo; } template <class T, class U> T lstTrue(T lo, T hi, U first) { lo--; assert(lo <= hi); while (lo < hi) { T mid = lo + (hi - lo + 1) / 2; first(mid) ? lo = mid : hi = mid - 1; } return lo; } template <class T> void remDup(V<T>& v) { sort(begin(v), end(v)); v.erase(unique(begin(v), end(v)), end(v)); } template <typename T1, typename T2> str to_string(pair<T1, T2> p); template <typename T1, typename T2, typename T3> str to_string(tuple<T1, T2, T3> p); template <typename T1, typename T2, typename T3, typename T4> str to_string(tuple<T1, T2, T3, T4> p); str to_string(const str& S) { return + S + ; } str to_string(const char* S) { return to_string((str)S); } str to_string(bool b) { return b ? true : false ; } template <class T> str to_string(complex<T> c) { stringstream ss; ss << c; return ss.str(); } template <size_t SZ> str to_string(bitset<SZ> v) { str res = ; for (int i = (0); i < (SZ); ++i) res += char(v[i] + 0 ); return res; } template <typename T> str to_string(T v) { bool fst = 1; str res = ; for (const auto& x : v) { if (!fst) res += ; fst = 0; res += to_string(x); } return res; } template <typename T1, typename T2> str to_string(pair<T1, T2> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } void DBG() { cerr << endl; } template <typename Head, typename... Tail> void DBG(Head H, Tail... T) { cerr << << to_string(H); DBG(T...); } void setPrec() { cout << fixed << setprecision(15); } void unsyncIO() { cin.tie(0)->sync_with_stdio(0); } void setIn(str name) { freopen(name.c_str(), r , stdin); } void setOut(str name) { freopen(name.c_str(), w , stdout); } void setIO(str name = ) { unsyncIO(); setPrec(); if ((int)((name).size())) setIn(name + .in ), setOut(name + .out ); } struct node { ll prefix, suffix, sum, msum; node() { prefix = suffix = sum = msum = 0LL; } node(ll value) { sum = value; prefix = suffix = sum = msum = max(0LL, value); } }; node operator+(node a, node b) { node res; res.sum = a.sum + b.sum; res.prefix = max(a.prefix, a.sum + b.prefix); res.suffix = max(b.suffix, a.suffix + b.sum); res.msum = max({a.msum, b.msum, a.suffix + b.prefix}); return res; } template <class T> struct Seg { const T ID = T(); T comb(T a, T b) { return a + b; } int N; vector<T> seg; void init(int _N) { N = _N; seg.assign(2 * N, ID); } void pull(int p) { seg[p] = comb(seg[2 * p], seg[2 * p + 1]); } void upd(int p, T val) { seg[p += N] = val; for (p /= 2; p; p /= 2) pull(p); } T query(int l, int r) { T ra = ID, rb = ID; for (l += N, r += N + 1; l < r; l /= 2, r /= 2) { if (l & 1) ra = comb(ra, seg[l++]); if (r & 1) rb = comb(seg[--r], rb); } return comb(ra, rb); } }; Seg<node> ST; int SZ(int n) { int sz = 0; while ((1 << sz) < n) sz++; return 1 << sz; } int32_t main() { setIO(); int t; cin >> t; while (t--) { int n; cin >> n; vi arr(n); for (auto& x : arr) cin >> x, --x; vi p(n); for (int i = (0); i < (n); ++i) p[arr[i]] = i; ST.init(SZ(n)); vb marked(n, false); bool res = true; int lst = n - 1, fst = 0; for (int i = (0); i < (n); ++i) { while (marked[lst]) --lst; ll csc = ST.query(fst, lst).msum + 1; auto can = [&](int x) { return ST.query(x, p[i]).sum == p[i] - x; }; ll sum = p[i] - fstTrue(0, p[i], can) + 1; if (sum != csc) { res = false; break; } ST.upd(p[i], 1); marked[p[i]] = 1; } cout << (res ? Yes n : No n ); } }
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios::sync_with_stdio(false); long long t; cin >> t; while (t--) { vector<long long> A(3); for (auto &a : A) cin >> a; sort((A).begin(), (A).end(), greater<long long>()); long long a, b, c; a = A[0]; b = A[1]; c = A[2]; long long ans = 0; if (a > 0) { a--; ans++; } if (b > 0) { b--; ans++; } if (c > 0) { c--; ans++; } if (a > 0 && b > 0) { a--; b--; ans++; } if (c > 0 && b > 0) { c--; b--; ans++; } if (a > 0 && c > 0) { a--; c--; ans++; } if (a > 0 && b > 0 && c > 0) { a--; b--; c--; ans++; } cout << ans << endl; } return 0; }
|
//////////////////////////////////////////////////////////////////
// //
// Barrel Shifter for Amber 2 Core //
// //
// The design is optimized for Altera family of FPGAs, //
// and it can be used directly or adapted other N-to-1 LUT //
// FPGA platforms. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Provides 32-bit shifts LSL, LSR, ASR and ROR //
// //
// Author(s): //
// - Dmitry Tarnyagin, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010-2013 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_barrel_shift_fpga (
input [31:0] i_in,
input i_carry_in,
input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero, // high when immediate shift value of zero selected
input [1:0] i_function,
output [31:0] o_out,
output o_carry_out
);
`include "a23_localparams.v"
wire [31:0] rot_prod; // Input rotated by the shift amount
wire [1:0] lsl_out; // LSL: {carry, bit_31}
wire [1:0] lsr_out; // LSR: {carry, bit_31}
wire [1:0] asr_out; // ASR: {carry, bit_31}
wire [1:0] ror_out; // ROR: {carry, bit_31}
reg [32:0] lsl_mask; // Left-hand mask
reg [32:0] lsr_mask; // Right-hand mask
reg [15:0] low_mask; // Mask calculation helper
reg [4:0] shift_amount; // Shift amount for the low-level shifter
reg [2:0] lsl_selector; // Left shift {shift_32, shift_over, shift_amount[4]}
reg [2:0] lsr_selector; // Right shift {shift_32, shift_over, shift_amount[4]}
reg [3:0] low_selector; // {shift_amount[3:0]}
reg shift_nzero; // Amount is not zero
reg shift_over; // Amount is 32 or higher
reg shift_32; // Amount is exactly 32
reg asr_sign; // Sign for ASR shift
reg direction; // Shift direction
wire [31:0] p_r; // 1 bit rotated rot_prod
wire [31:0] p_l; // Alias for the rot_prod
// Implementation details:
// Design is based on masking of rotated input by a left- and right- hand masks.
// Rotated product calculation requires 5 levels of combinational logic, and masks
// must be ready before the product is ready. In fact masks require just 3 to 4 levels
// of logic cells using 4-to-1/2x3-to-1 Altera.
always @*
begin
shift_32 = i_shift_amount == 32;
shift_over = |i_shift_amount[7:5];
shift_nzero = |i_shift_amount[7:0];
shift_amount = i_shift_amount[4:0];
if (i_shift_imm_zero) begin
if (i_function == LSR || i_function == ASR) begin
// The form of the shift field which might be
// expected to correspond to LSR #0 is used
// to encode LSR #32, which has a zero result
// with bit 31 of Rm as the carry output.
shift_nzero = 1'b1;
shift_over = 1'b1;
// Redundant and can be optimized out
// shift_32 = 1'b1;
end else if (i_function == ROR) begin
// RXR, (ROR w/ imm 0)
shift_amount[0] = 1'b1;
shift_nzero = 1'b1;
end
end
// LSB sub-selector calculation. Usually it is taken
// directly from the shift_amount, but ROR requires
// no masking at all.
case (i_function)
LSL: low_selector = shift_amount[3:0];
LSR: low_selector = shift_amount[3:0];
ASR: low_selector = shift_amount[3:0];
ROR: low_selector = 4'b0000;
endcase
// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
case (i_function)
LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
endcase
// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
case (i_function)
LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
endcase
// Direction
case (i_function)
LSL: direction = 1'b0; // Left shift
LSR: direction = 1'b1; // Right shift
ASR: direction = 1'b1; // Right shift
ROR: direction = 1'b1; // Right shift
endcase
// Sign for ASR shift
asr_sign = 1'b0;
if (i_function == ASR && i_in[31])
asr_sign = 1'b1;
end
// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
// Practically a bit higher due to high fanout of "direction".
generate
genvar i, j;
for (i = 0; i < 5; i = i + 1)
begin : netgen
wire [31:0] in;
reg [31:0] out;
for (j = 0; j < 32; j = j + 1)
begin : net
always @*
out[j] = in[j] & (~shift_amount[i] ^ direction) |
in[wrap(j, i)] & (shift_amount[i] ^ direction);
end
end
// Order is reverted with respect to volatile shift_amount[0]
assign netgen[4].in = i_in;
for (i = 1; i < 5; i = i + 1)
begin : router
assign netgen[i-1].in = netgen[i].out;
end
endgenerate
// Aliasing
assign rot_prod = netgen[0].out;
// Submask calculated from LSB sub-selector.
// Cost: 16 4-to-1 LUTs.
always @*
case (low_selector) // synthesis full_case parallel_case
4'b0000: low_mask = 16'hffff;
4'b0001: low_mask = 16'hfffe;
4'b0010: low_mask = 16'hfffc;
4'b0011: low_mask = 16'hfff8;
4'b0100: low_mask = 16'hfff0;
4'b0101: low_mask = 16'hffe0;
4'b0110: low_mask = 16'hffc0;
4'b0111: low_mask = 16'hff80;
4'b1000: low_mask = 16'hff00;
4'b1001: low_mask = 16'hfe00;
4'b1010: low_mask = 16'hfc00;
4'b1011: low_mask = 16'hf800;
4'b1100: low_mask = 16'hf000;
4'b1101: low_mask = 16'he000;
4'b1110: low_mask = 16'hc000;
4'b1111: low_mask = 16'h8000;
endcase
// Left-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsl_selector) // synthesis full_case parallel_case
7'b1??: lsl_mask = 33'h_1_0000_0000;
7'b01?: lsl_mask = 33'h_0_0000_0000;
7'b001: lsl_mask = { 1'h_1, low_mask, 16'h_0000};
7'b000: lsl_mask = {17'h_1_ffff, low_mask};
endcase
// Right-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsr_selector) // synthesis full_case parallel_case
7'b1??: lsr_mask = 33'h_1_0000_0000;
7'b01?: lsr_mask = 33'h_0_0000_0000;
7'b000: lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
7'b001: lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
endcase
// Alias: right-rotated
assign p_r = {rot_prod[30:0], rot_prod[31]};
// Alias: left-rotated
assign p_l = rot_prod[31:0];
// ROR MSB, handling special cases
assign ror_out[0] = i_shift_imm_zero ? i_carry_in :
p_r[31];
// ROR carry, handling special cases
assign ror_out[1] = i_shift_imm_zero ? i_in[0] :
shift_nzero ? p_r[31] :
i_carry_in;
// LSL MSB
assign lsl_out[0] = p_l[31] & lsl_mask[31];
// LSL carry, handling special cases
assign lsl_out[1] = shift_nzero ? p_l[0] & lsl_mask[32]:
i_carry_in;
// LSR MSB
assign lsr_out[0] = p_r[31] & lsr_mask[31];
// LSR carry, handling special cases
assign lsr_out[1] = i_shift_imm_zero ? i_in[31] :
shift_nzero ? p_r[31] & lsr_mask[32]:
i_carry_in;
// ASR MSB
assign asr_out[0] = i_in[31] ? i_in[31] :
p_r[31] & lsr_mask[31] ;
// LSR carry, handling special cases
assign asr_out[1] = shift_over ? i_in[31] :
shift_nzero ? p_r[31] :
i_carry_in;
// Carry and MSB are calculated as above
assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
i_function == LSR ? lsr_out :
i_function == ASR ? asr_out :
ror_out ;
// And the rest of result is the masked rotated input.
assign o_out[30:0] = (p_l[30:0] & lsl_mask[30:0]) |
(p_r[30:0] & lsr_mask[30:0]) |
(~lsr_mask[30:0] & {31{asr_sign}});
// Rotate: calculate bit pos for level "level" and offset "pos"
function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
out = pos - (1 << level);
wrap = out[4:0];
end
endfunction
// Swap bits in the input 16-bit value
function [15:0] bit_swap;
input [15:0] value;
integer i;
begin
for (i = 0; i < 16; i = i + 1)
bit_swap[i] = value[15 - i];
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 10; int n, a[N], b[N], c[N], p[N]; vector<int> v; int main() { cin >> n; for (int i = 1; i < N; i++) p[i] = i; for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i]; if (a[i] == 2) cin >> c[i]; } for (int i = n; i >= 1; i--) { if (a[i] == 1) v.push_back(p[b[i]]); else if (a[i] == 2) p[b[i]] = p[c[i]]; } for (int i = v.size() - 1; i >= 0; i--) printf( %d , v[i]); return 0; }
|
// -*- Mode: Verilog -*-
// Filename : testbench.v
// Description : UART RTL Test bench
// Author : Philip Tracton
// Created On : Mon Apr 20 16:05:13 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:05:13 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "includes.v"
module testbench (/*AUTOARG*/ ) ;
//
// Free Running 50 MHz Clock
//
reg clk_tb;
parameter _clk_50mhz_high = 10,
_clk_50mhz_low = 10,
_clk_50mhz_period = _clk_50mhz_high + _clk_50mhz_low;
initial
begin
clk_tb <= 'b0;
forever
begin
#(_clk_50mhz_low) clk_tb = 1;
#(_clk_50mhz_high) clk_tb = 0;
end
end
//
// Free Running 100 MHz Clock
//
reg clk_100mhz;
parameter _clk_100mhz_high = 5,
_clk_100mhz_low = 5,
_clk_100mhz_period = _clk_100mhz_high + _clk_100mhz_low;
initial
begin
clk_100mhz <= 'b0;
forever
begin
#(_clk_100mhz_low) clk_100mhz = 1;
#(_clk_100mhz_high) clk_100mhz = 0;
end
end
//
// Asynch. Reset to device
//
reg reset_tb;
initial
begin
reset_tb = 0;
#1 reset_tb = 1;
#200 reset_tb = 0;
end
uart_echo dut(
.TX(UART0_TX),
.CLK(clk_100mhz),
.RESET(reset_tb),
.RX(UART0_RX)
) ;
//
// Simulation tools
//
reg test_failed;
reg test_passed;
reg [31:0] read_word;
initial begin
test_failed <= 1'b0;
read_word <= 32'b0;
end
always @(posedge test_passed)
if (test_passed) begin
$display("*** TEST PASSED ***");
#1000;
$finish;
end
always @(posedge test_failed)
if (test_failed) begin
$display("*** TEST FAILED ***");
#50;
$finish;
end
/****************************************************************************
UART 0 -- This is used for CLI Interfacing
The WB UART16550 from opencores is used here to simulate a UART on the other end
of the cable. It will allow us to send/receive characters to the NGMCU firmware
***************************************************************************/
wire [31:0] uart0_adr;
wire [31:0] uart0_dat_o;
wire [31:0] uart0_dat_i;
wire [3:0] uart0_sel;
wire uart0_cyc;
wire uart0_stb;
wire uart0_we;
wire uart0_ack;
wire uart0_int;
assign uart0_dat_o[31:8] = 'b0;
uart_top uart0(
.wb_clk_i(clk_tb),
.wb_rst_i(reset_tb),
.wb_adr_i(uart0_adr[4:0]),
.wb_dat_o(uart0_dat_o),
.wb_dat_i(uart0_dat_i),
.wb_sel_i(uart0_sel),
.wb_cyc_i(uart0_cyc),
.wb_stb_i(uart0_stb),
.wb_we_i(uart0_we),
.wb_ack_o(uart0_ack),
.int_o(uart0_int),
.stx_pad_o(UART0_RX),
.srx_pad_i(UART0_TX),
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i(1'b0),
.dcd_pad_i(1'b0),
.baud_o()
);
wb_mast uart_master0(
.clk (clk_tb),
.rst (reset_tb),
.adr (uart0_adr),
.din (uart0_dat_o),
.dout(uart0_dat_i),
.cyc (uart0_cyc),
.stb (uart0_stb),
.sel (uart0_sel),
.we (uart0_we ),
.ack (uart0_ack),
.err (1'b0),
.rty (1'b0)
);
//
// Test Case
//
initial begin
test_failed <= 1'b0;
test_passed <= 1'b0;
@(negedge reset_tb);
$display("RESET RELEASED %d", $time);
repeat(10)@(posedge clk_tb);
`UART_CONFIG();
`UART_WRITE_CHAR("A");
`UART_WRITE_CHAR("B");
`UART_WRITE_CHAR("C");
`UART_WRITE_CHAR("D");
`UART_WRITE_CHAR("E");
repeat(100)@(posedge clk_tb);
`UART_READ_CHAR("A");
`UART_READ_CHAR("B");
`UART_READ_CHAR("C");
`UART_READ_CHAR("D");
`UART_READ_CHAR("E");
repeat(100)@(posedge clk_tb);
test_passed <= 1'b1;
end // initial begin
uart_tasks uart_tasks();
endmodule // testbench
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; struct ppi { long long max; int id; int w; } pp1; struct pi { int le; int ri; int max; int id; } pp[maxn << 2]; void build(int tot, int le, int ri) { pp[tot].le = le; pp[tot].ri = ri; pp[tot].max = -1000000001; if (le == ri) return; build(2 * tot, le, (le + ri) / 2); build(2 * tot + 1, (le + ri) / 2 + 1, ri); } void merg(int tot, int p, int k, int id) { if (pp[tot].le == pp[tot].ri) { if (pp[tot].max < k) { pp[tot].max = k; pp[tot].id = id; } return; } int mid = (pp[tot].le + pp[tot].ri) / 2; if (p <= mid) { merg(2 * tot, p, k, id); } else merg(2 * tot + 1, p, k, id); if (pp[2 * tot].max > pp[2 * tot + 1].max) { pp[tot].max = pp[2 * tot].max; pp[tot].id = pp[2 * tot].id; } else { pp[tot].max = pp[2 * tot + 1].max; pp[tot].id = pp[2 * tot + 1].id; } } ppi query(int tot, int l, int r) { if (pp[tot].le >= l && pp[tot].ri <= r) { pp1.max = pp[tot].max; pp1.id = pp[tot].id; return pp1; } int mid; mid = (pp[tot].le + pp[tot].ri) / 2; ppi pp2; pp2.max = -1000000001; if (l <= mid) { pp1 = query(2 * tot, l, r); if (pp1.max > pp2.max) { pp2.max = pp1.max; pp2.id = pp1.id; } } if (r > mid) { pp1 = query(2 * tot + 1, l, r); if (pp1.max > pp2.max) { pp2.max = pp1.max; pp2.id = pp1.id; } } return pp2; } struct pppi { int l; int r; int c; int id; int ii; } pp3[maxn], pp4[maxn], pp5[maxn << 1]; int a[maxn]; int cmp(pppi a, pppi b) { if (a.l != b.l) return a.l < b.l; return a.id > b.id; } int cmp1(pppi a, pppi b) { if (a.r != b.r) return a.r < b.r; return a.id < b.id; } int cmp2(pppi a, pppi b) { if (a.r != b.r) return a.r < b.r; return a.id > b.id; } int main() { int i, n, m; cin >> n >> m; int tot = 1; ppi pp6; pp6.max = -10000; for (i = 1; i <= n; i++) { scanf( %d%d , &pp3[i].l, &pp3[i].r); a[i] = pp3[i].r; pp3[i].id = 1; pp3[i].ii = i; pp5[tot] = pp3[i]; tot++; } sort(a + 1, a + 1 + n); for (i = 1; i <= m; i++) { scanf( %d%d%d , &pp4[i].l, &pp4[i].r, &pp4[i].c); pp4[i].id = -1; pp4[i].ii = i; pp5[tot] = pp4[i]; tot++; } tot--; build(1, 1, n); sort(pp5 + 1, pp5 + 1 + tot, cmp); for (i = 1; i <= tot; i++) { if (pp5[i].id == 1) { int p = lower_bound(a + 1, a + 1 + n, pp5[i].r) - a; merg(1, p, pp5[i].r, pp5[i].ii); } else { int p = lower_bound(a + 1, a + 1 + n, pp5[i].l) - a; ppi pp7; if (p >= 1 && p <= n) pp7 = query(1, p, n); else pp7.max = 0; if ((min(pp7.max, (long long)pp5[i].r) - pp5[i].l) * pp5[i].c > pp6.max) { pp6.max = (min(pp7.max, (long long)pp5[i].r) - pp5[i].l) * pp5[i].c; pp6.id = pp7.id; pp6.w = pp5[i].ii; } } } for (i = 1; i <= n; i++) { a[i] = pp3[i].l; } sort(a + 1, a + 1 + n); build(1, 1, n); sort(pp5 + 1, pp5 + tot + 1, cmp1); for (i = tot; i >= 1; i--) { if (pp5[i].id == 1) { int p = lower_bound(a + 1, a + 1 + n, pp5[i].l) - a; merg(1, p, -pp5[i].l, pp5[i].ii); } else { int p = lower_bound(a + 1, a + 1 + n, pp5[i].r) - a; if (p > n) p--; if (p >= 1 && p <= n && a[p] > pp5[i].r) p--; ppi pp7; if (p >= 1 && p <= n) { pp7 = query(1, 1, p); pp7.max = -pp7.max; if ((pp5[i].r - max((long long)pp5[i].l, pp7.max)) * pp5[i].c > pp6.max) { pp6.max = (pp5[i].r - max((long long)pp5[i].l, pp7.max)) * pp5[i].c; pp6.id = pp7.id; pp6.w = pp5[i].ii; } } } } sort(pp5 + 1, pp5 + 1 + n, cmp2); build(1, 1, n); for (i = 1; i <= tot; i++) { if (pp5[i].id == 1) { int p = lower_bound(a + 1, a + 1 + n, pp5[i].l) - a; merg(1, p, pp5[i].r - pp5[i].l, pp5[i].ii); } else { int p = lower_bound(a + 1, a + 1 + n, pp5[i].l) - a; if (p >= 1 && p <= n) { ppi pp7 = query(1, p, n); if (pp7.max * pp5[i].c > pp6.max) { pp6.max = pp7.max * pp5[i].c; pp6.id = pp7.id; pp6.w = pp5[i].ii; } } } } if (pp6.max >= 0) cout << pp6.max << endl; else cout << 0 << endl; if (pp6.max > 0) cout << pp6.id << << pp6.w; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:55 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_1_0_stub.v
// Design : system_ov7670_controller_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:29:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: TF_BCD_Segment_Decoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: BCD to Seven Segment Decoder Test Bench
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module TF_BCD_Segment_Decoder();
//
// System Clock Emulation
//
localparam CLK_RATE_HZ = 500000000; // 500 MHz
localparam CLK_HALF_PER = ((1.0 / CLK_RATE_HZ) * .0) / 2.0; // ns
reg CLK;
initial
begin
CLK = 1'b0;
forever #(CLK_HALF_PER) CLK = ~CLK;
end
//
// Unit Under Test: BCD_Segment_Decoder
//
localparam BCD_DIGITS = 5;
localparam BCD_WIDTH = 4; // 4-bits per digit
localparam SEG_WIDTH = 7; // 7-bits per segment
reg [BCD_WIDTH-1:0] bcd_reg_0;
reg [BCD_WIDTH-1:0] bcd_reg_1;
reg [BCD_WIDTH-1:0] bcd_reg_2;
reg [BCD_WIDTH-1:0] bcd_reg_3;
reg [BCD_WIDTH-1:0] bcd_reg_4;
wire [SEG_WIDTH-1:0] seg_out_0;
wire [SEG_WIDTH-1:0] seg_out_1;
wire [SEG_WIDTH-1:0] seg_out_2;
wire [SEG_WIDTH-1:0] seg_out_3;
wire [SEG_WIDTH-1:0] seg_out_4;
BCD_Segment_Decoder
#(
.BCD_DIGITS( BCD_DIGITS )
)
uut
(
// BCD Input (Packed Array)
.BCD_IN( { bcd_reg_4, bcd_reg_3, bcd_reg_2, bcd_reg_1, bcd_reg_0 } ),
// Seven-Segment Output (Packed Array)
.SEG_OUT( { seg_out_4, seg_out_3, seg_out_2, seg_out_1, seg_out_0 } ),
// System Signals
.CLK( CLK )
);
//
// Expected Segment Output Patterns
//
wire [6:0] Expected_Segment_Output [15:0];
assign Expected_Segment_Output[ 0] = 7'b0111111; // 0
assign Expected_Segment_Output[ 1] = 7'b0000110; // 1
assign Expected_Segment_Output[ 2] = 7'b1011011; // 2
assign Expected_Segment_Output[ 3] = 7'b1001111; // 3
assign Expected_Segment_Output[ 4] = 7'b1100110; // 4
assign Expected_Segment_Output[ 5] = 7'b1101101; // 5
assign Expected_Segment_Output[ 6] = 7'b1111101; // 6
assign Expected_Segment_Output[ 7] = 7'b0000111; // 7
assign Expected_Segment_Output[ 8] = 7'b1111111; // 8
assign Expected_Segment_Output[ 9] = 7'b1100111; // 9
assign Expected_Segment_Output[10] = 7'b0000000; // Blank
assign Expected_Segment_Output[11] = 7'b0000000; // Blank
assign Expected_Segment_Output[12] = 7'b0000000; // Blank
assign Expected_Segment_Output[13] = 7'b0000000; // Blank
assign Expected_Segment_Output[14] = 7'b0000000; // Blank
assign Expected_Segment_Output[15] = 7'b0000000; // Blank
//
// Testing Procedure
//
integer test_digit_0;
integer test_digit_1;
integer test_digit_2;
integer test_digit_3;
integer test_digit_4;
reg [4:0] test_output_errors;
integer total_errors;
initial
begin
// Initialize signals
bcd_reg_0 = {BCD_WIDTH{1'b0}};
bcd_reg_1 = {BCD_WIDTH{1'b0}};
bcd_reg_2 = {BCD_WIDTH{1'b0}};
bcd_reg_3 = {BCD_WIDTH{1'b0}};
bcd_reg_4 = {BCD_WIDTH{1'b0}};
test_digit_0 = 0;
test_digit_1 = 0;
test_digit_2 = 0;
test_digit_3 = 0;
test_digit_4 = 0;
test_output_errors = 5'b00000;
total_errors = 0;
// Wait for system to stabilize
#500;
//
// Generate full coverage test vectors for every possible input combination
//
for (test_digit_4 = 0; test_digit_4 < 16; test_digit_4 = test_digit_4 + 1)
begin
for (test_digit_3 = 0; test_digit_3 < 16; test_digit_3 = test_digit_3 + 1)
begin
for (test_digit_2 = 0; test_digit_2 < 16; test_digit_2 = test_digit_2 + 1)
begin
for (test_digit_1 = 0; test_digit_1 < 16; test_digit_1 = test_digit_1 + 1)
begin
for (test_digit_0 = 0; test_digit_0 < 16; test_digit_0 = test_digit_0 + 1)
begin
// Set the BCD Input Values on the Rising Clock Edge
@(posedge CLK);
bcd_reg_0 = test_digit_0[3:0];
bcd_reg_1 = test_digit_1[3:0];
bcd_reg_2 = test_digit_2[3:0];
bcd_reg_3 = test_digit_3[3:0];
bcd_reg_4 = test_digit_4[3:0];
// Wait a clock cycle for the inputs to be registered
@(posedge CLK);
// Wait another clock cycle for the outputs to update
@(posedge CLK);
// Check the output results
test_output_errors[0] = (seg_out_0 != Expected_Segment_Output[test_digit_0]) ? 1'b1 : 1'b0;
test_output_errors[1] = (seg_out_1 != Expected_Segment_Output[test_digit_1]) ? 1'b1 : 1'b0;
test_output_errors[2] = (seg_out_2 != Expected_Segment_Output[test_digit_2]) ? 1'b1 : 1'b0;
test_output_errors[3] = (seg_out_3 != Expected_Segment_Output[test_digit_3]) ? 1'b1 : 1'b0;
test_output_errors[4] = (seg_out_4 != Expected_Segment_Output[test_digit_4]) ? 1'b1 : 1'b0;
// Output Testing Message
$display("Test: %02d %02d %02d %02d %02d : %s %s %s %s %s : %s ",
bcd_reg_4, bcd_reg_3, bcd_reg_2, bcd_reg_1, bcd_reg_0,
test_output_errors[4] ? "X" : ".",
test_output_errors[3] ? "X" : ".",
test_output_errors[2] ? "X" : ".",
test_output_errors[1] ? "X" : ".",
test_output_errors[0] ? "X" : ".",
|test_output_errors ? "FAILURE!!!" : "Pass "
);
// Increment the Total Errors count if there was an error
if (|test_output_errors)
total_errors = total_errors + 1;
end
end
end
end
end
$display("Testing Complete: %d Total Errors", total_errors);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long l, r, ans; vector<long long> lucky; void lu(int f, int s) { string x = ; for (int i = 0; i < f; i++) x += 4 ; for (int i = 0; i < s; i++) x += 7 ; do lucky.push_back(atoll(x.c_str())); while (next_permutation(x.begin(), x.end())); } int main() { cin >> l >> r; for (int i = 0; i <= 10; i++) for (int j = 0; j <= 10; j++) if (i + j <= 10) lu(i, j); sort(lucky.begin(), lucky.end()); int j, k; j = k = 0; while (lucky[j++] < l) ; j--; while (lucky[k++] < r) ; k--; ans += lucky[j] * (min(r - l, lucky[j] - l) + 1); if (lucky[j] == lucky[k]) return cout << ans << endl, 0; ans += lucky[k] * (r - lucky[k - 1]); for (int i = j + 1; i < k; i++) ans += (lucky[i] - lucky[i - 1]) * lucky[i]; cout << ans << endl; }
|
`define MAX_VAL_P 7
`define INIT_VAL_P 0
`define MAX_STEP_P 1
`include "bsg_defines.v"
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
This test module tests the outputs of DUT for a complete count-cycle
i.e., from INIT_VAL_P to MAX_VAL_P and then from MAX_VAL_P to INIT_VAL_P.
If the MAX_VAL_P is less than INIT_VAL_P, simulation finishes
without doing anything.
2. PARAMETERIZATION
Since the DUT implements an algorithm that simply increments or decrements
the count, an arbitrary set of tests that include that include the edge
cases would do the job. So a minimum set of tests might be MAX_VAL_P=1,2,
3,4 with INIT_VAL_P=0,1,2,3. No need to worry about making parameters
compatiable as those tests finish without instatiating DUT.
***************************************************************************/
module test_bsg
#(parameter cycle_time_p = 20,
parameter max_val_p = `MAX_VAL_P,
parameter init_val_p = `INIT_VAL_P,
parameter max_step_p = `MAX_STEP_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_lo_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
logic test_input_up, test_input_down, finish_r;
logic [`BSG_WIDTH(max_val_p)-1:0] test_output;
logic [`BSG_SAFE_CLOG2(max_val_p):0] prev_count, count;
initial
begin
assert(max_val_p >= init_val_p) // checks if params are compatible
else
begin
$error( " Incompatible parameters"
, ": initial value greater than maximum value\n");
$finish;
end
$display( "\n\n\n"
, "================================================================="
, "\ntesting with ...",
, "\nMAX_VAL_P = %d", `MAX_VAL_P
, "\nINIT_VAL_P = %d\n", `INIT_VAL_P
, "\nMAX_STEP_P = %d\n", `MAX_STEP_P
);
end
always_ff @(posedge clk)
begin
if(reset)
begin
finish_r <= 0;
if(init_val_p < max_val_p)
{test_input_up, test_input_down} <= 2'b10;
else
{test_input_up, test_input_down} <= 2'b01;
end
else
begin
if((count == max_val_p-1) & test_input_up) // prevents overflow
{test_input_up, test_input_down} <= 2'b01;
else if((count == 1) & test_input_down) // prevents underflow
{test_input_up, test_input_down} <= 2'b10;
if(finish_r)
begin
$display("==============================================================\n");
$finish;
end
if((prev_count == 1) & (~|count)) // finish when count == 0
finish_r <= 1;
end
end
always_ff @(posedge clk)
begin
if(reset)
begin
count <= init_val_p;
prev_count <= init_val_p;
end
else
begin
//$display("count: %d, test_output: %d @ time: %d\n", count, test_output, $time);
assert(count == test_output)
else $error("mismatch on time %d\n", $time);
count <= count + test_input_up - test_input_down;
prev_count <= count;
end
end
if(max_val_p >= init_val_p) // instantiates only if params are comaptible
bsg_counter_up_down #( .max_val_p (max_val_p)
, .init_val_p (init_val_p)
, .max_step_p (max_step_p)
, .ptr_width_lp()
) DUT
( .clk_i (clk)
, .reset_i(reset)
, .up_i (test_input_up)
, .down_i (test_input_down)
, .count_o(test_output)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int N = 710; string s; int n, t[N]; stack<int> st; struct node { long long f[3][3]; void init() { for (int i = 1; i <= 2; i++) f[i][0] = f[0][i] = 1; } node() { memset(f, 0, sizeof(f)); } void mergein(node t) { for (int i = 0; i <= 2; i++) for (int j = 0; j <= 2; j++) if ((i == 0 || j == 0) && i != j) for (int i1 = 0; i1 <= 2; i1++) for (int j1 = 0; j1 <= 2; j1++) if ((i1 != i || i1 + i == 0) && (j1 != j || j1 + j == 0)) f[i][j] = (f[i][j] + t.f[i1][j1]) % MOD; } void mergenear(node x, node y) { for (int i = 0; i <= 2; i++) for (int j = 0; j <= 2; j++) for (int i1 = 0; i1 <= 2; i1++) for (int j1 = 0; j1 <= 2; j1++) if (i1 != j1 || i1 + j1 == 0) f[i][j] = (f[i][j] + (x.f[i][i1] * y.f[j1][j]) % MOD) % MOD; } }; node DAC(int l, int r) { node tmp; if (t[l] == r) { if (l == r - 1) tmp.init(); else tmp.mergein(DAC(l + 1, r - 1)); } else tmp.mergenear(DAC(l, t[l]), DAC(t[l] + 1, r)); return tmp; } void prepare() { cin >> s; n = s.length(); } void solve() { for (int i = 1; i <= n; i++) if (s[i - 1] == ( ) st.push(i); else t[i] = st.top(), st.pop(), t[t[i]] = i; node ans = DAC(1, n); long long way = 0; for (int i = 0; i <= 2; i++) for (int j = 0; j <= 2; j++) way = (way + ans.f[i][j]) % MOD; cout << way; } int main() { prepare(); solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { int hh, mm, h, d, c, n; cin >> hh >> mm; cin >> h >> d >> c >> n; float a; if (h % n == 0) a = (h / n) * c; else a = (h / n + 1) * c; float b; int tim = hh * 60 + mm; if (tim <= 1200) { h += (1200 - tim) * d; float rate = (float)c * 4 / 5; if (h % n == 0) { b = (h / n) * rate; } else b = (h / n + 1) * rate; } else { float rate = (float)c * 4 / 5; if (h % n == 0) b = (h / n) * rate; else b = (h / n + 1) * rate; } cout << fixed << setprecision(4) << min(a, b); return 0; }
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
`timescale 1 ps / 1 ps
module de1_soc_proc(
///////// CLOCK2 /////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
///////// HEX0 /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// SW /////////
input [9:0] SW
);
reg rCPU_CLK = 1;
integer dCPU_CLK_CNTR = 0;
assign LEDR[8] = rCPU_CLK;
always@(posedge CLOCK2_50)
begin
if(dCPU_CLK_CNTR == 250000) begin
dCPU_CLK_CNTR <= 0;
rCPU_CLK <= ~rCPU_CLK;
end
else begin
dCPU_CLK_CNTR <= dCPU_CLK_CNTR + 1;
end
end
core core(
.iCLK(rCPU_CLK),
.iGPI(SW[7:0]),
.oGPO(LEDR[7:0])
);
endmodule
|
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ia
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/),
// Inputs
.a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ua_h
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fun(long long a[], long long remain, long long total, long long n, long long m) { vector<long long> ans; long long i, j; for (i = 0; i < n && total > 0; i++) { if (a[i] % m == remain) { ans.push_back(a[i]); total--; } } sort(ans.begin(), ans.end()); for (i = 0; i < ans.size(); i++) cout << ans[i] << ; } int main() { long long t, n, i, j, k, m; t = 1; while (t--) { cin >> n >> k >> m; map<long long, long long> x; long long a[n], flag = 0; for (i = 0; i < n; i++) { cin >> a[i]; x[a[i] % m]++; } for (auto itr = x.begin(); itr != x.end(); itr++) { if (itr->second >= k) { flag = 1; cout << Yes << endl; fun(a, itr->first, k, n, m); break; } } if (flag == 0) cout << No << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; long long k; cin >> k; vector<int> a(n); int i; int mx_pos = -1; for (i = 0; i < n; i++) { cin >> a[i]; if (a[i] == n) { mx_pos = i; } } int p1 = -1, p2 = -1; long long w = 0; for (i = 0; w < k && i < mx_pos; i++) { if (p1 == -1) { p1 = a[i]; } else if (p2 == -1) { p2 = a[i]; } if (p2 != -1) { if (p1 < p2) { p1 = p2; p2 = -1; w = 1; } else { p2 = -1; w++; } } } if (w == k) { cout << p1; } else { cout << n; } return 0; }
|
#include <bits/stdc++.h> using namespace std; std::mt19937 rnd( (int)std::chrono::steady_clock::now().time_since_epoch().count()); long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXH = 200000; const int MAXW = 200000; const int MAXQ = 200000; int h, w, nq; int qx[MAXQ], qy[MAXQ]; bool qans[MAXQ]; int a[MAXW], b[MAXW]; bool can(int cnt) { for (int y = (0); y < (w); ++y) a[y] = b[y] = 0; for (int i = (0); i < (cnt); ++i) { int x = qx[i], y = qy[i]; if (x % 2 == 1 && y % 2 == 1) { x /= 2, y /= 2; a[y] = max(a[y], x + 1); } else { assert(x % 2 == 0 && y % 2 == 0); x /= 2, y /= 2; b[y] = max(b[y], h - x); } } for (int y = w - 2; y >= 0; --y) a[y] = max(a[y], a[y + 1]); for (int y = 2; y < w; ++y) b[y] = max(b[y], b[y - 1]); for (int y = (0); y < (w); ++y) if (a[y] + b[y] > h) return false; return true; } void solve() { int lo = 0, hi = nq + 1; while (lo + 1 < hi) { int mi = lo + (hi - lo) / 2; if (can(mi)) lo = mi; else hi = mi; } int res = lo; for (int i = (0); i < (nq); ++i) if (i + 1 <= res) qans[i] = true; else qans[i] = false; } void run() { scanf( %d%d%d , &h, &w, &nq); for (int i = (0); i < (nq); ++i) scanf( %d%d , &qx[i], &qy[i]), --qx[i], --qy[i]; solve(); for (int i = (0); i < (nq); ++i) printf( %s n , qans[i] ? YES : NO ); } int main() { run(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 0x3f3f3f3f; long long dp[maxn]; int n, m; struct node { int lb, lu; long long w; }; vector<node> ve[maxn]; int lb, lu; long long w, cost[maxn]; struct seg { long long ma, lazy; } tr[maxn << 2]; void build(int o, int l, int r) { tr[o].ma = 0; tr[o].lazy = 0; if (l == r) { return; } int mid = (l + r) >> 1; build(o << 1, l, mid); build(o << 1 | 1, mid + 1, r); } void pushup(int o) { tr[o].ma = max(tr[o << 1].ma, tr[o << 1 | 1].ma); } void pushdown(int o) { if (tr[o].lazy) { tr[o << 1].ma += tr[o].lazy; tr[o << 1 | 1].ma += tr[o].lazy; tr[o << 1].lazy += tr[o].lazy; tr[o << 1 | 1].lazy += tr[o].lazy; tr[o].lazy = 0; } } void update(int o, int l, int r, int ql, int qr, long long val) { if (ql <= l && qr >= r) { tr[o].ma += val; tr[o].lazy += val; return; } pushdown(o); int mid = (l + r) >> 1; if (ql <= mid) update(o << 1, l, mid, ql, qr, val); if (qr > mid) update(o << 1 | 1, mid + 1, r, ql, qr, val); pushup(o); } long long query(int o, int l, int r, int ql, int qr) { if (ql <= l && qr >= r) { return tr[o].ma; } pushdown(o); int mid = (l + r) >> 1; long long maxx = 0; if (ql <= mid) maxx = max(maxx, query(o << 1, l, mid, ql, qr)); if (qr > mid) maxx = max(maxx, query(o << 1 | 1, mid + 1, r, ql, qr)); return maxx; } int main() { while (cin >> n >> m) { for (int i = 1; i <= n; i++) { scanf( %lld , &cost[i]); ve[i].clear(); } for (int i = 1; i <= m; i++) { scanf( %d%d%lld , &lb, &lu, &w); ve[lu].push_back({lb, lu, w}); } build(1, 0, n); long long maxx = 0; for (int i = 1; i <= n; i++) { dp[i] = dp[i - 1]; update(1, 0, n, 0, i - 1, -cost[i]); for (int j = 0; j < ve[i].size(); j++) { lb = ve[i][j].lb, w = ve[i][j].w; update(1, 0, n, 0, lb - 1, w); } dp[i] = max(dp[i], query(1, 0, n, 0, i - 1)); update(1, 0, n, i, i, dp[i]); maxx = max(maxx, dp[i]); } printf( %lld n , maxx); } }
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: uart_fifo_64x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module uart_fifo_64x128 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; int n; int cnt[1 << 20]; int cnt2[1 << 20]; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> n; ll res = 0; ++cnt2[0]; for (int pref = 0, a, i = 1; i <= n; ++i) { cin >> a; pref ^= a; if (i & 1) { res += cnt[pref]; ++cnt[pref]; } else { res += cnt2[pref]; ++cnt2[pref]; } } cout << res << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_hd__dlxtn (
Q ,
D ,
GATE_N
);
// Module ports
output Q ;
input D ;
input GATE_N;
// Local signals
wire GATE ;
wire buf_Q;
// Name Output Other arguments
not not0 (GATE , GATE_N );
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTN_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long int s, sum = 0; cin >> n >> s; long long int* v = new long long int[n]; for (int i = 0; i < n; i++) { cin >> v[i]; sum += v[i]; } if (s > sum) cout << -1 << endl; else { sort(v, v + n); if (s < (sum - v[0] * n)) cout << v[0] << endl; else { s -= sum - v[0] * n; if (s % n == 0) cout << v[0] - s / n << endl; else cout << v[0] - (s / n) - 1 << endl; } } }
|
#include <bits/stdc++.h> using namespace std; int arr[100001]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i]; } sort(arr, arr + n); int cur = 1; for (int i = 0; i < n; i++) { if (cur <= arr[i]) { cur++; } } cout << cur; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_FUNCTIONAL_V
|
module testmod ();
always_comb begin
unique case (eeee)
ZERO[1:0] : begin
a = 1;
end // case: ZERO[1:0]
ONE[1:0] : begin
a = 1;
end // case: ONE[1:0]
TWO[1:0] : begin
a = 1;
end // case: TWO[1:0]
THREE[1:0] : begin
a = 1;
end // case: THREE[1:0]
endcase // unique case (eeee)
end // always_comb
always_ff @ (posedge clk) begin
if (reset) begin
current_state <= `TQ STATE0;
end // if (reset)
else begin
priority case (current_state)
STATE0 : begin
current_state <= `TQ STATE3;
end // case: STATE0
STATE1 : begin
current_state <= `TQ STATE3;
end // case: STATE1
STATE2 : begin
current_state <= `TQ STATE3;
end // case: STATE2
STATE3 : begin
current_state <= `TQ STATE0;
end // case: STATE3
default : current_state <= `TQ STATE0;
endcase // priority case (current_state)
end // else: !if(reset)
end // always_ff @
endmodule // testmod
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1050; int dp[maxn][9], nxt[maxn][9][maxn], a[maxn], n, cnt[9]; inline int ask(int k) { return (1 << (k - 1)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= 8; ++j) cnt[j] = 0; for (int j = 1; j <= 8; ++j) for (int k = 1; k <= n; ++k) nxt[i][j][k] = 1e9; for (int j = i; j <= n; ++j) nxt[i][a[j]][++cnt[a[j]]] = j; } int ans = 0; for (int num = 0; num * 8 <= n; ++num) { for (int i = 0; i < 256; ++i) for (int k = 0; k <= 8; ++k) dp[i][k] = 1e9; dp[0][0] = 1; for (int i = 0; i < 256; ++i) for (int j = 0; j <= 8; ++j) for (int k = 1; k <= 8; ++k) { if (dp[i][j] > n || ask(k) & i) continue; dp[i ^ ask(k)][j] = min(dp[i ^ ask(k)][j], nxt[dp[i][j]][k][num] + 1); dp[i ^ ask(k)][j + 1] = min(dp[i ^ ask(k)][j + 1], nxt[dp[i][j]][k][num + 1] + 1); } for (int i = 0; i <= 8; ++i) if (dp[255][i] <= n + 1) ans = max(ans, 8 * num + i); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, temp, k = 0, input[1001], a[1001]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> temp; a[temp]++; if (a[temp] == 1) input[k++] = temp; } sort(input, input + k); for (int i = 2; i < k; i++) { if (input[i] - input[i - 2] == 2 && input[i - 1] == input[i - 2] + 1) { cout << YES ; return 0; } } cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int maxn = n * n - 1; int c = 0; for (int i = 0; i <= maxn; i++) { if (i % 2 == 0) { cout << i << ; c++; } if (c == n) { cout << endl; c = 0; } } for (int i = 0; i <= maxn; i++) { if (i % 2 == 1) { cout << i << ; c++; } if (c == n) { cout << endl; c = 0; } } }
|
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