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/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module and_32(
input [31:0] a, //input values
input [31:0] b,
output [31:0] out //output value
);
//output is the AND of a and b
assign out[0] = a[0] & b[0];
assign out[1] = a[1] & b[1];
assign out[2] = a[2] & b[2];
assign out[3] = a[3] & b[3];
assign out[4] = a[4] & b[4];
assign out[5] = a[5] & b[5];
assign out[6] = a[6] & b[6];
assign out[7] = a[7] & b[7];
assign out[8] = a[8] & b[8];
assign out[9] = a[9] & b[9];
assign out[10] = a[10] & b[10];
assign out[11] = a[11] & b[11];
assign out[12] = a[12] & b[12];
assign out[13] = a[13] & b[13];
assign out[14] = a[14] & b[14];
assign out[15] = a[15] & b[15];
assign out[16] = a[16] & b[16];
assign out[17] = a[17] & b[17];
assign out[18] = a[18] & b[18];
assign out[19] = a[19] & b[19];
assign out[20] = a[20] & b[20];
assign out[21] = a[21] & b[21];
assign out[22] = a[22] & b[22];
assign out[23] = a[23] & b[23];
assign out[24] = a[24] & b[24];
assign out[25] = a[25] & b[25];
assign out[26] = a[26] & b[26];
assign out[27] = a[27] & b[27];
assign out[28] = a[28] & b[28];
assign out[29] = a[29] & b[29];
assign out[30] = a[30] & b[30];
assign out[31] = a[31] & b[31];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int limB = 1 << 20; const int limN = 20; bool usdA[limB][limN], usdB[limB][limN]; int ansA[limB][limN], ansB[limB][limN]; int ja(int n, int k); int jb(int n, int k); int ja(int n, int k) { if (k == 2) return n; if (usdA[n][k]) return ansA[n][k]; usdA[n][k] = true; int &ans = ansA[n][k]; ans = jb(n >> 1, k - 1); for (int i = 1; i < k; i++) { ans = min(ans, jb(((n >> (i + 1)) << i) + n % (1 << i), k - 1)); } return ans; } int jb(int n, int k) { if (k == 2) return n; if (usdB[n][k]) return ansB[n][k]; usdB[n][k] = true; int &ans = ansB[n][k]; ans = ja(n >> 1, k - 1); for (int i = 1; i < k; i++) { ans = max(ans, ja(((n >> (i + 1)) << i) + n % (1 << i), k - 1)); } return ans; } void pint(int n, int k) { int w = 0; for (int i = k - 1; i >= 0; i--) { printf( %d , (1 << i) & n ? 1 : 0); if ((1 << i) & n) w++; } printf( => %d n , w); } char str[limB]; int main() { scanf( %s , str); int mino = 0, maxo = 0, n = 0; char ut = ? ; for (char *c = str; *c; c++) { mino += *c == 1 ? 1 : 0; maxo += *c != 0 ? 1 : 0; ut = *c; n++; } n = (n + 1) / 2; if (mino <= n - 1) printf( 00 n ); if (mino <= n && n <= maxo) { if (ut == 1 || (ut == ? && mino + 1 <= n)) printf( 01 n ); if (ut == 0 || (ut == ? && n <= maxo - 1)) printf( 10 n ); } if (n + 1 <= maxo) printf( 11 n ); }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology sim models. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Changelog: 1) Removed unused VCC/GND modules
// > 2) Altera comments here (?). Removed.
// > 3) Reusing LUT sim model, removed wrong wires and parameters.
module PADIN (output padout, input padin);
assign padout = padin;
endmodule
module PADOUT (output padout, input padin, input oe);
assign padout = padin;
assign oe = oe;
endmodule
module LUT4 (output dout,
input din0, din1, din2, din3);
parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output q,
input d, ck);
reg q;
always @(posedge ck)
q <= d;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Metastability Hardened Registers
// /___/ /\ Filename : HARD_SYNC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 01/30/13 Initial version
// 05/08/13 712367 - fix blocking assignments
// 05/17/13 718960 - fix BIN encoding
// 05/17/13 719092 - remove SR, add IS_CLK_INVERTED
// 10/22/14 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module HARD_SYNC #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] INIT = 1'b0,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter integer LATENCY = 2
)(
output DOUT,
input CLK,
input DIN
);
// define constants
localparam MODULE_NAME = "HARD_SYNC";
// Parameter encodings and registers
localparam LATENCY_2 = 0;
localparam LATENCY_3 = 1;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "HARD_SYNC_dr.v"
`else
localparam [0:0] INIT_REG = INIT;
localparam [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
localparam [1:0] LATENCY_REG = LATENCY;
`endif
wire INIT_BIN;
wire IS_CLK_INVERTED_BIN;
wire LATENCY_BIN;
`ifdef XIL_XECLIB
tri0 glblGSR = 1'b0;
`else
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
`endif
wire CLK_in;
wire DIN_in;
`ifdef XIL_TIMING
wire CLK_delay;
wire DIN_delay;
`ifdef XIL_XECLIB
assign CLK_delay = CLK;
assign DIN_delay = DIN;
`endif
`endif
`ifdef XIL_TIMING
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_BIN;
assign DIN_in = DIN_delay;
`else
assign CLK_in = CLK ^ IS_CLK_INVERTED_BIN;
assign DIN_in = DIN;
`endif
assign INIT_BIN = INIT_REG;
assign IS_CLK_INVERTED_BIN = IS_CLK_INVERTED_REG;
assign LATENCY_BIN =
(LATENCY_REG == 2) ? LATENCY_2 :
(LATENCY_REG == 3) ? LATENCY_3 :
LATENCY_2;
`ifndef XIL_XECLIB
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((LATENCY_REG != 2) &&
(LATENCY_REG != 3))) begin
$display("Error: [Unisim %s-103] LATENCY attribute is set to %d. Legal values for this attribute are 2 or 3. Instance: %m", MODULE_NAME, LATENCY_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
reg [2:0] DIN_reg;
assign DOUT = (LATENCY_BIN == LATENCY_3) && DIN_reg[2] || (LATENCY_BIN == LATENCY_2) && DIN_reg[1];
always @ (posedge CLK_in or posedge glblGSR) begin
if (glblGSR == 1'b1) begin
DIN_reg <= {INIT_BIN, INIT_BIN, INIT_BIN};
end
else begin
DIN_reg <= {DIN_reg[1:0], DIN_in};
end
end
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_BIN;
assign clk_en_p = ~IS_CLK_INVERTED_BIN;
`endif
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, CLK_delay, DIN_delay);
$setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,clk_en_n,clk_en_n, CLK_delay, DIN_delay);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, CLK_delay, DIN_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,clk_en_p,clk_en_p, CLK_delay, DIN_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const long long N = 305; long long n, k; long long a[N][N], rows[N], cols[N]; long long sqr(long long x) { return x * x; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { cin >> n >> k; for (long long i = 0; i < n; i++) { rows[i] = cols[i] = 0; for (long long j = 0; j < n; j++) a[i][j] = 0; } long long sti = 0, i = 0, j = 0; while (k > 0) { if (a[i][j]) { sti++; i = sti, j = 0; } else { a[i][j] = 1; rows[i]++; cols[j]++; i++, j++; i %= n; j %= n; k--; } } long long ans = 0; sort(rows, rows + n); sort(cols, cols + n); ans += sqr(rows[n - 1] - rows[0]) + sqr(cols[n - 1] - cols[0]); cout << ans << n ; for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) cout << a[i][j]; cout << n ; } } return 0; }
|
module mul_plain(a, b, p);
parameter M = 6;
parameter N = 6;
input wire [M-1:0] a;
input wire [N-1:0] b;
output wire [M+N-1:0] p;
assign p = a * b;
endmodule
module mul_signed_async (clk, rst, en, a, b, p);
parameter M = 8;
parameter N = 6;
input wire signed clk, rst, en;
input wire signed [M-1:0] a;
input wire signed [N-1:0] b;
output reg signed [M+N-1:0] p;
reg signed [M-1:0] a_reg;
reg signed [N-1:0] b_reg;
// signed M*N multiplier with
// - input and output pipeline registers
// - asynchronous reset (active high)
// - clock enable (active high)
always @(posedge clk or posedge rst)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
module mul_unsigned_sync (clk, rst, en, a, b, p);
parameter M = 6;
parameter N = 3;
input wire clk, rst, en;
input wire [M-1:0] a;
input wire [N-1:0] b;
output reg [M+N-1:0] p;
reg [M-1:0] a_reg;
reg [N-1:0] b_reg;
// unsigned M*N multiplier with
// - input and output pipeline registers
// - synchronous reset (active high)
// - clock enable (active high)
always @(posedge clk)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool chkmin(T &x, T y) { return y < x ? x = y, 1 : 0; } template <class T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } inline long long Max(long long x, long long y) { return x > y ? x : y; } inline long long Min(long long x, long long y) { return x < y ? x : y; } int n, m; long long dp[2002][2002]; void Add(long long &x, long long y) { x += y; if (x >= 1000000007) x %= 1000000007; if (x < 0) (x += 1000000007) %= 1000000007; } int main() { scanf( %d%d , &n, &m); for (int i = (1), i_end_ = (n); i <= i_end_; i++) dp[i][1] = 1; for (int k = (2), k_end_ = (m); k <= k_end_; k++) for (int i = (1), i_end_ = (n); i <= i_end_; i++) for (int j = i; j <= n; j += i) Add(dp[j][k], dp[i][k - 1]); long long ans = 0; for (int i = (1), i_end_ = (n); i <= i_end_; i++) Add(ans, dp[i][m]); printf( %I64d n , ans); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4B_4_V
`define SKY130_FD_SC_HDLL__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4B_4_V
|
//
// Prof. Taylor 7/24/2014
// <>
//
// Updated by Paul Gao 02/2019
//
// DDR or center/edge-aligned SDR source synchronous input channel
//
// this implements:
// incoming source-synchronous capture flops
// async fifo to go from source-synchronous domain to core domain
// outgoing token channel to go from core domain deque to out of chip
// outgoing source-synchronous launch flops for token
//
// note, the default FIFO depth is set to 2^6 based on experiments on FPGA
// FIXME: update these numbers based on clocks in each clock domain and from actual waveforms.
//
// Below is a rough calculation:
//
// 2 clks for channel crossing
// 3 clks for receive fifo crossing
// 1 clk for deque
// 3 clks for receive token fifo crossing
// 4 clks for token decimation
// 2 clks for channel crossing
// 3 clks for sender token fifo crossing
// 1 clk for sender credit counter adjust
// -----------
// 19 clks
//
// This leaves us with 45 elements of margin
// for FPGA inefficiency. Since the FPGA may run
// at 4X slower, this is equivalent to 3 FPGA cycles.
//
// Aside: SERDES make bandwidth-delay product much worse
// because they simultaneously increase bandwidth and delay!
//
// io_*: signals synchronous to io_clk_i
// core_*: signals synchronous to core_clk_i
//
`include "bsg_defines.v"
module bsg_link_source_sync_downstream
#(parameter channel_width_p = 16
,parameter lg_fifo_depth_p = 6
,parameter lg_credit_to_token_decimation_p = 3
// When the async_fifo is not on critical path (e.g. when async_fifo size
// is small), bypass twofer fifo to minimize buffering and latency
,parameter bypass_twofer_fifo_p = 0
,parameter use_hardened_fifo_p = 0
)
(// control signals
input core_clk_i
,input core_link_reset_i
,input io_link_reset_i
// coming from IDDR PHY near the physical I/O. valid_i and data_i signals are assumed to be
// registered, but may be traversing long wires on the top level to reach this module.
,input io_clk_i // sdi_sclk
,input [channel_width_p-1:0] io_data_i // sdi_data
,input io_valid_i // sdi_valid
,output core_token_r_o // sdi_token; output registered
// going into core; uses core clock
,output [channel_width_p-1:0] core_data_o
,output core_valid_o
,input core_yumi_i
);
// ******************************************
// clock-crossing async fifo (with DDR interface)
//
// Note that this async fifo also serves as receive buffer
// The buffer size depends on lg_fifo_depth_p (must match bsg_link_source_sync_upstream)
//
// With token based flow control, fifo should never overflow
// io_async_fifo_full signal is only for debugging purposes
//
wire io_async_fifo_full, io_async_fifo_enq;
logic io_fifo_valid_lo, io_fifo_ready_lo;
logic [channel_width_p-1:0] io_async_fifo_data;
// synopsys translate_off
always_ff @(negedge io_clk_i)
assert(!(io_fifo_ready_lo===0 && io_valid_i===1))
else $error("attempt to enque on full async fifo");
// synopsys translate_on
if (use_hardened_fifo_p == 0)
begin
assign io_async_fifo_enq = io_valid_i;
assign io_async_fifo_data = io_data_i;
assign io_fifo_ready_lo = ~io_async_fifo_full;
end
else
begin: harden
assign io_async_fifo_enq = io_fifo_valid_lo & ~io_async_fifo_full;
bsg_fifo_1r1w_small
#(.width_p (channel_width_p)
,.els_p (1<<lg_fifo_depth_p)
,.harden_p(1)
) fifo
(.clk_i (io_clk_i)
,.reset_i (io_link_reset_i)
,.v_i (io_valid_i)
,.ready_o (io_fifo_ready_lo)
,.data_i (io_data_i)
,.v_o (io_fifo_valid_lo)
,.data_o (io_async_fifo_data)
,.yumi_i (io_async_fifo_enq)
);
end
wire core_async_fifo_deque, core_async_fifo_valid_lo;
logic [channel_width_p-1:0] core_async_fifo_data_lo;
bsg_async_fifo
#(.lg_size_p((use_hardened_fifo_p==0)?lg_fifo_depth_p:3)
,.width_p(channel_width_p)
) baf
(.w_clk_i (io_clk_i)
,.w_reset_i(io_link_reset_i)
,.w_enq_i (io_async_fifo_enq)
,.w_data_i (io_async_fifo_data)
,.w_full_o (io_async_fifo_full)
,.r_clk_i (core_clk_i)
,.r_reset_i(core_link_reset_i)
,.r_deq_i (core_async_fifo_deque)
,.r_data_o (core_async_fifo_data_lo)
,.r_valid_o(core_async_fifo_valid_lo));
if (bypass_twofer_fifo_p == 0)
begin
wire core_async_fifo_ready_li;
// Oct 17, 2014
// we insert a minimal fifo here for two purposes;
// first, this reduces critical
// paths causes by excessive access times of the async fifo.
//
// second, it ensures that asynchronous paths end inside of this module
// and do not propogate out to other modules that may be attached, complicating
// timing assertions.
//
bsg_two_fifo
#(.width_p(channel_width_p)
) twofer
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
// we feed this into the local yumi, but only if it is valid
,.ready_o(core_async_fifo_ready_li)
,.data_i (core_async_fifo_data_lo)
,.v_i (core_async_fifo_valid_lo)
,.v_o (core_valid_o)
,.data_o (core_data_o)
,.yumi_i (core_yumi_i)
);
// a word was transferred to fifo if ...
assign core_async_fifo_deque = core_async_fifo_valid_lo & core_async_fifo_ready_li;
end
else
begin
// keep async_fifo isolated when reset is asserted
assign core_valid_o = (core_link_reset_i)? 1'b0 : core_async_fifo_valid_lo;
assign core_data_o = core_async_fifo_data_lo;
assign core_async_fifo_deque = core_yumi_i;
end
// **********************************************
// credit return
//
// these are credits coming from the receive end of the async fifo in the core clk
// domain and passing to the io clk domain and out of the chip.
//
logic [lg_credit_to_token_decimation_p+1-1:0] core_credits_sent_r;
// which bit of the core_credits_sent_r counter we use determines
// the value of the token line in credits
//
//
// this signal's register should be placed right next to the I/O pad:
// glitch sensitive.
assign core_token_r_o = core_credits_sent_r[lg_credit_to_token_decimation_p];
// Increase token counter when dequeue from async fifo
bsg_counter_clear_up
#(.max_val_p({(lg_credit_to_token_decimation_p+1){1'b1}})
,.init_val_p(0)
,.disable_overflow_warning_p(1) // Allow overflow for this counter
)
token_counter
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.clear_i(1'b0)
,.up_i (core_async_fifo_deque)
,.count_o(core_credits_sent_r)
);
endmodule // bsg_source_sync_input
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4B_PP_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_PP_BLACKBOX_V
|
//
// Copyright (c) 2002 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic reg form
//
//
module basicreg ( clk, d, q);
input clk, d;
output [2:0] q;
reg [2:0] q;
(* ivl_synthesis_on *)
always @(posedge clk)
begin
q[0] <= d;
q[1] <= d;
q[2] <= d;
end
endmodule
module test ;
reg clk, d;
wire [2:0] q;
basicreg u_reg (clk,d,q);
(* ivl_synthesis_off *)
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
clk = 0;
d = 0;
# 1;
clk = 1;
# 1;
if (q !== 3'b0)
begin
$display("FAILED - Q isn't 0 on first edge");
$finish;
end
d = 1;
# 1;
clk = 0;
# 1;
if (q !== 3'b0)
begin
$display("FAILED - Q isn't 0 after first falling edge");
$finish;
end
# 1;
clk = 1;
# 1;
if (q !== 3'b111)
begin
#1 ;
$display("FAILED - Q isn't 1 2nd raising edge");
$finish;
end
# 1;
clk = 0;
# 1;
if (q !== 3'b111)
begin
$display("FAILED - Q isn't 1 after 2nd falling edge");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct P { int x, y, z; bool operator<(const P &a) const { return y > a.y; }; }; int a, b, c, d, i, k, n, m, e, dx[10] = {1, 0, -1, 0, 1, 1, -1, -1}, dy[10] = {0, 1, 0, -1, 1, -1, 1, -1}; long long o[500101]; int l[500111]; int j[201001]; long long x, y, z, mod = 998244353; string r; P u[500101]; queue<int> q; stack<int> s; map<int, int> p; vector<int> v; bool as(P a, P b) { if (a.x != b.x) return a.x < b.x; return a.y > b.y; } int main() { scanf( %d %d %d , &a, &b, &c); for (int t = 1; t <= c; t++) { scanf( %d %d %d , &n, &m, &k); u[t] = {n, m, k}; } sort(u + 1, u + c + 1, as); z = 1; for (int i = 0; i < b; i++) { e = 0; for (int t = 1; t <= a + 1; t++) l[t] = o[t] = 0; for (int t = 1; t <= c; t++) if (u[t].z & (1 << i)) { int p; for (p = max(e + 1, u[t].x); p <= u[t].y; p++) l[p] = 1; e = p - 1; } e = a + 1; n = a; o[a + 1] = 1; x = 1; for (int t = c; t; t--) if ((u[t].z & (1 << i)) == 0 && u[t].x <= n) { for (; n > u[t].y; n--) if (!l[n]) o[n] = x, x *= 2, x %= mod; for (; n >= u[t].x; n--) if (!l[n]) { o[n] = x, x *= 2, x %= mod; } for (; e > u[t].y; e--) x = (x - o[e] + mod) % mod; } for (; n >= 1; n--) if (!l[n]) x *= 2, x %= mod; z *= x, z %= mod; } printf( %lld , z); }
|
#include <bits/stdc++.h> using namespace std; int a[123][123], b[123][123], f1[54][54][54][54], f2[54][54][54][54]; int n; void getans(int i1, int j1, int i2, int j2) { int i, j, t; printf( ? %d %d %d %d n , i1, j1, i2, j2); fflush(stdout); scanf( %d , &t); if (t == f1[i1][j1][i2][j2]) { printf( ! n ), fflush(stdout); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) printf( %d , (1 + a[i][j]) / 2); printf( n ); } } else { printf( ! n ), fflush(stdout); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) printf( %d , (1 + b[i][j]) / 2); printf( n ); } } exit(0); } int main() { int i, j, i1, i2, j1, j2, t, j3, i3; scanf( %d , &n); a[1][1] = 1, a[n][n] = -1; for (i = 1; i <= n; i++) for (j = 2 - (i % 2); j <= n; j += 2) { if (!a[i][j]) { if (a[i - 1][j - 1]) { printf( ? %d %d %d %d n , i - 1, j - 1, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i - 1][j - 1]; else a[i][j] = a[i - 1][j - 1]; continue; } if (i > j) { printf( ? %d %d %d %d n , i - 2, j, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i - 2][j]; else a[i][j] = a[i - 2][j]; continue; } else { printf( ? %d %d %d %d n , i, j - 2, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i][j - 2]; else a[i][j] = a[i][j - 2]; continue; } } } a[1][2] = 1; for (i = 1; i <= n; i++) for (j = 3 - (i % 2); j <= n; j += 2) { if (!a[i][j]) { if (a[i - 1][j - 1]) { printf( ? %d %d %d %d n , i - 1, j - 1, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i - 1][j - 1]; else a[i][j] = a[i - 1][j - 1]; continue; } if (i > j - 1) { printf( ? %d %d %d %d n , i - 2, j, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i - 2][j]; else a[i][j] = a[i - 2][j]; continue; } else { printf( ? %d %d %d %d n , i, j - 2, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i][j - 2]; else a[i][j] = a[i][j - 2]; continue; } } } printf( ? %d %d %d %d n , 2, 1, 3, 2); fflush(stdout); scanf( %d , &t); if (!t) a[2][1] = -a[3][2]; else a[2][1] = a[3][2]; j = 1; for (i = 4; i <= n; i += 2) { printf( ? %d %d %d %d n , i - 2, j, i, j); fflush(stdout); scanf( %d , &t); if (!t) a[i][j] = -a[i - 2][j]; else a[i][j] = a[i - 2][j]; continue; } for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) b[i][j] = (((i + j) & 1) ? -a[i][j] : a[i][j]); for (i3 = 0; i3 < n; i3++) for (j3 = 0; j3 < n; j3++) { for (i2 = i3 + 1; i2 <= n; i2++) for (j2 = j3 + 1; j2 <= n; j2++) { i1 = i2 - i3, j1 = j2 - j3; if (i1 == i2 && j1 == j2) f1[i1][j1][i2][j2] = 1, f2[i1][j1][i2][j2] = 1; else if (i2 + j2 - i1 - j1 == 1) { f1[i1][j1][i2][j2] = (a[i1][j1] == a[i2][j2]); f2[i1][j1][i2][j2] = (b[i1][j1] == b[i2][j2]); } else { if (a[i1][j1] == a[i2][j2] && (f1[i1 + 1][j1][i2 - 1][j2] || f1[i1][j1 + 1][i2][j2 - 1] || f1[i1 + 1][j1][i2][j2 - 1] || f1[i1][j1 + 1][i2 - 1][j2])) f1[i1][j1][i2][j2] = 1; else f1[i1][j1][i2][j2] = 0; if (b[i1][j1] == b[i2][j2] && (f2[i1 + 1][j1][i2 - 1][j2] || f2[i1][j1 + 1][i2][j2 - 1] || f2[i1 + 1][j1][i2][j2 - 1] || f2[i1][j1 + 1][i2 - 1][j2])) f2[i1][j1][i2][j2] = 1; else f2[i1][j1][i2][j2] = 0; if (f1[i1][j1][i2][j2] != f2[i1][j1][i2][j2]) getans(i1, j1, i2, j2); } } } }
|
#include <bits/stdc++.h> using namespace std; int n, u, r; int a[35]; int b[35]; int k[35]; int p[35]; int op[35]; int tmpa[35]; int tmmmma[35]; long long dfs(int index, const int ta[]) { if (index == u) { long long res = 0; for (int i = (0); i < ((n)); ++i) res += (long long)ta[i] * k[i]; return res; } int tta[35]; long long res = -(((long long)1) << 62); if (index == 0 || op[index - 1] != 0) { op[index] = 0; for (int i = (0); i < ((n)); ++i) tta[i] = ta[i] ^ b[i]; res = max(res, dfs(index + 1, tta)); } op[index] = 1; for (int i = (0); i < ((n)); ++i) tta[i] = ta[p[i]] + r; res = max(res, dfs(index + 1, tta)); if ((u - index) % 2 == 0) { long long tmp = 0; for (int i = (0); i < ((n)); ++i) tmp += (long long)ta[i] * k[i]; res = max(res, tmp); } return res; } int main(void) { cin >> n >> u >> r; for (int i = (0); i < ((n)); ++i) cin >> a[i]; for (int i = (0); i < ((n)); ++i) cin >> b[i]; for (int i = (0); i < ((n)); ++i) cin >> k[i]; for (int i = (0); i < ((n)); ++i) cin >> p[i]; for (int i = (0); i < ((n)); ++i) --p[i]; cout << dfs(0, a) << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, x, y; int a[1000]; bool inrange(int v) { return (v >= x && v <= y); } int main() { ios ::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; a[i] = a[i - 1] + a[i]; } cin >> x >> y; for (int i = 1; i <= n; i++) if (inrange(a[i - 1]) && inrange(a[n] - a[i - 1])) { cout << i; return 0; } cout << 0; return 0; }
|
#include <bits/stdc++.h> int k, x, y; using namespace std; int main() { scanf( %d , &k); x = 1000000 - k % 2000; y = (k + x - 2000 * x) / 2000; printf( 2000 n ); for (int i = 1; i <= 1998; i++) printf( 0 ); printf( %d %d n , y, x); }
|
#include <bits/stdc++.h> using namespace std; int N; long long M; int A[200002], B[200002]; map<int, int> MP; vector<pair<long long, long long> > ST; long long getover(pair<long long, long long> p, int i2) { if (p.second >= ST[i2].second) return 0; return (ST[i2].second - p.second) / (p.first - ST[i2].first) + ((ST[i2].second - p.second) % (p.first - ST[i2].first) != 0); } long long getover(int i1, int i2) { if (ST[i1].second >= ST[i2].second) return 0; return (ST[i2].second - ST[i1].second) / (ST[i1].first - ST[i2].first) + ((ST[i2].second - ST[i1].second) % (ST[i1].first - ST[i2].first) != 0); } int main() { cin.sync_with_stdio(false); cin >> N >> M; int bestinit = 0; for (int i = 1; i <= N; ++i) { cin >> A[i] >> B[i]; if (B[i] == 0) bestinit = max(bestinit, A[i]); if (MP.find(A[i]) == MP.end()) MP[A[i]] = 0x3f3f3f3f; MP[A[i]] = min(MP[A[i]], B[i]); } ST.push_back(make_pair(bestinit, 0)); for (map<int, int>::iterator it = MP.begin(); it != MP.end(); ++it) { if (it->first <= bestinit) continue; int step = (1 << 17), now = 0; for (; step; step >>= 1) if (now + step < int(ST.size()) && 1LL * ST[now + step - 1].first * (getover(now + step, now + step - 1) - 1) + ST[now + step - 1].second < it->second) now += step; step = (1 << 30); int pos = 0; for (; step; step >>= 1) if (ST[now].first * (pos + step - 1) + ST[now].second < it->second) pos += step; int rem = ST[now].first * pos + ST[now].second - it->second; pair<long long, long long> pnow = make_pair(it->first, rem - 1LL * it->first * pos); while (ST.size() >= 2 && getover(pnow, ST.size() - 1) <= getover(ST.size() - 1, ST.size() - 2)) ST.pop_back(); ST.push_back(pnow); } int step = (1 << 17), now = 0; for (; step; step >>= 1) if (now + step < int(ST.size()) && 1LL * ST[now + step - 1].first * (getover(now + step, now + step - 1) - 1) + ST[now + step - 1].second < M) now += step; long long times = 100000000 + M / ST.back().first; long long astep = 1; while (astep <= times) astep *= 2; long long pos = 0; for (; astep; astep >>= 1) if (ST[now].first * (pos + astep - 1) + ST[now].second < M) pos += astep; cout << pos << n ; }
|
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-6; const long double pi = acos(-1.0); int dx[] = {0, 1, 0, -1, 1, 1, -1, -1, 0}, dy[] = {1, 0, -1, 0, 1, -1, 1, -1, 0}; int aq[5][5]; int main() { int n; cin >> n; for (int i = 0; i < (int)(n); ++i) { int x, y; cin >> x >> y; aq[x - 1][y - 1] = aq[y - 1][x - 1] = 1; } int ap = 0, nap = 0; for (int i = 0; i < (int)(5); ++i) for (int j = 0; j < (int)(i); ++j) for (int k = 0; k < (int)(j); ++k) { if (aq[i][j] && aq[j][k] && aq[k][i]) ap = 1; if (!aq[i][j] && !aq[j][k] && !aq[k][i]) nap = 1; } if (ap || nap) cout << WIN << endl; else cout << FAIL << endl; }
|
#include <bits/stdc++.h> using namespace std; static int io_sync_off = []() { ios::sync_with_stdio(false); cin.tie(nullptr); return 0; }(); long long Pow(long long a, long long b, long long mod) { long long res = 1; a %= mod; while (b) { if (b & 1) (res *= a) %= mod; (a *= a) %= mod; b >>= 1; } return res % mod; } long long inv(long long a, long long p) { if (a == 1) return 1; return (p - p / a) * inv(p % a, p) % p; } long long C(long long n, long long m, long long p) { long long res = 1; for (long long i = 1, j = n - m + 1; i <= m; ++i, ++j) { res = res * inv(i, p) % p * j % p; } return res; } const int N = 2e5 + 10; struct M { bool operator<(const M &t) const { return x < t.x; } int x, y, z; }; long long Max[N * 4], tag[N * 4]; void push_down(int o) { int lc = 2 * o, rc = 2 * o + 1; tag[lc] += tag[o]; tag[rc] += tag[o]; Max[lc] += tag[o]; Max[rc] += tag[o]; tag[o] = 0; } void update(int a, int b, int v, int o, int l, int r) { if (a == b) return; if (a <= l && b >= r) { tag[o] += v; Max[o] += v; return; } push_down(o); int mid = (l + r) >> 1, lc = 2 * o, rc = 2 * o + 1; if (a < mid) update(a, b, v, lc, l, mid); if (b > mid) update(a, b, v, rc, mid, r); Max[o] = max(Max[lc], Max[rc]); } M Mon[N]; pair<long long, long long> a[N], b[N]; int d[N]; void build(int o, int l, int r) { if (r - l == 1) { Max[o] = -b[l].second; return; } int mid = (l + r) >> 1, lc = 2 * o, rc = 2 * o + 1; build(lc, l, mid); build(rc, mid, r); Max[o] = max(Max[lc], Max[rc]); } int main() { int n, m, p; scanf( %d%d , &n, &m); scanf( %d , &p); for (int i = 0; i < n; ++i) scanf( %d%d , &a[i].first, &a[i].second); for (int i = 0; i < m; ++i) scanf( %d%d , &b[i].first, &b[i].second); for (int i = 0; i < p; ++i) scanf( %d%d%d , &Mon[i].x, &Mon[i].y, &Mon[i].z); sort(a, a + n); sort(b, b + m); sort(Mon, Mon + p); for (int i = 0; i < m; ++i) d[i] = b[i].first; build(1, 0, m); long long ans = -1e18; int j = 0; for (int i = 0; i < n; ++i) { while (j < p && Mon[j].x < a[i].first) { int l = upper_bound(d, d + m, Mon[j].y) - d; update(l, m, Mon[j++].z, 1, 0, m); } ans = max(ans, Max[1] - a[i].second); } printf( %lld , ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
// verilator lint_off WIDTH
// verilator lint_off VARHIDDEN
module t (
clk
);
input clk;
integer cyc=0;
reg [63:0] crc; initial crc = 64'h1;
chk chk (.clk (clk),
.rst_l (1'b1),
.expr (|crc)
);
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module chk (input clk, input rst_l, input expr);
integer errors; initial errors = 0;
task printerr;
input [8*64:1] msg;
begin
errors = errors + 1;
$write("%%Error: %0s\n", msg);
$stop;
end
endtask
always @(posedge clk) begin
if (rst_l) begin
if (expr == 1'b0) begin
printerr("expr not asserted");
end
end
end
wire noxs = ((expr ^ expr) == 1'b0);
reg hasx;
always @ (noxs) begin
if (noxs) begin
hasx = 1'b0;
end
else begin
hasx = 1'b1;
end
end
always @(posedge clk) begin
if (rst_l) begin
if (hasx) begin
printerr("expr has unknowns");
end
end
end
endmodule
|
// File: ./ex-target/Rectifier.v
// Generated by MyHDL 1.0dev
// Date: Mon Oct 5 14:11:09 2015
`timescale 1ns/10ps
module Rectifier (
y,
y_dx,
x
);
// Rectified linear unit (ReLU) and derivative model using fixbv type.
//
// :param y: return max(0, x) as fixbv
// :param y_dx: return d/dx max(0, x) as fixbv
// :param x: input value as fixbv
// :param leaky_val: factor for leaky ReLU, 0.0 without
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output signed [15:0] y_dx;
reg signed [15:0] y_dx;
input signed [15:0] x;
always @(x) begin: RECTIFIER_RELU
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
if ((x > zero)) begin
y = x;
end
else begin
y = fixbv((leaky * x));
end
end
always @(x) begin: RECTIFIER_RELU_DX
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
reg signed [16-1:0] one;
if ((x > zero)) begin
y_dx = one;
end
else begin
y_dx = leaky;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_M_V
`define SKY130_FD_SC_LP__OR4BB_M_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_m (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_m (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_M_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013, David M. Lloyd
//
// This file is part of the PBIBox suite.
//
// PBIBox is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// PBIBox is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with PBIBox. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
module EtherPBI(
inout tri [15:0] SysAddr,
input wire Phi2,
// 28Mhz (phi2 times 16)
input wire CLK1,
// ignored for now
input wire CLK2,
// always 1
output wire S0,
// always 0
output wire S1,
output tri MPD,
inout tri RdWr,
output wire OE,
output wire RamCS,
output wire RomCS,
// Addr 0-9 on W5300; bank address 0-4 on RAM and 0-7 on ROM
output wire [9:0] AddrOut,
inout tri [7:0] Data,
input wire [2:0] ID,
output tri IRQ,
output tri DmaReqOut,
input wire DmaAckIn,
input wire Halt,
input wire Reset,
input wire SpiDI,
output wire SpiDO,
output wire SpiCK,
output wire SpiCS,
output wire DeviceWr,
output wire DeviceRd,
output wire DeviceCS,
output tri EXTSEL,
input wire DeviceInt
);
reg [3:0] ClkPhase;
reg [2:0] DevID;
reg [5:0] RamBank;
reg [7:0] RomBank;
reg [3:0] DeviceBank;
reg [15:0] DmaAddr;
reg [15:0] DmaCount;
reg DmaReq;
reg DmaCycle;
reg DmaRead; /* Read from device, write to RAM if 1, Write to device, read from RAM if 0 */
reg DmaOdd;
reg DmaOddPickup; /* Blank read/write to align FIFO access */
reg ReadWrite; /* 1 = read, 0 = write, latched */
reg W5300Sel; /* 1 = selected */
reg RamSel; /* 1 = selected */
reg RomSel; /* 1 = selected */
reg Selected;
reg SpiBit;
reg SpiSel;
reg SpiClkSig;
// There are three parts of the clock we care about
// 1: Start of phase 1 (negative edge phi2) - all input data should be sampled at this time
// 2: Phase 1 plus 35 nS - all latched or held output data should be dropped at this time
// 8: Start of phase 2 (positive edge phi2) - addresses should be sampled at this time, and chip selects enabled
// 15: Just before start of phase 1 (negative edge phi2) - update DmaCycle latch
always @(negedge CLK1) begin
if (Reset == 1'b0) begin
/* sync clock */
if (Phi2 == 1'b0 && ClkPhase[3] != 1'b0) begin
ClkPhase <= {Phi2,3'b0};
end
/* Reset! */
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
DevID <= ID;
end else begin
/* next clock phase */
ClkPhase <= ClkPhase + 1;
/* test current clock phase */
if (ClkPhase == 4'b0000) begin
if (DmaCycle) begin
if (DmaRead == 1'b0) begin
if (DmaCount == 1) begin
DmaCount <= 0;
if (DmaOdd) begin
// one dummy cycle needed
DmaOdd <= 0;
end else begin
// last cycle
DmaReq <= 0;
end
end else begin
DmaOdd <= ! DmaOdd;
DmaCount <= DmaCount - 1;
DmaAddr <= DmaAddr + 1;
end
end
end else if (ReadWrite == 1'b0) begin
// sample inputs and perform write operation
if (SysAddr[15:7] == 9'b110100010 && Selected) begin // First 127 bytes
RomBank[7:0] <= SysAddr[7:0];
end else if (SysAddr[15:4] == 12'b110100011100 && Selected) begin // D1Cx
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr[15:3] == 13'b1101000111010 && Selected) begin // D1D0-7
SpiBit <= Data[SysAddr[2:0]];
end else if (SysAddr[15:0] == 16'b1101000111010100 && Selected) begin // D1D8
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010101 && Selected) begin // D1D9
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010110 && Selected) begin // D1DA
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr[15:0] == 16'b1101000111010111 && Selected) begin // D1DB
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr[15:1] == 15'b110100011101100 && Selected) begin // D1DC-DD
// Start DMA
DmaReq <= 1;
DmaRead <= SysAddr[0];
DmaOdd <= DmaCount[0];
end else if (SysAddr[15:1] == 15'b110100011101101 && Selected) begin // D1DE-DF
SpiClkSig <= SysAddr[0];
end else if (SysAddr[15:0] == 16'b1101000111111111) begin
Selected <= Data == 8'b1 << DevID; // disable on conflict
end else if (SysAddr[15:5] == 11'b11010001111 && Selected) begin // D1E0-D1FE
RamBank[4:0] <= SysAddr[4:0];
end
end
end else if (ClkPhase == 4'b0001 && ReadWrite == 1'b1) begin
// clear holds from read operation
W5300Sel <= 0;
RamSel <= 0;
RomSel <= 0;
end else if (ClkPhase == 4'b1000) begin
// Sample all address info and enable read operation
ReadWrite <= RdWr;
end else if (ClkPhase == 4'b1111) begin
// Check if the next cycle will be a DMA cycle
DmaCycle <= DmaReq && DmaAckIn && Halt;
end
end
end
always @(negedge Phi2) begin
if (Reset == 1'b0) begin
DeviceBank <= 0;
DmaAddr <= 0;
DmaCount <= 0;
DmaCycle <= 0;
RamAddr <= 0;
RomAddr <= 0;
Selected <= 0;
DmaReq <= 0;
SpiBit <= 0;
SpiSel <= 0;
end else begin
if ((DmaReq & !Halt) == 1'b1) begin
/* Just *starting* a DMA cycle */
DmaCycle <= 1'b1;
if (DmaOddPickup == 1'b1 || DmaCount == 16'h1 && DmaOdd == 1'b0) begin
/* Will be the last cycle */
DmaReq <= 0;
end
end else begin
DmaCycle <= 1'b0;
end
if (DmaCycle == 1'b1) begin
/* Just *finishing* a DMA cycle */
if (DmaOddPickup == 1'b0) begin
/* actual cycle */
if (DmaCount == 16'h1) begin
/* Last DMA cycle (maybe) */
if (DmaOdd == 1'b1) begin
/* One more cycle to align */
DmaOdd <= 0;
DmaOddPickup <= 1'b1;
end else begin
/* Next cycle is the last DMA cycle */
DmaRead <= 0;
DmaReq <= 0;
end
end
DmaAddr <= DmaAddr + 1;
DmaCount <= DmaCount - 1;
end
end else if ((Selected & RdWr) == 1'b0) begin
/* Just *finishing* a non-DMA cycle */
/* register loads */
if (SysAddr[15:6] == ('hD100 >> 6)) begin
RamAddr[13:8] <= SysAddr[5:0];
end else if (SysAddr[15:6] == ('hD140 >> 6)) begin
RomAddr[15:10] <= SysAddr[5:0];
// D180..D1BF = W5300 access
end else if (SysAddr[15:4] == ('hD1E0 >> 4)) begin
DeviceBank[3:0] <= SysAddr[3:0];
end else if (SysAddr == 'hD1F7) begin
DmaAddr[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1F8) begin
DmaAddr[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1F9) begin
DmaCount[7:0] <= Data[7:0];
end else if (SysAddr == 'hD1FA) begin
DmaCount[15:8] <= Data[7:0];
end else if (SysAddr == 'hD1FB) begin
// initiate DMA transfer, bit 0 = R/!W
DmaRead <= Data[0];
DmaOddPickup <= 0;
DmaOdd <= DmaCount[0];
DmaReq <= 1'b1;
// D1FC = /HALT detect (read only)
end else if (SysAddr == 'hD1FD) begin
SpiSel <= Data[0]; // Write 1 to select SPI, 0 to deselect
end else if (SysAddr == 'hD1FE) begin
SpiBit <= Data[7]; // MSB first, left shift to empty register
SpiClkSig <= 1'b1;
end else if (SysAddr == 'hD1FF) begin
Selected <= Dx;
end
end
end
if (SpiBit == 1'b1) begin
SpiBit <= 0;
end
if (SpiClkSig == 1'b1) begin
SpiClkSig <= 0;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_synch:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_synch,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_synch_0_0,frequency_analyzer_synch,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_synch_0_0,frequency_analyzer_synch,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_synch,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CLOCK=100000000,FREQUENCY=2000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_synch_0_0 (
clock,
reset,
enable,
start_analyzer_0,
stop_analyzer_0,
start_analyzer_1,
stop_analyzer_1
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *)
input wire clock;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
input wire reset;
input wire enable;
output wire start_analyzer_0;
output wire stop_analyzer_0;
output wire start_analyzer_1;
output wire stop_analyzer_1;
frequency_analyzer_synch #(
.CLOCK(100000000),
.FREQUENCY(2000)
) inst (
.clock(clock),
.reset(reset),
.enable(enable),
.start_analyzer_0(start_analyzer_0),
.stop_analyzer_0(stop_analyzer_0),
.start_analyzer_1(start_analyzer_1),
.stop_analyzer_1(stop_analyzer_1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { vector<string> s(9); for (long long int i = 0; i < 9; i++) { cin >> s[i]; } s[0][0] = s[0][1]; s[1][3] = s[1][4]; s[2][6] = s[2][7]; s[3][1] = s[3][2]; s[4][4] = s[4][5]; s[5][7] = s[5][8]; s[6][2] = s[6][1]; s[7][5] = s[7][4]; s[8][8] = s[8][7]; for (long long int i = 0; i < 9; i++) { cout << s[i] << endl; } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:47:47 10/02/2013
// Design Name:
// Module Name: VGA_Control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// RESOLUCION DE 640 x 480 con una frecuencia de refresh de 60Hz
// y un CLOCK de 25Mhz.
//////////////////////////////////////////////////////////////////////////////////
module VGA_Control(clock, reset, actual_x, actual_y, h_sync, v_sync);
input clock, reset;
output reg h_sync, v_sync;
/**
* Estas variables indican la posicion por la que se va escribiendo
* en pantalla en una resolucion de 640x480.
* X va de 0 a 639
* Y va de 0 a 479
*/
output [9:0] actual_x;
output [8:0] actual_y;
/** Se declaran las variables que recorren toda la pantalla */
reg [9:0] hcounter, vcounter;
initial
begin
hcounter <= 10'b0;
vcounter <= 10'b0;
end
/**
* Asigna los valores de X y Y
* hcounter counts from 0 to 799
* vcounter counts from 0 to 520
* x coordinate: 0 - 639 (x = hcounter - 144, i.e., hcounter -Tpw-Tbp)
* y coordinate: 0 - 479 (y = vcounter - 31, i.e., vcounter-Tpw-Tbp)
*/
assign actual_x = hcounter - 144;
assign actual_y = vcounter - 31;
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
hcounter <= 10'b0;
vcounter <= 10'b0;
end /** Fin reset */
else
begin
/**
* Here is the timing for horizontal synchronization.
* (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
* Pulse width: Tpw = 96 cycles @ 25 MHz
* Back porch: Tbp = 48 cycles
* Display time: Tdisp = 640 cycles
* Front porch: Tfp = 16 cycles
* Sync pulse time (total cycles) Ts = 800 cycles
*/
if( (hcounter > 10'd0) && (hcounter < 10'd97) ) /** Pulse width: Tpw = 96 cycles */
begin
h_sync <= 1'b0;
end
else
begin
h_sync <= 1'b1;
end
/**
* Here is the timing for vertical synchronization.
* (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
* Pulse width: Tpw = 1600 cycles (2 lines) @ 25 MHz
* Back porch: Tbp = 23200 cycles (29 lines)
* Display time: Tdisp = 38400 cycles (480 lines)
* Front porch: Tfp = 8000 cycles (10 lines)
* Sync pulse time (total cycles) Ts = 416800 cycles (521 lines)
*/
if( (vcounter > 10'd0) && (vcounter < 10'd3) ) /** Pulse width: Tpw = 2 cycles */
begin
v_sync <= 1'b0;
end
else
begin
v_sync <= 1'b1;
end
/** horizontal counts from 0 to 799 */
hcounter <= hcounter + 1;
if(hcounter == 10'd800)
begin
vcounter <= vcounter + 1;
hcounter <= 10'b0;
end
/** vertical counts from 0 to 520 */
if(vcounter == 10'd521)
begin
vcounter <= 10'b0;
end
end /** Fin else (NO reset) */
end /** Fin del always */
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File_communication.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_comm.v,v $
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
`ifdef DBG_IF_COMM
`include "timescale.v"
`include "dbg_defines.v"
`include "dbg_tb_defines.v"
`define GDB_IN "/projects/xess-damjan/sim/run/gdb_in.dat"
`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
//`define GDB_IN "/tmp/gdb_in.dat"
//`define GDB_OUT "/tmp/gdb_out.dat"
//`define GDB_IN "../src/gdb_in.dat"
//`define GDB_OUT "../src/gdb_out.dat"
module dbg_comm(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);
parameter Tp = 1;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
integer handle1, handle2;
reg [4:0] memory[0:0];
reg Mclk;
reg wb_rst_i;
reg alternator;
reg StartTesting;
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
reg [3:0] in_word_r;
wire [4:0] in_word;
wire [3:0] Temp;
initial
begin
alternator = 0;
StartTesting = 0;
wb_rst_i = 0;
#500;
wb_rst_i = 1;
#500;
wb_rst_i = 0;
#2000;
StartTesting = 1;
$display("StartTesting = 1");
end
initial
begin
wait(StartTesting);
while(1)
begin
#1;
$readmemh(`GDB_OUT, memory);
//#1000;
if(!(memory[0] & 5'b10000))
begin
handle1 = $fopen(`GDB_OUT);
$fwrite(handle1, "%h", 5'b10000 | memory[0]); // To ack to jp1 that we read dgb_out.dat
$fclose(handle1);
end
end
end
assign in_word = memory[0];
assign Temp = in_word_r;
always @ (posedge in_word[4] or posedge wb_rst_i)
begin
if(wb_rst_i)
in_word_r<=#Tp 5'b0;
else
in_word_r<=#Tp in_word[3:0];
end
//always alternator = #100 ~alternator;
always @ (posedge P_TCK or alternator)
begin
handle2 = $fopen(`GDB_IN);
$fdisplay(handle2, "%b", P_TDO); // Vriting output data to file (TDO)
$fclose(handle2);
end
assign P_TCK = Temp[0];
assign P_TRST = Temp[1];
assign P_TDI = Temp[2];
assign P_TMS = Temp[3];
// Generating master clock (RISC clock) 10 MHz
initial
begin
Mclk<=#Tp 0;
#1 forever #`RISC_CLOCK Mclk<=~Mclk;
end
// Generating random number for use in DATAOUT_RISC[31:0]
reg [31:0] RandNumb;
always @ (posedge Mclk or posedge wb_rst_i)
begin
if(wb_rst_i)
RandNumb[31:0]<=#Tp 0;
else
RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
end
wire [31:0] DataIn = RandNumb;
// Connecting dbgTAP module
`ifdef UNUSED
dbg_top dbg1 (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
.wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
.risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
.opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
.risc_stall_o(), .reset_o()
);
`endif
endmodule // TAP
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
/**
* lpflow_inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire SLEEP ;
wire or0_out_X;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long int inf = 1e9 + 7; const long long int inf2 = inf * inf; priority_queue<long long int, vector<long long int>, greater<long long int>> mnheap; priority_queue<long long int> mxheap; long long int gcd(long long int x, long long int y) { if (x == 0) return y; return gcd(y % x, x); } int is_prime(long long int x) { if (x < 2) return 0; for (long long int i = 2; i * i <= x; i++) { if (x % i == 0) return 0; } return 1; } inline long long int modpw(long long int x, long long int y, long long int z) { long long int res = 1; x = x % z; while (y) { if (y & 1) res = (res * x) % z; x = (x * x) % z; y /= 2; } return res; } inline long long int modinv(long long int x, long long int z) { return modpw(x, z - 2, z); } long long int lcm(long long int x, long long int y) { return (x * y) / gcd(x, y); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; int dp[n][m]; string st[n]; for (int i = 0; i < n; i++) cin >> st[i]; int cnt = 0; for (int i = 0; i < n - 1; i++) { if (st[i][m - 1] == R ) cnt++; } for (int i = 0; i < m - 1; i++) { if (st[n - 1][i] == D ) cnt++; } cout << cnt << endl; } }
|
#include <bits/stdc++.h> using namespace std; long long i, j, t, n, k, a, b; double v; string line; char s[4]; int main() { while (cin >> n >> a >> b) { if (b < 0) b = n + b; a = a + b; a = a % n; if (a == 0) a = n; else if (a < 0) a = n + a; cout << a; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, M = 1e5 + 5, P = 105; int n, m, p; long long d[N]; int h[M], t[M]; long long a[M], s[M]; long long f[P][M]; int q[M]; long long Y(int j, int k) { return f[j - 1][k] + s[k]; } int32_t main() { cin >> n >> m >> p; for (int i = 2; i <= n; ++i) { cin >> d[i]; d[i] += d[i - 1]; } for (int i = 1; i <= m; ++i) { cin >> h[i] >> t[i]; a[i] = t[i] - d[h[i]]; } sort(a + 1, a + 1 + m); for (int i = 1; i <= m; ++i) s[i] = s[i - 1] + a[i]; memset(f[0], 0x3f, sizeof f[0]); f[0][0] = 0; for (int j = 1; j <= p; ++j) { int hh = 0, tt = 0; q[0] = 0; for (int i = 1; i <= m; ++i) { while (hh < tt && (Y(j, q[hh + 1]) - Y(j, q[hh])) <= a[i] * (q[hh + 1] - q[hh])) hh++; int k = q[hh]; f[j][i] = f[j - 1][k] + a[i] * (i - k) - (s[i] - s[k]); while (hh < tt && (Y(j, q[tt]) - Y(j, q[tt - 1])) * (i - q[tt]) >= (Y(j, i) - Y(j, q[tt])) * (q[tt] - q[tt - 1])) tt--; q[++tt] = i; } } cout << f[p][m] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 205; int d[N], head[N], tot; int to[N * N], nex[N * N], vis[N * N]; vector<pair<int, int> > ans; void init() { tot = 0; memset(d, 0, sizeof(d)); memset(head, -1, sizeof(head)); ans.clear(); } void add(int u, int v, int w) { d[v]++; to[tot] = v; nex[tot] = head[u]; vis[tot] = w; head[u] = tot++; } void dfs(int x) { for (int& i = head[x]; ~i;) { if (vis[i] == 1) { i = nex[i]; continue; } if (vis[i] == 0) ans.push_back(make_pair(x, to[i])); vis[i] = vis[i ^ 1] = 1; dfs(to[i]); } } int main() { int t; scanf( %d , &t); while (t--) { init(); int n, m, u, v; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); add(u, v, 0); add(v, u, 0); } vector<int> tmp; int ret = n; for (int i = 1; i <= n; i++) if (d[i] & 1) tmp.push_back(i), ret--; for (int i = 0; i < tmp.size(); i += 2) { add(tmp[i], tmp[i + 1], -1); add(tmp[i + 1], tmp[i], -1); } for (int i = 1; i <= n; i++) dfs(i); printf( %d n , ret); for (int i = 0; i < ans.size(); i++) printf( %d %d n , ans[i].first, ans[i].second); } return 0; }
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the 2-bit pipe
module pipeline_buffer_2bit (in,out,clock,reset);
// Output signal for the design module
output [1:0] out; // Output data signal
// Input signals for the design module
input [1:0] in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg [1:0] out;
reg [1:0] o1; // Output of flip-flop #1
reg [1:0] o2; // Output of flip-flop #2
reg [1:0] o3; // Output of flip-flop #3
reg [1:0] o4; // Output of flip-flop #4
reg [1:0] o5; // Output of flip-flop #5
reg [1:0] o6; // Output of flip-flop #6
reg [1:0] o7; // Output of flip-flop #7
reg [1:0] o8; // Output of flip-flop #8
reg [1:0] o9; // Output of flip-flop #9
reg [1:0] o10; // Output of flip-flop #10
reg [1:0] o11; // Output of flip-flop #11
reg [1:0] o12; // Output of flip-flop #12
reg [1:0] o13; // Output of flip-flop #13
reg [1:0] o14; // Output of flip-flop #14
reg [1:0] o15; // Output of flip-flop #15
reg [1:0] o16; // Output of flip-flop #16
reg [1:0] o17; // Output of flip-flop #17
reg [1:0] o18; // Output of flip-flop #18
reg [1:0] o19; // Output of flip-flop #19
reg [1:0] o20; // Output of flip-flop #20
reg [1:0] o21; // Output of flip-flop #21
reg [1:0] o22; // Output of flip-flop #22
reg [1:0] o23; // Output of flip-flop #23
reg [1:0] o24; // Output of flip-flop #24
reg [1:0] o25; // Output of flip-flop #25
reg [1:0] o26; // Output of flip-flop #26
reg [1:0] o27; // Output of flip-flop #27
reg [1:0] o28; // Output of flip-flop #28
reg [1:0] o29; // Output of flip-flop #29
reg [1:0] o30; // Output of flip-flop #30
reg [1:0] o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 2'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 2'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 2'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 2'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 2'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 2'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 2'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 2'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 2'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 2'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 2'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 2'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 2'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 2'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 2'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 2'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 2'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 2'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 2'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 2'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 2'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 2'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 2'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 2'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 2'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 2'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 2'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 2'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 2'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 2'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 2'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 2'd0;
else
out = o31;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_tfifo.v,v $
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule
|
#include <bits/stdc++.h> int n, ust, x, y, mark[10]; int main() { scanf( %d , &n); scanf( %d , &ust); for (int i = 0; i < n; i++) { scanf( %d %d , &x, &y); mark[x] = 1; mark[y] = 1; mark[7 - x] = 1; mark[7 - y] = 1; if (!mark[7 - ust]) for (int j = 0; j < 7; j++) mark[j] = 0; else { printf( NO n ); return 0; } } printf( YES n ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_BEHAVIORAL_PP_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp2_3.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_arb_hp2_3(
sw_clk,
rstn,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_dv_ddr_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_hp3;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp2;
input [max_burst_bits-1:0] wr_data_hp2;
input [addr_width-1:0] wr_addr_hp2;
input [max_burst_bytes_width:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [addr_width-1:0] rd_addr_hp2;
input [max_burst_bytes_width:0] rd_bytes_hp2;
output [max_burst_bits-1:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [max_burst_bits-1:0] wr_data_hp3;
input [addr_width-1:0] wr_addr_hp3;
input [max_burst_bytes_width:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [addr_width-1:0] rd_addr_hp3;
input [max_burst_bytes_width:0] rd_bytes_hp3;
output [max_burst_bits-1:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp2),
.qos2(w_qos_hp3),
.prt_dv1(wr_dv_ddr_hp2),
.prt_dv2(wr_dv_ddr_hp3),
.prt_data1(wr_data_hp2),
.prt_data2(wr_data_hp3),
.prt_addr1(wr_addr_hp2),
.prt_addr2(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp2),
.prt_bytes2(wr_bytes_hp3),
.prt_ack1(wr_ack_ddr_hp2),
.prt_ack2(wr_ack_ddr_hp3),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp2),
.qos2(r_qos_hp3),
.prt_req1(rd_req_ddr_hp2),
.prt_req2(rd_req_ddr_hp3),
.prt_data1(rd_data_ddr_hp2),
.prt_data2(rd_data_ddr_hp3),
.prt_addr1(rd_addr_hp2),
.prt_addr2(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp2),
.prt_bytes2(rd_bytes_hp3),
.prt_dv1(rd_dv_ddr_hp2),
.prt_dv2(rd_dv_ddr_hp3),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
`timescale 1 ns / 1 ps
module emaxi_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 64,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
// FIFO read-master port, writes from RX channel
input wire [102:0] emwr_rd_data,
output wire emwr_rd_en,
input wire emwr_empty,
// FIFO read-master port, read requests from RX channel
input wire [102:0] emrq_rd_data,
output wire emrq_rd_en,
input wire emrq_empty,
// FIFO write-master port, read responses to TX channel
output wire [102:0] emrr_wr_data,
output wire emrr_wr_en,
input wire emrr_full,
input wire emrr_prog_full,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
emaxi_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) emaxi_v1_0_M00_AXI_inst (
.emwr_rd_data(emwr_rd_data),
.emwr_rd_en(emwr_rd_en),
.emwr_empty(emwr_empty),
.emrq_rd_data(emrq_rd_data),
.emrq_rd_en(emrq_rd_en),
.emrq_empty(emrq_empty),
.emrr_wr_data(emrr_wr_data),
.emrr_wr_en(emrr_wr_en),
.emrr_full(emrr_full),
.emrr_prog_full(emrr_prog_full),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
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#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int maxn = 5e5 + 5; struct Point { char ty; int x, y; Point(char ch = 0 , int x = 0, int y = 0) : ty(ch), x(x), y(y) {} } chess[maxn]; int X0, Y0, n; bool solve1() { vector<pair<int, char> > v; for (int i = 1; i <= n; i++) { if (chess[i].x == X0) v.push_back(make_pair(chess[i].y, chess[i].ty)); } if (v.size() == 0) return false; sort(v.begin(), v.end()); for (int i = 0; i < v.size() - 1; i++) { if (v[i].first < Y0 && v[i + 1].first > Y0) { if (v[i].second == R || v[i].second == Q || v[i + 1].second == R || v[i + 1].second == Q ) return true; return false; } } int len = v.size(); if (v[len - 1].first < Y0 && (v[len - 1].second == R || v[len - 1].second == Q )) return true; if (v[0].first > Y0 && (v[0].second == R || v[0].second == Q )) return true; return false; } bool solve2() { vector<pair<int, char> > v; for (int i = 1; i <= n; i++) { if (chess[i].y == Y0) v.push_back(make_pair(chess[i].x, chess[i].ty)); } if (v.size() == 0) return false; sort(v.begin(), v.end()); for (int i = 0; i < v.size() - 1; i++) { if (v[i].first < X0 && v[i + 1].first > X0) { if (v[i].second == R || v[i].second == Q || v[i + 1].second == R || v[i + 1].second == Q ) return true; return false; } } int len = v.size(); if (v[len - 1].first < X0 && (v[len - 1].second == R || v[len - 1].second == Q )) return true; if (v[0].first > X0 && (v[0].second == R || v[0].second == Q )) return true; return false; } bool solve3() { vector<pair<int, char> > v; for (int i = 1; i <= n; i++) { if (chess[i].x == chess[i].y) v.push_back(make_pair(chess[i].x, chess[i].ty)); } if (v.size() == 0) return false; sort(v.begin(), v.end()); for (int i = 0; i < v.size() - 1; i++) { if (v[i].first < X0 && v[i + 1].first > X0) { if (v[i].second == B || v[i].second == Q || v[i + 1].second == B || v[i + 1].second == Q ) return true; return false; } } int len = v.size(); if (v[len - 1].first < X0 && (v[len - 1].second == B || v[len - 1].second == Q )) return true; if (v[0].first > X0 && (v[0].second == B || v[0].second == Q )) return true; return false; } bool solve4() { vector<pair<int, char> > v; for (int i = 1; i <= n; i++) { if (chess[i].x == -chess[i].y) v.push_back(make_pair(chess[i].x, chess[i].ty)); } if (v.size() == 0) return false; sort(v.begin(), v.end()); for (int i = 0; i < v.size() - 1; i++) { if (v[i].first < X0 && v[i + 1].first > X0) { if (v[i].second == B || v[i].second == Q || v[i + 1].second == B || v[i + 1].second == Q ) return true; return false; } } int len = v.size(); if (v[len - 1].first < X0 && (v[len - 1].second == B || v[len - 1].second == Q )) return true; if (v[0].first > X0 && (v[0].second == B || v[0].second == Q )) return true; return false; } int main() { cin >> n >> X0 >> Y0; for (int i = 1; i <= n; i++) { char ch; int a, b; scanf( %s%d%d , &ch, &a, &b); chess[i] = Point(ch, a - X0, b - Y0); } X0 = Y0 = 0; if (solve1() || solve2() || solve3() || solve4()) printf( YES n ); else puts( NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, ans, c, d; int a[1005][1005], b[1005][1005]; string s[1003]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < n; i++) { d = 0; for (int j = 0; j < m; j++) { if (s[i][j] == * ) d++; } (d > 0) ? d-- : d; for (int j = 0; j < m; j++) { if (s[i][j] == * ) a[i][j] = d; } } for (int i = 0; i < m; i++) { d = 0; for (int j = 0; j < n; j++) { if (s[j][i] == * ) d++; } (d > 0) ? d-- : d; for (int j = 0; j < n; j++) { if (s[j][i] == * ) b[j][i] = d; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == * ) { ans += a[i][j] * b[i][j]; } } } cout << ans; }
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#include <bits/stdc++.h> using namespace std; int h, i, j, x, l, r, pa[200200], pb[200200]; bool ans; int main() { scanf( %d , &h); for (j = 0; j <= h; j++) { scanf( %d , &x); for (i = 1; i <= x; i++) { pa[r + i] = l; pb[r + i] = min(l + i - 1, r); if (pa[r + i] != pb[r + i]) ans = true; } l = r + 1; r = r + x; } if (ans) { puts( ambiguous ); for (i = 1; i <= r; i++) printf( %d , pa[i]); puts( ); for (i = 1; i <= r; i++) printf( %d , pb[i]); puts( ); } else puts( perfect ); return 0; }
|
#include <bits/stdc++.h> const long long Inf = 1e18; const long double eps = 1e-7; long long LINF = (long long)2e18; using namespace std; long long mod = 1e9 + 7; long long mod5 = 1e9 + 9; long long mod3 = 998244353; long long mod4 = 1000003; long long mod2 = 1e9 + 123; const int MAXN = 10100000; const int INF = 1000000000; vector<vector<int> > a; int n, m; vector<pair<int, int> > mx; int rec(int pos, vector<int> mxs) { if (pos == m) { int ss = 0; for (long long(i) = 0; (i) < n; (i)++) { ss += mxs[i]; } return ss; } int cur = 0; int ss = 0; for (long long(i) = 0; (i) < n; (i)++) { cur += mxs[i]; ss += mxs[i]; } int ans = cur; for (long long(i) = 0; (i) < n; (i)++) { cur = ss; vector<int> lol = mxs; for (long long(j) = 0; (j) < n; (j)++) { if (a[(i + j) % n][mx[pos].second] > mxs[j]) { cur += a[(i + j) % n][mx[pos].second] - mxs[j]; lol[j] = a[(i + j) % n][mx[pos].second]; } } ans = max(ans, rec(pos + 1, lol)); } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.setf(ios::fixed); cout.precision(20); int tt; cin >> tt; while (tt--) { cin >> n >> m; a.clear(); a.resize(n, vector<int>(m)); for (long long(i) = 0; (i) < n; (i)++) { for (long long(j) = 0; (j) < m; (j)++) { cin >> a[i][j]; } } mx.clear(); for (long long(i) = 0; (i) < m; (i)++) { int cur = -1; for (long long(j) = 0; (j) < n; (j)++) { cur = max(cur, a[j][i]); } mx.push_back({cur, i}); } sort((mx).rbegin(), (mx).rend()); mx.resize(min(4, m)); m = min(m, 4); vector<int> kek(n, 0); cout << rec(0, kek) << n ; } return 0; }
|
module EdgeDelay(clk, sigIn, waitCnt, sigOut, diagOut);
//module EdgeDelay(clk, sigIn, waitCnt, sigOut);
/***
This module looks at a signal and uses a timer to delay edges. Once the timer reaches the given number of clock cycles (specified by an input), an output is forced high.
Ted Golfinopoulos, 12 September 2012
***/
parameter WAIT_CNT_SIZE=11;
parameter INVERT_FLAG=1'b0; //If high, invert output.
parameter MIN_WAIT=3'b10; //Minimum number of clock cycles that a state change must hold in order to count as valid.
input clk, sigIn;
input [WAIT_CNT_SIZE-1:0] waitCnt;
output sigOut;
//output divOut;
output diagOut; //Diagnostic output
reg [WAIT_CNT_SIZE-1:0] posEdgeDelayTimer;
reg [WAIT_CNT_SIZE-1:0] negEdgeDelayTimer;
reg sigOutReg;
reg sigLast;
reg sigReg;
reg resetFlag; //Changes state every time positive edge counter is reset.
initial begin
#0
sigOutReg=1'b0;
posEdgeDelayTimer=1'b0;
negEdgeDelayTimer=1'b0;
sigLast=1'b0;
end
reg posEdgeReg, posEdgeRegLast, negEdgeReg, negEdgeRegLast;
always @(posedge sigIn) begin
posEdgeReg=~posEdgeReg;
end
always @(negedge sigIn) begin
negEdgeReg=~negEdgeReg;
end
//Check for state changes in sigInPosEdge, indicating rising edge in input signal. Wait a specified delay time, and then impose the corresponding rising edge in the output signal.
always @(posedge clk) begin
sigReg=sigIn;
if(posEdgeRegLast!=posEdgeReg && posEdgeDelayTimer>MIN_WAIT) begin
posEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
posEdgeRegLast=posEdgeReg;
end else if(negEdgeRegLast!=negEdgeReg && negEdgeDelayTimer>MIN_WAIT) begin
negEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
negEdgeRegLast=negEdgeReg;
resetFlag=~resetFlag;
end
/* ** POSITIVE EDGE DELAY ** */
/*
if(sigLast>sigReg) begin //Rising edge
posEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
sigLast=sigReg; //Update signal register.
end else if(sigLast<sigReg) begin //Falling edge // ** NEGATIVE EDGE DELAY ** //
negEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
sigLast=sigReg; //Update signal register.
resetFlag=~resetFlag;
end
*/
//Delay timer.
//If timer has been reset, start counting until wait limit is reached. Then, stop and update output.
//Since this is the positive edge timer, the update is to force the output high.
//After the output is forced high, the timer is incremented once more to unlock output.
if(posEdgeDelayTimer<waitCnt) begin
posEdgeDelayTimer=posEdgeDelayTimer+1'b1;
end else if(posEdgeDelayTimer==waitCnt) begin //Leave timer locked at waitCnt
posEdgeDelayTimer=posEdgeDelayTimer+1'b1;
sigOutReg=1'b1; //Set output high, effectively delaying rising edge.
end //Otherwise, don't increment timer any longer, and don't force the output state.
else
//Delay timer.
//If timer has been reset, start counting until wait limit is reached. Then, stop and update output.
//Since this is the positive edge timer, the update is to force the output high.
//After the output is forced high, the timer is incremented once more to unlock output.
if(negEdgeDelayTimer<waitCnt) begin
negEdgeDelayTimer=negEdgeDelayTimer+1'b1;
end else if(negEdgeDelayTimer==waitCnt) begin //Leave timer locked at waitCnt
negEdgeDelayTimer=negEdgeDelayTimer+1'b1;
sigOutReg=1'b0; //Set output low, effectively delaying falling edge.
end //Otherwise, don't increment timer any longer, and don't force the output state.
end
assign sigOut=sigOutReg; //Tie output to sigOutReg register, which is modified in clk always block.
//assign divOut=sigLast; //Diagnostic output.
assign diagOut=negEdgeReg;
endmodule
//Triggering off of signal edges might be problematic. Try using state changes.
/*
always @(posedge sigIn) begin
sigInPosEdge=~sigInPosEdge; //Changes state on positive edges of sigIn.
end
always @(negedge sigIn) begin
sigInNegEdge=~sigInNegEdge; //Changes state on negative edges of sigIn.
end
*/
/*
reg sigInPosEdge, sigInPosEdgeLast;
reg sigInNegEdge, sigInNegEdgeLast;
initial begin
#0
sigOutReg=1'b0;
posEdgeDelayTimer=1'b0;
negEdgeDelayTimer=1'b0;
sigInPosEdge=1'b0;
sigInNegEdge=1'b0;
sigInPosEdgeLast=1'b0;
sigInNegEdgeLast=1'b0;
end
always @(posedge clk) begin
if(sigIn>sigLast) begin //Rising Edge.
sigLast=sigIn;
sigInPosEdge=~sigInPosEdge;
end else if(sigIn<sigLast) begin //Falling edge
sigLast=sigIn;
sigInNegEdge=~sigInNegEdge;
end
end
//Check for state changes in sigInPosEdge, indicating rising edge in input signal. Wait a specified delay time, and then impose the corresponding rising edge in the output signal.
always @(posedge clk) begin
// ** POSITIVE EDGE DELAY ** //
if(sigInPosEdgeLast != sigInPosEdge) begin
posEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
sigInPosEdgeLast = sigInPosEdge; //Update positive edge state register.
end
//Delay timer.
//If timer has been reset, start counting until wait limit is reached. Then, stop and update output.
//Since this is the positive edge timer, the update is to force the output high.
//After the output is forced high, the timer is incremented once more to unlock output.
if(posEdgeDelayTimer<waitCnt) begin
posEdgeDelayTimer=posEdgeDelayTimer+1'b1;
end else if(posEdgeDelayTimer==waitCnt) begin //Leave timer locked at waitCnt
posEdgeDelayTimer=posEdgeDelayTimer+1'b1;
sigOutReg=1'b1; //Set output high, effectively delaying rising edge.
end //Otherwise, don't increment timer any longer, and don't force the output state.
// ** NEGATIVE EDGE DELAY ** //
if(sigInNegEdgeLast != sigInNegEdge) begin
negEdgeDelayTimer=1'b0; //Reset positive edge delay timer.
sigInNegEdgeLast = sigInNegEdge; //Update positive edge state register.
end
//Delay timer.
//If timer has been reset, start counting until wait limit is reached. Then, stop and update output.
//Since this is the positive edge timer, the update is to force the output high.
//After the output is forced high, the timer is incremented once more to unlock output.
if(negEdgeDelayTimer<waitCnt) begin
negEdgeDelayTimer=negEdgeDelayTimer+1'b1;
end else if(negEdgeDelayTimer==waitCnt) begin //Leave timer locked at waitCnt
negEdgeDelayTimer=negEdgeDelayTimer+1'b1;
sigOutReg=1'b0; //Set output low, effectively delaying falling edge.
end //Otherwise, don't increment timer any longer, and don't force the output state.
end
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V
|
module clkgen(
input clkin,
output clkout,
output lock
);
parameter INCLOCK_FREQ = 12000000;
parameter OUTCLOCK_FREQ = 24000000;
localparam r_bits = 4;
localparam f_bits = 7;
localparam q_bits = 3;
localparam rfq = compute_divisors(INCLOCK_FREQ, OUTCLOCK_FREQ);
localparam r = rfq[(q_bits+f_bits) +: r_bits];
localparam f = rfq[q_bits +: f_bits];
localparam q = rfq[0 +: q_bits];
function integer gcd;
input integer a;
input integer b;
integer t;
begin
while (b != 0) begin
t = b;
b = a % b;
a = t;
end;
gcd = a;
end
endfunction // gcd
function integer pack_rfq;
input integer r;
input integer f;
input integer q;
begin
pack_rfq = {r[0 +: r_bits], f[0 +: f_bits], q[0 +: q_bits]};
end
endfunction // pack_rfq
function integer compute_divisors;
input integer f_ref;
input integer f_out;
integer g;
integer r;
integer f;
integer q;
begin
g = gcd(f_ref, f_out);
r = f_ref / g;
f = f_out / g;
q = 3;
while (q > 0 && f_out > f_ref) begin
q = q - 1;
f_ref = f_ref * 2;
end
if (r < 1 || r > 16 || f < 1 || f > 64)
compute_divisors = -1;
else
compute_divisors = pack_rfq(r-1, f-1, q);
end
endfunction // compute_divisors
generate
if (rfq < 0) begin
initial $finish;
end else begin
initial $display("r = %d, f = %d, q = %d", r, f, q);
SB_PLL40_CORE #(.DIVR(r), .DIVF(f), .DIVQ(q),
.FILTER_RANGE(1), .FEEDBACK_PATH("PHASE_AND_DELAY"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_FEEDBACK(0), .FDA_RELATIVE(0),
.SHIFTREG_DIV_MODE(0), .ENABLE_ICEGATE(0),
.PLLOUT_SELECT("SHIFTREG_0deg"))
pll_inst(.REFERENCECLK(clkin),
.PLLOUTGLOBAL(clkout),
.RESETB(1'b1),
.BYPASS(1'b0),
.LOCK(lock));
end
endgenerate
endmodule // clkgen
|
#include <bits/stdc++.h> using namespace std; int const INF = 100000; int p[INF + 1]; int M[INF + 1]; int main() { memset(p, -1, sizeof(p)); memset(M, -1, sizeof(M)); set<pair<int, int> > S; int n, x, k; cin >> n; while (n--) { cin >> x >> k; if (p[k] < x) { p[k] = x; M[k] = max(M[k], x); S.insert(pair<int, int>(x, k)); } else { if (S.find(pair<int, int>(x, k)) != S.end()) continue; else { cout << NO ; return 0; } } } long long cmp = 0; for (int i = 0; i <= INF; i++) cmp += (M[i] + 1); if (cmp == S.size()) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int X[] = {1, 0, -1, 0, 1, -1, -1, 1}; int Y[] = {0, 1, 0, -1, 1, 1, -1, -1}; void MN(long long int &a, long long int b) { if (a > b) a = b; } void MX(long long int &a, long long int b) { if (a < b) a = b; } void MN(int &a, int b) { if (a > b) a = b; } void MX(int &a, int b) { if (a < b) a = b; } long long int MOD(long long int a, long long int b) { return a >= 0 ? a % b : (b - abs(a % b)) % b; } int OneD(int row, int col, int t_n_o_r) { return row * t_n_o_r + col; } int main() { int n, o = 0; scanf( %d , &n); unsigned long long int res = 0; vector<int> seq(n); for (int i = 0; i < n; i++) { scanf( %d , &seq[i]); if (seq[i] & 1) o++; } sort(seq.begin(), seq.end()); if (o & 1) o--; for (int i = n - 1; i >= 0; i--) { if (seq[i] & 1) { if (o > 0) { res += seq[i]; o--; } } else res += seq[i]; } printf( %lld n , res); return 0; }
|
//--------------------------------------------------------------------------------
// meta.v
//
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Inserts META data into spi_transmitter datapath upon command...
//
`timescale 1ns/100ps
module meta_handler (
// system signals
input wire clock,
input wire extReset,
//
input wire query_metadata,
input wire xmit_idle,
// outputs...
output reg writeMeta,
output wire [7:0] meta_data
);
reg [5:0] metasel, next_metasel;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
// Create meta data ROM...
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
assign meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n"); // Device name string...
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7"); // FPGA firmware version string
`ADDBYTE(0);
//`ADDLONG(8'h21,8'h00,8'h60,8'h00,8'h00); // Amount of sample memory (24K)
//`ADDLONG(8'h23,8'h00,8'hC2,8'hEB,8'h0B); // Max sample rate (200Mhz)
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00); // Amount of sample memory (24K)
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00); // Max sample rate (200Mhz)
`ADDSHORT(8'h40,8'h20); // Max # of probes
`ADDSHORT(8'h41,8'h02); // Protocol version
`ADDBYTE(0); // End of data flag
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0; // Padding
end
//
// Control FSM for sending meta data...
//
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge extReset)
if (extReset) begin
state <= IDLE;
metasel <= 3'h0;
end else begin
state <= next_state;
metasel <= next_metasel;
end
always @*
begin
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND : // output contents of META data rom - IED
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int L01P08(vector<int>& arr, int n) { bool check = true; if (arr[0] - 15 > 0) { return 15; } else { for (int i = 0; i < n - 1; i++) { for (int j = 1; j < n; j++) { if (arr[i] + 15 < arr[i + 1]) { return arr[i] + 15; break; } } } if (arr[arr.size() - 1] + 15 < 90) { return arr[arr.size() - 1] + 15; } else { return 90; } } } int main() { int n, val; cin >> n; vector<int> arr; for (int i = 0; i < n; i++) { cin >> val; arr.push_back(val); } int res = L01P08(arr, n); cout << res; return 0; }
|
// -------------------------------------------------------------
//
// File Name: mealy_rtl\Stateflow_Mealy_example\Mealy_Subsystem.v
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
//
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 0.2
// Target subsystem base rate: 0.2
//
//
// Clock Enable Sample Time
// -- -------------------------------------------------------------
// ce_out 0.2
// -- -------------------------------------------------------------
//
//
// Output Signal Clock Enable Sample Time
// -- -------------------------------------------------------------
// Out1 ce_out 0.2
// Out2 ce_out 0.2
// -- -------------------------------------------------------------
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: Mealy_Subsystem
// Source Path: Stateflow_Mealy_example/Mealy_Subsystem
// Hierarchy Level: 0
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module Mealy_Subsystem
(
clk,
rst_n,
clk_enable,
ce_out,
Out1,
Out2
);
input clk;
input rst_n;
input clk_enable;
output ce_out;
output [63:0] Out1; // double
output [63:0] Out2; // double
wire [63:0] a; // ufix64
wire [63:0] b; // ufix64
Mealy_Chart u_Mealy_Chart (.clk(clk),
.rst_n(rst_n),
.enb(clk_enable),
.a(a), // double
.b(b) // double
);
assign ce_out = clk_enable;
assign Out1 = a;
assign Out2 = b;
endmodule // Mealy_Subsystem
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long int, long long int> > P; int n; bool compare_y(const pair<long long int, long long int>& p1, const pair<long long int, long long int>& p2) { if (p1.second != p2.second) return p1.second < p2.second; return p1.first < p2.first; } long long int d(pair<long long int, long long int> p1, pair<long long int, long long int> p2) { return pow(p1.first - p2.first, 2) + pow(p1.second - p2.second, 2); } long long int func(int l, int h, vector<pair<long long int, long long int> > Y) { if (h - l == 1) return d(P[l], P[h]); if (h - l == 2) return min(min(d(P[l], P[l + 1]), d(P[l + 1], P[h])), d(P[l], P[h])); int mid = (l + h) / 2, sz = Y.size(); vector<pair<long long int, long long int> > left, right; for (int i = 0; i < sz; ++i) { if (Y[i].first <= P[mid].first) left.push_back(Y[i]); else right.push_back(Y[i]); } long long int m = min(func(l, mid, left), func(mid + 1, h, right)); for (int i = 0; i < sz; ++i) for (int j = i + 1; j < i + 10 && j < sz; ++j) if (d(Y[i], Y[j]) < m) m = d(Y[i], Y[j]); return m; } int main() { cin >> n; vector<pair<long long int, long long int> > Q; for (int i = 0; i < n; ++i) { long long int u; cin >> u; P.push_back(make_pair(i + 1, u)); Q.push_back(make_pair(i + 1, u)); if (i) P[i].second += P[i - 1].second; if (i) Q[i].second += Q[i - 1].second; } sort(Q.begin(), Q.end(), compare_y); cout << func(0, n - 1, Q) << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_1_V
`define SKY130_FD_SC_LS__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int hoa = 0; int thuong = 0; for (int i = 0; i < s.size(); i++) { if (s[i] >= 65 && s[i] <= 90) { hoa++; } else { thuong++; } } if (thuong >= hoa) { for (int i = 0; i < s.size(); i++) { if (s[i] >= 65 && s[i] <= 90) { s[i] += 32; } } } else { for (int i = 0; i < s.size(); i++) { if (s[i] >= 97 && s[i] <= 122) { s[i] -= 32; } } } cout << s; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_PP_BLACKBOX_V
|
#include <bits/stdc++.h> char putnb[20]; using namespace std; const long long mod = 1e9 + 7; const long long mod2 = 1999999973; const int infs = 1e8; const long long inf = 1e18; const int N = 200000; long long A[N + 5]; long long dp[N + 5][2]; bool vis[N + 5][2]; bool solved[N + 5][2]; long long n; long long solve(long long pos, int state) { if (pos <= 0 || pos > n) return 0; if (vis[pos][state] && !solved[pos][state]) return -1; vis[pos][state] = true; if (pos == 1) { if (state) return 0 - inf; return -1; } if (solved[pos][state]) return dp[pos][state]; if (!state) { long long v1 = solve(pos + A[pos], 1); if (v1 == -1) dp[pos][state] = -1; else dp[pos][state] = v1 + A[pos]; } else { long long v2 = solve(pos - A[pos], 0); if (v2 == -1) dp[pos][state] = -1; else dp[pos][state] = v2 + A[pos]; } solved[pos][state] = true; return dp[pos][state]; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int i = 2; i <= n; ++i) cin >> A[i]; for (int i = 1; i <= n - 1; ++i) { long long res = solve(1 + i, 1); if (res == -1) cout << res << n ; else if (res >= 0) cout << res + i << n ; else if (res < 0) cout << (res + inf + 2 * i) << n ; } return 0; }
|
`include "macro.v"
`include "machine/cpu/mips.v"
`include "machine/memory/rom.v"
`include "machine/memory/ram.v"
module machine(
input wire clock,
input wire reset
);
wire[`INST_ADDR_BUS] rom_addr;
wire[`INST_DATA_BUS] rom_instruction;
wire rom_chip_enable;
wire ram_operation;
wire[`INST_ADDR_BUS] ram_addr;
wire[`BYTE_SEL_BUS] ram_select_signal;
wire[`INST_DATA_BUS] ram_write_data;
wire[`INST_DATA_BUS] ram_read_data;
wire ram_chip_enable;
mips mips_instance(
.clock(clock),
.reset(reset),
.rom_data(rom_instruction),
.ram_read_data(ram_read_data),
.rom_addr(rom_addr),
.rom_chip_enable(rom_chip_enable),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_addr(ram_addr),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
rom rom_instance(
.chip_enable(rom_chip_enable),
.addr(rom_addr),
.instruction(rom_instruction)
);
ram ram_instance(
.clock(clock),
.chip_enable(ram_chip_enable),
.operation(ram_operation),
.addr(ram_addr),
.select_signal(ram_select_signal),
.write_data(ram_write_data),
.read_data(ram_read_data)
);
/* DEBUG AREA OUTPUT BEGIN*/
integer idx;
initial begin
$dumpfile("wave.lxt");
$dumpvars(0, mips_instance);
$dumpvars(0, rom_instance);
$dumpvars(0, ram_instance);
for (idx = 0; idx < 32; idx = idx + 1) begin
$dumpvars(0, mips_instance.gpr_file_instance.regs[idx]);
end
end
/* DEBUG AREA OUTPUT END*/
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int res = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -f; ch = getchar(); } while (isdigit(ch)) { res = (res << 3) + (res << 1) + ch - 0 ; ch = getchar(); } return res * f; } namespace qiqi { const int N = 6e5 + 5; int n, m, siz[N], si[N], fa[N], ch[N][2], rev[N], cnt, mx[N]; bool del[N]; struct Edge { int u, v, w, id; inline bool friend operator<(Edge a, Edge b) { return a.w < b.w; } } e[N]; priority_queue<Edge> q; inline bool isroot(int x) { return ch[fa[x]][0] != x && ch[fa[x]][1] != x; } inline void push_up(int x) { siz[x] = (x <= n) + si[x] + siz[ch[x][0]] + siz[ch[x][1]]; mx[x] = x > n ? x - n : 0; for (int i = (0); i <= (1); ++i) if (e[mx[ch[x][i]]].w > e[mx[x]].w) mx[x] = mx[ch[x][i]]; } inline void push_down(int x, bool k) { if (k && !isroot(x)) push_down(fa[x], k); if (rev[x]) { swap(ch[x][0], ch[x][1]); rev[ch[x][0]] ^= 1; rev[ch[x][1]] ^= 1; rev[x] = 0; } } inline void rotate(int x) { int y = fa[x], z = fa[y], l = x == ch[y][1]; if (!isroot(y)) ch[z][y == ch[z][1]] = x; fa[x] = z; push_up(fa[ch[y][l] = ch[x][l ^ 1]] = y); push_up(fa[ch[x][l ^ 1] = y] = x); } inline void splay(int x) { push_down(x, 1); while (!isroot(x)) { int y = fa[x]; if (!isroot(y)) rotate(x ^ y ^ ch[y][0] ^ ch[fa[y]][0] ? x : y); rotate(x); } push_up(x); } inline void access(int x) { for (int i = 0; x; x = fa[i = x]) { splay(x); si[x] += siz[ch[x][1]]; si[x] -= siz[ch[x][1] = i]; push_up(x); } } inline void makeroot(int x) { access(x); splay(x); rev[x] ^= 1; } inline void split(int x, int y) { makeroot(x); access(y); splay(y); } inline int find(int x) { access(x); splay(x); while (ch[x][rev[x]]) x = ch[x][rev[x]]; splay(x); return x; } inline int qry(int x, int y) { split(x, y); return mx[y]; } inline void cut(int x, int y) { split(x, y); cnt -= siz[y] & 1; ch[y][0] = fa[x] = 0; push_up(y); cnt += (siz[x] & 1) + (siz[y] & 1); } inline void link(int x, int y) { split(x, y); cnt -= (siz[x] & 1) + (siz[y] & 1); si[fa[x] = y] += siz[x]; push_up(y); cnt += siz[y] & 1; } inline int upd(int x, int y, int id) { bool flg = 1; if (find(x) == find(y)) { int k = qry(x, y); if (e[k].w > e[id].w) { del[k] = 1; cut(e[k].u, k + n); cut(e[k].v, k + n); } else flg = 0; } if (flg) { link(x, id + n); link(y, id + n); } if (cnt) return -1; while (1) { Edge e = q.top(); q.pop(); if (del[e.id]) continue; cut(e.u, e.id + n); cut(e.v, e.id + n); if (cnt) { q.push(e); link(e.u, e.id + n); link(e.v, e.id + n); return q.top().w; } } } void main() { e[0].w = 0; cnt = n = read(); m = read(); for (int i = (1); i <= (m); ++i) { q.push(e[i] = (Edge){read(), read(), read(), i}); printf( %d n , upd(e[i].u, e[i].v, i)); } } } // namespace qiqi int main() { qiqi::main(); return 0; }
|
#include <bits/stdc++.h> using namespace std; void Braka() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { Braka(); int n, k, ans = 0; cin >> n >> k; while (n--) { set<char> st; string s; cin >> s; for (int i = 0; i < s.length(); i++) if (s[i] - 0 <= k) st.insert(s[i]); if (st.size() == k + 1) ans++; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long expo(long long a, long long b, long long m) { long long result = 1; while (b) { if (b & 1) { result = (result * a) % m; } b = (b >> 1) % m; a = (a * a) % m; } return result; } double expof(double a, int b) { double result = 1; while (b) { if (b & 1) { result = (result * a); } b = (b >> 1); a = (a * a); } return result; } bool comp(pair<long long, long long> a, pair<long long, long long> b) { if (a.second < b.second) return true; } int main() { long long m, n, t, c, l, x; vector<pair<long long, pair<long long, long long> > > p; vector<long long> v; cin >> m; long long ans = 0; for (int i = 0; i < m; ++i) { cin >> t; if (t == 1) { cin >> x; ans++; v.push_back(ans); p.push_back(make_pair(1, make_pair(x, 0))); } else { cin >> l >> c; ans += c * l; v.push_back(ans); p.push_back(make_pair(2, make_pair(l, c))); } } cin >> n; long long q[100005]; for (int i = 0; i < n; ++i) { cin >> q[i]; } for (int i = 0; i < n; ++i) { x = q[i]; vector<long long>::iterator it = upper_bound(v.begin(), v.end(), x); long long ix = it - v.begin(); ix--; if (v[ix] == x) { if (p[ix].first == 1) { cout << p[ix].second.first << ; continue; } else { x = p[ix].second.first; } } else { if ((x - v[ix]) % p[ix + 1].second.first == 0) { x = p[ix + 1].second.first; } else x = (x - v[ix]) % p[ix + 1].second.first; } while (1) { vector<long long>::iterator it = upper_bound(v.begin(), v.end(), x); long long ix = it - v.begin(); ix--; if (v[ix] == x) { if (p[ix].first == 1) { cout << p[ix].second.first << ; break; } else { x = p[ix].second.first; continue; } } if ((x - v[ix]) % p[ix + 1].second.first == 0) { x = p[ix + 1].second.first; } else x = (x - v[ix]) % p[ix + 1].second.first; } } }
|
/*--------------------------------------------------------------------
---- ----
---- altera_virtual_jtag.vhd ----
---- ----
---- ----
---- ----
---- Author(s): ----
---- Nathan Yawn () ----
---- ----
---- Verilog conversion: ----
---- Stefan Kristiansson ()----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2008-2010 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
-- --
-- This file is a wrapper for the Altera Virtual JTAG device. --
-- It is designed to take the place of a separate TAP --
-- controller in Altera systems, to allow a user to access a CPU --
-- debug module (such as that of the OR1200) through the FPGA's --
-- dedicated JTAG / configuration port. --
-- --
--------------------------------------------------------------------*/
module altera_virtual_jtag (
output tck_o,
input debug_tdo_i,
output tdi_o,
output test_logic_reset_o,
output run_test_idle_o,
output shift_dr_o,
output capture_dr_o,
output pause_dr_o,
output update_dr_o,
output debug_select_o
);
localparam [3:0] CMD_DEBUG = 4'b1000;
wire [3:0] ir_value;
wire exit1_dr;
wire exit2_dr;
wire capture_ir;
wire update_ir;
sld_virtual_jtag #(
.sld_auto_instance_index ("YES"),
.sld_instance_index (0),
.sld_ir_width (4),
.sld_sim_action (""),
.sld_sim_n_scan (0),
.sld_sim_total_length (0),
.lpm_type ("sld_virtual_jtag")
) sld_virtual_jtag_component (
.ir_out (ir_value),
.tdo (debug_tdo_i),
.tdi (tdi_o),
.jtag_state_rti (run_test_idle_o),
.tck (tck_o),
.ir_in (ir_value),
.jtag_state_tlr (test_logic_reset_o),
.virtual_state_cir (capture_ir),
.virtual_state_pdr (pause_dr_o),
.virtual_state_uir (update_ir),
.virtual_state_sdr (shift_dr_o),
.virtual_state_cdr (capture_dr_o),
.virtual_state_udr (update_dr_o),
.virtual_state_e1dr (exit1_dr),
.virtual_state_e2dr (exit2_dr)
);
assign debug_select_o = (ir_value == CMD_DEBUG);
endmodule
|
`include "bsg_defines.v"
`include "config_defs.v"
module cfgtag #(parameter packet_ID_width_p = 4
,parameter RELAY_NUM = 5)
(input clk // destination side clock from pins
,input reset // destination side reset from pins
,input cfg_clk_i // from IO pads
,input cfg_bit_i // from IO pads
// To raw network
,input credit_i
,output valid_o
,output logic [31:0] data_o
);
logic [32+packet_ID_width_p-1:0] data;
config_s config_in;
config_s [RELAY_NUM-1:0] relay_output;
assign config_in.cfg_clk = cfg_clk_i;
assign config_in.cfg_bit = cfg_bit_i;
relay_node relay_0 (.config_i(config_in),
.config_o(relay_output[0])
);
genvar inst;
generate
for (inst = 1; inst < RELAY_NUM; inst = inst + 1) begin: gen_block
relay_node relay(.config_i(relay_output[inst-1]),
.config_o(relay_output[inst]));
end
endgenerate
config_node#(.id_p(1)
,.data_bits_p(36)
,.default_p(36'd52)
) cfg_node_1
(.clk(clk)
,.reset(reset)
,.config_i(relay_output[RELAY_NUM-1])
,.data_o(data)
);
cfgtaggw #(.packet_ID_width_p(packet_ID_width_p)) cfgtagGW
(.clk(clk)
,.reset(reset)
,.cfgtag_data_i(data)
// To raw network
,.credit_i(credit_i)
,.valid_o(valid_o)
,.data_o(data_o)
);
endmodule
|
module top
(input [(`WIDTH):0] a, /* This comma gets deleted */
/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module nocomma
(/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module ifdefcomma
(
`ifdef a
input foo,
`endif
/*AUTOOUTPUT*/
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input b // To child of child.v
// End of automatics
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module ifdefnocomma
(
`ifdef a
// It's up to the user to deal with the , themself
input foo,
`endif
/*AUTOOUTPUT*/
);
child child(/*AUTOINST*/
// Inputs
.b (b));
endmodule
module child(input b);
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
@brief HiL test case for GP_LFOSC
OUTPUTS:
Oscillator output, divided by 2 (should be ~865 Hz)
*/
module LFOsc(clkout);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P13" *)
output wire clkout;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The oscillator
GP_LFOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OUT_DIV(2)
) lfosc (
.PWRDN(1'b0),
.CLKOUT(clkout)
);
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for wb_reg
*/
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
wbm_adr_i,
wbm_dat_i,
wbm_we_i,
wbm_sel_i,
wbm_stb_i,
wbm_cyc_i,
wbs_dat_i,
wbs_ack_i,
wbs_err_i,
wbs_rty_i);
$to_myhdl(wbm_dat_o,
wbm_ack_o,
wbm_err_o,
wbm_rty_o,
wbs_adr_o,
wbs_dat_o,
wbs_we_o,
wbs_sel_o,
wbs_stb_o,
wbs_cyc_o);
// dump file
$dumpfile("test_wb_reg.lxt");
$dumpvars(0, test_wb_reg);
end
wb_reg #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_sim_netlist.v
// Design : RAT_Mux2x1_10_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Mux2x1_10_0_0,Mux2x1_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux2x1_10,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Mux2x1_10_0_0
(A,
B,
SEL,
X);
input [9:0]A;
input [9:0]B;
input SEL;
output [9:0]X;
wire [9:0]A;
wire [9:0]B;
wire SEL;
wire [9:0]X;
RAT_Mux2x1_10_0_0_Mux2x1_10 U0
(.A(A),
.B(B),
.SEL(SEL),
.X(X));
endmodule
(* ORIG_REF_NAME = "Mux2x1_10" *)
module RAT_Mux2x1_10_0_0_Mux2x1_10
(X,
B,
A,
SEL);
output [9:0]X;
input [9:0]B;
input [9:0]A;
input SEL;
wire [9:0]A;
wire [9:0]B;
wire SEL;
wire [9:0]X;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\X[0]_INST_0
(.I0(B[0]),
.I1(A[0]),
.I2(SEL),
.O(X[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\X[1]_INST_0
(.I0(B[1]),
.I1(A[1]),
.I2(SEL),
.O(X[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\X[2]_INST_0
(.I0(B[2]),
.I1(A[2]),
.I2(SEL),
.O(X[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\X[3]_INST_0
(.I0(B[3]),
.I1(A[3]),
.I2(SEL),
.O(X[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\X[4]_INST_0
(.I0(B[4]),
.I1(A[4]),
.I2(SEL),
.O(X[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\X[5]_INST_0
(.I0(B[5]),
.I1(A[5]),
.I2(SEL),
.O(X[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\X[6]_INST_0
(.I0(B[6]),
.I1(A[6]),
.I2(SEL),
.O(X[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\X[7]_INST_0
(.I0(B[7]),
.I1(A[7]),
.I2(SEL),
.O(X[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\X[8]_INST_0
(.I0(B[8]),
.I1(A[8]),
.I2(SEL),
.O(X[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\X[9]_INST_0
(.I0(B[9]),
.I1(A[9]),
.I2(SEL),
.O(X[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
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#include <bits/stdc++.h> int n, m, op, det; int dir[2]; long long mv[2]; int ans[1111111]; int main() { scanf( %d%d , &n, &m); dir[1] = 1; dir[0] = -1; mv[1] = mv[0] = 0LL; for (int i = 0; i < m; i++) { scanf( %d , &op); if (op == 1) { scanf( %d , &det); mv[1] += det; mv[0] += det; if (det % 2) { dir[1] = -dir[1]; dir[0] = -dir[0]; } } else { mv[1] += dir[1]; mv[0] += dir[0]; dir[1] = -dir[1]; dir[0] = -dir[0]; } } mv[1] %= n; if (mv[1] < 0) mv[1] += n; mv[0] %= n; if (mv[0] < 0) mv[0] += n; for (int i = 1; i <= n; i++) { int id = i % 2; int p = i + mv[id]; if (p > n) p -= n; ans[p] = i; } for (int i = 1; i <= n; i++) printf( %d%c , ans[i], i < n ? : n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int binarySearch(int arr[], int l, int r, int x) { while (l <= r) { int m = l + (r - l) / 2; if (arr[m] == x) return m; if (arr[m] < x) l = m + 1; else r = m - 1; } return -1; } bool isprime(int n) { if (n <= 1) return false; for (int i = 2; i < n; i++) if (n % i == 0) return false; return true; } long long int factorial(int n) { if (n == 0) return 1; return n * factorial(n - 1); } int countDigit(long long n) { int count = 0; while (n != 0) { n = n / 10; ++count; } return count; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int v1, v2, t, d, sum = 0; cin >> v1 >> v2 >> t >> d; for (int i = 0; i < t; i++) sum += min(v2 + (t - 1 - i) * d, v1 + i * d); cout << sum; return 0; }
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#include <bits/stdc++.h> using namespace std; using int64 = long long; int main() { string s; cin >> s; int v[26] = {}; for (auto &c : s) v[c - a ]++; deque<int> odd; for (int i = 0; i < 26; i++) { if (v[i] % 2 == 1) odd.emplace_back(i); } while (odd.size() >= 2) { int p = odd.front(); int q = odd.back(); odd.pop_front(); odd.pop_back(); v[p]++; v[q]--; } string pre; for (int i = 0; i < 26; i++) { int t = v[i] / 2; while (t--) pre += (char)(i + a ); } cout << pre; if (odd.size()) cout << (char)( a + odd[0]); reverse(begin(pre), end(pre)); cout << pre << endl; }
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 10:58:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_stub.v
// Design : system_vga_hessian_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_1_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m; char s[25][25]; int c[25][25]; int chs[1 << 21]; int dp[1 << 21]; vector<int> hv; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %s , s[i]); } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { scanf( %d , c[i] + j); } } memset(chs, 0x3f, sizeof(chs)); for (int i = 0; i < n; ++i) { hv.push_back(1 << i); for (int j = 0; j < m; ++j) { chs[1 << i] = min(chs[1 << i], c[i][j]); } } for (int i = 0; i < m; ++i) { for (int j = 0; j < 26; ++j) { int num = 0, maxx = 0, sum = 0; for (int k = 0; k < n; ++k) { if (s[k][i] == j + a ) { num |= 1 << k; maxx = max(maxx, c[k][i]); sum += c[k][i]; } } if (!num) { continue; } if (chs[num] == 0x3f3f3f3f) { hv.push_back(num); } chs[num] = min(chs[num], sum - maxx); } } memset(dp, 0x3f, sizeof(dp)); dp[0] = 0; for (int i = 0; i < (1 << n) - 1; ++i) { for (int j : hv) { dp[i | j] = min(dp[i | j], dp[i] + chs[j]); } } printf( %d n , dp[(1 << n) - 1]); return 0; }
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#include <bits/stdc++.h> using namespace std; int main(){ ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int T; cin >> T; while(T--){ int X[210] = {}; int N, M; cin >> N >> M; for(int i = 0; i < N; i++){ for(int j = 0; j < M; j++){ int a; cin >> a; X[i+j] ^= a; } } bool ok = true; for(int i = 0; i < N+M-1; i++){ if(X[i]) ok = false; } cout << (ok ? Jeel n : Ashish n ); } }
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#include <bits/stdc++.h> using namespace std; long long int const lac = 100000; long long int modmul(long long int a, long long int b) { return ((a % 1000000007) * (b % 1000000007)) % 1000000007; } long long int modadd(long long int a, long long int b) { return (((a % 1000000007) + (b % 1000000007))) % 1000000007; } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } class comp { public: bool operator()(int a, int b) const { return a > b; } }; bool compa(int a, int b) { return a > b; } void solve(long long int t1) { long long int n; cin >> n; vector<long long int> arr(n + 1); for (long long int i = 1; i <= n; i++) { cin >> arr[i]; } vector<long long int> prefix(n + 1, 0); long long int ans = 0; for (long long int i = 1; i <= n; i++) { prefix[i] = prefix[i - 1] ^ i; ans ^= arr[i]; } if (n == 1) { cout << ans << n ; return; } for (long long int i = 1; i <= n - 1; i++) { long long int temp = (n) / (i + 1); long long int rem = n % i; if (temp & 1) { ans ^= prefix[i]; } ans ^= prefix[rem]; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; t = 1; for (long long int i = 1; i <= t; i++) { solve(t); } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { string s; char a[100010]; int k; cin >> s; k = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == a[k]) k--; else { k++; a[k] = s[i]; } } if (k == 0) cout << Yes ; else cout << No ; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; void substr(int start, int end, char in[], char out[]) { for (int i = start; i < end; ++i) out[i - start] = in[i]; out[end - start] = 0 ; } int main() { int n, p, q; char s[100]; cin >> n >> p >> q; cin >> s; int pdivmax = n / p + 1, qdivmax = n / q + 1; bool divided = false; if (p == q) { if (n % p == 0) { cout << n / p << endl; for (int i = 0; i < n; i += p) { char out[100]; substr(i, i + p, s, out); cout << out << endl; } divided = true; } } else { for (int i = 0; i < pdivmax; ++i) { for (int j = 0; j < qdivmax; ++j) { if (p * i + q * j == n) { cout << i + j << endl; for (int k = 0; k < p * i; k += p) { char out[100]; substr(k, k + p, s, out); cout << out << endl; } for (int k = p * i; k < n; k += q) { char out[100]; substr(k, k + q, s, out); cout << out << endl; } divided = true; break; } } if (divided) break; } } if (!divided) cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200 + 10; int main() { int n, arr[N]; char f; char ch[N]; scanf( %d , &n); cin >> ch; n = 2 * n; for (int i = 0; i < n; i++) arr[i] = ch[i] - 0 ; sort(arr, arr + n / 2); sort(arr + n / 2, arr + n); bool a = false, b = false; for (int i = 0; i < n / 2; i++) { if (arr[i] >= arr[n / 2 + i]) a = true; if (arr[i] <= arr[n / 2 + i]) b = true; } if (a && b) cout << NO ; else cout << YES ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000000000000; map<pair<long long, int>, long long> memo; long long solve(long long n, int x) { pair<long long, int> p = make_pair(n, x); if (memo.find(p) != memo.end()) return memo[p]; if (n == 0) return memo[p] = 0; if (n == 1) return memo[p] = (x == 0) ? 1 : 0; return memo[p] = solve((n + 1) / 2, x) + (x ? solve(n / 2, x - 1) : 0); } int main() { ios_base::sync_with_stdio(false); long long n, t; cin >> n >> t; for (int i = 0; (1ll << i) <= t; ++i) if (t == (1ll << i)) { cout << solve(n + 2, i + 1) - solve(2, i + 1); return 0; } cout << 0; return 0; }
|
#include <bits/stdc++.h> using namespace std; void go(int parent, int node, int depth, int& odd_count, int& even_count, vector<vector<int>>& tree) { int count = 0; for (int i = 0; i < tree[node].size(); i++) { if (tree[node][i] != parent) { count++; go(node, tree[node][i], depth + 1, odd_count, even_count, tree); } } if (count == 0) { odd_count += depth % 2; even_count += !(depth % 2); } } int main() { int n; scanf( %d , &n); vector<vector<int>> tree(n); for (int i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v); tree[u - 1].push_back(v - 1); tree[v - 1].push_back(u - 1); } int root = -1; for (int i = 0; i < tree.size(); i++) { if (tree[i].size() > 1) { root = i; break; } } int odd_count = 0, even_count = 0; go(-1, root, 0, odd_count, even_count, tree); int min_ans = 0, max_ans = n - 1; if (!odd_count || !even_count) { min_ans = 1; } else { min_ans = 3; } vector<int> parent_leaf_count(n, 0); for (int i = 0; i < n; i++) { if (tree[i].size() == 1) { parent_leaf_count[tree[i][0]]++; } } for (int i = 0; i < n; i++) { if (parent_leaf_count[i]) { max_ans -= (parent_leaf_count[i] - 1); } } printf( %d %d n , min_ans, max_ans); return 0; }
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } template <class T> int cntbit(T s) { return __builtin_popcount(s); } template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } int n; string s; long long u[2000005], d[2000005]; long long nu[2000005], nd[2000005]; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> s; memset(nu, 0, sizeof(nu)); memset(nd, 0, sizeof(nd)); memset(u, 0, sizeof(u)); memset(d, 0, sizeof(d)); for (int i = (1); i <= (n); ++i) { char ch = s[i - 1]; nu[i] = nu[i - 1]; nd[i] = nd[i - 1]; if (ch == U ) { nu[i]++; u[nu[i]] = u[nu[i] - 1] + i; } else { nd[i]++; d[nd[i]] = d[nd[i] - 1] + i; } } for (int i = (1); i <= (n); ++i) { char ch = s[i - 1]; long long res = 0; if (ch == U ) { long long numd = nd[n] - nd[i]; long long numu = nu[i]; if (numd < numu) { res += (d[nd[i] + numd] - d[nd[i]]) * 2 + n + 1; res -= (u[nu[i]] - u[nu[i] - numd - 1]) * 2 - i; } else { res += (d[nd[i] + numu] - d[nd[i]]) * 2; res -= (u[nu[i]]) * 2 - i; } } else { long long numd = nd[n] - nd[i - 1]; long long numu = nu[i]; if (numd <= numu) { res += (d[nd[i - 1] + numd] - d[nd[i - 1]]) * 2 + n + 1 - i; res -= (u[nu[i]] - u[nu[i] - numd]) * 2; } else { res += (d[nd[i] + numu] - d[nd[i - 1]]) * 2 - i; res -= (u[nu[i]]) * 2; } } cout << res << ; } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:50000000 ) using namespace std; int tt[1000000], kix[1000000], num[1000000], degree[1000000], black[1000000], fix[1000000]; vector<int> q, g[1000000]; int pirveli, p, i, j, n, m, k, a, b; int par[100005][20]; long long ans[1000000]; void go(int x, int prev = -1) { fix[x] = 1; q.push_back(x); for (int i = 0; i < g[x].size(); i++) { int nxt = g[x][i]; if (nxt == prev) continue; if (fix[nxt] == 0) { go(nxt, x); continue; } if (num[nxt] != -1) continue; for (int j = q.size() - 1; j >= 0; j--) { num[q[j]] = nxt; if (q[j] == nxt) break; } } q.pop_back(); } void DFS(int v, int prev, int deg, int raod) { kix[v] = 1; degree[v] = deg; if (tt[v] != 1) raod++; black[v] = raod; par[v][0] = num[prev]; for (int j = 1; j <= 19; j++) if (par[v][j - 1] == -1) par[v][j] = -1; else par[v][j] = par[par[v][j - 1]][j - 1]; for (int i = 0; i < g[v].size(); i++) { int nxt = g[v][i]; if (nxt == prev) continue; DFS(nxt, v, deg + 1, raod); } } int LCA(int a, int b) { for (int i = 18; i >= 0; i--) { if (degree[a] - (1 << i) >= degree[b]) { a = par[a][i]; } } if (a == b) return a; for (int i = 18; i >= 0; i--) { if (par[a][i] != par[b][i]) { a = par[a][i]; b = par[b][i]; } } return par[a][0]; } int main() { cin >> n >> m; for (i = 0; i < m; i++) { cin >> a >> b; a--; b--; g[a].push_back(b); g[b].push_back(a); } for (i = 0; i < n; i++) num[i] = -1; go(0); for (i = 0; i <= n; i++) for (j = 0; j <= 20; j++) par[i][j] = -1; for (i = 0; i < n; i++) { if (num[i] == -1 || num[i] == i) continue; for (j = 0; j < g[i].size(); j++) g[num[i]].push_back(g[i][j]); } for (i = 0; i < n; i++) if ((num[i] == -1 || num[i] == i)) { for (j = 0; j < g[i].size(); j++) { int nxt = g[i][j]; if (num[nxt] == i) { g[i][j] = g[i].back(); g[i].pop_back(); j--; } else if (num[nxt] == -1) continue; else g[i][j] = num[nxt]; } } if (num[0] == -1) pirveli = 0; else pirveli = num[0]; for (i = 0; i < n; i++) if (num[i] == -1) { num[i] = i; tt[i] = 1; } DFS(pirveli, -1, 0, 0); ans[0] = 1; for (i = 1; i <= n; i++) ans[i] = ans[i - 1] * 2 % 1000000007; cin >> k; while (k--) { cin >> a >> b; a = num[a - 1]; b = num[b - 1]; if (degree[a] < degree[b]) swap(a, b); p = LCA(a, b); p = num[p]; cout << ans[black[a] + black[b] - 2 * black[p] + (tt[p] == 0)] << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> adj[100005]; long long sn[100005], an[100005], level[100005]; long long got = 1; void dfs(long long u, long long par, long long carry) { if (sn[u] != -1 && sn[u] < carry) got = 0; level[u] = level[par] + 1; if (sn[u] != -1) { an[u] = sn[u] - carry; carry = sn[u]; } else an[u] = 0; for (auto it : adj[u]) { if (it != par) dfs(it, u, carry); } } void dfs2(long long u, long long par, long long carry) { if (level[u] & 1) { if (u != 1) { an[u] = sn[u] - carry; carry = sn[u]; } } else { long long mn = 1e15 + 7; for (auto it : adj[u]) if (it != par) mn = min(mn, sn[it]); if (mn != 1e15 + 7) { an[u] = mn - carry; carry = mn; } else an[u] = 0; } for (auto it : adj[u]) if (it != par) dfs2(it, u, carry); } int main() { long long i, j, k; long long n, m; cin >> n; for (i = 2; i <= n; i++) { cin >> m; adj[m].push_back(i); adj[i].push_back(m); } for (i = 1; i <= n; i++) cin >> sn[i]; dfs(1, 0, sn[1]); if (!got) { cout << -1 << endl; return 0; } dfs2(1, 0, sn[1]); an[1] = sn[1]; long long ans = 0; for (i = 1; i <= n; i++) ans += an[i]; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; map<long long int, int> mp; map<long long int, int> mpp; long long int a[100007]; long long int b[100007]; long long int bb[100007]; int main() { int m, p; scanf( %d %d , &m, &p); int i, j; for (i = 0; i < m; i++) scanf( %lld , a + i); for (i = 0; i < p; i++) scanf( %lld , b + i); sort(b, b + p); long long int ans = 0; long long int anss = 0; long long int ansss; bb[0] = 0; mp[0] = 1; mpp[0] = 1; for (i = 1; i < m; i++) anss = anss + a[i], mp[anss]++, bb[i] = anss; for (i = 0; i < m; i++) { anss = bb[i]; if (mpp[b[0] - anss - a[0]]) continue; mpp[b[0] - anss - a[0]] = 1; ansss = 1; j = 1; while (j < p) { anss = anss + b[j] - b[j - 1]; if (mp[anss]) { if (!(b[j] - anss - a[0])) ansss = 0; } else { ansss = 0; break; } j++; } ans = ans + ansss; } printf( %lld n , ans); return 0; }
|
// $Id: c_extractor.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// module for extracting a set of bits from an input word (result is
// concatenation of these bits)
module c_extractor
(data_in, data_out);
// width of input word
parameter width = 32;
function integer pop_count(input [0:width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask specifying which bits to extract
parameter [0:width-1] mask = {width{1'b1}};
// width of result
localparam new_width = pop_count(mask);
// input word
input [0:width-1] data_in;
// result
output [0:new_width-1] data_out;
reg [0:new_width-1] data_out;
reg unused;
integer idx1, idx2;
always @(data_in)
begin
unused = 1'b0;
idx2 = 0;
for(idx1 = 0; idx1 < width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx2] = data_in[idx1];
idx2 = idx2 + 1;
end
else
begin
unused = unused | data_in[idx1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
/*
*
* Copyright (c) 2011
* All Rights Reserved
*
*/
`timescale 1ns/1ps
module pipelined_normal_top (CLK_100MHZ);
parameter LOOP_LOG2 = 1;
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input CLK_100MHZ;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h0;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLK_IN1(CLK_100MHZ), .CLK_OUT1(hash_clk));
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
wire [35:0] control0, control1, control2;
chipscope_icon ICON_inst ( .CONTROL0(control0), .CONTROL1(control1), .CONTROL2(control2));
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
chipscope_vio_tochip midstate_vw_blk ( .CONTROL(control0), .CLK(hash_clk), .SYNC_OUT(midstate_vw) );
chipscope_vio_tochip data_vw_blk ( .CONTROL(control1), .CLK(hash_clk), .SYNC_OUT(data2_vw) );
//virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("STAT")) midstate_vw_blk(.probe(), .source(midstate_vw));
//virtual_wire # (.PROBE_WIDTH(0), .WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk(.probe(), .source(data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
chipscope_vio_fromchip golden_nonce_vw_blk ( .CONTROL(control2), .CLK(hash_clk), .SYNC_IN(golden_nonce) );
//virtual_wire # (.PROBE_WIDTH(32), .WIDTH(0), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.probe(golden_nonce), .source());
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
wire reset = 1'b0;
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_ls__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long k; scanf( %d , &n); scanf( %I64d , &k); int a; scanf( %d , &a); int ans = a; int count = 0; if (k > n - 2) { for (int i = 1; i < n; ++i) { scanf( %d , &a); if (a > ans) ans = a; } } else { for (int i = 1; i < n; ++i) { scanf( %d , &a); if (count == k) break; if (ans > a) count++; else { count = 1; ans = a; } } } printf( %d n , ans); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic [7:0] arr [7:0];
logic [7:0] arri [7:0];
has_array am1 (.clk(clk), .arri(arr), .arro(arri));
integer cyc; initial cyc = 0;
initial begin
for (int i = 0; i < 8; i++) begin
arr[i] = 0;
end
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 5 && arri[1] != 8) begin
$stop;
end
for (int i = 0; i < 7; ++i) begin
arr[i+1] <= arr[i];
end
arr[0] <= arr[0] + 1;
end
endmodule : t
module has_array (
input clk,
input logic [7:0] arri [7:0],
output logic [7:0] arro [7:0]
);
integer cyc; initial cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (arri[0] == 10 && cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge clk) begin
for (integer i = 0; i < 7; ++i) begin
arro[i+1] <= arro[i];
end
arro[0] = arro[0] + 2;
end
endmodule : has_array
|
#include <bits/stdc++.h> using namespace std; int arr[1000001], dp[(1 << 22)], N; int main() { scanf( %d , &N); memset(dp, -1, sizeof dp); for (int i = 0; i < N; i++) { scanf( %d , &arr[i]); dp[arr[i]] = arr[i]; } for (int i = 0; i < (1 << 22); i++) { for (int j = 0; j < 22; j++) { if (i & (1 << j)) { dp[i] = max(dp[i], dp[i ^ (1 << j)]); } } } for (int i = 0; i < N; i++) { int need = dp[((1 << 22) - 1) ^ arr[i]]; printf( %d%c , need, i == N - 1 ? n : ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long n; int k; cin >> n >> k; long l = 1, r = n; while (l < r) { long m = l + (r - l) / 2; long s = 0, v = m; while (v != 0) { s += v; v /= k; } if (s >= n) r = m; else l = m + 1; } cout << l << endl; return 0; }
|
module MemoryUnit
#(
parameter DATA_WIDTH = 32,
parameter MEMORY_ADDR_WIDTH = 13,
parameter BIOS_ADDRESS_WIDTH = 8,
parameter STORAGE_ADDR_WIDTH = 15,
parameter INSTRUCTION_SIZE = 16
)(
input allow_write_on_memory, slow_clock, fast_clock,
input [(DATA_WIDTH -1):0] original_address,
original_instruction_address,
MemOut,
input is_bios,
output [(INSTRUCTION_SIZE -1):0] output_instruction,
output [(DATA_WIDTH-1):0] data_read_from_memory
);
wire [(STORAGE_ADDR_WIDTH - 1) : 0] storage_addr;
wire [(DATA_WIDTH -1): 0] memory_data, storage_data;
wire is_storage;
wire [(INSTRUCTION_SIZE -1) : 0] memory_instruction,
bios_instruction;
MemoryController controller(
original_address,
is_storage,
storage_addr
);
Memory main_memory(
MemOut,
original_instruction_address[(MEMORY_ADDR_WIDTH - 1) : 0],
original_address[(MEMORY_ADDR_WIDTH - 1) : 0],
allow_write_on_memory, fast_clock, slow_clock,
memory_instruction,
memory_data
);
StorageDrive hd(
storage_addr,
MemOut,
is_storage && allow_write_on_memory , fast_clock, slow_clock,
storage_data
);
MemoryDataHandler poolMux(
is_storage,
storage_data, memory_data,
data_read_from_memory
);
BIOS bios(
fast_clock,
original_instruction_address[(BIOS_ADDRESS_WIDTH - 1):0],
bios_instruction
);
MemoryDataHandler #(.DATA_WIDTH(INSTRUCTION_SIZE))
instructionMUX(
is_bios,
bios_instruction,
memory_instruction,
output_instruction
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_0_V
`define SKY130_FD_SC_LP__O2111A_0_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_0 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111a_0 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_0_V
|
`begin_keywords "1364-2005"
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*
* $Id: sqrt32synth.v,v 1.2 2007/08/30 01:25:29 stevewilliams Exp $"
*/
/*
* This module approximates the square root of an unsigned 32bit
* number. The algorithm works by doing a bit-wise binary search.
* Starting from the most significant bit, the accumulated value
* tries to put a 1 in the bit position. If that makes the square
* too big for the input, the bit is left zero, otherwise it is set
* in the result. This continues for each bit, decreasing in
* significance, until all the bits are calculated or all the
* remaining bits are zero.
*
* Since the result is an integer, this function really calculates
* value of the expression:
*
* x = floor(sqrt(y))
*
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* which amounts to 16 clocks.
*/
module sqrt
(input clk,
output wire rdy,
input reset,
input [31:0] x,
output reg [15:0] acc);
//32
parameter ss=5; localparam w=1<<ss; //need to change in 2 places 1/2
// acc holds the accumulated result, and acc2 is the accumulated
// square of the accumulated result.
//reg [w/2-1:0] acc;
reg [w-1:0] acc2;
// Keep track of which bit I'm working on.
reg [ss-1:0] bitl;
wire [w/2-1:0] bit = 1 << bitl;
wire [w-1:0] bit2 = 1 << (bitl << 1);
// The output is ready when the bitl counter underflows.
assign rdy = bitl[ss-1];
// guess holds the potential next values for acc, and guess2 holds
// the square of that guess. The guess2 calculation is a little bit
// subtle. The idea is that:
//
// guess2 = (acc + bit) * (acc + bit)
// = (acc * acc) + 2*acc*bit + bit*bit
// = acc2 + 2*acc*bit + bit2
// = acc2 + 2 * (acc<<bitl) + bit
//
// This works out using shifts because bit and bit2 are known to
// have only a single bit in them.
wire [w/2-1:0] guess = acc | bit;
wire [w-1:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
(* ivl_synthesis_on *)
always @(posedge clk or posedge reset)
if (reset) begin
acc = 0;
acc2 = 0;
bitl = w/2-1;
end else begin
if (guess2 <= x) begin
acc <= guess;
acc2 <= guess2;
end
bitl <= bitl - 1;
end
endmodule // sqrt
module testBench;
parameter ss=5; parameter w=1<<ss; //need to change in 2 places 2/2
//parameter Amax= ;
parameter Amax= 10001; //quick test
reg [w-1:0] A;
reg clk, reset;
wire [(w/2)-1:0] Z;
wire done;
sqrt dut (.clk(clk), .rdy(done), .reset(reset), .x(A), .acc(Z));
(* ivl_synthesis_off *)
always #5 clk = !clk;
task reset_dut ;
begin
reset = 1;
@(posedge clk);
#1 reset = 0;
@(negedge clk);
end
endtask
task run_dut ;
begin
while (done==0)
begin
@(posedge clk);
end
end
endtask
integer idx, a, z, errCnt;
(* ivl_synthesis_off *)
initial
begin
reset = 0;
clk = 0;
$display ("ss=%d, width=%d, Amax=%d", ss, w, Amax);
errCnt = 0;
A = 4;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax/10;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
A = Amax-1;
reset_dut;
run_dut;
$display("test=0 x=%d, y=%d", A, Z);
for (idx = 1 ; idx < Amax; idx = 2*idx) begin
A = idx;
reset_dut;
run_dut;
$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z *z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1)*(z + 1)))
begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end
else
begin
$display ("Could not verify above number");
end
end
$display ("Running tests Amax=%d random input numbers", Amax);
for (idx = 0 ; idx < Amax; idx = 1+ idx) begin
A = $random;
// A = A - ((A / Amax) * Amax); //this is needed only if <32 bit
//A = idx; //sequential -- comment out to get random tests
if (A < 1<<(w-1)) begin
reset_dut;
run_dut;
//$display("%d: x=%d, y=%d", idx, A, Z);
a = A;
z = Z;
if (a < (z *z)) begin
$display("test=%d x=%d, y=%d ERROR:y is too big", idx, A, Z);
$display("FAILED");
$finish;
end
if (z<65535) // at this number y*y overflows, so cannot test this way
begin
if (a >= ((z + 1)*(z + 1)))
begin
$display("test=%d x=%d, y=%d ERROR: y is too small", idx, A, Z);
$display("FAILED");
$finish;
end
end
else
begin
$display ("Could not verify above number");
end
//$display("%d: x=%d, y=%d", idx, A, Z);
if (idx%1000 == 0) $display("Finished %d tests", idx);
end // if (A < Amax) begin
end
$display ("PASSED");
$finish;
end
endmodule
`end_keywords
|
#include <bits/stdc++.h> using namespace std; const long long int INF = 2e18; const long long int N = 2e5 + 5; bool isPrime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) { if (n % i == 0 || n % (i + 2) == 0) return false; } return true; } long long int factorial(long long int n) { long long int ans = 1; for (long long int i = 1; i <= n; i++) ans = (ans * i) % 1000000007; return ans; } long long int exp(long long int x, long long int n) { long long int res = 1; while (n > 0) { if (n % 2 == 1) res = (res * x) % 1000000007; x = (x * x) % 1000000007; n = n / 2; } return res; } void null() { long long int n; cin >> n; char a[n][n]; for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < n; j++) { cin >> a[i][j]; } } long long int ans = 0; if (a[0][1] == a[1][0]) { if (a[n - 1][n - 2] == a[n - 2][n - 1]) { if (a[n - 1][n - 2] == a[0][1]) { cout << 2 << n ; cout << 1 << << 2 << n ; cout << 2 << << 1 << n ; return; } else { cout << 0 << n ; return; } } if (a[n - 1][n - 2] != a[n - 2][n - 1]) { if (a[n - 1][n - 2] == a[0][1]) { cout << 1 << n ; cout << n << << n - 1 << n ; return; } else if (a[n - 2][n - 1] == a[0][1]) { cout << 1 << n ; cout << n - 1 << << n << n ; return; } } } else { if (a[n - 1][n - 2] == a[n - 2][n - 1]) { if (a[0][1] == a[n - 1][n - 2]) { cout << 1 << n ; cout << 1 << << 2 << n ; return; } else { cout << 1 << n ; cout << 2 << << 1 << n ; return; } } else { cout << 2 << n ; if (a[0][1] == a[n - 1][n - 2]) { cout << 1 << << 2 << n ; cout << n - 1 << << n << n ; return; } else if (a[0][1] == a[n - 2][n - 1]) { cout << 1 << << 2 << n ; cout << n << << n - 1 << n ; return; } } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t = 1; clock_t start, end; start = clock(); cin >> t; while (t--) { null(); } end = clock(); double time_taken = double(end - start) / double(CLOCKS_PER_SEC); }
|
#include <bits/stdc++.h> using namespace std; double PI = 3.14159265358979323846; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long get(long long x, long long n) { long long l, r; if (x > n) return 0; long long acc = 0; if (x % 2 == 0) { l = x; r = x + 1; } else { l = 2 * x; r = 2 * x + 1; acc += 1; } while (r <= n) { acc += r - l + 1; l *= 2; r = 2 * r + 1; } if (l <= n) acc += (n - l + 1); return acc; } int dfs(int x, vector<bool> &chk, vector<int> &val, int step, vector<map<int, int> > &e) { chk[x] = true; int maxval = -1e9 - 1; for (auto &k : e[x]) { if (chk[k.first]) continue; maxval = max(maxval, dfs(k.first, chk, val, step + 1, e)); } if (step == 0) maxval = max(maxval, val[x]); else if (step == 1) maxval = max(maxval, val[x] + 1); else maxval = max(maxval, val[x] + 2); return maxval; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> a(n + 1); int mmm = -1e9 - 1; for (int i = 0; i < n; i++) { cin >> a[i + 1]; mmm = max(mmm, a[i + 1]); } set<int> s; for (int i = 1; i <= n; i++) { if (a[i] == mmm) s.insert(i); } vector<map<int, int> > v(n + 1); for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; v[x][y] = 1; v[y][x] = 1; } vector<bool> chk(n + 1); if (s.size() == 1) { int ans = dfs(*(s.begin()), chk, a, 0, v); cout << ans << endl; } else { bool isok = false; for (int i = 1; i <= n; i++) { if (v[i].size() + 1 < s.size()) continue; bool isok2 = true; for (auto k : s) { if (v[i][k] != 1 && k != i) { isok2 = false; break; } } if (isok2) { isok = true; break; } } if (isok) { cout << mmm + 1 << endl; } else { cout << mmm + 2 << endl; } } return 0; }
|
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