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#include <bits/stdc++.h> using namespace std; char inp[2000]; int toNum(char x) { if (x >= 0 && x <= 9 ) return x - 0 ; return 10 + x - A ; } char toChar(int x) { if (x < 10) return 0 + x; return A + (x - 10); } long long ato10(int a) { int len = strlen(inp); int lw = 0; while (lw < len && inp[lw] == 0 ) lw++; if (lw >= len) return 0; long long ret = 0; for (int i = lw; i < len; i++) { ret = ret * a + toNum(inp[i]); } return ret; } char pI[] = { I , X , C , M }; char pV[] = { V , L , D }; int main() { int a, b; gets(inp); bool iR = false; int len = strlen(inp); for (int i = 0; i < len; i++) { if (inp[i] == R ) iR = true; } if (!iR) sscanf(inp, %d%d , &a, &b); else sscanf(inp, %d , &a); gets(inp); long long number = ato10(a); if (!iR) { string ret = ; if (number == 0) ret = 0 ; else { while (number) { ret = toChar(number % b) + ret; number /= b; } } printf( %s n , ret.c_str()); } else { int idx = 0; string ret = ; while (number) { int tdec = number % 10; number /= 10; if (tdec <= 3) for (int t = 0; t < tdec; t++) ret = pI[idx] + ret; else if (tdec == 4) { ret = pV[idx] + ret; ret = pI[idx] + ret; } else if (tdec == 5) ret = pV[idx] + ret; else if (tdec <= 8) { tdec -= 5; for (int t = 0; t < tdec; t++) ret = pI[idx] + ret; ret = pV[idx] + ret; } else { ret = pI[idx + 1] + ret; ret = pI[idx] + ret; } idx++; } printf( %s n , ret.c_str()); } return 0; }
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// testbench_7.v
////////////////////////////////////////////////////////////////////////////////
// a testbench using the suggested program of lab 7
////////////////////////////////////////////////////////////////////////////////
// Dimitrios Paraschas ()
////////////////////////////////////////////////////////////////////////////////
// inf.uth.gr
// ce232 Computer Organization and Design
////////////////////////////////////////////////////////////////////////////////
// lab 8
// Implementation of a collection of MIPS instructions parsing CPU.
////////////////////////////////////////////////////////////////////////////////
`include "constants.h"
`timescale 1ns/1ps
module cpu_tb;
// unchangeable parameters
// http://www.edaboard.com/thread194570.html
localparam N_REGISTERS = 32;
localparam IMS = 32;
localparam DMS = 64;
reg clock, reset; // clock and reset signals
integer i;
// CPU (clock, reset);
// module with multiple parameters
// http://www.asic-world.com/verilog/para_modules1.html
CPU #(.INSTR_MEM_SIZE(IMS), .DATA_MEM_SIZE(DMS)) CPU_0 (clock, reset);
always begin
#5;
clock = ~clock;
end
initial begin
// specify a VCD dump file and variables
// http://verilog.renerta.com/source/vrg00056.htm
$dumpfile("dumpfile_7.vcd");
$dumpvars(0, cpu_tb);
for (i = 0; i < N_REGISTERS; i = i + 1)
$dumpvars(1, CPU_0.Registers_0.data[i]);
for (i = 0; i < IMS; i = i + 1)
$dumpvars(1, CPU_0.InstructionMemory_0.data[i]);
for (i = 0; i < DMS; i = i + 1)
$dumpvars(1, CPU_0.DataMemory_0.data[i]);
// clock and reset signals
clock = 1;
reset = 0;
// load the program to the instruction memory
//$readmemh("program_7.mhex", CPU_0.InstructionMemory_0.data);
$readmemb("program_7.mbin", CPU_0.InstructionMemory_0.data);
// TODO
// zero waiting time is preferred
//#0;
#5;
reset = 1;
// initialize the registers
for (i = 0; i < N_REGISTERS; i = i + 1)
CPU_0.Registers_0.data[i] = i;
#55;
#30;
if ((CPU_0.Registers_0.data[1] == 1) &&
(CPU_0.Registers_0.data[2] == 2) &&
(CPU_0.Registers_0.data[3] == 3) &&
(CPU_0.Registers_0.data[4] == 4) &&
(CPU_0.Registers_0.data[5] == 5) &&
(CPU_0.Registers_0.data[6] == 6) &&
(CPU_0.Registers_0.data[7] == 7) &&
(CPU_0.Registers_0.data[8] == 24) &&
(CPU_0.Registers_0.data[9] == 5) &&
(CPU_0.Registers_0.data[10] == 10) &&
(CPU_0.Registers_0.data[11] == 11) &&
(CPU_0.Registers_0.data[12] == 12) &&
(CPU_0.Registers_0.data[13] == 13) &&
(CPU_0.Registers_0.data[14] == 14) &&
(CPU_0.Registers_0.data[15] == 15) &&
(CPU_0.Registers_0.data[16] == 16) &&
(CPU_0.Registers_0.data[17] == 16) &&
(CPU_0.Registers_0.data[18] == 0) &&
(CPU_0.Registers_0.data[19] == 19) &&
(CPU_0.Registers_0.data[20] == 20) &&
(CPU_0.Registers_0.data[21] == 21) &&
(CPU_0.Registers_0.data[22] == 22) &&
(CPU_0.Registers_0.data[23] == 23) &&
(CPU_0.Registers_0.data[24] == 24) &&
(CPU_0.Registers_0.data[25] == 25) &&
(CPU_0.Registers_0.data[26] == 26) &&
(CPU_0.Registers_0.data[27] == 27) &&
(CPU_0.Registers_0.data[28] == 28) &&
(CPU_0.Registers_0.data[29] == 29) &&
(CPU_0.Registers_0.data[30] == 30) &&
(CPU_0.Registers_0.data[31] == 31)) begin
$display("\n");
$display("program 7 completed successfully");
$display("\n");
end // if
else begin
$display("\n");
$display("program 7 failed");
$display("\n");
end // else
$finish;
end // initial
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_TB_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_TB_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2hv_lh.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg LOWHVPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LOWHVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LOWHVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LOWHVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LOWHVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LOWHVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LOWHVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__lsbufhv2hv_lh dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LOWHVPWR(LOWHVPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_TB_V
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#include <bits/stdc++.h> using namespace std; int n; vector<string> s; string ans(200, ); set<string> Set; vector<string> cand; int main() { cin >> n; ans.resize(2 * n - 2); for (int i = 0; i < 2 * n - 2; ++i) { string a; cin >> a; Set.insert(a); s.push_back(a); if (a.size() == n - 1) cand.push_back(a); } bool prefix = true, suffix = true; string P, S; for (int i = 1; i < n - 1; ++i) prefix &= Set.count(cand[0].substr(0, i)); for (int i = 1; i < n - 1; ++i) suffix &= Set.count(cand[1].substr(n - 1 - i)); if (suffix && prefix && cand[0].substr(1, n - 1) == cand[1].substr(0, n - 2)) P = cand[0], S = cand[1]; else P = cand[1], S = cand[0]; for (int i = 1; i <= n - 1; ++i) { string sub = P.substr(0, i); for (int j = 0; j < ans.size(); ++j) if (ans[j] == && s[j] == sub) { ans[j] = P ; break; } } for (int i = 0; i < ans.size(); ++i) if (ans[i] == ) ans[i] = S ; cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<string> ans; int main() { char c; string ss = ; while ((c = getchar()) != n ) { if ( a <= c && z >= c) { ss += c; continue; } else if (c == ) { if (!ss.empty()) { ans.push_back(ss); ss = ; } } else { if (!ss.empty()) { ans.push_back(ss); ss = ; } ans[ans.size() - 1] += c; } } if (!ss.empty()) ans.push_back(ss); for (int i = 0; i < ans.size(); i++) { cout << ans[i]; if (i == ans.size() - 1) cout << n ; else cout << ; } return 0; }
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module SmallSerDes #(
parameter BYPASS_GCLK_FF = "FALSE", // TRUE, FALSE
parameter DATA_RATE_OQ = "DDR", // SDR, DDR | Data Rate setting
parameter DATA_RATE_OT = "DDR", // SDR, DDR, BUF | Tristate Rate setting.
parameter integer DATA_WIDTH = 2, // {1..8}
parameter OUTPUT_MODE = "SINGLE_ENDED", // SINGLE_ENDED, DIFFERENTIAL
parameter SERDES_MODE = "NONE", // NONE, MASTER, SLAVE
parameter integer TRAIN_PATTERN = 0 // {0..15}
)
(
input wire CLK0,
input wire CLK1,
input wire CLKDIV,
input wire D1,
input wire D2,
input wire D3,
input wire D4,
input wire IOCE,
input wire OCE,
input wire RST,
input wire SHIFTIN1,
input wire SHIFTIN2,
input wire SHIFTIN3,
input wire SHIFTIN4,
input wire T1,
input wire T2,
input wire T3,
input wire T4,
input wire TCE,
input wire TRAIN,
output wire OQ,
output wire SHIFTOUT1,
output wire SHIFTOUT2,
output wire SHIFTOUT3,
output wire SHIFTOUT4,
output wire TQ
);
OSERDES2 #(
.BYPASS_GCLK_FF(BYPASS_GCLK_FF), // TRUE, FALSE
.DATA_RATE_OQ (DATA_RATE_OQ ), // SDR, DDR | Data Rate setting
.DATA_RATE_OT (DATA_RATE_OT ), // SDR, DDR, BUF | Tristate Rate setting.
.DATA_WIDTH (DATA_WIDTH ), // {1..8}
.OUTPUT_MODE (OUTPUT_MODE ), // SINGLE_ENDED, DIFFERENTIAL
.SERDES_MODE (SERDES_MODE ), // NONE, MASTER, SLAVE
.TRAIN_PATTERN (TRAIN_PATTERN ) // {0..15}
)
serdes0 (
.OQ(OQ),
.SHIFTOUT1(SHIFTOUT1),
.SHIFTOUT2(SHIFTOUT2),
.SHIFTOUT3(SHIFTOUT3),
.SHIFTOUT4(SHIFTOUT4),
.TQ(TQ),
.CLK0(CLK0),
.CLK1(CLK1),
.CLKDIV(CLKDIV),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.IOCE(IOCE),
.OCE(OCE),
.RST(RST),
.SHIFTIN1(SHIFTIN1),
.SHIFTIN2(SHIFTIN2),
.SHIFTIN3(SHIFTIN3),
.SHIFTIN4(SHIFTIN4),
.T1(T1),
.T2(T2),
.T3(T3),
.T4(T4),
.TCE(TCE),
.TRAIN(TRAIN)
);
endmodule
|
module automatic test();
function static integer accumulate1(input integer value);
static int acc = 1;
acc = acc + value;
return acc;
endfunction
function integer accumulate2(input integer value);
int acc = 1;
acc = acc + value;
return acc;
endfunction
localparam value1 = accumulate1(2);
localparam value2 = accumulate1(3);
localparam value3 = accumulate2(2);
localparam value4 = accumulate2(3);
integer value;
reg failed = 0;
initial begin
$display("%d", value1);
if (value1 !== 3) failed = 1;
$display("%d", value2);
if (value2 !== 4) failed = 1;
$display("%d", value3);
if (value3 !== 3) failed = 1;
$display("%d", value4);
if (value4 !== 4) failed = 1;
value = accumulate1(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate1(3);
$display("%d", value);
if (value !== 6) failed = 1;
value = accumulate2(2);
$display("%d", value);
if (value !== 3) failed = 1;
value = accumulate2(3);
$display("%d", value);
if (value !== 4) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> const int maxN = 2000; const unsigned int mod = 998244353; constexpr int inf = INT_MAX; class Array { public: inline const int *begin() const { return data; } inline const int *end() const { return endPtr; } inline void push_back(const int x) { *(endPtr++) = x; } inline size_t size() const { return endPtr - data; } template <class T> inline void foreach (T fun) const { std::for_each<const int *>(data, endPtr, fun); } private: int data[maxN + 10], *endPtr = data; }; Array edgeIn[maxN + 10], edgeOut[maxN + 10]; int originDegree[maxN + 10], degree[maxN + 10]; inline void reset(const int n) { std::memcpy(degree, originDegree, sizeof(degree[0]) * n); } void readGraph(const int n) { for (int i = 0; i < n; ++i) { static char str[maxN + 10]; std::cin >> str; for (int j = 0; j < n; ++j) if (str[j] == 1 ) { edgeIn[j].push_back(i); edgeOut[i].push_back(j); ++originDegree[i]; } } } bool isStrongConnect(const int n) { std::sort(degree, degree + n); int sum = 0; for (int i = 0; i + 1 < n; ++i) { sum += degree[i]; if (i * (i + 1) / 2 == sum) return false; } return true; } void reverseSet(const int n, const unsigned int set) { for (int i = 0; i < n; ++i) for (auto to : edgeOut[i]) if ((((set) >> (i)) & 0x01u) ^ (((set) >> (to)) & 0x01u)) { --degree[i]; ++degree[to]; } } inline bool checkSet(const int n, const unsigned int set) { reset(n); reverseSet(n, set); return isStrongConnect(n); } void reverseSingle(const int vertex) { edgeOut[vertex].foreach ([](int p) { ++degree[p]; }); edgeIn[vertex].foreach ([](int p) { --degree[p]; }); degree[vertex] = edgeIn[vertex].size(); } inline bool checkSingle(const int n, const int vertex) { reset(n); reverseSingle(vertex); return isStrongConnect(n); } unsigned int factor(const unsigned int n) { unsigned int ret = 1; for (unsigned int i = 2; i <= n; ++i) ret = (ret * i) % mod; return ret; } std::pair<int, int> enumSet(const int n) { int count = inf, solution = 0; const unsigned int msk = 1u << n; for (unsigned int i = 1; i < msk; ++i) { const int cnt = __builtin_popcount(i); if (cnt <= count && checkSet(n, i)) { if (cnt == count) ++solution; else { solution = 1; count = cnt; } } } return std::make_pair(count, count != inf ? (solution * factor(count)) % mod : 0); } std::pair<int, int> enumVertex(const int n) { int solution = 0; for (int i = 0; i < n; ++i) solution += checkSingle(n, i); return std::make_pair(1, solution); } int main() { std::ios::sync_with_stdio(false); int n; std::cin >> n; readGraph(n); reset(n); if (isStrongConnect(n)) { std::cout << 0 1 n ; return 0; } const auto [count, solution] = n <= 6 ? enumSet(n) : enumVertex(n); if (count == inf) std::cout << -1 n ; else std::cout << count << << solution << n ; return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_8_V
`define SKY130_FD_SC_HDLL__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_8_V
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#include <bits/stdc++.h> using namespace std; inline long long read() { long long res = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { res = res * 10 + c - 48; c = getchar(); } return res * f; } const long long N = 610; long long f[N][N]; long long a[N][N]; long long n, m, mod; long long in[N], o[N], s[N], t[N], tots, tott, tot; long long head[N], to[N * N], nxt[N * N], res; queue<long long> q; long long id[N]; long long qpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod; b >>= 1; } return res; } void add(long long x, long long y) { nxt[++tot] = head[x]; head[x] = tot; to[tot] = y; } void guess(long long n) { res = 1; for (long long i = 1; i <= n; ++i) { for (long long j = i + 1; j <= n; ++j) { while (a[j][i]) { long long v = a[i][i] * qpow(a[j][i], mod - 2) % mod; for (long long k = i; k <= n; ++k) a[i][k] = ((a[i][k] - 1LL * v * a[j][k] % mod) + mod) % mod; swap(a[i], a[j]), res = -res; } } } for (long long i = 1; i <= n; ++i) { res = (1ll * res * a[i][i] % mod + mod) % mod; } } signed main() { n = read(), m = read(), mod = read(); for (long long i = 1; i <= m; ++i) { long long x = read(), y = read(); in[y]++, o[x]++; add(x, y); } for (long long i = 1; i <= n; ++i) { if (in[i] == 0) s[++tots] = i; if (o[i] == 0) t[++tott] = i; } for (long long i = 1; i <= n; ++i) if (!in[i]) q.push(i); tot = 0; while (q.size()) { long long u = q.front(); q.pop(); id[++tot] = u; for (long long i = head[u]; i; i = nxt[i]) { long long v = to[i]; --in[v]; if (!in[v]) q.push(v); } } for (long long i = 1; i <= n; ++i) { long long u = id[i]; f[u][u] = 1; for (long long j = i; j <= n; ++j) { long long v = id[j]; for (long long k = head[v]; k; k = nxt[k]) { long long vv = to[k]; f[u][vv] = (f[u][vv] + f[u][v]) % mod; } } } for (long long i = 1; i <= tots; ++i) { for (long long j = 1; j <= tott; ++j) { a[i][j] = f[s[i]][t[j]]; } } guess(tots); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const long long inf = 1e18; const double eps = 1e-9; const double pi = 4 * atan(1.0); const int N = int(2e5) + 100; const int ITERS = 80; int m; pair<int, int> a[N]; vector<pair<int, int> > group[N]; long long sum_t[N]; int p[N]; double fen_suff[N]; inline long long val(const pair<int, int>& a, const pair<int, int>& b) { return 1LL * a.first * b.second - 1LL * b.first * a.second; } inline bool cmp(const pair<int, int>& a, const pair<int, int>& b) { return val(a, b) > 0; } inline void add_suff(int cp, double val) { int pos = lower_bound(p, p + m, cp) - p; assert(pos < m && p[pos] == cp); while (pos >= 0) { if (val < fen_suff[pos]) { fen_suff[pos] = val; } else { break; } pos = (pos & (pos + 1)) - 1; } } inline double get_suff(int cp) { int pos = lower_bound(p, p + m, cp) - p; assert(pos < m && p[pos] == cp); double res = 1e100; ++pos; while (pos < m) { res = min(res, fen_suff[pos]); pos = (pos | (pos + 1)); } return res; } int main() { int n; cin >> n; for (int i = 0; i < n; ++i) { scanf( %d , &a[i].first); } for (int i = 0; i < n; ++i) { scanf( %d , &a[i].second); } sort(a, a + n, cmp); for (int i = 0; i < n; ++i) { p[i] = a[i].first; } sort(p, p + n); m = unique(p, p + n) - p; int i = 0, sz = 0; while (i < n) { int j = i; while (j + 1 < n && val(a[i], a[j + 1]) == 0) { ++j; } for (int z = i; z <= j; ++z) { group[sz].push_back(a[z]); } sort((group[sz]).begin(), (group[sz]).end()); ++sz; i = j + 1; } for (int i = 0; i < sz; ++i) { if (i > 0) { sum_t[i] += sum_t[i - 1]; } for (pair<int, int> p : group[i]) { sum_t[i] += p.second; } } double l = 0, r = 1; for (int it = 0; it < ITERS; ++it) { double mid = (l + r) / 2; for (int i = 0; i < m; ++i) { fen_suff[i] = 1e100; } bool fl = false; for (int i = sz - 1; i >= 0 && !fl; --i) { int ptr = ((int)(group[i]).size()) - 1; for (int j = ((int)(group[i]).size()) - 1; j >= 0; --j) { while (group[i][ptr].first > group[i][j].first) { add_suff( group[i][ptr].first, group[i][ptr].first * (1.0 - mid * sum_t[i] / sum_t[sz - 1])); --ptr; } if (group[i][j].first * (1.0 - mid * ((i > 0 ? sum_t[i - 1] : 0) + group[i][j].second) / sum_t[sz - 1]) > get_suff(group[i][j].first)) { fl = true; break; } } while (ptr >= 0) { add_suff(group[i][ptr].first, group[i][ptr].first * (1.0 - mid * sum_t[i] / sum_t[sz - 1])); --ptr; } } if (fl) { r = mid; continue; } for (int i = 0; i < m; ++i) { fen_suff[i] = 1e100; } for (int i = 0; i < sz && !fl; ++i) { int ptr = ((int)(group[i]).size()) - 1; for (int j = ((int)(group[i]).size()) - 1; j >= 0; --j) { while (group[i][ptr].first > group[i][j].first) { add_suff( group[i][ptr].first, group[i][ptr].first * (1.0 - mid * sum_t[i] / sum_t[sz - 1])); --ptr; } if (group[i][j].first * (1.0 - mid * ((i > 0 ? sum_t[i - 1] : 0) + group[i][j].second) / sum_t[sz - 1]) > get_suff(group[i][j].first)) { fl = true; break; } } while (ptr >= 0) { add_suff(group[i][ptr].first, group[i][ptr].first * (1.0 - mid * sum_t[i] / sum_t[sz - 1])); --ptr; } } if (fl) { r = mid; } else { l = mid; } } printf( %.18lf n , (l + r) / 2); return 0; }
|
`include "defines.v"
module data_ram(
input wire clk,
input wire ce,
input wire we,
input wire[`DataAddrBus] addr,
input wire[3:0] sel,
input wire[`DataBus] data_i,
output reg[`DataBus] data_o,
output wire[`DataBus] check,
input wire[2:0] direction,
output wire signal,
output reg[15:0] point,
input wire[7:0] AppleX,
input wire[7:0] AppleY,
inout wire[1:0] gamestatus,
output [7:0] snake
);
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
always @ (posedge clk) begin
if (ce == `ChipDisable) begin
//data_o <= ZeroWord;
end else if(we == `WriteEnable) begin
if(addr[`DataMemNumLog2+1:2] == 0) begin
data_mem3[0] <= 8'b0;
data_mem2[0] <= 8'b0;
data_mem1[0] <= 8'b0;
data_mem0[0] <= direction;
end
else if(addr[`DataMemNumLog2+1:2] == 22) begin
data_mem3[22] <= 8'b0;
data_mem2[22] <= 8'b0;
data_mem1[22] <= 8'b0;
data_mem0[22] <= AppleX;
end
else if(addr[`DataMemNumLog2+1:2] == 23) begin
data_mem3[23] <= 8'b0;
data_mem2[23] <= 8'b0;
data_mem1[23] <= 8'b0;
data_mem0[23] <= AppleY;
end
else begin
if (sel[3] == 1'b1) begin
data_mem3[addr[`DataMemNumLog2+1:2]] <= data_i[31:24];
end
if (sel[2] == 1'b1) begin
data_mem2[addr[`DataMemNumLog2+1:2]] <= data_i[23:16];
end
if (sel[1] == 1'b1) begin
data_mem1[addr[`DataMemNumLog2+1:2]] <= data_i[15:8];
end
if (sel[0] == 1'b1) begin
data_mem0[addr[`DataMemNumLog2+1:2]] <= data_i[7:0];
end
end
end
end
always @ (*) begin
if (ce == `ChipDisable) begin
data_o <= `ZeroWord;
end else if(we == `WriteDisable) begin
data_o <= {data_mem3[addr[`DataMemNumLog2+1:2]],
data_mem2[addr[`DataMemNumLog2+1:2]],
data_mem1[addr[`DataMemNumLog2+1:2]],
data_mem0[addr[`DataMemNumLog2+1:2]]};
point <= {data_mem1[24], data_mem0[24]} - 16'd3;
end else begin
data_o <= `ZeroWord;
end
end
assign snake = data_mem0[28];
assign gamestatus = 2'b01;
assign signal = (data_mem0[25] == 0) ? 0 : 1;
assign check = {data_mem3[0], data_mem2[0], data_mem1[0], data_mem0[0]};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: bwiec
// Create Date: Mon Jun 05 07:43:03 MDT 2015
// Design Name: dma_controller
// Module Name: tlast_gen
// Project Name: DMA Controller
// Target Devices: All
// Tool Versions: 2015.1
// Description: Generate tlast based on configured packet length
//
// Dependencies: None
//
// Revision:
// - Rev 0.20 - Behavior verified in hardware testcase
// - Rev 0.10 - Behavior verified in behavioral simulation
// - Rev 0.01 - File created
//
// Known Issues:
// - Rev 0.20 - None
// - Rev 0.10 - None
// - Rev 0.01 - None
//
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tlast_gen
#(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
)
(
// Clocks and resets
input aclk,
input resetn,
// Control signals
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
// Slave interface
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
// Master interface
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [TDATA_WIDTH-1:0] m_axis_tdata
);
// Internal signals
wire new_sample;
reg [$clog2(MAX_PKT_LENGTH):0] cnt = 0;
// Pass through control signals
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
// Count samples
assign new_sample = s_axis_tvalid & s_axis_tready;
always @ (posedge aclk) begin
if (~resetn | (m_axis_tlast & new_sample))
cnt <= 0;
else
if (new_sample)
cnt <= cnt + 1'b1;
end
// Generate tlast
assign m_axis_tlast = (cnt == pkt_length-1);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_BEHAVIORAL_PP_V
|
/***********************************************************************
Single Port RAM that maps to a Xilinx/Lattice BRAM
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This is a program memory for the AVR. It maps to a Xilinx/Lattice
BRAM.
This version can be modified by the CPU (i. e. SPM instruction)
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the BSD license
------------------------------------------------------------------------------
Design unit: SinglePortPM(Xilinx) (Entity and architecture)
File name: pm_s_rw.in.v (template used)
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
Target FPGA: Spartan 3 (XC3S1500-4-FG456)
iCE40 (iCE40HX4K)
Language: Verilog
Wishbone: No
Synthesis tools: Xilinx Release 9.2.03i - xst J.39
iCEcube2.2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module lattuino_1_blPM_2S
#(
parameter WORD_SIZE=16,// Word Size
parameter FALL_EDGE=0, // Ram clock falling edge
parameter ADDR_W=13 // Address Width
)
(
input clk_i,
input [ADDR_W-1:0] addr_i,
output [WORD_SIZE-1:0] data_o,
input we_i,
input [WORD_SIZE-1:0] data_i
);
localparam ROM_SIZE=2**ADDR_W;
reg [ADDR_W-1:0] addr_r;
reg [WORD_SIZE-1:0] rom[0:ROM_SIZE-1];
initial begin
$readmemh("../../../Work/lattuino_1_bl_2s_v.dat",rom,696);
end
generate
if (!FALL_EDGE)
begin : use_rising_edge
always @(posedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_rising_edge
else
begin : use_falling_edge
always @(negedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_falling_edge
endgenerate
assign data_o=rom[addr_r];
endmodule // lattuino_1_blPM_2S
|
#include <bits/stdc++.h> using namespace std; int main() { string str; cin >> str; string s = WUB ; size_t pos = str.find(s); while (pos != string::npos) { string token = str.substr(0, pos); if (token.length() != 0) cout << token << ; str.erase(0, pos + 3); pos = str.find(s); } cout << str << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> istream &operator>>(istream &in, pair<T1, T2> &P) { in >> P.first >> P.second; return in; } template <class T1, class T2> ostream &operator<<(ostream &out, const pair<T1, T2> &P) { out << ( << P.first << , << P.second << ) ; return out; } template <class T> istream &operator>>(istream &in, vector<T> &arr) { for (auto &x : arr) in >> x; return in; } template <class T> ostream &operator<<(ostream &out, const vector<T> &arr) { for (auto &x : arr) out << x << ; cout << n ; return out; } template <class T> istream &operator>>(istream &in, deque<T> &arr) { for (auto &x : arr) in >> x; return in; } template <class T> ostream &operator<<(ostream &out, const deque<T> &arr) { for (auto &x : arr) out << x << ; cout << n ; return out; } int f(int x, int y) { if (x % y == 0) { return f(x / y, y); } return x; } int n, k; int32_t main() { mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int u = 900000; cin >> n >> k; vector<int> v(n); cin >> v; vector<int> stv = v; while (u--) { vector<pair<int, int> > op; stv = v; while (v.size() > 1) { shuffle(v.begin(), v.end(), rng); pair<int, int> nv; nv.first = v.back(); int second = v.back(); v.pop_back(); nv.second = v.back(); second += v.back(); v.pop_back(); op.push_back(nv); v.push_back(f(second, k)); } if (v[0] == 1) { cout << YES << endl; for (auto w : op) { cout << w.first << << w.second << endl; } return 0; } v = stv; } cout << NO << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:18:40 03/03/2016
// Design Name:
// Module Name: register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module register(clock_in, readReg1,readReg2, writeReg,writeData,regWrite,readData1,readData2);
input clock_in;
input [25:21] readReg1;
input [20:16] readReg2;
input [4:0] writeReg;
input [31:0] writeData;
input regWrite;
output [31:0] readData1;
output [31:0] readData2;
reg[31:0] regFile[31:0];
reg[31:0] readData1;
reg[31:0] readData2;
integer i;
initial //³õʼ»¯
begin
for(i = 0; i < 32; i = i + 1)
regFile[i] = 0;
readData1 = 0;
readData2 = 0;
end
always @ (readReg1 or readReg2) //Ïò¼Ä´æÆ÷¶ÁÊý¾Ý
begin
readData1 = regFile[readReg1];
readData2 = regFile[readReg2];
end
always @ (negedge clock_in) //Ïò¼Ä´æÆ÷дÊý¾Ý
begin
if(regWrite)
regFile[writeReg] = writeData;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
ref_clk,
clk,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_MMCM_TYPE = 0;
input ref_clk;
output clk;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_clkgen #(.MMCM_TYPE (C_MMCM_TYPE)) i_clkgen (
.ref_clk (ref_clk),
.clk (clk),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const long double PI2 = atan2(1.L, 0.L); int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; long double r; cin >> n >> r; long double res = r * r * n * sin(PI2 / n) * sin(2 * PI2 / n) / sin(3 * PI2 / n); cout << fixed << setprecision(10) << res << n ; }
|
`timescale 1 ns / 1 ps
`include "interface_axi_master_v1_0_tb_include.vh"
module interface_axi_master_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
reg M00_AXI_INIT_AXI_TXN;
wire M00_AXI_TXN_DONE;
wire M00_AXI_ERROR;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn),
.M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
.M00_AXI_ERROR(M00_AXI_ERROR),
.M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN));
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
M00_AXI_INIT_AXI_TXN = 1'b0;
#500 M00_AXI_INIT_AXI_TXN = 1'b1;
$display("EXAMPLE TEST M00_AXI:");
wait( M00_AXI_TXN_DONE == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if ( M00_AXI_ERROR ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
end
endmodule
|
/* wb_data_resize. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
module wb_data_resize
#(parameter aw = 32, //Address width
parameter mdw = 32, //Master Data Width
parameter sdw = 8, //Slave Data Width
parameter [47:0] endian = "big") // Endian for byte reads/writes
(//Wishbone Master interface
input [aw-1:0] wbm_adr_i,
input [mdw-1:0] wbm_dat_i,
input [3:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
input [2:0] wbm_cti_i,
input [1:0] wbm_bte_i,
output [mdw-1:0] wbm_dat_o,
output wbm_ack_o,
output wbm_err_o,
output wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [sdw-1:0] wbs_dat_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [sdw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
assign wbs_adr_o[aw-1:2] = wbm_adr_i[aw-1:2];
generate if (endian == "little") begin : le_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2'd3 :
wbm_sel_i[2] ? 2'd2 :
wbm_sel_i[1] ? 2'd1 : 2'd0;
end else begin : be_resize_gen
assign wbs_adr_o[1:0] = wbm_sel_i[3] ? 2'd0 :
wbm_sel_i[2] ? 2'd1 :
wbm_sel_i[1] ? 2'd2 : 2'd3;
end endgenerate
assign wbs_dat_o = wbm_sel_i[3] ? wbm_dat_i[31:24] :
wbm_sel_i[2] ? wbm_dat_i[23:16] :
wbm_sel_i[1] ? wbm_dat_i[15:8] :
wbm_sel_i[0] ? wbm_dat_i[7:0] : 8'b0;
assign wbs_we_o = wbm_we_i;
assign wbs_cyc_o = wbm_cyc_i;
assign wbs_stb_o = wbm_stb_i;
assign wbs_cti_o = wbm_cti_i;
assign wbs_bte_o = wbm_bte_i;
assign wbm_dat_o = (wbm_sel_i[3]) ? {wbs_dat_i, 24'd0} :
(wbm_sel_i[2]) ? {8'd0 , wbs_dat_i, 16'd0} :
(wbm_sel_i[1]) ? {16'd0, wbs_dat_i, 8'd0} :
{24'd0, wbs_dat_i};
assign wbm_ack_o = wbs_ack_i;
assign wbm_err_o = wbs_err_i;
assign wbm_rty_o = wbs_rty_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O31A_PP_SYMBOL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o31a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_PP_SYMBOL_V
|
module \$__NX_PDPSC512K (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 14;
parameter CFG_DBITS = 32;
parameter CFG_ENABLE_A = 4;
parameter CLKPOL2 = 1;
parameter [524287:0] INIT = 524287'b0;
input CLK2;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
wire clk;
wire [31:0] rd;
assign B1DATA = rd[CFG_DBITS-1:0];
generate
if (CLKPOL2)
assign clk = CLK2;
else
INV clk_inv_i (.A(CLK2), .Z(clk));
endgenerate
wire we = |A1EN;
localparam INIT_CHUNK_SIZE = 4096;
function [5119:0] permute_init;
input [INIT_CHUNK_SIZE-1:0] chunk;
integer i;
begin
for (i = 0; i < 128; i = i + 1'b1)
permute_init[i * 40 +: 40] = {8'b0, chunk[i * 32 +: 32]};
end
endfunction
generate
PDPSC512K #(
.OUTREG("NO_REG"),
.ECC_BYTE_SEL("BYTE_EN"),
`include "lrams_init.vh"
.GSR("DISABLED")
) _TECHMAP_REPLACE_ (
.CLK(clk), .RSTR(1'b0),
.DI(A1DATA), .ADW(A1ADDR), .CEW(we), .WE(we), .CSW(1'b1),
.ADR(B1ADDR), .DO(rd), .CER(B1EN), .CSR(1'b1),
);
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; int mn = INT_MAX; int cnt = 0; for (int i = n - 1; i >= 0; i--) { if (v[i] > mn) cnt++; mn = min(mn, v[i]); } cout << cnt << n ; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; int dp[10][10][10][10]; for (int i = 0; i < 10; i++) for (int j = 0; j < 10; j++) for (int k = 0; k < 10; k++) for (int l = 0; l < 10; l++) { dp[i][j][k][l] = INT_MAX; for (int t1 = 0; t1 <= 10; t1++) { for (int t2 = 0; t2 <= 10; t2++) { if ((t1 * i + t2 * j) % 10 == (l - k + 10) % 10 && (t1 != 0 || t2 != 0)) { dp[i][j][k][l] = min(dp[i][j][k][l], t1 + t2); } } } } for (int i = 0; i < 10; i++) { for (int j = 0; j < 10; j++) { int ans = 0; for (int k = 0; k < s.length() - 1; k++) { if (dp[i][j][s[k] - 0 ][s[k + 1] - 0 ] == INT_MAX) { ans = -1; break; } else { ans += max(0, dp[i][j][s[k] - 0 ][s[k + 1] - 0 ] - 1); } } cout << ans << ; } cout << endl; } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:32:13 02/28/2016
// Design Name: Alu
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/tes.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tes;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0] aluRes;
// Instantiate the Unit Under Test (UUT)
Alu uut (
.input1(input1),
.input2(input2),
.aluCtr(aluCtr),
.zero(zero),
.aluRes(aluRes)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
aluCtr = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : fw_interface_logic.v
// Description : FW Interface Test Logic
// Author : Philip Tracton
// Created On : Wed Dec 21 14:09:23 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 21 14:09:23 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "timescale.v"
`ifdef SIMULATION
`include "simulation_includes.vh"
`endif
module fw_interface_logic (/*AUTOARG*/
// Inputs
wb_clk_i, wb_rst_i, new_report, new_warning, new_error,
new_compare, report_reg, warning_reg, error_reg, expected_reg,
measured_reg, index, data, write_mem
) ;
input wire wb_clk_i;
input wire wb_rst_i;
input wire new_report;
input wire new_warning;
input wire new_error;
input wire new_compare;
input wire [31:0] report_reg;
input wire [31:0] warning_reg;
input wire [31:0] error_reg;
input wire [31:0] expected_reg;
input wire [31:0] measured_reg;
input wire [5:0] index;
input wire [7:0] data;
input wire write_mem;
`ifdef SIMULATION
reg [7:0] string_mem[8*64:0];
always @(posedge wb_clk_i)
if (write_mem) begin
string_mem[index] <= data;
end
wire new_report_rising;
edge_detection new_report_edge(
// Outputs
.rising(new_report_rising),
.failling(),
// Inputs
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.signal(new_report)
);
integer i;
reg [8*64:0] test_string;
always @ (posedge new_report_rising) begin
i = 0;
test_string = 0;
while (string_mem[i] != 8'h0) begin
#1 test_string = {test_string[8*29:0], string_mem[i]};
#1 string_mem[i] = 0;
#1 i = i + 1;
end
`TEST_COMPARE(test_string,0,0);
end // always @ (posedge new_report_rising)
wire new_compare_rising;
edge_detection new_compare_edge(
// Outputs
.rising(new_compare_rising),
.failling(),
// Inputs
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.signal(new_compare)
);
always @ (posedge new_compare_rising) begin
i = 0;
test_string = 0;
while (string_mem[i] != 8'h0) begin
#1 test_string = {test_string[8*29:0], string_mem[i]};
#1 string_mem[i] = 0;
#1 i = i + 1;
end
`TEST_COMPARE(test_string,expected_reg,measured_reg);
end // always @ (posedge new_report_rising)
`endif
endmodule // fw_interface_logic
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_2_V
`define SKY130_FD_SC_HD__NAND4_2_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_TB_V
`define SKY130_FD_SC_LS__CONB_TB_V
/**
* conb: Constant value, low, high outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__conb.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire HI;
wire LO;
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__conb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .HI(HI), .LO(LO));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_TB_V
|
#include <bits/stdc++.h> int days(int y) { if (y % 400 == 0 || (y % 4 == 0 && y % 100 != 0)) { return 366; } else { return 365; } } int main() { int year, i, d, di, dii; unsigned long long int count = 0; scanf( %d , &year); d = days(year); di = d; for (i = year;; i++) { dii = days(i + 1); count += di; if (count % 7 == 0 && d == dii) { printf( %d n , i + 1); return 0; } di = dii; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int Id[2 * 105]; int L[2 * 105]; int W[2 * 105]; long long int dp[2 * 105][3005]; bool vis[2 * 105][3005]; int n, l; long long int solve(int LastTp, int Len) { if (Len > l) return 0LL; if (Len == l) return 1LL; if (vis[LastTp][Len] == 1) return dp[LastTp][Len]; vis[LastTp][Len] = 1; long long int ret = 0; for (int i = 1; i <= n; i++) { if (Id[i] == Id[LastTp]) continue; if (W[LastTp] == L[i]) ret = (ret + solve(i, Len + L[i])) % 1000000007; } return dp[LastTp][Len] = ret; } int main() { int N, x, y; scanf( %d %d , &N, &l); for (int i = 1; i <= N; i++) { scanf( %d %d , &x, &y); L[++n] = x; W[n] = y; Id[n] = i; if (x != y) { L[++n] = y; W[n] = x; Id[n] = i; } } long long int Sum = 0; for (int i = 1; i <= n; i++) Sum = (Sum + solve(i, L[i])) % 1000000007; cout << Sum << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_PP_BLACKBOX_V
`define SKY130_FD_IO__TOP_REFGEN_PP_BLACKBOX_V
/**
* top_refgen: The REFGEN block (sky130_fd_io__top_refgen) is used to
* provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
* Verilog HDL for "sky130_fd_io",
* "sky130_fd_io_top_refgen" "behavioral_tmp".
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen (
VINREF ,
VOUTREF ,
REFLEAK_BIAS,
HLD_H_N ,
IBUF_SEL ,
OD_H ,
VOHREF ,
VREF_SEL ,
VREG_EN ,
VTRIP_SEL ,
VCCD ,
VCCHIB ,
VDDA ,
VDDIO ,
VDDIO_Q ,
VSSD ,
VSSIO ,
VSSIO_Q
);
output VINREF ;
output VOUTREF ;
inout REFLEAK_BIAS;
input HLD_H_N ;
input IBUF_SEL ;
input OD_H ;
input VOHREF ;
input VREF_SEL ;
input VREG_EN ;
input VTRIP_SEL ;
inout VCCD ;
inout VCCHIB ;
inout VDDA ;
inout VDDIO ;
inout VDDIO_Q ;
inout VSSD ;
inout VSSIO ;
inout VSSIO_Q ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int Power(int base, int exp) { int ans = 1; while (exp > 0) { if (exp & 1) ans = (1LL * ans * base) % 1000000007; exp = exp >> 1; base = (1LL * base * base) % 1000000007; } return ans; } vector<map<long double, int> > p_CntS(2005); int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; long double x[n], y[n]; for (int i = 0; i < n; i += 1) cin >> x[i] >> y[i]; long double slope; for (int p1 = 0; p1 < n; p1 += 1) for (int p2 = 0; p2 < n; p2 += 1) { if (p1 == p2) continue; slope = y[p2] - y[p1]; if (x[p2] - x[p1] == 0) p_CntS[p1][600.0]++; else p_CntS[p1][300.0 + slope / (x[p2] - x[p1])]++; } long long int ans = (1LL * n * (n - 1) * (n - 2)) / 6, ans_ = 0; int cnt; for (int i = 0; i < n; i += 1) { map<long double, int>::iterator it = p_CntS[i].begin(); while (it != p_CntS[i].end()) { cnt = (*it).second; ans_ += 1LL * cnt * (cnt - 1) / 2; it++; } } cout << ans - ans_ / 3 << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:42:35 09/12/2015
// Design Name: CPU
// Module Name: Z:/share/ISE/CPUFly/tests/CPU_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CPU_test;
// Inputs
reg clk;
reg reset;
reg [31:0] inst;
reg [31:0] Data_I;
reg ACK;
// Outputs
wire [31:0] pc;
wire [31:0] Addr;
wire [31:0] Data_O;
wire WE;
wire STB;
wire [31: 0] debug_next_pc;
// Instantiate the Unit Under Test (UUT)
CPU uut (
.clk(clk),
.reset(reset),
.pc(pc),
.inst(inst),
.Addr(Addr),
.Data_I(Data_I),
.Data_O(Data_O),
.WE(WE),
.ACK(ACK),
.STB(STB),
.debug_next_pc(debug_next_pc)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
inst = 0;
Data_I = 0;
ACK = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
#50 inst = 32'h00008020;
#50 inst = 32'h3c101000;
#50 inst = 32'h20111234;
#50 inst = 32'hae110000;
ACK = 1;
#50 inst = 32'h08100004;
ACK = 0;
end
always begin
#25 clk = ~clk;
end
endmodule
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#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; vector<int> get_sb(int num) { vector<int> res; while (num) { res.push_back(num % 10); num /= 10; } return res; } string get_a(vector<int> kol, string sub) { string reserve = 9 ; ++reserve[0]; if (sub[0] == 0 ) return reserve; string ss = ; for (int i = 0; i < kol.size(); ++i) { for (int j = 0; j < kol[i]; ++j) ss += (char)(i + 0 ); } return sub + ss; } string get_b(vector<int> kol, string sub) { string res = ; string reserve = 9 ; ++reserve[0]; int mc = -1; for (int i = 1; i < kol.size(); ++i) { if (0 != kol[i]) { mc = i; break; } } if (-1 == mc) return reserve; int cci = sub[0] - 0 ; res += (char)(mc + 0 ); --kol[mc]; for (int i = 0; i < cci; ++i) { for (int j = 0; j < kol[i]; ++j) res += (char)(i + 0 ); } res += sub; for (int i = cci; i < kol.size(); ++i) { for (int j = 0; j < kol[i]; ++j) res += (char)(i + 0 ); } return res; } string get_c(vector<int> kol, string sub) { string res = ; string reserve = 9 ; ++reserve[0]; int mc = -1; for (int i = 1; i < kol.size(); ++i) { if (0 != kol[i]) { mc = i; break; } } if (-1 == mc) return reserve; int cci = sub[0] - 0 ; res += (char)(mc + 0 ); --kol[mc]; for (int i = 0; i <= cci; ++i) { for (int j = 0; j < kol[i]; ++j) res += (char)(i + 0 ); } res += sub; for (int i = cci + 1; i < kol.size(); ++i) { for (int j = 0; j < kol[i]; ++j) res += (char)(i + 0 ); } return res; } int main() { string num, sub; getline(cin, num); getline(cin, sub); if (num == 01 || num == 10 ) { printf( 0 ); return 0; } int len_all = (int)num.size(); bool flag = true; for (int i = 1; i < sub.size(); ++i) { if (sub[i - 1] < sub[i]) { flag = false; break; } } vector<int> kol(10); for (int i = 0; i < num.size(); ++i) ++kol[num[i] - 0 ]; for (int i = 0; i < sub.size(); ++i) --kol[sub[i] - 0 ]; for (int aa = 1; aa <= 1000000; ++aa) { bool flag = true; vector<int> vv = get_sb(aa); vector<int> kol1 = kol; for (int i = 0; i < vv.size(); ++i) { --kol1[vv[i]]; if (kol1[vv[i]] < 0) { flag = false; break; } } if (!flag) continue; int vsz = (int)vv.size(); if (len_all - vsz != aa) continue; string a = get_a(kol1, sub); string b = get_b(kol1, sub); string c = get_c(kol1, sub); string ans = min(a, b); ans = min(ans, c); cout << ans; break; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { int n; long long a = 0, b; cin >> n; b = pow(2, n); for (int i = 1; i < n / 2; i++) b += pow(2, i); for (int i = n / 2; i < n; i++) a += pow(2, i); cout << abs(b - a) << endl; } }
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#include <bits/stdc++.h> using namespace std; const int N = 200007, inf = 0x3f3f3f3f; vector<int> edges[N]; int d[N]; void bfs(int s) { queue<int> q; q.push(s); memset(d, -1, sizeof d); d[s] = 0; while (q.size()) { int u = q.front(); q.pop(); for (int v : edges[u]) { if (d[v] == -1) { q.push(v); d[v] = d[u] + 1; } } } } void no() { cout << No << endl; exit(0); } int main() { ios::sync_with_stdio(false); srand(time(NULL)); int n; cin >> n; if (n == 1) { cout << Yes << endl; return 0; } for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; edges[u].push_back(v); edges[v].push_back(u); } vector<int> vec; int a; for (int i = 0; i < n; ++i) { cin >> a; vec.push_back(a); } memset(d, -1, sizeof d); int t = 0; d[1] = 0; if (vec[0] != 1) no(); for (int i = 0; i < n; ++i) { if (d[vec[i]] == -1) no(); ++t; for (int v : edges[vec[i]]) { if (d[v] == -1) d[v] = t; } } for (int i = 1; i < n; ++i) { if (d[vec[i]] < d[vec[i - 1]]) no(); } cout << Yes << endl; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n; scanf( %lld , &n); long long int a[n]; long long int i, j, k; long long int ans = 0; k = 0; for (i = 0; i < n; i++) { scanf( %lld , &j); if (j == 1) { a[k++] = i; } } if (k == 0) { ans = 0; } else if (k == 1) { ans = 1; } else { ans = 1; for (i = 1; i < k; i++) { if ((a[i] - a[i - 1]) == 1) { ans++; } else { ans += 2; } } } printf( %lld n , ans); return 0; }
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//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Mon Mar 7 12:11:16 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
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#include <bits/stdc++.h> using namespace std; vector<int> dif; map<int, int> g; int a[120000]; int main() { int n, flag; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); for (int i = 2; i <= n; i++) { if (g[a[i] - a[i - 1]] == 0) dif.push_back(a[i] - a[i - 1]); g[a[i] - a[i - 1]]++; } int sz = dif.size(); if (sz > 2 || n == 1) { if (sz > 2) cout << 0 << endl; else cout << -1 << endl; return 0; } if (sz == 1) { int D = dif[0]; if (dif[0] == 0) { cout << 1 << endl; cout << a[1] << endl; return 0; } if (n == 2) { if ((a[2] - a[1]) % 2 == 0) { cout << 3 << endl; cout << a[1] - D << << (a[2] + a[1]) / 2 << << a[2] + D << endl; return 0; } } cout << 2 << endl; cout << a[1] - D << << a[n] + D << endl; return 0; } int D1 = min(dif[0], dif[1]), D2 = max(dif[0], dif[1]); if (D1 * 2 != D2 || g[D2] > 1) { cout << 0 << endl; return 0; } cout << 1 << endl; for (int i = 2; i <= n; i++) { if (a[i] - a[i - 1] == D2) { cout << a[i] - D1 << endl; return 0; } } return 0; }
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i (K.17)
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY4.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 04/11/05 - Initial version.
// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752)
// 05/31/05 - Change pin order, remove connection check for CYINIT and CI.
// 12/21/05 - Add timing path.
// 04/13/06 - Add full timing path for DI to O (CR228786)
// 06/04/07 - Add wire definition.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module CARRY4 (CO, O, CI, CYINIT, DI, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
wire [3:0] di_in, s_in, o_out, co_out;
wire ci_or_cyinit;
wire ci_in, cyinit_in;
pulldown P1 (CI);
pulldown P2 (CYINIT);
assign ci_in = CI;
assign cyinit_in = CYINIT;
assign di_in = DI;
assign s_in = S;
assign O = o_out;
assign CO = co_out;
assign o_out = s_in ^ {co_out[2:0], ci_or_cyinit};
assign co_out[0] = s_in[0] ? ci_or_cyinit : di_in[0];
assign co_out[1] = s_in[1] ? co_out[0] : di_in[1];
assign co_out[2] = s_in[2] ? co_out[1] : di_in[2];
assign co_out[3] = s_in[3] ? co_out[2] : di_in[3];
assign ci_or_cyinit = ci_in | cyinit_in;
`ifdef XIL_TIMING
specify
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CYINIT => CO[0]) = (0:0:0, 0:0:0);
(CYINIT => CO[1]) = (0:0:0, 0:0:0);
(CYINIT => CO[2]) = (0:0:0, 0:0:0);
(CYINIT => CO[3]) = (0:0:0, 0:0:0);
(CYINIT => O[0]) = (0:0:0, 0:0:0);
(CYINIT => O[1]) = (0:0:0, 0:0:0);
(CYINIT => O[2]) = (0:0:0, 0:0:0);
(CYINIT => O[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[0]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => O[0]) = (0:0:0, 0:0:0);
(DI[1] => O[1]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[0]) = (0:0:0, 0:0:0);
(DI[2] => CO[1]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => O[0]) = (0:0:0, 0:0:0);
(DI[2] => O[1]) = (0:0:0, 0:0:0);
(DI[2] => O[2]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[0]) = (0:0:0, 0:0:0);
(DI[3] => CO[1]) = (0:0:0, 0:0:0);
(DI[3] => CO[2]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => O[0]) = (0:0:0, 0:0:0);
(DI[3] => O[1]) = (0:0:0, 0:0:0);
(DI[3] => O[2]) = (0:0:0, 0:0:0);
(DI[3] => O[3]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[1] => CO[0]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => O[0]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[2] => CO[0]) = (0:0:0, 0:0:0);
(S[2] => CO[1]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => O[0]) = (0:0:0, 0:0:0);
(S[2] => O[1]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[3] => CO[0]) = (0:0:0, 0:0:0);
(S[3] => CO[1]) = (0:0:0, 0:0:0);
(S[3] => CO[2]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => O[0]) = (0:0:0, 0:0:0);
(S[3] => O[1]) = (0:0:0, 0:0:0);
(S[3] => O[2]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int _; for (cin >> _; _--;) { int n, q; cin >> n >> q; string a; cin >> a; vector<int> p(n); p[0] = (a[0] == + ? 1 : -1); for (int i = 1; i < n; i++) { if (i % 2) p[i] = p[i - 1] - (a[i] == + ? 1 : -1); else p[i] = p[i - 1] + (a[i] == + ? 1 : -1); } vector<int> s(n); s[n - 1] = (a[n - 1] == + ? 1 : -1); for (int i = n - 2; i >= 0; i--) { if ((n - 1 - i) % 2) s[i] = s[i + 1] - (a[i] == + ? 1 : -1); else s[i] = s[i + 1] + (a[i] == + ? 1 : -1); } while (q--) { int l, r; cin >> l >> r; l--, r--; if (l == 0) { if (p[r] == 0) { cout << 0 n ; continue; } } else { if (p[r] == p[l - 1]) { cout << 0 n ; continue; } } int s1 = 0, s2 = 0; if (l == 0) s1 = p[r]; else { if (l % 2 == 0) { s1 = p[r] - p[l - 1]; } else { s1 = p[l - 1] - p[r]; } } if (r == n - 1) s2 = s[l]; else { if ((n - 1 - r) % 2 == 0) { s2 = s[l] - s[r + 1]; } else { s2 = s[r + 1] - s[l]; } } if (s1 == s2) { cout << 1 n ; } else { cout << 2 n ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, d, ans; struct node; struct edge { node *ed; edge *next; } E[N << 1], *newE = E; struct node { edge *son; node *pa; bool flag; int dist[2], dis; void dfs() { dist[0] = dist[1] = dis = -1e8; if (flag) dist[0] = 0; for (edge *e = son; e; e = e->next) if (e->ed != pa) { e->ed->pa = this; e->ed->dfs(); if (e->ed->dist[0] + 1 > dist[0]) { dist[1] = dist[0]; dist[0] = e->ed->dist[0] + 1; } else if (e->ed->dist[0] + 1 > dist[1]) { dist[1] = e->ed->dist[0] + 1; } } } void dfs2() { if (flag) if (dis < 0) dis = 0; if (max(dis, dist[0]) <= d) ans++; for (edge *e = son; e; e = e->next) if (e->ed != pa) { e->ed->dis = max(dis, e->ed->dist[0] == dist[0] - 1 ? dist[1] : dist[0]) + 1; e->ed->dfs2(); } } } V[N]; int main() { scanf( %d%d%d , &n, &m, &d); for (int i = 0; i < m; i++) { int p; scanf( %d , &p); V[p].flag = 1; } for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); *newE = (edge){V + y, V[x].son}, V[x].son = newE++; *newE = (edge){V + x, V[y].son}, V[y].son = newE++; } V[1].dfs(); V[1].dfs2(); printf( %d n , ans); }
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#include <bits/stdc++.h> using namespace std; int a[100007], b[100007]; vector<int> v, ans; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m, x; cin >> n >> m; for (int i = 0; i < n; i++) cin >> x, a[x]++; for (int i = 0; i < n; i++) cin >> x, b[m - x - 1]++; for (int x = 0; x < 2 * m; x++) { int i = x % m; while (a[i]) v.push_back(i), a[i]--; while (b[i] && v.size()) ans.push_back((v.back() + m - i - 1) % m), v.pop_back(), b[i]--; } sort(ans.begin(), ans.end()); for (long i = ans.size() - 1; i >= 0; i--) cout << ans[i] << ; }
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// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axis_data_fifo:1.1
// IP Revision: 8
(* X_CORE_INFO = "axis_data_fifo_v1_1_8_axis_data_fifo,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_axis_data_fifo_4_0,axis_data_fifo_v1_1_8_axis_data_fifo,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_axis_data_fifo_4_0,axis_data_fifo_v1_1_8_axis_data_fifo,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axis_data_fifo,x_ipVersion=1.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_SIGNAL_SET=0b00000000000000000000000000011011,C_FIFO_DEPTH=256,C_FIFO_MODE=1,C_IS_ACLK_ASYNC=0,C_SYNCHRONIZER_STAGE=2,C_ACLKEN_CONV_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_axis_data_fifo_4_0 (
s_axis_aresetn,
s_axis_aclk,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tkeep,
s_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tlast,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count
);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_RSTIF RST" *)
input wire s_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_CLKIF CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input wire [3 : 0] s_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TKEEP" *)
output wire [3 : 0] m_axis_tkeep;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
output wire [31 : 0] axis_data_count;
output wire [31 : 0] axis_wr_data_count;
output wire [31 : 0] axis_rd_data_count;
axis_data_fifo_v1_1_8_axis_data_fifo #(
.C_FAMILY("zynq"),
.C_AXIS_TDATA_WIDTH(32),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(1),
.C_AXIS_SIGNAL_SET('B00000000000000000000000000011011),
.C_FIFO_DEPTH(256),
.C_FIFO_MODE(1),
.C_IS_ACLK_ASYNC(0),
.C_SYNCHRONIZER_STAGE(2),
.C_ACLKEN_CONV_MODE(0)
) inst (
.s_axis_aresetn(s_axis_aresetn),
.m_axis_aresetn(1'H0),
.s_axis_aclk(s_axis_aclk),
.s_axis_aclken(1'H1),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(4'HF),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(1'H0),
.s_axis_tdest(1'H0),
.s_axis_tuser(1'H0),
.m_axis_aclk(1'H0),
.m_axis_aclken(1'H1),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axis_data_count(axis_data_count),
.axis_wr_data_count(axis_wr_data_count),
.axis_rd_data_count(axis_rd_data_count)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> gph[500005]; int n, par[500005], dep[500005], msk[500005]; int dp[500005], sz[500005]; int mx[1 << 22]; int l[23] = {}; void dfs2(int x, vector<pair<int, int> > &v) { v.push_back(pair<int, int>(dep[x], msk[x])); for (auto &i : gph[x]) dfs2(i, v); } void dfs(int x) { if (gph[x].empty()) { mx[msk[x]] = dep[x]; return; } for (int i = 1; i < gph[x].size(); i++) { dfs(gph[x][i]); vector<pair<int, int> > w; dfs2(gph[x][i], w); for (auto &j : w) mx[j.second] = -1; } dfs(gph[x][0]); for (int i = 1; i < gph[x].size(); i++) { vector<pair<int, int> > w; dfs2(gph[x][i], w); for (auto &j : w) { for (int k = 0; k < 23; k++) { int val = mx[j.second ^ l[k]]; if (~val) dp[x] = max(dp[x], j.first + val - 2 * dep[x]); } } for (auto &j : w) mx[j.second] = max(mx[j.second], j.first); } for (int k = 0; k < 23; k++) { if (mx[msk[x] ^ l[k]] != -1) { dp[x] = max(dp[x], mx[msk[x] ^ l[k]] - dep[x]); } } mx[msk[x]] = max(mx[msk[x]], dep[x]); } int main() { scanf( %d , &n); char ch[6]; for (int i = 0; i < 22; i++) l[i] = (1 << i); for (int i = 2; i <= n; i++) { scanf( %d %s , &par[i], ch); gph[par[i]].push_back(i); dep[i] = dep[par[i]] + 1; msk[i] = msk[par[i]] ^ (1 << (*ch - a )); } for (int i = n; i; i--) { sz[i] = 1; for (auto &j : gph[i]) sz[i] += sz[j]; sort(gph[i].begin(), gph[i].end(), [&](const int &a, const int &b) { return sz[a] > sz[b]; }); } memset(mx, -1, sizeof(mx)); dfs(1); for (int i = n; i; i--) { for (auto &j : gph[i]) dp[i] = max(dp[i], dp[j]); } for (int i = 1; i <= n; i++) printf( %d , dp[i]); }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [1:0] clkvec = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] count; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.count (count[1:0]),
// Inputs
.clkvec (clkvec[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, count};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'hfe8bac0bb1a0e53b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef T_TEST1
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
initial count[igen] = 1'b0;
always @ (posedge clkvec[igen])
count[igen] <= count[igen] + 1;
end
endgenerate
always @ (count) begin
$write("hi\n");
end
endmodule
`endif
`ifdef T_TEST2
module Test
(
input wire [1:0] clkvec,
// verilator lint_off MULTIDRIVEN
output reg [1:0] count
// verilator lint_on MULTIDRIVEN
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
// Unsupported: Count is multidriven, though if we did better analysis it wouldn't
// need to be.
initial count[igen] = 1'b0;
always @ (posedge clk_tmp)
count[igen] <= count[igen] + 1;
end
endgenerate
endmodule
`endif
`ifdef T_TEST3
module Test
(
input wire [1:0] clkvec,
output wire [1:0] count
);
genvar igen;
generate
for (igen=0; igen<2; igen=igen+1) begin : code_gen
wire clk_tmp = clkvec[igen];
reg tmp_count = 1'b0;
always @ (posedge clk_tmp) begin
tmp_count <= tmp_count + 1;
end
assign count[igen] = tmp_count;
end
endgenerate
endmodule
`endif
|
//
// Copyright (c) 2015 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "pdp1_defs.v"
module pdp1_alu(al_op, al_a, al_b, al_r, al_ovfl, al_w);
parameter pdp_model = "PDP-1D";
input [0:4] al_op;
input [0:17] al_a;
input [0:17] al_b;
output reg [0:17] al_r;
output reg al_ovfl;
output reg al_w;
wire [0:17] w_add_opa;
wire [0:17] w_add_opb;
assign w_add_opa = (al_op == `PDP1_OP_ISP |
al_op == `PDP1_OP_IDX) ? 18'h1 : al_a;
assign w_add_opb = (al_op == `PDP1_OP_SUB) ? ~al_b : al_b;
wire [0:17] w_add_immed1;
wire [0:17] w_add_result;
wire [0:17] w_add_normalized;
wire w_add_ovfl;
assign {w_add_ovfl, w_add_immed1} = w_add_opa + w_add_opb;
assign w_add_result = (w_add_ovfl) ? (w_add_immed1) + 1 : w_add_immed1;
assign w_add_normalized = (&w_add_result) ? 18'h0 : w_add_result;
always @(al_op or al_a or al_b or w_add_result or
w_add_normalized or w_add_ovfl) begin
al_w = 1'b1;
case(al_op)
`PDP1_OP_ADD,
`PDP1_OP_SUB:
begin
al_r <= w_add_normalized;
al_ovfl <= (~w_add_opa[0] ^ w_add_opb[0]) &
(w_add_opa[0] ^ w_add_result[0]);
end
`PDP1_OP_ISP,
`PDP1_OP_IDX:
begin
al_r <= w_add_normalized;
al_ovfl <= 0;
end
`PDP1_OP_AND:
al_r <= al_a & al_b;
`PDP1_OP_XOR:
al_r <= al_a ^ al_b;
`PDP1_OP_IOR:
al_r <= al_a | al_b;
default:
{al_ovfl, al_r, al_w} <= 0;
endcase // case (al_op)
end
endmodule // pdp1_alu
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<long long int> a(n); vector<long long int> mp(n + 1, 0); for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; } vector<long long int> ans(n + 1); priority_queue<pair<long long, long long>> pq; long long cost = 0; for (int i = 0; i < n + 1; i++) { ans[i] = mp[i] + cost; if (mp[i] == 0) { if (pq.empty()) { for (int j = i + 1; j < n + 1; j++) ans[j] = -1; break; } auto tp = pq.top(); pq.pop(); cost += (long long)(i - tp.first); tp.second--; if (tp.second > 1) pq.push({tp.first, tp.second}); } if (mp[i] > 1) pq.push({i, mp[i]}); } for (int i = 0; i < n + 1; i++) cout << ans[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long i, j, k, n, m, ans = 0, sum = 0, a[100005] = {0}, mn = 2e9, mx = 0, cnt = 1, index = 0, x, y, z, xptr, yptr, id1, id2, zptr; string s; set<int> all; set<int>::iterator it2; set<pair<int, int> > seg, tem; set<pair<int, int> >::iterator it1, it, it3, it4; cin >> s; n = s.size(); for (i = 0; i < n; i++) { all.insert(i); if (i + 1 == n || s[i] != s[i + 1]) { seg.insert(make_pair(index, cnt)); tem.insert(make_pair(index, index + cnt - 1)); cnt = 1; index = i + 1; } else { cnt++; } } while (seg.size() > 1) { ans++; vector<pair<int, int> > v; for (it = seg.begin(); it != seg.end(); it++) { x = it->first; y = it->second; it1 = it; it1++; if (it == seg.begin()) { if (y > 1) { v.push_back(make_pair(x, y - 1)); } it3 = tem.lower_bound(make_pair(x, -1)); it2 = all.upper_bound(it3->second); it2--; all.erase(it2); if (y == 1) { tem.erase(it3); } } else if (it1 == seg.end()) { if (y > 1) { v.push_back(make_pair(x, y - 1)); } it2 = all.lower_bound(x); all.erase(it2); if (y == 1) { it3 = tem.lower_bound(make_pair(x, -1)); tem.erase(it3); } } else { it2 = all.lower_bound(x); all.erase(it2); if (y > 1) { it3 = tem.lower_bound(make_pair(x, -1)); it2 = all.upper_bound(it3->second); it2--; all.erase(it2); if (y > 2) { v.push_back(make_pair(x, y - 2)); } } if (y == 1 || y == 2) { it3 = tem.lower_bound(make_pair(x, -1)); tem.erase(it3); } } } seg.clear(); if (v.size() != 0) { xptr = v[0].first; yptr = v[0].second; it3 = tem.lower_bound(make_pair(xptr, -1)); zptr = it3->second; tem.erase(it3); } for (i = 0; i < v.size(); i++) { z = xptr; it2 = all.lower_bound(z); id1 = *it2; z = v[i].first; it2 = all.lower_bound(z); id2 = *it2; if (s[id1] == s[id2]) { if (i != 0) { yptr = yptr + v[i].second; it3 = tem.lower_bound(make_pair(v[i].first, -1)); zptr = it3->second; tem.erase(it3); } } else { seg.insert(make_pair(xptr, yptr)); tem.insert(make_pair(xptr, zptr)); xptr = v[i].first; yptr = v[i].second; it3 = tem.lower_bound(make_pair(v[i].first, -1)); zptr = it3->second; tem.erase(it3); } if (i + 1 == v.size()) { seg.insert(make_pair(xptr, yptr)); tem.insert(make_pair(xptr, zptr)); } } } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAX_H = 100; const int MAX_W = 100; int hs[MAX_H], vs[MAX_W]; int ps[MAX_H][MAX_W], as[MAX_H * MAX_W]; int main() { int h, w, q; scanf( %d%d%d , &h, &w, &q); for (int y = 0, p = 0; y < h; y++) for (int x = 0; x < w; x++, p++) ps[y][x] = p; while (q--) { int op; scanf( %d , &op); if (op == 1) { int y; scanf( %d , &y); y--; int tp = ps[y][0]; for (int x = 1; x < w; x++) ps[y][x - 1] = ps[y][x]; ps[y][w - 1] = tp; } else if (op == 2) { int x; scanf( %d , &x); x--; int tp = ps[0][x]; for (int y = 1; y < h; y++) ps[y - 1][x] = ps[y][x]; ps[h - 1][x] = tp; } else { int y, x, v; scanf( %d%d%d , &y, &x, &v); y--, x--; as[ps[y][x]] = v; } } for (int y = 0, p = 0; y < h; y++) for (int x = 0; x < w; x++, p++) { printf( %d , as[p]); putchar(x + 1 < w ? : n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int N, M; int tam[200005], ans[200005]; map<pair<int, int>, bool> ex; int main() { cin.tie(0); ios_base::sync_with_stdio(0); cin >> N >> M; for (int m = 0; m < M; m++) { int u, v; cin >> u >> v; tam[u]++; tam[v]++; ex[{u, v}] = 1; ex[{v, u}] = 1; } for (int i = 1; i <= N; i++) if (tam[i] < N - 1) { cout << YES n ; for (int j = 1; j <= N; j++) if (i != j && !ex[{i, j}]) { ans[i] = 1; ans[j] = 2; int id = 3; for (int k = 1; k <= N; k++) if (!ans[k]) ans[k] = id++; for (int i = 1; i <= N; i++) cout << ans[i] << n [i == N]; for (int i = 1; i <= N; i++) cout << (ans[i] == 2 ? 1 : ans[i]) << n [i == N]; exit(0); } } cout << NO n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; long long int a[n * k], c = 0; for (long long int i = 0; i < n * k; i++) { cin >> a[i]; } long long int m = (ceil)((double)n / 2); for (long long int i = (m - 1) * k; i < n * k; i += n - m + 1) { c += a[i]; } cout << c << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; const long long mo = 1e9 + 7; const long long inf = 1e9; const long long Inf = 1e18; int a[N], b[N]; int main() { int n, m, tot = 0; scanf( %d%d , &n, &m); int nw = 0; for (int i = (1); i <= (m); ++i) { scanf( %d , &a[i]); int x = a[i]; if (x <= nw) { b[i] = b[i - 1] + x; nw -= x; } else { x -= nw; tot += x / n; x = x % n; b[i] = x; if (x) nw = n - x, ++tot; else nw = 0; } } sort(b + 1, b + m); b[m] = n; for (int i = (m); i >= (1); --i) b[i] = b[i] - b[i - 1]; printf( %d n , tot); for (int i = (1); i <= (m); ++i) printf( %d , b[i]); printf( n ); int x = 1; for (int i = (1); i <= (m); ++i) { while (a[i] > 0) { a[i] -= b[x]; printf( %d , i); if (x == m) x = 1, printf( n ); else ++x; } } for (; x != 1 && x != m + 1; ++x) printf( %d , m); }
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#include <bits/stdc++.h> using namespace std; long long n, k; long double ans, eps = 1e-10, l, v1, v2; bool solve(long double mid) { int x = (n + k - 1) / k; long double tl = mid, pos = l; while (x--) { if (tl < 0) return 0; long double trav = (v2 * v1 * tl - v2 * pos) / (v1 - v2); if (trav > pos) return 0; long double oldTime = tl; tl -= trav / v2 + (trav - v1 * trav / v2) / (v1 + v2); pos -= v1 * (oldTime - tl); } return 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> l >> v1 >> v2 >> k; double long hi = 1e10, lo = 0; while (hi - lo >= eps) { long double mid = (hi + lo) / 2; if (solve(mid)) { ans = mid; hi = mid - eps; } else lo = mid + eps; } cout << setprecision(12) << ans; solve(ans); return 0; }
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#include <bits/stdc++.h> using namespace std; long long mInv[41]; long long fact[41]; long long factInv[41]; map<long, long> mymap; long long heights[5]; long long segTree[3]; long nums[5005]; long g[5005]; vector<long> primes; vector<long> badPrimes; long funcVal[1000006]; long long N; set<string> dictionary; set<string>::iterator it; pair<set<string>::iterator, bool> ret; long long gcd(long long a, long long b) { if (b == 0) return a; if (a % b == 0) return b; return gcd(b, a % b); } long long getmoduloInv(long long n) { if (n == 1) return 1; if (mInv[n] > 0) return mInv[n]; long long m = (-1 * 1000000007) / n; m += 1000000007; m *= getmoduloInv(1000000007 % n); mInv[n] = (m % 1000000007); return mInv[n]; } vector<long> get_primes(unsigned long maxN) { char *sieve; sieve = new char[maxN / 8 + 1]; long m = (maxN / 8) + 1; for (long long i = 0; i < m; i++) sieve[i] = 255; for (unsigned long x = 2; x <= maxN; x++) if (sieve[x / 8] & (0x01 << (x % 8))) { primes.push_back(x); for (unsigned long j = 2 * x; j <= maxN; j += x) sieve[j / 8] &= ~(0x01 << (j % 8)); } delete[] sieve; return primes; } long long getPow(long long b, long long p) { if (b < 2 || p == 1) return b; if (p == 0) return 1; long long val = getPow(b, p / 2); val *= val; val %= 1000000007; if (p % 2 == 1) { val *= b; val %= 1000000007; } return val; } void buildSegTree(long node, long b, long e) { if (b == e) segTree[node] = b; else { long mid = (b + e) / 2; buildSegTree(node * 2, b, mid); buildSegTree(1 + node * 2, mid + 1, e); if (heights[segTree[node * 2]] <= heights[segTree[1 + node * 2]]) segTree[node] = segTree[node * 2]; else segTree[node] = segTree[1 + node * 2]; } } long long getMin(long node, long segBeg, long segEnd, long qBeg, long qEnd) { if (segEnd < qBeg || segBeg > qEnd) return N + 1; if (segBeg >= qBeg && segEnd <= qEnd) return segTree[node]; long mid = (segBeg + segEnd) / 2; long fh = getMin(node * 2, segBeg, mid, qBeg, qEnd); long sh = getMin(1 + node * 2, mid + 1, segEnd, qBeg, qEnd); if (heights[sh] < heights[fh]) return sh; return fh; } string genMinString(long long val) { long len = val / 9, firstDigit = val % 9; string s = ; if (firstDigit > 0) { char ch = 0 + firstDigit; s = ch + s; } for (long i = 0; i < len; i++) s = s + 9 ; return s; } long maxBuild; vector<long> mult(vector<long> A, vector<long> B) { long len1 = A.size(), len2 = B.size(); vector<long> C; for (long i = 0; i < len1; i++) { long carry = 0; for (long j = 0; j < len2; j++) { long pos = i + j; long val = carry + (A[i] * B[j]); carry = val / 10; val = val % 10; if (pos >= C.size()) { C.push_back(val); } else { C[pos] += val; carry = C[pos] / 10; C[pos] = C[pos] % 10; } } if (carry > 0) C.push_back(carry); } return C; } vector<long> getVal(long power) { vector<long> C; C.push_back(5); if (power == 1) return C; vector<long> B = getVal(power / 2); B = mult(B, B); if (power % 2 == 1) B = mult(B, C); return B; } long getZeros(long fives) { long ans = 0; while (fives > 0) { ans += fives; fives /= 5; } return ans; } long long getPow(long zeros) { long val = ((zeros * 4) / 5) - 1; while (getZeros(val) < zeros) val++; if (getZeros(val) == zeros) return val; return -1; } long long rowVal[5050], colVal[5050]; long long rowAlter[5050], colAlter[5050]; int main(void) { long long test_cases = 1, l, r, seed = 1, maxVal; vector<string> originalStrings; long long curNum; long long m, n, k; long long ans = 0; for (long T = 0; T < test_cases; T++) { cin >> n >> m >> k; long rv, cv, av; memset(rowVal, 0, sizeof(rowVal)); memset(colVal, 0, sizeof(colVal)); memset(rowAlter, -1, sizeof(rowAlter)); memset(colAlter, -1, sizeof(colAlter)); for (long i = 0; i < k; i++) { scanf( %ld , &av); scanf( %ld , &rv); rv--; scanf( %ld , &cv); if (av == 1) { rowVal[rv] = cv; rowAlter[rv] = i; } else { colVal[rv] = cv; colAlter[rv] = i; } } for (long i = 0; i < n; i++) { for (long j = 0; j < m; j++) { if (rowAlter[i] > colAlter[j]) printf( %ld , rowVal[i]); else printf( %ld , colVal[j]); } cout << endl; } } return 0; }
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// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
//
// Transfer takes 2 dCLK to see data,
// sRDY recovers takes 2 dCLK + 2 sCLK
module SyncHandshake(
sCLK,
sRST_N,
dCLK,
sEN,
sRDY,
dPulse
);
parameter init = 1'b0;
// Source clock port signal
input sCLK ;
input sRST_N ;
input sEN ;
output sRDY ;
// Destination clock port signal
input dCLK ;
output dPulse ;
// Flops to hold data
reg dToggleReg ;
reg dSyncReg1, dSyncReg2 ;
reg dLastState ;
reg sToggleReg ;
reg sSyncReg1, sSyncReg2 ;
reg sLastState ;
reg sRDY_reg ;
wire pulseSignal ;
// Output signal
assign dPulse = pulseSignal ;
assign pulseSignal = dSyncReg2 != dLastState ;
assign sRDY = sRDY_reg ;
always @(posedge sCLK or negedge sRST_N)
begin
if (sRST_N == 0)
begin
sRDY_reg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY init ;
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY init ;
sLastState <= `BSV_ASSIGNMENT_DELAY init ;
sToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
// hadshake return synchronizer
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dToggleReg ;// clock domain crossing
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
sLastState <= `BSV_ASSIGNMENT_DELAY sSyncReg2 ;
// Pulse send
if ( sEN )
begin
sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ;
end // if ( sEN )
// Ready signal generation
if ( sEN )
begin
sRDY_reg <= `BSV_ASSIGNMENT_DELAY 1'b0 ;
end
else if ( sSyncReg2 != sLastState )
begin
sRDY_reg <= `BSV_ASSIGNMENT_DELAY 1'b1 ;
end
end
end // always @ (posedge sCLK or negedge sRST_N)
always @(posedge dCLK or negedge sRST_N)
begin
if (sRST_N == 0)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init;
dLastState <= `BSV_ASSIGNMENT_DELAY init ;
dToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
if ( pulseSignal )
begin
dToggleReg <= `BSV_ASSIGNMENT_DELAY ! dToggleReg ;
end
end
end // always @ (posedge dCLK or negedge sRST_N)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
dSyncReg1 = init ;
dSyncReg2 = init ;
dLastState = init ;
dToggleReg = init ;
sToggleReg = init ;
sSyncReg1 = init ;
sSyncReg2 = init ;
sLastState = init ;
sRDY_reg = 1'b1 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // HandshakeSync
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#include <bits/stdc++.h> using namespace std; inline long long max(long long a, long long b) { return a > b ? a : b; } class Box { public: string name; int type, border, spacing; vector<Box *> con; bool hcalc, wcalc; long long w, h; Box() { hcalc = wcalc = 0; } Box(string ni, int t) : name(ni), type(t) { con.clear(); hcalc = wcalc = 0; border = spacing = 0; } Box(string ni, int t, long long wi, long long hi) : name(ni), type(t), w(wi), h(hi) { con.clear(); hcalc = wcalc = 0; border = spacing = 0; } long long getw() { int i; if (!wcalc) { wcalc = 1; if (type == 0) { } else if (type == 1) { if (con.size() == 0) w = 0; else { w = border * 2 + spacing * (con.size() - 1); for (i = 0; i < con.size(); i++) w += con[i]->getw(); } } else if (type == 2) { if (con.size() == 0) w = 0; else { w = 0; for (i = 0; i < con.size(); i++) w = max(w, con[i]->getw()); w += border * 2; } } } return w; } long long geth() { int i; if (!hcalc) { hcalc = 1; if (type == 0) { } else if (type == 2) { if (con.size() == 0) h = 0; else { h = border * 2 + spacing * (con.size() - 1); for (i = 0; i < con.size(); i++) h += con[i]->geth(); } } else if (type == 1) { if (con.size() == 0) h = 0; else { h = 0; for (i = 0; i < con.size(); i++) h = max(h, con[i]->geth()); h += border * 2; } } } return h; } const bool operator<(const Box &b) const { return name < b.name; } }; map<string, int> mp; int bn; Box box[205]; int main(void) { int qn, qi, i, j, w, h, v, u; char cc[200], zz[200]; string cmd, a, b, c; scanf( %d , &qn); gets(cc); bn = 0; mp.clear(); for (qi = 0; qi < qn; qi++) { gets(cc); cmd = cc; if (cmd.substr(0, 4) == VBox ) { a = cmd.substr(5); mp[a] = bn; box[bn++] = Box(a, 2); } else if (cmd.substr(0, 4) == HBox ) { a = cmd.substr(5); mp[a] = bn; box[bn++] = Box(a, 1); } else if (cmd.substr(0, 6) == Widget ) { i = 7; for (j = i + 1; cmd[j] != ( ; j++) ; a = cmd.substr(i, j - i); mp[a] = bn; sscanf(cmd.substr(j).c_str(), (%d,%d) , &w, &h); box[bn++] = Box(a, 0, w, h); } else { for (i = 0; cmd[i] != . ; i++) ; a = cmd.substr(0, i); v = mp[a]; i++; for (j = i; cmd[j] != ( ; j++) ; b = cmd.substr(i, j - i); j++; c = cmd.substr(j, cmd.length() - j - 1); if (b == pack ) { u = mp[c]; box[v].con.push_back(box + u); } else if (b == set_border ) { sscanf(c.c_str(), %d , &w); box[v].border = w; } else if (b == set_spacing ) { sscanf(c.c_str(), %d , &w); box[v].spacing = w; } } } for (i = 0; i < bn; i++) { box[i].getw(); box[i].geth(); } std::sort(box, box + bn); for (i = 0; i < bn; i++) { cout << box[i].name << << box[i].getw() << << box[i].geth() << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 4e4 + 10, M = 32, INF = 1e9 + 10; int a, b, n; int dp[N][M]; long long mypw(long long a, int b) { double ans = pow(a, b); if (ans > INF) { return INF; } long long ret = 1; while (b--) ret = ret * a; return ret; } int check(int a, int b) { if (a < N && b < M && dp[a][b] != -1) return dp[a][b]; if (a == 1 && mypw(a + 1, b) >= n) { return 2; } if (b == 1 && mypw(a, b + 1) >= n) { return !((n - a) & 1); } if (mypw(a, b) >= n) return dp[a][b] = 1; int a1 = check(a + 1, b); int a2 = check(a, b + 1); if (a1 == 0 || a2 == 0) return dp[a][b] = 1; if (a1 == 2 || a2 == 2) return dp[a][b] = 2; return dp[a][b] = 0; } int main() { scanf( %d%d%d , &a, &b, &n); memset(dp, -1, sizeof(dp)); int t = check(a, b); if (t == 1) puts( Masha ); else if (t == 0) puts( Stas ); else puts( Missing ); return 0; }
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#include <bits/stdc++.h> using namespace std; long long x, a[] = {3, 15, 81, 6723, 50625, 2562991875LL}; int sg[] = {0, 1, 2, 0, 3, 1, 2}, n, ans = 0; int main() { cin >> n; while (n--) { cin >> x; ans ^= sg[lower_bound(a, a + 6, x) - a]; } cout << (ans ? Furlo : Rublo ) << endl; return 0; }
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/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* test "f permutation".
* write a block, wait 3 cycles, write another block, do not wait, write the third block */
`timescale 1ns / 1ps
`define P 20
module test_f_permutation;
// Inputs
reg clk;
reg reset;
reg [575:0] in;
reg in_ready;
// Outputs
wire ack;
wire [1599:0] out;
wire out_ready;
integer i;
// Instantiate the Unit Under Test (UUT)
f_permutation uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.ack(ack),
.out(out),
.out_ready(out_ready)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
in = 0;
in_ready = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
if (out !== 0) error; /* should be 0 */
if (ack !== 0) error; /* should be 0 */
if (out_ready !== 0) error; /* should be 0 */
#(`P);
reset = 0;
in = 0;
in_ready = 1;
#(`P);
if (out_ready !== 0) error; /* should be 0 */
in_ready = 0;
/* check 1~10-th cycles */
for(i=0; i<10; i=i+1)
begin
if (out === 0) error; /* should not be 0 */
if (ack !== 0) error; /* should be 0 */
if (out_ready !== 0) error; /* should be 0 */
#(`P);
end
/* check the 11-th cycle */
if (out === 0) error; /* should not be 0 */
if (ack !== 0) error; /* should be 0 */
if (out_ready !== 0) error; /* should be 0 */
#(`P);
/* check the 12-th cycle */
#(`P); /* wait out */
if (out_ready !== 1) error; /* should be 1 */
if(out !== 1600'hf1258f7940e1dde784d5ccf933c0478ad598261ea65aa9eebd1547306f80494d8b284e056253d057ff97a42d7f8e6fd490fee5a0a44647c48c5bda0cd6192e76ad30a6f71b19059c30935ab7d08ffc64eb5aa93f2317d635a9a6e6260d71210381a57c16dbcf555f43b831cd0347c82601f22f1a11a5569f05e5635a21d9ae6164befef28cc970f2613670957bc46611b87c5a554fd00ecb8c3ee88a1ccf32c8940c7922ae3a26141841f924a2c509e416f53526e70465c275f644e97f30a13beaf1ff7b5ceca249) error;
#(3*`P); /* wait more cycles */
if (out_ready !== 1) error; /* should be 1 */
/* "out" should not change */
if(out !== 1600'hf1258f7940e1dde784d5ccf933c0478ad598261ea65aa9eebd1547306f80494d8b284e056253d057ff97a42d7f8e6fd490fee5a0a44647c48c5bda0cd6192e76ad30a6f71b19059c30935ab7d08ffc64eb5aa93f2317d635a9a6e6260d71210381a57c16dbcf555f43b831cd0347c82601f22f1a11a5569f05e5635a21d9ae6164befef28cc970f2613670957bc46611b87c5a554fd00ecb8c3ee88a1ccf32c8940c7922ae3a26141841f924a2c509e416f53526e70465c275f644e97f30a13beaf1ff7b5ceca249) error;
in_ready = 1; /* feed in one more block */
in = 0;
#(`P);
if (out_ready !== 0) error; /* should be 0 */
in_ready = 0;
while (out_ready !== 1)
#(`P);
if(out !== 1600'h2d5c954df96ecb3c6a332cd07057b56d093d8d1270d76b6c8a20d9b25569d0944f9c4f99e5e7f156f957b9a2da65fb3885773dae1275af0dfaf4f247c3d810f71f1b9ee6f79a8759e4fecc0fee98b42568ce61b6b9ce68a1deea66c4ba8f974f33c43d836eafb1f5e00654042719dbd97cf8a9f009831265fd5449a6bf17474397ddad33d8994b4048ead5fc5d0be774e3b8c8ee55b7b03c91a0226e649e42e9900e3129e7badd7b202a9ec5faa3cce85b3402464e1c3db6609f4e62a44c105920d06cd26a8fbf5c) error;
/* no wait, feed in one more block */
in_ready = 1;
#(`P);
if (out_ready !== 0) error; /* should be 0 */
in_ready = 0;
while (out_ready !== 1)
#(`P);
if(out !== 1600'h55eabb80767d364686c354c8d01cbace9452d254b0979b3dde59422be2c66f16c660e4f2d4d8212e78414f691b639bb3cbb20f9f1b22e381cf16da5fac2da63f83c0b76552d95f7c44efc84eaf017e1548d380ff3e532c9592436ec5c5e02f05bde57ca1ee8de7e9240970468a1fd1b012a978439cbb7686d26b59fcceff8b4dd2aa0f472110fff87bd44abf53f72551e15ad2b722d00bb7c56095932c792c459e02d1766ad3a79c312f2da72ada4ec368b9f274a8d7d6b92b7239f7e51eea1eb6947f6894d77aeb) error;
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("Error!");
$finish;
end
endtask
endmodule
`undef P
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: RIT
// Engineer: Cody Cziesler and Nick Desaulniers
//
// Create Date: 3:03 04/17/2011
// Design Name: reg_block
// Module Name: reg_block
// Project Name: Omicron
// Target Devices: Xilinx Spartan-3E
// Tool versions:
// Description: The register block for the instruction decode
//
// Revision 0.01 - File Created, Tested, Works great (CRC)
// Revision 1.00 - Changed the number of registers, untested (CRC)
// Revision 2.00 - Changed size of raddr1, raddr2, waddr (CRC)
// Revision 3.00 - Added check for register $0 (CRC)
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module reg_block(
input [2:0] raddr1,
input [2:0] raddr2,
input [2:0] waddr,
input [15:0] wdata,
input clk_n,
input wea,
output [15:0] rdata1,
output [15:0] rdata2
);
// 16 bits wide, 2^3 bits deep register file
// {$0,$A,$B,$C,$D,$E,$F,$G}
reg [15:0] registers [7:0];
// Reads are combinational
assign rdata1 = registers[raddr1];
assign rdata2 = registers[raddr2];
// Writes only happen when wea is high and rising edge of clock
always@(posedge clk_n) begin
if(wea) begin
registers[3'b0] <= 16'b0;
if(waddr != 3'b0) begin
registers[waddr] <= wdata;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_TB_V
`define SKY130_FD_SC_HS__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B_N = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B_N = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B_N = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B_N = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hs__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_TB_V
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: test.v,v 1.5 2017/08/28 13:05:19 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/test.v,v $
//
//=============================================================
//=============================================================
// test
//
// Top level test module, instantiating the UUT, drivers
// memory and a monitor
//
//=============================================================
`include "test_defs.vh"
module test;
wire CLOCK_50;
wire jtag_clk;
wire nreset;
wire jtag_done;
// Display interface
wire [27:0] HEX;
wire [7:0] LEDG;
wire [9:0] LEDR;
// UART
wire UART_TXD;
wire UART_RXD;
// SRAM Interface
wire [15:0] SRAM_DQ;
wire [17:0] SRAM_ADDR;
wire SRAM_UB_N;
wire SRAM_LB_N;
wire SRAM_WE_N;
wire SRAM_CE_N;
wire SRAM_OE_N;
// SDRAM Interface
wire [15:0] DRAM_DQ;
wire [11:0] DRAM_ADDR;
wire DRAM_LDQM;
wire DRAM_UDQM;
wire DRAM_WE_N;
wire DRAM_CAS_N;
wire DRAM_RAS_N;
wire DRAM_CS_N;
wire DRAM_BA_0;
wire DRAM_BA_1;
wire DRAM_CLK;
wire DRAM_CKE;
// USB-JTAG
wire TDI;
wire TCS;
wire TDO;
wire TCK;
// I2C
wire I2C_SDAT;
wire I2C_SCLK;
// PS2
wire PS2_CLK;
wire PS2_DAT;
// UART
wire UART_TXRDY;
wire [7:0] UART_TXDATA;
wire UART_TXACK;
wire UART_RXRDY;
wire [7:0] UART_RXDATA;
wire UART_RXERR;
wire [35:0] GPIO_0;
wire [35:0] GPIO_1;
//-------------------------------------------------------------
// Hierarchical code
alt_lm32 UUT (
// Clock Input
.CLOCK_50 (CLOCK_50),
// Push Button
.KEY ({3'b111, nreset}),
.SW (10'h000),
// 7-SEG Display
.HEX0 (HEX[6:0]),
.HEX1 (HEX[13:7]),
.HEX2 (HEX[20:14]),
.HEX3 (HEX[27:21]),
// LED
.LEDG (LEDG),
.LEDR (LEDR),
// UART
.UART_TXD (UART_TXD),
.UART_RXD (UART_RXD),
// SRAM Interface
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_WE_N (SRAM_WE_N),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_OE_N (SRAM_OE_N),
// SDRAM interface
.DRAM_DQ (DRAM_DQ),
.DRAM_ADDR (DRAM_ADDR),
.DRAM_LDQM (DRAM_LDQM),
.DRAM_UDQM (DRAM_UDQM),
.DRAM_WE_N (DRAM_WE_N),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_BA_0 (DRAM_BA_0),
.DRAM_BA_1 (DRAM_BA_1),
.DRAM_CLK (DRAM_CLK),
.DRAM_CKE (DRAM_CKE),
// USB JTAG link
.TDI (TDI),
.TCK (TCK),
.TCS (TCS),
.TDO (TDO),
// I2C interface
.I2C_SCLK (I2C_SCLK),
.I2C_SDAT (I2C_SDAT),
// PS2 interface
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// GPIO interface
.GPIO_0 (GPIO_0),
.GPIO_1 (GPIO_1)
);
// Define parameters for PLL1 test component in UUT. PLL1 simulation
// model has a compatible subset of parameters to the Altera component,
// and so could be substituted for Altera's model.
defparam UUT.p1.altpll_component.inclk0_input_frequency = `CLKPERIOD50, // inclk0 is 50MHz
UUT.p1.altpll_component.clk0_multiply_by = `CLKMUL0, // c0 is inclk0 * 4 / 5 = 40MHz
UUT.p1.altpll_component.clk0_divide_by = `CLKDIV0,
UUT.p1.altpll_component.clk1_multiply_by = `CLKMUL1, // c1 is inclk0 * 4 / 5 = 40MHz
UUT.p1.altpll_component.clk1_divide_by = `CLKDIV1,
UUT.p1.altpll_component.clk2_multiply_by = `CLKMUL2, // c2 is inclk0 * 8 / 5 = 80MHz
UUT.p1.altpll_component.clk2_divide_by = `CLKDIV2,
UUT.p1.altpll_component.clk2_phase_shift = `CLKPHASE2_180, // 180 deg phase shift
UUT.u2.u1.clk_freq_khz = `SYS_CLK_FREQ_KHZ,
UUT.u2.u1.i2c_freq_khz = `I2C_CLK_FREQ_KHZ,
UUT.u4.BAUD_RATE = `TEST_BAUDRATE;
sram sram (
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_WE_N (SRAM_WE_N),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_OE_N (SRAM_OE_N)
);
sdram_1Mx16x4 sdram (
.DRAM_DQ (DRAM_DQ),
.DRAM_ADDR (DRAM_ADDR),
.DRAM_LDQM (DRAM_LDQM),
.DRAM_UDQM (DRAM_UDQM),
.DRAM_WE_N (DRAM_WE_N),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_BA_0 (DRAM_BA_0),
.DRAM_BA_1 (DRAM_BA_1),
.DRAM_CLK (DRAM_CLK),
.DRAM_CKE (DRAM_CKE)
);
jtag_drv jtag (
.clk (jtag_clk),
.nreset (nreset),
.TDI (TDI),
.TCK (TCK),
.TCS (TCS),
.TDO (TDO),
.done (jtag_done)
);
uart_drv uart (
.clk (CLOCK_50),
.nreset (nreset),
.rx (UART_TXD),
.tx (UART_RXD),
.txrdy (UART_TXRDY),
.txdata (UART_TXDATA),
.txack (UART_TXACK),
.rxrdy (UART_RXRDY),
.rxdata (UART_RXDATA),
.rxerr (UART_RXERR)
);
i2c_drv i2c (
.I2C_SCLK (I2C_SCLK),
.I2C_SDAT (I2C_SDAT)
);
monitor mon (
.CLOCK_50 (CLOCK_50),
.jtag_clk (jtag_clk),
.nreset (nreset),
.jtag_done (jtag_done),
// PS2 interface
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// LEDs
.HEX (HEX),
.LEDG (LEDG),
.LEDR (LEDR),
// UART
.txrdy (UART_TXRDY),
.txdata (UART_TXDATA),
.txack (UART_TXACK),
.rxrdy (UART_RXRDY),
.rxdata (UART_RXDATA),
.rxerr (UART_RXERR)
);
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: playback_fifo.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module playback_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
wrempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output rdempty;
output rdfull;
output wrempty;
output wrfull;
output [4:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "64"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL "rdfull"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL playback_fifo_bb.v TRUE
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_1_stub.v
// Design : zynq_design_1_axi_bram_ctrl_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int temp; map<int, vector<int>> mpp; for (int i = 2; i <= n; i++) { cin >> temp; mpp[temp].push_back(i); } for (auto itr = mpp.begin(); itr != mpp.end(); ++itr) { vector<int> v = (*itr).second; int cnt = 0; if (v.size() >= 1) { for (int j = 0; j < v.size(); j++) { if (mpp[v[j]].size() == 0) { cnt++; } } if (cnt < 3) { cout << No << endl; return 0; } } } cout << Yes << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long n, a, b, c, res = LONG_LONG_MAX; int main() { cin >> n >> a >> b >> c; if (n % 4 == 0) return puts( 0 ); if (n % 4 == 1) { res = min(res, a * 3); res = min(res, a + b); res = min(res, c); } else if (n % 4 == 2) { res = min(res, a * 2); res = min(res, b); res = min(res, c * 2); } else { res = min(res, a); res = min(res, b + c); res = min(res, c * 3); } cout << res; }
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#include <bits/stdc++.h> int main() { int team1, team2; std::string s; std::cin >> s; team1 = s.find( 1111111 ); team2 = s.find( 0000000 ); if (team1 >= 0 || team2 >= 0) { std::cout << YES ; } else std::cout << NO ; }
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#include <bits/stdc++.h> int main() { int N; std::cin >> N; std::set<std::pair<int, int>> doubled; std::set<std::pair<int, int>> pend; int to_double = 0; int f_doubled = 0; int64_t total_damage = 0; int t; int d; for (int i = 0; i < N; i++) { std::cin >> t; std::cin >> d; total_damage += d; to_double += t * (d > 0 ? 1 : -1); if (d > 0) { pend.insert({d, t}); } else { auto search = doubled.find({-d, t}); if (search != doubled.end()) { doubled.erase(search); if (t == 0) f_doubled--; total_damage += d; } else { pend.erase(pend.find({-d, t})); } if (t == 1) { if (doubled.size() > 0) { auto it_doubled = doubled.begin(); std::pair<int, int> max = *it_doubled; doubled.erase(it_doubled); pend.insert(max); if (max.second == 0) f_doubled--; total_damage -= max.first; } } } if (to_double > doubled.size()) { if (pend.size() > 0) { auto it_pend = --pend.end(); std::pair<int, int> max = *it_pend; doubled.insert(max); pend.erase(it_pend); if (max.second == 0) f_doubled++; total_damage += max.first; } } else if (doubled.size() == to_double) { if (to_double > 0 && pend.size() > 0) { auto it_doubled = doubled.begin(); auto it_pend = --pend.end(); std::pair<int, int> min = *it_doubled; std::pair<int, int> max = *it_pend; if (max.first > min.first) { if (max.second == 0) f_doubled++; if (min.second == 0) f_doubled--; doubled.erase(it_doubled); pend.erase(it_pend); doubled.insert(max); pend.insert(min); total_damage += max.first - min.first; } } } if (doubled.size() > 0 && f_doubled == 0 && doubled.size() == to_double) { auto it_doubled = doubled.begin(); doubled.erase(it_doubled); std::pair<int, int> min = *it_doubled; total_damage -= min.first; if (pend.size() > 0) { auto it_pend = --pend.end(); std::pair<int, int> max = *it_pend; pend.erase(it_pend); doubled.insert(max); f_doubled++; total_damage += max.first; } pend.insert(min); } printf( %lld n , total_damage); } return 0; }
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module relay_decode(
clk,
reset,
mode,
data_in,
data_out,
data_available
);
input clk, reset, mode, data_in;
output[3:0] data_out;
output[0:0] data_available;
reg [3:0] data_out = 4'b0;
reg [0:0] data_available = 1'b0;
reg [6:0] one_counter = 7'b0;
reg [6:0] zero_counter = 7'b0;
reg [0:0] receiving = 1'b0;
always @(posedge clk)
begin
// remove wrong bits
receiving = receiving | data_in == 1'b1;
one_counter = one_counter + (data_in == 1'b1 & receiving);
zero_counter = zero_counter + (data_in == 1'b0 & receiving);
if (one_counter + zero_counter == 7'd64)
begin
if (one_counter > zero_counter)
data_out = (mode == 1'b1 ? 4'hc : 4'hf);
else
data_out = 4'b0;
data_available = 1'b1;
one_counter = 7'b0;
zero_counter = 7'b0;
end
else
begin
data_out = 4'b0;
data_available = 1'b0;
end
// reset
if (reset == 1'b1)
begin
one_counter = 7'b0;
zero_counter = 7'b0;
receiving = 1'b0;
data_out = 4'h0;
data_available = 1'b0;
end
end
endmodule
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`define ADDER_WIDTH 014
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
module printvga(input wire clk, reset, vgae,
input wire [15:0] e,
output wire [7:0] vgax, vgay,
output wire vgaw);
// reg [7:0] i,j;
integer i;
// always @(posedge clock, posedge reset)
// if (reset)
// begin
// i <= 8'b00000000;
// j <= 8'b00000000;
// end
// else if (vgae)
// begin
// j <= 8'b00000000;
// end
// end
//0
initial begin
for (i=0; i<10; i=i+1) begin
i=i;
end
end
assign vgax = 8'b00000000;
assign vgay = 8'b00000000;
assign vgaw = 1;
// //1
// assign vgax = 8'b00000000;
// assign vgay = 8'b00000001;
// assign vgaw = 1;
// //2
// assign vgax = 8'b00000000;
// assign vgay = 8'b00000010;
// assign vgaw = 1;
// //3
// assign vgax = 8'b00000001;
// assign vgay = 8'b00000000;
// assign vgaw = 1;
// //4
// assign vgax = 8'b00000001;
// assign vgay = 8'b00000001;
// assign vgaw = 0;
// //5
// assign vgax = 8'b00000001;
// assign vgay = 8'b00000010;
// assign vgaw = 1;
// //6
// assign vgax = 8'b00000010;
// assign vgay = 8'b00000000;
// assign vgaw = 1;
// //7
// assign vgax = 8'b00000010;
// assign vgay = 8'b00000001;
// assign vgaw = 0;
// //8
// assign vgax = 8'b00000010;
// assign vgay = 8'b00000010;
// assign vgaw = 1;
// //9
// assign vgax = 8'b00000011;
// assign vgay = 8'b00000000;
// assign vgaw = 1;
// //10
// assign vgax = 8'b00000011;
// assign vgay = 8'b00000001;
// assign vgaw = 0;
// //11
// assign vgax = 8'b00000011;
// assign vgay = 8'b00000010;
// assign vgaw = 1;
// //12
// assign vgax = 8'b00000100;
// assign vgay = 8'b00000000;
// assign vgaw = 1;
// //13
// assign vgax = 8'b00000100;
// assign vgay = 8'b00000001;
// assign vgaw = 1;
// //14
// assign vgax = 8'b00000100;
// assign vgay = 8'b00000010;
// assign vgaw = 1;
endmodule // printvga
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// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: reading.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module reading (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/reading.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/reading.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/reading.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL reading_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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#include <bits/stdc++.h> using namespace std; struct edge { int src, dst; }; int const MOD = 1000000007; long long _MOD = 1000000009; double EPS = 1e-9; long long INF = LLONG_MAX / 2; int main() { int N, w; cin >> N >> w; vector<int> a(N); for (int i = 0; i < N; i++) cin >> a[i]; vector<int> b(N); int sum = 0; for (int i = 0; i < N; i++) { b[i] = (a[i] + 1) / 2; sum += b[i]; } if (sum > w) { cout << -1 << endl; return 0; } vector<pair<int, int> > ai(N); for (int i = 0; i < N; i++) ai[i] = pair<int, int>(a[i], i); sort(ai.rbegin(), ai.rend()); for (int t = 0; t < N; t++) { int i = ai[t].second; int d = min(a[i] - b[i], w - sum); b[i] += d; sum += d; } for (int i = 0; i < N; i++) cout << b[i] << ; cout << endl; }
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#include <bits/stdc++.h> using namespace std; const int Maxn = 2e5 + 10; long long Inf = 1e18; const int Log = 20; const long long Sqrt = 1000000; const long long Mod = 998244353LL; long long mul(long long a, long long b) { a %= Mod; b %= Mod; return (a * b) % Mod; } long long bin_pow(long long b, long long p) { long long res = 1; for (long long j = 1, pw = b; j <= p; j <<= 1, pw = mul(pw, pw)) if (p & j) res = mul(res, pw); return res; } long long a[Maxn]; long long X = 110000; long long cnt[Maxn]; long long dp[1010][1010]; long long ps[1010][1010]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; a[0] = -10000000; sort(a + 1, a + n + 1); long long mx = X / max(1LL, (k - 1)); for (int i = 1; i <= mx; i++) { for (int ii = 1; ii <= n; ii++) for (int j = 1; j <= k; j++) dp[ii][j] = 0, ps[ii][j] = 0; long long p1 = 0; dp[0][0] = 1; ps[0][0] = 1; for (int j = 1; j <= n; j++) ps[j][0] = 1; for (int j = 1; j <= n; j++) { while (a[p1] + i <= a[j]) { p1++; } p1--; for (int K = 1; K <= k; K++) { dp[j][K] = ps[p1][K - 1]; ps[j][K] = (ps[j - 1][K] + dp[j][K]) % Mod; } cnt[i] += dp[j][k]; cnt[i] %= Mod; } } long long ans = 0; for (int i = 1; i <= mx; i++) { ans += mul(i, cnt[i] - cnt[i + 1]); ans %= Mod; } ans += Mod; cout << ans % Mod; return 0; }
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#include <bits/stdc++.h> using namespace std; inline long long getnum() { char c = getchar(); long long num, sign = 1; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) sign = -1; for (num = 0; c >= 0 && c <= 9 ;) { c -= 0 ; num = num * 10 + c; c = getchar(); } return num * sign; } int nxt[400005], A[400005], store[400005], at[400005]; set<int> Set; set<pair<long long, long long> > Cur; int main() { int n = getnum(), k = getnum(), ans = 0; for (int i = 1; i <= n; i++) A[i] = getnum(); for (int i = n; i >= 1; i--) { if (store[A[i]] != 0) nxt[i] = store[A[i]]; else nxt[i] = n + 1; store[A[i]] = i; } for (int i = 1; i <= n; i++) { if (Set.find(A[i]) == Set.end()) { ans++; if (Set.size() == k) { auto it = Cur.end(); it--; Set.erase(it->second); Cur.erase(it); } Set.insert(A[i]); Cur.insert({nxt[i], A[i]}); at[A[i]] = i; } else { Cur.erase({nxt[at[A[i]]], A[i]}); Cur.insert({nxt[i], A[i]}); at[A[i]] = i; } } cout << ans << endl; }
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#include <bits/stdc++.h> int main() { int n, m, a[1003], b[1003], i, j, count = 0, k = 0, flag = 0; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { scanf( %d , &a[i]); } for (i = 0; i < m; i++) { scanf( %d , &b[i]); } for (i = 0; i < m; i++) { for (j = k; j < n; j++) { if (b[i] >= a[j]) { count++; flag = 1; break; } } if (flag == 1) { k = j + 1; } else if (flag == 0) { break; } flag = 0; } printf( %d n , count); }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << n << endl; for (int i = 1; i <= n; ++i) cout << 1 ; }
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int x, y, n = 0; cin >> x >> y; for (int i = 2; i <= x; i++) { if (x % i == 0) { n = i; break; } } cout << x + n + (y - 1) * 2 << endl; } }
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#include <bits/stdc++.h> using namespace std; int main(){ int T; cin >> T; long long A[114514]; while(T--){ int N; cin >> N; long long S = 0; for(int i = 0; i < N; i++){ cin >> A[i]; S += A[i]; } sort(A, A+N, greater<long long>()); if(S == 0) cout << 0 << n ; else cout << max({A[1] * (N-1) - S, A[0] * (N-1) - S, N-2 - (S-1) % (N-1)}) << n ; } }
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#include <bits/stdc++.h> using namespace std; vector<int> ev[1000099]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> p(n), pos(n); for (int(i) = (0); (i) < (int)(n); ++(i)) { cin >> p[i]; p[i]--; pos[p[i]] = i; ev[n - i].push_back(p[i]); int k = (p[i] - i + n) % n; if (k != n - i) ev[k].push_back(p[i]); } long long sm = 0; int x = 0, y = 0; vector<int> state(n); for (int(i) = (0); (i) < (int)(n); ++(i)) { if (i < p[i]) x++, state[p[i]] = -1; else y++, state[p[i]] = 1; sm += abs(i - p[i]); } long long mi = LLONG_MAX; int ans = -1; for (int(i) = (0); (i) < (int)(n); ++(i)) { if (i > 0) { for (auto &(num) : (ev[i])) { int nextPos = (pos[num] + i) % n; int prePos = (pos[num] + i - 1) % n; int nextState = nextPos < num ? -1 : 1; sm += abs(nextPos - num) - abs(prePos - num); if (state[num] == -1 && nextState == 1) { sm--; x--; y++; state[num] = 1; } else if (state[num] == 1 && nextState == -1) { sm++; x++; y--; state[num] = -1; } else if (state[num] == nextState) { if (state[num] == 1) sm--; else sm++; } } sm -= x; sm += y; } if (sm < mi) { ans = i; mi = sm; } } cout << mi << << ans << endl; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:37 11/03/2014
// Design Name:
// Module Name: trial
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
?module trial(
clock,
a,
out);
parameter NUM_BITS = 5;
//--------------------------------------------
input clock;
input [NUM_BITS-1:0] a;
output out;wire [NUM_BITS-1:0] a;
wire clock;
reg [NUM_BITS-1:0] out;
//--------------------------------------------
reg [3:0] remain;
reg [3:0] bits = NUM_BITS;
reg [3:0] shift = 4'h0;
//reg exponent;
reg [NUM_BITS-1:0] b;
reg [4:0] r1;
reg [3:0] store000 = 4'h0;
reg [3:0] store001 = 4'h0;
reg [3:0] store010 = 4'h0;
reg [3:0] store100 = 4'h0;
reg [3:0] store101 = 4'h0;
reg [3:0] store110 = 4'h0;
reg count = 1'b0;
//assign b = a;
reg [4:0] VAL1 = 5'h10;
reg [4:0] VAL2 = 5'h12;
reg [4:0] VAL3 = 5'h18;
reg [4:0] VAL4 = 5'h1B;
reg [3:0] exp1 = 4'h00;
reg [3:0] exp2 = 4'h03;
reg [3:0] exp3 = 4'h01;
reg [3:0] exp4 = 4'h04;
always@(posedge clock)
begin
if(count == 1'b0)
begin
b<=a;
remain <= NUM_BITS-1;
end
count <=1'b1;
end
always@(posedge clock)
begin
if(count==1'b1)
begin
if((b >= VAL1) && (remain >= exp1))
begin
if(b < VAL2)
begin
r1[2:0] <= remain - exp1;
r1[4:3] <= 2'b00;
b <= b - VAL1;
end
if((b >= VAL2) && (remain >= exp2))
begin
if(b < VAL3)
begin
r1[2:0] <= remain - exp2;
r1[4:3] <= 2'b10;
b <= b - VAL2;
end
end
if((b >= VAL3) && (remain >= exp3))
begin
if(b < VAL4)
begin
r1[2:0] <= remain - exp3;
r1[4:3] <= 2'b01;
b <= b - VAL3;
end
end
if((b >= VAL4) && (remain >= exp4))
begin
if(b< 6'b100000)
begin
r1[2:0] <= remain - exp4;
r1[4:3] <= 2'b11;
b <= b - VAL4;
end
end
end
else
begin
if(b[4] == 1'b1)
begin
shift <= 4'b0;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[3] == 1'b1)
begin
shift <= 4'b1;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[2] == 1'b1)
begin
shift <= 4'b10;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[1] == 1'b1)
begin
shift <= 4'b11;
remain <= remain - shift;
b <= (b<<shift);
end
else if(b[0] == 1'b1)
begin
shift <= 4'b100;
remain <= remain - shift;
b <= (b<<shift);
end
//else if(b[0] == 1'b1)
// begin
// shift <= 4'b101;
// remain <= remain - shift;
// b <= (b<<shift);
//end
else
begin
shift <= 4'b110;
remain <= remain - shift;
b <= (b<<shift);
end
end
end
end
always@(b)
begin
case(r1)
5'b00000 : store000[0] = 1'b1;
5'b00001 : store000[1] = 1'b1;
5'b01000 : store000[2] = 1'b1;
5'b01001 : store000[3] = 1'b1;
5'b00010 : store001[0] = 1'b1;
5'b00011 : store001[1] = 1'b1;
5'b01010 : store001[2] = 1'b1;
5'b01011 : store001[3] = 1'b1;
5'b00100 : store010[0] = 1'b1;
5'b01100 : store010[2] = 1'b1;
5'b10000 : store100[0] = 1'b1;
5'b10001 : store100[1] = 1'b1;
5'b11000 : store100[2] = 1'b1;
5'b11001 : store100[3] = 1'b1;
5'b10010 : store101[0] = 1'b1;
5'b10011 : store101[1] = 1'b1;
5'b11010 : store101[2] = 1'b1;
5'b11011 : store101[3] = 1'b1;
5'b10100 : store110[0] = 1'b1;
5'b11100 : store110[2] = 1'b1;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 2010; int n, a[N], p[N], pos[N]; vector<int> c[26], ans; string s, t; void add(int x) { if (0 < x) { ans.push_back(x); } vector<int> nw; for (int i = n - 1; i >= n - x; --i) { nw.push_back(p[i]); } for (int i = n - 1; i >= x; --i) { p[i] = p[i - x]; } for (int i = 0; i < x; ++i) { p[i] = nw[i]; } for (int i = 0; i < n; ++i) { pos[p[i]] = i; } } int main() { cin >> n >> s >> t; for (int i = 0; i < n; ++i) { c[t[i] - a ].push_back(i); } for (int i = 0; i < n; ++i) { int ind = s[i] - a ; if (c[ind].size() == 0) { puts( -1 ); return 0; } p[i] = c[ind].back(); c[ind].pop_back(); pos[p[i]] = i; } for (int i = 0; i < n; ++i) { add(n - pos[i] - 1); add(1); add(n); } cout << ans.size() << n ; for (int i : ans) cout << i << ; return 0; }
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`timescale 1ns / 1ns
module eth_rx
(input c, // must be the 50 MHz RMII reference clock
input [1:0] phy_rxd,
input phy_rxdv,
output [7:0] d,
output dv,
output erx); // end of RX
wire [1:0] rmii_d;
sync #(2) rmii_d_sync_r
(.in(phy_rxd), .clk(c), .out(rmii_d));
wire rmii_dv;
sync rmii_dv_sync_r
(.in(phy_rxdv), .clk(c), .out(rmii_dv));
wire rmii_dv_d1;
d1 rxdv_d1_r(.d(rmii_dv), .c(c), .q(rmii_dv_d1));
wire [7:0] rxd_shift;
r #(8) rxd_shift_r
(.c(c), .d({rmii_d, rxd_shift[7:2]}), .rst(1'b0), .en(1'b1), .q(rxd_shift));
wire shift_cnt_rst;
wire [1:0] shift_cnt;
r #(2) shift_cnt_r
(.c(c), .d(shift_cnt+1'b1), .en(1'b1), .rst(shift_cnt_rst), .q(shift_cnt));
assign d = rxd_shift;
localparam SW = 3, CW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_PREAMBLE = 3'd1;
localparam ST_PAYLOAD = 3'd2;
localparam ST_STOP = 3'd3;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
always @* begin
case (state)
ST_IDLE:
if (rmii_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PREAMBLE:
if (rmii_dv && d == 8'h55) ctrl = { ST_PREAMBLE, 3'b000 };
else if (rmii_dv && d == 8'hd5) ctrl = { ST_PAYLOAD , 3'b100 };
else ctrl = { ST_IDLE , 3'b000 };
ST_PAYLOAD:
if (rmii_dv | rmii_dv_d1) ctrl = { ST_PAYLOAD , 3'b001 };
else ctrl = { ST_STOP , 3'b010 };
ST_STOP: ctrl = { ST_IDLE , 3'b000 }; // fcs ?
default: ctrl = { ST_IDLE , 3'b000 };
endcase
end
assign dv = state == ST_PAYLOAD & &shift_cnt;
assign erx = ctrl[1];
assign shift_cnt_rst = ctrl[2];
endmodule
`ifdef test_eth_rx
module eth_rx_tb();
wire c;
sim_clk #(50) clk_50(c);
wire [1:0] rmii_txd, rmii_rxd;
wire rmii_rst, mdc, mdio;
wire rmii_txen, rmii_rxdv;
fake_rmii_phy #(.INPUT_FILE_NAME("tb_packets.dat")) phy
(.refclk(c), .rst(rmii_rst), .mdc(mdc), .mdio(mdio),
.txd(rmii_txd), .txen(rmii_txen),
.rxd(rmii_rxd), .rxdv(rmii_rxdv));
wire [7:0] rxd;
wire rxdv, erx;
eth_rx dut
(.c(c), .phy_rxd(rmii_rxd), .phy_rxdv(rmii_rxdv),
.d(rxd), .dv(rxdv), .erx(erx));
initial begin
$dumpfile("eth_rx.lxt");
$dumpvars();
#100000;
$finish();
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; template <typename T> inline void read(T &x) { x = 0; T fl = 1; char ch = 0; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) fl = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = (x << 1) + (x << 3) + (ch ^ 48); x *= fl; } template <typename T, typename... Args> inline void read(T &x, Args &...args) { read(x); read(args...); } const int N = 1e5 + 5; struct data { int s, m, r, t; data(int x = 0) { t = x; } bool operator<(const data &b) const { return t < b.t; } long long calc(long long tim) { return min(s + tim * r, m * 1ll); } } a[18][N]; struct seg { int trt[N << 2]; long long trm[18][N << 2], trr[18][N << 2]; void pushdown(int nod) { if (trt[nod] >= 0) trt[(nod << 1)] = trt[(nod << 1 | 1)] = trt[nod]; } void pushup(int nod) { if (trt[(nod << 1)] != trt[(nod << 1 | 1)]) trt[nod] = -1; else trt[nod] = trt[(nod << 1)]; } void build(int nod, int l, int r, int dep) { trt[nod] = -2; if (l == r) { read(a[dep][l].s, a[dep][l].m, a[dep][l].r); if (a[dep][l].r == 0) a[dep][l].t = inf; else a[dep][l].t = a[dep][l].m % a[dep][l].r == 0 ? a[dep][l].m / a[dep][l].r : a[dep][l].m / a[dep][l].r + 1; trm[dep][l] = trm[dep][l - 1] + a[dep][l].m; trr[dep][l] = trr[dep][l - 1] + a[dep][l].r; return; } int mid = (l + r) >> 1; build((nod << 1), l, mid, dep + 1); build((nod << 1 | 1), mid + 1, r, dep + 1); for (int i = (l); i <= (r); i++) a[dep][i] = a[dep + 1][i]; sort(a[dep] + l, a[dep] + r + 1); for (int i = (l); i <= (r); i++) { trm[dep][i] = trm[dep][i - 1] + a[dep][i].m; trr[dep][i] = trr[dep][i - 1] + a[dep][i].r; } } long long query(int tim, int nod, int l, int r, int ql, int qr, int dep) { long long res = 0; if (ql <= l && r <= qr && trt[nod] != -1) { if (trt[nod] == -2) for (int i = (l); i <= (r); i++) res += a[dep][i].calc(tim); else { int i = upper_bound(a[dep] + l, a[dep] + 1 + r, data(tim - trt[nod])) - a[dep] - 1; res = (tim - trt[nod]) * (trr[dep][r] - trr[dep][i]) + trm[dep][i] - trm[dep][l - 1]; } trt[nod] = tim; return res; } pushdown(nod); int mid = (l + r) >> 1; if (ql <= mid) res += query(tim, (nod << 1), l, mid, ql, qr, dep + 1); if (qr > mid) res += query(tim, (nod << 1 | 1), mid + 1, r, ql, qr, dep + 1); pushup(nod); return res; } } sgt; int n, m; int main() { read(n); sgt.build(1, 1, n, 0); read(m); for (int _ = (1); _ <= (m); _++) { int t, l, r; read(t); read(l); read(r); printf( %lld n , sgt.query(t, 1, 1, n, l, r, 0)); } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> inline void amax(T &x, U y) { if (x < y) x = y; } struct UnionFind { vector<int> data; UnionFind(int size_) : data(size_, -1) {} bool unionSet(int x, int y) { x = root(x); y = root(y); if (x != y) { if (data[y] < data[x]) swap(x, y); data[x] += data[y]; data[y] = x; } return x != y; } bool findSet(int x, int y) { return root(x) == root(y); } int root(int x) { return data[x] < 0 ? x : data[x] = root(data[x]); } int size(int x) { return -data[root(x)]; } }; struct Edge { int x, y; int w; Edge() {} Edge(int x_, int y_, int w_) : x(x_), y(y_), w(w_) {} }; bool operator<(const Edge &a, const Edge &b) { return a.w < b.w; } vector<vector<int> > g; vector<long long> dist; vector<vector<int> > d; void dfs(int i, int p, long long t) { dist[i] = t; for (typeof((g[i]).begin()) j = ((g[i]).begin()); j != (g[i]).end(); ++j) if (*j != p) dfs(*j, i, t + d[i][*j]); } int main() { int n; scanf( %d , &n); d.assign(n, vector<int>(n)); for (int(i) = 0; (i) < (int)(n); ++(i)) for (int(j) = 0; (j) < (int)(n); ++(j)) scanf( %d , &d[i][j]); bool ok = true; for (int(i) = 0; (i) < (int)(n); ++(i)) for (int(j) = 0; (j) < (int)(i); ++(j)) { ok &= d[i][j] == d[j][i]; ok &= d[i][j] > 0; } for (int(i) = 0; (i) < (int)(n); ++(i)) ok &= d[i][i] == 0; if (!ok) { puts( NO ); return 0; } vector<Edge> edges; edges.reserve(n * (n - 1) / 2); for (int(i) = 0; (i) < (int)(n); ++(i)) for (int(j) = 0; (j) < (int)(i); ++(j)) edges.push_back(Edge(i, j, d[i][j])); sort(edges.begin(), edges.end()); UnionFind uf(n); g.assign(n, vector<int>()); for (int i = 0; i < (int)edges.size(); i++) { int x = edges[i].x, y = edges[i].y; if (uf.unionSet(x, y)) { g[x].push_back(y); g[y].push_back(x); } } dist.resize(n); for (int(i) = 0; (i) < (int)(n); ++(i)) { dfs(i, -1, 0); for (int(j) = 0; (j) < (int)(n); ++(j)) ok &= dist[j] == d[i][j]; } puts(ok ? YES : NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } long long int INF = 1e17; long long int NINF = (INF * -1); priority_queue<pair<long long int, long long int>, vector<pair<long long int, long long int>>, greater<pair<long long int, long long int>>> pq; vector<long long int> indegree; vector<vector<pair<long long int, long long int>>> adj; vector<long long int> distances; vector<vector<long long int>> arr; vector<bool> visited; vector<long long int> level, height; vector<long long int> ans; long long int dfs(long long int src, long long int parent = -1, long long int l = 0) {} void solve() { long long int n; cin >> n; string a; string b; cin >> a >> b; vector<long long int> ab, ba; vector<pair<long long int, long long int>> ans; for (long long int i = 0; i < n; i++) { if (a[i] == b[i]) { continue; } if (a[i] == a and b[i] == b ) { if (ab.size() != 0) { ans.push_back({ab.back(), i + 1}); ab.pop_back(); } else { ab.push_back(i + 1); } } else { if (ba.size() != 0) { ans.push_back({ba.back(), i + 1}); ba.pop_back(); } else { ba.push_back(i + 1); } } } if (ab.size() == 1 and ba.size() == 1) { ans.push_back({ba.back(), ba.back()}); ans.push_back({ba.back(), ab.back()}); ab.pop_back(); ba.pop_back(); } if (ab.size() != 0 || ba.size() != 0) { cout << -1 n ; return; } cout << ans.size(); cout << n ; ; for (auto i : ans) { cout << i.first << << i.second; cout << n ; ; } return; } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); long long int t = 1; while (t--) { solve(); } }
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#include <bits/stdc++.h> using namespace std; const long long int INF = 1e18; const int inf = 1e9; const int MOD = 1e9 + 7; const int nax = 500000 + 10; int arr[nax], color[nax]; vector<int> graph[nax]; map<int, set<int> > map1; int main() { ios::sync_with_stdio(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) cin >> color[i]; while (m--) { int u, v; cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } for (int i = 1; i <= n; i++) { for (auto x : graph[i]) { if (color[i] != color[x]) map1[color[i]].insert(color[x]); } } int maxi = map1[color[1]].size(), ans = color[1]; for (int i = 2; i <= n; i++) { if (map1[color[i]].size() == maxi && color[i] < ans) { ans = color[i]; } else if (map1[color[i]].size() > maxi) { maxi = map1[color[i]].size(); ans = color[i]; } } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } using namespace std; bool b[100000 + 5]; vector<int> v[100000 + 5]; int n, m; int s[100000 + 5]; int ans[100000 + 5], cnt = 0; bool yes = true; void dfs(int x, int fa) { if (fa != 0 && s[x] != x && s[x] != s[fa]) { puts( -1 ); yes = false; } if (s[x] == x) ans[++cnt] = x; for (int i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (y == fa) continue; dfs(y, x); } } int main() { n = read(); m = read(); for (int i = 1; i <= m; i++) { int x = read(), y = read(); v[x].push_back(y); b[y] = 1; } for (int i = 1; i <= n; i++) s[i] = read(); for (int i = 1; i <= n; i++) { if (!b[i]) dfs(i, 0); } if (yes == true) { cout << cnt << endl; for (int i = cnt; i >= 1; i--) { cout << ans[i] << endl; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> int len(const T& c) { return (int)c.size(); } int main() { int n, bb; double b1; vector<double> b; cin >> n >> bb; for (int i(0), _n(n); i < _n; ++i) { cin >> b1; b.push_back(b1); } double sum = accumulate(b.begin(), b.end(), 0); double mx = *max_element(b.begin(), b.end()); double avg = (sum + bb) / n; if (mx > avg) { cout << -1; return 0; } for (int i(0), _n(n); i < _n; ++i) printf( %.6f n , avg - b[i]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_BLACKBOX_V
/**
* busdrivernovlpsleep: Bus driver, enable gates pulldown only,
* non-inverted sleep input (on kapwr rail).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlpsleep (
Z ,
A ,
TE_B ,
SLEEP,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B ;
input SLEEP;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_PP_BLACKBOX_V
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#include <bits/stdc++.h> using namespace std; int main() { string s; int i, count1 = 0, count = 0; cin >> s; for (i = 0; i < s.length(); i++) { if (s[i] == 1 ) { count++; count1 = 0; if (count == 7) { cout << YES ; return 0; } } else { count = 0; count1++; if (count1 == 7) { cout << YES ; return 0; } } } cout << NO ; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
module t;
`define TRIES 100
bit [6:0] b5a; // We use larger than [4:0] so make sure we truncate
bit [6:0] b5b; // We use larger than [4:0] so make sure we truncate
bit [6:0] b7c;
bit [6:0] b7d;
bit [59:0] b60c;
bit [89:0] b90c;
bit [6:0] max_b5a;
bit [6:0] max_b5b;
bit [6:0] max_b7c;
bit [6:0] max_b7d;
bit [59:0] max_b60c;
bit [89:0] max_b90c;
initial begin
for (int i = 0; i < `TRIES; ++i) begin
// verilator lint_off WIDTH
// Optimize away extracts
b5a = {$random}[4:0];
b5b = {$random}[14:10];
// Optimize away concats
b7c = {$random, $random, $random, $random, $random, $random, $random};
b7d = {{{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}, {{$random}[0]}};
b60c = {$random, $random, $random, $random, $random, $random, $random};
b90c = {$random, $random, $random, $random, $random, $random, $random};
// verilator lint_on WIDTH
max_b5a = max_b5a | b5a;
max_b5b = max_b5b | b5b;
max_b7c = max_b7c | b7c;
max_b7d = max_b7d | b7d;
max_b60c = max_b60c | b60c;
max_b90c = max_b90c | b90c;
end
`checkh(max_b5a, 7'h1f);
`checkh(max_b5b, 7'h1f);
`checkh(max_b7c, 7'h7f);
`checkh(max_b7d, 7'h1f);
`checkh(max_b60c, ~ 60'h0);
`checkh(max_b90c, ~ 90'h0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_2_V
`define SKY130_FD_SC_HS__HA_2_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dac vdma read
module ad_axis_dma_tx (
// vdma interface
dma_clk,
dma_rst,
dma_fs,
dma_valid,
dma_data,
dma_ready,
dma_ovf,
dma_unf,
// dac interface
dac_clk,
dac_rst,
dac_rd,
dac_valid,
dac_data,
// processor interface
dma_frmcnt);
// parameters
parameter DATA_WIDTH = 64;
localparam DW = DATA_WIDTH - 1;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
localparam RDY_THRESHOLD_LO = 6'd40;
localparam RDY_THRESHOLD_HI = 6'd50;
// vdma interface
input dma_clk;
input dma_rst;
output dma_fs;
input dma_valid;
input [DW:0] dma_data;
output dma_ready;
output dma_ovf;
output dma_unf;
// dac interface
input dac_clk;
input dac_rst;
input dac_rd;
output dac_valid;
output [DW:0] dac_data;
// processor interface
input [31:0] dma_frmcnt;
// internal registers
reg dac_start_m1 = 'd0;
reg dac_start = 'd0;
reg dac_resync_m1 = 'd0;
reg dac_resync = 'd0;
reg [ 5:0] dac_raddr = 'd0;
reg [ 5:0] dac_raddr_g = 'd0;
reg dac_rd_d = 'd0;
reg dac_rd_2d = 'd0;
reg dac_valid = 'd0;
reg [DW:0] dac_data = 'd0;
reg [31:0] dma_clkcnt = 'd0;
reg dma_fs = 'd0;
reg [ 5:0] dma_raddr_g_m1 = 'd0;
reg [ 5:0] dma_raddr_g_m2 = 'd0;
reg [ 5:0] dma_raddr = 'd0;
reg [ 5:0] dma_addr_diff = 'd0;
reg dma_ready = 'd0;
reg dma_almost_full = 'd0;
reg dma_almost_empty = 'd0;
reg dma_ovf = 'd0;
reg dma_unf = 'd0;
reg dma_resync = 'd0;
reg dma_start = 'd0;
reg dma_wr = 'd0;
reg [ 5:0] dma_waddr = 'd0;
reg [DW:0] dma_wdata = 'd0;
// internal signals
wire dma_wr_s;
wire [ 6:0] dma_addr_diff_s;
wire dma_ovf_s;
wire dma_unf_s;
wire [DW:0] dac_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// dac read interface
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_start_m1 <= 'd0;
dac_start <= 'd0;
dac_resync_m1 <= 'd0;
dac_resync <= 'd0;
end else begin
dac_start_m1 <= dma_start;
dac_start <= dac_start_m1;
dac_resync_m1 <= dma_resync;
dac_resync <= dac_resync_m1;
end
if ((dac_start == 1'b0) || (dac_resync == 1'b1) || (dac_rst == 1'b1)) begin
dac_raddr <= 6'd0;
end else if (dac_rd == 1'b1) begin
dac_raddr <= dac_raddr + 1'b1;
end
dac_raddr_g <= b2g(dac_raddr);
dac_rd_d <= dac_rd;
dac_rd_2d <= dac_rd_d;
dac_valid <= dac_rd_2d;
dac_data <= dac_rdata_s;
end
// generate fsync
always @(posedge dma_clk) begin
if ((dma_resync == 1'b1) || (dma_rst == 1'b1) || (dma_clkcnt >= dma_frmcnt)) begin
dma_clkcnt <= 16'd0;
end else begin
dma_clkcnt <= dma_clkcnt + 1'b1;
end
if (dma_clkcnt == 32'd1) begin
dma_fs <= 1'b1;
end else begin
dma_fs <= 1'b0;
end
end
// overflow or underflow status
assign dma_addr_diff_s = {1'b1, dma_waddr} - dma_raddr;
assign dma_ovf_s = (dma_addr_diff < BUF_THRESHOLD_LO) ? dma_almost_full : 1'b0;
assign dma_unf_s = (dma_addr_diff > BUF_THRESHOLD_HI) ? dma_almost_empty : 1'b0;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_raddr_g_m1 <= 'd0;
dma_raddr_g_m2 <= 'd0;
end else begin
dma_raddr_g_m1 <= dac_raddr_g;
dma_raddr_g_m2 <= dma_raddr_g_m1;
end
dma_raddr <= g2b(dma_raddr_g_m2);
dma_addr_diff <= dma_addr_diff_s[5:0];
if (dma_addr_diff >= RDY_THRESHOLD_HI) begin
dma_ready <= 1'b0;
end else if (dma_addr_diff <= RDY_THRESHOLD_LO) begin
dma_ready <= 1'b1;
end
if (dma_addr_diff > BUF_THRESHOLD_HI) begin
dma_almost_full <= 1'b1;
end else begin
dma_almost_full <= 1'b0;
end
if (dma_addr_diff < BUF_THRESHOLD_LO) begin
dma_almost_empty <= 1'b1;
end else begin
dma_almost_empty <= 1'b0;
end
dma_ovf <= dma_ovf_s;
dma_unf <= dma_unf_s;
dma_resync <= dma_ovf | dma_unf;
end
// vdma write
assign dma_wr_s = dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start <= 1'b0;
end else if (dma_wr_s == 1'b1) begin
dma_start <= 1'b1;
end
dma_wr <= dma_wr_s;
if ((dma_resync == 1'b1) || (dma_rst == 1'b1)) begin
dma_waddr <= 6'd0;
end else if (dma_wr == 1'b1) begin
dma_waddr <= dma_waddr + 1'b1;
end
dma_wdata <= dma_data;
end
// memory
ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6)) i_mem (
.clka (dma_clk),
.wea (dma_wr),
.addra (dma_waddr),
.dina (dma_wdata),
.clkb (dac_clk),
.addrb (dac_raddr),
.doutb (dac_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
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