text
stringlengths 59
71.4k
|
|---|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_clksw.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_clksel
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_clksw(/*AUTOARG*/
// Outputs
cmp_tst_clk, cmp_clk_sel, dram_tst_clk, dram_clk_sel, jbus_tst_clk,
jbus_clk_sel,
// Inputs
io_pwron_rst_l, jtag_clock_dr_cmp, jtag_clock_dr_jbus,
jtag_clock_dr_dram, capture_l, jtag_clsp_sel_cpu, jtag_clsp_sel_dram,
jtag_clsp_sel_jbus, jbus_alt_bypsel_l,
cmp_div_bypass, cmp_gclk_bypass, jbus_div_bypass, jbus_gclk_bypass,
dram_gclk_bypass, testmode_l, cmp_nstep_sel, jbus_nstep_sel,
dram_nstep_sel
);
input io_pwron_rst_l;
input jtag_clock_dr_cmp;
input jtag_clock_dr_jbus;
input jtag_clock_dr_dram;
input capture_l;
input [2:0] jtag_clsp_sel_cpu;
input [2:0] jtag_clsp_sel_dram;
input [2:0] jtag_clsp_sel_jbus;
input jbus_alt_bypsel_l;
input cmp_div_bypass;
input cmp_gclk_bypass;
input jbus_div_bypass;
input jbus_gclk_bypass;
input dram_gclk_bypass;
input testmode_l;
input cmp_nstep_sel;
input jbus_nstep_sel;
input dram_nstep_sel;
output cmp_tst_clk; // to sync mux
output cmp_clk_sel; // to sync mux
output dram_tst_clk;
output dram_clk_sel;
output jbus_tst_clk;
output jbus_clk_sel;
/* ctu_clsp_clkgn_clksel AUTO_TEMPLATE (
.sel (jtag_clsp_sel_cpu[2:0]),
.sysclk(cmp_gclk_bypass),
.divbypclk(cmp_div_bypass),
.clkout(cmp_tst_clk),
.sysclk_sel(cmp_clk_sel),
.nstepsel(cmp_nstep_sel),
.jtag_clock_dr(jtag_clock_dr_cmp),
.byp_mult_sel_l(1'b0),
.bypmode(1'b0),
);
*/
ctu_clsp_clkgn_clksel u_cmp(/*AUTOINST*/
// Outputs
.clkout (cmp_tst_clk), // Templated
.sysclk_sel(cmp_clk_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l),
.sel (jtag_clsp_sel_cpu[2:0]), // Templated
.testmode_l(testmode_l),
.sysclk (cmp_gclk_bypass), // Templated
.divbypclk(cmp_div_bypass), // Templated
.byp_mult_sel_l(1'b0), // Templated
.nstepsel(cmp_nstep_sel), // Templated
.jtag_clock_dr(jtag_clock_dr_cmp), // Templated
.capture_l(capture_l),
.bypmode (1'b0)); // Templated
/* ctu_clsp_clkgn_clksel AUTO_TEMPLATE (
.sel (jtag_clsp_sel_jbus[2:0]),
.sysclk(jbus_gclk_bypass),
.divbypclk(jbus_div_bypass),
.clkout(jbus_tst_clk),
.sysclk_sel(jbus_clk_sel),
.nstepsel(jbus_nstep_sel),
.jtag_clock_dr(jtag_clock_dr_jbus),
.byp_mult_sel_l(jbus_alt_bypsel_l),
.bypmode(jtag_clsp_sel_jbus[2]),
);
*/
ctu_clsp_clkgn_clksel u_jbus(/*AUTOINST*/
// Outputs
.clkout (jbus_tst_clk), // Templated
.sysclk_sel(jbus_clk_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l),
.sel (jtag_clsp_sel_jbus[2:0]), // Templated
.testmode_l(testmode_l),
.sysclk (jbus_gclk_bypass), // Templated
.divbypclk(jbus_div_bypass), // Templated
.byp_mult_sel_l(jbus_alt_bypsel_l), // Templated
.nstepsel(jbus_nstep_sel), // Templated
.jtag_clock_dr(jtag_clock_dr_jbus), // Templated
.capture_l(capture_l),
.bypmode(jtag_clsp_sel_jbus[2])); // Templated
/* ctu_clsp_clkgn_clksel AUTO_TEMPLATE (
.sel (jtag_clsp_sel_dram[2:0]),
.sysclk(dram_gclk_bypass),
.divbypclk(1'b0),
.clkout(dram_tst_clk),
.sysclk_sel(dram_clk_sel),
.nstepsel(dram_nstep_sel),
.jtag_clock_dr(jtag_clock_dr_dram),
.byp_mult_sel_l(1'b1),
.bypmode(1'b0),
);
*/
ctu_clsp_clkgn_clksel u_dram (/*AUTOINST*/
// Outputs
.clkout(dram_tst_clk), // Templated
.sysclk_sel(dram_clk_sel), // Templated
// Inputs
.io_pwron_rst_l(io_pwron_rst_l),
.sel (jtag_clsp_sel_dram[2:0]), // Templated
.testmode_l(testmode_l),
.sysclk(dram_gclk_bypass), // Templated
.divbypclk(1'b0), // Templated
.byp_mult_sel_l(1'b1), // Templated
.nstepsel(dram_nstep_sel), // Templated
.jtag_clock_dr(jtag_clock_dr_dram), // Templated
.capture_l(capture_l),
.bypmode(1'b0)); // Templated
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files:("../common/rtl/ctu_lib.v" "../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> int ss[250000], ff[250000], cc[250000], rr[250000], ii[250000]; int compare(const void *a, const void *b) { int i = *(int *)a; int j = *(int *)b; return rr[i] - rr[j]; } int main() { static int aa[400]; typedef int ian[400]; static ian dp_[400], dq_[400], *dp = dp_, *dq = dq_, *tmp; int n, m, h, h_, i, r, s, f; long long v; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) scanf( %d , &aa[i]); for (h = 0; h < m; h++) { scanf( %d%d%d%d , &ss[h], &ff[h], &cc[h], &rr[h]); ss[h]--; ff[h]--; ii[h] = h; } qsort(ii, m, sizeof *ii, compare); for (s = 0; s < n; s++) for (f = s + 1; f < n; f++) dp[s][f] = aa[f] - aa[s]; v = 0; for (r = 0, h_ = 0; r <= n; r++) { while (h_ < m && rr[h = ii[h_]] == r) { long long x; if (v < (x = (long long)dp[ss[h]][ff[h]] * cc[h])) v = x; h_++; } for (s = 0; s < n; s++) { i = s; for (f = s + 1; f < n; f++) { while (i < f && dp[s][i] < aa[f] - aa[i]) i++; dq[s][f] = aa[f] - aa[i - 1]; if (dq[s][f] > dp[s][i]) dq[s][f] = dp[s][i]; } } tmp = dp; dp = dq; dq = tmp; } printf( %lld n , v); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { long long n, a, b, c, d; cin >> n >> a >> b >> c >> d; int x = 0; if (((c + d) < n * (a - b)) || ((c - d) > n * (a + b))) cout << No << endl; else cout << Yes << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_SYMBOL_V
`define SKY130_FD_SC_MS__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int fx[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const int fxx[8][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; template <typename T, typename TT> ostream& operator<<(ostream& s, pair<T, TT> t) { return s << ( << t.first << , << t.second << ) ; } template <typename T> ostream& operator<<(ostream& s, vector<T> t) { s << [ ; for (int i = 0; i < ((int)(t.size())) - 1; i++) s << t[i] << , ; s << t[((int)(t.size())) - 1] << ] ; return s; } const int MOD = 1e9 + 7; template <typename T> inline T gcD(T a, T b) { if (a < b) swap(a, b); while (b) { a = a % b; b ^= a; a ^= b; b ^= a; }; return a; } template <typename T> inline T pow_mod(T a, T b) { T res = 1; while (b) { if (b & 1) res = (res * a) % MOD; a = (a * a) % MOD; b >>= 1; } return res; } struct Node { int value, x, y; bool operator<(const Node other) const { if (value == other.value && x == other.x) return y < other.y; else if (value == other.value) return x < other.x; else return value < other.value; } }; const int MAXN = 310; int room[MAXN][MAXN]; int dis[MAXN][MAXN]; vector<Node> dp[MAXN * MAXN]; vector<Node> bfs; int main() { int n, m, p; cin >> n >> m >> p; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> room[i][j]; if (room[i][j] == 1) { dp[1].push_back({i + j, i, j}); } else dp[room[i][j]].push_back({(int)1e9, i, j}); } for (int i = 2; i < p + 1; i++) { if (dp[i - 1].size() * dp[i].size() >= n * m) { bfs.clear(); sort(dp[i - 1].begin(), dp[i - 1].end()); bfs.push_back(dp[i - 1][0]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) dis[i][j] = (int)1e9; dis[dp[i - 1][0].x][dp[i - 1][0].y] = dp[i - 1][0].value; int pt = 1; int j = 0; while (j < bfs.size()) { Node top = bfs[j++]; while (pt < dp[i - 1].size() && dp[i - 1][pt].value <= top.value) bfs.push_back(dp[i - 1][pt++]); for (int k = 0; k < 4; k++) { int new_x = top.x + fx[k][0]; int new_y = top.y + fx[k][1]; if (new_x >= 0 && new_x < n && new_y >= 0 && new_y < m) { if (dis[new_x][new_y] > top.value + 1) { dis[new_x][new_y] = top.value + 1; bfs.push_back({dis[new_x][new_y], new_x, new_y}); } } } } for (__typeof((dp[i]).begin()) v = (dp[i]).begin(); v != (dp[i]).end(); ++v) { v->value = dis[v->x][v->y]; } } else { for (__typeof((dp[i]).begin()) v = (dp[i]).begin(); v != (dp[i]).end(); ++v) { for (__typeof((dp[i - 1]).begin()) w = (dp[i - 1]).begin(); w != (dp[i - 1]).end(); ++w) { v->value = min(v->value, w->value + abs(w->x - v->x) + abs(w->y - v->y)); } } } } cout << dp[p][0].value << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; string s; cin >> s; int l = -1; for (int i = 0; i < n - 1 && k > 0; i++) { if (s[i] == 4 && s[i + 1] == 7 ) { if (i % 2 == 1) { if (i - 1 >= 0 && s[i - 1] == 4 ) { l = i; break; } } --k; if (i % 2 == 0) s[i + 1] = 4 ; else s[i] = 7 ; } } if (l != -1) { if (k % 2 == 1) s[l] = 7 ; } cout << s; return 0; }
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4k (
data,
wrreq,
rdreq,
rdclk,
wrclk,
aclr,
q,
rdempty,
rdusedw,
wrfull,
wrusedw)/* synthesis synthesis_clearbox = 1 */;
input [15:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5, K = 505, INF = K * (1e4 + 5); int n, m, k; int c[N], a[N], visit[N]; int w[K][K]; vector<pair<int, int>> edges[N]; vector<int> colors; void dfs(int s) { visit[s] = 1; colors.push_back(a[s]); for (auto x : edges[s]) { int nxt = x.first; int w = x.second; if (visit[nxt] || w) continue; dfs(nxt); } } vector<vector<int>> ffloyd(int M) { vector<vector<int>> dist(M, vector<int>(M, INF)); for (int i = 0; i < M; i++) for (int j = 0; j < M; j++) dist[i][j] = w[i][j]; for (int k = 0; k < M; k++) { for (int i = 0; i < M; i++) { for (int j = 0; j < M; j++) { if (dist[i][k] < INF && dist[k][j] < INF) dist[i][j] = min(dist[i][j], dist[i][k] + dist[k][j]); } } } return dist; } void solve() { cin >> n >> m >> k; for (int i = 0; i < k; i++) cin >> c[i]; int col = 0; for (int i = 0, id = 0; i < k; i++) { for (int j = 0; j < c[i]; j++) a[id++] = col; col++; } for (int i = 0; i < k; i++) for (int j = 0; j < k; j++) if (i != j) w[i][j] = INF; while (m--) { int u, v, x; cin >> u >> v >> x; u--; v--; edges[u].push_back({v, x}); edges[v].push_back({u, x}); u = a[u], v = a[v]; if (u == v) continue; w[u][v] = min(w[u][v], x); w[v][u] = min(w[v][u], x); } int fail = 0; for (int i = 0; i < n; i++) { if (!visit[i]) { dfs(i); sort(colors.begin(), colors.end()); int count = 1; for (int i = 1; i < colors.size(); i++) { if (colors[i] == colors[i - 1]) { count++; continue; } if (c[colors[i - 1]] != count) { fail = 1; break; } count = 1; } if (c[colors.back()] != count) { fail = 1; break; } colors.clear(); } } if (fail) { cout << No n ; return; } cout << Yes n ; vector<vector<int>> dist = ffloyd(k); for (int i = 0; i < k; i++) { for (int j = 0; j < k; j++) { if (dist[i][j] == INF) dist[i][j] = -1; cout << dist[i][j] << ; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This is almost an exact copy of the lsu_burst_master, but has special support
// for placing items into a a block ram rather than a fifo. I'd rather leave them
// as separate files rather than complicating the already existing lsu's which are
// are known to work.
//
// Helper module to handle bursting large sequential blocks of memory to or
// from global memory.
//
/*****************************************************************************/
// Burst read master:
// Keeps a local buffer populated with data from a sequential block of
// global memory. The block of global memory is specified by a base address
// and size.
/*****************************************************************************/
module lsu_prefetch_block (
clk,
reset,
o_active, //Debugging signal
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
cache_line_to_write_to,
control_done,
control_early_done,
// user logic inputs and outputs
cache_line_to_read_from,
user_buffer_address,
user_buffer_data,
user_data_available,
read_reg_enable,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
/*************
* Parameters *
*************/
parameter DATAWIDTH = 32;
parameter MWIDTH = DATAWIDTH;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
parameter N=8;
parameter LOG2N=3;
/********
* Ports *
********/
input clk;
input reset;
output o_active;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
input [LOG2N-1:0] cache_line_to_write_to;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input [LOG2N-1:0] cache_line_to_read_from;
input [FIFODEPTH_LOG2-1:0] user_buffer_address;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
input read_reg_enable;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
/***************
* Architecture *
***************/
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
wire too_many_reads_pending;
reg [FIFODEPTH_LOG2:0] w_user_buffer_address;
// Pipelining
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata /* synthesis dont_merge */;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// user buffer address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
if(control_go == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
w_user_buffer_address <= w_user_buffer_address + r_avm_readdatavalid;
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = 1'b0;
assign control_early_done = 1'b0;
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = 0;
/* --- Pipeline Return Path --- */
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_avm_readdata <= 'x;
r_avm_readdatavalid <= 1'b0;
end
else
begin
r_avm_readdata <= master_readdata;
r_avm_readdatavalid <= master_readdatavalid;
end
end
assign user_data_available = w_user_buffer_address[FIFODEPTH_LOG2];
altsyncram altsyncram_component (
.clock0 (clk),
.address_a ({cache_line_to_write_to,w_user_buffer_address[FIFODEPTH_LOG2-1:0]}),
.wren_a (r_avm_readdatavalid),
.data_a (r_avm_readdata),
.address_b ({cache_line_to_read_from,user_buffer_address}),
.q_b (user_buffer_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (~read_reg_enable),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATAWIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = N*FIFODEPTH,
altsyncram_component.numwords_b = N*FIFODEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.widthad_b = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1;
assign o_active = |length;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100000], s[100000]; void qs(int q, int w) { int e = q, r = w, t = a[q + (rand() % (w - q + 1))], y; do { while (a[e] < t) e++; while (a[r] > t) r--; if (e <= r) { y = a[e]; a[e] = a[r]; a[r] = y; y = s[e]; s[e] = s[r]; s[r] = y; e++; r--; } } while (e <= r); if (q < r) qs(q, r); if (e < w) qs(e, w); } int main() { int q, w, e, r, t; cin >> q; for (w = 0; w < q; w++) { cin >> a[w]; s[w] = w + 1; } qs(0, q - 1); cout << (q + 1) / 2 << n ; for (w = 0; w < q; w += 2) cout << s[w] << ; cout << n << q / 2 << n ; for (w = 1; w < q; w += 2) cout << s[w] << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2 * 1e5 + 100; long long t, n; struct node { long long m, p; } sh[N]; bool cmp(node a, node b) { return a.m > b.m; } signed main() { scanf( %lld , &t); while (t--) { scanf( %lld , &n); for (long long i = 1; i <= n; i++) scanf( %lld%lld , &sh[i].m, &sh[i].p); sort(sh + 1, sh + 1 + n, cmp); long long ans = 0; priority_queue<long long, vector<long long>, greater<long long> > q; for (long long i = 1; i <= n;) { long long j = i; while (j <= n && sh[j].m == sh[i].m) { q.push(sh[j].p); j++; } while (n - (long long)q.size() < sh[i].m) { ans += q.top(); q.pop(); } i = j; } printf( %lld n , ans); } }
|
/*
Anthony De Caria - May 22, 2014
This module creates a Shift Register with a seperate enable signal.
This specific module creates an output that is 16-bits wide.
This module uses asyncronous D Flip Flops.
It also can allow data to be inputed into the flip flops before shifting.
*/
module ShiftRegisterWEnableFourteenAsyncMuxedInput(clk, resetn, enable, select, d, q);
//Define the inputs and outputs
input clk;
input resetn;
input enable;
input select;
input [13:0] d;
output [13:0] q;
wire [13:1]muxOut;
mux2to1_1bit One_mux(.data1x(d[1]), .data0x(q[0]), .sel(select), .result(muxOut[1]) );
mux2to1_1bit Two_mux(.data1x(d[2]), .data0x(q[1]), .sel(select), .result(muxOut[2]) );
mux2to1_1bit Three_mux(.data1x(d[3]), .data0x(q[2]), .sel(select), .result(muxOut[3]) );
mux2to1_1bit Four_mux(.data1x(d[4]), .data0x(q[3]), .sel(select), .result(muxOut[4]) );
mux2to1_1bit Five_mux(.data1x(d[5]), .data0x(q[4]), .sel(select), .result(muxOut[5]) );
mux2to1_1bit Six_mux(.data1x(d[6]), .data0x(q[5]), .sel(select), .result(muxOut[6]) );
mux2to1_1bit Seven_mux(.data1x(d[7]), .data0x(q[6]), .sel(select), .result(muxOut[7]) );
mux2to1_1bit Eight_mux(.data1x(d[8]), .data0x(q[7]), .sel(select), .result(muxOut[8]) );
mux2to1_1bit Nine_mux(.data1x(d[9]), .data0x(q[8]), .sel(select), .result(muxOut[9]) );
mux2to1_1bit Ten_mux(.data1x(d[10]), .data0x(q[9]), .sel(select), .result(muxOut[10]) );
mux2to1_1bit Eleven_mux(.data1x(d[11]), .data0x(q[10]), .sel(select), .result(muxOut[11]) );
mux2to1_1bit Twelve_mux(.data1x(d[12]), .data0x(q[11]), .sel(select), .result(muxOut[12]) );
mux2to1_1bit Thirteen_mux(.data1x(d[13]), .data0x(q[12]), .sel(select), .result(muxOut[13]) );
D_FF_with_Enable Zero(.clk(clk), .resetn(resetn), .enable(enable), .d(d[0]), .q(q[0]) );
D_FF_with_Enable One(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[1]), .q(q[1]) );
D_FF_with_Enable Two(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[2]), .q(q[2]) );
D_FF_with_Enable Three(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[3]), .q(q[3]) );
D_FF_with_Enable Four(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[4]), .q(q[4]) );
D_FF_with_Enable Five(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[5]), .q(q[5]) );
D_FF_with_Enable Six(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[6]), .q(q[6]) );
D_FF_with_Enable Seven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[7]), .q(q[7]) );
D_FF_with_Enable Eight(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[8]), .q(q[8]) );
D_FF_with_Enable Nine(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[9]), .q(q[9]) );
D_FF_with_Enable Ten(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[10]), .q(q[10]) );
D_FF_with_Enable Eleven(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[11]), .q(q[11]) );
D_FF_with_Enable Twelve(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[12]), .q(q[12]) );
D_FF_with_Enable Thirteen(.clk(clk), .resetn(resetn), .enable(enable), .d(muxOut[13]), .q(q[13]) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int x; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> x; if (x == 3) { cout << 5 << endl; return 0; } for (int i = 1; i <= 199; i += 2) { int temp = i * i + 1; temp /= 2; if (temp >= x) { cout << i << endl; break; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<pair<int, int> > > Mat; vector<int> Grafo; vector<int> Entrada; vector<int> Rev; vector<int> Aristas; stack<int> STACK; vector<int> Backi; int grafos; bool dfs(int A, int i, int pos) { Grafo[A] = grafos; Entrada[A] = pos; Backi[A] = pos; bool J = false; for (int I = 0; I < Mat[A].size(); I++) { if (Mat[A][I].first != i) { if (Grafo[Mat[A][I].first] == 0) { STACK.push(Mat[A][I].second); bool JJ = dfs(Mat[A][I].first, A, pos + 1); Backi[A] = min(Backi[A], Backi[Mat[A][I].first]); if (i == -1 || (i != -1 && Backi[Mat[A][I].first] >= Entrada[A])) { if (JJ) { int UU = STACK.top(); STACK.pop(); while (UU != Mat[A][I].second) { Aristas[UU] = 1; UU = STACK.top(); STACK.pop(); } Aristas[Mat[A][I].second] = 1; } else { int UU = STACK.top(); STACK.pop(); while (UU != Mat[A][I].second) { UU = STACK.top(); STACK.pop(); } } } else { if (JJ) J = JJ; } } else if (Entrada[Mat[A][I].first] < Entrada[A]) { if ((Entrada[A] - Entrada[Mat[A][I].first]) % 2 == 0) { J = true; } STACK.push(Mat[A][I].second); Backi[A] = min(Backi[A], Backi[Mat[A][I].first]); } } } return J; } int main() { int N, A, B, C; scanf( %d%d , &N, &A); Mat.resize(N); for (int I = 0; I < A; I++) { scanf( %d%d , &B, &C); B--; C--; Mat[B].push_back(make_pair(C, I)); Mat[C].push_back(make_pair(B, I)); } Backi.resize(N); Aristas.resize(A); Grafo.resize(N); grafos = 1; Entrada.resize(N); Entrada.resize(0); Entrada.resize(N); Rev.resize(N); for (int I = 0; I < N; I++) { if (Grafo[I] == 0) { bool OO = dfs(I, -1, 0); grafos++; } } vector<int> Distancias(N); vector<int> CC(N), Rev3(N); int cont = 0; int var; for (int I = 0; I < N; I++) { if (Rev3[I] == 0) { cont++; queue<int> COLA; COLA.push(I); Distancias[I] = 1; CC[I] = cont; Rev3[I] = 1; while (!COLA.empty()) { int KKK = COLA.front(); COLA.pop(); CC[KKK] = cont; Rev3[KKK] = 1; for (int I2 = 0; I2 < Mat[KKK].size(); I2++) { var = Mat[KKK][I2].first; if (Aristas[Mat[KKK][I2].second] == 0 && Rev3[var] == 0) { Distancias[var] = Distancias[KKK] + 1; COLA.push(var); Rev3[var] = 1; } } } } } int MM, AA, BB; scanf( %d , &MM); for (int I = 0; I < MM; I++) { scanf( %d%d , &AA, &BB); AA--; BB--; if (Grafo[AA] != Grafo[BB] || AA == BB) { printf( No n ); } else { if (CC[AA] != CC[BB]) printf( Yes n ); else { if ((Distancias[AA] + Distancias[BB] + 1) % 2 == 0) { printf( Yes n ); } else printf( No n ); } } } return 0; }
|
`define bsg_mux_gen_macro(words,bits) \
if (harden_p && els_p == words && width_p == bits) \
begin: macro \
wire [els_p-1:0] sel_onehot = els_p ' (1'b1 << sel_i); \
\
bsg_rp_tsmc_40_mux_w``words``_b``bits w``words``_b``bits \
(.* \
, .sel_one_hot_i(sel_onehot) \
); \
end
`define bsg_mux4_balanced_gen_macro(BITS) \
if (balanced_p && harden_p && (els_p==4)) \
begin: macro \
wire [width_p-1:0] lo; \
\
/* A B C D S0 S1 Y S1 S0 */ \
bsg_rp_tsmc_40_MUX4ND4BWP_b``BITS b``BITS``_m (.i0 (data_i[0]) /* 0 0 A */ \
,.i1(data_i[1]) /* 0 1 B */ \
,.i2(data_i[2]) /* 1 0 C */ \
,.i3(data_i[3]) /* 1 1 D */ \
,.i4(sel_i[0] ) /* S0 */ \
,.i5(sel_i[1] ) /* S1 */ \
,.o (lo ) \
); \
bsg_rp_tsmc_40_CKND16BWP_b``BITS b``BITS``_i(.i0(lo) \
,.o(data_o) \
); \
end
module bsg_mux #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
, balanced_p=0
, lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [lg_els_lp-1:0] sel_i
,output [width_p-1:0] data_o
);
`bsg_mux4_balanced_gen_macro(1)
else `bsg_mux_gen_macro(2,33)
else `bsg_mux_gen_macro(2,32)
else `bsg_mux_gen_macro(2,30)
else `bsg_mux_gen_macro(2,29)
else `bsg_mux_gen_macro(2,20)
else `bsg_mux_gen_macro(2,19)
else `bsg_mux_gen_macro(2,18)
else `bsg_mux_gen_macro(2,17)
else `bsg_mux_gen_macro(2,16)
else `bsg_mux_gen_macro(2,15)
else `bsg_mux_gen_macro(2,14)
else `bsg_mux_gen_macro(2,13)
else `bsg_mux_gen_macro(2,12)
else `bsg_mux_gen_macro(2,11)
else `bsg_mux_gen_macro(2,10)
else `bsg_mux_gen_macro(2,9)
else `bsg_mux_gen_macro(2,8)
else `bsg_mux_gen_macro(2,7)
else `bsg_mux_gen_macro(2,6)
else `bsg_mux_gen_macro(2,5)
else `bsg_mux_gen_macro(2,4)
else `bsg_mux_gen_macro(2,3)
else `bsg_mux_gen_macro(2,2)
else `bsg_mux_gen_macro(2,1)
else `bsg_mux_gen_macro(4,32)
else
begin: notmacro
initial assert (harden_p==0) else $error("## %m: warning, failed to harden bsg_mux width=%d, els=%d, balanced=%d",width_p, els_p, balanced_p);
if (els_p == 1) begin
assign data_o = data_i;
wire unused = sel_i;
end
else begin
assign data_o = data_i[sel_i];
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mux)
|
#include <bits/stdc++.h> using namespace std; int main() { int s1, s2, s3, a, b, c; cin >> s1 >> s2 >> s3; a = (s1 * s2) / s3; a = pow(a, 0.5); b = (s2 * s3) / s1; b = pow(b, 0.5); c = (s1 * s3) / s2; c = pow(c, 0.5); cout << 4 * (a + b + c) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T getint() { T x = 0, p = 1; char ch; do { ch = getchar(); } while (ch <= ); if (ch == - ) p = -1, ch = getchar(); while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * p; } mt19937 gen(chrono::system_clock::now().time_since_epoch().count()); template <typename T1, typename T2> bool umin(T1 &x, const T2 &y) { if (x > y) return x = y, true; return false; } template <typename T1, typename T2> bool umax(T1 &x, const T2 &y) { if (x < y) return x = y, true; return false; } const int maxn = (int)3e5 + 10; const int inf = (int)1e9 + 5; const int mod = (int)1e9 + 7; const long long llinf = (long long)1e18 + 5; const long double pi = acos(-1.0); int nxt[maxn * 30][2]; int f[maxn * 30]; int sz = 1; int v[maxn], t[maxn]; void add(int x, int d) { int v = 1; for (int i = 29; i >= 0; --i) { int b = (x >> i & 1); if (nxt[v][b] == 0) nxt[v][b] = ++sz; v = nxt[v][b]; f[v] += d; } } int get(int x) { int v = 1; int res = 0; for (int i = 29; i >= 0; --i) { int b = (x >> i & 1); if (f[nxt[v][b]] > 0) { v = nxt[v][b]; } else { res |= 1 << i; v = nxt[v][b ^ 1]; } } return res; } int main() { ios_base::sync_with_stdio(0); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> v[i]; } for (int i = 1; i <= n; ++i) { cin >> t[i]; add(t[i], 1); } for (int i = 1; i <= n; ++i) { int z = get(v[i]); cout << z << ; add(z ^ v[i], -1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 1; const long long M = 1e5 + 1; vector<int> len; vector<int> dist[N]; vector<long long> pre[N]; long long n, m; void mer(long long v, long long l, long long addl, long long r, long long addr) { dist[v].push_back(0); long long sl = dist[l].size(); long long sr = dist[r].size(); long long pl = 0; long long pr = 0; while (pl < sl && pr < sr) { if (dist[l][pl] + addl <= dist[r][pr] + addr) { dist[v].push_back(dist[l][pl] + addl); pl++; } else { dist[v].push_back(dist[r][pr] + addr); pr++; } } while (pl < sl) { dist[v].push_back(dist[l][pl] + addl); pl++; } while (pr < sr) { dist[v].push_back(dist[r][pr] + addr); pr++; } return; } void bfs(long long v) { if (v > n) return; long long l = 2 * v; long long r = 2 * v + 1; bool cl = false, cr = false; if (l <= n) { bfs(l); cl = true; } if (r <= n) { bfs(r); cr = true; } if (cl && cr) { long long addl = len[2 * v - 1]; long long addr = len[2 * v]; mer(v, l, addl, r, addr); } else if (cl && !cr) { long long addl = len[2 * v - 1]; dist[v].push_back(0); for (long long x : dist[l]) dist[v].push_back(addl + x); } else if (cr && !cl) { long long addr = len[2 * v]; dist[v].push_back(0); for (long long x : dist[r]) dist[v].push_back(addr + x); } else { dist[v].push_back(0); } long long sze = dist[v].size(); pre[v].resize(sze); long long prev = 0ll; for (long long i = 0; i < sze; i++) { pre[v][i] = prev + dist[v][i]; prev = pre[v][i]; } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); len.push_back(-1); cin >> n >> m; for (long long i = 0; i < n - 1; i++) { long long x; cin >> x; len.push_back(x); } bfs(1); for (long long i = 0; i < m; i++) { long long ans = 0ll; long long a, h; cin >> a >> h; long long opt = 3; while (a >= 1) { if (h < 0) break; if (opt == 3) { long long cnt = (upper_bound(dist[a].begin(), dist[a].end(), h) - dist[a].begin()); if (cnt > 0) ans += (cnt)*h - pre[a][cnt - 1]; } else if (opt == 2) { ans += h; if (2 * a <= n) { long long cnt = (upper_bound(dist[2 * a].begin(), dist[2 * a].end(), h - len[2 * a - 1]) - dist[2 * a].begin()); if (cnt > 0) ans += (cnt) * (h - len[2 * a - 1]) - pre[2 * a][cnt - 1]; } } else { if (h > 0) ans += h; if (2 * a + 1 <= n) { long long cnt = (upper_bound(dist[2 * a + 1].begin(), dist[2 * a + 1].end(), h - len[2 * a]) - dist[2 * a + 1].begin()); if (cnt > 0) ans += (cnt) * (h - len[2 * a]) - pre[2 * a + 1][cnt - 1]; } } if (a % 2) { h -= len[2 * (a / 2)]; opt = 2; } else { h -= len[2 * (a / 2) - 1]; opt = 1; } a /= 2; } cout << ans << endl; } }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; using ii = pair<int, int>; using ll = long long; const int mod = 1e9 + 7; const int N = 1e6 + 5; const int M = 29; int ans[N]; int dp[3][N]; struct suffixAutomaton { struct state { int len; int link; int next[M]; ll cnt; bool terminal; state() { len = 0, link = -1, cnt = 0; terminal = false; for (int i = 0; i < M; i++) next[i] = -1; } }; int get(char c) { if (c == @ ) return 0; if (c == # ) return 1; if (c == $ ) return 2; return 3 + c - a ; } vector<state> st; int sz, last, l; char offset = a ; suffixAutomaton() {} int pos[3]; int getLen(int x) { if (~x) return st[x].len; return 0; } suffixAutomaton(string s) { int l = s.length(); st.resize(2 * l); for (int i = 0; i < 2 * l; i++) st[i] = state(); sz = 1, last = 0; st[0].len = 0; st[0].link = -1; for (int i = 0; i < l; i++) { addChar(get(s[i])); } for (int i = last; i != -1; i = st[i].link) st[i].terminal = true; vector<vector<int>> adj(2 * l); memset(dp, -1, sizeof dp); for (int i = 0; i < sz; i++) { ans[getLen(st[i].link) + 1] += solve(0, i) * 1ll * solve(1, i) * 1ll * solve(2, i) % mod; ans[getLen(i) + 1] -= solve(0, i) * 1ll * solve(1, i) * 1ll * solve(2, i) % mod; if (ans[getLen(st[i].link) + 1] >= mod) ans[getLen(st[i].link) + 1] -= mod; if (ans[getLen(i) + 1] < 0) ans[getLen(i) + 1] += mod; } } int solve(int f, int idx) { if (idx == pos[f]) return 1; if (idx == pos[0] || idx == pos[1] || idx == pos[2]) return 0; int &ret = dp[f][idx]; if (~ret) return ret; ret = 0; for (int i = 0; i < M; i++) if (~st[idx].next[i]) { ret += solve(f, st[idx].next[i]); if (ret >= mod) ret -= mod; } return ret; } void addChar(int c) { int cur = sz++; assert(cur < N * 2); if (c < 3) pos[c] = cur; st[cur].len = st[last].len + 1; st[cur].cnt = 1; int p = last; while (p != -1 and st[p].next[c] == -1) { st[p].next[c] = cur; p = st[p].link; } last = cur; if (p == -1) { st[cur].link = 0; return; } int q = st[p].next[c]; if (st[q].len == st[p].len + 1) { st[cur].link = q; return; } int clone = sz++; for (int i = 0; i < M; i++) st[clone].next[i] = st[q].next[i]; st[clone].link = st[q].link; st[clone].len = st[p].len + 1; st[clone].cnt = 0; while (p != -1 and st[p].next[c] == q) { st[p].next[c] = clone; p = st[p].link; } st[q].link = st[cur].link = clone; return; } bool contains(string &t) { int cur = 0; for (int i = 0; i < t.length(); i++) { cur = st[cur].next[t[i] - offset]; if (cur == -1) return false; } return true; } ll numberOfSubstrings() { ll res = 0; for (int i = 1; i < sz; i++) res += st[i].len - st[st[i].link].len; return res; } void numberOfOccPreprocess() { vector<ii> v; for (int i = 1; i < sz; i++) v.push_back(make_pair(st[i].len, i)); sort(v.begin(), v.end(), greater<ii>()); for (int i = 0; i < sz - 1; i++) { int suf = st[v[i].second].link; st[suf].cnt += st[v[i].second].cnt; } } ll numberOfOcc(string &t) { int cur = 0; for (int i = 0; i < t.length(); i++) { cur = st[cur].next[t[i] - offset]; if (cur == -1) return 0; } return st[cur].cnt; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); string a, b, c; cin >> a >> b >> c; suffixAutomaton SA(a + @ + b + # + c + $ ); int mn = min(a.size(), min(b.size(), c.size())); int cur = 0; for (int i = 1; i <= mn; i++) { cur += ans[i]; if (cur >= mod) cur -= mod; if (cur < 0) cur += mod; cout << cur << ; } return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200,
parameter break_en_default = 1'b0
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output irq,
input uart_rx,
output uart_tx,
output break
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire uart_tx_transceiver;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data),
.tx_wr(tx_wr),
.tx_done(tx_done),
.break(break_transceiver)
);
assign uart_tx = thru_en ? uart_rx : uart_tx_transceiver;
assign break = break_en & break_transceiver;
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
assign irq = (tx_event & tx_irq_en) | (rx_event & rx_irq_en);
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[2:0] == 3'b000);
parameter default_divisor = clk_freq/baud/16;
reg thru_en;
reg break_en;
reg tx_irq_en;
reg rx_irq_en;
reg rx_event;
reg tx_event;
reg thre;
always @(posedge sys_clk) begin
if(sys_rst) begin
divisor <= default_divisor;
csr_do <= 32'd0;
thru_en <= 1'b0;
break_en <= break_en_default;
rx_irq_en <= 1'b0;
tx_irq_en <= 1'b0;
tx_event <= 1'b0;
rx_event <= 1'b0;
thre <= 1'b1;
end else begin
csr_do <= 32'd0;
if(break)
break_en <= 1'b0;
if(tx_done) begin
tx_event <= 1'b1;
thre <= 1'b1;
end
if(tx_wr)
thre <= 1'b0;
if(rx_done) begin
rx_event <= 1'b1;
end
if(csr_selected) begin
case(csr_a[2:0])
3'b000: csr_do <= rx_data;
3'b001: csr_do <= divisor;
3'b010: csr_do <= {tx_event, rx_event, thre};
3'b011: csr_do <= {thru_en, tx_irq_en, rx_irq_en};
3'b100: csr_do <= {break_en};
endcase
if(csr_we) begin
case(csr_a[2:0])
3'b000:; /* handled by transceiver */
3'b001: divisor <= csr_di[15:0];
3'b010: begin
/* write one to clear */
if(csr_di[1])
rx_event <= 1'b0;
if(csr_di[2])
tx_event <= 1'b0;
end
3'b011: begin
rx_irq_en <= csr_di[0];
tx_irq_en <= csr_di[1];
thru_en <= csr_di[2];
end
3'b100: break_en <= csr_di[0];
endcase
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Compteur { int nbs[4]; Compteur() { for (int iCoeff = 0; iCoeff < 4; iCoeff++) { nbs[iCoeff] = 0; } } }; Compteur operator+(const Compteur &a, const Compteur &b) { Compteur nouv; for (int iCoeff = 0; iCoeff < 4; iCoeff++) { nouv.nbs[iCoeff] = a.nbs[iCoeff] + b.nbs[iCoeff]; } return nouv; } int getP2(int a) { int s = 1; while (s < a) { s *= 2; } return s; } vector<Compteur> arbres[10][10]; void modif(vector<Compteur> &a, int pos, Compteur val) { pos += (int)a.size() / 2; while (pos != 0) { a[pos] = a[pos] + val; pos /= 2; } } Compteur getSomme(vector<Compteur> &a, int deb, int fin) { deb += (int)a.size() / 2; fin += (int)a.size() / 2; Compteur somme; while (deb < fin) { if (deb % 2 == 1) { somme = somme + a[deb]; deb++; } if (fin % 2 == 1) { fin--; somme = somme + a[fin]; } deb /= 2; fin /= 2; } return somme; } int conv[256]; int main() { string chaine; cin >> chaine; conv[ A ] = 0; conv[ T ] = 1; conv[ G ] = 2; conv[ C ] = 3; for (int iTaille = 1; iTaille <= 10; iTaille++) { for (int iMod = 0; iMod < iTaille; iMod++) { arbres[iTaille - 1][iMod] = vector<Compteur>( 2 * getP2((chaine.size() + iTaille) / iTaille), Compteur()); } } for (int iCar = 0; iCar < chaine.size(); iCar++) { Compteur nouv; nouv.nbs[conv[chaine[iCar]]]++; for (int iTaille = 1; iTaille <= 10; iTaille++) { int mod = iCar % iTaille; int pos = iCar / iTaille; modif(arbres[iTaille - 1][mod], pos, nouv); } } int nbReqs; cin >> nbReqs; for (int iReq = 0; iReq < nbReqs; iReq++) { int type; cin >> type; if (type == 1) { int iCar; char val; cin >> iCar >> val; iCar--; Compteur nouv; nouv.nbs[conv[val]]++; nouv.nbs[conv[chaine[iCar]]]--; for (int iTaille = 1; iTaille <= 10; iTaille++) { int mod = iCar % iTaille; int pos = iCar / iTaille; modif(arbres[iTaille - 1][mod], pos, nouv); } chaine[iCar] = val; } else { int deb, fin; string comp; cin >> deb >> fin >> comp; deb--; int iTaille = comp.size(); int somme = 0; for (int iMod = 0; iMod < iTaille; iMod++) { int mod = (deb + iMod) % iTaille; int debPos = (deb + iMod) / iTaille; int finPos = (fin - iTaille) / iTaille; while (finPos * iTaille + mod < fin) { finPos++; } Compteur vals = getSomme(arbres[iTaille - 1][mod], debPos, finPos); somme += vals.nbs[conv[comp[iMod]]]; } cout << somme << endl; } } }
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cmd_seq #(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1,
parameter CMD_MEM_SIZE = 2048
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output wire CMD_READY,
output wire CMD_START_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
cmd_seq_core #(
.CMD_MEM_SIZE(CMD_MEM_SIZE),
.ABUSWIDTH(ABUSWIDTH),
.OUTPUTS(OUTPUTS)
) i_cmd_seq_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(CMD_CLK_IN),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(CMD_EXT_START_ENABLE),
.CMD_DATA(CMD_DATA),
.CMD_READY(CMD_READY),
.CMD_START_FLAG(CMD_START_FLAG)
);
endmodule
|
#include <bits/stdc++.h> constexpr int Maxn = 53; std::vector<int> e[Maxn]; int n, m; int main() { scanf( %d%d , &n, &m); for (int i = 1, u, v; i <= m; ++i) { scanf( %d%d , &u, &v); if (u <= 50 && v <= 50) { e[u].emplace_back(v); e[v].emplace_back(u); } } n = std::min(n, 50); for (int i = 1; i <= n; ++i) std::sort(e[i].begin(), e[i].end()); for (int i = 1; i <= n; ++i) for (int j = 1; j < i; ++j) for (int k = 1; k < j; ++k) for (int l = 1; l < k; ++l) for (int r = 1; r < l; ++r) { std::vector<int> vec = {i, j, k, l, r}; int cnt = 0; for (int x : {0, 1, 2, 3, 4}) for (int y = 0; y < x; ++y) { auto iter = std::lower_bound(e[vec[x]].begin(), e[vec[x]].end(), vec[y]); if (iter == e[vec[x]].end() || *iter != vec[y]) ++cnt; } if (cnt == 0 || cnt == 10) { printf( %d %d %d %d %d n , i, j, k, l, r); return 0; } } puts( -1 ); }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e11; const int M = 1e5 + 5; vector<pair<long long, int> > adj[M]; vector<int> ans; long long d[M], vis[M], pre[M]; int n, m; void Dijkstra() { for (int i = 1; i <= n; ++i) d[i] = INF; d[1] = 0; priority_queue<pair<long long, int> > q; q.push(make_pair(d[1], 1)); while (!q.empty()) { int u = q.top().second; q.pop(); if (vis[u]) continue; vis[u] = 1; for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i].second; long long dist = adj[u][i].first + d[u]; if (d[v] > dist) { d[v] = dist; pre[v] = u; q.push(make_pair(-d[v], v)); } } } } int main() { int u, v, w; cin >> n >> m; while (m--) { cin >> u >> v >> w; adj[u].push_back(make_pair(w, v)); adj[v].push_back(make_pair(w, u)); } Dijkstra(); if (d[n] == INF) cout << -1 << endl; else { for (int i = n; pre[i]; i = pre[i]) ans.push_back(pre[i]); for (int i = ans.size() - 1; i >= 0; --i) cout << ans[i] << ; cout << n << ; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int r, c, i, j, flag = 0; cin >> r >> c; char a[r + 2][c + 2]; for (i = 0; i < (r + 2); i++) { for (j = 0; j < (c + 2); j++) a[i][j] = . ; } for (i = 1; i < (r + 1); i++) { for (j = 1; j < (c + 1); j++) { cin >> a[i][j]; } } for (i = 1; i < (r + 1); i++) { for (j = 1; j < (c + 1); j++) { if (a[i][j] == S ) { if (a[i + 1][j] == W || a[i][j + 1] == W || a[i - 1][j] == W || a[i][j - 1] == W ) { flag = 1; cout << No n ; break; } } } if (flag == 1) break; } if (flag == 0) { cout << Yes n ; for (i = 1; i < (r + 1); i++) { for (j = 1; j < (c + 1); j++) { if (a[i][j] == . ) cout << D ; else cout << a[i][j]; } cout << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int n; cin >> n; int a[n], i, j, k, l, m; string s, temp; for (i = 0; i < n; i++) cin >> a[i]; char c = a , d; for (i = 0; i <= 50; i++) { s += a ; } cout << s << endl; for (i = 0; i < n; i++) { k = a[i]; temp = 0 ; for (j = 0; j < k; j++) { temp += s[j]; c = s[j]; } for (j = k; j <= 50; j++) { if (s[j] != z ) { d = s[j] + 1; } else { d = a ; } temp += d; } s = temp; cout << temp << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRBN_PP_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_PP_SYMBOL_V
|
`define ADDER_WIDTH 021
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule
|
// A few simple tests of translating parameters to generics
module top();
wire [7:0] v1, v2, v3;
wire [7:0] w1, w2, w3;
child c1(v1, w1);
child c2(v2, w2);
child c3(v3, w3);
defparam c1.MY_VALUE = 6;
defparam c2.MY_VALUE = 44;
initial begin
#2;
$display("c1 reg value: %d", v1);
$display("c2 reg value: %d", v2);
$display("c3 reg value: %d", v3);
$display("c1 wire value: %d", w1);
$display("c2 wire value: %d", w2);
$display("c3 wire value: %d", w3);
if (v1 !== 6)
$display("FAILED - v1 !== 6");
else if (v2 !== 44)
$display("FAILED - v2 !== 44");
else if (v3 !== 12)
$display("FAILED - v3 !== 12");
else if (w1 !== 7)
$display("FAILED - v1 !== 7");
else if (w2 !== 45)
$display("FAILED - v2 !== 45");
else if (w3 !== 13)
$display("FAILED - v3 !== 13");
else
$display("PASSED");
end
endmodule // top
module child(value, value_w);
output [7:0] value, value_w;
reg [7:0] value;
parameter MY_VALUE = 12;
assign value_w = MY_VALUE + 1;
// Make a non-trivial process
initial begin
#1;
value <= MY_VALUE;
end
endmodule // child
|
#include <bits/stdc++.h> using namespace std; int to[55][35][35][4][3]; int dx[] = {0, 1, 0, -1}; int dy[] = {1, 0, -1, 0}; int Sign(int x) { return x > 0 ? 1 : x < 0 ? -1 : 0; } int main() { int n, b; cin >> n >> b; ++b; for (int i = 0; i < b; ++i) { for (int j = 0; j < b; ++j) { for (int d = 0; d < 4; ++d) { int nx = i + dx[d], ny = j + dy[d]; to[0][i][j][d][0] = nx; to[0][i][j][d][1] = ny; to[0][i][j][d][2] = d; } } } for (int i = 0; i < n; ++i) { int x0, y0, x1, y1; cin >> x0 >> y0 >> x1 >> y1; int dx = Sign(x1 - x0), dy = Sign(y1 - y0); int dd = 0; for (int j = 0; j < 4; ++j) { if (dx == ::dx[j] && dy == ::dy[j]) { dd = j; break; } } while (x0 != x1 || y0 != y1) { for (int j = 0; j < 4; ++j) { to[0][x0][y0][j][0] = x0 + dx; to[0][x0][y0][j][1] = y0 + dy; to[0][x0][y0][j][2] = dd; } x0 += dx; y0 += dy; } for (int j = 0; j < 4; ++j) { to[0][x0][y0][j][0] = x0 + dx; to[0][x0][y0][j][1] = y0 + dy; to[0][x0][y0][j][2] = dd; } } for (int i = 1; i < 55; ++i) { for (int x = 0; x < b; ++x) { for (int y = 0; y < b; ++y) { for (int j = 0; j < 4; ++j) { int nx = to[i - 1][x][y][j][0], ny = to[i - 1][x][y][j][1], dd = to[i - 1][x][y][j][2]; if (nx < 0 || nx >= b || ny < 0 || ny >= b) { to[i][x][y][j][0] = nx; to[i][x][y][j][1] = ny; to[i][x][y][j][2] = -1; } else { to[i][x][y][j][0] = to[i - 1][nx][ny][dd][0]; to[i][x][y][j][1] = to[i - 1][nx][ny][dd][1]; to[i][x][y][j][2] = to[i - 1][nx][ny][dd][2]; } } } } } int q; cin >> q; for (int i = 0; i < q; ++i) { int x, y; char d; long long t; cin >> x >> y >> d >> t; int dir = 0; if (d == L ) { dir = 3; } else if (d == R ) { dir = 1; } else if (d == D ) { dir = 2; } else { dir = 0; } for (int j = 0; t; ++j, t >>= 1) { if (t & 1) { int nx = to[j][x][y][dir][0]; int ny = to[j][x][y][dir][1]; dir = to[j][x][y][dir][2]; x = nx; y = ny; } if (x < 0 || x >= b || y < 0 || y >= b) { break; } } x = max(0, min(x, b - 1)); y = max(0, min(y, b - 1)); cout << x << << y << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, Cnt = 0, Num = 0; int l[200000 + 10], r[200000 + 10]; map<int, int> mp; int Di[200000 + 10]; vector<int> f[200000 + 10], No[200000 + 10]; int cur[200000 + 10]; bool b[200000 + 10]; int Ans[200000 + 10]; int Check() { int Now = -1, ODD = 0; for (int i = 1; i <= Cnt; i++) if (f[i].size() % 2 == 1) { ODD++; Now = i; } if (ODD == 2) return Now; if (ODD == 0) return 1; return -1; } void Euler(int x) { for (int i = cur[x]; i < f[x].size(); i = cur[x]) { cur[x] = i + 1; if (b[No[x][i]]) continue; b[No[x][i]] = true; Euler(f[x][i]); } Ans[++Ans[0]] = x; } int main() { scanf( %d , &n); n--; for (int i = 1; i <= n; i++) scanf( %d , &l[i]); for (int i = 1; i <= n; i++) scanf( %d , &r[i]); int x, y; for (int i = 1; i <= n; i++) { if (l[i] > r[i]) return printf( -1 ), 0; if (!mp.count(l[i])) x = mp[l[i]] = ++Cnt, Di[Cnt] = l[i]; else x = mp[l[i]]; if (!mp.count(r[i])) y = mp[r[i]] = ++Cnt, Di[Cnt] = r[i]; else y = mp[r[i]]; Num++; f[x].push_back(y); No[x].push_back(Num); f[y].push_back(x); No[y].push_back(Num); } int Begin = Check(); if (Begin == -1) return printf( -1 ), 0; Euler(Begin); if (Ans[0] != n + 1) return printf( -1 ), 0; for (int i = n + 1; i; i--) printf( %d , Di[Ans[i]]); return 0; }
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 02-15-2007
module vga_driver (
r,g,b,
current_x,current_y,request,
vga_r,vga_g,vga_b,vga_hs,vga_vs,vga_blank,vga_clock,
clk27,rst27);
input [9:0] r,g,b;
output [9:0] current_x;
output [9:0] current_y;
output request;
output [9:0] vga_r, vga_g, vga_b;
output vga_hs, vga_vs, vga_blank, vga_clock;
input clk27, rst27;
////////////////////////////////////////////////////////////
// Horizontal Timing
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
// Vertical Timing
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
reg [9:0] h_cntr, v_cntr, current_x, current_y;
reg h_active, v_active, vga_hs, vga_vs;
assign vga_blank = h_active & v_active;
assign vga_clock = ~clk27;
assign vga_r = r;
assign vga_g = g;
assign vga_b = b;
assign request = ((h_cntr>=H_BLANK && h_cntr<H_TOTAL) &&
(v_cntr>=V_BLANK && v_cntr<V_TOTAL));
always @(posedge clk27) begin
if(rst27) begin
h_cntr <= 0;
v_cntr <= 0;
vga_hs <= 1'b1;
vga_vs <= 1'b1;
current_x <= 0;
current_y <= 0;
h_active <= 1'b0;
v_active <= 1'b0;
end
else begin
if(h_cntr != H_TOTAL) begin
h_cntr <= h_cntr + 1'b1;
if (h_active) current_x <= current_x + 1'b1;
if (h_cntr == H_BLANK-1) h_active <= 1'b1;
end
else begin
h_cntr <= 0;
h_active <= 1'b0;
current_x <= 0;
end
if(h_cntr == H_FRONT-1) begin
vga_hs <= 1'b0;
end
if (h_cntr == H_FRONT+H_SYNC-1) begin
vga_hs <= 1'b1;
if(v_cntr != V_TOTAL) begin
v_cntr <= v_cntr + 1'b1;
if (v_active) current_y <= current_y + 1'b1;
if (v_cntr == V_BLANK-1) v_active <= 1'b1;
end
else begin
v_cntr <= 0;
current_y <= 0;
v_active <= 1'b0;
end
if(v_cntr == V_FRONT-1) vga_vs <= 1'b0;
if(v_cntr == V_FRONT+V_SYNC-1) vga_vs <= 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500005; int ult; int cont; int prim; char cad[MAXN]; bool Solve(int a, int n, int T) { int c = 0, time = 0; queue<int> s; prim = -1; for (int i = 0; i < n && c < cont; i++, time++) { if (cad[i] == H && a > 0) { c++; a--; if (prim == -1) prim = i; } else if (cad[i] == H ) { s.push(i); if (prim == -1) prim = i; } else if (cad[i] == S ) { a++; if (a >= s.size()) { if (!s.empty()) { int aux = abs(s.front() - i); time += aux; s.pop(); a--; c++; while (!s.empty()) { c++; a--; s.pop(); } if (c < cont) time += aux; } } } if (c == cont) ult = i; } time = min(time, ult + 1 + (ult - prim)); return (time <= T && c == cont); } int main() { int n; long long int T; scanf( %d %lld , &n, &T); scanf( n%s , cad); for (int i = 0; i < n; i++) if (cad[i] == H ) cont++; int ini = 0, fin = cont; while (ini < fin) { int med = (ini + fin) / 2; if (!Solve(med, n, T)) ini = med + 1; else fin = med; } if (Solve(ini, n, T)) printf( %d n , ini); else printf( -1 n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, b, x, q, t, ans, l, r, m, p, now, sum; bool ok; string s; map<int, int> a, pos; map<char, int> c; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> q; while (q--) { cin >> n >> m; cin >> s; for (int i = 1; i <= m; ++i) { cin >> x; a[x + 1]++; } sum = m + 1; for (int i = 0; i < s.size(); ++i) { sum -= a[i + 1]; c[s[i]] += sum; } for (char j = a ; j <= z ; ++j) { cout << c[j] << ; } cout << n ; a.clear(); c.clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; vector<int> *mapo; long long Montgomery(long long a, long long b) { long long ans = 1; a = a % mod; while (b > 0) { if (b & 1) ans = ans * a % mod; b >>= 1; a = a * a % mod; } return ans; } bool inQueue[size_t(3e5 + 10)]; int status[size_t(3e5 + 10)]; long long dfs_detect_possibility(int, int); int main() { int t; scanf( %d , &t); for (int i = 0; i < t; ++i) { int n, m; scanf( %d%d , &n, &m); fill(inQueue, inQueue + n + 2, false); fill(status, status + n + 2, -1); vector<int> links[n + 1]; mapo = links; for (int j = 0; j < m; ++j) { int t1, t2; scanf( %d%d , &t1, &t2); links[t1].push_back(t2); links[t2].push_back(t1); } long long ans = 1; for (int j = 1; j <= n; j++) { if (inQueue[j]) continue; ans = ans * dfs_detect_possibility(n, j) % mod; } cout << ans << endl; } return 0; } long long dfs_detect_possibility(int n, int st) { int same = 1; status[st] = 1; queue<int> q; q.push(st); inQueue[st] = true; long long dans = 1; int cnt = 1; while (!q.empty()) { int poi = q.front(); q.pop(); for (int &i : mapo[poi]) { if (status[i] == status[poi]) { return 0; } else if (status[i] == -1) { cnt++; if (status[poi] == 1) status[i] = 0; else { status[i] = 1; same++; } q.push(i); inQueue[i] = true; } } } dans = Montgomery(2, same) + Montgomery(2, cnt - same); return dans % mod; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_SYMBOL_V
`define SKY130_FD_SC_MS__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; set<long long int> s; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > 0) { s.insert(a[i]); } } long long int len1 = s.size(); cout << len1 << endl; return 0; }
|
`timescale 1 ns / 1 ps
module sensor_interface_v1_0 #
(
// Users to add parameters here
parameter integer C_SYSTEM_CLOCK = 100_000_000,
parameter integer C_BUS_CLOCK = 400_000,
// User parameters ends
// THESE AREN'T USER CONFIGURABLE
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 8
)
(
// Users to add ports here
// I2C interface ports
input wire m00_iic_scl_i,
output wire m00_iic_scl_o,
output wire m00_iic_scl_t,
input wire m00_iic_sda_i,
output wire m00_iic_sda_o,
output wire m00_iic_sda_t,
input wire sync,
output wire interrupt,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
wire mm_en;
wire mm_wr;
wire [C_S00_AXI_ADDR_WIDTH-1:0] mm_addr;
wire [C_S00_AXI_DATA_WIDTH-1:0] mm_rdata;
// Instantiation of Axi Bus Interface S00_AXI
sensor_interface_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) sensor_interface_v1_0_S00_AXI_inst (
// Memory mapped interface
.clk(s00_axi_aclk),
.mm_en(mm_en),
.mm_wr(mm_wr),
.mm_addr(mm_addr),
.mm_rdata(mm_rdata),
// AXI interface
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
wire i2c_en;
wire [6:0] i2c_addr;
wire i2c_write;
wire [7:0] i2c_wdata;
wire [7:0] i2c_rdata;
wire i2c_act;
wire i2c_err;
wire i2c_next;
wire i2c_multibyte_n;
sensor_control #(
.C_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.C_SYSTEM_CLOCK(C_SYSTEM_CLOCK)
) sensor_control_inst(
// Device
.clk(s00_axi_aclk),
.rst_n(s00_axi_aresetn),
.sync(sync),
.interrupt(interrupt),
// Memory mapped interface
.mm_en(mm_en),
.mm_wr(mm_wr),
.mm_addr(mm_addr[C_S00_AXI_ADDR_WIDTH-1:2]),
.mm_rdata(mm_rdata),
// I2C interface
.en(i2c_ena),
.addr(i2c_addr),
.write(i2c_write),
.wdata(i2c_wdata),
.rdata(i2c_rdata),
.act(i2c_act),
.err(i2c_err),
.next(i2c_next),
.multibyte_n(i2c_multibyte_n)
);
i2c_master #
(
.SYSTEM_CLOCK(C_SYSTEM_CLOCK),
.BUS_CLOCK(C_BUS_CLOCK)
)
I2C_master_inst
(
.clk(s00_axi_aclk),
.rst_n(s00_axi_aresetn),
.en(i2c_ena),
.addr(i2c_addr),
.write(i2c_write),
.wdata(i2c_wdata),
.rdata(i2c_rdata),
.act(i2c_act),
.err(i2c_err),
.next(i2c_next),
.multibyte_n(i2c_multibyte_n),
.sda_i(m00_iic_sda_i),
.sda_o(m00_iic_sda_o),
.sda_t(m00_iic_sda_t),
.scl_i(m00_iic_scl_i),
.scl_o(m00_iic_scl_o),
.scl_t(m00_iic_scl_t)
);
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[60002][10]; int main() { int n, m; scanf( %d%d , &n, &m); int a; for (int j = 0; j < m; j++) { cin >> a; if (!j) dp[0][j] = a; else dp[0][j] = dp[0][j - 1] + a; } cout << dp[0][m - 1] << ; for (int i = 1; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a; if (!j) dp[i][j] = dp[i - 1][j] + a; else { if (dp[i - 1][j] >= dp[i][j - 1]) dp[i][j] = dp[i - 1][j] + a; else dp[i][j] = dp[i][j - 1] + a; } } cout << dp[i][m - 1] << ; } }
|
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 10; vector<int> e[N], b[N], d[N]; bool v[N], in[N]; void dfs(int root, int parent, int depth) { v[root] = true, in[root] = true; d[depth].push_back(root); for (auto child : e[root]) { if (in[child]) b[root].push_back(child); if (!v[child]) dfs(child, root, depth + 1); } in[root] = false; } int main() { int n, m; scanf( %d%d , &n, &m); if (m & 1) return puts( No solution ), 0; for (int i = 0, x, y; i < m; ++i) { scanf( %d%d , &x, &y); e[x].push_back(y), e[y].push_back(x); } dfs(1, -1, 0); for (int t = n - 1, i; t >= 0; --t) { for (auto x : d[t]) { int sz = (int)b[x].size(); for (i = sz - 1; i >= 1; i -= 2) printf( %d %d %d n , b[x][i], x, b[x][i - 1]); if (sz & 1) b[b[x][0]].push_back(x); } } return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (lin64) Build Thu Jun 15 18:39:10 MDT 2017
// Date : Fri Jun 23 10:02:11 2017
// Host : dshwdev running 64-bit Ubuntu 16.04.2 LTS
// Command : write_verilog -force -mode funcsim
// /home/h-ishihara/workspace/FPGAMAG18/FPGA/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module clk_wiz_0
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
clk_wiz_0_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0_clk_wiz_0_clk_wiz
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(30.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ps
`default_nettype none
`ifndef VCDFILE
`define VCDFILE "testbench_lcu_tb.vcd"
`endif
module tb;
`include "../../../../library/tbassert.v"
// ============================================================================
reg clk;
reg thresh_sw;
reg [31:0] threshold, threshold_down, counter, counter_down;
initial clk <= 1'd0;
initial thresh_sw <= 1'd0;
initial threshold <= 32'd0;
initial threshold_down <= 32'd0;
initial counter <= 32'd0;
initial counter_down <= 32'd0;
always #5 clk <= !clk;
always #500 thresh_sw <= !thresh_sw;
initial begin
$dumpfile(`VCDFILE);
$dumpvars;
#500000 $finish();
end
// ============================================================================
// DUT
wire gtu, gts, ltu, lts, geu, ges, leu, les, zero, max;
wire gtu_n, gts_n, ltu_n, lts_n, geu_n, ges_n, leu_n, les_n, zero_n, max_n;
top dut
(
.count (clk),
.count_sw (thresh_sw),
.thresh_sw (thresh_sw),
.gtu (gtu),
.gts (gts),
.ltu (ltu),
.lts (lts),
.geu (geu),
.ges (ges),
.leu (leu),
.les (les),
.zero (zero),
.max (max),
.gtu_n (gtu_n),
.gts_n (gts_n),
.ltu_n (ltu_n),
.lts_n (lts_n),
.geu_n (geu_n),
.ges_n (ges_n),
.leu_n (leu_n),
.les_n (les_n),
.zero_n (zero_n),
.max_n (max_n)
);
always @(posedge clk) begin
if (thresh_sw) begin
counter <= counter + 1;
counter_down <= counter_down - 1;
threshold <= counter - 32'd31;
threshold_down <= counter_down + 32'd31;
end else begin
threshold <= threshold + 1;
threshold_down <= threshold_down - 1;
end
tbassert((counter == 32'b0) == zero, counter);
tbassert((counter == 32'hFFFFFFFF) == max, counter);
tbassert((counter > threshold) == gtu, gtu);
tbassert(($signed(counter) > $signed(threshold)) == gts, gts);
tbassert((counter < threshold) == ltu, ltu);
tbassert(($signed(counter) < $signed(threshold)) == lts, lts);
tbassert((counter >= threshold) == geu, geu);
tbassert(($signed(counter) >= $signed(threshold)) == ges, ges);
tbassert((counter <= threshold) == leu, leu);
tbassert(($signed(counter) <= $signed(threshold)) == les, les);
tbassert((counter_down == 32'b0) == zero_n, counter);
tbassert((counter_down == 32'hFFFFFFFF) == max_n, counter);
tbassert((counter_down > threshold_down) == gtu_n, gtu_n);
tbassert(($signed(counter_down) > $signed(threshold_down)) == gts_n, gts_n);
tbassert((counter_down < threshold_down) == ltu_n, ltu_n);
tbassert(($signed(counter_down) < $signed(threshold_down)) == lts_n, lts_n);
tbassert((counter_down >= threshold_down) == geu_n, geu_n);
tbassert(($signed(counter_down) >= $signed(threshold_down)) == ges_n, ges_n);
tbassert((counter_down <= threshold_down) == leu_n, leu_n);
tbassert(($signed(counter_down) <= $signed(threshold_down)) == les_n, les_n);
end
// ============================================================================
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEII",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEII",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string q; cin >> q; int n; cin >> n; vector<string> m(n); for (int i = 0; i < (n); ++i) cin >> m[i]; sort(m.begin(), m.end()); for (int i = 0; i < (n); ++i) { if (m[i].size() < q.size()) continue; if (m[i].substr(0, q.size()) == q) { cout << m[i] << endl; return 0; } } cout << q << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:00:19 12/14/2016
// Design Name:
// Module Name: BR_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BR_Top(
input wire clk, clr,
input wire ps2c, ps2d,
output wire hsync, vsync,
output wire [3:0] red, green, blue,
output wire [7:0] an,
output wire [7:0] segment
);
// Keyboard signal
wire [ 3: 0] status;
// VGA signal
wire signed [31:0] scroll;
wire video_on;
wire [ 9: 0] pixel_x, pixel_y;
wire btn_pos, mycar_pos, explode_pos,game_over_pos, score_pos;
wire btn_visible, explode_visible;
wire obstacle_pos [0:4];
wire digit_pos [0:3];
wire iscollide [0:4];
wire [16:0] back_addr, side_addr;
wire [15:0] explode_addr;
wire [13:0] digit_addr [0:3];
wire [14:0] game_over_addr;
wire [13:0] btn_addr, score_addr;
wire [12:0] mycar_addr;
wire [12:0] obstacle_addr [0:4];
wire [ 3:0] high_score [0:3];
Renderer render_unit (.clk(clk), .clr(clr),
.status(status),
.video_on(video_on),
.pixel_x(pixel_x), .pixel_y(pixel_y),
.scroll(scroll),
.btn_pos(btn_pos), .mycar_pos(mycar_pos), .explode_pos(explode_pos), .game_over_pos(game_over_pos), .score_pos(score_pos),
.btn_visible(btn_visible), .explode_visible(explode_visible),
.obstacle_pos0(obstacle_pos[0]), .obstacle_pos1(obstacle_pos[1]), .obstacle_pos2(obstacle_pos[2]), .obstacle_pos3(obstacle_pos[3]), .obstacle_pos4(obstacle_pos[4]),
.digit_pos0(digit_pos[0]), .digit_pos1(digit_pos[1]), .digit_pos2(digit_pos[2]), .digit_pos3(digit_pos[3]),
.iscollide0(iscollide[0]), .iscollide1(iscollide[1]), .iscollide2(iscollide[2]), .iscollide3(iscollide[3]), .iscollide4(iscollide[4]),
.back_addr(back_addr), .side_addr(side_addr), .btn_addr(btn_addr), .mycar_addr(mycar_addr), .explode_addr(explode_addr), .game_over_addr(game_over_addr), .score_addr(score_addr),
.obstacle_addr0(obstacle_addr[0]), .obstacle_addr1(obstacle_addr[1]), .obstacle_addr2(obstacle_addr[2]), .obstacle_addr3(obstacle_addr[3]), .obstacle_addr4(obstacle_addr[4]),
.digit_addr0(digit_addr[0]), .digit_addr1(digit_addr[1]), .digit_addr2(digit_addr[2]), .digit_addr3(digit_addr[3]),
.red(red), .green(green), .blue(blue)
);
Controller control_unit (.clk(clk), .clr(clr),
.ps2c(ps2c), .ps2d(ps2d),
.status(status),
.hsync(hsync), .vsync(vsync), .video_on(video_on), .pixel_x(pixel_x), .pixel_y(pixel_y),
.btn_pos(btn_pos), .mycar_pos(mycar_pos), .explode_pos(explode_pos), .game_over_pos(game_over_pos), .score_pos(score_pos),
.btn_visible(btn_visible), .explode_visible(explode_visible),
.obstacle_pos0(obstacle_pos[0]), .obstacle_pos1(obstacle_pos[1]), .obstacle_pos2(obstacle_pos[2]), .obstacle_pos3(obstacle_pos[3]), .obstacle_pos4(obstacle_pos[4]),
.digit_pos0(digit_pos[0]), .digit_pos1(digit_pos[1]), .digit_pos2(digit_pos[2]), .digit_pos3(digit_pos[3]),
.iscollide0(iscollide[0]), .iscollide1(iscollide[1]), .iscollide2(iscollide[2]), .iscollide3(iscollide[3]), .iscollide4(iscollide[4]),
.scroll(scroll),
.back_addr(back_addr), .side_addr(side_addr), .btn_addr(btn_addr), .mycar_addr(mycar_addr), .game_over_addr(game_over_addr), .score_addr(score_addr),
.obstacle_addr0(obstacle_addr[0]), .obstacle_addr1(obstacle_addr[1]), .obstacle_addr2(obstacle_addr[2]), .obstacle_addr3(obstacle_addr[3]), .obstacle_addr4(obstacle_addr[4]),
.explode_addr(explode_addr),
.digit_addr0(digit_addr[0]), .digit_addr1(digit_addr[1]), .digit_addr2(digit_addr[2]), .digit_addr3(digit_addr[3]),
.high_score0(high_score[0]), .high_score1(high_score[1]), .high_score2(high_score[2]), .high_score3(high_score[3])
);
Model model_unit (.clk(clk), .high_score0(high_score[0]), .high_score1(high_score[1]), .high_score2(high_score[2]), .high_score3(high_score[3]), .segment(segment), .an(an));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long x, y, z; long long x1, y1, z1; vector<long long> a(6); long long sum = 0; cin >> x >> y >> z; cin >> x1 >> y1 >> z1; for (int i = 0; i < 6; ++i) { long long b; cin >> b; a[i] = b; } if (x < 0) { sum += a[4]; } else if (x > x1) { sum += a[5]; } if (y < 0) { sum += a[0]; } else if (y > y1) { sum += a[1]; } if (z < 0) { sum += a[2]; } else if (z > z1) { sum += a[3]; } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; for (int q = 0; q < t; ++q) { int n, k; cin >> n >> k; vector<int> x(n); for (int i = 0; i < n; ++i) { cin >> x[i]; } vector<int> p(n, 0); for (int i = 1; i < n - 1; ++i) { if (x[i] > x[i + 1] && x[i] > x[i - 1]) { p[i] = p[i - 1] + 1; } else { p[i] = p[i - 1]; } } p[n - 1] = p[n - 2]; int ans = 0, left = 0; for (int l = 0; l + k - 1 < n; ++l) { if (p[l + k - 2] - p[l] > ans) { ans = p[l + k - 2] - p[l]; left = l; } } cout << ans + 1 << << left + 1 << endl; } return 0; }
|
#include<bits/stdc++.h> using namespace std; #define forg(i,x) for(register int i=fir[x];i;i=nxt[i]) #define uu unsigned #define scanf a14=scanf #define rint register int #define fre(x) freopen(#x .in , r ,stdin),freopen(#x .out , w ,stdout) typedef long long ll; typedef uu long long ull; typedef pair<int,int>pii; int a14; inline int rd(int l,int r){return rand()%(r-l+1)+l;} const int mxn=1e5+3,sq=200,qs=320; int n,b[mxn],lp[mxn],rp[mxn],kn,be[mxn],po[mxn],qn; int ju[mxn/sq+2][mxn],ad[mxn/sq+2][mxn/qs+1]; int TG; struct shu{ int a[mxn],tg[mxn]; void add(int x){for(;x<=n;x+=x&-x){if(tg[x]!=TG)tg[x]=TG,a[x]=0;++a[x];}} int ask(int x){ int su=0,p=0; for(int i=1<<16;i;i>>=1){ if(p+i>=n)continue; p+=i;if(tg[p]!=TG)tg[p]=TG,a[p]=0; if(p+a[p]+su>=x)p-=i;else su+=a[p]; } return p+1; } void gb(int t){for(int i=1;i<=n;++i){if(tg[i]!=TG)a[i]=0;ju[t][i]=ju[t][i-(i&-i)]+a[i];}for(int i=1;i<=n;++i)ju[t][i]+=i;} }ar; void add2(int t,int x,int y){ int k=(x-1)/qs; for(int i=x;i<=(k+1)*qs;++i)ju[t][i]+=y; for(++k;k*qs+1<=n;++k)ad[t][k]+=y; } int main(){ //cout<<(sizeof(ju)>>20)<<endl; scanf( %d ,&n);for(int i=1;i<=n;++i)scanf( %d ,b+i),b[i]=i-b[i];scanf( %d ,&qn); for(int l=1,r;r!=n;l=r+1){r=min(l+sq-1,n);lp[++kn]=l,rp[kn]=r;for(int i=l;i<=r;++i)be[i]=kn;} for(int t=1;t<=kn;++t){ ++TG; for(int i=lp[t];i<=rp[t];++i)po[i]=ar.ask(b[i]),ar.add(po[i]); ar.gb(t); } while(qn--){ int o,x,y;scanf( %d%d ,&o,&x);if(o==1){ scanf( %d ,&y);b[x]=x-y;int k=be[x],ls; ++TG;for(int i=lp[k];i<=rp[k];++i){ if(i<x)ar.add(po[i]);else{ ls=po[i],po[i]=ar.ask(b[i]),ar.add(po[i]); if(ls==po[i])continue; if(ls==po[i]-1){--ju[k][ls];continue;} if(ls==po[i]+1){++ju[k][po[i]];continue;} assert(i==x); add2(k,ls,-1),add2(k,po[i],1); } } }else{ int t=be[x],re=b[x];for(int i=x+1;i<=rp[t];++i)re+=b[i]<=re; for(++t;t<=kn;++t)re=ju[t][re]+ad[t][(re-1)/qs]; printf( %d n ,re); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int size = 50 + 10; int n, k, aim[size], num[size], ans = -1; int main() { cin >> n >> k; if (k > n) { cout << -1 << endl; return 0; } for (int i = 1; i <= n; i++) cin >> aim[i]; sort(aim + 1, aim + n + 1); num[1] = 0; for (int i = 2; i <= n; i++) if (aim[i] > aim[i - 1]) num[i] = i - 1; else num[i] = num[i - 1]; for (int i = 1; i <= n; i++) if (aim[i] != aim[i + 1] && n - num[i] == k) ans = aim[i]; if (ans < 0) { cout << ans << endl; return 0; } cout << ans << << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long a, long long b) { if (b == 0) return a; return (a % b == 0 ? b : GCD(b, a % b)); } long long POW(long long base, long long exp) { long long val; val = 1; while (exp > 0) { if (exp % 2 == 1) { val = (val * base) % 1000000007; } base = (base * base) % 1000000007; exp = exp / 2; } return val; } int main() { int n, m, ans; scanf( %d%d , &n, &m); if (n == 1) { ans = 1; } else { if ((m - 1) >= (n - m)) { ans = m - 1; } else { ans = m + 1; } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; while (test--) { int a, b; cin >> a >> b; cout << (a ^ b) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[1000]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); double ans = 0; for (int i = 1; i <= m; ++i) { int x, y, z; scanf( %d%d%d , &x, &y, &z); ans = max(ans, ((double)a[x] + a[y]) / z); } printf( %.15f n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = (int)1e9 + 7; const int INF = (int)1e9; const long long LINF = (long long)1e18; const long double PI = acos((long double)-1); const long double EPS = 1e-9; inline long long gcd(long long a, long long b) { long long r; while (b) { r = a % b; a = b; b = r; } return a; } inline long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } inline long long fpow(long long n, long long k, int p = MOD) { long long r = 1; for (; k; k >>= 1) { if (k & 1) r = r * n % p; n = n * n % p; } return r; } template <class T> inline int chkmin(T& a, const T& val) { return a > val ? a = val, 1 : 0; } template <class T> inline int chkmax(T& a, const T& val) { return a < val ? a = val, 1 : 0; } inline long long isqrt(long long k) { long long r = sqrt(k) + 1; while (r * r > k) r--; return r; } inline long long icbrt(long long k) { long long r = cbrt(k) + 1; while (r * r * r > k) r--; return r; } inline void addmod(int& a, int val, int p = MOD) { if ((a = (a + val)) >= p) a -= p; } inline void submod(int& a, int val, int p = MOD) { if ((a = (a - val)) < 0) a += p; } inline int mult(int a, int b, int p = MOD) { return (long long)a * b % p; } inline int inv(int a, int p = MOD) { return fpow(a, p - 2, p); } const int maxn = 100010; int n, m; vector<int> adj[maxn]; int a[maxn]; int d[maxn]; int tin[maxn]; int tms; int dfs(int u) { tin[u] = tms++; int res = tin[a[u]]; for (int i = (0); i < (int((adj[u]).size())); i++) { int v = adj[u][i]; int r = dfs(v); if (r <= tin[u] && r != tin[a[u]]) { cout << -1 n ; exit(0); } chkmin(res, r); } return res; } void solve() { cin >> n >> m; for (int i = (0); i < (m); i++) { int u, v; cin >> u >> v; u--; v--; adj[u].push_back(v); d[v]++; } for (int i = (0); i < (n); i++) cin >> a[i], a[i]--; for (int i = (0); i < (n); i++) if (!d[i]) { dfs(i); } vector<pair<int, int> > res; for (int i = (0); i < (n); i++) { res.push_back(make_pair(tin[a[i]], a[i])); } sort((res).begin(), (res).end()); (res).erase(unique((res).begin(), (res).end()), (res).end()); cout << int((res).size()) << n ; for (int i = (int((res).size())) - 1; i >= (0); i--) cout << res[i].second + 1 << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; }
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
/*
Copyright (C) {2014} {James Thomas} <>
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
///////////////////////////////////////////////////////////////////////////////////////////////////
// a simple module for mapping hcount and vcount to address in bram
// the math:
// bram is 320*240 = 76800 lines, 320 columns, and 240 rows
// each line of bram corresponds to one pixel
// currently, each line is 12 bits (4 pixels r, 4 pixels g, 4 pixels b)
// hcount and vcount are in the 640x480 space
// Thus, the desired address is: 320*(vcount/2) + (hcount/2)
// = (128 + 32)vcount + hcount/2
///////////////////////////////////////////////////////////////////////////////////////////////////
module addr_map(input[9:0] hcount,
input[9:0] vcount,
output[16:0] addr);
assign addr = (vcount[9:1] << 8) + (vcount[9:1] << 6) + (hcount >> 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A21BO_PP_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; long double PI = 3.14159265358979323846; using ll = long long; const ll modo = 1000000000; const ll inf = LONG_LONG_MAX; const ll ms = (2e6) + 5; ll peil(ll a, ll b) { if (a % b) return a / b + 1; return a / b; } long double help(long double mid, long double k, long double val, ll pp, long double t) { ll tmp = mid; ll dd = tmp / pp; long double rem = mid - (dd * pp); long double ans = dd * val; long double hh = min(rem, k); ans += hh; rem -= hh; ans += (rem / 2); return ans; } int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); cout << fixed << setprecision(10); ll k, d, t; cin >> k >> d >> t; long double kk = peil(k, d) * d; long double tt = k + ((kk - k) / 2); long double l = t; long double r = 2 * t; long double mid; long double ans = r; long double res; long double pp = 1 / (1e9); while ((r - l) > pp) { mid = (l + r) / 2; res = help(mid, k, tt, kk, t); if (res == t) { cout << mid; return 0; } if (res > t) { r = mid; ans = min(ans, mid); } else l = mid; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 2000; const int maxm = 1000 * 10; struct edge { int v, w, next; } e[maxm * 2]; struct node { int d, u; bool operator<(const node &b) const { return d > b.d; } }; int head[maxn], d[maxn], d2[maxn]; int tot; bool vis[maxn]; int g[maxn][maxn]; void add(int u, int v, int w) { e[tot].v = v; e[tot].w = w; e[tot].next = head[u]; head[u] = tot++; } void dijkstra(int s, int t, int n, bool dir) { for (int i = 1; i <= n; i++) { if (dir) d[i] = INF; else d2[i] = INF; } if (dir) d[s] = 0; else d2[s] = 0; memset(vis, 0, sizeof(vis)); priority_queue<node> q; q.push(node{0, s}); while (!q.empty()) { node temp = q.top(); q.pop(); int u = temp.u; if (vis[u]) continue; vis[u] = 1; for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].v; int w = e[i].w; if (dir) { if (d[v] > d[u] + w) { d[v] = d[u] + w; q.push(node{d[v], v}); } } else { if (d2[v] > d2[u] + w) { d2[v] = d2[u] + w; q.push(node{d2[v], v}); } } } } } int main() { int n, m, s, t, u, v; cin >> n >> m >> s >> t; memset(head, -1, sizeof(head)); for (int i = 0; i < m; i++) { cin >> u >> v; g[u][v] = 1; g[v][u] = 1; add(u, v, 1); add(v, u, 1); } dijkstra(s, t, n, true); dijkstra(t, s, n, false); long long ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (!g[i][j] && i != j) { if (d[i] + d2[j] + 1 >= d[t] && d2[i] + d[j] + 1 >= d[t]) { ans++; g[i][j] = g[j][i] = true; } } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int n, k; vector<vector<long long>> adj, leaf; vector<long long> level, par, out; vector<long long> counti; void dfs(int src, int lvl, int p = -1) { int child = 0; level[src] = lvl; for (auto it : adj[src]) { if (it == p) continue; par[it] = src; child++; dfs(it, lvl + 1, src); } if (!child) leaf.push_back({src, lvl, 0}); out[src] = child; } class comp { public: bool operator()(vector<long long> a, vector<long long> b) { return a[1] - a[2] < b[1] - b[2]; } }; void solve() { cin >> n >> k; adj.resize(n); for (int i = 0, x, y; i < n - 1; i++) { cin >> x >> y; x--, y--; adj[x].push_back(y); adj[y].push_back(x); } level.resize(n); par.resize(n); out.resize(n); dfs(0, 0); vector<long long> total(n, 0); priority_queue<vector<long long>, vector<vector<long long>>, comp> pq; for (auto it : leaf) pq.push(it); long long ans = 0; while (!pq.empty() && k--) { auto f = pq.top(); pq.pop(); long long node = f[0]; ans += f[1] - total[node]; if (node) { total[par[node]] += f[2] + 1; --out[par[node]]; if (!out[par[node]]) { pq.push({par[node], f[1] - 1, total[par[node]]}); } } } cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); }
|
module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15, po0);
input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09,
pi10, pi11, pi12, pi13, pi14, pi15;
output po0;
wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,
n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90;
OR2 U47 ( .A(n46), .B(n47), .Z(po0));
OR2 U48 ( .A(n48), .B(n49), .Z(n47));
AN2 U49 ( .A(n50), .B(n51), .Z(n49));
OR2 U50 ( .A(n52), .B(n53), .Z(n51));
AN2 U51 ( .A(n54), .B(n55), .Z(n53));
AN2 U52 ( .A(n56), .B(n57), .Z(n54));
AN2 U53 ( .A(n58), .B(n59), .Z(n52));
AN2 U54 ( .A(n60), .B(n61), .Z(n48));
IV2 U55 ( .A(n50), .Z(n61));
AN2 U56 ( .A(n62), .B(pi15), .Z(n50));
IV2 U57 ( .A(pi14), .Z(n62));
OR2 U58 ( .A(n63), .B(n64), .Z(n60));
AN2 U59 ( .A(n65), .B(n55), .Z(n64));
IV2 U60 ( .A(n59), .Z(n55));
AN2 U61 ( .A(n57), .B(n58), .Z(n65));
IV2 U62 ( .A(n56), .Z(n58));
AN2 U63 ( .A(n56), .B(n59), .Z(n63));
AN2 U64 ( .A(n66), .B(pi00), .Z(n56));
IV2 U65 ( .A(pi01), .Z(n66));
AN2 U66 ( .A(n67), .B(n59), .Z(n46));
OR2 U67 ( .A(n68), .B(n69), .Z(n59));
OR2 U68 ( .A(n70), .B(n71), .Z(n69));
AN2 U69 ( .A(n72), .B(n73), .Z(n71));
IV2 U70 ( .A(n74), .Z(n70));
OR2 U71 ( .A(n73), .B(n72), .Z(n74));
AN2 U72 ( .A(n75), .B(pi12), .Z(n72));
IV2 U73 ( .A(pi13), .Z(n75));
OR2 U74 ( .A(pi10), .B(n76), .Z(n73));
IV2 U75 ( .A(pi11), .Z(n76));
AN2 U76 ( .A(n77), .B(n78), .Z(n68));
OR2 U77 ( .A(n79), .B(n80), .Z(n78));
IV2 U78 ( .A(n81), .Z(n77));
AN2 U79 ( .A(n80), .B(n79), .Z(n81));
AN2 U80 ( .A(n82), .B(pi08), .Z(n79));
IV2 U81 ( .A(pi09), .Z(n82));
OR2 U82 ( .A(pi06), .B(n83), .Z(n80));
IV2 U83 ( .A(pi07), .Z(n83));
IV2 U84 ( .A(n57), .Z(n67));
OR2 U85 ( .A(n84), .B(n85), .Z(n57));
AN2 U86 ( .A(n86), .B(n87), .Z(n85));
IV2 U87 ( .A(n88), .Z(n84));
OR2 U88 ( .A(n87), .B(n86), .Z(n88));
AN2 U89 ( .A(n89), .B(pi04), .Z(n86));
IV2 U90 ( .A(pi05), .Z(n89));
OR2 U91 ( .A(pi02), .B(n90), .Z(n87));
IV2 U92 ( .A(pi03), .Z(n90));
endmodule
module IV2(A, Z);
input A;
output Z;
assign Z = ~A;
endmodule
module AN2(A, B, Z);
input A, B;
output Z;
assign Z = A & B;
endmodule
module OR2(A, B, Z);
input A, B;
output Z;
assign Z = A | B;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t = 1; while (t--) { string s; cin >> s; sort(s.begin(), s.end()); long long n = s.size(), ans = 0; long long l = 0, r = n - 1; while (l <= r) { long long m = l + (r - l) / 2; if (s[m] == s[n - 1]) { if (s[m - 1] != s[n - 1] || m == 0) { ans = m; break; } else r = m - 1; } else { l = m + 1; } } cout << s.substr(ans) << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n; string s; vector<string> text; vector<int> lens; bool check(int w) { int c = 0, lines = 1; for (int i = 0; i < (int)(lens).size(); i++) { if (lens[i] > w) return false; if (c + lens[i] > w) { lines++; i--; c = 0; } else c += lens[i]; } return lines <= n; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; while (cin >> s) text.push_back(s); int c; for (int i = 0; i < (int)(text).size(); i++) { c = 0; for (int j = 0; j < (int)(text[i]).size(); j++) { c++; if (text[i][j] == || text[i][j] == - ) { lens.push_back(c); c = 0; } } if (c) { if (i != (int)(text).size() - 1) lens.push_back(c + 1); else lens.push_back(c); } } int s = 0, e = 1e9, mid; while (e - s > 1) { mid = (s + e) >> 1; if (check(mid)) e = mid; else s = mid; } cout << e << n ; return 0; }
|
`default_nettype none
module pulse_gen(
input clk, // 12 MHz base clock
input RS232_Rx, // Receive pin for the FTDI chip
input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output P2
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
wire [31:0] period;
wire [15:0] p1width;
wire [15:0] delay;
wire [15:0] p2width;
wire [15:0] nut_del;
wire [7:0] nut_wid;
wire block;
wire [7:0] pulse_block;
wire [15:0] pulse_block_off;
wire [7:0] cpmg;
wire rx_done;
// wire [6:0] pre_att;
// wire [6:0] post_att;
// NOSIM_START
wire clk_pll;
wire clk_pll_gl;
wire lock;
// Setting the PLL to output a 201 MHz clock, based on code from
// https://gist.github.com/thoughtpolice/8ec923e1b3fc4bb12c11aa23b4dc53b5#file-ice40-v
// Note: These values are slightly different from those outputted by icepll
pll ecppll(
.clock_in(clk),
.clock_out(clk_pll),
.locked(lock)
);
// Setting up communications with LabView over USB
pulse_control control(
.clk(clk),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done)
);
// NOSIM_END
// Generating the necessary pulses
pulses pulses(
.clk(clk),
.clk_pll(clk_pll),
.reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
.nut_d(nut_del),
.nut_w(nut_wid),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
.p_bl(pulse_block),
.p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(P2)
// .test({FM, P3, P4})
);
// NOSIM2_START
endmodule // pulse_gen
|
#include <bits/stdc++.h> using namespace std; int a[5000 + 10]; int main() { int n; cin >> n; for (int i = 1; i < n + 1; i++) cin >> a[i]; bool flag = false; for (int i = 1; i < n; i++) { if (a[a[a[i]]] == i) { flag = true; break; } } if (flag) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, head[100005], tot, d[100005], fa[100005], vis[100005], lf[100005], cnt; struct node { int v, nxt; } edg[100005 << 1]; inline void addedg(int u, int v) { edg[tot].v = v; edg[tot].nxt = head[u]; head[u] = tot++; } inline void init() { memset(head, -1, sizeof(int) * (n + 1)); tot = cnt = 0; } inline void dfs1(int u, int f) { int v; d[u] = 0; for (int i = head[u]; i != -1; i = edg[i].nxt) { v = edg[i].v; ++d[u]; if (v == f) continue; dfs1(v, u); } } inline void dfs2(int u, int f, int dis) { int v; fa[u] = f; d[u] = dis; for (int i = head[u]; i != -1; i = edg[i].nxt) { v = edg[i].v; if (f == v) continue; dfs2(v, u, dis + 1); } } inline bool cmp(int u, int v) { return d[u] > d[v]; } set<int> se; int main() { scanf( %d , &n); init(); int u, v; for (int i = 1; i < n; ++i) { scanf( %d%d , &u, &v); addedg(u, v); addedg(v, u); } dfs1(1, 1); for (int i = 1; i <= n; ++i) { if (d[i] == 1) lf[cnt++] = i; } int root = lf[0]; dfs2(root, root, 0); vis[root] = 1; int maxn = 0, minn = 1; for (int i = 1; i < cnt; ++i) { if (d[lf[i]] & 1) minn = 3; } fa[root] = edg[head[root]].v; maxn = n - 1 - cnt; for (int i = 0; i < cnt; ++i) se.insert(fa[lf[i]]); maxn += se.size(); printf( %d %d n , minn, maxn); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[2][300005], x[300005], y[300005]; int n, k; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> x[i]; for (int i = 1; i <= n; i++) cin >> y[i]; for (int i = 1; i <= n; i++) { if (!(~dp[0][i - 1])) { dp[0][i] = -1; dp[1][i] = -1; continue; } if (x[i] > y[i]) { long long h = (long long)k * ((long long)y[i] + 1LL); if (x[i] + dp[0][i - 1] > h) { dp[0][i] = -1; dp[1][i] = -1; continue; } dp[1][i] = 0; h = (long long)k * (long long)y[i]; if (x[i] + dp[0][i - 1] <= h) { dp[0][i] = 0; continue; } else dp[0][i] = x[i] + dp[0][i - 1] - k * y[i]; } if (y[i] > x[i]) { long long h = (long long)k * ((long long)x[i] + 1LL); if (y[i] + dp[1][i - 1] > h) { dp[0][i] = -1; dp[1][i] = -1; continue; } dp[0][i] = 0; h = (long long)k * (long long)x[i]; if (y[i] + dp[1][i - 1] <= h) { dp[1][i] = 0; continue; } else dp[1][i] = y[i] + dp[1][i - 1] - k * x[i]; } if (x[i] == y[i]) { if (x[i] == 1) { if (max(dp[0][i - 1], dp[1][i - 1]) == k) { dp[(dp[0][i - 1] > dp[1][i - 1] ? 1 : 0)][i] = 0; dp[(dp[0][i - 1] > dp[1][i - 1] ? 0 : 1)][i] = 1; } else continue; } else { if (k == 1 && max(dp[0][i - 1], dp[1][i - 1]) == k) { dp[(dp[0][i - 1] > dp[1][i - 1] ? 1 : 0)][i] = 0; dp[(dp[0][i - 1] > dp[1][i - 1] ? 0 : 1)][i] = 1; } else continue; } } } if (~dp[0][n]) cout << YES ; else cout << NO ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/18 10:59:33
// Design Name:
// Module Name: data_in
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_in(clk,rst_n,sw,btn,DIPsw,isRunningFlag,resetFlag,agCtrlFlag);
input clk,rst_n;
input sw;
input [4:0] btn;
input [3:0] DIPsw;
//input [7:0] din;
output reg [3:0] agCtrlFlag;
output wire isRunningFlag;
//output wire runLoopFlag;
//output wire run1StepFlag;
output wire resetFlag;
//output wire setOffsetFlag;
wire runLoopFlag_n,run1StepFlag_n,resetFlag_n;
wire [3:0] agCtrlFlag_n;
assign runLoopFlag = ~runLoopFlag_n;
assign run1StepFlag = ~run1StepFlag_n;
assign resetFlag = ~resetFlag_n;
//assign agCtrlFlag = ~agCtrlFlag_n;
always @ ( agCtrlFlag_n )
begin
case(agCtrlFlag)
4'b0001: begin
if (agCtrlFlag_n[0] == 0) agCtrlFlag <= 4'b0000;
else if(agCtrlFlag_n[1] == 0) agCtrlFlag <= 4'b0010;
else if(agCtrlFlag_n[2] == 0) agCtrlFlag <= 4'b0100;
else if(agCtrlFlag_n[3] == 0) agCtrlFlag <= 4'b1000;
else agCtrlFlag <= 4'b0001;
end
4'b0010: begin
if (agCtrlFlag_n[0] == 0) agCtrlFlag <= 4'b0001;
else if(agCtrlFlag_n[1] == 0) agCtrlFlag <= 4'b0000;
else if(agCtrlFlag_n[2] == 0) agCtrlFlag <= 4'b0100;
else if(agCtrlFlag_n[3] == 0) agCtrlFlag <= 4'b1000;
else agCtrlFlag <= 4'b0010;
end
4'b0100: begin
if (agCtrlFlag_n[0] == 0) agCtrlFlag <= 4'b0001;
else if(agCtrlFlag_n[1] == 0) agCtrlFlag <= 4'b0010;
else if(agCtrlFlag_n[2] == 0) agCtrlFlag <= 4'b0000;
else if(agCtrlFlag_n[3] == 0) agCtrlFlag <= 4'b1000;
else agCtrlFlag <= 4'b0100;
end
4'b1000: begin
if (agCtrlFlag_n[0] == 0) agCtrlFlag <= 4'b0001;
else if(agCtrlFlag_n[1] == 0) agCtrlFlag <= 4'b0010;
else if(agCtrlFlag_n[2] == 0) agCtrlFlag <= 4'b0100;
else if(agCtrlFlag_n[3] == 0) agCtrlFlag <= 4'b0000;
else agCtrlFlag <= 4'b1000;
end
default: begin
if(agCtrlFlag_n[0] == 0) agCtrlFlag <= 4'b0001;
else if(agCtrlFlag_n[1] == 0) agCtrlFlag <= 4'b0010;
else if(agCtrlFlag_n[2] == 0) agCtrlFlag <= 4'b0100;
else if(agCtrlFlag_n[3] == 0) agCtrlFlag <= 4'b1000;
else agCtrlFlag <= 4'b0000;
end
endcase
end
btn2btn sw_isRunning(.clk(clk),.rst_n(rst_n),.din(sw),.flag(isRunningFlag));
//btn2sw btn_runLoop(.clk(clk),.rst_n(rst_n),.din(btn[0]),.flag(runLoopFlag_n));
//btn2btn btn_run1Step(.clk(clk),.rst_n(rst_n),.din(btn[1]),.flag(run1StepFlag_n));
btn2btn btn_reset(.clk(clk),.rst_n(rst_n),.din(btn[4]),.flag(resetFlag_n));
btn2btn btn_agCtrl0(.clk(clk),.rst_n(rst_n),.din(btn[0]),.flag(agCtrlFlag_n[0]));
btn2btn btn_agCtrl1(.clk(clk),.rst_n(rst_n),.din(btn[1]),.flag(agCtrlFlag_n[1]));
btn2btn btn_agCtrl2(.clk(clk),.rst_n(rst_n),.din(btn[2]),.flag(agCtrlFlag_n[2]));
btn2btn btn_agCtrl3(.clk(clk),.rst_n(rst_n),.din(btn[3]),.flag(agCtrlFlag_n[3]));
//btn2sw btn_setOffset(.clk(clk),.rst_n(rst_n),.din(sw),.flag(!setOffsetFlag));
endmodule
module btn2sw(clk,rst_n,din,flag);
input clk,rst_n,din;
output reg flag;
reg [31:0] counter;
reg [2:0] state;
parameter SstableHigh=0,SunstableHigh=1,Snegedge=2,SstableLow=3,SunstableLow=4,Sposedge=5;
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
state <= SstableHigh;
counter <= 32'd0;
flag <= din;
end
else begin
case(state)
SstableHigh: begin
if(din == 1'b1) begin
state <= SstableHigh;
end
else begin
counter <= 0;
state <= SunstableHigh;
end
end
SunstableHigh: begin
if(counter >= 32'd200_000) begin
counter <= 32'd0;
if ( din == 1'b0 ) state <= Snegedge;
else state <= SstableHigh;
end
else begin
counter <= counter + 1;
state <= SunstableHigh;
end
end
Snegedge: begin
flag <= ~flag;
state <= SstableLow;
end
SstableLow: begin
if(din == 1'b0) begin
state <= SstableLow;
end
else begin
counter <= 0;
state <= SunstableLow;
end
end
SunstableLow: begin
if(counter >= 32'd200_000) begin
counter <= 32'd0;
if ( din == 1'b1 ) state <= Sposedge;
else state <= SstableLow;
end
else begin
counter <= counter + 1;
state <= SunstableLow;
end
end
Sposedge: begin
state <= SstableHigh;
end
endcase
end
endmodule
module btn2btn(clk,rst_n,din,flag);
input clk,rst_n,din;
output reg flag;
reg [31:0] counter;
reg [2:0] state;
parameter SstableHigh=0,SunstableHigh=1,Snegedge=2,SstableLow=3,SunstableLow=4,Sposedge=5;
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
state <= SstableHigh;
counter <= 32'd0;
flag <= din;
end
else begin
case(state)
SstableHigh: begin
if(din == 1'b1) begin
state <= SstableHigh;
end
else begin
counter <= 0;
state <= SunstableHigh;
end
end
SunstableHigh: begin
if(counter >= 32'd2_000_000) begin
counter <= 32'd0;
if ( din == 1'b0 ) state <= Snegedge;
else state <= SstableHigh;
end
else begin
counter <= counter + 1;
state <= SunstableHigh;
end
end
Snegedge: begin
flag <= 1'b0;
state <= SstableLow;
end
SstableLow: begin
if(din == 1'b0) begin
state <= SstableLow;
end
else begin
counter <= 0;
state <= SunstableLow;
end
end
SunstableLow: begin
if(counter >= 32'd2_000_000) begin
counter <= 32'd0;
if ( din == 1'b1 ) state <= Sposedge;
else state <= SstableLow;
end
else begin
counter <= counter + 1;
state <= SunstableLow;
end
end
Sposedge: begin
flag <= 1'b1;
state <= SstableHigh;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; namespace io { string separator = ; } template <typename T> inline void write(T x) { cout << x << io::separator; } template <typename T, typename... Args> inline void write(T x, Args... args) { write(x); write(args...); } inline void writeln() { cout << n ; } template <typename... Args> inline void writeln(Args... args) { write(args...); writeln(); } template <typename T> inline void read(T& x) { cin >> x; } template <typename T, typename... Args> inline void read(T& x, Args&... args) { cin >> x; read(args...); } template <typename T> inline void writec(T x) { for (auto i = x.begin(); i != x.end(); i++) write(*i); writeln(); } template <typename TL, typename TR> inline TL GCD(TL a, TR b) { TL c; while (b) { c = b; b = a % b; a = c; } return a; } template <typename TL, typename TR> inline TL LCM(TL a, TR b) { return a / GCD(a, b) * b; } template <typename TL, typename TR> inline TL MAX(TL a, TR b) { return a > b ? a : b; } template <typename T, typename... Args> inline T MAX(T a, Args... args) { return MAX(a, MAX(args...)); } template <typename TL, typename TR> inline TL MIN(TL a, TR b) { return a < b ? a : b; } template <typename T, typename... Args> inline T MIN(T a, Args... args) { return MIN(a, MIN(args...)); } inline int64_t fac(int16_t n) { static vector<int64_t> f(1, 1); for (auto i = f.size(); i <= n; i++) f.push_back(f.back() * i); return f[n]; } inline int64_t suma(int32_t a1, int32_t d, int32_t n) { return n * (2 * a1 + (n - 1) * d) / 2; } inline int32_t factor(int32_t n) { static vector<int32_t> d(2, 2), prime; if (n + 1 > d.size()) { int32_t np = d.size() - 1; int32_t nn = d.size(); while (n > nn - 1) nn *= 2; nn--; d.resize(nn + 1); for (auto i = 2; i <= nn; i++) { if (!d[i]) { d[i] = i; prime.push_back(i); } int64_t x; for (int32_t j = 0; prime[j] <= d[i] && j < prime.size() && (x = (int64_t)i * prime[j]) <= nn; j++) d[x] = prime[j]; } } return d[n]; } inline bool isprime(int32_t n) { return (factor(n) == n); } inline int32_t prime(int32_t n) { static vector<int32_t> p(1, 2); if (n + 1 > p.size()) { int32_t np = p.size() - 1; int32_t nn = p.size(); while (n > nn - 1) nn *= 2; factor(nn * (log(nn) + log(log(nn)))); nn--; p.resize(nn + 1); int32_t x = p[np] + 1; for (auto i = np + 1; i <= nn; i++) { while (!isprime(x)) x++; p[i] = x++; } } return p[n]; } int32_t MOD = 1e9 + 7; inline int32_t SUM(int32_t x, int32_t y) { return (x + y) % MOD; } inline int32_t MUL(int32_t x, int32_t y) { return (int64_t)x * y % MOD; } inline int32_t POW(int32_t x, int32_t n) { int32_t y = 1; while (n) { if (n % 2) y = MUL(y, x); x = MUL(x, x); n /= 2; } return y; } inline int32_t INV(int32_t x) { return POW(x, MOD - 2); } inline int32_t DIV(int32_t x, int32_t y) { return MUL(x, INV(y)); } inline int32_t P(int32_t l, int32_t r) { int32_t x = 1; for (auto i = l; i <= r; i++) x = MUL(x, i); return x; } inline int32_t FAC(int32_t n) { return P(2, n); } inline int32_t C(int32_t n, int32_t k) { return DIV(P(k + 1, n), P(2, n - k)); } void solve(); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } inline void solve() { int16_t n; read(n); vector<int16_t> r(n); for (auto i = r.begin(); i != r.end(); i++) read(*i); int16_t mn = (*min_element(r.begin(), r.end())); int16_t mx = (*max_element(r.begin(), r.end())); int16_t s = 0; for (auto i : r) s += i - mn; s -= mx - mn; while (s < mx - mn && mn != 0) { s += n - 1; mn--; } s += mx - mn; if (!mn) { s = 0; for (auto i : r) s += i; } (s); string ans0(n, 0 ); string ans = ans0; writeln(mn); if (mn) { writeln(s / 2); if (s % 2) { int16_t i = 0; for (auto i_ = 3; i_--;) { while (r[i] == mn) i++; ans[i] = 1 ; r[i]--; i++; } writeln(ans); s -= 3; } for (auto i_ = s / 2; i_--;) { int16_t mxi = distance(r.begin(), max_element(r.begin(), r.end())); int16_t i = 0; while (r[i] == mn || i == mxi) i++; ans = ans0; ans[i] = ans[mxi] = 1 ; r[i]--; r[mxi]--; writeln(ans); } } else { writeln(s); for (auto i = 0; i <= n - 1; i++) { ans = ans0; ans[i] = ans[(i + 1) % n] = 1 ; for (auto i_ = r[i]; i_--;) writeln(ans); } } }
|
/* Atari on an FPGA
Masters of Engineering Project
Cornell University, 2007
Daniel Beer
RIOT.v
Redesign of the MOS 6532 chip. Provides RAM, I/O and timers to the Atari.
*/
`timescale 1ns / 1ps
`include "riot.vh"
module RIOT(A, // Address bus input
Din, // Data bus input
Dout, // Data bus output
CS, // Chip select input
CS_n, // Active low chip select input
R_W_n, // Active low read/write input
RS_n, // Active low rom select input
RES_n, // Active low reset input
IRQ_n, // Active low interrupt output
CLK, // Clock input
PAin, // 8 bit port A input
PAout, // 8 bit port A output
PBin, // 8 bit port B input
PBout);// 8 bit port B output
input [6:0] A;
input [7:0] Din;
output [7:0] Dout;
input CS, CS_n, R_W_n, RS_n, RES_n, CLK;
output IRQ_n;
input [7:0] PAin, PBin;
output [7:0] PAout, PBout; // Output register
reg [7:0] Dout; // RAM allocation
reg [7:0] RAM[127:0]; // I/O registers
reg [7:0] DRA, DRB; // Data registers
reg [7:0] DDRA, DDRB; // Data direction registers
wire PA7;
reg R_PA7;
assign PA7 = (PAin[7] & ~DDRA[7]) | (DRA[7] & DDRA[7]);
assign PAout = DRA & DDRA;
assign PBout = DRB & DDRB;
// Timer registers
reg [8:0] Timer;
reg [9:0] Prescaler;
reg [1:0] Timer_Mode;
reg Timer_Int_Flag, PA7_Int_Flag, Timer_Int_Enable, PA7_Int_Enable, PA7_Int_Mode; // Timer prescaler constants
wire [9:0] PRESCALER_VALS[3:0];
assign PRESCALER_VALS[0] = 10'd0;
assign PRESCALER_VALS[1] = 10'd7;
assign PRESCALER_VALS[2] = 10'd63;
assign PRESCALER_VALS[3] = 10'd1023;
// Interrupt
assign IRQ_n = ~(Timer_Int_Flag & Timer_Int_Enable | PA7_Int_Flag & PA7_Int_Enable);
// Operation decoding
wire [6:0] op;
reg [6:0] R_op;
assign op = {RS_n, R_W_n, A[4:0]};
// Registered data in
reg [7:0] R_Din;
integer cnt;
// Software operations
always @(posedge CLK)
begin
// Reset operation
if (~RES_n) begin
DRA <= 8'b0;
DDRA <= 8'b0;
DRB <= 8'b0;
DDRB <= 8'b0;
Timer_Int_Flag <= 1'b0;
PA7_Int_Flag <= 1'b0;
PA7_Int_Enable <= 1'b0;
PA7_Int_Mode <= 1'b0;
// Fill RAM with 0s
for (cnt = 0; cnt < 128; cnt = cnt + 1)
RAM[cnt] <= 8'b0;
R_PA7 <= 1'b0;
R_op <= `NOP;
R_Din <= 8'b0;
end
// If the chip is enabled, execute an operation
else if (CS & ~CS_n) begin
// Register inputs for use later
R_PA7 <= PA7;
R_op <= op;
R_Din <= Din;
// Update the timer interrupt flag
casex (op)
`WRITE_TIMER: Timer_Int_Flag <= 1'b0;
`READ_TIMER: Timer_Int_Flag <= 1'b0;
default: if (Timer == 9'b111111111) Timer_Int_Flag <= 1'b1;
endcase
// Update the port A interrupt flag
casex (op)
`READ_INT_FLAG: PA7_Int_Flag <= 1'b0;
default: PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
endcase
// Process the current operation
casex(op) // RAM access
`READ_RAM: Dout <= RAM[A];
`WRITE_RAM: RAM[A] <= Din;
// Port A data access
`READ_DRA : Dout <= (PAin & ~DDRA) | (DRA & DDRA);
`WRITE_DRA: DRA <= Din;
// Port A direction register access
`READ_DDRA: Dout <= DDRA;
`WRITE_DDRA: DDRA <= Din;
// Port B data access
`READ_DRB: Dout <= (PBin & ~DDRB) | (DRB & DDRB);
`WRITE_DRB: DRB <= Din;
// Port B direction register access
`READ_DDRB: Dout <= DDRB;
`WRITE_DDRB: DDRB <= Din;
// Timer access
`READ_TIMER: Dout <= Timer[7:0];
// Status register access
`READ_INT_FLAG: Dout <= {Timer_Int_Flag, PA7_Int_Flag, 6'b0};
// Enable the port A interrupt
`WRITE_EDGE_DETECT: begin
PA7_Int_Mode <= A[0]; PA7_Int_Enable <= A[1];
end
endcase
end
// Even if the chip is not enabled, update background functions
else begin
// Update the timer interrupt
if (Timer == 9'b111111111)
Timer_Int_Flag <= 1'b1;
// Update the port A interrupt
R_PA7 <= PA7;
PA7_Int_Flag <= PA7_Int_Flag | (PA7 != R_PA7 & PA7 == PA7_Int_Mode);
// Set the operation to a NOP
R_op <=`NOP;
end
end
// Update the timer at the negative edge of the clock
always @(negedge CLK)begin
// Reset operation
if (~RES_n) begin
Timer <= 9'b0;
Timer_Mode <= 2'b0;
Prescaler <= 10'b0;
Timer_Int_Enable <= 1'b0;
end
// Otherwise, process timer operations
else
casex
(R_op)
// Write value to the timer and update the prescaler based on the address
`WRITE_TIMER:begin
Timer <= {1'b0, R_Din};
Timer_Mode <= R_op[1:0];
Prescaler <= PRESCALER_VALS[R_op[1:0]];
Timer_Int_Enable <= R_op[3];
end
// Otherwise decrement the prescaler and if necessary the timer.
// The prescaler holds a variable number of counts that must be
// run before the timer is decremented
default:if (Timer != 9'b100000000) begin
if (Prescaler != 10'b0)
Prescaler <= Prescaler - 10'b1;
else begin
if (Timer == 9'b0)
begin
Prescaler <= 10'b0;
Timer_Mode <= 2'b0;
end
else
Prescaler <= PRESCALER_VALS[Timer_Mode];
Timer <= Timer - 9'b1;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a[3][333333], x, y, sum[4][333333], r[4][333333]; set<pair<long long, long long> > s[333333]; map<pair<long long, long long>, long long> d; map<long long, long long> last[4]; void read(long long &x) { scanf( %lld , &x); } int main() { cin >> n; for (long long i = 1; i <= 2; i++) for (long long j = 1; j <= n; j++) read(a[i][j]); for (long long i = 1; i <= 2; i++) for (long long j = n; j >= 1; j--) { sum[i][j] = sum[i][j + 1] + a[i][j]; sum[3][j] += sum[i][j]; } last[1][0] = last[2][0] = last[3][0] = n + 1; r[1][n + 1] = r[2][n + 1] = r[3][n + 1] = n + 1; for (long long i = 1; i <= 3; i++) for (long long j = n; j >= 1; j--) { r[i][j] = r[i][j + 1]; if (last[i].count(sum[i][j])) r[i][j] = min(r[i][j], last[i][sum[i][j]] - 1); last[i][sum[i][j]] = j; } s[0].insert(make_pair(0, 0)); d[make_pair(0, 0)] = 0; for (long long i = 0; i < n; i++) { for (pair<long long, long long> cur : s[i]) { x = cur.first; y = cur.second; if (x <= y) { s[min(x + 1, y)].insert(make_pair(x + 1, y)); d[make_pair(x + 1, y)] = max(d[make_pair(x + 1, y)], d[make_pair(x, y)]); s[min(r[1][x + 1], y)].insert(make_pair(r[1][x + 1], y)); d[make_pair(r[1][x + 1], y)] = max(d[make_pair(r[1][x + 1], y)], d[make_pair(x, y)] + 1); } if (y <= x) { s[min(x, y + 1)].insert(make_pair(x, y + 1)); d[make_pair(x, y + 1)] = max(d[make_pair(x, y + 1)], d[make_pair(x, y)]); s[min(r[2][y + 1], x)].insert(make_pair(x, r[2][y + 1])); d[make_pair(x, r[2][y + 1])] = max(d[make_pair(x, r[2][y + 1])], d[make_pair(x, y)] + 1); } if (x == y) { s[r[3][x + 1]].insert(make_pair(r[3][x + 1], r[3][x + 1])); d[make_pair(r[3][x + 1], r[3][x + 1])] = max(d[make_pair(r[3][x + 1], r[3][x + 1])], d[make_pair(x, y)] + 1); } d.erase(make_pair(x, y)); } s[i].clear(); } assert(d.size() <= 4 * n); cout << d[make_pair(n, n)]; }
|
#include <bits/stdc++.h> using namespace std; void debug_out() { cerr << endl; } template <class T> ostream& prnt(ostream& out, T v) { out << v.size() << n ; for (auto e : v) out << e << ; return out; } template <class T> ostream& operator<<(ostream& out, vector<T> v) { return prnt(out, v); } template <class T> ostream& operator<<(ostream& out, set<T> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, map<T1, T2> v) { return prnt(out, v); } template <class T1, class T2> ostream& operator<<(ostream& out, pair<T1, T2> p) { return out << ( << p.first << << p.second << ) ; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << H; debug_out(T...); } const int N = 1001; const int MOD = 998244353; int n, dp[2][N], a[N], k, f[100100], r[N]; int solve(int x) { for (int i = 1; i <= n; i++) { int j = upper_bound(a + 1, a + n + 1, a[i] - x) - a; j--; r[i] = j; } for (int j = 1; j <= k; j++) { for (int i = 1; i <= n; i++) if (j == 1) dp[1][i] = 1; else dp[j % 2][i] = dp[1 - j % 2][r[i]]; for (int i = 2; i <= n; i++) dp[j % 2][i] += dp[j % 2][i - 1], dp[j % 2][i] %= MOD; } return dp[k % 2][n]; } int main() { ios_base::sync_with_stdio(false); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); int mx = a[n] / (k - 1) + 1; for (int x = 0; x <= mx; x++) f[x] = solve(x); long long ans = 0; for (int x = 0; x < mx; x++) { f[x] -= f[x + 1]; if (f[x] < 0) f[x] += MOD; ans += (1LL * x * f[x]) % MOD; ans %= MOD; } cout << ans << n ; }
|
#include <bits/stdc++.h> const int N = 1e7 + 5; int n, pos[N], ans1, ans2; long long ans = 1e14; int main() { scanf( %d , &n); for (int i = 1, x; i <= n; ++i) { scanf( %d , &x); if (pos[x]) { if (x < ans) ans1 = pos[x], ans2 = i, ans = x; } else pos[x] = i; } for (int i = 1, tmp1, tmp2; i < N; ++i) { if (i >= ans) break; tmp1 = tmp2 = 0; for (int j = i; j < N; j += i) { if (!pos[j]) continue; if (!tmp1) tmp1 = j, tmp2 = pos[j]; else { if (1LL * j / i * tmp1 < ans) { ans = 1LL * j / i * tmp1, ans1 = pos[j], ans2 = tmp2; break; } } } } if (ans1 > ans2) ans1 ^= ans2 ^= ans1 ^= ans2; printf( %d %d n , ans1, ans2); return 0; }
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-27 23:56:17
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module RecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output reg [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
subRecursiveKOA #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
subRecursiveKOA #(.SW((SW/2)+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
subRecursiveKOA #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output wire [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
assign bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:11:44 04/08/2014
// Design Name: fourbit_cpu
// Module Name: C:/Users/Jonathan/Documents/Xilinx/Projects/CPU/test_cpu.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fourbit_cpu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cpu;
// Inputs
reg clk;
reg clr;
reg [7:0] sw;
reg [1:0] btn;
// Outputs
wire [3:0] led;
wire decimal;
wire [3:0] enable;
wire [6:0] segs;
// Instantiate the Unit Under Test (UUT)
fourbit_cpu uut (
.clk(clk),
.clr(clr),
.sw(sw),
.btn(btn),
.led(led),
.decimal(decimal),
.enable(enable),
.segs(segs)
);
initial begin
$display("Simulation has Started..");
// Initialize Inputs
clk = 0;
clr = 0;
sw = 0;
btn = 0;
// Wait 100 ns for global reset to finish
#100;
clr = 1'b1;
#30;
clr = 1'b0;
// Test user mode.
// **************************************************************
// Test load
sw = 8'b00000100; // R[0] <- 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00010011; // R[1] <- 3
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00100010; // R[2] <- 2
btn = 2'b01;
#40;
btn = 2'b00;
#100;
sw = 8'b00110001; // R[3] <- 1
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// **************************************************************
// Test store
// **************************************************************
sw = 8'b01000000; // LEDS <- R[0] = 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// **************************************************************
// Test move
sw = 8'b10010000; // R[1] <- R[0] = 4
btn = 2'b01;
#40;
btn = 2'b00;
#100;
// Test ALU operations.
// **************************************************************
// add
sw = 8'b11111000; // R[3] <- R[3] + R[2] = 1 + 2
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// sub
sw = 8'b11000101; // R[0] <- R[0] - R[1] = 4 - 4
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// and
sw = 8'b11101110; // R[2] <- R[2] & R[3] = 10 & 11 = 2
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// not
sw = 8'b11010011; // R[1] <- ~R[1] = ~(0100) = 1011 = 11
btn = 2'b01;
#40;
btn = 2'b00;
#120;
// **************************************************************
// Test run mode
// **************************************************************
clr = 1'b1;
#30;
clr = 1'b0;
btn = 2'b10;
#30;
btn = 2'b00;
// **************************************************************
$display("Simulation has Ended.");
end
always
#20 clk <= ~clk;
endmodule
|
`include "adder.v"
module IMUL16 # (parameter NUM_BITS = 2)
(
input wire [NUM_BITS-1:0] A,
input wire [NUM_BITS-1:0] B,
output wire [2*NUM_BITS-1:0] oResult
);
wire [NUM_BITS-1:0] wCarry [NUM_BITS-2:0]; // matriz definida para conectar los carry's
wire[NUM_BITS-1:0] Temp_results [NUM_BITS-1:0]; // matriz definida para conectar los resultados de los sumadores y los carry's de los ultimos digitos en la ultima columna.
genvar CurrentRow, CurrentCol; // iteradores de columnas y filas
assign oResult[0]=A[0]&B[0]; // se asigna el primer digito de la multiplicacion ya que es fijo
assign Temp_results[0][NUM_BITS-1]=1'b0; // se asigna un 0 al ultimo sumador de la primera fila siempre
generate
for(CurrentRow=0; CurrentRow<NUM_BITS-1;CurrentRow=CurrentRow+1)
begin:MULTIROW
assign wCarry[CurrentRow][0]=0;
for(CurrentCol=0; CurrentCol<NUM_BITS;CurrentCol=CurrentCol+1)
begin:MULTICOL
// Se guardan en Temp_results los primeros numeros en entrar a la primera fila de sumadores
if(CurrentRow==0 & CurrentCol<NUM_BITS-1)
begin
assign Temp_results[0][CurrentCol]=A[CurrentCol+1]&B[0];
end
// Caso de los sumadores intermedios:
//Se instancian de la forma que tomen sus sumandos de Temp_Result (previos)
//y se guardan sus resultados tanto en Temp_Result como en wCarry para cablear el resto de
// sumadores y niveles.
if(CurrentCol<(NUM_BITS-1))
begin
if(CurrentCol==0)
begin
adder Circuit_Adders(
.a(A[0]&B[CurrentRow+1]),
.b(Temp_results[CurrentRow][0]),
.s(oResult[CurrentRow+1]),
.ci(wCarry[ CurrentRow ][ 0 ] ),
.co(wCarry[ CurrentRow ][ 1 ] )
);
end
else
begin
adder Circuit_Adders(
.a(A[CurrentCol]&B[CurrentRow+1]),
.b(Temp_results[CurrentRow][CurrentCol]),
.s(Temp_results[CurrentRow+1][CurrentCol-1]),
.ci(wCarry[ CurrentRow ][ CurrentCol ] ),
.co(wCarry[ CurrentRow ][ CurrentCol + 1])
);
end
end
//Caso del ultimo bloque sumador por fila:
// Este es especial ya que su carry out se guarda en los Tem_Results para poder
// sumarselo al ultimo bloque del siguiente nivel.
if(CurrentCol==(NUM_BITS-1) & CurrentRow<NUM_BITS-2)
begin
adder Circuit_Adders(
.a(A[CurrentCol]&B[CurrentRow+1]),
.b(Temp_results[CurrentRow][CurrentCol]),
.s(Temp_results[CurrentRow+1][CurrentCol-1]),
.ci(wCarry[ CurrentRow ][ CurrentCol ] ),
.co(Temp_results[ CurrentRow + 1 ][ CurrentCol])
);
end
if(CurrentRow==NUM_BITS-2)
begin
assign oResult[CurrentCol+NUM_BITS]=Temp_results[CurrentRow+1][CurrentCol];
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 512; const int INF = 0x3f3f3f3f; long long dis[MAXN][MAXN], a[MAXN], ans[MAXN]; bool in[MAXN]; int n; void Floyd() { for (int k = n; k >= 1; k--) { int t = a[k]; in[t] = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dis[i][j] = min(dis[i][j], dis[i][t] + dis[t][j]); if (in[i] && in[j]) ans[k] += dis[i][j]; } } } for (int i = 1; i <= n; i++) printf( %lld , ans[i]); puts( ); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { scanf( %lld , &dis[i][j]); } } for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } Floyd(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_BEHAVIORAL_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Flow generator - IP packet generator module
*/
module fg_ip_packet_gen #(
parameter DEST_WIDTH = 8,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter MAC_PREFIX = 48'hDA0000000000,
parameter IP_PREFIX = 32'hc0a80100
)
(
input wire clk,
input wire rst,
/*
* Burst descriptor input
*/
input wire input_bd_valid,
output wire input_bd_ready,
input wire [DEST_WIDTH-1:0] input_bd_dest,
input wire [31:0] input_bd_burst_len,
/*
* IP output
*/
output wire output_ip_hdr_valid,
input wire output_ip_hdr_ready,
output wire [47:0] output_ip_eth_dest_mac,
output wire [47:0] output_ip_eth_src_mac,
output wire [15:0] output_ip_eth_type,
output wire [5:0] output_ip_dscp,
output wire [1:0] output_ip_ecn,
output wire [15:0] output_ip_length,
output wire [15:0] output_ip_identification,
output wire [2:0] output_ip_flags,
output wire [12:0] output_ip_fragment_offset,
output wire [7:0] output_ip_ttl,
output wire [7:0] output_ip_protocol,
output wire [31:0] output_ip_source_ip,
output wire [31:0] output_ip_dest_ip,
output wire [DATA_WIDTH-1:0] output_ip_payload_tdata,
output wire [KEEP_WIDTH-1:0] output_ip_payload_tkeep,
output wire output_ip_payload_tvalid,
input wire output_ip_payload_tready,
output wire output_ip_payload_tlast,
output wire output_ip_payload_tuser,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [15:0] frame_mtu,
input wire dest_wr_en,
input wire [DEST_WIDTH-1:0] dest_index,
input wire [47:0] dest_mac,
input wire [31:0] dest_ip
);
reg output_ip_hdr_valid_reg = 0;
reg [15:0] output_ip_length_reg = 0;
reg [47:0] output_ip_eth_dest_mac_reg = 0;
reg [31:0] output_ip_dest_ip_reg = 0;
reg [47:0] mem_mac[2**DEST_WIDTH-1:0];
reg [31:0] mem_ip[2**DEST_WIDTH-1:0];
integer i;
initial begin
for (i = 0; i < 2**DEST_WIDTH; i = i + 1) begin
mem_mac[i] <= MAC_PREFIX + i;
mem_ip[i] <= IP_PREFIX + i;
end
end
wire pkt_hdr_valid;
wire [7:0] pkt_hdr_dest;
wire [15:0] pkt_hdr_len;
assign output_ip_hdr_valid = output_ip_hdr_valid_reg;
assign output_ip_eth_dest_mac = output_ip_eth_dest_mac_reg;
assign output_ip_eth_src_mac = local_mac;
assign output_ip_eth_type = 16'h0800;
assign output_ip_dscp = 0;
assign output_ip_ecn = 0;
assign output_ip_length = output_ip_length_reg;
assign output_ip_identification = 0;
assign output_ip_flags = 3'b010;
assign output_ip_fragment_offset = 0;
assign output_ip_ttl = 64;
assign output_ip_protocol = 8'h11;
assign output_ip_source_ip = local_ip;
assign output_ip_dest_ip = output_ip_dest_ip_reg;
fg_packet_gen #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
)
fg_packet_gen_inst (
.clk(clk),
.rst(rst),
.input_bd_valid(input_bd_valid),
.input_bd_ready(input_bd_ready),
.input_bd_dest(input_bd_dest),
.input_bd_burst_len(input_bd_burst_len),
.output_hdr_valid(pkt_hdr_valid),
.output_hdr_ready(output_ip_hdr_ready),
.output_hdr_dest(pkt_hdr_dest),
.output_hdr_len(pkt_hdr_len),
.output_payload_tdata(output_ip_payload_tdata),
.output_payload_tkeep(output_ip_payload_tkeep),
.output_payload_tvalid(output_ip_payload_tvalid),
.output_payload_tready(output_ip_payload_tready),
.output_payload_tlast(output_ip_payload_tlast),
.output_payload_tuser(output_ip_payload_tuser),
.busy(busy),
.payload_mtu(frame_mtu-20)
);
always @(posedge clk) begin
if (rst) begin
output_ip_hdr_valid_reg <= 0;
output_ip_eth_dest_mac_reg <= 0;
output_ip_dest_ip_reg <= 0;
end else begin
if (pkt_hdr_valid & ~output_ip_hdr_valid) begin
output_ip_hdr_valid_reg <= 1;
output_ip_length_reg <= pkt_hdr_len + 20;
output_ip_eth_dest_mac_reg <= mem_mac[pkt_hdr_dest];
output_ip_dest_ip_reg <= mem_ip[pkt_hdr_dest];
end else begin
output_ip_hdr_valid_reg <= output_ip_hdr_valid_reg & ~output_ip_hdr_ready;
end
if (dest_wr_en) begin
mem_mac[dest_index] <= dest_mac;
mem_ip[dest_index] <= dest_ip;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; istream& in = cin; int n; int a[1000010]; void input() { in >> n; for (int i = 1; i <= n; ++i) in >> a[i]; } long long mod = (long long)1e9 + 7; long long fac[1000010], inv[1000010]; long long quick_mod(long long a, long long p) { long long ret = 1; a %= mod; while (p) { if (p & 1) ret = ret * a % mod; a = a * a % mod; p /= 2; } return ret; } long long C(int n, int m) { return fac[n] * inv[m] % mod * inv[n - m] % mod; } long long cale(int k) { long long large = fac[k]; long long less = 1; less = fac[n] * inv[k + 1] % mod; return large * less % mod; } int main() { fac[0] = 1; for (int i = 1; i < 1000010; ++i) fac[i] = fac[i - 1] * i % mod; inv[1000009] = quick_mod(fac[1000009], mod - 2); for (int i = 1000008; i >= 0; --i) inv[i] = inv[i + 1] * (i + 1) % mod; int TEST_CASE = 1; while (TEST_CASE-- > 0) { input(); sort(a + 1, a + n + 1); long long ans = 0; a[0] = -1; int pos = 1, K = n; while (pos <= n) { int val = a[pos]; int num = 0; while (a[pos] == val) { pos++; num++; } if (val != a[n]) ans = (ans + cale(K - 1) * num % mod * val % mod) % mod; K -= num; } cout << ans << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/07/2016 09:24:55 AM
// Design Name:
// Module Name: Deslinealizador
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESLINEALIZADOR#(parameter P = 32)(
input wire CLK, //system clock
input wire [P-1:0] T, //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
input wire RST_EX, //system reset
input wire Begin_FSM_EX, //INICIAL EL CALCULO
output wire ACK_EX, //INDICA QUE EL CALCULO FUE REALIZADO
output wire ACK_SUMX,
output wire ACK_SUMY,
output wire ACK_SUMZ,
output wire ACK_MULT,
output wire O_FX, //BANDERA DE OVER FLOW X
output wire O_FY, //BANDERA DE OVER FLOW Y
output wire O_FZ, //BANDERA DE OVER FLOW Z
output wire O_Fmult, //BANDERA DE OVER FLOW MULT
output wire U_FX, //BANDERA DE UNDER FLOW X
output wire U_FY, //BANDERA DE UNDER FLOW Y
output wire U_FZ, //BANDERA DE UNDER FLOW Z
output wire U_Fmult, //BANDERA DE UNDER FLOW MULT
output wire [P-1:0] RESULT //RESULTADO FINAL
);
wire [4:0] CONT_ITERA;
wire RST;
wire MS_1;
wire [1:0] MS_M;
wire EN_REG3;
wire EN_REG4;
wire ADD_SUBT;
wire Begin_SUMX;
wire Begin_SUMY;
wire Begin_SUMZ;
wire Begin_MULT;
wire EN_REG1X;
wire EN_REG1Y;
wire EN_REG1Z;
wire [1:0] MS_2;
wire EN_REG2;
wire CLK_CDIR;
wire EN_REG2XYZ;
// wire ACK_SUMX;
// wire ACK_SUMY;
// wire ACK_SUMZ;
wire EN_MS1;
wire EN_MS2;
wire EN_MS_M;
wire EN_ADDSUBT;
wire [1:0] MS_M_reg;
wire MS_1_reg;
wire [1:0] MS_2_reg;
wire ADD_SUBT_reg;
assign BeginSUMX = Begin_SUMX;
assign BeginSUMY = Begin_SUMY;
assign BeginSUMZ = Begin_SUMZ;
assign BeginMULT = Begin_MULT;
//assign MS_Mreg = MS_M_reg;
//assign MS_1reg = MS_1_reg;
//assign MS_2reg = MS_2_reg;
Coprocesador_CORDIC C_CORDIC_EX (
.T(T),
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST),
.MS_M(MS_M_reg),
.MS_1(MS_1_reg),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT_reg),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.Begin_MULT(Begin_MULT),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2_reg),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_SUMX(ACK_SUMX),
.ACK_SUMY(ACK_SUMY),
.ACK_SUMZ(ACK_SUMZ),
.ACK_MULT(ACK_MULT),
.O_FX(O_FX),
.U_FX(U_FX),
.O_FY(O_FY),
.U_FY(U_FY),
.O_FZ(O_FZ),
.U_FZ(U_FZ),
.O_Fmult(O_Fmult),
.U_Fmult(U_Fmult),
.RESULT(RESULT),
.CONT_ITERA(CONT_ITERA)
);
FF_D #(.P(1)) REG_ADDSUBTL( //#(.P(1))
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_ADDSUBT), //ENABLE
.D(ADD_SUBT), //ENTRADA
.Q(ADD_SUBT_reg) //SALIDA
);
FF_D #(.P(2)) REG_MS_M(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS_M), //ENABLE
.D(MS_M), //ENTRADA
.Q(MS_M_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_1(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
FF_D #(.P(2)) REG_MS_2(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS2), //ENABLE
.D(MS_2), //ENTRADA
.Q(MS_2_reg) //SALIDA
);
FSM_C_CORDIC M_E_EX (
.CLK(CLK), //RELOJ DEL SISTEMA
.RST_EX(RST_EX), //system reset
.ACK_ADD_SUBTX(ACK_SUMX),
.ACK_ADD_SUBTY(ACK_SUMY),
.ACK_ADD_SUBTZ(ACK_SUMZ),
.ACK_MULT(ACK_MULT),
.Begin_FSM_EX(Begin_FSM_EX),
.CONT_ITER(CONT_ITERA),
.RST(RST),
.MS_M(MS_M),
.MS_1(MS_1),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.Begin_MULT(Begin_MULT),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_EX(ACK_EX),
.EN_ADDSUBT(EN_ADDSUBT),
.EN_MS_M(EN_MS_M),
.EN_MS1(EN_MS1),
.EN_MS2(EN_MS2)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_BLACKBOX_V
`define SKY130_FD_SC_HS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void checkMin(T &a, T b) { if (b < a) a = b; } template <class T> inline void checkMax(T &a, T b) { if (a < b) a = b; } template <class T> inline T Min(T a, T b) { return a < b ? a : b; } template <class T> inline T Max(T a, T b) { return a > b ? a : b; } template <class T> inline T Myabs(T a) { return a > 0 ? a : -a; } const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; const int inf = 0x3f3f3f3f; const long long linf = 1LL << 60; const double pi = acos(-1.0); const double eps = 1e-9; const int mod = 100000007; const int maxn = 10010; int n, r, c; char ch[maxn], s[maxn]; void print(int v) { if (v) { print((v - 1) / 26); printf( %c , A + (v - 1) % 26); } } int main() { scanf( %d , &n); for (int cas = 1; cas <= n; cas++) { scanf( %s , ch); if (sscanf(ch, R%dC%d , &r, &c) == 2) { print(c); printf( %d n , r); } else { sscanf(ch, %[^0-9]%d , s, &r); int ans = 0; for (int i = 0; s[i]; i++) ans *= 26, ans += s[i] - A + 1; printf( R%dC%d n , r, ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int mat[1005][1005]; long long cols[1000005]; long long rows[1000005]; priority_queue<long long> pq; int main() { int n, m; long long k, p; scanf( %d %d %lld %lld , &n, &m, &k, &p); for (int i = 0; i < n; i++) { long long sum = 0; for (int j = 0; j < m; j++) { scanf( %d , &mat[i][j]); sum += mat[i][j]; } pq.push(sum); } for (int i = 1; i <= k; i++) { long long val = pq.top(); pq.pop(); pq.push(val - p * m); rows[i] = rows[i - 1] + val; } while (pq.size()) pq.pop(); for (int i = 0; i < m; i++) { long long sum = 0; for (int j = 0; j < n; j++) { sum += mat[j][i]; } pq.push(sum); } for (int i = 1; i <= k; i++) { long long val = pq.top(); pq.pop(); pq.push(val - p * n); cols[i] = cols[i - 1] + val; } long long ans = -1e18; for (long long i = 0; i <= k; i++) { ans = max(ans, rows[i] + cols[k - i] - i * (k - i) * p); } printf( %lld n , ans); return 0; }
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAM (
address,
clock,
data,
wren,
q);
input [9:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../Modules/RAM_Init.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../Modules/RAM_Init.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../Modules/RAM_Init.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; struct node { long k, na; }; const long maxn = 100001; node a[maxn]; long n, b[maxn]; int qsort(long low, long high) { long i = low, j = high, x = a[(i + j) / 2].k; while (i < j) { while (a[i].k < x) i++; while (a[j].k > x) j--; if (i <= j) { swap(a[i], a[j]); i++; j--; } } if (i < high) qsort(i, high); if (j > low) qsort(low, j); return 0; } void init() { cin >> n; for (long i = 1; i <= n; i++) { cin >> a[i].k; a[i].na = i; } qsort(1, n); } void work() { memset(b, 0, sizeof(b)); for (long i = 1; i <= n; i++) b[a[i].k] += 1; int bj = 1; for (long i = 2; i <= a[n].k; i++) if (b[i] > b[i - 1]) bj = 0; if (bj) { cout << b[1] << endl; long s = 0; for (long i = 1; i <= n; i++) { if ((i == 1) || (a[i].k == a[i - 1].k)) s++; else s = 1; b[a[i].na] = s; } for (long i = 1; i <= n; i++) { cout << b[i]; if (i != n) cout << ; } cout << endl; } else cout << -1 << endl; } int main() { init(); work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 * 2 + 10; int n, len, h; struct node { int flag, mx, l, r; } t[MAXN << 2]; int a[MAXN], b[MAXN]; int L[MAXN]; void push_down(int k) { if (t[k].flag) { t[k << 1].flag += t[k].flag; t[k << 1 | 1].flag += t[k].flag; t[k << 1].mx += t[k].flag; t[k << 1 | 1].mx += t[k].flag; t[k].flag = 0; } } void push_up(int k) { t[k].mx = min(t[k << 1].mx, t[k << 1 | 1].mx); } void build(int l, int r, int k) { t[k].l = l; t[k].r = r; t[k].flag = 0; if (t[k].l == t[k].r) { t[k].mx = -t[k].l; return; } int mid = t[k].l + t[k].r >> 1; build(l, mid, k << 1); build(mid + 1, r, k << 1 | 1); push_up(k); } void update(int l, int r, int val, int k) { if (l <= t[k].l && t[k].r <= r) { t[k].mx += val; t[k].flag += val; return; } push_down(k); int mid = t[k].l + t[k].r >> 1; if (l <= mid) update(l, r, val, k << 1); if (r > mid) update(l, r, val, k << 1 | 1); push_up(k); } int main() { scanf( %d%d%d , &n, &len, &h); for (int i = 1; i <= len; i++) scanf( %d , b + i); sort(b + 1, b + len + 1); build(1, len, 1); for (int i = 1; i <= n; i++) { scanf( %d , a + i); int ll = 1, rr = len, ans = -1; while (ll <= rr) { int mid = ll + rr >> 1; if (b[mid] + a[i] >= h) { ans = mid; rr = mid - 1; } else ll = mid + 1; } L[i] = ans; } int res = 0; for (int i = 1; i <= n; i++) { if (L[i] != -1) update(L[i], len, 1, 1); if (i >= len) { if (t[1].mx >= 0) res++; if (L[i - len + 1] != -1) update(L[i - len + 1], len, -1, 1); } } printf( %d n , res); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_2_V
`define SKY130_FD_SC_MS__MUX2_2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_2_V
|
#include <bits/stdc++.h> using namespace std; struct Node { int num, cnt; friend bool operator<(const Node &n1, const Node &n2) { if (n1.cnt != n2.cnt) return n1.cnt < n2.cnt; else return n1.num < n2.num; } }; set<Node> cur, tmp; vector<int> xx, num; map<int, int> mp; int main() { int n, x; scanf( %d%d , &n, &x); if (x == 0 && n == 2) { puts( NO ); return 0; } while (x > 0) { xx.push_back(x % 2); x /= 2; } int sz = xx.size(); int pre = 0; cur.insert({0, n}); int idx = 0; while (true) { int need; if (idx < sz) { need = xx[idx]; } else need = 0; tmp.clear(); int tar = need, now = 0; for (auto o : cur) { int zc = o.num * 2, cc = o.cnt; if (cc / 2 > 0) tmp.insert({zc + 1, cc / 2}); if ((cc + 1) / 2 > 0) tmp.insert({zc, (cc + 1) / 2}); now ^= ((cc / 2) % 2); } if (tar != now) { for (auto o : cur) { int zc = o.num * 2, cc = o.cnt; if (cc == 1) { tmp.erase({zc, (cc + 1) / 2}); tmp.insert({zc + 1, cc / 2 + 1}); } else { tmp.erase({zc, (cc + 1) / 2}); tmp.erase({zc + 1, cc / 2}); if ((cc + 1) / 2 > 1) tmp.insert({zc, (cc + 1) / 2 - 1}); tmp.insert({zc + 1, cc / 2 + 1}); } break; } } cur.clear(); for (auto o : tmp) { cur.insert(o); } idx++; int siz = cur.size(); if (siz == n && idx >= sz) break; } vector<int> ans; bool ok = true; for (auto o : cur) { int t = o.num, res = 0; for (int i = 1; i <= idx; i++) { int now = t % 2; res = res * 2 + now; t /= 2; } ans.push_back(res); if (res > 1000000) { ok = false; break; } } if (!ok) { puts( NO ); } else { int ord = 0; puts( YES ); for (auto o : ans) { if (ord != 0) putchar( ); printf( %d , o); ord++; } puts( ); } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_rml_inc3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sparc_exu_rml_inc3 (/*AUTOARG*/
// Outputs
dout,
// Inputs
din, inc
) ;
input [2:0] din;
input inc;
output [2:0] dout;
assign dout[2] = ((~din[2] & ~din[1] & ~din[0] & ~inc) |
(~din[2] & din[1] & din[0] & inc) |
(din[2] & din[1] & ~din[0]) |
(din[2] & ~din[1] & inc) |
(din[2] & din[0] & ~inc));
assign dout[1] = ((~din[1] & ~din[0] & ~inc) |
(din[1] & ~din[0] & inc) |
(~din[1] & din[0] & inc) |
(din[1] & din[0] & ~inc));
assign dout[0] = ~din[0];
endmodule // sparc_exu_rml_inc3
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module acc
#(parameter IWIDTH=16, OWIDTH=30)
(input clk,
input clear,
input acc,
input [IWIDTH-1:0] in,
output reg [OWIDTH-1:0] out);
wire [OWIDTH-1:0] in_signext;
sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH))
acc_signext (.in(in),.out(in_signext));
// CLEAR & ~ACC --> clears the accumulator
// CLEAR & ACC --> loads the accumulator
// ~CLEAR & ACC --> accumulates
// ~CLEAR & ~ACC --> hold
wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
wire [OWIDTH-1:0] sum_int = addend1 + addend2;
always @(posedge clk)
out <= sum_int;
endmodule // acc
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 + 5; int N, P[MAXN]; long long D[MAXN]; vector<pair<long long, int>> v, f[2]; int main() { scanf( %d , &N); P[1] = 1, P[2] = 2; for (int i = 3, x; i <= N; ++i) { printf( 2 1 %d %d n , P[2], i); fflush(stdout); scanf( %d , &x); if (x == -1) P[2] = i; } for (int i = 2; i <= N; ++i) { if (i == P[2]) continue; printf( 1 1 %d %d n , P[2], i); fflush(stdout); scanf( %lld , &D[i]); v.push_back(make_pair(D[i], i)); } sort(v.begin(), v.end()); int p = v.back().second; for (int i = 2, x; i <= N; ++i) { if (i == p || i == P[2]) continue; printf( 2 1 %d %d n , p, i); fflush(stdout); scanf( %d , &x); f[x == -1].push_back(make_pair(D[i], i)); } sort(f[0].begin(), f[0].end()); sort(f[1].begin(), f[1].end()); printf( 0 %d %d , P[1], P[2]); for (int i = 0; i < f[1].size(); ++i) printf( %d , f[1][i].second); printf( %d , p); for (int i = f[0].size() - 1; i >= 0; --i) printf( %d , f[0][i].second); fflush(stdout); return 0; }
|
// creates an array of shift registers, with independently
// controlled three input muxes,
// 0=keep value, 1=get prev value,2=set new value
//
//
`include "bsg_defines.v"
module bsg_fifo_shift_datapath #(parameter `BSG_INV_PARAM( width_p )
,parameter `BSG_INV_PARAM(els_p )
,parameter default_p = { (width_p) {1'b0} }
)
(input clk_i
, input [width_p-1:0] data_i
, input [els_p-1:0][1:0] sel_i
, output [width_p-1:0] data_o
);
genvar i;
logic [els_p:0][width_p-1:0] r, r_n;
assign r[els_p] = default_p;
for (i = 0; i < els_p; i=i+1)
begin: el
always_comb
begin
unique case (sel_i[i])
2'b01:
r_n[i] = r[i+1];
2'b10:
r_n[i] = data_i;
default:
r_n[i] = r[i];
endcase
end
always_ff @(posedge clk_i)
r[i] <= r_n[i];
end
assign data_o = r[0];
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_shift_datapath)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_SYMBOL_V
`define SKY130_FD_SC_HS__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int tot; struct node { node *ch[26], *fail; int len, id; node* init(int tlen) { memset(ch, 0, sizeof(ch)); fail = NULL; len = tlen; return this; } } * root, spT[N]; vector<int> g[N]; void addin(char* c) { node* tmp = root; while (*c != 0 ) { int t = *c - a ; if (tmp->ch[t] == NULL) tmp->ch[t] = spT[++tot].init(tmp->len + 1); tmp = tmp->ch[t]; c++; } } queue<node*> q; int en, st; void getfail() { q.push(root); while (!q.empty()) { node* tmp = q.front(); q.pop(); for (int t = 0; t < 26; t++) if (tmp->ch[t] != NULL) { if (tmp == root) tmp->ch[t]->fail = root; else { node* p = tmp->fail; while (p != root && p->ch[t] == NULL) p = p->fail; if (p->ch[t] != NULL) tmp->ch[t]->fail = p->ch[t]; else tmp->ch[t]->fail = root; } q.push(tmp->ch[t]); } } } char S[N]; int f[N][2]; int dfs(int x) { f[x][0] = 0; f[x][1] = 1; for (auto p : g[x]) { dfs(p); f[x][1] += f[p][0]; f[x][0] += max(f[p][0], f[p][1]); } return max(f[x][0], f[x][1]); } bool v[N]; int main() { int T, n; for (int i = (1); i <= (N - 1); i++) spT[i].id = i; cin >> T; while (T--) { root = spT[tot = 1].init(0); cin >> n; for (int i = (1); i <= (n); i++) { scanf( %s , S); addin(S); } getfail(); for (int i = (1); i <= (tot); i++) g[i].clear(), v[i] = 0; for (int i = (1); i <= (tot); i++) { node* tmp = &spT[i]; if (tmp->fail && tmp->fail != root && tmp->fail->len + 1 == tmp->len) { g[tmp->fail->id].push_back(tmp->id); v[tmp->id] = 1; } } int ans = 0; for (int i = (2); i <= (tot); i++) if (!v[i]) ans += dfs(i); cout << ans << endl; } return 0; }
|
`include "route_compute.v"
module test_route_compute ();
reg [12:0] inc;
reg [1:0] addrx;
reg [1:0] addry;
reg [1:0] addrx_max;
reg [1:0] addry_max;
wire [3:0] rmatrix;
reg clock;
reg [2:0] test;
RouteCompute rc(inc, addrx, addry, addrx_max, addry_max, clock, rmatrix);
always
#10 clock = ~clock;
always @(negedge clock) begin
$display("Bits: |V|SRC |DST |AGE |");
$display("Input: |%b|%b|%b|%b|", inc[12], inc[11:8],
inc[7:4], inc[3:0]);
$display("Dirs |N|S|E|W|");
$display("Matrix |%b|%b|%b|%b|", rmatrix[0], rmatrix[1],
rmatrix[2], rmatrix[3]);
$display("");
end
initial begin
clock = 0;
inc = 13'h1000;
addrx = 2'b01;
addry = 2'b01;
addrx_max = 2'b11;
addry_max = 2'b11;
@(negedge clock)
$display("West and North");
inc = 13'b1_1010_0000_0000;
@(negedge clock)
$display("Equal and North");
inc = 13'b1_1010_0100_0000;
@(negedge clock)
$display("Equal and North/South");
inc = 13'b1_1010_0111_0000;
@(negedge clock)
$display("West and Equal");
inc = 13'b1_1010_0001_0000;
@(negedge clock)
$display("East/West and Equal");
inc = 13'b1_1010_1101_0000;
@(negedge clock)
$display("East/West and North");
inc = 13'b1_1010_1100_0000;
@(negedge clock)
$display("West and North/South");
inc = 13'b1_1010_0011_0000;
//@(negedge clock)
//$display("South and West");
//inc = 13'b1_1010_1100_0000;
@(negedge clock)
$display("Equal and Equal");
inc = 13'b1_1010_0101_0000;
@(negedge clock)
$finish;
end
endmodule
|
#include <bits/stdc++.h> clock_t t = clock(); namespace my_std { using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> inline T rnd(T l, T r) { return uniform_int_distribution<T>(l, r)(rng); } template <typename T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } template <typename T> inline bool chkmin(T &x, T y) { return x > y ? x = y, 1 : 0; } template <typename T> inline void read(T &t) { t = 0; char f = 0, ch = getchar(); double d = 0.1; while (ch > 9 || ch < 0 ) f |= (ch == - ), ch = getchar(); while (ch <= 9 && ch >= 0 ) t = t * 10 + ch - 48, ch = getchar(); if (ch == . ) { ch = getchar(); while (ch <= 9 && ch >= 0 ) t += d * (ch ^ 48), d *= 0.1, ch = getchar(); } t = (f ? -t : t); } template <typename T, typename... Args> inline void read(T &t, Args &...args) { read(t); read(args...); } char __sr[1 << 21], __z[20]; int __C = -1, __zz = 0; inline void Ot() { fwrite(__sr, 1, __C + 1, stdout), __C = -1; } inline void print(register int x) { if (__C > 1 << 20) Ot(); if (x < 0) __sr[++__C] = - , x = -x; while (__z[++__zz] = x % 10 + 48, x /= 10) ; while (__sr[++__C] = __z[__zz], --__zz) ; __sr[++__C] = n ; } void file() {} inline void chktime() {} long long ksm(long long x, int y) { long long ret = 1; for (; y; y >>= 1, x = x * x) if (y & 1) ret = ret * x; return ret; } } // namespace my_std using namespace my_std; int n, K; vector<int> bl[30100]; int ok[30100]; struct hh { int t, nxt; } edge[30100]; int head[30100], ecnt; void make_edge(int f, int t) { edge[++ecnt] = (hh){t, head[f]}; head[f] = ecnt; } int vis[30100]; int pth[30100], c; void dfs(int x) { for (int &i = head[x], t; (t = i); i = edge[i].nxt) if (!vis[i]) vis[i] = 1, dfs(edge[i].t), pth[++c] = edge[t].t; } int ask(int x) { printf( ? %d n , x); fflush(stdout); char c; cin >> c; return c == Y ; } void add(int id, int flg) { for (int i = (0); i <= (K - 1); i++) ok[bl[id][i]] &= !(flg & ask(bl[id][i])); } void add2(int id, int flg) { int p = -1; for (int i = (K - 1); i >= (0); i--) if (ok[bl[id][i]]) p = i; if (p == -1) { for (int i = (0); i <= (K - 1); i++) ask(bl[id][i]); return; } if (p == 0) { for (int i = (0); i <= (K - 1); i++) if (ok[bl[id][i]]) ok[bl[id][i]] &= !(flg & ask(bl[id][i])); else ask(bl[id][p]); } else { ok[bl[id][p]] &= !(flg & ask(bl[id][p])); for (int i = (1); i <= (p); i++) ask(bl[id][p]); for (int i = (p + 1); i <= (K - 1); i++) if (ok[bl[id][i]]) ok[bl[id][i]] &= !(flg & ask(bl[id][i])); else ask(bl[id][p]); } } void work(int t) { int n = ::n / K; for (int i = (1); i <= (n); i++) for (int j = (i + 1); j <= (n); j++) make_edge(i, j); for (int i = (1); i <= (n / 2); i++) for (int j = (1); j <= (n - 2 * i + 1); j++) make_edge(n - i + 1, i); dfs(1); pth[++c] = 1; reverse(pth + 1, pth + c + 1); --c; add(1, !t); for (int i = (2); i <= (c); i++) t ? add2(pth[i], pth[i] > pth[i - 1]) : add(pth[i], pth[i] > pth[i - 1]); for (int i = (1); i <= (ecnt); i++) vis[i] = 0; c = ecnt = 0; for (int i = (1); i <= (n); i++) head[i] = 0; } int main() { read(n, K); for (int i = (1); i <= (n); i++) ok[i] = 1; for (int i = (1); i <= (n / K); i++) for (int j = ((i - 1) * K + 1); j <= (i * K); j++) bl[i].push_back(j); work(0); for (int i = (1); i <= (n / K); i++) reverse(bl[i].begin(), bl[i].end()); if (K != n) work(1); int ans = 0; for (int i = (1); i <= (n); i++) ans += ok[i]; printf( ! %d n , ans); fflush(stdout); return 0; }
|
#include <bits/stdc++.h> using namespace ::std; int main() { long long int temp, q, v1, v2, t, d, i, sum = 0; cin >> v1 >> v2 >> t >> d; long long int a[t]; sum = d * (t - 1); i = 0; temp = 0; bool ff = false; while (1) { if (!ff) { i += v1; a[temp] = i; temp++; ff = true; continue; } else if (i + d - sum + d <= v2) { i += d; sum -= d; a[temp] = i; } else { for (long long int k = d - 1; k >= -d; k--) { if (i + k - sum + d <= v2) { i += k; sum -= d; a[temp] = i; break; } } } temp++; if (temp == t) break; } long long int s = 0; for (long long int j = 0; j < t; j++) s += a[j]; cout << s; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.