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#include <bits/stdc++.h> using namespace std; const int MAXN = 2 * 100 * 1000 + 100; int n, dp[MAXN], d[MAXN], mark[MAXN], ans[MAXN], D = 0, MIN = MAXN; pair<int, int> par[MAXN]; vector<pair<int, int> > g[MAXN]; vector<int> q, depth[MAXN], res; void bfs() { for (int i = 0; i < q.size(); i++) { int v = q[i]; for (int j = 0; j < g[v].size(); j++) { int u = g[v][j].first; if (!mark[u]) { mark[u] = true; par[u] = make_pair(v, (g[v][j].second + 1) % 2); d[u] = d[v] + 1; D = max(D, d[u]); depth[d[u]].push_back(u); q.push_back(u); } } } } int main() { cin >> n; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; x--, y--; g[x].push_back(make_pair(y, 0)); g[y].push_back(make_pair(x, 1)); } d[0] = 0; mark[0] = true; q.push_back(0); depth[0].push_back(0); bfs(); for (int i = D - 1; i >= 0; i--) { for (int j = 0; j < depth[i].size(); j++) { int v = depth[i][j]; for (int z = 0; z < g[v].size(); z++) { int u = g[v][z].first; if (u != par[v].first) dp[v] += dp[u] + g[v][z].second; } } } ans[0] = dp[0]; MIN = ans[0]; for (int i = 1; i <= D; i++) { for (int j = 0; j < depth[i].size(); j++) { int v = depth[i][j]; int p = par[v].first; ans[v] = ans[p]; if (par[v].second == 0) ans[v] -= 1; else ans[v] += 1; MIN = min(ans[v], MIN); } } cout << MIN << endl; for (int i = 0; i < n; i++) if (ans[i] == MIN) cout << i + 1 << ; return 0; }
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#include <bits/stdc++.h> using namespace std; bool isprime(int n) { for (int i = 2; i < n; i++) { if (n % i == 0) { return false; } } return true; } int main() { int n; cin >> n; string s; cin >> s; int diff = 1; int i = 0; while (i < n) { cout << s[i]; i = i + diff; diff++; } }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_TB_V
`define SKY130_FD_SC_HS__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 D = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 D = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 D = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_TB_V
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#include <bits/stdc++.h> using namespace std; const int N = 45; int nd, nm, G[N][N]; int cntClique, pts[N], res[N], cnt[N]; map<string, int> H; int n; vector<int> v; bool dfs(int pos, int num) { for (int i = pos + 1; i <= n; ++i) { if (cnt[i] + num <= cntClique) return false; if (G[pos][i]) { int ok = 1; for (int id = 1; id <= num; ++id) { if (!G[i][pts[id]]) { ok = 0; break; } } if (ok) { pts[num + 1] = i; if (dfs(i, num + 1)) return true; } } } if (num > cntClique) { for (int i = 1; i <= num; ++i) { res[i] = pts[i]; } cntClique = num; return true; } return false; } void maxClique() { cntClique = -1; for (int i = n; i > 0; --i) { pts[1] = i; dfs(i, 1); cnt[i] = cntClique; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); memset(G, 1, sizeof G); cin >> nd >> nm; for (int i = 1; i <= nd; ++i) { int op; string s; cin >> op; if (op == 1) { v.clear(); } else { cin >> s; if (!H.count(s)) { H[s] = ++n; } int y = H[s]; for (auto& x : v) { G[x][y] = 0; G[y][x] = 0; } v.push_back(y); } } maxClique(); if (cntClique < 0) { cout << 0 ; } else { cout << cntClique; } return 0; }
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#include <bits/stdc++.h> #pragma comment(linker, /stack:640000000 ) using namespace std; const double EPS = 1e-9; const int INF = 0x7f7f7f7f; const double PI = acos(-1.0); template <class T> inline T _abs(T n) { return ((n) < 0 ? -(n) : (n)); } template <class T> inline T _max(T a, T b) { return (!((a) < (b)) ? (a) : (b)); } template <class T> inline T _min(T a, T b) { return (((a) < (b)) ? (a) : (b)); } template <class T> inline T _swap(T& a, T& b) { a = a ^ b; b = a ^ b; a = a ^ b; } template <class T> inline T gcd(T a, T b) { return (b) == 0 ? (a) : gcd((b), ((a) % (b))); } template <class T> inline T lcm(T a, T b) { return ((a) / gcd((a), (b)) * (b)); } template <typename T> string NumberToString(T Number) { ostringstream second; second << Number; return second.str(); } struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; while (cin >> n) { priority_queue<pair<int, string> > pq; for (int i = (int)(1); i <= (int)(n); i++) { string st; int no; cin >> st >> no; pq.push(make_pair(-no, st)); } vector<pair<int, string> > v; int hh = 1; int flg = 1; while (!pq.empty()) { pair<int, string> p = pq.top(); pq.pop(); p.first *= -1; if (p.first == 0) { v.push_back(make_pair(hh, p.second)); hh++; continue; } vector<int> tmp; for (int i = (int)(0); i <= (int)((int)v.size() - 1); i++) { tmp.push_back(v[i].first); } sort(tmp.rbegin(), tmp.rend()); if (tmp.size() < p.first) { flg = 0; break; } int tmpNo = tmp[p.first - 1]; for (int i = (int)(0); i <= (int)((int)v.size() - 1); i++) { if (v[i].first >= tmpNo) v[i].first += 1; } v.push_back(make_pair(tmpNo, p.second)); } if (flg) { for (int i = (int)(0); i <= (int)(n - 1); i++) { cout << v[i].second << << v[i].first << n ; } } else printf( -1 n ); } return 0; }
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// main control unit thant gets
module mcu(clk, clr, OP, PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegWrite, RegDst);
input clk, clr;
input [5:0] OP;
output PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
reg PCWriteCond, PCWrite, IorD, MemRead, MemWrite, MemtoReg, IRWrite, ALUSrcA, RegWrite, RegDst;
output [1:0] PCSource, ALUOp, ALUSrcB;
reg [1:0] PCSource, ALUOp, ALUSrcB;
//reg [3:0] current_state;
//reg [3:0] next_state;
integer current_state;
integer next_state;
always @(current_state)
begin
case(current_state)
0:
begin
IorD = 0;
MemRead = 1;
MemWrite = 0;
IRWrite = 1;
ALUSrcA = 0;
ALUSrcB = 2'b01;
ALUOp = 2'b00;
PCWrite = 1;
PCWriteCond = 0;
RegWrite = 0;
MemtoReg = 0;
RegDst = 0;
#3;
PCSource = 2'b00;
end
1:
begin
ALUSrcA = 0;
ALUSrcB = 2'b11;
ALUOp = 2'b00;
IRWrite = 0;
MemRead = 0;
PCWrite = #1 0;
end
2:
begin
ALUSrcA = 1;
ALUSrcB = 2'b10;
ALUOp = 2'b00;
end
3:
begin
IorD = 1;
MemRead = 1;
end
4:
begin
MemtoReg = 1;
RegDst = 0;
RegWrite = 1;
MemRead = 0;
end
5:
begin
IorD = 1;
MemWrite = 1;
end
6:
begin
ALUSrcA = 1;
ALUSrcB = 2'b00;
ALUOp = 2'b10;
end
7:
begin
RegDst = 1;
RegWrite = 1;
MemtoReg = 0;
end
8:
begin
ALUSrcA = 1;
ALUSrcB = 2'b00;
ALUOp = 2'b01;
PCSource = 2'b01;
PCWriteCond = 1;
end
9:
begin
PCSource = 2'b10;
PCWrite = 1;
end
endcase
end
always @(posedge clk)
begin
//if (clr == 1'b0)
if (clr == 1'b1)
current_state = -1;
else
current_state = next_state;
end
always @(current_state or OP)
begin
next_state = -1;
case (current_state)
-1: next_state = 0;
0: next_state = 1;
1:
begin
case (OP)
6'b100011: next_state = 2;
6'b101011: next_state = 2;
0: next_state = 6;
4: next_state = 8;
2: next_state = 9;
endcase
end
2:
begin
case (OP)
6'b100011: next_state = 3;
6'b101011: next_state = 5;
endcase
end
3: next_state = 4;
4: next_state = 0;
5: next_state = 0;
6: next_state = 7;
7: next_state = 0;
8: next_state = 0;
9: next_state = 0;
default:
next_state = -1;
endcase
end
endmodule
module acu(funct, ALUOp, ALUcontrol);
input [5:0] funct;
input [1:0] ALUOp;
output [2:0] ALUcontrol;
reg [2:0] ALUcontrol;
always @(funct or ALUOp)
begin
case(ALUOp)
2'b00: ALUcontrol = 3'b010;
2'b01: ALUcontrol = 3'b110;
2'b10:
begin
case(funct)
6'b100000: ALUcontrol = 3'b010;
6'b100010: ALUcontrol = 3'b110;
6'b100100: ALUcontrol = 3'b000;
6'b100101: ALUcontrol = 3'b001;
6'b101010: ALUcontrol = 3'b111;
endcase
end
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int dif[n]; memset(dif, 0, sizeof(dif)); int ans = 0; for (int i = 1; i < n; i++) { int cnt = 1; int temp = a[i]; while (a[i - 1] > a[i]) { dif[i]++; a[i] = temp + cnt; cnt *= 2; } if (a[i] > a[i - 1] && dif[i]) { dif[i]--; a[i] = a[i - 1]; } ans = max(ans, dif[i]); } cout << ans << n ; } return 0; }
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// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_counter#(parameter WIDTH=32) (
input clock,
input resetn,
input i_start,
input i_counter_reset,
input [WIDTH-1:0] i_local_size[2:0],
input [WIDTH-1:0] i_global_size[2:0],
input [WIDTH-1:0] i_group_size[2:0],
// The counter values we export.
output reg [WIDTH-1:0] local_id[2:0],
output reg [WIDTH-1:0] global_id[2:0],
output reg [WIDTH-1:0] group_id[2:0],
output reg [WIDTH-1:0] scalar_local_id,
output reg [WIDTH-1:0] scalar_group_id,
output o_dataout_valid,
input i_dataout_stall
);
// This is the invariant relationship between the various ids.
// Keep these around for debugging.
wire [WIDTH-1:0] global_total = global_id[0] + i_global_size[0] * ( global_id[1] + i_global_size[1] * global_id[2] );
wire [WIDTH-1:0] local_total = local_id[0] + i_local_size[0] * ( local_id[1] + i_local_size[1] * local_id[2] );
// The issue signal starts the counter going, and will stop if stalled, or
// we've reached the maximum global size
wire issue;
reg done_counting;
assign issue = i_start & ~i_dataout_stall & ~done_counting;
assign o_dataout_valid = i_start && !i_counter_reset & ~done_counting;
function [WIDTH-1:0] incr_lid ( input [WIDTH-1:0] old_lid, input to_incr, input last );
if ( to_incr )
if ( last )
incr_lid = {WIDTH{1'b0}};
else
incr_lid = old_lid + 2'b01;
else
incr_lid = old_lid;
endfunction
//////////////////////////////////
// Handle local ids.
reg [WIDTH-1:0] max_local_id[2:0];
wire last_local_id[2:0];
assign last_local_id[0] = (local_id[0] == max_local_id[0] );
assign last_local_id[1] = (local_id[1] == max_local_id[1] );
assign last_local_id[2] = (local_id[2] == max_local_id[2] );
wire last_in_group;
assign last_in_group = last_local_id[0] & last_local_id[1] & last_local_id[2];
wire bump_local_id[2:0];
assign bump_local_id[0] = (max_local_id[0] != 0);
assign bump_local_id[1] = (max_local_id[1] != 0) && last_local_id[0];
assign bump_local_id[2] = (max_local_id[2] != 0) && last_local_id[0] && last_local_id[1];
// Local id register updates.
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
scalar_local_id <= {WIDTH{1'b0}};
max_local_id[0] <= {WIDTH{1'b0}};
max_local_id[1] <= {WIDTH{1'b0}};
max_local_id[2] <= {WIDTH{1'b0}};
end else if ( i_counter_reset ) begin
local_id[0] <= {WIDTH{1'b0}};
local_id[1] <= {WIDTH{1'b0}};
local_id[2] <= {WIDTH{1'b0}};
scalar_local_id <= {WIDTH{1'b0}};
max_local_id[0] <= i_local_size[0] - 2'b01;
max_local_id[1] <= i_local_size[1] - 2'b01;
max_local_id[2] <= i_local_size[2] - 2'b01;
end else
begin
if ( issue ) begin
local_id[0] <= incr_lid (local_id[0], bump_local_id[0], last_local_id[0]);
local_id[1] <= incr_lid (local_id[1], bump_local_id[1], last_local_id[1]);
local_id[2] <= incr_lid (local_id[2], bump_local_id[2], last_local_id[2]);
scalar_local_id <= (last_in_group) ? {WIDTH{1'b0}} : scalar_local_id + 2'b01;
end
end
end
//////////////////////////////////
// Handle global ids.
wire last_global_id[2:0];
assign last_global_id[0] = (global_id[0] == (i_global_size[0] - 2'b01) );
assign last_global_id[1] = (global_id[1] == (i_global_size[1] - 2'b01) );
assign last_global_id[2] = (global_id[2] == (i_global_size[2] - 2'b01) );
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
done_counting = 1'b0;
end else if ( i_counter_reset ) begin
done_counting = 1'b0;
end else begin
done_counting = i_start & ~i_dataout_stall & last_global_id[0] & last_global_id[1] & last_global_id[2] ? 1'b1 : done_counting;
end
end
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else if ( i_counter_reset ) begin
global_id[0] <= {WIDTH{1'b0}};
global_id[1] <= {WIDTH{1'b0}};
global_id[2] <= {WIDTH{1'b0}};
end else
begin
if ( issue ) begin
if (last_in_group) begin
global_id[0] <= last_global_id[0] ? {WIDTH{1'b0}} :
(global_id[0] + 2'b01);
global_id[1] <= (last_global_id[0] & last_global_id[1]) ? {WIDTH{1'b0}} :
(last_global_id[0] ? (global_id[1] + 2'b01) : (global_id[1] - max_local_id[1]));
global_id[2] <= (last_global_id[0] & last_global_id[1] & last_global_id[2]) ? {WIDTH{1'b0}} :
(last_global_id[0] & last_global_id[1]) ? (global_id[2] + 2'b01) :
(global_id[2] - max_local_id[2]);
end else begin
if ( bump_local_id[0] ) global_id[0] <= last_local_id[0] ? (global_id[0] - max_local_id[0]) : (global_id[0] + 2'b01);
if ( bump_local_id[1] ) global_id[1] <= last_local_id[1] ? (global_id[1] - max_local_id[1]) : (global_id[1] + 2'b01);
if ( bump_local_id[2] ) global_id[2] <= last_local_id[2] ? (global_id[2] - max_local_id[2]) : (global_id[2] + 2'b01);
end
end
end
end
//////////////////////////////////
// Handle group ids.
wire last_group_id[2:0];
assign last_group_id[0] = (group_id[0] == (i_group_size[0] - 2'b01) );
assign last_group_id[1] = (group_id[1] == (i_group_size[1] - 2'b01) );
assign last_group_id[2] = (group_id[2] == (i_group_size[2] - 2'b01) );
wire bump_group_id[2:0];
assign bump_group_id[0] = ((i_group_size[0] - 2'b01) != 0);
assign bump_group_id[1] = ((i_group_size[1] - 2'b01) != 0) && last_group_id[0];
assign bump_group_id[2] = ((i_group_size[2] - 2'b01) != 0) && last_group_id[0] && last_group_id[1];
always @(posedge clock or negedge resetn) begin
if ( ~resetn ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
scalar_group_id <= {WIDTH{1'b0}};
end else if ( i_counter_reset ) begin
group_id[0] <= {WIDTH{1'b0}};
group_id[1] <= {WIDTH{1'b0}};
group_id[2] <= {WIDTH{1'b0}};
scalar_group_id <= {WIDTH{1'b0}};
end else // We presume that i_counter_reset and issue are mutually exclusive.
begin
if ( issue ) begin
if ( last_in_group ) begin
group_id[0] <= incr_lid (group_id[0], bump_group_id[0], last_group_id[0]);
group_id[1] <= incr_lid (group_id[1], bump_group_id[1], last_group_id[1]);
group_id[2] <= incr_lid (group_id[2], bump_group_id[2], last_group_id[2]);
scalar_group_id <= scalar_group_id + 1;
end
end
end
end
//assign scalar_group_id = group_id[0] + i_group_size[0] * ( group_id[1] + i_group_size[1] * group_id[2] );
wire [WIDTH-1:0] global_id_out[2:0];
wire [WIDTH-1:0] local_id_out[2:0];
wire [WIDTH-1:0] group_id_out[2:0];
wire [WIDTH-1:0] max_local_id_out[2:0];
assign global_id_out = global_id;
assign local_id_out = local_id;
assign group_id_out = group_id;
assign max_local_id_out = max_local_id;
endmodule
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#include <bits/stdc++.h> using namespace std; const int maxn = 200005; inline int read() { register int x = 0, w = 1, ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) w = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 48; return w * x; } int n, m, k, tot1, tot2, tot3, cnt; long long s[maxn]; struct node { int opt, id, x; long long v, w; } m1[maxn], m2[maxn], m3[maxn], ans[maxn]; inline bool cmp1(node a, node b) { return (a.x != b.x) ? (a.x < b.x) : (a.v < b.v); } inline bool cmp2(node a, node b) { return (a.x != b.x) ? (a.x < b.x) : (a.v > b.v); } inline bool cmp3(node a, node b) { return a.opt < b.opt; } inline bool cmp4(node a, node b) { return a.v * b.w > a.w * b.v; } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) s[i] = read(); for (int i = 1; i <= m; i++) { int a = read(), b = read(), c = read(); if (a == 1 && c > s[b]) m1[++tot1] = (node){1, i, b, c, 1}; else if (a == 2) m2[++tot2] = (node){2, i, b, c, 1}; else if (a == 3) m3[++tot3] = (node){3, i, b, c, 1}; } sort(m1 + 1, m1 + tot1 + 1, cmp1); int tmp = 0; for (int i = 1; i <= tot1; i++) if (m1[i].x != m1[i + 1].x) m1[++tmp] = m1[i]; tot1 = tmp; for (int i = 1; i <= tot1; i++) m1[i].v = m1[i].v - s[m1[i].x], m2[++tot2] = m1[i]; sort(m2 + 1, m2 + tot2 + 1, cmp2); long long sum = 0; for (int i = 1; i <= tot2; i++) { if (m2[i].x != m2[i - 1].x) sum = s[m2[i].x]; m2[i].w = sum, sum += m2[i].v; } for (int i = 1; i <= tot3; i++) m3[i].v--; for (int i = 1; i <= tot2; i++) m3[++tot3] = m2[i]; sort(m3 + 1, m3 + tot3 + 1, cmp4); tmp = min(tot3, k); for (int i = 1; i <= tmp; i++) ans[++cnt] = m3[i]; printf( %d n , cnt); sort(ans + 1, ans + cnt + 1, cmp3); for (int i = 1; i <= cnt; i++) printf( %d , ans[i].id); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_HD__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n, x, l[60], r[60], ans; int main() { scanf( %d %d , &n, &x); for (int i = 1; i <= n; ++i) { scanf( %d %d , &l[i], &r[i]); } for (int i = 1; i <= n; ++i) { ans += (l[i] - r[i - 1] - 1) % x; ans += r[i] - l[i] + 1; } printf( %d , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; class team { public: int x, y, z; }; int search(team *, int, int); int main() { int m, n, t; cin >> n >> m; int *arr1, *arr2; arr1 = new int[m]; arr2 = new int[m]; for (int i = 0; i < m; i++) cin >> arr1[i] >> arr2[i]; team *res = new team[n / 3]; for (int i = 0; i < n / 3; i++) { res[i].x = 0; res[i].y = 0; res[i].z = 0; } bool *tak = new bool[n + 1]; bool resf = false; for (int i = 0; i < n + 1; i++) tak[i] = false; tak[0] = true; for (int i = 0; i < m; i++) { if ((!tak[arr1[i]]) && (!tak[arr2[i]])) { bool f = true; for (int j = 0; j < n / 3; j++) { if (res[j].x == 0) { res[j].x = arr1[i]; res[j].y = arr2[i]; tak[arr1[i]] = true; tak[arr2[i]] = true; f = false; break; } } if (f) { resf = true; goto End; } } else if (tak[arr1[i]] && tak[arr2[i]]) { if (search(res, arr1[i], n / 3) == search(res, arr2[i], n / 3)) continue; else { resf = true; goto End; } } else if (tak[arr1[i]]) { t = search(res, arr1[i], n / 3); if (res[t].z == 0) { res[t].z = arr2[i]; tak[arr2[i]] = true; } else { resf = true; goto End; } } else if (tak[arr2[i]]) { t = search(res, arr2[i], n / 3); if (res[t].z == 0) { res[t].z = arr1[i]; tak[arr1[i]] = true; } else { resf = true; goto End; } } } for (int i = 0; i < n / 3; i++) { if (res[i].x == 0) { for (int j = 1; j < n + 1; j++) if (!tak[j]) { res[i].x = j; tak[j] = true; break; } } if (res[i].y == 0) { for (int j = 1; j < n + 1; j++) if (!tak[j]) { res[i].y = j; tak[j] = true; break; } } if (res[i].z == 0) { for (int j = 1; j < n + 1; j++) if (!tak[j]) { res[i].z = j; tak[j] = true; break; } } } End: if (resf) cout << -1; else { for (int i = 0; i < n / 3; i++) cout << res[i].x << << res[i].y << << res[i].z << endl; } return 0; } int search(team *input, int val, int size) { for (int i = 0; i < size; i++) { if (input[i].x == val) return i; if (input[i].y == val) return i; if (input[i].z == val) return i; } }
|
#include <bits/stdc++.h> using namespace std; long long pow2[61]; vector<long long> ans; int main() { std::ios_base::sync_with_stdio(false); pow2[0] = 1; pow2[1] = 2; for (int i = 2; i <= 60; i++) pow2[i] = pow2[i - 1] * 2; long long X, d; scanf( %lld %lld , &X, &d); while (X > 1) { long long k = 0; while (pow2[k] - 1 < X) k++; k--; long long j = 1; if (ans.size()) { j = ans.back() + d; } for (int i = 1; i <= k; i++) ans.push_back(j); X -= pow2[k] - 1; } if (X == 1) { if (ans.size()) ans.push_back(ans.back() + d); else ans.push_back(1); } if (ans.size() > 10000) printf( -1 n ); else { printf( %lu n , ans.size()); for (int i = 0; i < ans.size(); i++) if (ans[i] >= 1e18) return 0 * printf( -1 n ); for (int i = 0; i < ans.size(); i++) printf( %lld , ans[i]); printf( n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_1_V
`define SKY130_FD_SC_LP__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_1_V
|
#include <bits/stdc++.h> using namespace std; int block; unordered_map<int, int> x; vector<long long> a; struct query { int l, r, pos; bool operator<(const query &other) const { if (l / block == other.l / block) return r < other.r; return l / block < other.l / block; } }; int l = 0, r = -1, cnt = 0; void remove(int val) { if (x[val] == val) cnt--; x[val]--; if (x[val] == val) cnt++; if (x[val] == 0) x.erase(val); } void add(int val) { if (x[val] == val) cnt--; x[val]++; if (x[val] == val) cnt++; } void solve() { long long n, m; cin >> n >> m; block = sqrt(n) + 1; a.resize(n); for (long long i = 0; i < n; i++) cin >> a[i]; vector<query> q(m); for (int i = 0; i < m; i++) { cin >> q[i].l >> q[i].r; q[i].pos = i; q[i].l--, q[i].r--; } sort(q.begin(), q.end()); vector<int> ans(m); for (int i = 0; i < m; i++) { while (l < q[i].l) remove(a[l++]); while (l > q[i].l) add(a[--l]); while (r < q[i].r) add(a[++r]); while (r > q[i].r) remove(a[r--]); ans[q[i].pos] = cnt; } for (auto i : ans) cout << i << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [63:0] rf;
reg [63:0] rf2;
reg [63:0] biu;
reg okidoki;
always @* begin
rf[63:32] = biu[63:32] & {32{okidoki}};
rf[31:0] = {32{okidoki}};
rf2 = rf;
rf2[31:0] = ~{32{okidoki}};
end
reg [31:0] src1, src0, sr, mask;
wire [31:0] dualasr
= ((| src1[31:4])
? {{16{src0[31]}}, {16{src0[15]}}}
: ( ( sr & {2{mask[31:16]}})
| ( {{16{src0[31]}}, {16{src0[15]}}}
& {2{~mask[31:16]}})));
wire [31:0] sl_mask
= (32'hffffffff << src1[4:0]);
wire [31:0] sr_mask
= {sl_mask[0], sl_mask[1],
sl_mask[2], sl_mask[3], sl_mask[4],
sl_mask[5], sl_mask[6], sl_mask[7],
sl_mask[8], sl_mask[9],
sl_mask[10], sl_mask[11],
sl_mask[12], sl_mask[13], sl_mask[14],
sl_mask[15], sl_mask[16],
sl_mask[17], sl_mask[18], sl_mask[19],
sl_mask[20], sl_mask[21],
sl_mask[22], sl_mask[23], sl_mask[24],
sl_mask[25], sl_mask[26],
sl_mask[27], sl_mask[28], sl_mask[29],
sl_mask[30], sl_mask[31]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
`endif
if (cyc==1) begin
biu <= 64'h12451282_abadee00;
okidoki <= 1'b0;
src1 <= 32'h00000001;
src0 <= 32'h9a4f1235;
sr <= 32'h0f19f567;
mask <= 32'h7af07ab4;
end
if (cyc==2) begin
biu <= 64'h12453382_abad8801;
okidoki <= 1'b1;
if (rf != 64'h0) $stop;
if (rf2 != 64'h00000000ffffffff) $stop;
src1 <= 32'h0010000f;
src0 <= 32'h028aa336;
sr <= 32'h42ad0377;
mask <= 32'h1ab3b906;
if (dualasr != 32'h8f1f7060) $stop;
if (sl_mask != 32'hfffffffe) $stop;
if (sr_mask != 32'h7fffffff) $stop;
end
if (cyc==3) begin
biu <= 64'h12422382_77ad8802;
okidoki <= 1'b1;
if (rf != 64'h12453382ffffffff) $stop;
if (rf2 != 64'h1245338200000000) $stop;
src1 <= 32'h0000000f;
src0 <= 32'h5c158f71;
sr <= 32'h7076c40a;
mask <= 32'h33eb3d44;
if (dualasr != 32'h0000ffff) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
end
if (cyc==4) begin
if (rf != 64'h12422382ffffffff) $stop;
if (rf2 != 64'h1242238200000000) $stop;
if (dualasr != 32'h3062cc1e) $stop;
if (sl_mask != 32'hffff8000) $stop;
if (sr_mask != 32'h0001ffff) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 11:21:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_util_ds_buf_1_0 -prefix
// system_util_ds_buf_1_0_ system_util_ds_buf_0_0_stub.v
// Design : system_util_ds_buf_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_ds_buf,Vivado 2016.4" *)
module system_util_ds_buf_1_0(BUFG_I, BUFG_O)
/* synthesis syn_black_box black_box_pad_pin="BUFG_I[0:0],BUFG_O[0:0]" */;
input [0:0]BUFG_I;
output [0:0]BUFG_O;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e9 + 7; const int N = 1e5 + 10; int n, p[N], h[N]; vector<int> g[N]; vector<pair<int, int> > ans; void build(int x, int y) { int m1 = g[x].size(); if (x == y) { for (auto i = 0; i < m1 - 1; i++) ans.push_back(pair<int, int>(g[x][i], g[x][i + 1])); return; } for (auto i = 0; i < g[y].size(); i++) ans.push_back(pair<int, int>(g[x][i % m1], g[y][i])); } void solve() { int m = 0; for (auto i = 1; i <= n; i++) if (!h[i]) { m++; int cur = i; while (!h[cur]) { h[cur] = 1; g[m].push_back(cur); cur = p[cur]; } } int root = 1; for (auto i = 1; i <= m; i++) if (g[i].size() < g[root].size()) root = i; if (g[root].size() > 2) { printf( NO ); return; } for (auto i = 1; i <= m; i++) if (g[i].size() % g[root].size()) { printf( NO ); return; } for (auto i = 1; i <= m; i++) build(root, i); if (ans.size() != n - 1) { printf( NO n ); return; } printf( YES n ); for (auto i : ans) printf( %d %d n , i.first, i.second); } int main() { scanf( %d , &n); for (auto i = 1; i <= n; i++) scanf( %d , p + i); solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; string s1, s2, s3; cin >> t; map<string, int> mp; mp[ polycarp ] = 1; while (t--) { cin >> s1 >> s2 >> s3; transform(s1.begin(), s1.end(), s1.begin(), ::tolower); transform(s3.begin(), s3.end(), s3.begin(), ::tolower); mp[s1] = mp[s3] + 1; } map<string, int>::iterator it; int ans = 0; for (it = mp.begin(); it != mp.end(); ++it) if (it->second > ans) ans = it->second; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; ifstream fin( A.in ); ofstream fout( A.out ); int n, m, a, b, v[100001], viz[100001]; vector<int> G[100001]; long long sum; struct sor { int x, i; } s[100001]; bool cmp(sor a, sor b) { return a.x > b.x; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> v[i]; s[i].x = v[i]; s[i].i = i; } for (int i = 1; i <= m; ++i) { cin >> a >> b; G[a].push_back(b); G[b].push_back(a); } sort(s + 1, s + n + 1, cmp); for (int i = 1; i <= n; ++i) { viz[s[i].i] = 1; for (vector<int>::iterator it = G[s[i].i].begin(); it != G[s[i].i].end(); ++it) { if (!viz[*it]) sum += v[*it]; } } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; int arr[n]; for (int i = (int)(0); i <= (int)(n - 1); i++) { cin >> arr[i]; } int hash1[100005] = {0}; for (int i = (int)(0); i <= (int)(n / 2 - 1); i++) { if (arr[i] - i > 0) hash1[arr[i] - i]++; } for (int i = (int)(n / 2); i <= (int)(n - 1); i++) { if (arr[i] - (n - i - 1) > 0) hash1[arr[i] - (n - i - 1)]++; } int cnt = 0, val = 0; for (int i = (int)(1); i <= (int)(100000); i++) { if (cnt < hash1[i]) { cnt = hash1[i]; val = i; } } cout << n - cnt << n ; }
|
#include <bits/stdc++.h> using namespace std; int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, m; cin >> n >> m; string s; char x, y; cin >> s; char ch[26]; for (long long int i = 0; i < 26; i++) { ch[i] = i + a ; } for (long long int i = 0; i < m; i++) { cin >> x >> y; for (long long int j = 0; j < 26; j++) { if (x == ch[j]) { ch[j] = y; } else if (y == ch[j]) { ch[j] = x; } } } for (long long int i = 0; i < s.size(); i++) { cout << ch[s[i] - a ]; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_SYMBOL_V
`define SKY130_FD_SC_LP__A2111OI_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_SYMBOL_V
|
#include <bits/stdc++.h> inline int readChar(); template <class T = int> inline T readInt(); template <class T> inline void writeInt(T x, char end = 0); inline void writeChar(int x); inline void writeWord(const char* s); static const int buf_size = 4096; inline int getChar() { static char buf[buf_size]; static int len = 0, pos = 0; if (pos == len) pos = 0, len = fread(buf, 1, buf_size, stdin); if (pos == len) return -1; return buf[pos++]; } inline int readChar() { int c = getChar(); while (c <= 32) c = getChar(); return c; } template <class T> inline T readInt() { int s = 1, c = readChar(); T x = 0; if (c == - ) s = -1, c = getChar(); while ( 0 <= c && c <= 9 ) x = x * 10 + c - 0 , c = getChar(); return s == 1 ? x : -x; } static int write_pos = 0; static char write_buf[buf_size]; inline void writeChar(int x) { if (write_pos == buf_size) fwrite(write_buf, 1, buf_size, stdout), write_pos = 0; write_buf[write_pos++] = x; } template <class T> inline void writeInt(T x, char end) { if (x < 0) writeChar( - ), x = -x; char s[24]; int n = 0; while (x || !n) s[n++] = 0 + x % 10, x /= 10; while (n--) writeChar(s[n]); if (end) writeChar(end); } inline void writeWord(const char* s) { while (*s) writeChar(*s++); } struct Flusher { ~Flusher() { if (write_pos) fwrite(write_buf, 1, write_pos, stdout), write_pos = 0; } } flusher; using namespace std; struct static_graph { int colors[500000]; int firstv[500000]; set<int> pool; static const int N = 500000; static const int M = 900000; struct edge { int v; edge* next; } edges[M]; int nedges; struct node { vector<int>* ice; int prev_colors; bool depth_use; edge* firstedge; inline void init() { firstedge = NULL; }; inline edge* add_edge(edge* e) { e->next = firstedge; firstedge = e; return firstedge; }; } nodes[N]; int nnodes; static_graph() { nnodes = 0, nedges = 0; }; inline node& new_node() { node& r = nodes[nnodes++]; return r; } inline edge* new_edge() { return &(edges[nedges++]); }; inline edge* add_edge(int a, int b) { edge* e = new_edge(); e->v = b; return nodes[a].add_edge(e); }; inline void add_bi_edge(int a, int b) { add_edge(a, b); add_edge(b, a); }; void depth_go(int index, int prev) { node& cur = nodes[index]; if (cur.depth_use++) return; for (int x : (*cur.ice)) if (colors[x]) pool.erase(colors[x]); for (int x : (*cur.ice)) if (!colors[x]) { colors[x] = (*pool.upper_bound(0)); firstv[x] = index; pool.erase(colors[x]); } for (int x : (*cur.ice)) pool.insert(colors[x]); for (edge* e = cur.firstedge; e; e = e->next) { depth_go(e->v, index); }; }; void depth_run(int first) { chrono::time_point<chrono::high_resolution_clock> start, end; start = std::chrono::high_resolution_clock::now(); for (int i = 0; i < nnodes; i++) { node& cur = nodes[i]; cur.depth_use = false; }; depth_go(first, -1); }; vector<node*> depth_to_wide(int first) {} void read_graph(istream* f){}; }; static_graph g; int main() { istream& f = cin; ios_base::sync_with_stdio(false); cin.tie(NULL); chrono::time_point<chrono::high_resolution_clock> start, end; start = std::chrono::high_resolution_clock::now(); int n, m, c, x = 0; n = readInt<int>(); m = readInt<int>(); for (int i = 0; i < n; i++) { c = readInt<int>(); static_graph::node& cur = g.new_node(); cur.ice = new vector<int>(); cur.ice->resize(c); cur.prev_colors = 0; for (int t = 0; t < c; t++) { x = readInt<int>(); (*cur.ice)[t] = x - 1; }; sort((*cur.ice).begin(), (*cur.ice).end()); ; }; for (int i = 0; i < n - 1; i++) { int a, b; a = readInt<int>(), b = readInt<int>(); g.add_bi_edge(a - 1, b - 1); }; for (int i = 0; i < m; i++) g.colors[i] = 0; for (int i = 0; i < m; i++) g.pool.insert(i + 1); g.depth_run(0); int mx = 1; for (int i = 0; i < m; i++) { mx = max(mx, g.colors[i]); if (!g.colors[i]) g.colors[i] = 1; } cout << mx << endl; for (int i = 0; i < m; i++) cout << g.colors[i] << ; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using P = pair<ll, ll>; using PP = pair<ll, P>; const ll n_ = 2222 + 100, inf = 1e18 + 1, mod = 1e9 + 7, sqrtN = 333; ll dy[4] = {-1, 0, 1, 0}, dx[4] = {0, 1, 0, -1}; ll n, m, k, tc = 1, a, b, c, sum, x, y, z, w, base, ans; ll gcd(ll x, ll y) { if (!y) return x; return gcd(y, x % y); } ll dp[n_][n_][2], A[n_][n_]; void solve() { ll q; cin >> n >> m >> q; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) A[i][j] = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { dp[i][j][0] = A[i][j] * (dp[i][j - 1][1] + A[i][j - 1]); dp[i][j][1] = A[i][j] * (dp[i - 1][j][0] + A[i - 1][j]); ans += dp[i][j][0] + dp[i][j][1] + A[i][j]; } ll i, j; while (q--) { cin >> i >> j; ans -= dp[i][j][0] + dp[i][j][1] + A[i][j]; A[i][j] ^= 1; dp[i][j][0] = A[i][j] * (dp[i][j - 1][1] + A[i][j - 1]); dp[i][j][1] = A[i][j] * (dp[i - 1][j][0] + A[i - 1][j]); ans += dp[i][j][0] + dp[i][j][1] + A[i][j]; b = i + 1, a = j, c = 0; while (1) { if (b > n || a > m) break; ans -= dp[b][a][0] + dp[b][a][1] + A[b][a]; dp[b][a][0] = A[b][a] * (dp[b][a - 1][1] + A[b][a - 1]); dp[b][a][1] = A[b][a] * (dp[b - 1][a][0] + A[b - 1][a]); ans += dp[b][a][0] + dp[b][a][1] + A[b][a]; if (c) b++; else a++; c = (c + 1) % 2; } b = i, a = j + 1, c = 1; while (1) { if (b > n || a > m) break; ans -= dp[b][a][0] + dp[b][a][1] + A[b][a]; dp[b][a][0] = A[b][a] * (dp[b][a - 1][1] + A[b][a - 1]); dp[b][a][1] = A[b][a] * (dp[b - 1][a][0] + A[b - 1][a]); ans += dp[b][a][0] + dp[b][a][1] + A[b][a]; if (c) b++; else a++; c = (c + 1) % 2; } cout << ans << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); while (tc--) solve(); }
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Flow generator - burst generator module
*/
module fg_burst_gen #(
parameter FLOW_ADDR_WIDTH = 5,
parameter DEST_WIDTH = 8,
parameter RATE_SCALE = 8
)
(
input wire clk,
input wire rst,
/*
* Flow descriptor input
*/
input wire input_fd_valid,
output wire input_fd_ready,
input wire [DEST_WIDTH-1:0] input_fd_dest,
input wire [15:0] input_fd_rate_num,
input wire [15:0] input_fd_rate_denom,
input wire [31:0] input_fd_len,
input wire [31:0] input_fd_burst_len,
/*
* Burst descriptor output
*/
output wire output_bd_valid,
input wire output_bd_ready,
output wire [DEST_WIDTH-1:0] output_bd_dest,
output wire [31:0] output_bd_burst_len,
/*
* Status
*/
output wire busy,
output wire [FLOW_ADDR_WIDTH-1:0] active_flows
/*
* Configuration
*/
);
reg [FLOW_ADDR_WIDTH-1:0] cur_flow_reg = 0, cur_flow_next;
// flow state
reg update_flow_state;
reg flow_active[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_active, flow_active_next;
reg [DEST_WIDTH-1:0] flow_dest[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_dest, flow_dest_next;
reg [15:0] flow_rate_num[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_rate_num, flow_rate_num_next;
reg [15:0] flow_rate_denom[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_rate_denom, flow_rate_denom_next;
reg [31:0] flow_len[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_len, flow_len_next;
reg [31:0] flow_burst_len[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_burst_len, flow_burst_len_next;
reg [31:0] flow_delay[(2**FLOW_ADDR_WIDTH)-1:0], cur_flow_delay, flow_delay_next;
integer i;
initial begin
for (i = 0; i < 2**FLOW_ADDR_WIDTH; i = i + 1) begin
flow_active[i] <= 0;
flow_dest[i] <= 0;
flow_rate_num[i] <= 0;
flow_rate_denom[i] <= 0;
flow_len[i] <= 0;
flow_burst_len[i] <= 0;
flow_delay[i] <= 0;
end
end
// debug
wire [DEST_WIDTH-1:0] flow_dest_0 = flow_dest[0];
wire [15:0] flow_rate_num_0 = flow_rate_num[0];
wire [15:0] flow_rate_denom_0 = flow_rate_denom[0];
wire [31:0] flow_len_0 = flow_len[0];
wire [31:0] flow_burst_len_0 = flow_burst_len[0];
wire [31:0] flow_delay_0 = flow_delay[0];
reg input_fd_ready_reg = 0, input_fd_ready_next;
reg busy_reg = 0;
reg [FLOW_ADDR_WIDTH-1:0] active_flows_reg = 0, active_flows_next;
// internal datapath
reg [DEST_WIDTH-1:0] output_bd_dest_int;
reg [31:0] output_bd_burst_len_int;
reg output_bd_valid_int;
reg output_bd_ready_int = 0;
wire output_bd_ready_int_early;
assign input_fd_ready = input_fd_ready_reg;
assign busy = busy_reg;
assign active_flows = active_flows_reg;
always @* begin
cur_flow_next = cur_flow_reg+1;
input_fd_ready_next = 0;
output_bd_dest_int = 0;
output_bd_burst_len_int = 0;
output_bd_valid_int = 0;
update_flow_state = 0;
flow_active_next = cur_flow_active;
flow_dest_next = cur_flow_dest;
flow_rate_num_next = cur_flow_rate_num;
flow_rate_denom_next = cur_flow_rate_denom;
flow_len_next = cur_flow_len;
flow_burst_len_next = cur_flow_burst_len;
flow_delay_next = cur_flow_delay;
active_flows_next = active_flows_reg;
if (cur_flow_active) begin
// flow has data to send
if (cur_flow_delay >= (cur_flow_rate_num * RATE_SCALE * (2**FLOW_ADDR_WIDTH))) begin
// waiting - update counter
flow_delay_next = cur_flow_delay - (cur_flow_rate_num * RATE_SCALE * (2**FLOW_ADDR_WIDTH));
update_flow_state = 1;
end else begin
// send burst
output_bd_dest_int = cur_flow_dest;
output_bd_valid_int = 1;
if (cur_flow_len > cur_flow_burst_len) begin
// not last burst
flow_len_next = cur_flow_len - cur_flow_burst_len;
flow_delay_next = cur_flow_delay + (cur_flow_burst_len * cur_flow_rate_denom) - (cur_flow_rate_num * RATE_SCALE * (2**FLOW_ADDR_WIDTH));
output_bd_burst_len_int = cur_flow_burst_len;
update_flow_state = 1;
end else begin
// last burst
flow_active_next = 0;
flow_len_next = 0;
flow_delay_next = 0;
output_bd_burst_len_int = cur_flow_len;
update_flow_state = 1;
active_flows_next = active_flows - 1;
end
end
end else if (input_fd_valid & ~input_fd_ready) begin
// read new flow descriptor into empty slot
input_fd_ready_next = 1;
update_flow_state = 1;
flow_active_next = 1;
flow_dest_next = input_fd_dest;
flow_rate_num_next = input_fd_rate_num;
flow_rate_denom_next = input_fd_rate_denom;
flow_len_next = input_fd_len;
flow_burst_len_next = input_fd_burst_len;
flow_delay_next = 0;
active_flows_next = active_flows + 1;
end
end
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < 2**FLOW_ADDR_WIDTH; i = i + 1) begin
flow_active[i] <= 0;
end
end else begin
cur_flow_active <= flow_active[cur_flow_next];
cur_flow_dest <= flow_dest[cur_flow_next];
cur_flow_rate_num <= flow_rate_num[cur_flow_next];
cur_flow_rate_denom <= flow_rate_denom[cur_flow_next];
cur_flow_len <= flow_len[cur_flow_next];
cur_flow_burst_len <= flow_burst_len[cur_flow_next];
cur_flow_delay <= flow_delay[cur_flow_next];
if (update_flow_state) begin
flow_active[cur_flow_reg] <= flow_active_next;
flow_dest[cur_flow_reg] <= flow_dest_next;
flow_rate_num[cur_flow_reg] <= flow_rate_num_next;
flow_rate_denom[cur_flow_reg] <= flow_rate_denom_next;
flow_len[cur_flow_reg] <= flow_len_next;
flow_burst_len[cur_flow_reg] <= flow_burst_len_next;
flow_delay[cur_flow_reg] <= flow_delay_next;
end
end
end
always @(posedge clk or posedge rst) begin
if (rst) begin
cur_flow_reg <= 0;
input_fd_ready_reg <= 0;
busy_reg <= 0;
active_flows_reg <= 0;
end else begin
cur_flow_reg <= cur_flow_next;
input_fd_ready_reg <= input_fd_ready_next;
busy_reg <= active_flows_next != 0;
active_flows_reg <= active_flows_next;
end
end
// output datapath logic
reg [DEST_WIDTH-1:0] output_bd_dest_reg = 0;
reg [31:0] output_bd_burst_len_reg = 0;
reg output_bd_valid_reg = 0;
reg [DEST_WIDTH-1:0] temp_bd_dest_reg = 0;
reg [31:0] temp_bd_burst_len_reg = 0;
reg temp_bd_valid_reg = 0;
assign output_bd_dest = output_bd_dest_reg;
assign output_bd_burst_len = output_bd_burst_len_reg;
assign output_bd_valid = output_bd_valid_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_bd_ready_int_early = output_bd_ready | (~temp_bd_valid_reg & ~output_bd_valid_reg) | (~temp_bd_valid_reg & ~output_bd_valid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_bd_dest_reg <= 0;
output_bd_burst_len_reg <= 0;
output_bd_valid_reg <= 0;
output_bd_ready_int <= 0;
temp_bd_dest_reg <= 0;
temp_bd_burst_len_reg <= 0;
temp_bd_valid_reg <= 0;
end else begin
// transfer sink ready state to source
output_bd_ready_int <= output_bd_ready_int_early;
if (output_bd_ready_int) begin
// input is ready
if (output_bd_ready | ~output_bd_valid_reg) begin
// output is ready or currently not valid, transfer data to output
output_bd_dest_reg <= output_bd_dest_int;
output_bd_burst_len_reg <= output_bd_burst_len_int;
output_bd_valid_reg <= output_bd_valid_int;
end else begin
// output is not ready, store input in temp
temp_bd_dest_reg <= output_bd_dest_int;
temp_bd_burst_len_reg <= output_bd_burst_len_int;
temp_bd_valid_reg <= output_bd_valid_int;
end
end else if (output_bd_ready) begin
// input is not ready, but output is ready
output_bd_dest_reg <= temp_bd_dest_reg;
output_bd_burst_len_reg <= temp_bd_burst_len_reg;
output_bd_valid_reg <= temp_bd_valid_reg;
temp_bd_dest_reg <= 0;
temp_bd_valid_reg <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int input() { int res = 0; char c = ; while (c < 0 && c != - ) c = getchar(); while (c >= 0 ) res = res * 10 + (c - 0 ), c = getchar(); return res; } const int N = 1e5 + 1; string to_str(int x) { string res; while (x) res += 0 + x % 10, x /= 10; reverse(res.begin(), res.end()); return res; } string rc(string s) { int i = 0, x = 0, y = 0; for (; i < s.size(); ++i) if (s[i] >= 0 && s[i] <= 9 ) break; else y = y * 26 + s[i] - A + 1; for (; i < s.size(); ++i) x = x * 10 + (s[i] - 0 ); return { R + to_str(x) + C + to_str(y)}; } string aa(string s) { int i = 1, x = 0, y = 0; for (; s[i] != C ; ++i) x = x * 10 + (s[i] - 0 ); for (++i; i < s.size(); ++i) y = y * 10 + (s[i] - 0 ); string r; while (y) r += A + (y - 1) % 26, y = (y - 1) / 26; reverse(r.begin(), r.end()); return r + to_str(x); } int main() { for (int i = input(); i; --i) { string s; cin >> s; bool f = false, RC = false; for (auto i : s) { if (i >= A && i <= Z && f) RC = true; else if (i >= 0 && i <= 9 ) f = true; } if (RC) cout << aa(s) << endl; else cout << rc(s) << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int inf = 80009; unsigned long long n; vector<int> adj[inf]; unsigned long long low[inf]; unsigned long long sl[inf]; unsigned long long sz[inf]; unsigned long long als; unsigned long long ans = 0; void dfs(int x, int p) { unsigned long long s = 0; int k; unsigned long long tr = 0, fr = 0; for (int i = 0; i < adj[x].size(); ++i) { k = adj[x][i]; if (k == p) continue; dfs(k, x); sl[x] += sl[k]; fr += sz[k] * tr; tr += sz[k] * low[x]; low[x] += sz[k] * sz[x]; sz[x] += sz[k]; } fr += (n - sz[x] - 1) * tr; tr += (n - sz[x] - 1) * low[x]; ans += (fr + tr) * 6 + ((n - sz[x] - 1) * sz[x] + low[x]) * 2; low[x] += sz[x]; low[x] += low[x] + 1; sl[x] += low[x]; sz[x]++; } void solve(int x, int p) { ans += (als - sl[x]) * low[x]; als -= low[x]; unsigned long long g = low[x] / 2 + (n - sz[x]) * sz[x]; int k; for (int i = 0; i < adj[x].size(); ++i) { k = adj[x][i]; if (k == p) continue; ans += sl[k] * ((g - sz[k] * (n - sz[k])) * 2 + 1); solve(k, x); } } int main() { int a, b; scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } dfs(1, 1); als = sl[1]; solve(1, 1); unsigned long long all = (n * (n - 1)) / 2; all = all * all; printf( %I64d n , all - ans); }
|
#include <bits/stdc++.h> using namespace std; long long n, k; int main() { cin >> n >> k; int ans = 1; while ((k & 1LL) == 0) { ++ans; k = k >> 1; } printf( %d n , ans); return 0; }
|
//
`timescale 1ns/1ps
module stage3(
input reset,
input core_sp_clk,
input [31:0] previous_bblock,
input [31:0] previous_nhop,
input [31:0] fifo_pr_bblock, // previous block read from the fifo
input [31:0] fifo_pr_nhop,
output [12:2] jump_index_addr,
output [31:0] jump_bblock
);
reg [12:2] jump_index_addr_reg;
assign jump_index_addr = jump_index_addr_reg;
reg [31:0] jump_bblock_reg;
reg [31:0] jump_bblock_reg_tmp;
assign jump_bblock = jump_bblock_reg;
always @(posedge core_sp_clk)
begin
if(reset) begin
jump_index_addr_reg <= 0;
jump_bblock_reg <= 32'b00000000000000000000000000000001;
end else begin
if ((fifo_pr_bblock == previous_bblock) || ((fifo_pr_bblock+1'b1) == previous_bblock) || ((fifo_pr_bblock-1'b1) == previous_bblock)) begin
jump_index_addr_reg <= 0;
jump_bblock_reg_tmp <= 32'b00000000000000000000000000000001;
end else begin
jump_index_addr_reg <= fifo_pr_nhop[12:2];
jump_bblock_reg_tmp <= previous_bblock;
end
jump_bblock_reg <= jump_bblock_reg_tmp;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_falling & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b001};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct ned { int x, y; bool operator<(const ned &a) const { return x == a.x ? (y < a.y) : x < a.x; } }; ned ned[4000010]; int n, m, cnt; int a[2010], b[2010], c[2010], d[2010]; int sma[4000010]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %d%d , &a[i], &b[i]); for (int i = 1; i <= m; ++i) scanf( %d%d , &c[i], &d[i]); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (a[i] <= c[j] && b[i] <= d[j]) { ned[++cnt] = {c[j] - a[i] + 1, d[j] - b[i] + 1}; } } } sort(ned + 1, ned + cnt + 1); for (int i = cnt; i >= 1; --i) sma[i] = max(sma[i + 1], ned[i].y); int ans = 0x3f3f3f3f; for (int i = 0; i <= cnt; ++i) ans = min(ans, ned[i].x + sma[i + 1]); ans = ans * (cnt > 0); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 7, maxn = 3e5 + 500; vector<pair<int, int> > v[maxn]; bool visited[maxn], deg[maxn]; int d[maxn]; set<int> s; void dfs(int u, int par) { visited[u] = 1; int idx; for (int i = 0; i < v[u].size(); i++) { int w = v[u][i].first; if (!visited[w]) dfs(w, u); if (w == par) idx = v[u][i].second; } if (deg[u] != d[u]) { deg[par] ^= 1; s.insert(idx); } } int main() { ios_base::sync_with_stdio(false); int n, m, cntt = 0, cnt = 0; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> d[i]; if (d[i] == 1) cnt++; if (d[i] == -1) cntt++; } for (int i = 1; i <= m; i++) { int u, w; cin >> u >> w; v[u].push_back(make_pair(w, i)); v[w].push_back(make_pair(u, i)); } if (cnt % 2 == 1 and cntt == 0) return cout << -1 << endl, 0; if (cnt % 2 == 1) { for (int i = 1; i <= n; i++) { if (d[i] == -1) { d[i] = 1; break; } } } for (int i = 1; i <= n; i++) if (d[i] == -1) d[i] = 0; dfs(1, -1); cout << s.size() << endl; for (auto it : s) cout << it << ; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module controls VGA output for Altera's DE1 and DE2 Boards. *
* *
******************************************************************************/
module amm_master_qsys_with_pcie_video_vga_controller_0 (
// Inputs
clk,
reset,
data,
startofpacket,
endofpacket,
empty,
valid,
// Bidirectionals
// Outputs
ready,
VGA_CLK,
VGA_BLANK,
VGA_SYNC,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 7;
parameter DW = 29;
parameter R_UI = 29;
parameter R_LI = 22;
parameter G_UI = 19;
parameter G_LI = 12;
parameter B_UI = 9;
parameter B_LI = 2;
/* Number of pixels */
parameter H_ACTIVE = 640;
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
parameter H_TOTAL = 800;
/* Number of lines */
parameter V_ACTIVE = 480;
parameter V_FRONT_PORCH = 10;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 33;
parameter V_TOTAL = 525;
parameter LW = 10;
parameter LINE_COUNTER_INCREMENT = 10'h001;
parameter PW = 10;
parameter PIXEL_COUNTER_INCREMENT = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] data;
input startofpacket;
input endofpacket;
input [ 1: 0] empty;
input valid;
// Bidirectionals
// Outputs
output ready;
output VGA_CLK;
output reg VGA_BLANK;
output reg VGA_SYNC;
output reg VGA_HS;
output reg VGA_VS;
output reg [CW: 0] VGA_R;
output reg [CW: 0] VGA_G;
output reg [CW: 0] VGA_B;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
localparam STATE_0_SYNC_FRAME = 1'b0,
STATE_1_DISPLAY = 1'b1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_enable;
wire end_of_active_frame;
wire vga_blank_sync;
wire vga_c_sync;
wire vga_h_sync;
wire vga_v_sync;
wire vga_data_enable;
wire [CW: 0] vga_red;
wire [CW: 0] vga_green;
wire [CW: 0] vga_blue;
wire [CW: 0] vga_color_data;
// Internal Registers
reg [ 3: 0] color_select; // Use for the TRDB_LCM
// State Machine Registers
reg ns_mode;
reg s_mode;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk) // sync reset
begin
if (reset == 1'b1)
s_mode <= STATE_0_SYNC_FRAME;
else
s_mode <= ns_mode;
end
always @(*)
begin
// Defaults
ns_mode = STATE_0_SYNC_FRAME;
case (s_mode)
STATE_0_SYNC_FRAME:
begin
if (valid & startofpacket)
ns_mode = STATE_1_DISPLAY;
else
ns_mode = STATE_0_SYNC_FRAME;
end
STATE_1_DISPLAY:
begin
if (end_of_active_frame)
ns_mode = STATE_0_SYNC_FRAME;
else
ns_mode = STATE_1_DISPLAY;
end
default:
begin
ns_mode = STATE_0_SYNC_FRAME;
end
endcase
end
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
VGA_BLANK <= vga_blank_sync;
VGA_SYNC <= 1'b0;
VGA_HS <= vga_h_sync;
VGA_VS <= vga_v_sync;
VGA_R <= vga_red;
VGA_G <= vga_green;
VGA_B <= vga_blue;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
color_select <= 4'h1;
else if (s_mode == STATE_0_SYNC_FRAME)
color_select <= 4'h1;
else if (~read_enable)
color_select <= {color_select[2:0], color_select[3]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign ready =
(s_mode == STATE_0_SYNC_FRAME) ?
valid & ~startofpacket :
read_enable;
assign VGA_CLK = ~clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_avalon_video_vga_timing VGA_Timing (
// Inputs
.clk (clk),
.reset (reset),
.red_to_vga_display (data[R_UI:R_LI]),
.green_to_vga_display (data[G_UI:G_LI]),
.blue_to_vga_display (data[B_UI:B_LI]),
.color_select (color_select),
// .data_valid (1'b1),
// Bidirectionals
// Outputs
.read_enable (read_enable),
.end_of_active_frame (end_of_active_frame),
.end_of_frame (), // (end_of_frame),
// dac pins
.vga_blank (vga_blank_sync),
.vga_c_sync (vga_c_sync),
.vga_h_sync (vga_h_sync),
.vga_v_sync (vga_v_sync),
.vga_data_enable (vga_data_enable),
.vga_red (vga_red),
.vga_green (vga_green),
.vga_blue (vga_blue),
.vga_color_data (vga_color_data)
);
defparam
VGA_Timing.CW = CW,
VGA_Timing.H_ACTIVE = H_ACTIVE,
VGA_Timing.H_FRONT_PORCH = H_FRONT_PORCH,
VGA_Timing.H_SYNC = H_SYNC,
VGA_Timing.H_BACK_PORCH = H_BACK_PORCH,
VGA_Timing.H_TOTAL = H_TOTAL,
VGA_Timing.V_ACTIVE = V_ACTIVE,
VGA_Timing.V_FRONT_PORCH = V_FRONT_PORCH,
VGA_Timing.V_SYNC = V_SYNC,
VGA_Timing.V_BACK_PORCH = V_BACK_PORCH,
VGA_Timing.V_TOTAL = V_TOTAL,
VGA_Timing.LW = LW,
VGA_Timing.LINE_COUNTER_INCREMENT = LINE_COUNTER_INCREMENT,
VGA_Timing.PW = PW,
VGA_Timing.PIXEL_COUNTER_INCREMENT = PIXEL_COUNTER_INCREMENT;
endmodule
|
`timescale 1ns / 1ps
`include "cache_defines.vh"
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:36 03/01/2015
// Design Name: cache
// Module Name: D:/Modelsim Projects/Xilinx/cache_implementation/top_tb.v
// Project Name: cache_implementation
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cacheblock1_tb;
parameter TAG_WIDTH = 8; // width of the tag
parameter DATA_WIDTH = 16; // width of the data
parameter ENTRIES_WIDTH = 64; // # of entries
parameter OPCODE_WIDTH = 2; // width of opcode
parameter LINE_WIDTH = TAG_WIDTH+DATA_WIDTH+OPCODE_WIDTH; // length of the input vector
// Inputs
reg [LINE_WIDTH-1:0]vector_in;
reg clk;
reg enable;
reg [TAG_WIDTH-1:0]tag_count;
reg [DATA_WIDTH-1:0]data_test;
// Outputs
wire [DATA_WIDTH-1:0]data_out;
wire [DATA_WIDTH-1:0]data_out_miss;
wire [TAG_WIDTH-1:0]tag_out_miss;
wire hit_miss_out;
// Instantiate the Unit Under Test (UUT)
cache #(TAG_WIDTH,DATA_WIDTH,ENTRIES_WIDTH) cacheblock1 (
.data_out(data_out),
.data_out_miss(data_out_miss),
.tag_out_miss(tag_out_miss),
.hit_miss_out(hit_miss_out),
.vector_in(vector_in),
.clk(clk),
.enable(enable)
);
initial begin
// Initialize Inputs
// data_in = 0;
clk = 0;
enable = 0;
// Wait 100 ns for global reset to finish
// Fill up cache
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
// This loop fills up the cache
repeat(ENTRIES_WIDTH)begin: bench1
#2 vector_in = {`WRITE,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 8'b1;
data_test = data_test + 16'b1;
end // end repeat loop
// This loop reads all the data that has been written in the cache previously
#2 tag_count = {TAG_WIDTH{1'b0}};
#2 data_test = {DATA_WIDTH{1'b1}};
repeat(ENTRIES_WIDTH)begin: bench2
#2 vector_in = {`READ,tag_count,data_test}; // write to a new tag entry every time
// #2 vector_in = {`READ,8'b111,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1010,data_test}; // read a new tag entry every time
// #2 vector_in = {`READ,8'b1111,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
#2 vector_in = 26'b10_11111111_0001000100010001; // write to a different tag entry
#2 vector_in = 26'b01_11111111_0001000100010001; // read the above tag entry
#2 vector_in = 26'b01_00001111_0001000100010001; // read the above tag entry
repeat(4)begin: bench3
#2 vector_in = {`READ,8'b00001010,data_test}; // read same tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
end // end repeat loop
#2 vector_in = 26'b00_00110001_0000000000000001; // flashes entire cache
// reads entire cache to confirm that has been flashed
tag_count = {TAG_WIDTH{1'b0}};
data_test = {DATA_WIDTH{1'b1}};
repeat(8)begin: bench4
#2 vector_in = {`READ,tag_count,data_test}; // read a new tag entry every time
// #2 vector_in = {2'b01,tag_count,data_test}; // read such tag entry
tag_count = tag_count + 1'b1;
data_test = data_test + 1'b1;
end // end repeat loop
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 100000 + 10; long long n, K, a[N], b[N]; struct Node { long long v, id; } p[N]; bool cmp(Node x, Node y) { return x.v > y.v; } long long get(long long x, long long v) { return -3ll * (x * x + x) + v + 1; } long long func(long long v, long long y) { long long l = 0, r = v, mid, ret = 0; while (l <= r) { mid = (l + r) >> 1ll; if (get(mid, v) >= y) ret = mid, l = mid + 1; else r = mid - 1; } return ret; } long long calc(long long y) { long long sum = 0; for (long long i = 1; i <= n; ++i) sum += func(a[i], y); return sum; } long long ans, sum; void solve() { long long l = -4e18, r = 1e18, mid; while (l <= r) { mid = (l + r) >> 1ll; if (calc(mid) <= K) ans = mid, r = mid - 1; else l = mid + 1; } } signed main() { scanf( %lld%lld , &n, &K); for (long long i = 1; i <= n; ++i) scanf( %lld , &a[i]); solve(); sum = 0; for (long long i = 1; i <= n; ++i) { b[i] = func(a[i], ans); sum += b[i]; p[i].v = get(b[i], a[i]); p[i].id = i; } sort(p + 1, p + n + 1, cmp); for (long long i = 1; i <= n; ++i) if (sum < K && a[p[i].id] > b[p[i].id]) sum++, b[p[i].id]++; for (long long i = 1; i <= n; ++i) printf( %lld , b[i]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__BUFBUF_FUNCTIONAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__bufbuf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_rptr_macros.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module fpu_bufrpt_grp64 (
in,
out
);
input [63:0] in;
output [63:0] out;
assign out[63:0] = in[63:0];
endmodule
module fpu_bufrpt_grp32 (
in,
out
);
input [31:0] in;
output [31:0] out;
assign out[31:0] = in[31:0];
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFBUF_PP_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_PP_BLACKBOX_V
|
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
University of Illinois/NCSA
Open Source License
Copyright(C) 2004, The Board of Trustees of the
University of Illinois. All rights reserved
IVM 1.0
Developed by:
Advanced Computing Systems Group
Center for Reliable and High-Performance Computing
University of Illinois at Urbana-Champaign
http://www.crhc.uiuc.edu/ACS
-- with support from --
Center for Circuits and Systems Solutions (C2S2)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the Software), to
deal with the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimers.
Redistributions in binary, gate-level, layout-level, or physical form must
reproduce the above copyright notice, this list of conditions and the
following disclaimers in the documentation and/or other materials provided
with the distribution.
Neither the names of Advanced Computing Systems Group, Center for Reliable
and High-Performance Computing, Center for Circuits and Systems Solution
(C2S2), University of Illinois at Urbana-Champaign, nor the names of its
contributors may be used to endorse or promote products derived from this
Software without specific prior written permission.
THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
WITH THE SOFTWARE.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*******************************************************************************
File: REGn.v
Description: This file contains the definition of a n-bit register
******************************************************************************/
`timescale 1ns/100ps
/*
* FUNC_NAME: REGn
*
* DESCRIPTION:
* Definition for a n-bit register, asynch. reset
*
* INPUT:
* reg_in - the value to be stored in the register on the next clock edge
* clk - the system clock
*
* OUTPUT:
* reg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 17-Apr-03
* LAST MODIFICATION:
* Created modules
*/
module REGn(reg_out, clk, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge
always @(posedge clk)
begin
reg_val <= reg_in;
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGn
/*
* FUNC_NAME: REGfn
*
* DESCRIPTION:
* Definition for a n-bit register, with synchronous AND asynchronous reset signal
*
* INPUT:
* reg_in - the value to be stored in the register on the next clock edge
* clk - the system clock
* flush - synchronous reset
*
* OUTPUT:
* reg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 19-Apr-03
* LAST MODIFICATION:
* Created modules
*/
module REGfn(reg_out, clk, reset, flush, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input reset;
input flush;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the flush signal is low
always @(posedge clk)
begin
if (flush == 1'b1)
begin
reg_val <= 'b0;
end
else
begin
reg_val <= reg_in;
end
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGfn
/*
* FUNC_NAME: REGln
*
* DESCRIPTION:
* Definition for a n-bit register, with load signal and synchronous reset
*
* INPUT:
* reg_in - the value to be stored in the register on the next clock edge
* clk - the system clock
* load - if we should store on the next clock edge
*
* OUTPUT:
* reg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 10-Apr-03
* LAST MODIFICATION:
* Created modules
*/
module REGln(reg_out, clk, load, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input load;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the load signal is high
always @(posedge clk)
begin
if (reset == 1'b1)
begin
reg_val <= 'b0;
end
else if (load == 1'b1)
begin
reg_val <= reg_in;
end
end
endmodule // REGln
/*
* FUNC_NAME: REGan
*
* DESCRIPTION:
* Definition for a n-bit register, with load signal and asynchronous reset
*
* INPUT:
* reg_in - the value to be stored in the register on the next clock edge
* clk - the system clock
* load - if we should store on the next clock edge
*
* OUTPUT:
* reg_out - the current value of the register
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 10-Apr-03
* LAST MODIFICATION:
* Created modules
*/
module REGan(reg_out, clk, load, reset, reg_in);
parameter RegLen = 63;
// outputs
output [RegLen:0] reg_out;
// inouts
// special inputs
input clk;
input load;
input reset;
// inputs
input [RegLen:0] reg_in;
// internal vars
reg [RegLen:0] reg_val;
// assign vars
// assign outputs
assign reg_out = reg_val;
// instantiate other modules
// change the value of the register on every rising clock edge if the load signal is high
always @(posedge clk)
begin
if (load == 1'b1)
begin
reg_val <= reg_in;
end
end
// async. reset
always @(posedge reset)
begin
reg_val = 'b0;
end
endmodule // REGan
|
#include <bits/stdc++.h> using namespace std; long long a[100001]; int main() { long long int n, i, count = 0; long long sum = 0; scanf( %I64d , &n); for (i = 0; i < n; i++) scanf( %I64d , a + i); sort(a, a + n); for (i = 0; i < n; i++) { if (sum <= a[i]) { count++; sum += a[i]; } } printf( %I64d n , count); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long N; cin >> N; vector<long long> a(N); for (auto &x : a) cin >> x; ; long long l = -1; for (int i = 0; i < N - 1; i++) { if (abs(a[i + 1] - a[i]) >= 2) { l = i; break; } } if (l == -1) cout << No << endl; else cout << Yes n << l + 1 << << l + 2 << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_SYMBOL_V
`define SKY130_FD_SC_HD__A31O_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_TB_V
`define SKY130_FD_SC_HVL__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long n; long long t1(0), t2(0); long long mn = 0, mx = 0; cin >> n; vector<long> vec(n, 0); for (long i = 0; i < n; i++) { cin >> vec[i]; } sort(vec.begin(), vec.end()); mn = vec[0]; mx = vec[n - 1]; for (long i = 0; i < vec.size(); i++) { t1 += (vec[i] == mn); t2 += (vec[i] == mx); } cout << mx - mn << ; if (mx - mn == 0) cout << n * (n - 1) / 2 << endl; else cout << t1 * t2 << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_FUNCTIONAL_V
|
/*
* Copyright (c) 2014, Aleksander Osman
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module simple_biclk_bidir_ram
#(parameter width = 1,
parameter widthad = 1)
(
input clk,
input [widthad-1:0] address_a,
input wren_a,
input [width-1:0] data_a,
output reg [width-1:0] q_a,
input clk2,
input [widthad-1:0] address_b,
output reg [width-1:0] q_b
);
reg [width-1:0] mem [(2**widthad)-1:0];
always @(posedge clk) begin
if(wren_a) mem[address_a] <= data_a;
q_a <= mem[address_a];
end
always @(posedge clk2) begin
q_b <= mem[address_b];
end
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
/* =========================================================================
*
* Filename: testbench_sample.v
* Date created: 05-28-2012
* Last modified: 11-30-2012
* Authors: Michael Papamichael <papamixATcs.cmu.edu>
*
* Description:
* Minimal testbench sample for CONNECT networks with Peek flow control
*
* =========================================================================
*/
`ifndef XST_SYNTH
`timescale 1ns / 1ps
`include "connect_parameters.v"
module CONNECT_testbench_sample_peek();
parameter HalfClkPeriod = 5;
localparam ClkPeriod = 2*HalfClkPeriod;
// non-VC routers still reeserve 1 dummy bit for VC.
localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;
localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);
localparam flit_port_width = 2 /*valid and tail bits*/+ `FLIT_DATA_WIDTH + dest_bits + vc_bits;
//localparam credit_port_width = 1 + vc_bits; // 1 valid bit
localparam credit_port_width = `NUM_VCS; // 1 valid bit
localparam test_cycles = 20;
reg Clk;
reg Rst_n;
// input regs
reg send_flit [0:`NUM_USER_SEND_PORTS-1]; // enable sending flits
reg [flit_port_width-1:0] flit_in [0:`NUM_USER_SEND_PORTS-1]; // send port inputs
reg send_credit [0:`NUM_USER_RECV_PORTS-1]; // enable sending credits
reg [credit_port_width-1:0] credit_in [0:`NUM_USER_RECV_PORTS-1]; //recv port credits
// output wires
wire [credit_port_width-1:0] credit_out [0:`NUM_USER_SEND_PORTS-1];
wire [flit_port_width-1:0] flit_out [0:`NUM_USER_RECV_PORTS-1];
reg [31:0] cycle;
integer i;
// packet fields
reg is_valid;
reg is_tail;
reg [dest_bits-1:0] dest;
reg [vc_bits-1:0] vc;
reg [`FLIT_DATA_WIDTH-1:0] data;
// Generate Clock
initial Clk = 0;
always #(HalfClkPeriod) Clk = ~Clk;
// Run simulation
initial begin
cycle = 0;
for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end
for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 'b1; send_credit[i] = 'b1; end //constantly provide credits
$display("---- Performing Reset ----");
Rst_n = 0; // perform reset (active low)
#(5*ClkPeriod+HalfClkPeriod);
Rst_n = 1;
#(HalfClkPeriod);
// send a 2-flit packet from send port 0 to receive port 1
send_flit[0] = 1'b1;
dest = 1;
vc = 0;
data = 'ha;
flit_in[0] = {1'b1 /*valid*/, 1'b0 /*tail*/, dest, vc, data};
$display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
#(ClkPeriod);
// send 2nd flit of packet
send_flit[0] = 1'b1;
data = 'hb;
flit_in[0] = {1'b1 /*valid*/, 1'b1 /*tail*/, dest, vc, data};
$display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
#(ClkPeriod);
// stop sending flits
send_flit[0] = 1'b0;
flit_in[0] = 'b0; // valid bit
end
// Monitor arriving flits
always @ (posedge Clk) begin
cycle <= cycle + 1;
for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin
if(flit_out[i][flit_port_width-1]) begin // valid flit
$display("@%3d: Ejecting flit %x at receive port %0d", cycle, flit_out[i], i);
end
end
// terminate simulation
if (cycle > test_cycles) begin
$finish();
end
end
// Add your code to handle flow control here (sending receiving credits)
// Instantiate CONNECT network
mkNetworkSimple dut
(.CLK(Clk)
,.RST_N(Rst_n)
,.send_ports_0_putFlit_flit_in(flit_in[0])
,.EN_send_ports_0_putFlit(send_flit[0])
,.EN_send_ports_0_getNonFullVCs(1'b1) // drain credits
,.send_ports_0_getNonFullVCs(credit_out[0])
,.send_ports_1_putFlit_flit_in(flit_in[1])
,.EN_send_ports_1_putFlit(send_flit[1])
,.EN_send_ports_1_getNonFullVCs(1'b1) // drain credits
,.send_ports_1_getNonFullVCs(credit_out[1])
// add rest of send ports here
//
,.EN_recv_ports_0_getFlit(1'b1) // drain flits
,.recv_ports_0_getFlit(flit_out[0])
,.recv_ports_0_putNonFullVCs_nonFullVCs(credit_in[0])
,.EN_recv_ports_0_putNonFullVCs(send_credit[0])
,.EN_recv_ports_1_getFlit(1'b1) // drain flits
,.recv_ports_1_getFlit(flit_out[1])
,.recv_ports_1_putNonFullVCs_nonFullVCs(credit_in[1])
,.EN_recv_ports_1_putNonFullVCs(send_credit[1])
// add rest of receive ports here
//
);
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { do { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); } while (false); string L, R; cin >> L >> R; reverse(L.begin(), L.end()); L.resize(R.size(), 0 ); reverse(L.begin(), L.end()); int n, m = 0; cin >> n; const int sigma = 10, M = 3 * R.size() * sigma + 100; vector<vector<int> > son(M, vector<int>(sigma)), sum(M, vector<int>(R.size())); function<void(int, int, bool, bool, bool)> gen = [&](int idx, int u, bool big, bool small, bool start) { if (idx >= R.size() || (big && small)) { sum[u][R.size() - idx]++; } else { for (int i = (big ? 0 : L[idx] - 0 ); i <= (small ? 9 : R[idx] - 0 ); i++) { int v = u; if (start || i) { if (!son[u][i]) { son[u][i] = m++; } v = son[u][i]; } gen(idx + 1, v, big || L[idx] - 0 < i, small || R[idx] - 0 > i, start || i); } } }; gen(0, m++, false, false, false); vector<int> fail(m); auto build = [&]() { queue<int> que; que.push(0); while (!que.empty()) { int u = que.front(); que.pop(); for (int i = 0; i < sigma; i++) { if (!son[u][i]) { son[u][i] = son[fail[u]][i]; } else { int v = fail[u]; while (v && !son[v][i]) { v = fail[v]; } if (son[v][i] && son[v][i] != son[u][i]) { fail[son[u][i]] = son[v][i]; for (int j = 0; j < R.size(); j++) { sum[son[u][i]][j] += sum[son[v][i]][j]; } } que.push(son[u][i]); } } } }; build(); vector<vector<int> > trans(m, vector<int>(sigma)); for (int u = 0; u < m; u++) { for (int i = 1; i < R.size(); i++) { sum[u][i] += sum[u][i - 1]; } for (int i = 0; i < sigma; i++) { int v = u; while (v && !son[v][i]) { v = fail[v]; } trans[u][i] = son[v][i]; } } vector<vector<int> > dp(n + 1, vector<int>(m, -1e9)); dp[0][0] = 0; for (int i = 0; i < n; i++) { for (int u = 0; u < m; u++) { if (dp[i][u] >= 0) { for (int j = 0; j < sigma; j++) { int v = trans[u][j]; dp[i + 1][v] = max(dp[i + 1][v], dp[i][u] + sum[v][min((int)R.size(), n - i) - 1]); } } } } int goal = *max_element(dp[n].begin(), dp[n].end()); cout << goal << endl; vector<vector<bool> > on(n + 1, vector<bool>(m)); for (int i = 0; i < m; i++) { on[n][i] = dp[n][i] == goal; } for (int i = n - 1; i >= 0; i--) { for (int u = 0; u < m; u++) { if (dp[i][u] >= 0) { bool ok = false; for (int j = 0; j < sigma; j++) { int v = trans[u][j]; ok |= on[i + 1][v] && dp[i][u] + sum[v][min((int)R.size(), n - i) - 1] == dp[i + 1][v]; } on[i][u] = ok; } } } int u = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < sigma; j++) { int v = trans[u][j]; if (on[i + 1][v] && dp[i][u] + sum[v][min((int)R.size(), n - i) - 1] == dp[i + 1][v]) { cout << j; u = v; break; } } } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int a, b, c, ans, x[4]; int main() { cin >> a >> b >> c; x[0] = a + b + c; x[1] = a + c + c + a; x[2] = b + c + c + b; x[3] = b + b + a + a; ans = x[0]; for (int i = 1; i < 4; i++) { if (ans > x[i]) ans = x[i]; } cout << ans << endl; return 0; }
|
`timescale 1ps/1ps
module tb_gcd16;
parameter DELAY = 1;
parameter NUM_DATA = 2;
parameter [15:0] x_data [0:NUM_DATA-1] = {10000, 1000};
parameter [15:0] y_data [0:NUM_DATA-1] = {1000, 10000};
integer counter;
reg activate_0r; wire activate_0a;
reg x_0a; wire x_0r; reg [15:0] x_0d;
reg y_0a; wire y_0r; reg [15:0] y_0d;
reg z_0a; wire z_0r; wire [15:0] z_0d;
reg initialise;
Balsa_gcd16 (
.activate_0r(activate_0r), .activate_0a(activate_0a),
.x_0a(x_0a), .x_0r(x_0r), .x_0d(x_0d),
.y_0a(y_0a), .y_0r(y_0r), .y_0d(y_0d),
.z_0a(z_0a), .z_0r(z_0r), .z_0d(z_0d),
.initialise(initialise)
);
always@(posedge z_0r) begin
if (activate_0r) begin
$display("gcd(%d, %d) = %d", x_0d, y_0d, z_0d);
end
end
always@(x_0r) begin
if (x_0r) begin
#DELAY x_0d = x_data[counter];
end
#DELAY x_0a = x_0r;
end
always@(y_0r) begin
if (y_0r) begin
#DELAY y_0d = y_data[counter];
end
#DELAY y_0a = y_0r;
end
always@(z_0r) begin
#DELAY
z_0a = z_0r;
if (activate_0r && !z_0r) begin
counter = counter + 1;
if (counter >= NUM_DATA) begin
$finish;
end
end
end
initial begin
counter = 0;
x_0d = 0;
y_0d = 0;
x_0a = 0;
y_0a = 0;
z_0a = 0;
activate_0r = 0;
initialise = 1;
#DELAY initialise = 0;
#DELAY activate_0r = 1;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:53:12 09/29/2016
// Design Name:
// Module Name: vga640x480
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga640x480(
input wire clk,
input wire [2:0] redin,
input wire [2:0] greenin,
input wire [1:0] bluein,
output reg [9:0] hc,
output reg [9:0] vc,
output wire hsync,
output wire vsync,
output reg [2:0] red,
output reg [2:0] green,
output reg [1:0] blue
);
// Constantes de la estructura de video
parameter hpixels = 800;// Pixeles horizontales
parameter vlines = 521; // Lineas verticales
parameter hpulse = 96; // hsync pulse length
parameter vpulse = 2; // vsync pulse length
parameter hbp = 144; // Fin del "back-porch" horizontal
parameter hfp = 784; // Inicio del "front-porch" horizontal
parameter vbp = 31; // Fin del "back-porch" vertical
parameter vfp = 511; // Inicio del "front-porch" vertical
// Zona horizontal: 784 - 144 = 640
// Zona vertical: 511 - 31 = 480
// Las asignaciones solo pueden ser "non-blocking": <=
always @(posedge clk)
begin
if (hc < hpixels - 1) // Se cuenta hasta los 800 pixeles (fin de la línea)
hc <= (hc + 1'b1);
else // Se llega al fin de la línea
begin
hc <= 0;
if (vc < vlines - 1)
vc <= (vc + 1'b1);
else
vc <= 0;
end
end
// Se generan los pulsos de sincronización (activo en 0)
assign hsync = (hc < hpulse) ? 1'b0:1'b1;
assign vsync = (vc < vpulse) ? 1'b0:1'b1;
// Se dibuja en pantalla
always @(*)
begin
if (vc >= vbp && vc < vfp) // Si está en el rango vertical
begin
if (hc >= hbp && hc < (hbp+640)) // Si está en el rango horizontal
begin
red = redin;
green = greenin;
blue = bluein;
end
else // afuera del rango horizontal negro
begin
red = 0;
green = 0;
blue = 0;
end
end
else // afuera del rango vertical negro
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule
|
#include <bits/stdc++.h> int main() { int n; int a[10000]; while (scanf( %d , &n) != EOF) { for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) { if (a[i] % 2 == 0) a[i] -= 1; } for (int i = 1; i <= n - 1; i++) printf( %d , a[i]); printf( %d n , a[n]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const int dx4[] = {-1, 0, 1, 0}; const int dy4[] = {0, 1, 0, -1}; const int dx8[] = {-1, -1, -1, 0, 0, 1, 1, 1}; const int dy8[] = {-1, 0, 1, -1, 1, -1, 0, 1}; inline long long Int() { long long num = 0; char c = getchar_unlocked(); bool sign = true; while (!((c >= 0 && c <= 9 ) || c == - )) c = getchar_unlocked(); if (c == - ) { sign = false; c = getchar_unlocked(); } while (c >= 0 && c <= 9 ) { num = (num << 1) + (num << 3) + c - 0 ; c = getchar_unlocked(); } return sign ? num : -num; } template <class S, class T> ostream& operator<<(ostream& out, const pair<S, T>& P) { out << { << P.first << , << P.second << } ; return out; } template <class T> ostream& operator<<(ostream& out, const vector<T>& v) { out << [ ; for (int i = 0; i < (int)v.size(); ++i) { out << v[i]; if (i + 1 < (int)v.size()) out << , ; } out << ] ; return out; } template <class S, class T> ostream& operator<<(ostream& out, const map<S, T>& mp) { out << [ n ; for (const auto& x : mp) { out << { << x.first << , << x.second << } n ; } out << ] n ; return out; } template <class T> ostream& operator<<(ostream& out, const set<T>& cs) { out << { ; for (auto it = cs.begin(); it != cs.end();) { out << *it; it++; if (it != cs.end()) out << , ; else out << } ; } return out; } void solve(); int main() { cout << fixed << setprecision(15); cerr << fixed << setprecision(15); solve(); return 0; } const double eps = 1e-10; const int mod = (int)1e9 + 7; const int N = (int)2e5 + 5; int sm(string S) { int r = 0; for (char c : S) r += (c - 48); return r; } int sm(long long x) { int r = 0; while (x) { r += (x % 10); x /= 10; } return r; } string sub(string a, string b) { reverse((a).begin(), (a).end()); reverse((b).begin(), (b).end()); while (((int)(b).size()) < ((int)(a).size())) b += 0 ; string res = ; int carry = 0; for (int i = 0; i < (((int)(a).size())); ++i) { int x = a[i] - 48, y = b[i] - 48; int add = -1; if (x >= y + carry) { add = x - (y + carry); carry = 0; } else { add = (x + 10) - (y + carry); carry = 1; } res += (char)(add + 48); } if (carry) { cout << ERROR << n ; return ; } reverse((res).begin(), (res).end()); return res; } void print(string b) { int i = 0; while (i < ((int)(b).size()) && b[i] == 0 ) ++i; while (i < ((int)(b).size())) putchar(b[i++]); } void solve() { int n = Int(), m = Int(); string ab = ; for (int i = 0; i < (m); ++i) ab += 1 ; string a = ; for (int i = 0; i < (n); ++i) a += 1 ; while (((int)(ab).size()) < ((int)(a).size()) + 1) ab += 0 ; cout << a << n ; string b = sub(ab, a); print(b); putchar( n ); }
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module E1x0
(input CLK_FPGA_P, input CLK_FPGA_N, // Diff
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
input debug_pb, output FPGA_TXD, input FPGA_RXD,
output fpga_txd1, input fpga_rxd1, input overo_txd1, output overo_rxd1,
// GPMC
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
input EM_NWE, input EM_NOE,
inout db_sda, inout db_scl, // I2C
output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI
output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI
output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI
output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI
input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
input overo_gpio65, input overo_gpio128, input overo_gpio145, output overo_gpio147, //aux SPI
output overo_gpio144, output overo_gpio146, // Fifo controls
input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO
input overo_gpio23, input overo_gpio64, input overo_gpio127, // Misc GPIO
input overo_gpio176, input overo_gpio163, input overo_gpio170, // Misc GPIO
inout [15:0] io_tx, inout [15:0] io_rx,
output [13:0] TX, output TXSYNC, output TXBLANK,
input [11:0] DA, input [11:0] DB, input RXSYNC,
input PPS_IN
);
assign FPGA_TXD = 0; //dont care
// /////////////////////////////////////////////////////////////////////////
// Clocking
wire clk_fpga;
wire reset;
reg por_rst;
reg [7:0] por_counter = 8'h0;
always @(posedge clk_fpga)
if (por_counter != 8'h55)
begin
por_counter <= por_counter + 8'h1;
por_rst <= 1'b1;
end
else por_rst <= 1'b0;
wire async_reset;
cross_clock_reader #(.WIDTH(1)) read_gpio_reset
(.clk(clk_fpga), .rst(por_rst), .in(cgen_sen_b & ~cgen_sclk), .out(async_reset));
IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
reset_sync reset_sync(.clk(clk_fpga), .reset_in(async_reset), .reset_out(reset));
// /////////////////////////////////////////////////////////////////////////
// UART level conversion
assign fpga_txd1 = overo_txd1;
assign overo_rxd1 = fpga_rxd1;
// SPI
wire mosi, sclk, miso;
assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
//assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; //replaced by aux spi
assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
(~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
//assign the aux spi to the cgen (bypasses control fifo)
assign cgen_sclk = overo_gpio65;
assign cgen_sen_b = overo_gpio128;
assign cgen_mosi = overo_gpio145;
wire has_resp; //re-purpose gpio for interrupt when we are not using aux spi
assign overo_gpio147 = (cgen_sen_b == 1'b0)? cgen_miso : has_resp;
wire _cgen_sen_b;
//assign cgen_sen_b = _cgen_sen_b; //replaced by aux spi
// /////////////////////////////////////////////////////////////////////////
// TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
assign TXBLANK = 0;
wire [13:0] tx_i, tx_q;
reg[13:0] delay_q;
always @(posedge clk_fpga)
delay_q <= tx_q;
genvar i;
generate
for(i=0;i<14;i=i+1)
begin : gen_dacout
ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(tx_i[i]), // 1-bit data input (associated with C0)
.D1(delay_q[i]), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
end // block: gen_dacout
endgenerate
ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data
.C0(clk_fpga), // 1-bit clock input
.C1(~clk_fpga), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b0), // 1-bit data input (associated with C0)
.D1(1'b1), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0)); // 1-bit set input
// /////////////////////////////////////////////////////////////////////////
// RX ADC -- handles inversion
reg [11:0] rx_i, rx_q;
always @(posedge clk_fpga) begin
rx_i <= ~DA;
rx_q <= ~DB;
end
// /////////////////////////////////////////////////////////////////////////
// Main Core
wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
wire dsp_rx_run, dsp_tx_run;
wire [7:0] sen8;
assign {_cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx} = sen8[3:0];
wire [31:0] core_debug;
assign debug_led = ~{PPS_IN, dsp_tx_run, dsp_rx_run, cgen_st_ld};
wire cgen_sync;
assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
u1plus_core #(
.NUM_RX_DSPS(2),
.DSP_RX_XTRA_FIFOSIZE(10),
.DSP_TX_XTRA_FIFOSIZE(10),
.USE_PACKET_PADDER(0)
) core(
.clk(clk_fpga), .reset(reset),
.debug(core_debug), .debug_clk(debug_clk),
.rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
.tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
.ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
.resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
.dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
.clock_sync(cgen_sync),
.db_sda(db_sda), .db_scl(db_scl),
.sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
.io_tx(io_tx), .io_rx(io_rx),
.tx_i(tx_i), .tx_q(tx_q),
.rx_i(rx_i), .rx_q(rx_q),
.pps_in(PPS_IN) );
// /////////////////////////////////////////////////////////////////////////
// Interface between GPMC/host
wire [31:0] gpmc_debug;
gpmc #(.TXFIFOSIZE(13), .RXFIFOSIZE(13))
gpmc (.arst(async_reset),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
.EM_NOE(EM_NOE),
.rx_have_data(overo_gpio146), .tx_have_space(overo_gpio144),
.resp_have_data(has_resp),
.fifo_clk(clk_fpga), .fifo_rst(reset),
.rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
.tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
.ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
.resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
.debug(gpmc_debug));
//assign debug = gpmc_debug;
assign debug = core_debug;
endmodule // E1x0
|
#include <bits/stdc++.h> using namespace std; int m, k, d; void print(int a, int b) { printf( %d %d n , a, b); a += d, b += d; printf( %d %d n , a, b); } int main() { cin >> k; if (k % 2 == 0) { cout << NO ; return 0; } cout << YES << endl; d = 4 * k - 2, m = (k * d) / 2; cout << d << << m << endl; d /= 2; cout << 1 << << 1 + d << endl; for (int i = 2; i <= k; i++) print(1, i); for (int i = 2; i <= k; i++) for (int j = k + 1; j <= 2 * k - 1; j++) print(i, j); for (int i = 0; i < (k / 2); i++) print(k + 1 + 2 * i, k + 2 + 2 * i); return 0; }
|
#include <bits/stdc++.h> using std::cerr; const int N = 998244, M = 1001; int n, m, d[N], las[N], seq[N], cnt[M][M], blo, x[N], y[N]; inline void add(int a, int b, int val) { seq[a] += val, seq[b + 1] -= val; } signed main() { std::ios::sync_with_stdio(0); scanf( %d%d , &n, &m), blo = sqrt(m); for (int i = 1; i <= n; i++) scanf( %d%d , &x[i], &y[i]); int op, k; for (int now = 1; now <= m; now++) { scanf( %d%d , &op, &k); if (op == 1) { if (x[k] + y[k] <= blo) { for (int i = x[k]; i < x[k] + y[k]; i++) cnt[x[k] + y[k]][(now + i) % (x[k] + y[k])]++; } else for (int i = now + x[k]; i <= m; i += x[k] + y[k]) add(i, i + y[k] - 1, 1); las[k] = now; } else { if (x[k] + y[k] <= blo) { for (int i = x[k]; i < x[k] + y[k]; i++) cnt[x[k] + y[k]][(las[k] + i) % (x[k] + y[k])]--; } else { for (int i = las[k] + x[k]; i <= m; i += x[k] + y[k]) { if (i + y[k] - 1 < now) continue; if (i <= now && i + y[k] - 1 >= now) add(now, i + y[k] - 1, -1); else add(i, i + y[k] - 1, -1); } } } int ans = 0; for (int i = 2; i <= blo; i++) { ans += cnt[i][now % i]; } seq[now] += seq[now - 1]; printf( %d n , ans + seq[now]); } }
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_reg1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [22:0] c;
// Output of stage 2
wire [22:0] cx;
// Output of stage 3
wire [10:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [10:0] b;
reg [10:0] r_b;
reg [22:0] e;
reg [22:0] r_e;
// 2nd stage
reg [22:0] r_c;
reg [22:0] rr_e;
reg [10:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [14:0] cx;
//reg [10:0] qx;
reg [22:0] r_qx;
reg [10:0] rb;
reg clk,reset;
reg [22:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000100000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00001000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00100000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 23'b00000000000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll MOD = 1e9 + 7; class SegTree { private: const ll NEUT = 0; vector<ll> seg, tag; int h = 1; ll len(int i) { return h >> (31 - __builtin_clz(i)); } void apply(int i, ll v) { seg[i] = (seg[i] + v * len(i)) % MOD; if (i < h) tag[i] = (tag[i] + v) % MOD; } void push(int i) { if (tag[i] == 0) return; apply(2 * i, tag[i]); apply(2 * i + 1, tag[i]); tag[i] = 0; } ll combine(ll a, ll b) { return (a + b) % MOD; } ll recGet(int a, int b, int i, int ia, int ib) { if (ib <= a || b <= ia) return NEUT; if (a <= ia && ib <= b) return seg[i]; push(i); int im = (ia + ib) >> 1; return combine(recGet(a, b, 2 * i, ia, im), recGet(a, b, 2 * i + 1, im, ib)); } void recApply(int a, int b, ll v, int i, int ia, int ib) { if (ib <= a || b <= ia) return; if (a <= ia && ib <= b) apply(i, v); else { push(i); int im = (ia + ib) >> 1; recApply(a, b, v, 2 * i, ia, im); recApply(a, b, v, 2 * i + 1, im, ib); seg[i] = combine(seg[2 * i], seg[2 * i + 1]); } } public: SegTree(int n) { while (h < n) h *= 2; seg.resize(2 * h, NEUT); tag.resize(h, 0); } ll rangeSum(int a, int b) { return recGet(a, b + 1, 1, 0, h); } void rangeAdd(int a, int b, ll v) { recApply(a, b + 1, v, 1, 0, h); } }; class HLD { private: vector<int> par, siz, cmp, ind; void dfs1(int i, vector<vector<int>>& g) { for (auto& t : g[i]) { if (t == par[i]) continue; par[t] = i; dfs1(t, g); siz[i] -= siz[t]; if (siz[t] > siz[g[i][0]]) swap(t, g[i][0]); } siz[i] *= -1; } void dfs2(int i, int& x, const vector<vector<int>>& g) { ind[i] = x; ++x; for (auto t : g[i]) { if (t == par[i]) continue; cmp[t] = (x == ind[i] + 1 ? cmp[i] : t); dfs2(t, x, g); } } public: HLD(vector<vector<int>> g, int r = 0) : par(g.size(), -1), siz(g.size(), -1), cmp(g.size(), r), ind(g.size()) { dfs1(r, g); int x = 0; dfs2(r, x, g); } const vector<pair<int, int>>& path(int a, int b) const { static vector<pair<int, int>> res; res.clear(); for (;; b = par[cmp[b]]) { if (ind[b] < ind[a]) swap(a, b); if (ind[cmp[b]] <= ind[a]) { res.push_back({ind[a], ind[b]}); return res; } res.push_back({ind[cmp[b]], ind[b]}); } } pair<int, int> subtree(int i) const { return {ind[i], ind[i] + siz[i] - 1}; } int lca(int a, int b) const { for (;; b = par[cmp[b]]) { if (ind[b] < ind[a]) swap(a, b); if (ind[cmp[b]] <= ind[a]) return a; } } bool deeper(int a, int b) { return siz[a] < siz[b]; } }; ll modPow(ll a, ll b) { if (b & 1) return a * modPow(a, b - 1) % MOD; if (b == 0) return 1; return modPow(a * a % MOD, b / 2); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; ll colc = 1; vector<ll> weight(n); vector<pair<int, int>> evs; for (int i = 0; i < n; ++i) { int a, b; cin >> a >> b; evs.push_back({a, i + 1}); evs.push_back({b + 1, -(i + 1)}); colc = (colc * (b - a + 1)) % MOD; weight[i] = modPow(b - a + 1, MOD - 2); } sort(evs.begin(), evs.end()); vector<vector<int>> g(n); for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b; --a; --b; g[a].push_back(b); g[b].push_back(a); } HLD hld(g); ll cur = 0; ll res = 0; SegTree above(n), below(n); int c = 0; for (int j = 0; j < evs.size(); ++j) { int nc = evs[j].first; res = (res + cur * (nc - c)) % MOD; c = nc; int i = abs(evs[j].second) - 1; ll v = (evs[j].second < 0 ? MOD - 1 : 1) * weight[i] % MOD; vector<pair<int, int>> path = hld.path(i, 0); int pi = n - 1; for (auto pr : path) { cur = (cur + v * below.rangeSum(pr.second + 1, pi)) % MOD; above.rangeAdd(pr.second + 1, pi, v); cur = (cur + v * above.rangeSum(pr.first, pr.second)) % MOD; below.rangeAdd(pr.first, pr.second, v); pi = pr.first - 1; } } res = (res * colc) % MOD; if (res < 0) res += MOD; cout << res << n ; }
|
#include <bits/stdc++.h> using namespace std; struct state { state(int a, int b, int c, int d) : num(a), ind1(b), ind2(c), oper(d){}; int num; int ind1, ind2; int oper; }; vector<state> ansState; int n, ans = 100000; map<set<int>, int> m; vector<state> v; void dfs() { if (v[v.size() - 1].num == n) { if (v.size() < ans) { ans = v.size(); ansState = v; } return; } if (v.size() >= ans || v.size() > 5) return; set<int> s; for (int i = 0; i < v.size(); ++i) s.insert(v[i].num); if (m[s]) return; m.insert(make_pair(s, 1)); for (int i = 0; i < v.size(); ++i) { for (int j = 1; j <= 3; ++j) { int x = v[i].num * (1 << j); if (x > n) break; int flag = 1; for (int k = 0; k < v.size(); ++k) if (v[k].num == x) { flag = 0; break; } if (!flag) continue; v.push_back(state(x, i, -1, j)); dfs(); v.pop_back(); } for (int j = 0; j < v.size(); ++j) for (int k = 0; k <= 3; ++k) { int x = v[i].num + (1 << k) * v[j].num; if (x > n) break; int flag = 1; for (int t = 0; t < v.size(); ++t) if (v[t].num == x) { flag = 0; break; } if (flag) { v.push_back(state(x, i, j, 4 + k)); dfs(); v.pop_back(); } } } } int Solution() { cin >> n; v.push_back(state(1, -1, -1, -1)); dfs(); cout << ans - 1 << endl; for (int i = 1; i < ansState.size(); ++i) { cout << lea e << (char)( a + i) << x, [ ; if (ansState[i].oper < 4) { cout << (1 << ansState[i].oper) << *e << (char)( a + ansState[i].ind1) << x] << endl; } if (ansState[i].oper == 4) { cout << e << (char)( a + ansState[i].ind1) << x + << e << (char)( a + ansState[i].ind2) << x] << endl; } if (ansState[i].oper > 4) { cout << e << (char)( a + ansState[i].ind1) << x + << (1 << (ansState[i].oper - 4)) << * << e << (char)( a + ansState[i].ind2) << x] << endl; } } return 0; } int main() { Solution(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = n, p = 1; i - 1; i >>= 1, p <<= 1) { for (int j = 0; j < (i + 1) / 2; j++) cout << p << ; if (n % p) n -= p / 2; } cout << n; }
|
// ============================================================================
// Copyright (c) 2012 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
//
// web: http://www.terasic.com/
// email:
//
// ============================================================================
/*
Function:
WOLFSON WM8731 controller
I2C Configuration Requirements:
Master Mode
I2S, 16-bits
Clock:
18.432MHz to XTI/MCLK pin of WM8731
Revision:
1.0, 10/22/2007, Init by Richard
Compatibility:
Quartus 7.2
*/
//`include "./AUDIO_ADC.v"
//`include "./AUDIO_DAC.v"
//`include "./audio_fifo.v"
module AUDIO_IF(
avs_s1_clk,
avs_s1_reset,
avs_s1_address,
avs_s1_read,
avs_s1_readdata,
avs_s1_write,
avs_s1_writedata,
//
avs_s1_export_BCLK,
avs_s1_export_DACLRC,
avs_s1_export_DACDAT,
avs_s1_export_ADCLRC,
avs_s1_export_ADCDAT,
avs_s1_export_XCK
);
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
`define DAC_LFIFO_ADDR 0
`define DAC_RFIFO_ADDR 1
`define ADC_LFIFO_ADDR 2
`define ADC_RFIFO_ADDR 3
`define CMD_ADDR 4
`define STATUS_ADDR 5
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input avs_s1_clk;
input avs_s1_reset;
input [2:0] avs_s1_address;
input avs_s1_read;
output [15:0] avs_s1_readdata;
input avs_s1_write;
input [15:0] avs_s1_writedata;
//
input avs_s1_export_BCLK;
input avs_s1_export_DACLRC;
output avs_s1_export_DACDAT;
input avs_s1_export_ADCLRC;
input avs_s1_export_ADCDAT;
output avs_s1_export_XCK;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// host
reg [15:0] reg_readdata;
reg fifo_clear;
// dac
wire dacfifo_full;
reg dacfifo_write;
reg [31:0] dacfifo_writedata;
// adc
wire adcfifo_empty;
reg adcfifo_read;
wire [31:0] adcfifo_readdata;
reg [31:0] data32_from_adcfifo;
reg [31:0] data32_from_adcfifo_2;
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
////////// fifo clear
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset)
fifo_clear <= 1'b0;
else if (avs_s1_write && (avs_s1_address == `CMD_ADDR))
fifo_clear <= avs_s1_writedata[0];
else if (fifo_clear)
fifo_clear <= 1'b0;
end
////////// write audio data(left&right) to dac-fifo
always @ (posedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
begin
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_LFIFO_ADDR))
begin
dacfifo_writedata[31:16] <= avs_s1_writedata;
dacfifo_write <= 1'b0;
end
else if (avs_s1_write && (avs_s1_address == `DAC_RFIFO_ADDR))
begin
dacfifo_writedata[15:0] <= avs_s1_writedata;
dacfifo_write <= 1'b1;
end
else
dacfifo_write <= 1'b0;
end
////////// response data to avalon-mm
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset || fifo_clear)
data32_from_adcfifo = 0;
else if (avs_s1_read && (avs_s1_address == `STATUS_ADDR))
reg_readdata <= {adcfifo_empty, dacfifo_full};
else if (avs_s1_read && (avs_s1_address == `ADC_LFIFO_ADDR))
reg_readdata <= data32_from_adcfifo[31:16];
else if (avs_s1_read && (avs_s1_address == `ADC_RFIFO_ADDR))
begin
reg_readdata <= data32_from_adcfifo[15:0];
data32_from_adcfifo <= data32_from_adcfifo_2;
end
end
////////// read audio data from adc fifo
always @ (negedge avs_s1_clk)
begin
if (avs_s1_reset)
begin
adcfifo_read <= 1'b0;
data32_from_adcfifo_2 <= 0;
end
else if ((avs_s1_address == `ADC_LFIFO_ADDR) & avs_s1_read & ~adcfifo_empty)
begin
adcfifo_read <= 1'b1;
end
else if (adcfifo_read)
begin
data32_from_adcfifo_2 = adcfifo_readdata;
adcfifo_read <= 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign avs_s1_readdata = reg_readdata;
assign avs_s1_export_XCK = avs_s1_clk;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
AUDIO_DAC DAC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.write(dacfifo_write),
.writedata(dacfifo_writedata),
.full(dacfifo_full),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.daclrc(avs_s1_export_DACLRC),
.dacdat(avs_s1_export_DACDAT)
);
AUDIO_ADC ADC_Instance(
// host
.clk(avs_s1_clk),
.reset(avs_s1_reset),
.read(adcfifo_read),
.readdata(adcfifo_readdata),
.empty(adcfifo_empty),
.clear(fifo_clear),
// dac
.bclk(avs_s1_export_BCLK),
.adclrc(avs_s1_export_ADCLRC),
.adcdat(avs_s1_export_ADCDAT)
);
defparam
DAC_Instance.DATA_WIDTH = 32;
defparam
ADC_Instance.DATA_WIDTH = 32;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3,no-stack-protector,unroll-loops,fast-math ) using namespace std; struct coor { long long x, y, x1, y1; }; vector<struct coor> v; struct coor ldp[200005], rdp[200005]; struct coor inter(struct coor l, struct coor r) { struct coor res = {INT_MIN, INT_MIN, INT_MIN, INT_MIN}; if (min(l.x1, r.x1) < max(r.x, l.x) || min(l.y1, r.y1) < max(r.y, l.y)) return res; res.x = max(l.x, r.x); res.x1 = min(l.x1, r.x1); res.y = max(l.y, r.y); res.y1 = min(l.y1, r.y1); return res; } bool check(struct coor l) { return (l.x != INT_MIN); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long a = 0, b = 0, c, d, e, f = 0, l, g, m, n, k, i, j, t, p, q; cin >> n; for (i = 0; i < n; i++) { cin >> a >> b >> c >> d; v.push_back({a, b, c, d}); } ldp[0] = v[0]; for (i = 1; i < n; i++) { ldp[i] = inter(ldp[i - 1], v[i]); } rdp[n - 1] = v[n - 1]; for (i = n - 2; i >= 0; i--) { rdp[i] = inter(rdp[i + 1], v[i]); } if (check(ldp[n - 2])) { cout << ldp[n - 2].x << << ldp[n - 2].y << n ; } else if (check(rdp[1])) { cout << rdp[1].x << << rdp[1].y << n ; } else { for (i = 1; i < n - 1; i++) { struct coor fin = inter(ldp[i - 1], rdp[i + 1]); if (check(fin)) { cout << fin.x << << fin.y << n ; return 0; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, i, j; cin >> n; int arr[n], locked[n]; for (i = 0; i < n; i++) cin >> arr[i]; for (i = 0; i < n; i++) cin >> locked[i]; vector<int> unlocked; for (i = 0; i < n; i++) if (!locked[i]) unlocked.push_back(arr[i]); sort(unlocked.begin(), unlocked.end()); j = unlocked.size() - 1; for (i = 0; i < n; i++) { if (!locked[i]) arr[i] = unlocked[j--]; } for (i = 0; i < n; i++) cout << arr[i] << ; cout << endl; } int main() { int t; cin >> t; while (t--) solve(); return 0; }
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module bt656cap_input(
input sys_clk,
input sys_rst,
input vid_clk,
input [7:0] p,
output stb,
input ack,
output field,
output [31:0] rgb565
);
wire decoder_stb;
wire decoder_field;
wire [31:0] decoder_ycc422;
bt656cap_decoder decoder(
.vid_clk(vid_clk),
.p(p),
.stb(decoder_stb),
.field(decoder_field),
.ycc422(decoder_ycc422)
);
wire colorspace_stb;
wire colorspace_field;
wire [31:0] colorspace_rgb565;
bt656cap_colorspace colorspace(
.vid_clk(vid_clk),
.stb_i(decoder_stb),
.field_i(decoder_field),
.ycc422(decoder_ycc422),
.stb_o(colorspace_stb),
.field_o(colorspace_field),
.rgb565(colorspace_rgb565)
);
wire empty;
asfifo #(
.data_width(33),
.address_width(6)
) fifo (
.data_out({field, rgb565}),
.empty(empty),
.read_en(ack),
.clk_read(sys_clk),
.data_in({colorspace_field, colorspace_rgb565}),
.full(),
.write_en(colorspace_stb),
.clk_write(vid_clk),
.rst(sys_rst)
);
assign stb = ~empty;
endmodule
|
#include <bits/stdc++.h> using namespace std; map<char, int> M; char t[7] = { B , u , l , b , a , s , r }; int num[7] = {1, 2, 1, 1, 2, 1, 1}; char ch[200020]; int main() { scanf( %s , ch); int n = strlen(ch); for (int i = 0; i < n; i++) M[ch[i]]++; int ans = 1 << 30; for (int i = 0; i < 7; i++) ans = min(ans, M[t[i]] / num[i]); printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int a[maxn], used[maxn], change[maxn]; int n, m, odd, even, sz, ans; int o = 0, e = 0; map<int, int> id; int num[maxn]; int main(void) { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] % 2 == 0) even++; else odd++; if (!id[a[i]]) id[a[i]] = ++sz; num[id[a[i]]]++; } for (int i = 1; i <= n; i++) { if (num[id[a[i]]] > 1) { change[i] = true; num[id[a[i]]]--; if (a[i] % 2 == 0) even--; else odd--; ans++; } } for (int i = 1; i <= n; i++) if (!change[i]) { if (odd > n / 2 && a[i] % 2 == 1) { change[i] = true; num[id[a[i]]]--; odd--; ans++; } else if (even > n / 2 && a[i] % 2 == 0) { change[i] = true; num[id[a[i]]]--; even--; ans++; } } for (int i = 1; i <= n; i++) if (change[i]) { if (odd < n / 2) { if (o == 0) o = 1; while (id[o]) o += 2; a[i] = o; id[o] = ++sz; odd++; } else if (even < n / 2) { if (e == 0) e = 2; while (id[e]) e += 2; a[i] = e; id[e] = ++sz; even++; } } if (o > m || e > m) printf( -1 n ); else { printf( %d n , ans); for (int i = 1; i <= n; i++) { printf( %d , a[i]); } puts( ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 2e6 + 10; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m, k; cin >> n >> m >> k; if (n == 1 && m == 1) { cout << 0 ; return 0; } if (n * m == 2) { cout << 4 nUDLR ; return 0; } int t = n - 1 + m - 1 + n * m; cout << t << n ; for (int i = (0); i < (n - 1); ++i) cout << U ; for (int i = (0); i < (m - 1); ++i) cout << L ; for (int i = (1); i < (n + 1); ++i) { if (i & 1) { for (int j = (0); j < (m - 1); ++j) cout << R ; cout << D ; } else { for (int j = (0); j < (m - 1); ++j) cout << L ; cout << D ; } } return 0; }
|
//`include "gpio_test.v"
`include "ram_defines.v"
module ram0_top(
//Wishbone interface
input clk_i,
input rst_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input [31:0] wb_addr_i,
input [3:0] wb_sel_i,
input wb_we_i,
input [31:0] wb_data_i,
output [31:0] wb_data_o,
//FIFO write to ram
input openRISC_STALL,
input RAM_WE,
input [15:0] RAM_ADDR,
input [31:0] RAM_DATA_I,
output [31:0] RAM_DATA_O,
//GPIO signals
output [7:0] GPIO_o, //LED
input [1:0] GPIO_i //Button
);
wire [31:0] ram_out_normal;
wire [31:0] ram_out_GPIO;
// request signal
wire request;
// inputs to ram
`ifdef RAM_65536
wire [15:0] ram_address;
`endif
`ifdef RAM_8192
wire [12:0] ram_address;
`endif
wire [31:0] ram_data;
wire [3:0] ram_byteena;
wire ram_wren;
// request signal's rising edge
reg request_delay;
wire request_rising_edge;
// ack signal
reg ram_ack;
// get request signal
assign request = wb_stb_i & wb_cyc_i;
// select data to on-chip ram only when request = '1'
// otherwise wren will be '0', so that no data will be
// written into onchip ram by mistake.
assign ram_data = (openRISC_STALL==1'b1)? RAM_DATA_I
:(request == 1'b1)? (wb_data_i & {{8{ram_byteena[3]}},{8{ram_byteena[2]}},{8{ram_byteena[1]}},{8{ram_byteena[0]}}}):32'b0; //xilinx
assign ram_byteena = (openRISC_STALL==1'b1)? 4'b1111
:(request == 1'b1)? wb_sel_i:4'b0;
assign ram_wren = (openRISC_STALL==1'b1)? RAM_WE
:(request == 1'b1)? wb_we_i:1'b0;
`ifdef RAM_65536
assign ram_address = (openRISC_STALL==1'b1)? RAM_ADDR
:(request == 1'b1)? wb_addr_i[17:2]:16'b0;
assign RAM_DATA_O = (ram_address == 16'hffff) ? ram_out_GPIO : ram_out_normal; //16'hffff is for our GPIO
assign wb_data_o = (ram_address == 16'hffff) ? ram_out_GPIO : ram_out_normal; //16'hffff is for our GPIO
`endif
`ifdef RAM_8192
assign ram_address = (openRISC_STALL==1'b1)? RAM_ADDR[12:0]
:(request == 1'b1)? wb_addr_i[14:2]:13'b0;
assign RAM_DATA_O = (ram_address == 13'h1fff) ? ram_out_GPIO : ram_out_normal; //13'h1fff is for our GPIO
assign wb_data_o = (ram_address == 13'h1fff) ? ram_out_GPIO : ram_out_normal; //13'h1fff is for our GPIO
`endif
// [17:2] of 32-bit address input is connected to ram0,
// for the reason of 4 byte alignment of OR1200 processor.
// 8-bit char or 16-bit short int accesses are accomplished
// with the help of wb_sel_i (byteena) signal.
//Mapping address 65535 / 8191 for GPIO
simple_gpio simple_gpio(
.clk(clk_i),
.rst(rst_i),
.wea(ram_wren),
.addr(ram_address),
.din(ram_data),
.dout(ram_out_GPIO),
.GPIO_o(GPIO_o),
.GPIO_i({14'b1111_1111_1111_11, GPIO_i})
);
`ifdef RAM_8192
//xilinx ram
xilinx_ram_8192 u_ram0(
.clka(clk_i),
.rsta(rst_i),
.wea(ram_wren),
.addra(ram_address),
.dina(ram_data),
.douta(ram_out_normal)
);
`endif
`ifdef RAM_65536
//xilinx ram
xilinx_ram_65536 u_ram0(
.clka(clk_i),
.rsta(rst_i),
.wea(ram_wren),
.addra(ram_address),
.dina(ram_data),
.douta(ram_out_normal)
);
`endif
// get the rising edge of request signal
always @ (posedge clk_i)
begin
if(rst_i == 1)
request_delay <= 0;
else
request_delay <= request;
end
assign request_rising_edge = (request_delay ^ request) & request;
// generate a 1 cycle acknowledgement for each request rising edge
always @ (posedge clk_i)
begin
if (rst_i == 1)
ram_ack <= 0;
else if (request_rising_edge == 1)
ram_ack <= 1;
else
ram_ack <= 0;
end
// register wb_ack output, because onchip ram0 uses registered output
always @ (posedge clk_i)
begin
if (rst_i == 1)
wb_ack_o <= 0;
else
wb_ack_o <= ram_ack;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[424242]; int main() { long long n; cin >> n; int ans = 0; if (n % 3 == 0) { n /= 3; int kp = 0; for (int d = 1; d <= 50000; d++) if ((4 * n) % d == 0) p[kp++] = d; for (int a = 1; 8LL * a * a * a <= n; a++) for (int id = 0; id < kp; id++) { int b = p[id] - a; if (b < a) continue; if (2LL * b * (a + b) * (a + b) > n) continue; long long d = (long long)(a + b) * (a + b) * (a - b) * (a - b) + 4LL * (a + b) * n; long long dd = sqrt(1.0 * d); while (dd * dd < d) dd++; while (dd * dd > d) dd--; if (dd * dd == d) { long long c = -a - b + dd / (a + b); if (c < 2 * b || (c & 1)) continue; c >>= 1; if (a < b && b < c) ans += 6; else if (a == b && b == c) ans += 1; else ans += 3; } } } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, p; cin >> n >> m; if (n < m) p = n; else p = m; if (p % 2 == 0) cout << Malvika ; else cout << Akshat ; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A32O_BEHAVIORAL_PP_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 and0_out ;
wire B1 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_BEHAVIORAL_PP_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI4Lite Upizer
// Converts 32-bit AXI4Lite on Slave Interface to 64-bit AXI4Lite on Master Interface.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi4lite_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_8_axi4lite_upsizer #
(
parameter C_FAMILY = "none",
// FPGA Family.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range 3 - 64.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
// Global Signals
input wire aresetn,
input wire aclk,
// Slave Interface Write Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [3-1:0] s_axi_awprot,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [32-1:0] s_axi_wdata,
input wire [32/8-1:0] s_axi_wstrb,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [3-1:0] s_axi_arprot,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [32-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [3-1:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [64-1:0] m_axi_wdata,
output wire [64/8-1:0] m_axi_wstrb,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [3-1:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [64-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rvalid,
output wire m_axi_rready
);
reg s_axi_arready_i ;
reg m_axi_arvalid_i ;
reg m_axi_rready_i ;
reg s_axi_rvalid_i ;
reg ar_done ;
reg araddr2 ;
reg s_axi_awready_i ;
reg s_axi_bvalid_i ;
reg m_axi_awvalid_i ;
reg m_axi_wvalid_i ;
reg m_axi_bready_i ;
reg aw_done ;
reg w_done ;
generate
if (C_AXI_SUPPORTS_READ != 0) begin : gen_read
always @(posedge aclk) begin
if (~aresetn) begin
s_axi_arready_i <= 1'b0 ;
m_axi_arvalid_i <= 1'b0 ;
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1;
ar_done <= 1'b0 ;
araddr2 <= 1'b0 ;
end else begin
s_axi_arready_i <= 1'b0 ; // end single-cycle pulse
m_axi_rready_i <= 1'b0; // end single-cycle pulse
if (s_axi_rvalid_i) begin
if (s_axi_rready) begin
s_axi_rvalid_i <= 1'b0;
m_axi_rready_i <= 1'b1; // begin single-cycle pulse
ar_done <= 1'b0;
end
end else if (m_axi_rvalid & ar_done) begin
s_axi_rvalid_i <= 1'b1;
end else if (m_axi_arvalid_i) begin
if (m_axi_arready) begin
m_axi_arvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1 ; // begin single-cycle pulse
araddr2 <= s_axi_araddr[2];
ar_done <= 1'b1;
end
end else if (s_axi_arvalid & ~ar_done) begin
m_axi_arvalid_i <= 1'b1;
end
end
end
assign m_axi_arvalid = m_axi_arvalid_i ;
assign s_axi_arready = s_axi_arready_i ;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arprot = s_axi_arprot;
assign s_axi_rvalid = s_axi_rvalid_i ;
assign m_axi_rready = m_axi_rready_i ;
assign s_axi_rdata = araddr2 ? m_axi_rdata[63:32] : m_axi_rdata[31:0];
assign s_axi_rresp = m_axi_rresp;
end else begin : gen_noread
assign m_axi_arvalid = 1'b0 ;
assign s_axi_arready = 1'b0 ;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_arprot = 3'b0 ;
assign s_axi_rvalid = 1'b0 ;
assign m_axi_rready = 1'b0 ;
assign s_axi_rresp = 2'b0 ;
assign s_axi_rdata = 32'b0 ;
end
if (C_AXI_SUPPORTS_WRITE != 0) begin : gen_write
always @(posedge aclk) begin
if (~aresetn) begin
m_axi_awvalid_i <= 1'b0 ;
s_axi_awready_i <= 1'b0 ;
m_axi_wvalid_i <= 1'b0 ;
s_axi_bvalid_i <= 1'b0 ;
m_axi_bready_i <= 1'b0 ;
aw_done <= 1'b0 ;
w_done <= 1'b0 ;
end else begin
m_axi_bready_i <= 1'b0; // end single-cycle pulse
if (s_axi_bvalid_i) begin
if (s_axi_bready) begin
s_axi_bvalid_i <= 1'b0;
m_axi_bready_i <= 1'b1; // begin single-cycle pulse
aw_done <= 1'b0;
w_done <= 1'b0;
end
end else if (s_axi_awready_i) begin
s_axi_awready_i <= 1'b0; // end single-cycle pulse
s_axi_bvalid_i <= 1'b1;
end else if (aw_done & w_done) begin
if (m_axi_bvalid) begin
s_axi_awready_i <= 1'b1; // begin single-cycle pulse
end
end else begin
if (m_axi_awvalid_i) begin
if (m_axi_awready) begin
m_axi_awvalid_i <= 1'b0;
aw_done <= 1'b1;
end
end else if (s_axi_awvalid & ~aw_done) begin
m_axi_awvalid_i <= 1'b1;
end
if (m_axi_wvalid_i) begin
if (m_axi_wready) begin
m_axi_wvalid_i <= 1'b0;
w_done <= 1'b1;
end
end else if (s_axi_wvalid & (m_axi_awvalid_i | aw_done) & ~w_done) begin
m_axi_wvalid_i <= 1'b1;
end
end
end
end
assign m_axi_awvalid = m_axi_awvalid_i ;
assign s_axi_awready = s_axi_awready_i ;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_wvalid = m_axi_wvalid_i ;
assign s_axi_wready = s_axi_awready_i ;
assign m_axi_wdata = {s_axi_wdata,s_axi_wdata};
assign m_axi_wstrb = s_axi_awaddr[2] ? {s_axi_wstrb, 4'b0} : {4'b0, s_axi_wstrb};
assign s_axi_bvalid = s_axi_bvalid_i ;
assign m_axi_bready = m_axi_bready_i ;
assign s_axi_bresp = m_axi_bresp;
end else begin : gen_nowrite
assign m_axi_awvalid = 1'b0 ;
assign s_axi_awready = 1'b0 ;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}} ;
assign m_axi_awprot = 3'b0 ;
assign m_axi_wvalid = 1'b0 ;
assign s_axi_wready = 1'b0 ;
assign m_axi_wdata = 64'b0 ;
assign m_axi_wstrb = 8'b0 ;
assign s_axi_bvalid = 1'b0 ;
assign m_axi_bready = 1'b0 ;
assign s_axi_bresp = 2'b0 ;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_TB_V
`define SKY130_FD_SC_HS__TAPMET1_TB_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__tapmet1.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VPWR = 1'b0;
#60 VGND = 1'b1;
#80 VPWR = 1'b1;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 VGND = 1'b1;
#180 VPWR = 1'bx;
#200 VGND = 1'bx;
end
sky130_fd_sc_hs__tapmet1 dut (.VPWR(VPWR), .VGND(VGND));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_TB_V
|
`include "timescale.v"
module fb_slave_counters (MRxClk, Clk_100MHz, Reset, MRxDV, RxValid, MRxDEqDataSoC, MTxEn_TxSync2,
StateIdle, StatePreamble, StateNumb, StateSlaveID, StateDist, StateDelay, StateDelayMeas,
StateDelayDist, StateData, StateSlaveData, StateSlaveCrc, StateFrmCrc,
TotalRecvNibCnt, TotalSentNibCnt, LogicDelay, SlaveCrcEnd, FrmCrcStateEnd, TxRamAddr, RxRamAddr
);
input MRxClk; // Tx clock
input Clk_100MHz;
input Reset; // Reset
input MRxDV;
input RxValid;
input MRxDEqDataSoC;
input MTxEn_TxSync2;
input StateIdle; // Idle state
input StatePreamble; // Preamble state
input StateNumb;
input [1:0] StateSlaveID;
input StateDist;
input StateDelay;
input StateDelayMeas;
input StateDelayDist;
input StateData; // Data state
input [1:0] StateSlaveData; // StateSlaveData state
input StateSlaveCrc; // slave CRC state
input StateFrmCrc;
output [15:0] TotalSentNibCnt;
output [15:0] TotalRecvNibCnt; // total Nibble counter
output [7:0] LogicDelay; // Nibble counter
output [7: 0] TxRamAddr;
output [7: 0] RxRamAddr;
output SlaveCrcEnd;
output FrmCrcStateEnd;
reg [15:0] TotalSentNibCnt;
reg [15:0] TotalRecvNibCnt;
reg [7:0] LogicDelay;
reg [7:0] LogicDelayCnt;
reg [3: 0] CrcNibCnt;
reg [3: 0] PreambleNibCnt;
reg [3: 0] FrmCrcNibCnt;
reg [7: 0] TxRamAddr;
reg [7: 0] RxRamAddr;
reg ResetLogicDelayCnt_100MHzSync1 ;
reg ResetLogicDelayCnt_100MHzSync2 ;
reg IncrementLogicDelayCnt_100MHzSync1 ;
reg IncrementLogicDelayCnt_100MHzSync2 ;
reg MTxEn_TxSync2_100MHzSync1 ;
reg MTxEn_TxSync2_100MHzSync2 ;
reg MTxEn_TxSync2_100MHzSync3 ;
wire ResetLogicDelayCnt;
wire IncrementLogicDelayCnt;
assign IncrementLogicDelayCnt = MRxDV & ~MTxEn_TxSync2;
assign ResetLogicDelayCnt = StateIdle & ~MRxDV ;
////////////////////////////// 100 MHz clock domain /////////////////////
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
begin
ResetLogicDelayCnt_100MHzSync1 <= 1'b0;
ResetLogicDelayCnt_100MHzSync2 <= 1'b0;
IncrementLogicDelayCnt_100MHzSync1 <= 1'b0;
IncrementLogicDelayCnt_100MHzSync2 <= 1'b0;
MTxEn_TxSync2_100MHzSync1 <= 1'b0;
MTxEn_TxSync2_100MHzSync2 <= 1'b0;
MTxEn_TxSync2_100MHzSync3 <= 1'b0;
end
else
begin
ResetLogicDelayCnt_100MHzSync1 <= ResetLogicDelayCnt;
ResetLogicDelayCnt_100MHzSync2 <= ResetLogicDelayCnt_100MHzSync1;
IncrementLogicDelayCnt_100MHzSync1 <= IncrementLogicDelayCnt;
IncrementLogicDelayCnt_100MHzSync2 <= IncrementLogicDelayCnt_100MHzSync1;
MTxEn_TxSync2_100MHzSync1 <= MTxEn_TxSync2;
MTxEn_TxSync2_100MHzSync2 <= MTxEn_TxSync2_100MHzSync1;
MTxEn_TxSync2_100MHzSync3 <= MTxEn_TxSync2_100MHzSync2;
end
end
// register logic delay
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
LogicDelay <= 8'b0;
else
if ((MTxEn_TxSync2_100MHzSync3==0) & (MTxEn_TxSync2_100MHzSync2 ==1))
LogicDelay <= LogicDelayCnt;
end
// delay counter count from receiving to starting sending signal
always @ (posedge Clk_100MHz or posedge Reset)
begin
if(Reset)
LogicDelayCnt <= 8'd0;
else
begin
if(ResetLogicDelayCnt_100MHzSync2)
LogicDelayCnt <= 8'd0;
else
if(IncrementLogicDelayCnt_100MHzSync2)
LogicDelayCnt <= LogicDelayCnt + 8'd1;
end
end
////////////////////////////// 100 MHz clock domain end/////////////////////
// Total Nibble Counter received for the whole frame incl.( Preamble, SoC, SlaveDate, SlaveCRC, NO FrameCRC)
wire ResetTotalRecvNibCnt;
wire IncrementTotalRecvNibCnt;
assign IncrementTotalRecvNibCnt = MRxDV;
assign ResetTotalRecvNibCnt = StateIdle;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalRecvNibCnt <= 16'h0;
else
begin
if(ResetTotalRecvNibCnt)
TotalRecvNibCnt <= 16'h0;
else
if(IncrementTotalRecvNibCnt)
TotalRecvNibCnt <= TotalRecvNibCnt + 16'd1;
end
end
// Total Nibble Counter already sent( Preamble,SoC, SlaveDate, SlaveCRC, NO FrameCRC)
wire ResetTotalSentNibCnt;
wire IncrementTotalSentNibCnt;
assign IncrementTotalSentNibCnt = StateNumb | (|StateSlaveID) | StateDist | StateDelay | StateDelayMeas | StateDelayDist |StateData | (|StateSlaveData) | StateSlaveCrc ;
assign ResetTotalSentNibCnt = StateIdle;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TotalSentNibCnt <= 16'h0;
else
begin
if(ResetTotalSentNibCnt)
TotalSentNibCnt <= 16'h0;
else
if(IncrementTotalSentNibCnt)
TotalSentNibCnt <= TotalSentNibCnt + 16'd1;
end
end
wire IncrementCrcNibCnt;
wire ResetCrcNibCnt;
assign IncrementCrcNibCnt = StateSlaveCrc ;
assign ResetCrcNibCnt = |StateSlaveData ;
assign SlaveCrcEnd = CrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
CrcNibCnt <= 4'b0;
else
begin
if(ResetCrcNibCnt)
CrcNibCnt <= 4'b0;
else
if(IncrementCrcNibCnt)
CrcNibCnt <= CrcNibCnt + 4'b0001;
end
end
wire IncrementFrmCrcNibCnt;
wire ResetFrmCrcNibCnt;
assign IncrementFrmCrcNibCnt = StateFrmCrc ;
assign ResetFrmCrcNibCnt = StateIdle | StatePreamble | StateData | (|StateSlaveData) | StateSlaveCrc;
assign FrmCrcStateEnd = FrmCrcNibCnt[0] ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
FrmCrcNibCnt <= 4'b0;
else
begin
if(ResetFrmCrcNibCnt)
FrmCrcNibCnt <= 4'b0;
else
if(IncrementFrmCrcNibCnt)
FrmCrcNibCnt <= FrmCrcNibCnt + 4'b0001;
end
end
wire IncrementTxRamAddr;
wire ResetTxRamAddr;
assign ResetTxRamAddr = StateIdle | StatePreamble | StateData;
assign IncrementTxRamAddr = StateSlaveData[0];
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
TxRamAddr <= 8'b0;
else
begin
if(ResetTxRamAddr)
TxRamAddr <= 8'b0;
else
if(IncrementTxRamAddr)
TxRamAddr <= TxRamAddr + 8'b0001;
end
end
wire ResetRxRamAddr;
wire IncrementRxRamAddr;
assign ResetRxRamAddr = StateIdle | StatePreamble;
assign IncrementRxRamAddr = RxValid ;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxRamAddr[7:0] <= 8'd0;
else
begin
if(ResetRxRamAddr)
RxRamAddr[7:0] <= 8'd0;
else
if(IncrementRxRamAddr)
RxRamAddr[7:0] <= RxRamAddr[7:0] + 8'd1;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: cross_domain_signal.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Send a signal from clock domain A into clock domain B
// and get the signal back into clock domain A. Domain A can know roughly when
// the signal is received domain B.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module cross_domain_signal (
input CLK_A, // Clock for domain A
input CLK_A_SEND, // Signal from domain A to domain B
output CLK_A_RECV, // Signal from domain B received in domain A
input CLK_B, // Clock for domain B
output CLK_B_RECV, // Signal from domain A received in domain B
input CLK_B_SEND // Signal from domain B to domain A
);
// Sync level signals across domains.
syncff sigAtoB (.CLK(CLK_B), .IN_ASYNC(CLK_A_SEND), .OUT_SYNC(CLK_B_RECV));
syncff sigBtoA (.CLK(CLK_A), .IN_ASYNC(CLK_B_SEND), .OUT_SYNC(CLK_A_RECV));
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; static const long long maxn = 2005; long long M[maxn][maxn]; long long MyM[maxn][maxn]; vector<vector<long long>*> graph; long long dsu[maxn]; bool PreCheck() { for (long long i = 0; i < n; i++) { if (M[i][i] != 0) return false; } for (long long i = 0; i < n; i++) for (long long j = 0; j < n; j++) { if (M[i][j] != M[j][i]) return false; } return true; } long long edge_count = 0; struct edge { long long u; long long v; long long d; bool operator<(const edge& rhs) const { return d < rhs.d; } }; long long dsu_root(long long i) { while (dsu[i] != i) { dsu[i] = dsu[dsu[i]]; i = dsu[i]; } return i; } bool dsu_connected(long long i, long long j) { return dsu_root(i) == dsu_root(j); } void dsu_join(long long i, long long j) { long long r = rand() % 2; if (r) dsu[dsu_root(i)] = j; else dsu[dsu_root(j)] = i; } void init() { for (long long i = 0; i < n; i++) { dsu[i] = i; vector<long long>* v = new vector<long long>(); graph.push_back(v); } } bool dfs_visited[maxn]; void dfs(long long i, long long root, long long curr) { if (dfs_visited[i]) return; dfs_visited[i] = true; for (auto it : *graph[i]) { if (dfs_visited[it]) continue; else { long long d = curr + M[i][it]; MyM[root][it] = d; MyM[it][root] = d; dfs(it, root, d); } } } bool FinalCheck() { for (long long i = 1; i < n; i++) { if (!dsu_connected(i, 0)) return false; } for (long long i = 0; i < n; i++) for (long long j = 0; j < i; j++) { if (M[i][j] != MyM[i][j]) return false; } return true; } int main() { ios_base::sync_with_stdio(0); cin >> n; init(); for (long long i = 0; i < n; i++) for (long long j = 0; j < n; j++) { cin >> M[i][j]; MyM[i][j] = 0; } if (!PreCheck()) { cout << NO << endl; return 0; } vector<edge> edges; for (long long i = 0; i < n; i++) for (long long j = 0; j < i; j++) { edge curr; curr.u = i; curr.v = j; curr.d = M[i][j]; if (curr.d > 0) edges.push_back(curr); } sort(edges.begin(), edges.end()); for (auto it : edges) { if (!dsu_connected(it.u, it.v)) { edge_count++; graph[it.u]->push_back(it.v); graph[it.v]->push_back(it.u); dsu_join(it.u, it.v); } } if (edge_count != n - 1) { cout << NO << endl; return 0; } for (long long i = 0; i < n; i++) { memset(dfs_visited, 0, sizeof(dfs_visited)); dfs(i, i, 0); } if (FinalCheck()) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; struct node { int x, id; } a[N], ans[N]; int anss; bool cmp(node x, node y) { if (x.x != y.x) return x.x > y.x; return x.id < y.id; } void solve() { int k = a[2].x / a[3].x; while (k) { if (k & 1) { a[2].x -= a[3].x; a[3].x <<= 1; ans[++anss].x = a[3].id; ans[anss].id = a[2].id; } else { a[1].x -= a[3].x; a[3].x <<= 1; ans[++anss].x = a[3].id; ans[anss].id = a[1].id; } k >>= 1; } } int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) a[i].id = i, scanf( %d , &a[i].x); sort(a + 1, a + n + 1, cmp); if (!a[2].x) { puts( -1 ); return 0; } while (a[3].x) { solve(); sort(a + 1, a + n + 1, cmp); } printf( %d n , anss); for (int i = 1; i <= anss; ++i) printf( %d %d n , ans[i].x, ans[i].id); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool isgood(const vector<vector<char> > &graph, const vector<char> &choice) { int n = (int)graph.size() / 2; assert((int)graph[0].size() == 2 * n); assert((int)choice.size() == n); for (int i = 0; i < n; i++) { bool ok = false; int lbound = 2 * i; int rbound = 2 * i + 1; if (choice[i] != -1) lbound = rbound = 2 * i + choice[i]; for (int who = lbound; who <= rbound; who++) { bool cur = true; for (int j = 0; j < n; j++) { if (choice[j] != -1 && graph[who][2 * j + 1 - choice[j]]) cur = false; if (graph[who][2 * j] && graph[who][2 * j + 1]) cur = false; } ok |= cur; } if (!ok) return false; } return true; } void solve(string alph) { int n, m; cin >> n >> m; vector<vector<char> > graph(2 * n, vector<char>(2 * n)); int pos1, pos2; char t1, t2; for (int i = 0; i < m; i++) { scanf( %d %c %d %c , &pos1, &t1, &pos2, &t2); int x1 = 2 * (pos1 - 1) + (t1 == V ? 0 : 1); int x2 = 2 * (pos2 - 1) + (t2 == V ? 0 : 1); graph[x1][x2] = 1; graph[x2 ^ 1][x1 ^ 1] = 1; } string word; cin >> word; assert((int)word.size() == n); for (int i = 0; i < 2 * n; i++) graph[i][i] = 1; for (int k = 0; k < 2 * n; k++) for (int i = 0; i < 2 * n; i++) for (int j = 0; j < 2 * n; j++) graph[i][j] |= (graph[i][k] & graph[k][j]); for (int i = 0; i < 2 * n; i++) if (graph[i][i ^ 1] && graph[i ^ 1][i]) { puts( -1 ); return; } vector<char> choice(n, -1); for (int i = 0; i < n; i++) choice[i] = (alph[word[i] - a ] == V ? 0 : 1); vector<int> next_vowel(alph.size() + 1, -1), next_cons(alph.size() + 1, -1); for (int i = 0; i < (int)alph.size(); i++) { for (int j = i; j < (int)alph.size(); j++) { if (alph[j] == V && next_vowel[i] == -1) next_vowel[i] = j; if (alph[j] == C && next_cons[i] == -1) next_cons[i] = j; } } if (isgood(graph, choice)) { puts(word.c_str()); return; } int lcp; for (lcp = n - 1; lcp > 0; lcp--) { int num = word[lcp] - a + 1; if (next_vowel[num] != -1) { choice[lcp] = 0; if (isgood(graph, choice)) break; } if (next_cons[num] != -1) { choice[lcp] = 1; if (isgood(graph, choice)) break; } choice[lcp] = -1; } choice[lcp] = -1; string ans = word.substr(0, lcp); for (int i = lcp; i < n; i++) { char start = (i == lcp ? word[i] + 1 : a ); bool was_vowel = false; bool was_cons = false; bool ok = false; for (char ch = start; ch < a + (int)alph.size(); ch++) { if (!was_vowel && alph[ch - a ] == V ) { was_vowel = true; choice[i] = 0; ok |= isgood(graph, choice); if (ok) { ans += ch; break; } } if (!was_cons && alph[ch - a ] == C ) { was_cons = true; choice[i] = 1; ok |= isgood(graph, choice); if (ok) { ans += ch; break; } } } if (!ok) { puts( -1 ); return; } } puts(ans.c_str()); } int main() { string n; while (cin >> n) solve(n); }
|
#include <bits/stdc++.h> using namespace std; const double pi = 2 * acos(0.0); long long int pow1(long long int n, long long int k) { long long int ret = 1; while (k) { if (k % 2 == 1) ret = (ret * n) % 1000000007; n = (n * n) % 1000000007; k /= 2; } return ret; } string s, s1; int n; string q[100000]; long long int A[10], len[10]; int main() { cin >> s; cin >> n; for (int i = 0; i < n; i++) cin >> q[i]; for (int i = 0; i < 10; i++) { A[i] = i; len[i] = 1; } for (int i = n - 1; i >= 0; i--) { int idx = q[i][0] - 0 ; long long int val = 0, val1 = 0; for (int j = 3; j < q[i].size(); j++) { int d = q[i][j] - 0 ; val = (val * pow1(10, len[d])) % 1000000007; val += A[d]; val %= 1000000007; val1 += len[d]; val1 %= (1000000007 - 1); } A[idx] = val; len[idx] = val1; } long long int ans = 0; for (int i = 0; i < s.size(); i++) { int d = s[i] - 0 ; ans = (ans * pow1(10, len[d]) + A[d]) % 1000000007; } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e6 + 5; const int inf = 0x3f3f3f3f; int main() { int n; scanf( %d , &n); char a; getchar(); int ans = 0; for (int i = 1; i <= n; i++) { scanf( %c , &a); if (a == - ) ans--; else ans++; ans = max(0, ans); } printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9; const int SIZE = 1e6 + 5; const long long INF = 1LL << 55; const double eps = 1e-10; int d[1000009]; int main() { int(n); scanf( %d , &n); if (n % 2) { int h = n / 2; for (int i = 0; i < (h); ++i) { d[i] = d[n - 2 - i] = 2 * (i + 1); } for (int i = 0; i < (h + 1); ++i) { d[i + n - 1] = d[2 * n - 2 - i] = 2 * i + 1; } d[2 * n - 1] = n; } else { int h = n / 2; for (int i = 0; i < (h); ++i) { d[i] = d[n - 1 - i] = 2 * i + 1; } for (int i = 0; i < (h); ++i) { d[i + n] = d[2 * n - 2 - i] = (2 * (i + 1)); } d[2 * n - 1] = n; } for (int i = 0; i < (2 * n); ++i) printf( %d , d[i]); }
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#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30) - 1; const int maxn = 100010; int IN() { int c, f, x; while (!isdigit(c = getchar()) && c != - ) ; c == - ? (f = 1, x = 0) : (f = 0, x = c - 0 ); while (isdigit(c = getchar())) x = (x << 1) + (x << 3) + c - 0 ; return !f ? x : -x; } int n, T; char s[maxn]; bool vis[maxn], c[maxn]; bool check() { int ans = 0; for (int i = 0; i < 26; i++) if (vis[i]) ans++; return ans == 1; } int main() { scanf( %d , &n); int ans = 0; fill(vis, vis + maxn, 1); fill(c, c + maxn, 1); for (int i = 1; i <= n; i++) { char op[10]; scanf( %s%s , op, s); char tp = op[0]; int len = strlen(s); if (tp == . ) { for (int i = 0; i < len; i++) vis[s[i] - a ] = 0; } else if (tp == ! ) { if (check()) ans++; int t[27]; memset(t, 0, sizeof(t)); for (int i = 0; i < len; i++) t[s[i] - a ]++; for (int i = 0; i < 26; i++) if (!t[i]) vis[i] = 0; } else if (tp == ? ) { if (i != n && check()) ans++; vis[s[0] - a ] = 0; } } printf( %d n , ans); return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: sa1_mult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sa1_mult (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Boundary Scan Logic Control Circuit for VIRTEX7
// /___/ /\ Filename : BSCANE2.v
// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010
// \___\/\___\
//
// Revision:
// 02/08/10 - Initial version.
// 06/10/11 - CR 613789.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BSCANE2 (
CAPTURE,
DRCK,
RESET,
RUNTEST,
SEL,
SHIFT,
TCK,
TDI,
TMS,
UPDATE,
TDO
);
parameter DISABLE_JTAG = "FALSE";
parameter integer JTAG_CHAIN = 1;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CAPTURE;
output DRCK;
output RESET;
output RUNTEST;
output SEL;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO;
reg SEL_zd;
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
//--####################################################################
//--##### Initialization ###
//--####################################################################
initial begin
//-------- JTAG_CHAIN
if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin
$display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN);
$finish;
end
end
//--####################################################################
//--##### Jtag_select ###
//--####################################################################
always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin
if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL;
else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL;
else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL;
else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL;
end
//--####################################################################
//--####################################################################
//--##### USER_TDO ###
//--####################################################################
always@(TDO) begin
if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO;
else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO;
else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO;
else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO;
end
//--####################################################################
//--##### Output ###
//--####################################################################
assign CAPTURE = glbl.JTAG_CAPTURE_GLBL;
assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL)
||
(SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL)
||
(SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL));
assign RESET = glbl.JTAG_RESET_GLBL;
assign RUNTEST = glbl.JTAG_RUNTEST_GLBL;
assign SEL = SEL_zd;
assign SHIFT = glbl.JTAG_SHIFT_GLBL;
assign TDI = glbl.JTAG_TDI_GLBL;
assign TCK = glbl.JTAG_TCK_GLBL;
assign TMS = glbl.JTAG_TMS_GLBL;
assign UPDATE = glbl.JTAG_UPDATE_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 06:23:47 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_rst_ps7_0_50M_0 -prefix
// design_1_rst_ps7_0_50M_0_ design_1_rst_ps7_0_50M_0_stub.v
// Design : design_1_rst_ps7_0_50M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module design_1_rst_ps7_0_50M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; vector<pair<long long, long long> > v; for (int i = 0; i < m; i++) { long long a, b; cin >> b >> a; v.push_back(make_pair(a, b)); } sort(v.rbegin(), v.rend()); long long total = 0, i = 0, count = 0; while (i < m && (count + v[i].second) <= n) { total += v[i].first * v[i].second; count += v[i].second; i++; } if (i != m) total += v[i].first * (n - count); cout << total << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { double fact[51], all = 0.0; fact[0] = 1; for (int i = 1; i < 51; i++) fact[i] = fact[i - 1] * i; int N, A[50], P; double dp[51][51]; cin >> N; for (int i = 0; i < N; i++) cin >> A[i]; cin >> P; int sum = 0; for (int i = 0; i < N; i++) sum += A[i]; if (sum <= P) { cout << N << endl; return (0); } for (int i = 0; i < N; i++) { memset(dp, 0, sizeof(dp)); dp[0][0] = 1; for (int j = 0; j < N; j++) { if (i == j) continue; for (int k = N - 1; k >= 0; k--) { for (int l = P; l >= A[j]; l--) { dp[k + 1][l] += dp[k][l - A[j]]; } } } for (int j = 0; j < N; j++) { for (int k = max(0, P - A[i] + 1); k <= P; k++) { all += fact[j] * fact[N - 1 - j] * dp[j][k] * j; } } } cout << fixed << setprecision(10) << all / fact[N] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int size1 = 8e5; const long long INF = 1e18; const int INF1 = 1e9; const double eps = 1e-5; const long long mod = 1e9 + 7; vector<vector<int> > graph(size1); vector<vector<long long> > graph1(size1); static int maxder[size1], minder[size1], d[size1], v[size1], u[size1], w[size1], tin[size1], tout[size1]; static bool used[size1]; static long long ras[size1]; static long long tree[size1], tree1[size1], tree2[size1], tree3[size1], w1[size1]; int num = 1; int time1 = 0; void dfs(int v) { used[v] = true; minder[v] = INF1; for (int i = 0; i < graph[v].size(); i++) { if (!used[graph[v][i]]) { dfs(graph[v][i]); minder[v] = min(minder[v], minder[graph[v][i]]); } } maxder[v] = num; num++; minder[v] = min(minder[v], maxder[v]); } void dfs1(int v, long long ras1, int depth) { time1++; used[v] = true; ras[maxder[v]] = ras1; d[v] = depth; tin[v] = time1; for (int i = 0; i < graph[v].size(); i++) { if (!used[graph[v][i]]) { dfs1(graph[v][i], ras1 + graph1[v][i], depth + 1); } } time1++; tout[v] = time1; } void build_tree(int tl, int tr, int pos) { if (tl == tr) { tree[pos] = ras[tl]; } else { int tm = (tl + tr) / 2; build_tree(tl, tm, pos * 2); build_tree(tm + 1, tr, pos * 2 + 1); tree[pos] = tree[pos * 2] + tree[pos * 2 + 1]; } } void prib(int tl, int tr, int pos, int l, int r, long long x) { if (l <= tl && tr <= r) { tree1[pos] += x; } else { int tm = (tl + tr) / 2; if (max(tl, l) <= min(tm, r)) { prib(tl, tm, pos * 2, l, r, x); } if (max(tm + 1, l) <= min(tr, r)) { prib(tm + 1, tr, pos * 2 + 1, l, r, x); } tree[pos] = tree[pos * 2] + tree[pos * 2 + 1] + tree1[pos * 2] * (tm - tl + 1) + tree1[pos * 2 + 1] * (tr - tm); } } long long zn(int tl, int tr, int pos, int pos1, long long add) { if (tl == pos1 && tr == pos1) { return add + tree[pos] + tree1[pos]; } else { int tm = (tl + tr) / 2; if (tl <= pos1 && pos1 <= tm) { return zn(tl, tm, pos * 2, pos1, add + tree1[pos]); } else { return zn(tm + 1, tr, pos * 2 + 1, pos1, add + tree1[pos]); } } } void build_tree1(int tl, int tr, int pos) { if (tl == tr) { tree2[pos] = ras[tl] + w1[tl]; } else { int tm = (tl + tr) / 2; build_tree1(tl, tm, pos * 2); build_tree1(tm + 1, tr, pos * 2 + 1); tree2[pos] = min(tree2[pos * 2], tree2[pos * 2 + 1]); } } void upd2(int tl, int tr, int pos, int l, int r, long long x) { if (l <= tl && tr <= r) { tree3[pos] += x; } else { int tm = (tl + tr) / 2; if (max(tl, l) <= min(tm, r)) { upd2(tl, tm, pos * 2, l, r, x); } if (max(tm + 1, l) <= min(tr, r)) { upd2(tm + 1, tr, pos * 2 + 1, l, r, x); } tree2[pos] = min(tree2[pos * 2] + tree3[pos * 2], tree2[pos * 2 + 1] + tree3[pos * 2 + 1]); } } long long zn1(int tl, int tr, int pos, int l, int r, long long add) { if (l <= tl && tr <= r) { return add + tree3[pos] + tree2[pos]; } else { int tm = (tl + tr) / 2; long long ans = INF; if (max(l, tl) <= min(r, tm)) { ans = min(ans, zn1(tl, tm, pos * 2, l, r, add + tree3[pos])); } if (max(tm + 1, l) <= min(tr, r)) { ans = min(ans, zn1(tm + 1, tr, pos * 2 + 1, l, r, add + tree3[pos])); } return ans; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, q, i; cin >> n >> q; for (i = 1; i <= n - 1; i++) { cin >> v[i] >> u[i] >> w[i]; graph[v[i]].push_back(u[i]); graph[u[i]].push_back(v[i]); graph1[v[i]].push_back(w[i]); graph1[u[i]].push_back(w[i]); } dfs(1); for (i = n; i <= 2 * n - 2; i++) { cin >> v[i] >> u[i] >> w[i]; w1[maxder[v[i]]] = w[i]; } memset(used, false, sizeof used); dfs1(1, 0, 0); build_tree(1, n, 1); build_tree1(1, n, 1); for (i = 1; i <= q; i++) { int t, a, b; cin >> t >> a >> b; if (t == 1) { if (a >= n) { upd2(1, n, 1, maxder[v[a]], maxder[v[a]], b - w1[maxder[v[a]]]); w1[maxder[v[a]]] = b; } else { int v1 = 0; if (d[v[a]] > d[u[a]]) { v1 = v[a]; } else { v1 = u[a]; } prib(1, n, 1, minder[v1], maxder[v1], b - w[a]); upd2(1, n, 1, minder[v1], maxder[v1], b - w[a]); w[a] = b; } } else { long long res = INF; if (max(tin[a], tin[b]) <= min(tout[a], tout[b]) && d[a] <= d[b]) { res = min(res, zn(1, n, 1, maxder[b], 0) - zn(1, n, 1, maxder[a], 0)); } res = min(res, zn1(1, n, 1, minder[a], maxder[a], 0) - zn(1, n, 1, maxder[a], 0) + zn(1, n, 1, maxder[b], 0)); cout << res << endl; } } return 0; }
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: prnf5ccc.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module prnf5ccc (
address,
clock,
q);
input [15:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "prn5.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 50000,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "prn5.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "50000"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "prn5.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "50000"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prnf5ccc_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// This qa_wrapper takes the data and outputs alternately
// bit position and bit contents.
// If data arrives too frequently then ERRORCODE is output.
module bits
#(
parameter WIDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
output reg [WIDTH-1:0] out_data,
output reg out_nd,
output reg error
);
reg ready;
reg [`LOG_WIDTH-1:0] bit_pos;
reg pos_not_value;
reg [WIDTH-1:0] stored_data;
always @ (posedge clk)
if (reset)
begin
ready <= 1'b1;
error <= 1'b0;
out_nd <= 1'b0;
end
else if (error)
begin
out_nd <= 1'b1;
out_data <= `ERRORCODE;
end
else
begin
if (in_nd)
begin
if (!ready)
error <= 1'b1;
stored_data <= in_data;
ready <= 1'b0;
bit_pos <= WIDTH-1;
out_nd <= 1;
out_data <= WIDTH-1;
pos_not_value <= 0;
end
else if (!ready)
begin
out_nd <= 1'b1;
pos_not_value <= ~pos_not_value;
if (pos_not_value)
begin
out_data <= bit_pos;
end
else
begin
out_data <= stored_data[bit_pos];
if (!(|bit_pos))
ready <= 1'b1;
else
bit_pos <= bit_pos - 1;
end
end
else
out_nd <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_1_V
`define SKY130_FD_SC_HS__O2BB2AI_1_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o2bb2ai_1 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_1_V
|
#include <bits/stdc++.h> using namespace std; vector<int> e[200000 + 5]; int main() { int T, n; int m, p; scanf( %d , &T); for (int t = 1; t <= T; ++t) { scanf( %d , &n); for (int i = 0; i <= n; ++i) e[i].clear(); for (int i = 1; i <= n; ++i) { scanf( %d%d , &m, &p); e[m].push_back(p); } priority_queue<int, vector<int>, greater<int> > que; long long ans = 0; for (int i = n; i >= 0; --i) { int len = e[i].size(); for (int j = 0; j < len; ++j) que.push(e[i][j]); while (que.size() > n - i) { ans += que.top(); que.pop(); } } printf( %lld n , ans); } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/system_clock_splitter_1_0_stub.v
// Design : system_clock_splitter_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "clock_splitter,Vivado 2016.4" *)
module system_clock_splitter_1_0(clk_in, latch_edge, clk_out)
/* synthesis syn_black_box black_box_pad_pin="clk_in,latch_edge,clk_out" */;
input clk_in;
input latch_edge;
output clk_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/18/2016 01:33:37 PM
// Design Name:
// Module Name: fslcd
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fslcd #
(
/// single component data width
parameter integer C_IN_COMP_WIDTH = 8,
parameter integer C_OUT_COMP_WIDTH = 6
) (
input vid_io_in_clk,
input vid_active_video,
input [C_IN_COMP_WIDTH*3-1:0] vid_data,
input vid_hsync,
input vid_vsync,
output [C_OUT_COMP_WIDTH-1:0] r,
output [C_OUT_COMP_WIDTH-1:0] g,
output [C_OUT_COMP_WIDTH-1:0] b,
output hsync_out,
output vsync_out,
output active_data,
output out_clk
);
function integer com_msb (input integer com_idx);
begin
com_msb = C_IN_COMP_WIDTH * (com_idx + 1) - 1;
end
endfunction
function integer com_lsb_shrink (input integer com_idx);
begin
com_lsb_shrink = C_IN_COMP_WIDTH * (com_idx + 1) - C_OUT_COMP_WIDTH;
end
endfunction
function integer com_lsb_extent (input integer com_idx);
begin
com_lsb_extent = C_IN_COMP_WIDTH * com_idx;
end
endfunction
localparam integer C_EXTENT = C_OUT_COMP_WIDTH - C_IN_COMP_WIDTH;
assign active_data = vid_active_video;
if (C_IN_COMP_WIDTH >= C_OUT_COMP_WIDTH) begin
assign r = vid_data[com_msb(2):com_lsb_shrink(2)];
assign g = vid_data[com_msb(1):com_lsb_shrink(1)];
assign b = vid_data[com_msb(0):com_lsb_shrink(0)];
end
else begin
assign r = { vid_data[com_msb(2):com_lsb_extent(2)], {C_EXTENT{1'b1}} };
assign g = { vid_data[com_msb(1):com_lsb_extent(1)], {C_EXTENT{1'b1}} };
assign b = { vid_data[com_msb(0):com_lsb_extent(0)], {C_EXTENT{1'b1}} };
end
assign hsync_out = vid_hsync;
assign vsync_out = vid_vsync;
assign out_clk = vid_io_in_clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; char b, c; int n, m; int l, r; cin >> n >> m; cin >> s; for (int j = 1; j <= m; j++) { cin >> l >> r >> b >> c; for (int i = l - 1; i < r; i++) { if (s[i] == b) { s[i] = c; } } } for (int i = 0; i < n; i++) cout << s[i]; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_BEHAVIORAL_V
|
package test_pkg;
virtual class uvm_void;
endclass : uvm_void
class uvm_object extends uvm_void;
function new (string name = "uvm_object");
$display("uvm_object::new(%s)", name); // XXXX
m_name = name;
endfunction : new
virtual function void print ();
$display ("uvm_object::Print: m_name=%s", m_name);
endfunction : print
string m_name;
endclass : uvm_object
class uvm_report_object extends uvm_object;
function new (string name = "uvm_report_object");
// super.new must be the first statement in a constructor.
// If it is not, generate an error.
$display("uvm_report_object::new");
super.new (name);
$display("uvm_report_object::new");
endfunction : new
endclass : uvm_report_object
endpackage : test_pkg
module m;
import test_pkg::*;
uvm_object u0;
uvm_report_object u1;
initial begin : test
#100;
$display ("Hello World");
u0 = new ();
u0.print();
u1 = new ();
u1.print();
end : test
endmodule : m
|
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