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#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; int z = n / 2; if (x >= z && x <= z + 1 && y >= z && y <= z + 1) cout << NO ; else cout << YES ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n; cin >> k; if (n < k) { cout << -1; return 0; } if (k == 1) { if (n == 1) cout << a ; else cout << -1; return 0; } if (k == 2) { for (int i = 0; i < n >> 1; i++) cout << ab ; if (n & 1) cout << a ; return 0; } else { string temp = cdefghijklmnopqrstuvwxyz ; for (int i = 0; i < (n - k + 2) >> 1; i++) cout << ab ; if ((n - k + 2) & 1) cout << a ; for (int j = 0; j < (k - 2); j++) cout << temp[j]; } cout << endl; return 0; }
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/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
@brief HiL test case for GP_INV, GP_LUTx
OUTPUTS:
Bitwise NAND of inputs (1 to 4 bits wide)
*/
module Luts(din, dout_instantiated, dout_inferred);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P5 P4 P3 P2" *)
input wire[3:0] din;
(* LOC = "P9 P8 P7 P6" *)
output wire[3:0] dout_instantiated;
(* LOC = "P15 P14 P13 P12" *)
output wire[3:0] dout_inferred;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// LUTs created from direct instantiation
GP_INV inv_inst (
.IN(din[0]), .OUT(dout_instantiated[0]));
GP_2LUT #(.INIT(4'h7)) lut2_inst (
.IN0(din[0]), .IN1(din[1]), .OUT(dout_instantiated[1]));
GP_3LUT #(.INIT(8'h7F)) lut3_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .OUT(dout_instantiated[2]));
GP_4LUT #(.INIT(16'h7FFF)) lut4_inst (
.IN0(din[0]), .IN1(din[1]), .IN2(din[2]), .IN3(din[3]), .OUT(dout_instantiated[3]));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// LUTs created from inference
assign dout_inferred[0] = ~din[0];
assign dout_inferred[1] = ~(din[0] & din[1]);
assign dout_inferred[2] = ~(din[0] & din[1] & din[2]);
assign dout_inferred[3] = ~(din[0] & din[1] & din[2] & din[3]);
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 110; int a[N], c[N][N]; int main() { int n, k; scanf( %d %d , &n, &k); for (int i = 0; i < n; ++i) { scanf( %d , a + i); } int mn = a[0], mx = a[0]; for (int i = 0; i < n; ++i) { if (a[i] < mn) mn = a[i]; if (a[i] > mx) mx = a[i]; } int d = mx - mn; if (d > k) { puts( NO ); return 0; } puts( YES ); for (int i = 0; i < n; ++i) { for (int j = 0; j <= mn; ++j) { c[i][j] = 1; } int t = 2; for (int j = mn + 1; j < a[i]; ++j) { c[i][j] = t; ++t; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < a[i]; ++j) { if (j > 0) putchar( ); printf( %d , c[i][j]); } putchar( n ); } return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:51:49 01/30/2016
// Design Name:
// Module Name: alu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu #(parameter B = 32)
(
input wire signed [B-1:0] op1,
input wire signed [B-1:0] op2,
input wire [3:0] alu_control,
output wire [B-1:0] result,
output wire zero
);
assign result = (alu_control == 4'b0000) ? op1 + op2 : //ADD
(alu_control == 4'b0001) ? op1 - op2 : //SUB
(alu_control == 4'b0010) ? op1 & op2 : //AND
(alu_control == 4'b0011) ? op1 | op2 : //OR
(alu_control == 4'b0100) ? op1 ^ op2 : //XOR
(alu_control == 4'b0101) ? ~(op1 | op2) : //NOR
(alu_control == 4'b0110) ? op1 < op2 : //SLT
(alu_control == 4'b0111) ? op1 << op2[10:6] : //SLL
(alu_control == 4'b1000) ? op1 >> op2[10:6] : //SRL
(alu_control == 4'b1001) ? {$signed(op1) >>> op2[10:6]} : //SRA
(alu_control == 4'b1010) ? op2 << op1 : //SLLV
(alu_control == 4'b1011) ? op2 >> op1 : //SRLV
(alu_control == 4'b1100) ? {$signed(op2) >>> op1} : //SRAV
(alu_control == 4'b1101) ? {op2[15:0],16'b00000000_00000000} : //LUI
32'b11111111_11111111_11111111_11111111;
assign zero = (result == 0) ? 1'b1 : 1'b0;
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module led_green (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 8: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 8: 0] data_out;
wire [ 8: 0] out_port;
wire [ 8: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {9 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[8 : 0];
end
assign readdata = {{{32- 9}{1'b0}},read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m; void in() { cin >> n >> m; } void out() { int s = 0; if (n > m) { cout << n - m; return; } while (n < m) { s++; n <<= 1; } int diff = n - m; n >>= 1; long long x = 2; long long c = 0; while (x <= diff && c < s) { c++; x *= 2; } x /= 2; while (diff > 0) { diff -= x; s++; while (diff < x) { x /= 2; } } cout << s; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { in(); out(); } return 0; }
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#include <bits/stdc++.h> using namespace std; int n, s1, s2; int x[100001]; bool C(int v) { if (abs(s1 - s2) > v) return false; set<int> st; st.insert(s1); int pos = s2; for (int i = 0; i < n; i++) { if (st.size()) { st.insert(pos); } while (st.size() && abs(*st.begin() - x[i]) > v) { st.erase(*st.begin()); } while (st.size() && abs(*st.rbegin() - x[i]) > v) { st.erase(*st.rbegin()); } pos = x[i]; } if (st.empty()) return false; return true; } int main(void) { scanf( %d%d%d , &n, &s1, &s2); for (int i = 0; i < n; i++) { scanf( %d , &x[i]); } int l = -1, r = 1000000007; while (l + 1 < r) { int mid = (l + r) / 2; if (C(mid)) r = mid; else l = mid; } printf( %d n , r); return 0; }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* SGMII autonegotiation state machine
*/
module sgmii_autoneg
(
input rst,
input tbi_rx_clk,
input [7:0] rx_byte,
input rx_is_k,
input rx_disp_err,
output sgmii_autoneg_start,
output sgmii_autoneg_ack,
output sgmii_autoneg_idle,
output sgmii_autoneg_done,
output [15:0] sgmii_config
);
parameter LINK_TIMER = 16'd40000;
//
// RX Autonegotiation state machine
//
reg [5:0] rx_state;
wire [5:0] rx_state_next = (rx_state + 6'd1);
reg rx_state_start;
reg rx_state_ack;
reg rx_state_idle;
reg rx_state_complete;
reg [15:0] rx_cfg_cnt;
reg [15:0] rx_cfg1;
reg [15:0] rx_cfg2;
reg [15:0] rx_cfg;
wire rx_error = rx_disp_err || (rx_is_k && (rx_byte == 8'd0));
assign sgmii_autoneg_start = rx_state_start;
assign sgmii_autoneg_ack = rx_state_ack;
assign sgmii_autoneg_idle = rx_state_idle;
assign sgmii_autoneg_done = rx_state_complete;
assign sgmii_config = rx_cfg;
always @ (posedge tbi_rx_clk or posedge rst)
if (rst)
begin
rx_state <= 6'd0;
rx_state_start <= 1'b0;
rx_state_ack <= 1'b0;
rx_state_idle <= 1'b0;
rx_state_complete <= 1'b0;
rx_cfg_cnt <= 16'd0;
rx_cfg1 <= 16'd0;
rx_cfg2 <= 16'd0;
rx_cfg <= 16'd0;
end
else
case (rx_state)
6'd0:
begin
rx_state <= 6'd1;
rx_state_start <= 1'b0;
rx_state_ack <= 1'b0;
rx_state_idle <= 1'b0;
rx_state_complete <= 1'b0;
rx_cfg_cnt <= 16'd0;
rx_cfg1 <= 16'd0;
rx_cfg2 <= 16'd0;
rx_cfg <= 16'd0;
end
// Search for first CFG1/2
6'd1: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd1;
6'd2: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd1;
6'd3: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd4: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd5: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd6: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd7: rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
6'd8: rx_state <= (rx_is_k) ? 6'd0 : 6'd11;
// Continue to count LINK_TIMER x CFG1/2
6'd11: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd12: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd13:
begin
rx_state_start <= 1'b1;
rx_cfg_cnt <= rx_cfg_cnt + 16'd1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd14:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd15: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd16: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd17:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd18:
begin
rx_cfg2[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg_cnt == LINK_TIMER) ? 6'd21 : 6'd11;
end
// Wait for non-zero CFG
6'd21: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd22: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd23:
begin
rx_cfg_cnt <= 16'd0;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd24:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd25: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd26: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd27:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd28:
begin
rx_cfg2[15:8] <= rx_byte;
rx_cfg <= rx_cfg2;
rx_state <= (rx_is_k) ? 6'd0 : (rx_cfg1[0] && rx_cfg2[0] && rx_cfg[0]) ? 6'd31 : 6'd21;
end
// Wait for ACK
6'd31: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd32: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? rx_state_next : 6'd0;
6'd33:
begin
rx_state_ack <= 1'b1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd34:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd35: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd36: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd37:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd38:
begin
rx_cfg2[15:8] <= rx_byte;
rx_cfg <= rx_cfg2;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg1[14] && rx_cfg1[0] && rx_cfg2[14] && rx_cfg2[0] && rx_cfg[14] && rx_cfg[0]) ? 6'd41 : 6'd31;
end
// Continue to count LINK_TIMER more x CFG1/2, must match previous non-zero value
6'd41: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd42: rx_state <= (rx_is_k) ? 6'd0 : (rx_byte == 8'hB5) ? rx_state_next :
((rx_byte == 8'hC5) || (rx_byte == 8'h50)) ? 6'd51 : 6'd0;
6'd43:
begin
rx_cfg_cnt <= rx_cfg_cnt + 16'd1;
rx_cfg1[7:0] <= rx_byte;
rx_state <= (rx_is_k || (rx_cfg1 != rx_cfg2) || (rx_cfg1 != rx_cfg)) ? 6'd0 : rx_state_next;
end
6'd44:
begin
rx_cfg1[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd45: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd0;
6'd46: rx_state <= (!rx_is_k && (rx_byte == 8'h42)) ? rx_state_next : 6'd0;
6'd47:
begin
rx_cfg2[7:0] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 : rx_state_next;
end
6'd48:
begin
rx_cfg2[15:8] <= rx_byte;
rx_state <= (rx_is_k) ? 6'd0 :
(rx_cfg_cnt == LINK_TIMER) ? 6'd51 : 6'd41;
end
// Wait for 2 x IDLE
6'd51:
begin
rx_state_idle <= 1'b1;
rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
end
6'd52: rx_state <= (!rx_is_k && (rx_byte == 8'hB5)) ? 6'd59 :
(!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd53: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd54: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd55: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd56: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? rx_state_next : 6'd51;
6'd57: rx_state <= (rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : 6'd51;
6'd58: rx_state <= (!rx_is_k && ((rx_byte == 8'h50) || (rx_byte == 8'hC5))) ? 6'd61 : 6'd51;
// Error condition if CFG changed
6'd59: rx_state <= (!rx_is_k && (rx_byte != rx_cfg[7:0])) ? 6'd0 : 6'd60;
6'd60: rx_state <= (!rx_is_k && (rx_byte != rx_cfg[15:8])) ? 6'd0 : 6'd51;
// Done receiving CFG - restart on error or seeing another CFG sequence
6'd61:
begin
rx_state_complete <= 1'b1;
rx_state <= rx_state_next;
end
6'd62:
rx_state <= (rx_error) ? 6'd0 :
(rx_is_k && (rx_byte == 8'hBC)) ? rx_state_next : rx_state;
6'd63:
rx_state <= (rx_error) ? 6'd0 :
(!rx_is_k && ((rx_byte == 8'hB5) || (rx_byte == 8'h42))) ? 6'd0 : 6'd62;
default: rx_state <= 6'd0;
endcase
endmodule
|
/******************************************************************************/
/* LCD Controller monotone-RK 2014.12.01 */
/******************************************************************************/
`default_nettype none
`include "define.v"
module LCDCON #(parameter DIGIT = 8)
(input wire CLK,
input wire RST,
input wire [DIGIT*4-1:0] DATA,
input wire WE,
output reg TXD,
output reg READY);
function [7:0] mux;
input [7:0] a;
input [7:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
reg [(DIGIT+1)*10-1:0] cmd;
reg [11:0] waitnum;
reg [(DIGIT+3):0] cnt;
reg [DIGIT*4-1:0] D;
genvar i;
generate
wire [(DIGIT+1)*10-1:0] value;
for (i=0; i<(DIGIT+1); i=i+1) begin: val
if (i == DIGIT) begin
assign value[10*(i+1)-1:10*i] = {8'h20, 2'b01}; // add space
end else begin
wire [7:0] data = mux((8'd87+D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))]), // a ~ f
(8'd48+D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))]), // 0 ~ 9
(D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))]<10));
assign value[10*(i+1)-1:10*i] = {data, 2'b01};
end
end
endgenerate
always @(posedge CLK) begin
if (RST) begin
TXD <= 1;
READY <= 1;
cmd <= {((DIGIT+1)*10){1'b1}};
waitnum <= 0;
cnt <= 0;
D <= 0;
end else begin
if (READY) begin
TXD <= 1;
waitnum <= 0;
if (WE) begin
READY <= 0;
D <= DATA;
cnt <= (DIGIT+1)*10+2;
end
end else if (cnt == (DIGIT+1)*10+2) begin
cnt <= cnt - 1;
cmd <= value;
end else if (waitnum >= `SERIAL_WCNT) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[(DIGIT+1)*10-1:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
end
endmodule
`default_nettype wire
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#include <bits/stdc++.h> using namespace std; int main() { int x0, y0, x, y; cin >> x0 >> y0 >> x >> y; if (x0 != x && y != y0 && abs(x - x0) != abs(y - y0)) { cout << -1 << endl; return 0; } int dx = abs(y - y0); int dy = abs(x0 - x); if (x0 == x) cout << x0 + dx << << y0 << << x + dx << << y << endl; else if (y0 == y) cout << x0 << << y0 + dy << << x << << y + dy << endl; else cout << x0 << << y << << x << << y0 << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, a, b; int main() { cin >> n >> a >> b; long long chores[n]; for (int i = 0; i < n; i++) cin >> chores[i]; sort(chores, chores + n); cout << chores[b] - chores[b - 1] << endl; return 0; }
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#include <bits/stdc++.h> int main() { int m, n, i, j, k, p, l; scanf( %d %d , &m, &n); p = m + n; int a[m], b[n], c[p]; for (i = 0; i < m; i++) { scanf( %d , &a[i]); } for (i = 0; i < n; i++) { scanf( %d , &b[i]); } k = 0; for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { if (a[i] == b[j]) { c[k] = a[i]; k++; } } } l = k; for (k = 0; k < l; k++) { printf( %d , c[k]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; string t; map<string, int> mp; int solve(int l, int r) { int val = 0; for (int i = r - 1; i >= l; i--) { if (t[i] == ( ) val++; if (t[i] == ) ) val--; if (!val && (t[i] == + || t[i] == - )) { int L = solve(l, i); int R = solve(i + 1, r); if (L && R && (t[i] == + || R > 1)) return 1; else return 0; } } for (int i = r - 1; i >= l; i--) { if (t[i] == ( ) val++; if (t[i] == ) ) val--; if (!val && (t[i] == * || t[i] == / )) { int L = solve(l, i); int R = solve(i + 1, r); if (L > 1 && R > 1 && (t[i] == * || R > 2)) return 2; else return 0; } } string x = t.substr(l, r - l); if (t[l] == ( ) { if (solve(l + 1, r - 1)) return 3; return 0; } if (mp.count(x)) return mp[x]; return 3; } int Get() { string tmp; getline(cin, tmp); int len = tmp.length(); t = ; for (int i = 0; i < len; i++) if (tmp[i] != ) t += tmp[i]; return solve(0, t.length()); } int main() { scanf( %d , &n); string s; for (int i = 1; i <= n; i++) { scanf( #%*s ); cin >> s; mp[s] = Get(); } if (Get()) puts( OK ); else puts( Suspicious ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, x, y, arr1[2] = {0, 0}, arr2[2] = {0, 0}; cin >> n; for (int i = 0; i < n; i++) { cin >> t >> x >> y; if (t == 1) { arr1[0] += x; arr1[1] += y; } if (t == 2) { arr2[0] += x; arr2[1] += y; } } if (arr1[0] >= arr1[1]) { cout << LIVE << endl; } if (arr1[0] < arr1[1]) { cout << DEAD << endl; } if (arr2[0] >= arr2[1]) { cout << LIVE << endl; } if (arr2[0] < arr2[1]) { cout << DEAD << endl; } }
|
#include <bits/stdc++.h> using namespace std; const long long int mxn = 2 * 1e5 + 5; long long int vis[mxn]; vector<vector<long long int>> ad(mxn); long long int leaf, ans = 0; void dfs(long long int n, long long int d) { vis[n] = 1; for (auto child : ad[n]) if (!vis[child]) dfs(child, d + 1); if (d > ans) { ans = d; leaf = n; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t = 1; while (t--) { long long int i, j, k, n, m; cin >> n >> k; vector<long long int> par(k + 1); for (j = 1; j <= k; j++) par[j] = j; vector<vector<long long int>> adj(n + 1); for (i = 1; i <= k; i++) { adj[n].emplace_back(i); ad[n].emplace_back(i); ad[i].emplace_back(n); } for (j = 0; i < n; i++, j++) { adj[par[j % k + 1]].emplace_back(i); ad[par[j % k + 1]].emplace_back(i); ad[i].emplace_back(par[j % k + 1]); par[j % k + 1] = i; } dfs(1, 0); ans = 0; memset(vis, 0, sizeof vis); dfs(leaf, 0); cout << ans << n ; for (i = 1; i <= n; i++) { for (auto j : adj[i]) cout << i << << j << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = 1e9; int n, q; int a[400005]; struct rmq { int tree[1050000], lim; void init(int n) { memset(tree, 0, sizeof(tree)); for (lim = 1; lim <= n; lim <<= 1) ; } void add(int x, int v) { x += lim; tree[x] = max(tree[x], v); while (x > 1) { x >>= 1; tree[x] = max(tree[2 * x], tree[2 * x + 1]); } } int query(int s, int e) { s += lim; e += lim; int ret = 0; while (s < e) { if (s % 2 == 1) ret = max(ret, tree[s++]); if (e % 2 == 0) ret = max(ret, tree[e--]); s >>= 1; e >>= 1; } if (s == e) ret = max(ret, tree[s]); return ret; } } rmq; int dpl[400005], dpr[400005], lis; int cnt[400005]; bool check_indep(int x) { return cnt[dpr[x]] != 1 || dpl[x] + dpr[x] != lis + 1; } int is_indep[400005]; int aux[400005], ret[400005]; struct query { int x, y, idx; bool operator<(const query &q) const { return x < q.x; } }; int main() { scanf( %d %d , &n, &q); vector<int> v; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); v.push_back(a[i]); } sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); for (int i = 1; i <= n; i++) { a[i] = lower_bound(v.begin(), v.end(), a[i]) - v.begin() + 1; } rmq.init(n); for (int i = 1; i <= n; i++) { dpl[i] = rmq.query(1, a[i] - 1) + 1; rmq.add(a[i], dpl[i]); } rmq.init(n); for (int i = n; i; i--) { dpr[i] = rmq.query(a[i] + 1, n) + 1; rmq.add(a[i], dpr[i]); } for (int i = 1; i <= n; i++) { lis = max(lis, dpl[i]); } for (int i = 1; i <= n; i++) { if (dpl[i] + dpr[i] == lis + 1) { cnt[dpr[i]]++; } } for (int i = 1; i <= n; i++) { is_indep[i] = check_indep(i); } vector<query> qr; for (int i = 0; i < q; i++) { int x, y; scanf( %d %d , &x, &y); if (is_indep[x]) { ret[i] = lis; } else ret[i] = lis - 1; qr.push_back({x, y, i}); } sort(qr.begin(), qr.end()); rmq.init(n); int pnt = 1; for (int i = 0; i < q; i++) { while (pnt <= n && pnt < qr[i].x) { rmq.add(a[pnt], dpl[pnt]); pnt++; } int sy = lower_bound(v.begin(), v.end(), qr[i].y) - v.begin(); aux[qr[i].idx] += rmq.query(1, sy); } pnt = n; rmq.init(n); for (int i = q - 1; i >= 0; i--) { while (pnt && pnt > qr[i].x) { rmq.add(a[pnt], dpr[pnt]); pnt--; } int ey = upper_bound(v.begin(), v.end(), qr[i].y) - v.begin() + 1; aux[qr[i].idx] += rmq.query(ey, n); } for (int i = 0; i < q; i++) { ret[i] = max(ret[i], aux[i] + 1); printf( %d n , ret[i]); } }
|
#include <bits/stdc++.h> using namespace std; vector<int> finger; int seq[100]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> seq[i]; for (int i = 0; i < m; i++) { int x; cin >> x; finger.push_back(x); } for (int i = 0; i < n; i++) { for (vector<int>::iterator itr = finger.begin(); itr != finger.end(); itr++) { if (*itr == seq[i]) { cout << *itr << ; break; } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_2_V
`define SKY130_FD_SC_HDLL__OR4_2_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_2 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4_2 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_2_V
|
module wb_stream_writer_tb;
localparam FIFO_AW = 5;
localparam MAX_BURST_LEN = 32;
localparam WB_AW = 32;
localparam WB_DW = 32;
localparam WSB = WB_DW/8; //Word size in bytes
localparam MEM_SIZE = 128*WSB; //Memory size in bytes
localparam MAX_BUF_SIZE = 128; //Buffer size in bytes
localparam BURST_SIZE = 8;
//Configuration registers
localparam REG_CSR = 0*WSB;
localparam REG_START_ADDR = 1*WSB;
localparam REG_BUF_SIZE = 2*WSB;
localparam REG_BURST_SIZE = 3*WSB;
reg clk = 1'b1;
reg rst = 1'b1;
always#10 clk <= ~clk;
initial #100 rst <= 0;
vlog_tb_utils vlog_tb_utils0();
vlog_functions utils();
vlog_tap_generator #("wb_stream_writer_tb.tap", 1) tap();
//Wishbone memory interface
wire [WB_AW-1:0] wb_m2s_data_adr;
wire [WB_DW-1:0] wb_m2s_data_dat;
wire [WB_DW/8-1:0] wb_m2s_data_sel;
wire wb_m2s_data_we;
wire wb_m2s_data_cyc;
wire wb_m2s_data_stb;
wire [2:0] wb_m2s_data_cti;
wire [1:0] wb_m2s_data_bte;
wire [WB_DW-1:0] wb_s2m_data_dat;
wire wb_s2m_data_ack;
wire wb_s2m_data_err;
//Wishbone configuration interface
wire [WB_AW-1:0] wb_m2s_cfg_adr;
wire [WB_DW-1:0] wb_m2s_cfg_dat;
wire [WB_DW/8-1:0] wb_m2s_cfg_sel;
wire wb_m2s_cfg_we;
wire wb_m2s_cfg_cyc;
wire wb_m2s_cfg_stb;
wire [2:0] wb_m2s_cfg_cti;
wire [1:0] wb_m2s_cfg_bte;
wire [WB_DW-1:0] wb_s2m_cfg_dat;
wire wb_s2m_cfg_ack;
wire wb_s2m_cfg_err;
//Stream interface
wire [WB_DW-1:0] stream_data;
wire stream_valid;
wire stream_ready;
wire irq;
wb_stream_writer
#(.FIFO_AW (FIFO_AW),
.MAX_BURST_LEN (MAX_BURST_LEN))
dut
(.clk (clk),
.rst (rst),
//Stream data output
.wbm_adr_o (wb_m2s_data_adr),
.wbm_dat_o (wb_m2s_data_dat),
.wbm_sel_o (wb_m2s_data_sel),
.wbm_we_o (wb_m2s_data_we),
.wbm_cyc_o (wb_m2s_data_cyc),
.wbm_stb_o (wb_m2s_data_stb),
.wbm_cti_o (wb_m2s_data_cti),
.wbm_bte_o (wb_m2s_data_bte),
.wbm_dat_i (wb_s2m_data_dat),
.wbm_ack_i (wb_s2m_data_ack),
.wbm_err_i (wb_s2m_data_err),
//FIFO interface
.stream_m_data_o (stream_data),
.stream_m_valid_o (stream_valid),
.stream_m_ready_i (stream_ready),
.stream_m_irq_o (irq),
//Control Interface
.wbs_adr_i (wb_m2s_cfg_adr[4:0]),
.wbs_dat_i (wb_m2s_cfg_dat),
.wbs_sel_i (wb_m2s_cfg_sel),
.wbs_we_i (wb_m2s_cfg_we),
.wbs_cyc_i (wb_m2s_cfg_cyc),
.wbs_stb_i (wb_m2s_cfg_stb),
.wbs_cti_i (wb_m2s_cfg_cti),
.wbs_bte_i (wb_m2s_cfg_bte),
.wbs_dat_o (wb_s2m_cfg_dat),
.wbs_ack_o (wb_s2m_cfg_ack),
.wbs_err_o (wb_s2m_cfg_err));
stream_reader
#(.WIDTH (WB_DW),
.MAX_BLOCK_SIZE (MAX_BUF_SIZE/WSB))
stream_reader0
(.clk (clk),
.stream_s_data_i (stream_data),
.stream_s_valid_i (stream_valid),
.stream_s_ready_o (stream_ready));
wb_bfm_memory
#(.mem_size_bytes(MEM_SIZE),
.rd_min_delay (0),
.rd_max_delay (5))
wb_ram0
(//Wishbone Master interface
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_i (wb_m2s_data_adr),
.wb_dat_i (wb_m2s_data_dat),
.wb_sel_i (wb_m2s_data_sel),
.wb_we_i (wb_m2s_data_we),
.wb_cyc_i (wb_m2s_data_cyc),
.wb_stb_i (wb_m2s_data_stb),
.wb_cti_i (wb_m2s_data_cti),
.wb_bte_i (wb_m2s_data_bte),
.wb_dat_o (wb_s2m_data_dat),
.wb_ack_o (wb_s2m_data_ack),
.wb_err_o (wb_s2m_data_err),
.wb_rty_o ());
wb_bfm_master
#(.MAX_BURST_LEN (2))
wb_cfg
(.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_adr_o (wb_m2s_cfg_adr),
.wb_dat_o (wb_m2s_cfg_dat),
.wb_sel_o (wb_m2s_cfg_sel),
.wb_we_o (wb_m2s_cfg_we),
.wb_cyc_o (wb_m2s_cfg_cyc),
.wb_stb_o (wb_m2s_cfg_stb),
.wb_cti_o (wb_m2s_cfg_cti),
.wb_bte_o (wb_m2s_cfg_bte),
.wb_dat_i (wb_s2m_cfg_dat),
.wb_ack_i (wb_s2m_cfg_ack),
.wb_err_i (wb_s2m_cfg_err),
.wb_rty_i (1'b0));
integer transaction;
integer TRANSACTIONS;
reg VERBOSE = 0;
initial begin
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
if($test$plusargs("verbose"))
VERBOSE = 1;
@(negedge rst);
@(posedge clk);
//stream_reader0.rate = 0.08;
//fifo_reader0.timeout = ;
//Initialize memory
init_mem();
@(posedge clk);
for(transaction=1;transaction<=TRANSACTIONS;transaction=transaction+1) begin
test_main();
utils.progress_bar("Completed transaction", transaction, TRANSACTIONS);
end
tap.ok("All done");
$finish;
end
task test_main;
reg [MAX_BUF_SIZE*WB_DW-1:0] received;
integer seed;
integer tmp;
integer start_addr;
integer buf_size;
integer burst_len;
begin
burst_len = $dist_uniform(seed, 2, MAX_BURST_LEN/WSB);
//FIXME: buf_size currently needs to be a multiple of burst_size
//buf_size = $dist_uniform(seed,1,MAX_BUF_SIZE/WSB)*WSB;
buf_size = burst_len*WSB*$dist_uniform(seed, 1, MAX_BUF_SIZE/(burst_len*WSB));
start_addr = $dist_uniform(seed,0,(MEM_SIZE-buf_size)/WSB)*WSB;
if(VERBOSE) $display("Setting start address to 0x%8x", start_addr);
if(VERBOSE) $display("Setting buffer size to %0d", buf_size);
if(VERBOSE) $display("Setting burst length to %0d", burst_len);
wb_write(REG_START_ADDR, start_addr);
wb_write(REG_BUF_SIZE , buf_size);
wb_write(REG_BURST_SIZE, burst_len);
@(posedge clk);
fork
begin
//Enable stream writer
wb_write(REG_CSR, 1);
//Wait for interrupt
@(posedge irq);
//Clear interrupt
wb_write(REG_CSR, 2);
end
begin
//Start receive transactor
fifo_read(received, buf_size/WSB);
end
join
verify(received, buf_size/WSB, start_addr);
end
endtask
task wb_write;
input [WB_AW-1:0] addr_i;
input [WB_DW-1:0] data_i;
reg err;
begin
wb_cfg.write(addr_i, data_i, 4'hf, err);
if(err) begin
$display("Error writing to config interface address 0x%8x", addr_i);
$finish;
end
end
endtask
task fifo_read;
output [MAX_BUF_SIZE*8-1:0] data_o;
input integer length_i;
begin
stream_reader0.read_block(data_o, length_i);
end
endtask
task init_mem;
integer idx;
integer tmp;
integer seed;
begin
for(idx = 0; idx < MEM_SIZE/WSB ; idx = idx + 1) begin
tmp = $random(seed);
wb_ram0.mem[idx] = tmp[WB_DW-1:0];
if(VERBOSE) $display("Writing 0x%8x to address 0x%8x", tmp, idx*WSB);
end
end
endtask
task verify;
input [MAX_BUF_SIZE*8-1:0] received_i;
input integer samples_i;
input integer start_addr_i;
integer idx;
reg [WB_DW-1:0] expected;
reg [WB_DW-1:0] received;
reg err;
begin
err = 0;
for(idx=0 ; idx<samples_i ; idx=idx+1) begin
expected = wb_ram0.mem[start_addr_i/WSB+idx];
received = received_i[idx*WB_DW+:WB_DW];
if(expected !==
received) begin
$display("Error at address 0x%8x. Expected 0x%8x, got 0x%8x", start_addr_i+idx*4, expected, received);
err = 1'b1;
end //else $display("0x%8x : 0x%8x", start_addr_i+idx*WSB, received);
end
if(err)
$finish;
else
if (VERBOSE) $display("Successfully verified %0d words", idx);
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int o, trues, Bruh, YO; bool levls[696969]; int main() { int n, X; cin >> n; for (int a = 0; a < 2; a++) { cin >> Bruh; for (int AL = 0; AL < Bruh; AL++) { cin >> YO; levls[YO] = true; } } for (int x = 1; x <= n; x++) { if (levls[x] == true) trues++; } if (trues == n) cout << I become the guy. << endl; else cout << Oh, my keyboard! << endl; }
|
#include <bits/stdc++.h> using namespace std; const string problemName = ; const string inputFile = problemName + .in ; const string outputFile = problemName + .out ; const int INF = (1LL << 31) - 1; const long long int LINF = (1LL << 62) - 1; const int dx[] = {1, 0, -1, 0, 1, -1, 1, -1}; const int dy[] = {0, 1, 0, -1, 1, -1, -1, 1}; const int MOD = (int)(1e9) + 7; const int NMAX = 100000 + 5; const int MMAX = 100000 + 5; const int KMAX = 100000 + 5; const int PMAX = 100000 + 5; const int LMAX = 100000 + 5; const int VMAX = 100000 + 5; long long int t, a, b, n, i, tt, q, sol = 0; long long int A[NMAX]; int putere(long long int b, long long int a) { if (a == 1 && b != 1) return 0; if (a != 1 && b == 1) return 0; while (b != 1 && b % a == 0) b /= a; return b == 1; } int main() { scanf( %lld%lld%lld , &t, &a, &b); if (t != 1 || (t == 1 && !putere(b, a))) { if (a == b) sol++; for (n = 0; b && a > 1; n++) { A[n] = b % a; b /= a; } for (i = q = 0, tt = 1; i < n; i++) { q += A[i] * tt; tt *= t; if (q < 0 || q > a) break; } if (q == a) sol++; printf( %lld , sol); } else { if (a == 1 && b == 1) printf( inf ); else printf( %d , putere(b, a)); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_PP_SYMBOL_V
|
//Alan Achtenberg
//Lab 7
//Part 2
module Dlatch (q,qbar,clock,data);
output q, qbar;
input clock, data;
wire nand1, nand2;
wire databar;
not #1 (databar,data);
nand #1 (nand1,clock, data);
nand #1 (nand2,clock, databar);
nand #1 (qbar,nand2,q);
nand #1 (q,nand1,qbar);
endmodule
module m555(clock);
parameter InitDelay = 10, Ton = 50, Toff = 50;
output clock;
reg clock;
initial begin
#InitDelay clock = 1;
end
always begin
#Ton clock = ~clock;
#Toff clock = ~clock;
end
endmodule
module testD(q, qbar, clock, data);
input q, qbar, clock;
output data;
reg data;
initial begin
$monitor ($time, " q = %d, qbar = %d, clock = %d, data = %d", q, qbar, clock, data);
data = 0;
#25
data = 1;
#100
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
$finish; /* $finish simulation after 100 time simulation units */
end
endmodule
module testBenchD;
wire clock, q, qbar, data;
m555 clk(clock);
Dlatch dl(q, qbar, clock, data);
testD td(q, qbar, clock, data);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, j = 0; cin >> a >> b >> c; for (int i = 1; i <= a; i++) { if (b >= 2 * i && c >= 4 * i) j++; } cout << j + 2 * j + 4 * j; return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = (1e-8); int dcmp(double a, double b) { if (fabs(a - b) <= eps) return 0; return a < b ? -1 : 1; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n, m; double w; cin >> n >> w >> m; double how = n * w / (m * 1.0); vector<vector<pair<int, double> > > res(m); vector<double> bottles; vector<int> cnt(n, 0); for (int i = 0; i < n; i++) bottles.push_back(w); cout << fixed << setprecision(6); for (int i = 0; i < m; i++) { double temp = how; for (int j = 0; j < n; j++) { if (dcmp(bottles[j], 0) == 0) continue; if (dcmp(temp, 0) == 0) break; if (bottles[j] > temp) { res[i].push_back({j, temp}); bottles[j] -= temp; temp = 0; cnt[j]++; break; } else { res[i].push_back({j, bottles[j]}); temp -= bottles[j]; bottles[j] = 0; cnt[j]++; } } if (dcmp(temp, 0) != 0) return cout << NO << endl, 0; } for (int i = 0; i < n; i++) { if (cnt[i] > 2 || dcmp(bottles[i], 0) != 0) return cout << NO << endl, 0; } cout << YES << endl; for (int i = 0; i < m; i++) { for (auto p : res[i]) { cout << p.first + 1 << << p.second << ; } cout << endl; } return 0; }
|
`include "memory.v"
`include "register_file.v"
`include "sim.v"
`include "decoder.v"
`define ADDRESS_WIDTH 32
`define DATA_WIDTH 32
module decoder_test();
wire reset;
wire clk;
reg [`ADDRESS_WIDTH-1:0] mem_address = 0;
wire [`DATA_WIDTH-1:0] mem_data_out;
reg[31:0] decoder_inp;
reg[1:0] instr_size;
reg mem_cmd = `MEM_CMD_READ;
reg mem_valid;
wire mem_ready;
wire mem_res_valid;
integer tests;
initial begin
//$dumpfile("dump.vcd");
// $dumpvars;
tests = 0;
end
always @(posedge clk) begin
if (!reset && mem_ready) begin
mem_valid <= 1;
decoder_inp = mem_data_out;
end
if (!reset && mem_res_valid) begin
mem_valid <= 0;
// $display("Address = %h, data = %h, data 2 = %h", mem_address, mem_data_out, decoder_inp);
mem_address += (`DATA_WIDTH / 8);
//tests += 1;
//if (tests > 20)
// #20 $finish;
end
end
decoder my_decoder(
.i_clk(clk),
.i_reset(reset),
.i_ready(mem_valid),
.i_data(decoder_inp),
.o_instr_size(instr_size));
// Memory module
memory #(`ADDRESS_WIDTH, `DATA_WIDTH) my_mem(
.clk(clk),
.reset(reset),
.i_address(mem_address),
.i_res_ready(1'b1), //we are always ready to receive data
.i_cmd(mem_cmd), //R/W
.i_data(`DATA_WIDTH'bx),//no write data
.i_valid(mem_valid),
.o_data(mem_data_out),
.o_res_valid(mem_res_valid),
.o_ready(mem_ready)
);
// Simulator (clock + reset)
sim my_sim(
.clk(clk),
.reset(reset)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; struct ant { int id; int novo_id; long long int p; int dir; }; struct rotate_edges { int id_ini; int id_fim; }; int compara_p(ant a, ant b) { return a.p < b.p || (a.p == b.p && a.dir < b.dir); } int compara_p_reverso(ant a, ant b) { return a.p > b.p; } int compara_id(ant a, ant b) { return a.id < b.id; } int cont_pos, cont_neg; long long int N, M, T; ant v[400000]; ant v_final[400000]; ant v_pos[400000]; ant v_neg[400000]; char c; rotate_edges calcula_rotate_edges(long long int t, int pivot) { long long int p_pivot = v[pivot].p; int cont_neg = 0; int cont_pos = 0; for (int i = 0; i < N; i++) { if (v[i].dir < 0) { v_neg[cont_neg] = v[i]; if (v_neg[cont_neg].p < p_pivot) v_neg[cont_neg].p += M; cont_neg++; } else { v_pos[cont_pos] = v[i]; if (v_pos[cont_pos].p > p_pivot) v_pos[cont_pos].p -= M; cont_pos++; } } sort(v_neg, v_neg + cont_neg, compara_p); sort(v_pos, v_pos + cont_pos, compara_p_reverso); rotate_edges resp; if (cont_neg == 0) { resp.id_ini = v_pos[0].id; resp.id_fim = v_pos[0].id; } else if (cont_pos == 0) { resp.id_ini = v_neg[0].id; resp.id_fim = v_neg[0].id; } else { resp.id_ini = v_pos[0].id; resp.id_fim = v_pos[0].id; int id_pos; int id_neg; long long int p_pos; long long int p_neg; for (int i = 0;; i++) { id_pos = (i + 1) / 2; id_neg = i / 2; p_pos = v_pos[id_pos % cont_pos].p - M * (id_pos / cont_pos); p_neg = v_neg[id_neg % cont_neg].p + M * (id_neg / cont_neg); if (p_neg - p_pos <= 2 * t) { resp.id_fim = (i % 2 == 0) ? v_neg[id_neg % cont_neg].id : v_pos[id_pos % cont_pos].id; } else { break; } } } return resp; } long long int calcula_delta(rotate_edges re) { int vi_ini, vi_fim; for (int i = 0; i < N; i++) { if (v[i].id == re.id_ini) vi_ini = i; if (v[i].id == re.id_fim) vi_fim = i; } return (vi_fim + N - vi_ini) % N; } void rotate(long long int delta) { for (int i = 0; i < N; i++) { v[i].novo_id = v[(i + N - delta) % N].id; } for (int i = 0; i < N; i++) { v[i].id = v[i].novo_id; } } void rotate_final(rotate_edges re) { int id, id_final; for (int i = 0; i < N; i++) { if (v[i].id == re.id_ini) id = i; if (v_final[i].id == re.id_fim) id_final = i; } for (int i = 0; i < N; i++) { v_final[(id_final + i) % N].id = v[(id + i) % N].id; } } int main() { scanf( %lld %lld %lld , &N, &M, &T); for (int i = 0; i < N; i++) { v[i].id = i; scanf( %lld %c , &v[i].p, &c); v[i].p = v[i].p % M; if (c == L ) { v[i].dir = -1; } else { v[i].dir = 1; } } sort(v, v + N, compara_p); int pivot = 0; for (int i = 0; i < N; i++) { if (v[i].dir > 0 && v[(i + 1) % N].dir < 0) { pivot = i; break; } } long long int delta_por_ciclo = calcula_delta(calcula_rotate_edges(M, pivot)); rotate((delta_por_ciclo * (T / M)) % N); T = T % M; rotate_edges re = calcula_rotate_edges(T, pivot); for (int i = 0; i < N; i++) { v_final[i] = v[i]; v_final[i].p = (((v[i].p + v[i].dir * T) % M) + M) % M; } sort(v_final, v_final + N, compara_p); rotate_final(re); sort(v_final, v_final + N, compara_id); printf( %d , v_final[0].p == 0 ? M : v_final[0].p); for (int i = 1; i < N; i++) { printf( %d , v_final[i].p == 0 ? M : v_final[i].p); } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; long long a[k + 1]; for (long long i = 0; i < k; i++) { cin >> a[i]; } long long c4 = n, c2 = 2 * n; long long o1 = 0; for (long long i = 0; i < k; i++) { while (c4 > 0 && a[i] > 3) { c4 -= 1; a[i] -= 4; } while (c2 >= 2 && a[i] > 3) { c2 -= 2; a[i] -= 4; } if (a[i] >= 3) { while (c4 > 0 && a[i] > 0) { c4 -= 1; a[i] -= 3; } while (c2 >= 2 && a[i] > 0) { c2 -= 2; a[i] -= 3; } } if (a[i] >= 2) { while (c2 > 0 && a[i] > 0) { c2 -= 1; a[i] -= 2; } while (c4 > 0 && a[i] > 0) { c4 -= 1; o1++; a[i] -= 2; } } if (a[i] > 0) { while (o1 > 0 && a[i] > 0) { o1--; a[i]--; } while (c4 > 0 && a[i] > 0) { c4 -= 1; a[i] -= 1; c2++; } while (a[i] > 0 && c2 > 0) { c2 -= 1; a[i] -= 1; } } if (a[i] > 0) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, r; int y1, y2, yw, x, y; scanf( %d%d%d%d%d%d , &a, &b, &c, &x, &y, &r); y2 = b; if (b - a < r) { printf( -1 n ); return 0; } y1 = a + r; yw = c - r; y = 2 * yw - y; double k = (1.0) * (y - y1) / x; double ans = (yw - y1) / k; double dis = (y2 - y1) / sqrt(k * k + 1); if (dis < r) printf( -1 n ); else printf( %.10f n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; const long long INF = 1LL << 60; const long long mod = 1e9 + 7; const long double eps = 1e-8; const long double pi = acos(-1.0); template <class T> inline bool chmax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } template <class T> inline bool chmin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } long long f(long long l, long long p) { long long w = l / p; long long p2 = l % p, p1 = p - p2; return p1 * w * w + p2 * (w + 1) * (w + 1); } void solve() { long long n, k; cin >> n >> k; vector<long long> a(n); long long ans = 0; priority_queue<pair<long long, pair<long long, long long>>> pque; for (long long i = 0; i < n; i++) { cin >> a[i]; ans += a[i] * a[i]; pque.push({f(a[i], 1) - f(a[i], 2), {a[i], 2}}); } for (long long i = 0; i < k - n; i++) { auto x = pque.top(); pque.pop(); ans -= x.first; long long l = x.second.first, p = x.second.second; pque.push({f(l, p) - f(l, p + 1), {l, p + 1}}); } cout << ans << endl; } signed main() { ios::sync_with_stdio(false); cin.tie(0); solve(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_SYMBOL_V
`define SKY130_FD_SC_LS__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_SYMBOL_V
|
//======================================================================
//
// avalanche_entropy_core.v
// ------------------------
// Core functionality for the entropy provider core based on
// an external avalanche noise based source. (or any other source that
// can toggle a single bit input).
//
// Currently the design consists of a counter running at clock speeed.
// When a positive flank event is detected in the noise source the
// current LSB value of the counter is pushed into a 32bit
// entropy collection shift register.
//
// The core provides functionality to measure the time betwee
// positive flank events counted as number of clock cycles. There
// is also access ports for the collected entropy.
//
// No post-processing is currently performed done on the entropy.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module avalanche_entropy_core(
input wire clk,
input wire reset_n,
input wire noise,
input wire enable,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [31 : 0] delta,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG_DELAY = 32'h002c4b40;
parameter MIN_ENTROPY_BITS = 6'h20;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg noise_sample0_reg;
reg noise_sample_reg;
reg flank0_reg;
reg flank1_reg;
reg entropy_bit_reg;
reg [31 : 0] entropy_reg;
reg [31 : 0] entropy_new;
reg entropy_we;
reg entropy_valid_reg;
reg entropy_valid_new;
reg [5 : 0] bit_ctr_reg;
reg [5 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_we;
reg enable_reg;
reg [31 : 0] cycle_ctr_reg;
reg [31 : 0] cycle_ctr_new;
reg [31 : 0] delta_reg;
reg delta_we;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [7 : 0] debug_reg;
reg debug_we;
reg debug_update_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign entropy_valid = entropy_valid_reg;
assign entropy_data = entropy_reg;
assign delta = delta_reg;
assign debug = debug_reg;
assign entropy_enabled = enable_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
noise_sample0_reg <= 1'b0;
noise_sample_reg <= 1'b0;
flank0_reg <= 1'b0;
flank1_reg <= 1'b0;
entropy_valid_reg <= 1'b0;
entropy_reg <= 32'h00000000;
entropy_bit_reg <= 1'b0;
bit_ctr_reg <= 6'h00;
cycle_ctr_reg <= 32'h00000000;
delta_reg <= 32'h00000000;
debug_delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
debug_update_reg <= 0;
enable_reg <= 0;
end
else
begin
noise_sample0_reg <= noise;
noise_sample_reg <= noise_sample0_reg;
flank0_reg <= noise_sample_reg;
flank1_reg <= flank0_reg;
entropy_valid_reg <= entropy_valid_new;
entropy_bit_reg <= ~entropy_bit_reg;
cycle_ctr_reg <= cycle_ctr_new;
debug_update_reg <= debug_update;
enable_reg <= enable;
if (delta_we)
begin
delta_reg <= cycle_ctr_reg;
end
if (bit_ctr_we)
begin
bit_ctr_reg <= bit_ctr_new;
end
if (entropy_we)
begin
entropy_reg <= entropy_new;
end
if (debug_delay_ctr_we)
begin
debug_delay_ctr_reg <= debug_delay_ctr_new;
end
if (debug_we)
begin
debug_reg <= entropy_reg[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// debug_out
//
// Logic that updates the debug port.
//----------------------------------------------------------------
always @*
begin : debug_out
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 0;
debug_we = 0;
if (debug_update_reg)
begin
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
debug_delay_ctr_we = 1;
end
if (debug_delay_ctr_reg == DEBUG_DELAY)
begin
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 1;
debug_we = 1;
end
end
//----------------------------------------------------------------
// entropy_collect
//
// We collect entropy by adding the current state of the
// entropy bit register the entropy shift register every time
// we detect a positive flank in the noise source.
//----------------------------------------------------------------
always @*
begin : entropy_collect
entropy_new = 32'h00000000;
entropy_we = 1'b0;
bit_ctr_inc = 1'b0;
if ((flank0_reg) && (!flank1_reg))
begin
entropy_new = {entropy_reg[30 : 0], entropy_bit_reg};
entropy_we = 1'b1;
bit_ctr_inc = 1'b1;
end
end // entropy_collect
//----------------------------------------------------------------
// delta_logic
//
// The logic implements the delta time measuerment system.
//----------------------------------------------------------------
always @*
begin : delta_logic
cycle_ctr_new = cycle_ctr_reg + 1'b1;
delta_we = 1'b0;
if ((flank0_reg) && (!flank1_reg))
begin
cycle_ctr_new = 32'h00000000;
delta_we = 1'b1;
end
end // delta_logic
//----------------------------------------------------------------
// entropy_ack_logic
//
// The logic needed to handle detection that entropy has been
// read and ensure that we collect more than 32 entropy
// bits beforeproviding more entropy.
//----------------------------------------------------------------
always @*
begin : entropy_ack_logic
bit_ctr_new = 6'h00;
bit_ctr_we = 1'b0;
entropy_valid_new = 1'b0;
if (bit_ctr_reg == MIN_ENTROPY_BITS)
begin
entropy_valid_new = 1'b1;
end
if ((bit_ctr_inc) && (bit_ctr_reg < 6'h20))
begin
bit_ctr_new = bit_ctr_reg + 1'b1;
bit_ctr_we = 1'b1;
end
else if (entropy_ack)
begin
bit_ctr_new = 6'h00;
bit_ctr_we = 1'b1;
end
end // entropy_ack_logic
endmodule // avalanche_entropy_core
//======================================================================
// EOF avalanche_entropy_core.v
//======================================================================
|
`timescale 1ns / 1ps
module test_GPIA();
reg [15:0] story_o;
reg clk_o;
reg rst_o;
reg adr_o;
reg we_o;
reg cyc_o;
reg stb_o;
reg [15:0] dat_o;
reg [15:0] port_o;
wire [15:0] port_i;
wire [15:0] dat_i;
wire ack_i;
GPIA gpia(
.RST_I(rst_o),
.CLK_I(clk_o),
.PORT_O(port_i),
.PORT_I(port_o),
.ADR_I(adr_o),
.WE_I(we_o),
.CYC_I(cyc_o),
.STB_I(stb_o),
.DAT_I(dat_o),
.DAT_O(dat_i),
.ACK_O(ack_i)
);
always begin
#50 clk_o <= ~clk_o;
end
initial begin
clk_o <= 0;
rst_o <= 0;
adr_o <= 0;
we_o <= 0;
cyc_o <= 0;
stb_o <= 0;
dat_o <= 16'h0000;
wait(clk_o); wait(~clk_o);
// AS A systems engineer
// I WANT all outputs to go to zero upon reset
// SO THAT the system starts in a well-known state.
story_o <= 16'h0000;
rst_o <= 1;
wait(clk_o); wait(~clk_o);
rst_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(port_i !== 16'h0000) begin
$display("Reset should set output port to all zeros."); $stop;
end
// AS A software engineer
// I WANT to be able to write a value to the output port
// SO THAT peripherals may be controlled.
story_o <= 16'h0010;
adr_o <= 1;
we_o <= 1;
cyc_o <= 1;
stb_o <= 1;
dat_o <= 16'hDEAD;
wait(clk_o); wait(~clk_o);
if(port_i !== 16'hDEAD) begin
$display("Writing to a port should take effect immediately."); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A hardware engineer
// I WANT the GPIA to issue its own acknowledge signal for a write cycle
// SO THAT the bus master doesn't hang indefinitely.
story_o <= 16'h0020;
adr_o <= 1;
we_o <= 1;
cyc_o <= 1;
stb_o <= 1;
dat_o <= 16'hBEEF;
wait(clk_o); wait(~clk_o);
if(~ack_i) begin
$display("ACK signal expected to complete bus transaction."); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A hardware engineer
// I WANT the GPIA to handle back-to-back writes gracefully
// SO THAT the bus master doesn't get confused about its bus timing.
story_o <= 16'h0025;
adr_o <= 1;
we_o <= 1;
cyc_o <= 1;
stb_o <= 1;
dat_o <= 16'hBEEF;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(ack_i) begin
$display("ACK signal expected to be negated at this point."); $stop;
end
wait(clk_o); wait(~clk_o);
if(~ack_i) begin
$display("ACK for 2nd cycle supposed to be here."); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A software engineer
// I WANT to read the last written contents of the output port
// SO THAT I can bit-bang with impunity.
story_o <= 16'h0030;
adr_o <= 1;
we_o <= 1;
cyc_o <= 1;
stb_o <= 1;
dat_o <= 16'hFEED;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
adr_o <= 1;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
wait(clk_o); wait(~clk_o);
if(dat_i !== 16'hFEED) begin
$display("We just wrote a value; we should be able to read it again."); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A software engineer
// I WANT to read the status of the input ports
// SO THAT I can respond to external stimuli.
story_o <= 16'h0040;
adr_o <= 0;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
port_o <= 16'hFACE;
wait(clk_o); wait(~clk_o);
if(dat_i !== 16'hFACE) begin
$display("Expected to read input port value"); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A hardware engineer
// I WANT the ACK_O signal to become valid when the data bus is driven.
// SO THAT the bus master doesn't hang indefinitely waiting for data, or latching bad data.
story_o <= 16'h0050;
adr_o <= 0;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
port_o <= 16'h0BAD;
wait(clk_o); wait(~clk_o);
if(~ack_i) begin
$display("Expected to ACK at the same time as the driven data"); $stop;
end
wait(clk_o); wait(~clk_o);
// AS A hardware engineer
// I WANT the GPIA to negate its ACK once no longer addressed
// SO THAT other bus masters can start using the bus right away.
story_o <= 16'h0060;
adr_o <= 0;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
port_o <= 16'hC0FF;
wait(clk_o);
cyc_o <= 0;
wait(~clk_o);
if(~ack_i) begin
$display("Synchronous bus: Should not negate right now."); $stop;
end
wait(clk_o); wait(~clk_o);
if(ack_i) begin
$display("Expected ACK to negate now."); $stop;
end
story_o <= 16'h0070;
adr_o <= 0;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
port_o <= 16'h600D;
wait(clk_o);
stb_o <= 0;
wait(~clk_o);
if(~ack_i) begin
$display("Synchronous bus: Should not negate right now."); $stop;
end
wait(clk_o); wait(~clk_o);
if(ack_i) begin
$display("Expected ACK to negate now."); $stop;
end
// AS A hardware engineer
// I WANT the GPIA to properly differentiate back to back reads
// SO THAT the bus master timing remains intact.
story_o <= 16'h0080;
adr_o <= 0;
we_o <= 0;
cyc_o <= 1;
stb_o <= 1;
port_o <= 16'h7EA0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(ack_i) begin
$display("Expected new bus cycle this cycle"); $stop;
end
wait(clk_o); wait(~clk_o);
if(~ack_i) begin
$display("Expected ACK for 2nd cycle here."); $stop;
end
// We're done.
story_o <= 16'hFFFF;
wait(clk_o); wait(~clk_o);
$stop;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// flow_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:19 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module flow_ctrl
(
Reset ,
Clk ,
//host processor ,
tx_pause_en ,
xoff_cpu ,
xon_cpu ,
//MAC_rx_flow ,
pause_quanta ,
pause_quanta_val ,
//MAC_tx_ctrl ,
pause_apply ,
pause_quanta_sub ,
xoff_gen ,
xoff_gen_complete ,
xon_gen ,
xon_gen_complete
);
input Reset ;
input Clk ;
//host processor ;
input tx_pause_en ;
input xoff_cpu ;
input xon_cpu ;
//MAC_rx_flow ;
input [15:0] pause_quanta ;
input pause_quanta_val ;
//MAC_tx_ctrl ;
output pause_apply ;
input pause_quanta_sub ;
output xoff_gen ;
input xoff_gen_complete ;
output xon_gen ;
input xon_gen_complete ;
//******************************************************************************
//internal signals
//******************************************************************************
reg xoff_cpu_dl1 ;
reg xoff_cpu_dl2 ;
reg xon_cpu_dl1 ;
reg xon_cpu_dl2 ;
reg [15:0] pause_quanta_dl1 ;
reg pause_quanta_val_dl1 ;
reg pause_quanta_val_dl2 ;
reg pause_apply ;
reg xoff_gen ;
reg xon_gen ;
reg [15:0] pause_quanta_counter ;
reg tx_pause_en_dl1 ;
reg tx_pause_en_dl2 ;
//******************************************************************************
//boundery signal processing
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
xoff_cpu_dl1 <=0;
xoff_cpu_dl2 <=0;
end
else
begin
xoff_cpu_dl1 <=xoff_cpu;
xoff_cpu_dl2 <=xoff_cpu_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
xon_cpu_dl1 <=0;
xon_cpu_dl2 <=0;
end
else
begin
xon_cpu_dl1 <=xon_cpu;
xon_cpu_dl2 <=xon_cpu_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
pause_quanta_dl1 <=0;
end
else
begin
pause_quanta_dl1 <=pause_quanta;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
pause_quanta_val_dl1 <=0;
pause_quanta_val_dl2 <=0;
end
else
begin
pause_quanta_val_dl1 <=pause_quanta_val;
pause_quanta_val_dl2 <=pause_quanta_val_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
tx_pause_en_dl1 <=0;
tx_pause_en_dl2 <=0;
end
else
begin
tx_pause_en_dl1 <=tx_pause_en;
tx_pause_en_dl2 <=tx_pause_en_dl1;
end
//******************************************************************************
//gen output signals
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
xoff_gen <=0;
else if (xoff_gen_complete)
xoff_gen <=0;
else if (xoff_cpu_dl1&&!xoff_cpu_dl2)
xoff_gen <=1;
always @ (posedge Clk or posedge Reset)
if (Reset)
xon_gen <=0;
else if (xon_gen_complete)
xon_gen <=0;
else if (xon_cpu_dl1&&!xon_cpu_dl2)
xon_gen <=1;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_counter <=0;
else if(pause_quanta_val_dl1&&!pause_quanta_val_dl2)
pause_quanta_counter <=pause_quanta_dl1;
else if(pause_quanta_sub&&pause_quanta_counter!=0)
pause_quanta_counter <=pause_quanta_counter-1;
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_apply <=0;
else if(pause_quanta_counter==0)
pause_apply <=0;
else if (tx_pause_en_dl2)
pause_apply <=1;
endmodule
|
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Cyclone V" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
//VERSION_BEGIN 14.0 cbx_altclkbuf 2014:06:05:09:45:41:SJ cbx_cycloneii 2014:06:05:09:45:41:SJ cbx_lpm_add_sub 2014:06:05:09:45:41:SJ cbx_lpm_compare 2014:06:05:09:45:41:SJ cbx_lpm_decode 2014:06:05:09:45:41:SJ cbx_lpm_mux 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratix 2014:06:05:09:45:41:SJ cbx_stratixii 2014:06:05:09:45:41:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus II License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_clkena 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module clock_control_altclkctrl_0_sub
(
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_outclk;
wire [1:0] clkselect;
cyclonev_clkena sd1
(
.ena(ena),
.enaout(),
.inclk(inclk[0]),
.outclk(wire_sd1_outclk));
defparam
sd1.clock_type = "Auto",
sd1.ena_register_mode = "falling edge",
sd1.lpm_type = "cyclonev_clkena";
assign
clkselect = {2{1'b0}},
outclk = wire_sd1_outclk;
endmodule //clock_control_altclkctrl_0_sub
//VALID FILE // (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clock_control_altclkctrl_0 (
ena,
inclk,
outclk);
input ena;
input inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire outclk;
wire sub_wire1;
wire [3:0] sub_wire2;
wire [2:0] sub_wire3;
assign outclk = sub_wire0;
assign sub_wire1 = inclk;
assign sub_wire2[3:0] = {sub_wire3, sub_wire1};
assign sub_wire3[2:0] = 3'h0;
clock_control_altclkctrl_0_sub clock_control_altclkctrl_0_sub_component (
.ena (ena),
.inclk (sub_wire2),
.outclk (sub_wire0));
endmodule
|
`include "brouter_3x3.v"
`include "defines.v"
module test_brouter_3x3();
reg `control_w b0_ci, b1_ci, b2_ci,
b4_ci, b5_ci, b6_ci,
b8_ci, b9_ci, ba_ci;
wire `control_w b0_co, b1_co, b2_co,
b4_co, b5_co, b6_co,
b8_co, b9_co, ba_co;
reg `data_w b0_di, b1_di, b2_di,
b4_di, b5_di, b6_di,
b8_di, b9_di, ba_di;
wire `data_w b0_do, b1_do, b2_do,
b4_do, b5_do, b6_do,
b8_do, b9_do, ba_do;
wire b0_r, b1_r, b2_r,
b4_r, b5_r, b6_r,
b8_r, b9_r, ba_r;
reg rst;
reg clk;
// Instantiate Network
brouter_3x3 br
(b0_ci, b1_ci, b2_ci, b4_ci, b5_ci, b6_ci, b8_ci, b9_ci, ba_ci,
b0_di, b1_di, b2_di, b4_di, b5_di, b6_di, b8_di, b9_di, ba_di,
clk, rst,
b0_co, b1_co, b2_co, b4_co, b5_co, b6_co, b8_co, b9_co, ba_co,
b0_do, b1_do, b2_do, b4_do, b5_do, b6_do, b8_do, b9_do, ba_do,
b0_r, b1_r, b2_r, b4_r, b5_r, b6_r, b8_r, b9_r, ba_r);
// Clock
always begin
#10;
clk = ~clk;
end
// Prints out resource port for each router
task print_port(
input [15:0] n,
input `control_w c,
input `data_w d,
input r);
begin
$display("B%h: |%h|%b|%b|%b|%b|%b|%b|", n, r, c[`valid_f],
c[`seq_f], c[`src_f], c[`dest_f], c[`age_f], d);
end
endtask
always @(posedge clk) begin
$display("OUT: |R|V|SEQ|SRC |DEST|AGE | DATA |");
print_port(0, b0_co, b0_do, b0_r);
print_port(1, b1_co, b1_do, b1_r);
print_port(2, b2_co, b2_do, b2_r);
print_port(4, b4_co, b4_do, b4_r);
print_port(5, b5_co, b5_do, b5_r);
print_port(6, b6_co, b6_do, b6_r);
print_port(8, b8_co, b8_do, b8_r);
print_port(9, b9_co, b9_do, b9_r);
print_port(10, ba_co, ba_do, ba_r);
$display("");
end
initial begin
clk = 0;
rst = 1;
//North links
/*
b0_ci = {1'b1, `seq_n'd3, `addr_n'd0, `addr_n'd2, `age_n'd0};
b0_di = `data_n'd0;
b1_ci = {1'b1, `seq_n'd3, `addr_n'd1, `addr_n'd0, `age_n'd0};
b1_di = `data_n'd1;
b2_ci = {1'b1, `seq_n'd3, `addr_n'd2, `addr_n'd1, `age_n'd0};
b2_di = `data_n'd2;
b4_ci = {1'b1, `seq_n'd3, `addr_n'd4, `addr_n'd6, `age_n'd0};
b4_di = `data_n'd4;
b5_ci = {1'b1, `seq_n'd3, `addr_n'd5, `addr_n'd4, `age_n'd0};
b5_di = `data_n'd5;
b6_ci = {1'b1, `seq_n'd3, `addr_n'd6, `addr_n'd5, `age_n'd0};
b6_di = `data_n'd6;
b8_ci = {1'b1, `seq_n'd3, `addr_n'd8, `addr_n'd10, `age_n'd0};
b8_di = `data_n'd8;
b9_ci = {1'b1, `seq_n'd3, `addr_n'd9, `addr_n'd8, `age_n'd0};
b9_di = `data_n'd9;
ba_ci = {1'b1, `seq_n'd3, `addr_n'd10, `addr_n'd9, `age_n'd0};
ba_di = `data_n'd10;
*/
// South Links
/*
b0_ci = {1'b1, `seq_n'd3, `addr_n'd0, `addr_n'd1, `age_n'd0};
b0_di = `data_n'd0;
b1_ci = {1'b1, `seq_n'd3, `addr_n'd1, `addr_n'd2, `age_n'd0};
b1_di = `data_n'd1;
b2_ci = {1'b1, `seq_n'd3, `addr_n'd2, `addr_n'd0, `age_n'd0};
b2_di = `data_n'd2;
b4_ci = {1'b1, `seq_n'd3, `addr_n'd4, `addr_n'd5, `age_n'd0};
b4_di = `data_n'd4;
b5_ci = {1'b1, `seq_n'd3, `addr_n'd5, `addr_n'd6, `age_n'd0};
b5_di = `data_n'd5;
b6_ci = {1'b1, `seq_n'd3, `addr_n'd6, `addr_n'd4, `age_n'd0};
b6_di = `data_n'd6;
b8_ci = {1'b1, `seq_n'd3, `addr_n'd8, `addr_n'd9, `age_n'd0};
b8_di = `data_n'd8;
b9_ci = {1'b1, `seq_n'd3, `addr_n'd9, `addr_n'd10, `age_n'd0};
b9_di = `data_n'd9;
ba_ci = {1'b1, `seq_n'd3, `addr_n'd10, `addr_n'd8, `age_n'd0};
ba_di = `data_n'd10;
*/
// East Links
/*
b0_ci = {1'b1, `seq_n'd3, `addr_n'd0, `addr_n'd4, `age_n'd0};
b0_di = `data_n'd0;
b1_ci = {1'b1, `seq_n'd3, `addr_n'd1, `addr_n'd5, `age_n'd0};
b1_di = `data_n'd1;
b2_ci = {1'b1, `seq_n'd3, `addr_n'd2, `addr_n'd6, `age_n'd0};
b2_di = `data_n'd2;
b4_ci = {1'b1, `seq_n'd3, `addr_n'd4, `addr_n'd8, `age_n'd0};
b4_di = `data_n'd4;
b5_ci = {1'b1, `seq_n'd3, `addr_n'd5, `addr_n'd9, `age_n'd0};
b5_di = `data_n'd5;
b6_ci = {1'b1, `seq_n'd3, `addr_n'd6, `addr_n'd10, `age_n'd0};
b6_di = `data_n'd6;
b8_ci = {1'b1, `seq_n'd3, `addr_n'd8, `addr_n'd0, `age_n'd0};
b8_di = `data_n'd8;
b9_ci = {1'b1, `seq_n'd3, `addr_n'd9, `addr_n'd1, `age_n'd0};
b9_di = `data_n'd9;
ba_ci = {1'b1, `seq_n'd3, `addr_n'd10, `addr_n'd2, `age_n'd0};
ba_di = `data_n'd10;
*/
// West Links
b0_ci = {1'b1, `seq_n'd3, `addr_n'd0, `addr_n'd8, `age_n'd0};
b0_di = `data_n'd0;
b1_ci = {1'b1, `seq_n'd3, `addr_n'd1, `addr_n'd9, `age_n'd0};
b1_di = `data_n'd1;
b2_ci = {1'b1, `seq_n'd3, `addr_n'd2, `addr_n'd10, `age_n'd0};
b2_di = `data_n'd2;
b4_ci = {1'b1, `seq_n'd3, `addr_n'd4, `addr_n'd0, `age_n'd0};
b4_di = `data_n'd4;
b5_ci = {1'b1, `seq_n'd3, `addr_n'd5, `addr_n'd1, `age_n'd0};
b5_di = `data_n'd5;
b6_ci = {1'b1, `seq_n'd3, `addr_n'd6, `addr_n'd2, `age_n'd0};
b6_di = `data_n'd6;
b8_ci = {1'b1, `seq_n'd3, `addr_n'd8, `addr_n'd4, `age_n'd0};
b8_di = `data_n'd8;
b9_ci = {1'b1, `seq_n'd3, `addr_n'd9, `addr_n'd5, `age_n'd0};
b9_di = `data_n'd9;
ba_ci = {1'b1, `seq_n'd3, `addr_n'd10, `addr_n'd6, `age_n'd0};
ba_di = `data_n'd10;
// Reset Overhead
@(negedge clk);
rst = 0;
@(negedge clk);
@(negedge clk);
// Cycle 1
@(negedge clk);
@(negedge clk);
@(negedge clk);
// Cycle 2
@(negedge clk);
@(negedge clk);
@(negedge clk);
// Cycle 3
@(negedge clk);
$display("%b", br.br0000.rc4.disty_wrap);
$display("%b", br.br0000.rc4.disty_norm);
$display("%b", br.br0000.rc4.disty_norm_dir);
$display("%b", br.br0000.rmatrix4);
$finish;
end
endmodule
|
// megafunction wizard: %LPM_FIFO+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: Altera_UP_Video_In_Dual_Clock_FIFO.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_up_video_dual_clock_fifo (
// Inputs
wrclk,
wrreq,
data,
rdclk,
rdreq,
// Outputs
wrusedw,
wrfull,
q,
rdusedw,
rdempty
);
parameter DW = 18;
input wrclk;
input wrreq;
input [(DW-1):0] data;
input rdclk;
input rdreq;
output [6:0] wrusedw;
output wrfull;
output [(DW-1):0] q;
output [6:0] rdusedw;
output rdempty;
dcfifo dcfifo_component (
// Inputs
.wrclk (wrclk),
.wrreq (wrreq),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
// Outputs
.wrusedw (wrusedw),
.wrfull (wrfull),
.q (q),
.rdusedw (rdusedw),
.rdempty (rdempty)
// synopsys translate_off
,
.aclr (),
.rdempty (),
.rdfull (),
.wrempty ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = DW,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "26"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "26"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL data[25..0]
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL q[25..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL rdusedw[6..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_Video_In_Dual_Clock_FIFO_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int c = 3002; int w, n, m, dif[c], rf[c]; long long sok = 1e15; pair<long long, long long> op[c][c], cl[c][c]; vector<int> sz[c]; bool v[c]; pair<long long, long long> add(pair<long long, long long> a, pair<long long, long long> b) { return {a.first + b.first, a.second + b.second}; } void dfs(int a) { v[a] = true; rf[a] = 1; for (int i = 0; i <= n; i++) { op[a][i] = {-sok, -sok}; } op[a][1] = {0, dif[a]}; for (int x : sz[a]) { if (!v[x]) { dfs(x); rf[a] += rf[x]; for (int db = rf[a]; db >= 1; db--) { op[a][db] = max(add(op[a][db], op[x][1]), add(op[a][db - 1], cl[x][1])); for (int i = max(2, db - rf[a] + rf[x]); i <= min(rf[x], db); i++) { op[a][db] = max({op[a][db], add(op[a][db - i], cl[x][i]), add(op[a][db - i + 1], op[x][i])}); } } } } for (int i = 1; i <= rf[a]; i++) { cl[a][i] = {op[a][i].first + (op[a][i].second > 0), 0}; } } int main() { ios_base::sync_with_stdio(false); cin >> w; while (w--) { cin >> n >> m; for (int i = 1; i <= n; i++) { int x; cin >> x; dif[i] = -x; } for (int i = 1; i <= n; i++) { int x; cin >> x; dif[i] += x; } for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; sz[a].push_back(b), sz[b].push_back(a); } dfs(1); cout << cl[1][m].first << n ; for (int i = 1; i <= n; i++) { v[i] = 0; sz[i].clear(); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; void query() { int n, m; cin >> n >> m; vector<string> t(n); for (auto& i : t) cin >> i; vector<vector<int>> col(n, vector<int>(m, 0)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) col[i][j] = (i > 0 ? col[i - 1][j] : 0) + t[i][j] - 0 ; int res = inf; queue<pair<int, int>> q; for (int a = 5; a <= n; a++) { for (int i = 0; i <= n - a; i++) { while (!q.empty()) q.pop(); pair<int, int> X(inf, 0); int add = 0; for (int j = 0; j < m; j++) { while (q.size() >= 3) { if (q.front().first - q.front().second < X.first - X.second) X = q.front(); q.pop(); } int A = col[i + a - 2][j] - col[i][j]; if (j - 3 >= 0) res = min(res, X.first - X.second + add + a - 2 - A); if (j > 0) add += A + 2 - (int)(t[i][j] - 0 ) - (int)(t[i + a - 1][j] - 0 ); q.push({a - 2 - A, add}); } } } cout << res << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int q = 1; cin >> q; while (q--) query(); return 0; }
|
/* This file is part of jt51.
jt51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
jt51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with jt51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 7th 2017
*/
`timescale 1ns / 1ps
module jt51_fir_ram
#(parameter data_width=8, parameter addr_width=7)
(
input [(data_width-1):0] data,
input [(addr_width-1):0] addr,
input we, clk,
output [(data_width-1):0] q
);
(* ramstyle = "no_rw_check" *) reg [data_width-1:0] ram[2**addr_width-1:0];
reg [addr_width-1:0] addr_reg;
always @ (posedge clk) begin
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests size casting of complex expressions.
module resize(output wire logic[4:0] result);
reg logic[6:0] a;
assign result = (5'(a + 2));
initial begin
a = 7'd39;
end
endmodule
module resize_test();
logic [4:0] result;
resize dut(result);
initial begin
#1;
if(result !== 5'd9) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("25.175000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbp (
RESET_B,
D ,
GATE ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int in[2 * 100010], s[2 * 100010]; int n; int main() { scanf( %d , &n); memset(in, 0, sizeof(in)); memset(s, 0, sizeof(s)); for (int i = 0; i < n; i++) { int xx; scanf( %d , &xx); s[i] = xx; in[xx] = i + 1; } int t = 0; for (int i = 0; i < n; i++) { int x, j; scanf( %d , &x); if (in[x]) for (j = t; j < n && s[j] != x; j++) in[s[j]] = 0; else { printf( 0 ); continue; } printf( %d , j - t + 1); t = j + 1; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long cq, q, c[2000 + 10][2000 + 10], cg[2000 + 10][2000 + 10], pos[2000 + 10], n, m, k, bl[2000 + 10][2000 + 10][3], cnt[2000 + 10]; template <class T> bool Read(T &x) { char c; bool f = 0; while (c = getchar(), c != EOF) { if (c == - ) f = 1; else if (c >= 0 && c <= 9 ) { x = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) x = x * 10 + c - 0 ; ungetc(c, stdin); if (f) x = -x; return 1; } } return 0; } inline int lowbit(long long x) { return x & -x; } inline void update(long long *c, int x, long long d) { while (x <= m) { c[x] += d; x += lowbit(x); } } inline void update(int x, int y, long long d) { while (x <= n) { update(c[x], y, d); x += lowbit(x); } } inline long long get_sum(long long *c, int x) { long long ret = 0; while (x) { ret += c[x]; x ^= lowbit(x); } return ret; } inline long long get_sum(int x, int y) { long long ret = 0; while (x) { ret += get_sum(c[x], y); x ^= lowbit(x); } return ret; } struct Query { int p, x1, x2, y1, y2; } Q[1000000 + 10]; void read() { Read(n), Read(m), Read(k); int i, j; for (i = 1; i <= k; i++) { Read(cnt[i]); for (j = 1; j <= cnt[i]; j++) Read(bl[i][j][0]), Read(bl[i][j][1]), Read(bl[i][j][2]); } Read(q); char s[20]; for (i = 1; i <= q; i++) { scanf( %s , s); if (*s == S ) { Q[i].p = 1; Read(Q[i].x1); } else { Q[i].p = 2; Read(Q[i].x1), Read(Q[i].y1), Read(Q[i].x2), Read(Q[i].y2); pos[++cq] = i; } } } bool vis[2000 + 10]; void solve() { int i, j; for (i = 1; i <= k; i++) { for (j = 1; j <= cnt[i]; j++) update(bl[i][j][0], bl[i][j][1], bl[i][j][2]); for (j = 1; j <= cq; j++) cg[j][i] = get_sum(Q[pos[j]].x2, Q[pos[j]].y2) - get_sum(Q[pos[j]].x2, Q[pos[j]].y1 - 1) - get_sum(Q[pos[j]].x1 - 1, Q[pos[j]].y2) + get_sum(Q[pos[j]].x1 - 1, Q[pos[j]].y1 - 1); for (j = 1; j <= cnt[i]; j++) update(bl[i][j][0], bl[i][j][1], -bl[i][j][2]); } int cc = 0; long long ans = 0; for (i = 1; i <= q; i++) { if (Q[i].p == 1) vis[Q[i].x1] ^= 1; else { ans = 0; cc++; for (j = 1; j <= k; j++) if (!vis[j]) ans += cg[cc][j]; printf( %I64d n , ans); } } } int main() { read(); solve(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/12/2015 12:22:18 PM
// Design Name:
// Module Name: SerialHandler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SerialHandler(
input wire clk100MHz,
input wire clk1MHz,
input wire rst,
input wire ext_clk,
input wire ext_flush,
input wire serial,
input wire [CHANNEL_WIDTH-1:0] channel,
output reg [CHANNEL_WIDTH-1:0] ser_channel,
output reg [POSITION_WIDTH-1:0] ser_pos
);
parameter POSITION_WIDTH = 11;
parameter CHANNEL_WIDTH = 5;
parameter BUFFER_LENGTH = 16;
reg [BUFFER_LENGTH-1:0] buffer;
reg [CHANNEL_WIDTH-1:0] channel_select;
reg [POSITION_WIDTH-1:0] position;
wire clk;
wire flush;
ExtToIntSync U0(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_clk),
.int_signal(clk)
);
ExtToIntSync U1(
.clk(clk100MHz),
.rst(rst),
.ext_signal(ext_flush),
.int_signal(flush)
);
integer ptr;
always @(posedge clk or posedge rst) begin
if(rst) begin
position = 0;
buffer = 0;
ptr = 0;
end
else if(!flush) begin
if(ptr < 15) begin
buffer[(BUFFER_LENGTH-1)-ptr] = serial;
ptr = ptr + 1;
end
else begin
// Channel Select: 15th-11th bit (5 bit width)
channel_select = buffer[BUFFER_LENGTH-1:BUFFER_LENGTH-5];
// Position: 11th-0th bit (11 bit width)
position = buffer[BUFFER_LENGTH-6:0];
// Write to position file @ channel select point
// Make position a 11 bit signal and OR a 1 with it.
//position_file[channel_select] = (position << 1) | 1'b1;
if(channel_select == channel) begin
ser_pos = position;
end
//ser_pos = position;
ser_channel = channel_select;
// Reset buffer and ptr
buffer = 0;
ptr = 0;
end
end
else begin
position = 0;
buffer = 0;
ptr = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long f(int d) { long long res = 0; long long dp[100]; memset(dp, 0ll, sizeof(dp)); for (int k = 1; k < d; k++) if (d % k == 0) { res += ((1ll << (k - 1)) - dp[k]); int nk = k * 2; for (; nk <= d; nk += k) dp[nk] += ((1ll << (k - 1)) - dp[k]); } return res; } bool periodic(long long N, int d) { for (int i = 0; i < d; i++) if ((d + 1) % (i + 1) == 0) { long long num = 0; for (int j = 0; j <= d; j++) if (N & (1ll << (d - j % (i + 1)))) num ^= (1ll << (d - j)); if (num == N) return true; } return false; } bool differs(long long a, long long b, int bt, int nb) { for (int i = nb; i > bt; i--) if ((a & (1ll << i)) != (b & (1ll << i))) return false; return (a & (1ll << bt)) < (b & (1ll << bt)); } long long F(long long N) { if (!N) return 0; int nd = 0; for (; (1ll << nd) <= N; nd++) ; nd--; long long ans = periodic(N, nd); for (int d = 2; d <= nd; d++) ans += f(d); long long dp[100]; for (int i = nd - 1; i >= 0; i--) { memset(dp, 0ll, sizeof(dp)); if (N & (1ll << i)) { memset(dp, 0ll, sizeof(dp)); for (int j = 0; j < (nd - i); j++) if ((j + 1) < (nd + 1) && (nd + 1) % (j + 1) == 0) { long long num = 0; for (int k = 0; k <= nd; k++) if (N & (1ll << (nd - k % (j + 1)))) num ^= (1ll << (nd - k)); if (num < N && differs(num, N, i, nd)) { ans++; for (int k = (j + 1) * 2; k <= (nd + 1); k += (j + 1)) dp[k - 1]++; } } for (int j = (nd - i); j <= nd; j++) { if ((j + 1) < (nd + 1) && (nd + 1) % (j + 1) == 0) { ans += (1ll << (j - (nd - i))) - dp[j]; for (int k = (j + 1) * 2; k <= (nd + 1); k += (j + 1)) dp[k - 1] += (1ll << (j - (nd - i))) - dp[j]; } } } } return ans; } int main() { long long L, R; cin >> L >> R; cout << F(R) - F(L - 1) << endl; return 0; }
|
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
reg clk;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
`ifdef SINGLE
parameter SW = 24;
`endif
`ifdef DOUBLE
parameter SW = 54;// */
`endif
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
wire [2*SW-1:0] RKOA_RESULT;
reg clk;
reg rst;
reg load_b_i;
integer ERROR = 0;
`ifdef SINGLE
RecursiveKOA_SW24
`endif
`ifdef DOUBLE
RecursiveKOA_SW54
`endif
inst_Sgf_Multiplication (.clk(clk),.rst(rst),.load_b_i(load_b_i),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(RKOA_RESULT));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b, RKOA_RESULT, a*b);
if (a*b != RKOA_RESULT) begin
$display("ERROR> NO SON IGUALES");
ERROR = ERROR + 1;
end
end
initial begin
b = 1;
rst = 1;
a = 1;
load_b_i = 0;
#30;
rst = 0;
#15;
load_b_i = 1;
#100;
b = 2;
#5;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; double eps = 1e-8; vector<int> b, c; int vis[2100000], a[210000], ans[210000], x; int read() { int v = 0, f = 1; char c = getchar(); while (c < 48 || 57 < c) { if (c == - ) f = -1; c = getchar(); } while (48 <= c && c <= 57) v = (v << 3) + v + v + c - 48, c = getchar(); return v * f; } void ins(int u) { int t = u; for (int &v : b) u = min(u, u ^ v); if (u) { b.push_back(u); c.push_back(t); for (int i = (int)(int)b.size() - 1; i >= (int)1; i--) if (b[i] > b[i - 1]) swap(b[i], b[i - 1]); else break; } } void dfs(int u, int s) { ans[s] = u; vis[u] = 1; if (s == (1 << x) - 1) return; for (int &v : c) if (!vis[u ^ v]) { dfs(u ^ v, s + 1); return; } } int main() { int n = read(); for (int i = (int)1; i <= (int)n; i++) a[i] = read(); sort(a + 1, a + n + 1); x = 0; int j = 1; for (int i = (int)1; i <= (int)19; i++) { while (j <= n && a[j] <= ((1 << i) - 1)) { ins(a[j]); j++; } if (b.size() == i) x = i; } b.clear(); c.clear(); for (int i = (int)1; i <= (int)n; i++) if (a[i] <= ((1 << x) - 1)) ins(a[i]); else break; dfs(0, 0); printf( %d n , x); for (int i = (int)0; i <= (int)(1 << x) - 1; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; using LL = long long; using PII = pair<int, int>; int main() { auto get_factors = [](int n) { vector<int> ret; for (int i = 1; i * i <= n; i++) { if (n % i == 0) { ret.push_back(i); if (i * i != n) ret.push_back(n / i); } } sort(ret.begin(), ret.end()); return ret; }; vector<vector<int>> factors(1e5 + 1); for (int i = (1); i <= (1e5); ++i) factors[i] = get_factors(i); ios::sync_with_stdio(false); int tc; cin >> tc; while (tc--) { int x[3], cnt[8] = {0}; cin >> x[0] >> x[1] >> x[2]; vector<int> v; for (int i = 0; i < 3; i++) { for (auto val : factors[x[i]]) v.push_back(val); } sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); for (auto val : v) { int mask = 0; for (int i = 0; i < 3; i++) { if (x[i] % val == 0) mask |= 1 << i; } cnt[mask]++; } int ans = 0; for (int a = 1; a < 8; a++) { for (int b = a; b < 8; b++) { int t1 = a | b; if (t1 == (t1 & -t1)) continue; for (int c = b; c < 8; c++) { int t2 = a | c, t3 = b | c; if (t2 == (t2 & -t2)) continue; if (t3 == (t3 & -t3)) continue; if ((a | b | c) != 7) continue; if (a != b && a != c && b != c) { ans += cnt[a] * cnt[b] * cnt[c]; } else if (a == b && b == c) { int n = cnt[a] + 2; ans += n * (n - 1) * (n - 2) / 6; } else if (a == b) { ans += cnt[a] * (cnt[a] + 1) / 2 * cnt[c]; } else if (a == c) { ans += cnt[a] * (cnt[a] + 1) / 2 * cnt[b]; } else if (b == c) { ans += cnt[b] * (cnt[b] + 1) / 2 * cnt[a]; } } } } cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int m, n, L, cnt, sum[1000005]; char s[1000005], x[1000005]; struct Node { Node *par, *go[26]; int val, sum, flag, num; void Clear(int _val) { par = NULL; for (int i = 0; i < 26; i++) go[i] = NULL; sum = flag = 0; val = _val; } } * root, *last, *a[1000005 * 2], *b[1000005 * 2]; void Extend(int w) { Node *p = last, *np = new Node; a[++cnt] = np; np->num = cnt; np->Clear(p->val + 1); for (; p && (!(p->go[w])); p = p->par) p->go[w] = np; if (!p) np->par = root; else { Node *q = p->go[w]; if (q->val == p->val + 1) np->par = q; else { Node *nq = new Node; a[++cnt] = nq; nq->num = cnt; nq->Clear(p->val + 1); for (int i = 0; i < 26; i++) nq->go[i] = q->go[i]; nq->par = q->par; q->par = np->par = nq; for (; p && (p->go[w] == q); p = p->par) p->go[w] = nq; } } last = np; } void BuildSAM() { scanf( %s , &s); m = strlen(s); cnt = 0; root = new Node; root->Clear(0); root->num = 0; last = root; for (int i = 0; i < m; i++) Extend(s[i] - a ); } void DP() { for (Node *p = last; p; p = p->par) p->sum = 1; for (int i = 0; i <= m; i++) sum[i] = 0; for (int i = 1; i <= cnt; i++) sum[a[i]->val]++; for (int i = 1; i <= m; i++) sum[i] += sum[i - 1]; for (int i = 1; i <= cnt; i++) b[sum[a[i]->val]--] = a[i]; for (int i = cnt; i >= 1; i--) { Node *p = b[i]; for (int j = 0; j < 26; j++) if (p->go[j]) { p->sum += p->go[j]->sum; } } } int main() { BuildSAM(); DP(); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , &x); L = strlen(x); Node *p = root; int len = 0; for (int j = 0; j < L; j++) { int w = x[j] - a ; while (p && (!p->go[w])) p = p->par; if (!p) p = root; len = min(len, p->val); if (p->go[w]) { p = p->go[w]; len++; } } int ans = 0; for (int j = 0; j < L; j++) { int w = x[j] - a ; while (p && (!p->go[w])) p = p->par; if (!p) { p = root; continue; } len = min(len + 1, p->val + 1); p = p->go[w]; while (p->par && (p->par->val >= L)) p = p->par; if (p->flag == i) continue; if (len >= L) { ans += p->sum; p->flag = i; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 5e3 + 10; int a[M]; int dp[M][M]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , a + i), dp[i][i] = a[i]; for (int d = 1; d < n; d++) { for (int i = 1; i + d <= n; i++) { int j = i + d; dp[i][j] = dp[i][j - 1] ^ dp[i + 1][j]; } } for (int d = 1; d < n; d++) { for (int i = 1; i + d <= n; i++) { int j = i + d; dp[i][j] = max({dp[i][j], dp[i + 1][j], dp[i][j - 1]}); } } int q, l, r; scanf( %d , &q); while (q--) { scanf( %d%d , &l, &r); printf( %d n , dp[l][r]); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_4_V
`define SKY130_FD_SC_HDLL__O211A_4_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211a_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o211a_4 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, adder. This is a simple adder, but had to be
// pipe-lined for faster clock rates. The delay input is delay-matched to
// the sum pipe-line stages
`timescale 1ps/1ps
module cf_add (
// data_p = data_1 + data_2 + data_3 + data_4 (all the inputs are signed)
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [24:0] data_1;
input [24:0] data_2;
input [24:0] data_3;
input [24:0] data_4;
output [ 7:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [ 7:0] data_p = 'd0;
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
// pipe line stage 2, get the sum (intermediate, 4->2)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
// pipe line stage 3, get the sum (final, 2->1)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 00:02:33 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_0_1/RAT_FlagReg_0_1_sim_netlist.v
// Design : RAT_FlagReg_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_FlagReg_0_1,FlagReg,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "FlagReg,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_FlagReg_0_1
(IN_FLAG,
LD,
SET,
CLR,
CLK,
OUT_FLAG);
input IN_FLAG;
input LD;
input SET;
input CLR;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
output OUT_FLAG;
wire CLK;
wire CLR;
wire IN_FLAG;
wire LD;
wire OUT_FLAG;
wire SET;
RAT_FlagReg_0_1_FlagReg U0
(.CLK(CLK),
.CLR(CLR),
.IN_FLAG(IN_FLAG),
.LD(LD),
.OUT_FLAG(OUT_FLAG),
.SET(SET));
endmodule
(* ORIG_REF_NAME = "FlagReg" *)
module RAT_FlagReg_0_1_FlagReg
(OUT_FLAG,
IN_FLAG,
SET,
LD,
CLR,
CLK);
output OUT_FLAG;
input IN_FLAG;
input SET;
input LD;
input CLR;
input CLK;
wire CLK;
wire CLR;
wire IN_FLAG;
wire LD;
wire OUT_FLAG;
wire OUT_FLAG_i_1_n_0;
wire SET;
LUT5 #(
.INIT(32'hACAFACAC))
OUT_FLAG_i_1
(.I0(IN_FLAG),
.I1(SET),
.I2(LD),
.I3(CLR),
.I4(OUT_FLAG),
.O(OUT_FLAG_i_1_n_0));
FDRE OUT_FLAG_reg
(.C(CLK),
.CE(1'b1),
.D(OUT_FLAG_i_1_n_0),
.Q(OUT_FLAG),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
module Tic_tac_toe(
input iCLK_50,
input [3:0] iSW,
input BTN_WEST,
input BTN_EAST,
input BTN_NORTH,
input BTN_SOUTH,
output wire oVGA_R,
output wire oVGA_G,
output wire oVGA_B,
output oHS,
output oVS,
output [7:0] oLED
);
reg CLK_25;
wire reset;
wire start;
wire btn_player1;
wire btn_player2;
wire [10:0] vcounter;
wire [11:0] hcounter;
wire [8:0] symbol;
wire [8:0] occupied;
assign reset = BTN_SOUTH;
syn_edge_detect sed1(CLK_25, reset, BTN_EAST, btn_player1);
syn_edge_detect sed2(CLK_25, reset, BTN_WEST, btn_player2);
syn_edge_detect sed3(CLK_25, reset, BTN_NORTH, start);
// generate a 25Mhz clock
always @(posedge iCLK_50)
CLK_25 = ~CLK_25;
VGA_control vga_c(.CLK(CLK_25),.reset(reset),.vcounter(vcounter),
.hcounter(hcounter),.visible(visible),.oHS(oHS),.oVS(oVS));
state_control s_control(.CLK(CLK_25),.START(start),.RESET(reset),.BTN_PLAYER1(btn_player1), .BTN_PLAYER2(btn_player2),.iSW(iSW),.OLED(oLED), .occupied(occupied), .symbol(symbol));
draw_symbols d_symbol(.reset(reset), .vcounter(vcounter), .hcounter(hcounter), .visible(visible), .VGA_R(oVGA_R), .VGA_G(oVGA_G), .VGA_B(oVGA_B), .occupied(occupied), .symbol(symbol));
endmodule
|
/******************************************************************************/
/* DRAM Controller for VC707 Ryohei Kobayashi */
/* 2016-03-23 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
module DRAMCON(input wire CLK_P,
input wire CLK_N,
input wire RST_X_IN,
////////// User logic interface ports //////////
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`APPDATA_WIDTH-1:0] D_DIN, //
output wire D_W, //
output reg [`APPDATA_WIDTH-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY, //
output wire USERCLK, //
output wire RST_O, //
////////// Memory interface ports //////////
inout wire [`DDR3_DATA] DDR3DQ,
inout wire [7:0] DDR3DQS_N,
inout wire [7:0] DDR3DQS_P,
output wire [`DDR3_ADDR] DDR3ADDR,
output wire [2:0] DDR3BA,
output wire DDR3RAS_N,
output wire DDR3CAS_N,
output wire DDR3WE_N,
output wire DDR3RESET_N,
output wire [0:0] DDR3CK_P,
output wire [0:0] DDR3CK_N,
output wire [0:0] DDR3CKE,
output wire [0:0] DDR3CS_N,
output wire [7:0] DDR3DM,
output wire [0:0] DDR3ODT);
function [`APPADDR_WIDTH-1:0] mux;
input [`APPADDR_WIDTH-1:0] a;
input [`APPADDR_WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
// inputs of u_dram
reg [`APPADDR_WIDTH-1:0] app_addr;
reg [`DDR3_CMD] app_cmd;
reg app_en;
// reg [`APPDATA_WIDTH-1:0] app_wdf_data;
wire [`APPDATA_WIDTH-1:0] app_wdf_data = D_DIN;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
wire app_sr_req = 0; // no used
wire app_ref_req = 0; // no used
wire app_zq_req = 0; // no used
// outputs of u_dram
wire [`APPDATA_WIDTH-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire app_sr_active; // no used
wire app_ref_ack; // no used
wire app_zq_ack; // no used
wire ui_clk;
wire ui_clk_sync_rst;
wire init_calib_complete;
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
dram u_dram (
// Memory interface ports
.ddr3_addr (DDR3ADDR),
.ddr3_ba (DDR3BA),
.ddr3_cas_n (DDR3CAS_N),
.ddr3_ck_n (DDR3CK_N),
.ddr3_ck_p (DDR3CK_P),
.ddr3_cke (DDR3CKE),
.ddr3_ras_n (DDR3RAS_N),
.ddr3_reset_n (DDR3RESET_N),
.ddr3_we_n (DDR3WE_N),
.ddr3_dq (DDR3DQ),
.ddr3_dqs_n (DDR3DQS_N),
.ddr3_dqs_p (DDR3DQS_P),
.ddr3_cs_n (DDR3CS_N),
.ddr3_dm (DDR3DM),
.ddr3_odt (DDR3ODT),
.sys_clk_p (CLK_P),
.sys_clk_n (CLK_N),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.app_wdf_mask ({`APPMASK_WIDTH{1'b0}}),
.sys_rst (RST_X_IN)
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
reg [1:0] mode;
reg [31:0] remain, remain2;
reg rst_o;
always @(posedge ui_clk) rst_o <= (ui_clk_sync_rst || ~init_calib_complete); // High Active
assign USERCLK = ui_clk;
assign RST_O = rst_o;
assign D_BUSY = (mode != M_REQ); // DRAM busy
assign D_W = (mode == M_WRITE && app_rdy && app_wdf_rdy); // store one element
always @(posedge ui_clk) begin
if (RST_O) begin
mode <= M_REQ;
app_addr <= 0;
app_cmd <= 0;
app_en <= 0;
// app_wdf_data <= 0;
app_wdf_wren <= 0;
D_DOUT <= 0;
D_DOUTEN <= 0;
remain <= 0;
remain2 <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
case (D_REQ)
`DRAM_REQ_READ: begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
`DRAM_REQ_WRITE: begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
default: begin
app_wdf_wren <= 0;
app_en <= 0;
end
endcase
end
///////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain2 <= remain2 - 1;
if (remain2 == 1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
remain <= remain - 1;
if (remain == 1) mode <= M_REQ;
end
end
///////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= mux((app_addr+8), 0, (app_addr==`MEM_LAST_ADDR));
remain <= remain - 1;
if (remain == 1) begin
mode <= M_REQ;
app_en <= 0;
end
end else begin
app_wdf_wren <= 0;
end
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) ////////////////////////////////////////////
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; struct edge { long long int A; long long int B; }; bool edgecompare(edge lhs, edge rhs) { if (lhs.B != rhs.B) return lhs.B < rhs.B; else return lhs.A < rhs.A; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, m, i, j, k, flag = 0, a[100005]; string str; map<long long int, long long int> Map; set<long long int> Set; set<long long int, greater<long long int> >::iterator itr; cin >> n >> k; long long int ma = 0; i = 0; while (pow(2, i) <= n) { i++; } ma = pow(2, i) - 1; if (k == 1) cout << n; else cout << ma; return 0; }
|
//-------------------------------------------------------------------
//-- fsmtx_tb.v
//-- Banco de pruebas para la tranmision de datos
//-------------------------------------------------------------------
//-- BQ September 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module fsmtx2_tb();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tiempo entre caracteres
localparam DELAY = `F_8KHz;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
localparam FRAME = (BITRATE * 11);
//-- Tiempo entre dos bits enviados
localparam FRAME_WAIT = (BITRATE * 4);
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Instanciar el componente
fsmtx2 #(.BAUD(BAUD), .DELAY(DELAY))
dut(
.clk(clk),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("fsmtx2_tb.vcd");
$dumpvars(0, fsmtx2_tb);
#(FRAME_WAIT * 10) $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; string s = ; for (int i = 0; i < k; i++) s += char(i + 97); for (int i = 0; i < n - k; i++) { s += char(i % k + 97); } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int sa[100005], s1[100005]; char s[100005]; int save[6]; int main() { int n; while (scanf( %d , &n) != EOF) { for (int a = 1; a <= n; a++) scanf( %d , &sa[a]); scanf( %s , s + 1); int l = -1000000000, r = 1000000000; for (int a = 1; a <= n; a++) s1[a] = s[a] - 48; for (int a = 5; a <= n; a++) { for (int b = a - 4; b <= a; b++) save[b - (a - 5)] = sa[b]; sort(save + 1, save + 1 + 5); if (s1[a - 1] == 0 && s1[a - 2] == 0 && s1[a - 3] == 0 && s1[a - 4] == 0) { if (s1[a] == 1 && s1[a - 1] != 1) l = max(l, save[5] + 1); else { continue; } } else if (s1[a - 1] == 1 && s1[a - 2] == 1 && s1[a - 3] == 1 && s1[a - 4] == 1) { if (s1[a] == 0 && s1[a - 1] != 0) { r = min(r, save[1] - 1); } else continue; } else { continue; } } printf( %d %d n , l, r); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_TB_V
`define SKY130_FD_SC_HD__NAND3_TB_V
/**
* nand3: 3-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__nand3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_TB_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 1; const double pi = acos(-1); int dp[1001][2002][4]; int MOD = 998244353; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(20); int n, k; cin >> n >> k; dp[0][0][0] = 1; dp[0][0][1] = 1; dp[0][0][2] = 1; dp[0][0][3] = 1; for (int i = 1; i < n; ++i) { for (int j = 0; j <= k; ++j) { dp[i][j][0] = (dp[i][j][0] + dp[i - 1][j][0]) % MOD; dp[i][j][1] = (dp[i][j][1] + dp[i - 1][j][0]) % MOD; dp[i][j][2] = (dp[i][j][2] + dp[i - 1][j][0]) % MOD; dp[i][j + 1][3] = (dp[i][j + 1][3] + dp[i - 1][j][0]) % MOD; dp[i][j + 1][0] = (dp[i][j + 1][0] + dp[i - 1][j][1]) % MOD; dp[i][j][1] = (dp[i][j][1] + dp[i - 1][j][1]) % MOD; dp[i][j + 2][2] = (dp[i][j + 2][2] + dp[i - 1][j][1]) % MOD; dp[i][j + 1][3] = (dp[i][j + 1][3] + dp[i - 1][j][1]) % MOD; dp[i][j + 1][0] = (dp[i][j + 1][0] + dp[i - 1][j][2]) % MOD; dp[i][j + 2][1] = (dp[i][j + 2][1] + dp[i - 1][j][2]) % MOD; dp[i][j][2] = (dp[i][j][2] + dp[i - 1][j][2]) % MOD; dp[i][j + 1][3] = (dp[i][j + 1][3] + dp[i - 1][j][2]) % MOD; dp[i][j + 1][0] = (dp[i][j + 1][0] + dp[i - 1][j][3]) % MOD; dp[i][j][1] = (dp[i][j][1] + dp[i - 1][j][3]) % MOD; dp[i][j][2] = (dp[i][j][2] + dp[i - 1][j][3]) % MOD; dp[i][j][3] = (dp[i][j][3] + dp[i - 1][j][3]) % MOD; } } int ans = 0; ans = (ans + dp[n - 1][k - 1][0]) % MOD; if (k > 1) { ans = (ans + dp[n - 1][k - 2][1]) % MOD; ans = (ans + dp[n - 1][k - 2][2]) % MOD; } ans = (ans + dp[n - 1][k - 1][3]) % MOD; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool f(int a, string s) { vector<char> v; int tmp; int ss = (s.size() - 1); while (a) { tmp = a % 10; if (tmp == 7) v.push_back( 7 ); if (tmp == 4) v.push_back( 4 ); a /= 10; } if (v.size() != s.size()) return false; for (int i = 0; i < s.size(); i++) { if (s[i] != v[s.size() - i - 1]) return false; } return true; } int main() { int a; string s; cin >> a >> s; for (int i = (a + 1); i <= 100000000; i++) { if (f(i, s)) { cout << i << endl; return 0; } } }
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int n) { if (n <= 1) return false; for (int i = 2; i < n; i++) if (n % i == 0) return false; return true; } int odd(int arr[], int n) { for (int i = 0; i < n; i++) { if (arr[i] % 2 != 0) { return i; } } } int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } int sum = 0; for (int i = 0; i < n; i++) { sum += arr[i]; } int fodd = odd(arr, n); if (isPrime(sum)) { cout << n - 1 << endl; for (int i = 0; i < n; i++) { if (i == fodd) { continue; } cout << (i + 1) << ; } cout << endl; } if (!(isPrime(sum))) { cout << n << endl; for (int i = 0; i < n; i++) { cout << (i + 1) << ; } cout << endl; } } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:500000000 ) using namespace std; vector<int> A[2]; int main() { int n, i, j, t, w; cin >> n; for (i = 0; i < n; i++) { cin >> t >> w; A[t - 1].push_back(w); } for (i = 0; i < 2; i++) sort(A[i].begin(), A[i].end(), greater<int>()); int res = 0x3F3F3F3F; for (int x = -1; x < (int)A[0].size(); x++) { for (int y = -1; y < (int)A[1].size(); y++) { w = (x + 1) + 2 * (y + 1); int s = 0; for (i = x + 1; i < A[0].size(); i++) s += A[0][i]; for (i = y + 1; i < A[1].size(); i++) s += A[1][i]; if (s <= w) res = min(res, w); } } cout << res << endl; }
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Achronix eFPGA technology sim models. User must first simulate the generated \
// > netlist before going to test it on board/custom chip.
// > Changelog: 1) Removed unused VCC/GND modules
// > 2) Altera comments here (?). Removed.
// > 3) Reusing LUT sim model, removed wrong wires and parameters.
module PADIN (output padout, input padin);
assign padout = padin;
endmodule
module PADOUT (output padout, input padin, input oe);
assign padout = padin;
assign oe = oe;
endmodule
module LUT4 (output dout,
input din0, din1, din2, din3);
parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;
assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;
function lut_data;
input [15:0] mask;
input dataa, datab, datac, datad;
reg [7:0] s3;
reg [3:0] s2;
reg [1:0] s1;
begin
s3 = datad ? mask[15:8] : mask[7:0];
s2 = datac ? s3[7:4] : s3[3:0];
s1 = datab ? s2[3:2] : s2[1:0];
lut_data = dataa ? s1[1] : s1[0];
end
endfunction
always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule
module DFF (output q,
input d, ck);
reg q;
always @(posedge ck)
q <= d;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long n, m; long a[4], b[4], c[4]; int main() { cin >> n; for (int i = 1; i <= 3; i++) { cin >> a[i] >> b[i]; c[i] = a[i]; } m = a[1] + a[2] + a[3]; for (int i = 1; i <= 3; i++) { while (c[i] < b[i] && m < n) { c[i] += 1; m += 1; } } cout << c[1] << << c[2] << << c[3]; return 0; }
|
// vim: ts=4 sw=4 noexpandtab
/*
* Edge detection
*
* Copyright (c) 2019 Michael Buesch <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`ifndef EDGE_DETECT_MOD_V_
`define EDGE_DETECT_MOD_V_
module edge_detect #(
parameter NR_BITS = 1, /* Number of bits */
) (
input wire clk, /* Clock */
input wire [NR_BITS - 1 : 0] signal, /* Input signal */
output wire [NR_BITS - 1 : 0] rising, /* Rising edge detected on input signal */
output wire [NR_BITS - 1 : 0] falling, /* Falling edge detected on input signal */
);
reg [NR_BITS - 1 : 0] prev_signal;
always @(posedge clk) begin
prev_signal <= signal;
end
assign rising = ~prev_signal & signal;
assign falling = prev_signal & ~signal;
endmodule
`endif /* EDGE_DETECT_MOD_V_ */
|
/* wb_arbiter. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2013-2019 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
Wishbone arbiter, burst-compatible
Simple round-robin arbiter for multiple Wishbone masters
*/
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 0)
(
input wb_clk_i,
input wb_rst_i,
// Wishbone Master Interface
input [num_masters*aw-1:0] wbm_adr_i,
input [num_masters*dw-1:0] wbm_dat_i,
input [num_masters*4-1:0] wbm_sel_i,
input [num_masters-1:0] wbm_we_i,
input [num_masters-1:0] wbm_cyc_i,
input [num_masters-1:0] wbm_stb_i,
input [num_masters*3-1:0] wbm_cti_i,
input [num_masters*2-1:0] wbm_bte_i,
output [num_masters*dw-1:0] wbm_dat_o,
output [num_masters-1:0] wbm_ack_o,
output [num_masters-1:0] wbm_err_o,
output [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [dw-1:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [dw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
//ISim does not implement $clog2. Other tools have broken implementations
`ifdef BROKEN_CLOG2
function integer clog2;
input integer in;
begin
in = in - 1;
for (clog2 = 0; in > 0; clog2=clog2+1)
in = in >> 1;
end
endfunction
`define clog2 clog2
`else // !`ifdef BROKEN_CLOG2
`define clog2 $clog2
`endif
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire active;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select (master_sel),
.active (active));
/* verilator lint_off WIDTH */
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel];
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel];
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
/* verilator lint_on WIDTH */
endmodule // wb_arbiter
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long inf = LLONG_MAX; void IO() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cout.setf(ios::fixed); srand(chrono::high_resolution_clock::now().time_since_epoch().count()); } long long pw(long long x, long long y, long long p = inf) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long invmod(long long a, long long m) { return pw(a, m - 2, m); } long long cl(long long a, long long x) { return a % x == 0 ? a / x : a / x + 1; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } void run_time_terror() { long long n; cin >> n; cout << ? 1 3 << endl; long long a, b; cin >> a; vector<long long> ans(n); cout << ? 2 3 << endl; cin >> b; ans[0] = a - b; for (long long i = 0; i < n - 1; ++i) { long long x; if (i == 1) { x = b; } else { cout << ? << i + 1 << << i + 2 << endl; cin >> x; } ans[i + 1] = x - ans[i]; } cout << ! ; for (long long i = 0; i < n; ++i) { cout << ans[i] << ; } } int32_t main() { cout << setprecision(0); long long tt = 1; for (long long case_no = 1; case_no <= tt; case_no++) { run_time_terror(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int oo = 1 << 30; const double PI = M_PI; const double EPS = 1e-15; double w, h, u; double cross(const complex<double> &a, const complex<double> &b) { return imag(conj(a) * b); } complex<double> rotate_by(const complex<double> &p, const complex<double> &about, double radians) { return (p - about) * exp(complex<double>(0, radians)) + about; } complex<double> intersect(const complex<double> &a, const complex<double> &b, const complex<double> &p, const complex<double> &q) { double d1 = cross(p - a, b - a); double d2 = cross(q - a, b - a); return (d1 * q - d2 * p) / (d1 - d2); } int main() { cin.sync_with_stdio(false); cin >> w >> h >> u; if (w < h) swap(w, h); if (u > 90) u = 180 - u; u = u * M_PI / 180.; cout.precision(10); if (u == 0) { cout << fixed << w * h << endl; return 0; } if (u >= (M_PI - 2. * atan(w / (double)h))) { cout << fixed << h * h / sin(u) << endl; } else { double answer = w * h; complex<double> a1 = rotate_by(complex<double>(+w / 2., -h / 2), complex<double>(0, 0), u); complex<double> a2 = rotate_by(complex<double>(+w / 2., +h / 2), complex<double>(0, 0), u); complex<double> a3 = rotate_by(complex<double>(-w / 2., +h / 2), complex<double>(0, 0), u); complex<double> b1 = intersect(a1, a2, complex<double>(-w / 2., h / 2.), complex<double>(w / 2., h / 2.)); complex<double> b2 = intersect(a2, a3, complex<double>(-w / 2., h / 2.), complex<double>(w / 2., h / 2.)); { double side1 = b1.real() - b2.real(); double side2 = side1 * cos(u); double area = side1 * side2 * sin(u); answer = answer - area; } { double side1 = w / 2. - b1.real(); double side2 = side1 * tan(M_PI / 2. - u); double area = side1 * side2; answer = answer - area; } cout << fixed << answer << endl; } return 0; }
|
`include "timescale.v"
`include "defines.v"
module clk_rst(
clk_sys_o,
clk_adc_o,
clk_adc2x_o,
clk_100mhz_o,
clk_200mhz_o,
rstn_o
);
// Defaults parameters
parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;
parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;
parameter CLK_ADC_2X_PERIOD = `CLK_ADC_2X_PERIOD;
localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;
localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;
// Output Clocks
output reg
clk_sys_o,
clk_adc_o,
clk_adc2x_o,
clk_100mhz_o,
clk_200mhz_o;
// Output Reset
output reg rstn_o;
// Reset generate
initial
begin
clk_sys_o = 0;
clk_adc_o = 0;
clk_adc2x_o = 0;
clk_100mhz_o = 0;
clk_200mhz_o = 0;
rstn_o = 0;
#(`RST_SYS_DELAY)
rstn_o = 1;
end
// Clock Generation
always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o;
always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;
always #(CLK_ADC_2X_PERIOD/2) clk_adc2x_o <= ~clk_adc2x_o;
always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;
always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;
endmodule
|
#include <bits/stdc++.h> using std::abs; using std::bitset; using std::cerr; using std::cin; using std::copy; using std::cout; using std::endl; using std::fill; using std::fixed; using std::greater; using std::lower_bound; using std::map; using std::max; using std::min; using std::next_permutation; using std::pair; using std::priority_queue; using std::queue; using std::reverse; using std::rotate; using std::set; using std::sort; using std::string; using std::swap; using std::unique; using std::unordered_map; using std::unordered_set; using std::upper_bound; using std::vector; int const INF = (int)1e9; long long const INFL = (long long)1e18; long double const PI = 3.1415926535897932384626433832795028; bool isPrime(int x) { for (int a = 2; a * a <= x; ++a) { if (x % a == 0) { return false; } } return true; } int const N = 100100; int len[N]; int g[N], next[N]; int find(int v) { if (next[v] != v) { int root = find(next[v]); len[v] += len[next[v]]; next[v] = root; } return next[v]; } int v[N], res[N]; bool did[N]; int calc(int a, int b) { int ret = 0; find(a); b -= len[a]; a = next[a]; while (b > 0 && !did[a]) { ++ret; did[a] = true; next[a] = find(g[a]); len[a] = 1 + len[g[a]]; b -= len[a]; a = find(g[a]); } return ret; } void solve() { int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) { next[i] = i; len[i] = 0; cin >> g[i]; --g[i]; } for (int i = 1; i <= m; ++i) { cin >> v[i]; } for (int i = 1; i <= m; ++i) { int b; cin >> b; int a = (v[i] + res[i - 1] - 1) % n; res[i] = calc(a, b); } for (int i = 1; i <= m; ++i) { cout << res[i] << n ; } } int main() { solve(); }
|
#include <bits/stdc++.h> using namespace std; double ans = 0.0000; void bfs(); list<int> arr[100005]; int visited[100005], dep[100005]; int main() { int n, i, start, end; cin >> n; n--; while (n--) { cin >> start; cin >> end; arr[start].push_back(end); arr[end].push_back(start); } bfs(); cout.precision(7); cout << fixed << ans; return 0; } void bfs() { int node; dep[1] = 1; queue<int> qu; list<int>::iterator iter = arr[1].begin(); node = 1; visited[1] = 1; qu.push(1); while (!qu.empty()) { for (iter = arr[node].begin(); iter != arr[node].end(); ++iter) { if (!visited[*iter]) { qu.push(*iter); visited[*iter] = 1; dep[*iter] = dep[node] + 1; } } int k = qu.front(); qu.pop(); node = qu.front(); ans += 1 / (double)dep[k]; } }
|
// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module SerialTX(clk, TxD_start, TxD_data, TxD, TxD_busy);
input clk, TxD_start;
input [7:0] TxD_data;
output TxD, TxD_busy;
parameter ClkFrequency = 16000000; // 64MHz
parameter Baud = 115200;
parameter RegisterInputData = 1; // in RegisterInputData mode, the input doesn't have to stay valid while the character is been transmitted
// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_dataReg = 0;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <= TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;
always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase
// Output mux
reg muxbit;
always @( * )
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase
// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,sse3,sse4,popcnt,abm,mmx ) using namespace std; const double eps = 0.000001; const long double pi = acos(-1); const int maxn = 1e7 + 9; const int mod = 1e9 + 7; const long long MOD = 1e18 + 9; const long long INF = 1e18 + 123; const int inf = 2e9 + 11; const int mxn = 1e6 + 9; const int N = 3e5 + 123; const int PRI = 555557; const int pri = 997; int tests = 1; int n, m, q; int sz[N], pr[N], ans[N]; bool u[N]; vector<int> g[N]; void dfs(int v, int p = 1) { sz[v] = 1; pr[v] = p; for (int to : g[v]) { if (to == p) continue; dfs(to, v); sz[v] += sz[to]; } } void dfs_center(int v) { u[v] = 1; if (sz[v] == 1) { ans[v] = v; return; } int mx = g[v].back(); for (int to : g[v]) { if (u[to]) continue; dfs_center(to); if (sz[mx] < sz[to]) { mx = to; } } int c = ans[mx]; while (sz[v] > sz[c] * 2) { c = pr[c]; } ans[v] = c; } inline void Solve() { cin >> n >> q; for (int i = 2; i <= n; i++) { int x; cin >> x; g[x].push_back(i); } dfs(1); dfs_center(1); while (q--) { int x; cin >> x; cout << ans[x] << n ; } } int main() { ios_base::sync_with_stdio(0), cin.tie(0); while (tests--) { Solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int segtree[4 * ((24 * 3600) + 100)], lazy[4 * ((24 * 3600) + 100)]; void propagate(int root, int l, int r) { segtree[root] += lazy[root]; if (l != r) { lazy[2 * root + 1] += lazy[root]; lazy[2 * root + 2] += lazy[root]; } lazy[root] = 0; } int query(int root, int l, int r, int a, int b) { if (b < l || r < a) return 0; propagate(root, l, r); if (a <= l && r <= b) return segtree[root]; int mid = (l + r) / 2; return max(query(2 * root + 1, l, mid, a, b), query(2 * root + 2, mid + 1, r, a, b)); } void update(int root, int l, int r, int a, int b, int val) { if (b < l || r < a) return; if (a <= l && r <= b) { lazy[root] += val; return; } int mid = (l + r) / 2; update(2 * root + 1, l, mid, a, b, val); update(2 * root + 2, mid + 1, r, a, b, val); propagate(2 * root + 1, l, mid); propagate(2 * root + 2, mid + 1, r); segtree[root] = max(segtree[2 * root + 1], segtree[2 * root + 2]); } int n, M, T, h, m, s; int main() { scanf( %d %d %d , &n, &M, &T); vector<int> resp; int user = 0; int ult = -1; for (int i = 0; i < n; i++) { scanf( %d:%d:%d , &h, &m, &s); int ini = h * 3600 + m * 60 + s; int fim = ini + T - 1; int val = query(0, 0, ((24 * 3600) + 100), ini, fim); if (val < M) { user++; resp.push_back(user); update(0, 0, ((24 * 3600) + 100), ini, fim, 1); } else { update(0, 0, ((24 * 3600) + 100), max(ult + 1, ini), fim, 1); resp.push_back(user); } ult = fim; } if (query(0, 0, ((24 * 3600) + 100), 0, ((24 * 3600) + 100)) != M) printf( No solution n ); else { printf( %d n , user); for (int i = 0; i < resp.size(); i++) { printf( %d n , resp[i]); } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[1000006], BLOCK; long long ans[200005], answer = 0; int asdf[1000006]; struct Node { int L, R, ind; } q[200005]; bool cmp(Node x, Node y) { if (x.L / BLOCK != y.L / BLOCK) return x.L / BLOCK < y.L / BLOCK; else return x.R < y.R; } void add(int pos) { answer -= 1ll * asdf[a[pos]] * asdf[a[pos]] * a[pos]; asdf[a[pos]]++; answer += 1ll * asdf[a[pos]] * asdf[a[pos]] * a[pos]; } void remove(int pos) { answer -= 1ll * asdf[a[pos]] * asdf[a[pos]] * a[pos]; asdf[a[pos]]--; answer += 1ll * asdf[a[pos]] * asdf[a[pos]] * a[pos]; } int main() { int n, t; cin >> n >> t; BLOCK = sqrt(n); for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= t; i++) { q[i].ind = i; cin >> q[i].L >> q[i].R; } sort(q + 1, q + t + 1, cmp); int curL = 0, curR = 0; for (int i = 1; i <= t; i++) { while (curL < q[i].L) { remove(curL); curL++; } while (curL > q[i].L) { add(curL - 1); curL--; } while (curR > q[i].R + 1) { remove(curR - 1); curR--; } while (curR <= q[i].R) { add(curR); curR++; } ans[q[i].ind] = answer; } for (int i = 1; i <= t; i++) cout << ans[i] << n ; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, size_t N> long long SIZE(const T (&t)[N]) { return N; } template <typename T> long long SIZE(const T &t) { return t.size(); } string to_string(const string s, long long x1 = 0, long long x2 = 1e9) { return + ((x1 < s.size()) ? s.substr(x1, x2 - x1 + 1) : ) + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(const bool b) { return (b ? true : false ); } string to_string(const char c) { return string({c}); } template <size_t N> string to_string(const bitset<N> &b, long long x1 = 0, long long x2 = 1e9) { string t = ; for (long long __iii__ = min(x1, SIZE(b)), __jjj__ = min(x2, SIZE(b) - 1); __iii__ <= __jjj__; ++__iii__) { t += b[__iii__] + 0 ; } return + t + ; } template <typename A, typename... C> string to_string(const A(&v), long long x1 = 0, long long x2 = 1e9, C... coords); long long l_v_l_v_l = 0, t_a_b_s = 0; template <typename A, typename B> string to_string(const pair<A, B> &p) { l_v_l_v_l++; string res = ( + to_string(p.first) + , + to_string(p.second) + ) ; l_v_l_v_l--; return res; } template <typename A, typename... C> string to_string(const A(&v), long long x1, long long x2, C... coords) { long long rnk = rank<A>::value; string tab(t_a_b_s, ); string res = ; bool first = true; if (l_v_l_v_l == 0) res += n ; res += tab + [ ; x1 = min(x1, SIZE(v)), x2 = min(x2, SIZE(v)); auto l = begin(v); advance(l, x1); auto r = l; advance(r, (x2 - x1) + (x2 < SIZE(v))); for (auto e = l; e != r; e = next(e)) { if (!first) { res += , ; } first = false; l_v_l_v_l++; if (e != l) { if (rnk > 1) { res += n ; t_a_b_s = l_v_l_v_l; }; } else { t_a_b_s = 0; } res += to_string(*e, coords...); l_v_l_v_l--; } res += ] ; if (l_v_l_v_l == 0) res += n ; return res; } void dbgm() { ; } template <typename Heads, typename... Tails> void dbgm(Heads H, Tails... T) { cerr << to_string(H) << | ; dbgm(T...); } void FIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long long N = 2e5 + 6; int32_t main() { FIO(); long long tc; cin >> tc; while (tc--) { long long x, y; cin >> x >> y; long long n = x; if (x == y) n = x; else if (x > y) { n = x * y + y; } else { long long r = y % x; n = y - r / 2; } assert(n <= (long long)2e18 and (n % x == y % n)); cout << n << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int cost[2005]; bool have[2005][3]; int dp[2003][10]; int solve(int i, int vits) { if (i >= n) { if (vits == 7) return 0; return 1e9; } int &ret = dp[i][vits]; if (ret + 1) return ret; int sol1 = 0, sol2 = 0; sol1 = solve(i + 1, vits); sol2 = cost[i] + solve(i + 1, vits | (have[i][0] | (2 * have[i][1]) | (4 * have[i][2]))); return ret = min(sol1, sol2); } int main() { ios_base::sync_with_stdio(false); memset(dp, -1, sizeof(dp)); cin >> n; for (int i = 0; i < n; i++) { cin >> cost[i]; string s; cin >> s; for (auto x : s) { if (x == A ) have[i][0] = true; if (x == B ) have[i][1] = true; if (x == C ) have[i][2] = true; } } int res = solve(0, 0); if (res > 7e8) res = -1; cout << res << n ; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Oct 23 16:54:16 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver2006.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.1 2006/10/30 15:38:11 wig Exp $
// $Date: 2006/10/30 15:38:11 $
// $Log: inst_a_e.v,v $
// Revision 1.1 2006/10/30 15:38:11 wig
// Updated testcase bitsplice/rfe20060904a and added some bug testcases.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.96 2006/10/23 08:31:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No user `defines in this module
module inst_a_e
//
// Generated Module inst_a
//
(
only_low // Only ::low defined
);
// Generated Module Outputs:
output only_low;
// Generated Wires:
wire only_low;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int dp[141][141][12]; int peas[141][141]; char track[141][141][12]; int main() { int n, m, k; cin >> n >> m >> k; string str; for (int i = 0; i < 141; i++) for (int j = 0; j < 141; j++) for (int p = 0; p < 12; p++) dp[i][j][p] = -111111111; for (int i = 0; i < n; i++) { cin >> str; for (int j = 0; j < m; j++) { peas[n - i][j + 1] = str[j] - 0 ; } } for (int j = 1; j <= m; j++) dp[1][j][peas[1][j] % (k + 1)] = peas[1][j]; for (int i = 2; i <= n; i++) for (int j = 1; j <= m; j++) for (int r = 0; r < k + 1; r++) { int pr = (r - peas[i][j] + 1000 * k + 1000) % (k + 1); dp[i][j][r] = max(dp[i - 1][j - 1][pr], dp[i - 1][j + 1][pr]) + peas[i][j]; track[i][j][r] = (dp[i - 1][j - 1][pr] > dp[i - 1][j + 1][pr]) ? R : L ; } int sol = -1, idx = 0; for (int j = 1; j <= m; j++) { if (sol < dp[n][j][0]) { sol = dp[n][j][0]; idx = j; } } if (sol < 0) { cout << -1 << endl; return 0; } int starting = 0; string ans = ; int rem = 0; for (int i = n; i >= 1; i--) { if (i == 1) break; if (track[i][idx][rem] == R ) { rem = (rem + 1000 * k + 1000 - peas[i][idx]) % (k + 1); idx = idx - 1; ans += R ; } else { rem = (rem + 1000 * k + 1000 - peas[i][idx]) % (k + 1); idx = idx + 1; ans += L ; } } cout << sol << endl; cout << idx << endl; reverse(ans.begin(), ans.end()); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[3003]; int main() { int n, inv = 0; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) if (a[i] > a[j]) ++inv; if (inv % 2 == 0) cout << fixed << setprecision(6) << 2.0 * inv << endl; else cout << fixed << setprecision(6) << 2.0 * inv - 1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { string s; cin >> s; int n = s.length(); if (n < 3) { cout << 0 << endl; continue; } if (n == 3) { if (s == 101 || s == 010 ) cout << 1 << endl; else cout << 0 << endl; continue; } long long int zero = 0, one = 0; for (long long int i = 0; i < n; i++) { if (s[i] == 1 ) one++; else zero++; } if (one == n || zero == n) { cout << 0 << endl; continue; } long long int done = 0, dzero = 0; long long int min1 = INT_MAX, min2 = INT_MAX; for (long long int i = 0; i < n; i++) { if (s[i] == 1 ) done++; else dzero++; min1 = min(min1, (dzero + one - done)); min2 = min(min2, (done + zero - dzero)); } cout << min(min1, min2) << endl; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:36 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_0_0 -prefix
// system_ov7670_controller_0_0_ system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
#include <bits/stdc++.h> using namespace std; void my_functions() { return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } string s; cin >> s; long long int b[n], i; b[0] = a[0]; for (i = 1; i < n; i++) { b[i] = a[i] + b[i - 1]; } long long int m1 = 0, m2 = 0; for (i = 0; i < n; i++) { if (s[i] == 1 ) { m1 = a[i] + m1; if (i > 0) { m2 = b[i - 1]; } m1 = max(m1, m2); } } long long int ans = max(m1, m2); cout << ans; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of m0
//
// Generated
// by: wig
// on: Tue Apr 1 13:31:51 2008
// cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: m0.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: m0.v,v $
// Revision 1.1 2008/04/01 12:53:30 wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of m0
//
// No user `defines in this module
module m0
//
// Generated Module M0
//
(
output reg clk_o,
output reg data_o,
input wire ready0_i,
input wire ready1_i,
output reg clk2_o,
output reg data2_o,
input wire ready2_0,
input wire ready2_1
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of m0
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int const maxn = 60, maxl = 10010; int f[maxn * maxl]; int n, d, c, sum; int main() { cin >> n >> d; f[0] = 1; for (int i = 0; i < n; i++) { cin >> c; for (int j = sum; j >= 0; j--) if (f[j]) f[j + c] = 1; sum += c; } int last = 0, t = 0; while (true) { int cur = last; for (int i = d; i > 0; i--) { if (f[last + i]) { cur = last + i; break; } } if (cur == last) { cout << last << << t << endl; break; } last = cur; t++; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_TB_V
`define SKY130_FD_SC_LP__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_TB_V
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#include <bits/stdc++.h> using namespace std; const int N = 200010; long long a[N], f[N]; int main() { long long o, t, n = 1; long long s = 0; scanf( %I64d , &o); while (o--) { scanf( %I64d , &t); if (t == 2) { n++; scanf( %I64d , &a[n]); f[n] = 0; s += a[n]; } else if (t == 1) { long long cnt, x; scanf( %I64d%I64d , &cnt, &x); f[cnt] += x; s += cnt * x; } else if (t == 3) { s -= (f[n] + a[n]); f[n - 1] += f[n]; f[n] = 0; n--; } printf( %.9lf n , s * 1.0 / n); } }
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