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`define bsg_tiehi_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_TIEHBWP_b``bits tiehi (.o); \
end
module bsg_tiehi #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
)
(output [width_p-1:0] o
);
`bsg_tiehi_macro(34) else
`bsg_tiehi_macro(33) else
`bsg_tiehi_macro(32) else
`bsg_tiehi_macro(31) else
`bsg_tiehi_macro(30) else
`bsg_tiehi_macro(29) else
`bsg_tiehi_macro(28) else
`bsg_tiehi_macro(27) else
`bsg_tiehi_macro(26) else
`bsg_tiehi_macro(25) else
`bsg_tiehi_macro(24) else
`bsg_tiehi_macro(23) else
`bsg_tiehi_macro(22) else
`bsg_tiehi_macro(21) else
`bsg_tiehi_macro(20) else
`bsg_tiehi_macro(19) else
`bsg_tiehi_macro(18) else
`bsg_tiehi_macro(17) else
`bsg_tiehi_macro(16) else
`bsg_tiehi_macro(15) else
`bsg_tiehi_macro(14) else
`bsg_tiehi_macro(13) else
`bsg_tiehi_macro(12) else
`bsg_tiehi_macro(11) else
`bsg_tiehi_macro(10) else
`bsg_tiehi_macro(9) else
`bsg_tiehi_macro(8) else
`bsg_tiehi_macro(7) else
`bsg_tiehi_macro(6) else
`bsg_tiehi_macro(5) else
`bsg_tiehi_macro(4) else
`bsg_tiehi_macro(3) else
`bsg_tiehi_macro(2) else
`bsg_tiehi_macro(1) else
begin :notmacro
assign o = { width_p {1'b1} };
// synopsys translate_off
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
// synopsys translate_on
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_tiehi)
|
/* sigma-delta modulator test */
module sdm
(
input clk, //bus clock
input [14:0] ldatasum, // left channel data
input [14:0] rdatasum, // right channel data
output reg left=0, //left bitstream output
output reg right=0 //right bitsteam output
);
//--------------------------------------------------------------------------------------
// local signals
localparam DW = 15;
localparam CW = 2;
localparam RW = 4;
localparam A1W = 2;
localparam A2W = 5;
wire [DW+2+0 -1:0] sd_l_er0, sd_r_er0;
reg [DW+2+0 -1:0] sd_l_er0_prev=0, sd_r_er0_prev=0;
wire [DW+A1W+2-1:0] sd_l_aca1, sd_r_aca1;
wire [DW+A2W+2-1:0] sd_l_aca2, sd_r_aca2;
reg [DW+A1W+2-1:0] sd_l_ac1=0, sd_r_ac1=0;
reg [DW+A2W+2-1:0] sd_l_ac2=0, sd_r_ac2=0;
wire [DW+A2W+3-1:0] sd_l_quant, sd_r_quant;
// LPF noise LFSR
reg [24-1:0] seed1 = 24'h654321;
reg [19-1:0] seed2 = 19'h12345;
reg [24-1:0] seed_sum=0, seed_prev=0, seed_out=0;
always @ (posedge clk) begin
if (&seed1)
seed1 <= #1 24'h654321;
else
seed1 <= #1 {seed1[22:0], ~(seed1[23] ^ seed1[22] ^ seed1[21] ^ seed1[16])};
end
always @ (posedge clk) begin
if (&seed2)
seed2 <= #1 19'h12345;
else
seed2 <= #1 {seed2[17:0], ~(seed2[18] ^ seed2[17] ^ seed2[16] ^ seed2[13] ^ seed2[0])};
end
always @ (posedge clk) begin
seed_sum <= #1 seed1 + {5'b0, seed2};
seed_prev <= #1 seed_sum;
seed_out <= #1 seed_sum - seed_prev;
end
// linear interpolate
localparam ID=4; // counter size, also 2^ID = interpolation rate
reg [ID+0-1:0] int_cnt = 0;
always @ (posedge clk) int_cnt <= #1 int_cnt + 'd1;
reg [DW+0-1:0] ldata_cur=0, ldata_prev=0;
reg [DW+0-1:0] rdata_cur=0, rdata_prev=0;
wire [DW+1-1:0] ldata_step, rdata_step;
reg [DW+ID-1:0] ldata_int=0, rdata_int=0;
wire [DW+0-1:0] ldata_int_out, rdata_int_out;
assign ldata_step = {ldata_cur[DW-1], ldata_cur} - {ldata_prev[DW-1], ldata_prev}; // signed subtract
assign rdata_step = {rdata_cur[DW-1], rdata_cur} - {rdata_prev[DW-1], rdata_prev}; // signed subtract
always @ (posedge clk) begin
if (~|int_cnt) begin
ldata_prev <= #1 ldata_cur;
ldata_cur <= #1 ldatasum; //{~ldatasum[DW-1], ldatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
rdata_prev <= #1 rdata_cur;
rdata_cur <= #1 rdatasum; //{~rdatasum[DW-1], rdatasum[DW-2:0]}; // convert to offset binary, samples no longer signed!
ldata_int <= #1 {ldata_cur[DW-1], ldata_cur, {ID{1'b0}}};
rdata_int <= #1 {rdata_cur[DW-1], rdata_cur, {ID{1'b0}}};
end else begin
ldata_int <= #1 ldata_int + {{ID{ldata_step[DW+1-1]}}, ldata_step};
rdata_int <= #1 rdata_int + {{ID{rdata_step[DW+1-1]}}, rdata_step};
end
end
assign ldata_int_out = ldata_int[DW+ID-1:ID];
assign rdata_int_out = rdata_int[DW+ID-1:ID];
// input gain x3
wire [DW+2-1:0] ldata_gain, rdata_gain;
assign ldata_gain = {ldata_int_out[DW-1], ldata_int_out, 1'b0} + {{(2){ldata_int_out[DW-1]}}, ldata_int_out};
assign rdata_gain = {rdata_int_out[DW-1], rdata_int_out, 1'b0} + {{(2){rdata_int_out[DW-1]}}, rdata_int_out};
/*
// random dither to 15 bits
reg [DW-1:0] ldata=0, rdata=0;
always @ (posedge clk) begin
ldata <= #1 ldata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
rdata <= #1 rdata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 );
end
*/
// accumulator adders
assign sd_l_aca1 = {{(A1W){ldata_gain[DW+2-1]}}, ldata_gain} - {{(A1W){sd_l_er0[DW+2-1]}}, sd_l_er0} + sd_l_ac1;
assign sd_r_aca1 = {{(A1W){rdata_gain[DW+2-1]}}, rdata_gain} - {{(A1W){sd_r_er0[DW+2-1]}}, sd_r_er0} + sd_r_ac1;
assign sd_l_aca2 = {{(A2W-A1W){sd_l_aca1[DW+A1W+2-1]}}, sd_l_aca1} - {{(A2W){sd_l_er0[DW+2-1]}}, sd_l_er0} - {{(A2W+1){sd_l_er0_prev[DW+2-1]}}, sd_l_er0_prev[DW+2-1:1]} + sd_l_ac2;
assign sd_r_aca2 = {{(A2W-A1W){sd_r_aca1[DW+A1W+2-1]}}, sd_r_aca1} - {{(A2W){sd_r_er0[DW+2-1]}}, sd_r_er0} - {{(A2W+1){sd_r_er0_prev[DW+2-1]}}, sd_r_er0_prev[DW+2-1:1]} + sd_r_ac2;
// accumulators
always @ (posedge clk) begin
sd_l_ac1 <= #1 sd_l_aca1;
sd_r_ac1 <= #1 sd_r_aca1;
sd_l_ac2 <= #1 sd_l_aca2;
sd_r_ac2 <= #1 sd_r_aca2;
end
// value for quantizaton
assign sd_l_quant = {sd_l_ac2[DW+A2W+2-1], sd_l_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
assign sd_r_quant = {sd_r_ac2[DW+A2W+2-1], sd_r_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]};
// error feedback
assign sd_l_er0 = sd_l_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
assign sd_r_er0 = sd_r_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}};
always @ (posedge clk) begin
sd_l_er0_prev <= #1 (&sd_l_er0) ? sd_l_er0 : sd_l_er0+1;
sd_r_er0_prev <= #1 (&sd_r_er0) ? sd_r_er0 : sd_r_er0+1;
end
// output
always @ (posedge clk) begin
left <= #1 (~|ldata_gain) ? ~left : ~sd_l_er0[DW+2-1];
right <= #1 (~|rdata_gain) ? ~right : ~sd_r_er0[DW+2-1];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t, x, c, d, ch = 0, caser = 0, lol = 0, sum = 0, rating = -1, upper = 1e9, lower = -1e9; cin >> n; for (int i = 0; i < n; i++) { cin >> c >> d; if (i == 0) { if (d == 1) lower = 1900; else upper = 1899; } else { if (d == 2) { upper = min(upper, sum + 1899); } else { lower = max(lower, sum + 1900); } } sum -= c; } if (upper == 1e9) cout << Infinity n ; else if (lower > upper) cout << Impossible n ; else cout << upper - sum << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int th = 0; for (int i = 1; i < n; i++) { th += i; th %= n; cout << (th + 1) << ; } return 0; }
|
module riscv_fid (
clk,
resetn,
//Instruction bif
instr_bif_addr,
instr_bif_rdata,
instr_bif_req,
instr_bif_ack,
//bypass
wdata_bypass,
//STall
stall_back,
//RF write channel
rf_wdata,
rf_wr_req,
rf_wr_ack
);
reg [31:0] pc;
assign instr_bif_addr = pc;
always @ (*) begin
if (stalled) begin
pc_nxt = pc;
end
else if (branch_taken) begin
pc_nxt = target;
end
else begin
pc_nxt = pc + 4;
end
end
assign br_immed_b_muxed = (br_sel_b == `SEL_REG) ? rsk_val : br_immed_b;
assign target = br_immed_a + br_immed_b_muxed;
case (br_funct)
BR_BNE :
BR_BEQ :
BR_BLT :
BR_BLTU :
BR_BGE :
BR_BGEU :
BR_JUMP :
default :
module instr_decoder (
input [31:0] instr,
input [31:0] pc_in ,
output use_rsj ,
output use_rsk ,
output use_rsd ,
output [1:0] rsd_lockout ,
output [`ALU_FUNCT_W-1:0] alu_funct ,
output alu_sel_a ,
output alu_sel_b ,
output [31:0] alu_immed_a ,
output [31:0] alu_immed_b ,
output [`BR_FUNCT_W-1:0] br_funct ,
output br_sel_a ,
output [31:0] br_immed_a ,
output [31:0] br_immed_b ,
output [`MEM_FUNCT_W-1:0] mem_funct
);
|
#include <bits/stdc++.h> using namespace std; int main() { int n, b, d; int a[100000 + 10]; cin >> n >> b >> d; for (int i = 0; i < n; i++) cin >> a[i]; int p = 0, emp = 0; int temp = 0; for (int i = 0; i < n; i++) { if (a[i] > b) continue; temp += a[i]; if (temp > d) { emp++; temp = 0; } } cout << emp; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int a[N]; int main() { int i, j, k = 0, n; cin >> n; long long s = 0, t; for (i = 1; i <= n; i++) { cin >> a[i]; s += a[i]; } if (s % 2 == 1) { cout << 0 n ; return 0; } t = 0; for (i = 1; i < n; i++) { s -= a[i]; t += a[i]; if (s == t) k++; } cout << k << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=next_pc+32'd4;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg [2*32-1:0] w2; initial w2 = {2 {32'h12345678}};
reg [9*32-1:0] w9; initial w9 = {9 {32'h12345678}};
reg [10*32-1:0] w10; initial w10 = {10{32'h12345678}};
reg [11*32-1:0] w11; initial w11 = {11{32'h12345678}};
reg [15*32-1:0] w15; initial w15 = {15{32'h12345678}};
reg [31*32-1:0] w31; initial w31 = {31{32'h12345678}};
reg [47*32-1:0] w47; initial w47 = {47{32'h12345678}};
reg [63*32-1:0] w63; initial w63 = {63{32'h12345678}};
// Aggregate outputs into a single result vector
wire [63:0] result = (w2[63:0]
^ w9[64:1]
^ w10[65:2]
^ w11[66:3]
^ w15[67:4]
^ w31[68:5]
^ w47[69:6]
^ w63[70:7]);
// What checksum will we end up with
`define EXPECTED_SUM 64'h184cb39122d8c6e3
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w2 <= w2 >> 1;
w9 <= w9 >> 1;
w10 <= w10 >> 1;
w11 <= w11 >> 1;
w15 <= w15 >> 1;
w31 <= w31 >> 1;
w47 <= w47 >> 1;
w63 <= w63 >> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, id = 0; int Hash[333], L[333]; map<string, int> M; vector<int> v; int kmp(int Len) { int len = v.size(); int lps[len], I = 0, num = 0; lps[0] = 0; for (int i = 1; i < len; i++) { if (v[I] != v[i]) I = -1; lps[i] = ++I; } int i = 0, j = 0; while (i < n) { if (Hash[i] == v[j]) { i++; j++; } else { if (j == 0) i++; else { if (j == lps[j]) j = 0; else j = lps[j - 1]; } } if (j == len) { num++; j = 0; } } if (num == 1) num = 0; return (Len - 1) * num; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s; int Len = 0, res = 0, len; cin >> n; for (int i = 0; i < n; i++) { cin >> s; if (!M[s]) { M[s] = ++id; } Hash[i] = M[s]; L[i] = s.length(); Len += L[i]; } Len += (n - 1); for (int i = 0; i < n; i++) { v.clear(); len = 0; for (int j = i; j < n; j++) { v.push_back(Hash[j]); len += L[j]; res = max(res, kmp(len)); } } cout << Len - res << endl; return 0; }
|
#include <bits/stdc++.h> int main() { int n, s, i, a, b, t, j, v, f, c; int candy = -1, d; scanf( %d%d , &n, &s); s = s * 100; while (n--) { scanf( %d%d , &a, &b); d = (a * 100) + b; if (d <= s) { f = s - d; c = f % 100; if (c > candy) candy = c; } } if (c != -1) printf( %d , candy); else printf( -1 ); }
|
#include <bits/stdc++.h> using namespace std; const long long N = 200005; int main() { long long n, z, x, y; cin >> n; z = (n * (n - 1) * (n - 2) * (n - 3) * (n - 4)) / 120; x = (z * (n - 5)) / 6; y = (x * (n - 6)) / 7; cout << z + x + y << n ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O22AI_PP_BLACKBOX_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_PP_BLACKBOX_V
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_divSqrtRecFN_small_div#(
parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
localparam maxNumCyclesToDelay = sigWidth + 10;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount, moreIn, queueCount;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg nReset, clock;
initial begin
clock = 1;
forever #5 clock = !clock;
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg inValid;
wire inReady;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg integer delay;
always @(negedge nReset, posedge clock) begin
if (!nReset) begin
delay <= 0;
end else begin
delay <=
inValid && inReady ? {$random} % maxNumCyclesToDelay
: delay ? delay - 1 : 0;
end
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, b, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA, recB;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
fNToRecFN#(expWidth, sigWidth) fNToRecFN_b(b, recB);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [formatWidth:0] queue_recA[1:5], queue_recB[1:5];
reg [(formatWidth - 1):0] queue_expectOut[1:5];
reg [4:0] queue_expectExceptionFlags[1:5];
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'divSqrtRecF%0d_small_div'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
moreIn = 1;
queueCount = 0;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
inValid = 0;
nReset = 0;
#21;
nReset = 1;
while (
$fscanf(
'h80000000,
"%h %h %h %h",
a,
b,
expectOut,
expectExceptionFlags
) == 4
) begin
while (delay != 0) #10;
inValid = 1;
while (!inReady) #10;
#10;
inValid = 0;
queueCount = queueCount + 1;
queue_recA[5] = queue_recA[4];
queue_recA[4] = queue_recA[3];
queue_recA[3] = queue_recA[2];
queue_recA[2] = queue_recA[1];
queue_recA[1] = recA;
queue_recB[5] = queue_recB[4];
queue_recB[4] = queue_recB[3];
queue_recB[3] = queue_recB[2];
queue_recB[2] = queue_recB[1];
queue_recB[1] = recB;
queue_expectOut[5] = queue_expectOut[4];
queue_expectOut[4] = queue_expectOut[3];
queue_expectOut[3] = queue_expectOut[2];
queue_expectOut[2] = queue_expectOut[1];
queue_expectOut[1] = expectOut;
queue_expectExceptionFlags[5] = queue_expectExceptionFlags[4];
queue_expectExceptionFlags[4] = queue_expectExceptionFlags[3];
queue_expectExceptionFlags[3] = queue_expectExceptionFlags[2];
queue_expectExceptionFlags[2] = queue_expectExceptionFlags[1];
queue_expectExceptionFlags[1] = expectExceptionFlags;
end
moreIn = 0;
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recExpectOut;
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(queue_expectOut[queueCount], recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire outValid, sqrtOpOut;
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
divSqrtRecFN_small#(expWidth, sigWidth, 0)
divRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b0,
recA,
recB,
roundingMode,
outValid,
sqrtOpOut,
recOut,
exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer doExit;
always @(posedge clock) begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
doExit = 0;
if (outValid) begin
if (!queueCount) begin
$fdisplay('h80000002, "--> Spurious 'outValid'.");
`finish_fail;
end
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut
|| (exceptionFlags !== queue_expectExceptionFlags[queueCount])
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'divSqrtRecF%0d_small_div', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write(
"%H %H", queue_recA[queueCount], queue_recB[queueCount]);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$write("=> %H %H", recOut, exceptionFlags);
if (formatWidth > 32) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H",
recExpectOut,
queue_expectExceptionFlags[queueCount]
);
errorCount = errorCount + 1;
doExit = (errorCount == maxNumErrors);
end
queueCount = queueCount - 1;
end else begin
doExit = !moreIn && !queueCount;
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (doExit) begin
count = count + partialCount;
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'divSqrtRecF%0d_small_div', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
$finish;
end
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_divSqrtRecF16_small_div;
test_divSqrtRecFN_small_div#(5, 11) test_divRecF16();
endmodule
module test_divSqrtRecF32_small_div;
test_divSqrtRecFN_small_div#(8, 24) test_divRecF32();
endmodule
module test_divSqrtRecF64_small_div;
test_divSqrtRecFN_small_div#(11, 53) test_divRecF64();
endmodule
module test_divSqrtRecF128_small_div;
test_divSqrtRecFN_small_div#(15, 113) test_divRecF128();
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211AI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; char c1[1005], c2[1005]; long long f[100005][2], ans, k, l; bool pd; int main() { scanf( %s , c1); scanf( %s , c2); scanf( %lld , &k); l = strlen(c1); f[0][0] = 1; for (register long long i = 1; i <= k; i = -~i) { f[i][0] = ((l - 1) * f[i - 1][1]) % 1000000007; f[i][1] = (((l - 2) * f[i - 1][1]) % 1000000007 + f[i - 1][0]) % 1000000007; } for (register long long i = 0; i < l; i = -~i) { pd = false; for (register long long j = 0; j < l; j = -~j) if (c1[(i + j) % l] != c2[j]) { pd = true; break; } if (!pd) { if (i) ans = (ans + f[k][1]) % 1000000007; else ans = (ans + f[k][0]) % 1000000007; } } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n; cin >> n; vector<pair<int, int>> a(n); for (int i = 0; i < n; i++) { cin >> a[i].first; } for (int i = 0; i < n; i++) { cin >> a[i].second; } sort(a.begin(), a.end()); a.push_back(make_pair(static_cast<int>(2e9), 0)); n++; multiset<int> s; int recent = 0; long long ans = 0LL, sum = 0LL; for (int i = 0; i < n; i++) { while (a[i].first > recent && s.size()) { recent++; auto it = prev(s.end()); sum -= *it; ans += sum; s.erase(it); } recent = a[i].first; sum += a[i].second; s.insert(a[i].second); } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n; double r; cin >> n >> r; double X[n]; for (int i = 0; i < n; i++) { cin >> X[i]; } double Y[n]; Y[0] = r; for (int i = 1; i < n; i++) { Y[i] = r; for (int j = 0; j < i; j++) { if (abs(X[i] - X[j]) <= 2 * r) Y[i] = max(Y[i], Y[j] + sqrt(4 * r * r + 2 * X[i] * X[j] - X[i] * X[i] - X[j] * X[j])); } } for (int i = 0; i < n; i++) { cout << fixed << setprecision(9) << Y[i] << ; } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Copyright (C) 2005 Rice University - Rice Open License Fill
`include "spi_defines.v"
module spi_shift (clk, rst, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input /*31*/ [17:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
wire [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//assign p_out = data;
assign data = p_in;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 998244353; long long pwr(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % MOD; b >>= 1, a = a * a % MOD; } return ans; } long long inv(long long a) { return pwr(a, MOD - 2); } template <class T, int SZ> struct BIT { T bit[SZ + 1]; BIT() { memset(bit, 0, sizeof bit); } void upd(int k, T val) { for (; k <= SZ; k += (k & -k)) bit[k] += val; } T query(int k) { T temp = 0; for (; k > 0; k -= (k & -k)) temp += bit[k]; return temp; } T query(int l, int r) { return query(r) - query(l - 1); } }; BIT<long long, 1 << 18> b1; BIT<long long, 1 << 18> b2; map<int, bool> m; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, cnt = 0, ans = 0, k; cin >> n; long long a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; if (a[i] == -1) ++cnt; else { m[a[i]] = 1; } } ans += ((cnt * (cnt - 1)) % MOD * inv((long long)4)) % MOD; for (int i = 0; i < n; ++i) { if (a[i] != -1) { b1.upd(a[i], 1LL); ans += b1.query(a[i] + 1, n); ans %= MOD; } } for (int i = 1; i <= n; ++i) { if (!m[i]) b2.upd(i, 1LL); } long long left[n], right[n], t = 0; for (int i = 0; i < n; ++i) { left[i] = t; t += (a[i] == -1); } t = 0; for (int i = n - 1; i >= 0; --i) { right[i] = t; t += (a[i] == -1); } for (int i = 0; i < n; ++i) { if (a[i] != -1) { k = (left[i] * b2.query(a[i], n)) % MOD; k = (k * inv(cnt)) % MOD; ans += k; k = (right[i] * b2.query(1, a[i])) % MOD; k = (k * inv(cnt)) % MOD; ans += k; ans %= MOD; } } cout << ans % MOD << n ; return 0; }
|
#include <bits/stdc++.h> inline int two(int n) { return 1 << n; } inline int test(int n, int b) { return (n >> b) & 1; } inline void set_bit(int& n, int b) { n |= two(b); } inline void unset_bit(int& n, int b) { n &= ~two(b); } inline int last_bit(int n) { return n & (-n); } inline int ones(int n) { int res = 0; while (n && ++res) n -= n & (-n); return res; } long long int gcd(long long int a, long long int b) { return (a ? gcd(b % a, a) : b); } long long int modPow(long long int a, long long int b, long long int MOD) { long long int x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y) % MOD; } b /= 2; y = (y * y) % MOD; } return x; } long long int modInverse(long long int a, long long int p) { return modPow(a, p - 2, p); } using namespace std; int A[26]; int marked[26]; bool check(int ex) { int i, ctr; ctr = 0; for (i = 0; i < (26); i++) { if (A[i] == ex) ctr++; } if (ctr == 1) return true; else return false; } int main() { int n, i, j, k; cin >> n; char ch; int inf = -999999; string str; int ans, ex, f; ans = ex = f = 0; for (i = (1); i <= (n); i++) { cin >> ch >> str; int len = str.size(); if (f) { if (i == n) continue; if (ch == ! || ch == ? ) ans++; } if (ch == ! ) { memset(marked, 0, sizeof(marked)); ex++; for (j = 0; j < (len); j++) { if (A[str[j] - a ] != inf && !marked[str[j] - a ]) A[str[j] - a ]++; marked[str[j] - a ]++; } } else if (ch == . ) { for (j = 0; j < (len); j++) A[str[j] - a ] = inf; } else A[str[0] - a ] = inf; if (check(ex) && !f) f++; } cout << ans; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:53:42 05/12/2015
// Design Name:
// Module Name: EX_ME
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EX_ME(
clk,rst,
ex_aluresult, ex_td, ex_d2, ex_WREG, ex_WMEM, ex_LW,ex_instr,
me_aluresult, me_td, me_d2, me_WREG, me_WMEM, me_LW,me_instr
);
input clk,rst;
input wire [31:0] ex_aluresult,ex_d2,ex_instr;
input wire [4:0] ex_td;
input wire ex_WREG,ex_WMEM,ex_LW;
output reg [31:0] me_aluresult,me_d2,me_instr;
output reg [4:0] me_td;
output reg me_WREG,me_WMEM,me_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
me_aluresult <= 0;
me_d2 <= 0;
me_td <= 0;
me_WREG <= 0;
me_WMEM <= 0;
me_LW <= 0;
me_instr<=32'b100000;
end
else
begin
me_aluresult <= ex_aluresult;
me_d2 <= ex_d2;
me_td <= ex_td;
me_WREG <= ex_WREG;
me_WMEM <= ex_WMEM;
me_LW <= ex_LW;
me_instr<=ex_instr;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; template <class T, class U> ostream& operator<<(ostream& o, const pair<T, U>& p) { o << ( << p.first << , << p.second << ) ; return o; } template <class T> ostream& operator<<(ostream& o, const vector<T>& v) { o << [ ; for (T t : v) { o << t << , ; } o << ] ; return o; } struct LazySegTree { int n; vector<ll> dat, lazy; LazySegTree(int _n) { n = 1; while (n < _n) n *= 2; dat = vector<ll>(2 * n - 1, LLONG_MAX / 2); lazy = vector<ll>(2 * n - 1, 0); } void show() { for (int(j) = 0; (j) < (int)(dat.size()); ++(j)) printf( %d: dat= %lld, lazy= %lld n , j, dat[j], lazy[j]); } void setLazy(int k, ll v) { lazy[k] = v; dat[k] = v; } void push(int k, int l, int r) { if (lazy[k] != 0) { setLazy(2 * k + 1, lazy[k]); setLazy(2 * k + 2, lazy[k]); } lazy[k] = 0; } void fix(int k, int l, int r) { dat[k] = min(dat[2 * k + 1], dat[2 * k + 2]); } ll merge(ll x, ll y) { return min(x, y); } void _update(int a, int b, ll x, int k, int l, int r) { if (r <= a || b <= l) return; if (a <= l && r <= b) { setLazy(k, x); return; } push(k, l, r); _update(a, b, x, 2 * k + 1, l, (l + r) / 2); _update(a, b, x, 2 * k + 2, (l + r) / 2, r); fix(k, l, r); } void update(int a, int b, ll x) { return _update(a, b, x, 0, 0, n); } ll _query(int a, int b, int k, int l, int r) { if (r <= a || b <= l) return LLONG_MAX / 2; if (a <= l && r <= b) return dat[k]; push(k, l, r); ll vl = _query(a, b, 2 * k + 1, l, (l + r) / 2); ll vr = _query(a, b, 2 * k + 2, (l + r) / 2, r); return merge(vl, vr); } ll query(int a, int b) { return _query(a, b, 0, 0, n); } }; int main() { int n, k; cin >> n >> k; vector<int> b(n); for (int(i) = 0; (i) < (int)(n); ++(i)) cin >> b[i]; int q; cin >> q; vector<int> t(q), l(q), r(q), x(q, -1); for (int(i) = 0; (i) < (int)(q); ++(i)) { cin >> t[i] >> l[i] >> r[i]; --l[i]; --r[i]; if (t[i] == 1) cin >> x[i]; } vector<int> idx; for (int(i) = 0; (i) < (int)(q); ++(i)) { idx.push_back(l[i]); idx.push_back(r[i]); } idx.push_back(0); idx.push_back(n * k - 1); sort((idx).begin(), (idx).end()); idx.erase(unique((idx).begin(), (idx).end()), idx.end()); LazySegTree one(n); for (int(i) = 0; (i) < (int)(n); ++(i)) one.update(i, i + 1, b[i]); map<int, int> m; vector<int> comp; comp.push_back(b[0]); m[0] = 0; for (int i = 1; i < idx.size(); ++i) { if (idx[i] - idx[i - 1] > 1) { int L = (idx[i - 1] + 1) % n, R = (idx[i] + n - 1) % n; int v; if (L <= R) v = one.query(L, R + 1); else v = min(one.query(0, R + 1), one.query(L, n)); comp.push_back(v); } m[idx[i]] = comp.size(); comp.push_back(b[idx[i] % n]); } LazySegTree st(comp.size()); for (int(i) = 0; (i) < (int)(comp.size()); ++(i)) st.update(i, i + 1, comp[i]); for (int(i) = 0; (i) < (int)(q); ++(i)) { int L = m[l[i]], R = m[r[i]]; if (t[i] == 1) st.update(L, R + 1, x[i]); else cout << st.query(L, R + 1) << endl; } return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
(* X_CORE_INFO = "frequency_analyzer_manager,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_frequency_analyzer_manager_1_0,frequency_analyzer_manager,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_frequency_analyzer_manager_1_0,frequency_analyzer_manager,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=frequency_analyzer_manager,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S00_AXI_DATA_WIDTH=32,C_S00_AXI_ADDR_WIDTH=10,PIXEL0_INDEX=63,PIXEL1_INDEX=511,PIXEL2_INDEX=1000,PIXEL0_FREQUENCY0=5000,PIXEL0_FREQUENCY1=10000,PIXEL1_FREQUENCY0=15000,PIXEL1_FREQUENCY1=20000,PIXEL2_FREQUENCY0=40000,PIXEL2_FREQ\
UENCY1=50000,FREQUENCY_DEVIATION=20,CLOCK_FREQUENCY=100000000}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_1_0 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [9 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [9 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(10),
.PIXEL0_INDEX(63),
.PIXEL1_INDEX(511),
.PIXEL2_INDEX(1000),
.PIXEL0_FREQUENCY0(5000),
.PIXEL0_FREQUENCY1(10000),
.PIXEL1_FREQUENCY0(15000),
.PIXEL1_FREQUENCY1(20000),
.PIXEL2_FREQUENCY0(40000),
.PIXEL2_FREQUENCY1(50000),
.FREQUENCY_DEVIATION(20),
.CLOCK_FREQUENCY(100000000)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a[n + 1]; memset(a, 0, sizeof(a)); for (long long i = 1; i <= n; i++) cin >> a[i]; sort(a, a + n + 1); long long sum[n + 1]; memset(sum, 0, sizeof(sum)); sum[1] = a[1]; for (int i = 2; i <= n; i++) { sum[i] = sum[i - 1] + a[i]; } long long ans = 0; for (int i = 0; i <= n; i++) { ans = ans + a[i] + (sum[n] - sum[i]); } cout << ans - a[n] << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
integer p_i; // signal type IData
reg [15:0] p_s; // signal type SData
reg [7:0] p_c; // signal type CData
real p_r; // signal type double
reg [7*8:1] p_str;
string sv_str;
reg [7*8:1] p_in;
string sv_in;
initial begin
if ($test$plusargs("PLUS")!==1) $stop;
if ($test$plusargs("PLUSNOT")!==0) $stop;
if ($test$plusargs("PL")!==1) $stop;
//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
if ($test$plusargs("NOTTHERE")!==0) $stop;
p_i = 10;
if ($value$plusargs("NOTTHERE%d", p_i) !== 0) $stop;
if ($value$plusargs("NOTTHERE%0d", p_i) !== 0) $stop;
if (p_i !== 10) $stop;
p_i = 0;
if ($value$plusargs("INT=%d", p_i) !== 1) $stop;
if (p_i !== 32'd1234) $stop;
p_i = 0;
if ($value$plusargs("INT=%0d", p_i) !== 1) $stop;
if (p_i !== 32'd1234) $stop;
p_i = 0;
if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
if (p_i !== 32'h1234) $stop;
p_i = 0;
// Check octal and WIDTH
if (!$value$plusargs("INT=%o", p_i)) $stop;
if (p_i !== 32'o1234) $stop;
// Check handling of 'SData' type signals (Issue #1592)
p_s = 0;
if (!$value$plusargs("INT=%d", p_s)) $stop;
if (p_s !== 16'd1234) $stop;
// Check handling of 'CData' type signals (Issue #1592)
p_c = 0;
if (!$value$plusargs("INT=%d", p_c)) $stop;
if (p_c !== 8'd210) $stop;
// Check handling of 'double' type signals (Issue #1619)
p_r = 0;
if (!$value$plusargs("REAL=%e", p_r)) $stop;
$display("r='%e'", p_r);
if (p_r !== 1.2345) $stop;
p_r = 0;
if (!$value$plusargs("REAL=%f", p_r)) $stop;
$display("r='%f'", p_r);
if (p_r !== 1.2345) $stop;
p_r = 0;
if (!$value$plusargs("REAL=%g", p_r)) $stop;
$display("r='%g'", p_r);
if (p_r !== 1.2345) $stop;
p_str = "none";
if ($value$plusargs("IN%s", p_str)!==1) $stop;
$display("str='%s'",p_str);
if (p_str !== "T=1234") $stop;
sv_str = "none";
if ($value$plusargs("IN%s", sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_str = "none";
$value$plusargs("IN%s", sv_str);
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
p_in = "IN%s";
`ifdef VERILATOR
p_in = $c(p_in); // Prevent constant propagation
`endif
sv_str = "none";
if ($value$plusargs(p_in, sv_str)!==1) $stop;
$display("str='%s'",sv_str);
if (sv_str != "T=1234") $stop;
sv_str = "none";
if ($value$plusargs("IP%%P%b", p_i)!==1) $stop;
$display("str='%s'",sv_str);
if (p_i != 'b101) $stop;
sv_in = "INT=%d";
`ifdef VERILATOR
if ($c1(0)) sv_in = "NEVER"; // Prevent constant propagation
`endif
p_i = 0;
if ($value$plusargs(sv_in, p_i)!==1) $stop;
$display("i='%d'",p_i);
if (p_i !== 32'd1234) $stop;
// bug3131 - really "if" side effect test
p_i = 0;
if ($value$plusargs("INT=%d", p_i)) ;
if (p_i !== 32'd1234) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event ^ start_event);
assign valid_test_expr = ~(test_expr ^ test_expr);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
// local parameters
parameter num_cks = (max_cks>min_cks)?max_cks:min_cks;
parameter FRAME_START = 1'b0;
parameter FRAME_CHECK = 1'b1;
reg r_state;
reg r_start_event;
integer ii;
always @(posedge clk)
if (`OVL_RESET_SIGNAL == 1'b0) // active low reset
r_start_event <= 1'b1; // reset high to avoid fail straight out of reset
else
r_start_event <= start_event;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
FRAME_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// assert_frame() behaves like assert_implication()
// when min_cks==0 and max_cks==0
if ((min_cks==0) && (max_cks==0)) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if ( (r_start_event == 1'b0) && (start_event == 1'b1) )
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((r_start_event == 1'b0) && (start_event==1'b1) &&
(test_expr==1'b0)) begin
// FAIL, it does not behave like assert_implication()
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE while start event is asserted when both parameters min_cks and max_cks are set to 0");
end
end
// wait for start_event (0->1)
else if ((r_start_event == 1'b0) && (start_event == 1'b1)) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((min_cks != 0) && (test_expr==1'b1)) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
end
else if (!(min_cks == 0 && test_expr == 1'b1)) begin
r_state <= FRAME_CHECK;
ii <= 1;
end
end
end
FRAME_CHECK:
// start_event (0->1) has occurred
// start checking
begin
// Count clock ticks
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((r_start_event == 1'b0) && (start_event == 1'b1)) begin
if ((min_cks != 0) && (test_expr==1'b1) &&
(action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
r_state <= FRAME_START;
end
// start_event (0->1) happens again -- re-started!!!
else if (action_on_new_start == `OVL_IGNORE_NEW_START) begin
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
else if (action_on_new_start == `OVL_RESET_ON_NEW_START)
ii <= 1;
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
end
else begin
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
// Check for (0,0), (0,M), (m,0), (m,M) conditions
if (min_cks == 0) begin
if (max_cks == 0) begin
// (0,0): (min_cks==0, max_cks==0)
// This condition is UN-REACHABLE!!!
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE while start event is asserted when both parameters min_cks and max_cks are set to 0");
r_state <= FRAME_START;
end
else begin // max_cks > 0
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// (0,M): (min_cks==0, max_cks>0)
if (test_expr == 1'b1) begin
// OK, ckeck is done. Go to FRAME_START state for next check.
r_state <= FRAME_START;
end
else begin
if (ii == max_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr does not happen at/before max_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified maximum max_cks cycles from start event");
r_state <= FRAME_START;
end
end
end
end
else begin // min_cks > 0
if (max_cks == 0) begin
// (m,0): (min_cks>0, max_cks==0)
if (ii == min_cks) begin
// OK, test_expr does not happen before min_cks
r_state <= FRAME_START;
end
else begin
if ((test_expr == 1'b1) &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
r_state <= FRAME_START;
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
else begin // max_cks > 0
// (m,M): (min_cks>0, max_cks>0)
if (test_expr == 1'b1) begin
r_state <= FRAME_START;
if (ii < min_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
end
// else OK, we are done!!!
end
else begin
if (ii == max_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr does not happen at/before max_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified maximum max_cks cycles from start event");
r_state <= FRAME_START;
end
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
end
endcase
end
else begin
r_state <= FRAME_START;
ii <= 0;
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_COVER_ON
reg prev_start_event;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if ((start_event != prev_start_event) && (prev_start_event == 1'b0)) begin
ovl_cover_t("start_event covered");
end
prev_start_event <= start_event;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
prev_start_event <= 1'b0;
end
end //always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; template <class T, class U> inline void Max(T &a, U b) { if (a < b) a = b; } template <class T, class U> inline void Min(T &a, U b) { if (a > b) a = b; } char s[3][105]; int ok[3][105], dp[105][3]; pair<int, int> b[3][105]; int main() { int T, i, j, k, m, n; scanf( %d , &T); while (T--) { scanf( %d%d , &n, &m); for (i = 0; i < 3; i++) scanf( %s , s[i]); int st, c[3] = {0}; for (i = 0; i < 3; i++) if (s[i][0] == s ) { st = i; break; } for (i = 0; i < 3; i++) { for (j = 0; j < n; j++) if (s[i][j] >= A && s[i][j] <= Z ) { k = j; while (k < n && s[i][k] == s[i][j]) k++; b[i][c[i]] = make_pair(j, k - 1); c[i]++; j = k - 1; } } memset(dp, 0, sizeof(dp)); memset(ok, 0, sizeof(ok)); dp[0][st] = 1; for (i = 0; i < n - 1; i++) { for (j = 0; j < 3; j++) { for (k = 0; k < c[j]; k++) { if (b[j][k].first <= i + 1 && b[j][k].second >= i + 1) { ok[j][i + 1] = 1; } if (b[j][k].first <= i && b[j][k].second >= i) { dp[i][j] = 0; } } } if (dp[i][0]) { if (!ok[0][i + 1]) { dp[i + 1][0] = 1; if (!ok[1][i + 1]) dp[i + 1][1] = 1; } } if (dp[i][1]) { if (!ok[1][i + 1]) { dp[i + 1][1] = 1; if (!ok[0][i + 1]) dp[i + 1][0] = 1; if (!ok[2][i + 1]) dp[i + 1][2] = 1; } } if (dp[i][2]) { if (!ok[2][i + 1]) { dp[i + 1][2] = 1; if (!ok[1][i + 1]) dp[i + 1][1] = 1; } } for (j = 0; j < 3; j++) { for (k = 0; k < c[j]; k++) b[j][k].first -= 2, b[j][k].second -= 2; } } if (dp[n - 1][0] || dp[n - 1][1] || dp[n - 1][2]) puts( YES ); else puts( NO ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_TB_V
`define SKY130_FD_SC_LS__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ls__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int num = sqrt(n); if (num * num == n) { for (int i = n - num + 1; i >= 1; i -= num) { for (int j = 0; j < num; j++) { printf( %d , i + j); } } printf( n ); return 0; } else { int index1 = n / num; int index2 = n % num; for (int i = index1 * num + 1; i <= n; i++) printf( %d , i); for (int i = n - index2 - num + 1; i >= 1; i -= num) { for (int j = 0; j < num; j++) printf( %d , i + j); } } }
|
#include <bits/stdc++.h> using namespace std; int n, m, lim; struct node { int to; int val; }; stack<int> ans; vector<node> g[5500]; int f[5500][5500]; int fa[5500][5500]; void dfs(int u, int dep) { for (int i = 0; i != g[u].size(); i++) { int& co = g[u][i].val; int& v = g[u][i].to; if (f[dep][u] + co <= lim && f[dep][u] + co < f[dep + 1][v]) { fa[v][dep] = u; f[dep + 1][v] = f[dep][u] + co; dfs(v, dep + 1); } } } int main() { scanf( %d%d%d , &n, &m, &lim); int t1, t2, t3; for (int i = 0; i != m; i++) { scanf( %d%d%d , &t1, &t2, &t3); g[t1].push_back(node{t2, t3}); } memset(f, 0x7f, sizeof(f)); f[1][1] = 0; dfs(1, 1); int i = n; while (!fa[n][i]) i--; cout << i + 1 << endl; ans.push(n); while (fa[n][i]) { ans.push(fa[n][i]); n = fa[n][i]; i--; } cout << ans.top(); ans.pop(); while (!ans.empty()) { cout << << ans.top(); ans.pop(); } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; enum { MAXPOS = 110500, MAXBYTE = 20, MAXN = 7070 }; int q_level[MAXN], q_left[MAXN], q_right[MAXN], q_value[MAXN]; int jump_up[MAXBYTE][MAXPOS], jump_low[MAXBYTE][MAXPOS]; int high[MAXPOS]; void init() { for (int i = 0; (1 << i) < MAXPOS; i++) high[1 << i] = 1; for (int i = 2; i < MAXPOS; i++) { high[i] += high[i - 1]; } for (int i = 1; i < MAXPOS; i++) { jump_up[0][i] = i + high[i]; jump_low[0][i] = i + high[i] - !(i & (i - 1)); } for (int i = 1; i < MAXBYTE; i++) { for (int j = 1; j < MAXPOS; j++) { if (jump_up[i - 1][j] < MAXPOS) { jump_up[i][j] = jump_up[i - 1][jump_up[i - 1][j]]; } if (jump_low[i - 1][j] < MAXPOS) { jump_low[i][j] = jump_low[i - 1][jump_low[i - 1][j]]; } } } } inline int get_left(int start, int jumps) { if (jumps == 0) return start; for (int i = MAXBYTE - 1; i >= 0; i--) { if (jumps >= (1 << i)) { jumps -= (1 << i); start = jump_low[i][start]; } } return start; } inline int get_right(int start, int jumps) { if (jumps == 0) return start; for (int i = MAXBYTE - 1; i >= 0; i--) { if (jumps >= (1 << i)) { jumps -= (1 << i); start = jump_up[i][start]; } } return start; } int main() { init(); int n, m; scanf( %d %d , &n, &m); int q_cnt = 0; for (int i = 0; i < m; i++) { int type; scanf( %d , &type); if (type == 1) { scanf( %d %d %d %d , &q_level[q_cnt], &q_left[q_cnt], &q_right[q_cnt], &q_value[q_cnt]); q_cnt++; } else { int level, position; scanf( %d %d , &level, &position); set<int> subtree; for (int j = 0; j < q_cnt; j++) { if (q_level[j] < level) continue; int left = get_left(position, q_level[j] - level); int right = get_right(position, q_level[j] - level); if (max(left, q_left[j]) <= min(right, q_right[j])) subtree.insert(q_value[j]); } printf( %d n , (int)subtree.size()); } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RBL2; // From t of Test.v
// End of automatics
wire RWL1 = crc[2];
wire RWL2 = crc[3];
Test t (/*AUTOINST*/
// Outputs
.RBL2 (RBL2),
// Inputs
.RWL1 (RWL1),
.RWL2 (RWL2));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, RBL2};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hb6d6b86aa20a882a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
output RBL2,
input RWL1, RWL2);
// verilator lint_off IMPLICIT
not I1 (RWL2_n, RWL2);
bufif1 I2 (RBL2, n3, 1'b1);
Mxor I3 (n3, RWL1, RWL2_n);
// verilator lint_on IMPLICIT
endmodule
module Mxor (output out, input a, b);
assign out = (a ^ b);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_4_V
`define SKY130_FD_SC_LP__INVLP_4_V
/**
* invlp: Low Power Inverter.
*
* Verilog wrapper for invlp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__invlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__invlp_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_4_V
|
//////////////////////////////////////////////////////////////////
// //
// Barrel Shifter for Amber 2 Core //
// //
// The design is optimized for Altera family of FPGAs, //
// and it can be used directly or adapted other N-to-1 LUT //
// FPGA platforms. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Provides 32-bit shifts LSL, LSR, ASR and ROR //
// //
// Author(s): //
// - Dmitry Tarnyagin, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010-2013 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_barrel_shift_fpga (
input [31:0] i_in,
input i_carry_in,
input [7:0] i_shift_amount, // uses 8 LSBs of Rs, or a 5 bit immediate constant
input i_shift_imm_zero, // high when immediate shift value of zero selected
input [1:0] i_function,
output [31:0] o_out,
output o_carry_out
);
`include "a23_localparams.vh"
wire [31:0] rot_prod; // Input rotated by the shift amount
wire [1:0] lsl_out; // LSL: {carry, bit_31}
wire [1:0] lsr_out; // LSR: {carry, bit_31}
wire [1:0] asr_out; // ASR: {carry, bit_31}
wire [1:0] ror_out; // ROR: {carry, bit_31}
reg [32:0] lsl_mask; // Left-hand mask
reg [32:0] lsr_mask; // Right-hand mask
reg [15:0] low_mask; // Mask calculation helper
reg [4:0] shift_amount; // Shift amount for the low-level shifter
reg [2:0] lsl_selector; // Left shift {shift_32, shift_over, shift_amount[4]}
reg [2:0] lsr_selector; // Right shift {shift_32, shift_over, shift_amount[4]}
reg [3:0] low_selector; // {shift_amount[3:0]}
reg shift_nzero; // Amount is not zero
reg shift_over; // Amount is 32 or higher
reg shift_32; // Amount is exactly 32
reg asr_sign; // Sign for ASR shift
reg direction; // Shift direction
wire [31:0] p_r; // 1 bit rotated rot_prod
wire [31:0] p_l; // Alias for the rot_prod
// Implementation details:
// Design is based on masking of rotated input by a left- and right- hand masks.
// Rotated product calculation requires 5 levels of combinational logic, and masks
// must be ready before the product is ready. In fact masks require just 3 to 4 levels
// of logic cells using 4-to-1/2x3-to-1 Altera.
always @*
begin
shift_32 = i_shift_amount == 32;
shift_over = |i_shift_amount[7:5];
shift_nzero = |i_shift_amount[7:0];
shift_amount = i_shift_amount[4:0];
if (i_shift_imm_zero) begin
if (i_function == LSR || i_function == ASR) begin
// The form of the shift field which might be
// expected to correspond to LSR #0 is used
// to encode LSR #32, which has a zero result
// with bit 31 of Rm as the carry output.
shift_nzero = 1'b1;
shift_over = 1'b1;
// Redundant and can be optimized out
// shift_32 = 1'b1;
end else if (i_function == ROR) begin
// RXR, (ROR w/ imm 0)
shift_amount[0] = 1'b1;
shift_nzero = 1'b1;
end
end
// LSB sub-selector calculation. Usually it is taken
// directly from the shift_amount, but ROR requires
// no masking at all.
case (i_function)
LSL: low_selector = shift_amount[3:0];
LSR: low_selector = shift_amount[3:0];
ASR: low_selector = shift_amount[3:0];
ROR: low_selector = 4'b0000;
endcase
// Left-hand MSB sub-selector calculation. Opaque for every function but LSL.
case (i_function)
LSL: lsl_selector = {shift_32, shift_over, shift_amount[4]};
LSR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ASR: lsl_selector = 3'b0_1_0; // Opaque mask selector
ROR: lsl_selector = 3'b0_1_0; // Opaque mask selector
endcase
// Right-hand MSB sub-selector calculation. Opaque for LSL, transparent for ROR.
case (i_function)
LSL: lsr_selector = 3'b0_1_0; // Opaque mask selector
LSR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ASR: lsr_selector = {shift_32, shift_over, shift_amount[4]};
ROR: lsr_selector = 3'b0_0_0; // Transparent mask selector
endcase
// Direction
case (i_function)
LSL: direction = 1'b0; // Left shift
LSR: direction = 1'b1; // Right shift
ASR: direction = 1'b1; // Right shift
ROR: direction = 1'b1; // Right shift
endcase
// Sign for ASR shift
asr_sign = 1'b0;
if (i_function == ASR && i_in[31])
asr_sign = 1'b1;
end
// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
// Practically a bit higher due to high fanout of "direction".
generate
genvar i, j;
for (i = 0; i < 5; i = i + 1)
begin : netgen
wire [31:0] in;
reg [31:0] out;
for (j = 0; j < 32; j = j + 1)
begin : net
always @*
out[j] = in[j] & (~shift_amount[i] ^ direction) |
in[wrap(j, i)] & (shift_amount[i] ^ direction);
end
end
// Order is reverted with respect to volatile shift_amount[0]
assign netgen[4].in = i_in;
for (i = 1; i < 5; i = i + 1)
begin : router
assign netgen[i-1].in = netgen[i].out;
end
endgenerate
// Aliasing
assign rot_prod = netgen[0].out;
// Submask calculated from LSB sub-selector.
// Cost: 16 4-to-1 LUTs.
always @*
case (low_selector) // synthesis full_case parallel_case
4'b0000: low_mask = 16'hffff;
4'b0001: low_mask = 16'hfffe;
4'b0010: low_mask = 16'hfffc;
4'b0011: low_mask = 16'hfff8;
4'b0100: low_mask = 16'hfff0;
4'b0101: low_mask = 16'hffe0;
4'b0110: low_mask = 16'hffc0;
4'b0111: low_mask = 16'hff80;
4'b1000: low_mask = 16'hff00;
4'b1001: low_mask = 16'hfe00;
4'b1010: low_mask = 16'hfc00;
4'b1011: low_mask = 16'hf800;
4'b1100: low_mask = 16'hf000;
4'b1101: low_mask = 16'he000;
4'b1110: low_mask = 16'hc000;
4'b1111: low_mask = 16'h8000;
endcase
// Left-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsl_selector) // synthesis full_case parallel_case
7'b1??: lsl_mask = 33'h_1_0000_0000;
7'b01?: lsl_mask = 33'h_0_0000_0000;
7'b001: lsl_mask = { 1'h_1, low_mask, 16'h_0000};
7'b000: lsl_mask = {17'h_1_ffff, low_mask};
endcase
// Right-hand mask calculation.
// Cost: 33 4-to-1 LUTs.
always @*
casez (lsr_selector) // synthesis full_case parallel_case
7'b1??: lsr_mask = 33'h_1_0000_0000;
7'b01?: lsr_mask = 33'h_0_0000_0000;
7'b000: lsr_mask = { 1'h_1, bit_swap(low_mask), 16'h_ffff};
7'b001: lsr_mask = {17'h_1_0000, bit_swap(low_mask)};
endcase
// Alias: right-rotated
assign p_r = {rot_prod[30:0], rot_prod[31]};
// Alias: left-rotated
assign p_l = rot_prod[31:0];
// ROR MSB, handling special cases
assign ror_out[0] = i_shift_imm_zero ? i_carry_in :
p_r[31];
// ROR carry, handling special cases
assign ror_out[1] = i_shift_imm_zero ? i_in[0] :
shift_nzero ? p_r[31] :
i_carry_in;
// LSL MSB
assign lsl_out[0] = p_l[31] & lsl_mask[31];
// LSL carry, handling special cases
assign lsl_out[1] = shift_nzero ? p_l[0] & lsl_mask[32]:
i_carry_in;
// LSR MSB
assign lsr_out[0] = p_r[31] & lsr_mask[31];
// LSR carry, handling special cases
assign lsr_out[1] = i_shift_imm_zero ? i_in[31] :
shift_nzero ? p_r[31] & lsr_mask[32]:
i_carry_in;
// ASR MSB
assign asr_out[0] = i_in[31] ? i_in[31] :
p_r[31] & lsr_mask[31] ;
// LSR carry, handling special cases
assign asr_out[1] = shift_over ? i_in[31] :
shift_nzero ? p_r[31] :
i_carry_in;
// Carry and MSB are calculated as above
assign {o_carry_out, o_out[31]} = i_function == LSL ? lsl_out :
i_function == LSR ? lsr_out :
i_function == ASR ? asr_out :
ror_out ;
// And the rest of result is the masked rotated input.
assign o_out[30:0] = (p_l[30:0] & lsl_mask[30:0]) |
(p_r[30:0] & lsr_mask[30:0]) |
(~lsr_mask[30:0] & {31{asr_sign}});
// Rotate: calculate bit pos for level "level" and offset "pos"
function [4:0] wrap;
input integer pos;
input integer level;
integer out;
begin
out = pos - (1 << level);
wrap = out[4:0];
end
endfunction
// Swap bits in the input 16-bit value
function [15:0] bit_swap;
input [15:0] value;
integer i;
begin
for (i = 0; i < 16; i = i + 1)
bit_swap[i] = value[15 - i];
end
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Tag Valid
// File : de3d_tc_tag_val.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_tag_val
(
// Inputs
input de_clk, /* drawing engine clock */
input de_rstn, /* drawing engine reset */
input invalidate, /* Invalidate cache. */
input ee_s0_loadn, /* load even, even valid */
input ee_s1_loadn, /* load even, even valid */
input eo_s0_loadn, /* load even, odd valid */
input eo_s1_loadn, /* load even, odd valid */
input oe_s0_loadn, /* load odd, even valid */
input oe_s1_loadn, /* load odd, even valid */
input oo_s0_loadn, /* load odd, odd valid */
input oo_s1_loadn, /* load odd, odd valid */
input [4:0] ee_tag_adr_wr, /* val bit address even, even. */
input [4:0] eo_tag_adr_wr, /* val bit address even, odd. */
input [4:0] oe_tag_adr_wr, /* val bit address odd, even. */
input [4:0] oo_tag_adr_wr, /* val bit address odd, odd. */
input [4:0] ee_tag_adr_rd, /* val bit address even, even. */
input [4:0] eo_tag_adr_rd, /* val bit address even, odd. */
input [4:0] oe_tag_adr_rd, /* val bit address odd, even. */
input [4:0] oo_tag_adr_rd, /* val bit address odd, odd. */
// Outputs
output [1:0] ee_val, /* valid bit for even, even. */
output [1:0] eo_val, /* valid bit for even, odd. */
output [1:0] oe_val, /* valid bit for odd, even. */
output [1:0] oo_val /* valid bit for odd, odd. */
);
/* Registers ****************************************************/
reg [31:0] ee_val_s0_reg; /* valid bit for (even, even),s0*/
reg [31:0] ee_val_s1_reg; /* valid bit for (even, even),s1*/
reg [31:0] eo_val_s0_reg; /* valid bit for (even, odd),s0 */
reg [31:0] eo_val_s1_reg; /* valid bit for (even, odd),s1 */
reg [31:0] oe_val_s0_reg; /* valid bit for (odd, even),s0 */
reg [31:0] oe_val_s1_reg; /* valid bit for (odd, even),s1 */
reg [31:0] oo_val_s0_reg; /* valid bit for (odd, odd),s0 */
reg [31:0] oo_val_s1_reg; /* valid bit for (odd, odd),s1 */
assign ee_val[0] = ee_val_s0_reg[ee_tag_adr_rd];
assign ee_val[1] = ee_val_s1_reg[ee_tag_adr_rd];
assign eo_val[0] = eo_val_s0_reg[eo_tag_adr_rd];
assign eo_val[1] = eo_val_s1_reg[eo_tag_adr_rd];
assign oe_val[0] = oe_val_s0_reg[oe_tag_adr_rd];
assign oe_val[1] = oe_val_s1_reg[oe_tag_adr_rd];
assign oo_val[0] = oo_val_s0_reg[oo_tag_adr_rd];
assign oo_val[1] = oo_val_s1_reg[oo_tag_adr_rd];
wire inv;
assign inv = invalidate;
wire [31:0] set_s0_ee;
wire [31:0] set_s1_ee;
wire [31:0] set_s0_eo;
wire [31:0] set_s1_eo;
wire [31:0] set_s0_oe;
wire [31:0] set_s1_oe;
wire [31:0] set_s0_oo;
wire [31:0] set_s1_oo;
assign set_s0_ee = {31'b0,~ee_s0_loadn} << (ee_tag_adr_wr & {5{~ee_s0_loadn}});
assign set_s1_ee = {31'b0,~ee_s1_loadn} << (ee_tag_adr_wr & {5{~ee_s1_loadn}});
assign set_s0_eo = {31'b0,~eo_s0_loadn} << (eo_tag_adr_wr & {5{~eo_s0_loadn}});
assign set_s1_eo = {31'b0,~eo_s1_loadn} << (eo_tag_adr_wr & {5{~eo_s1_loadn}});
assign set_s0_oe = {31'b0,~oe_s0_loadn} << (oe_tag_adr_wr & {5{~oe_s0_loadn}});
assign set_s1_oe = {31'b0,~oe_s1_loadn} << (oe_tag_adr_wr & {5{~oe_s1_loadn}});
assign set_s0_oo = {31'b0,~oo_s0_loadn} << (oo_tag_adr_wr & {5{~oo_s0_loadn}});
assign set_s1_oo = {31'b0,~oo_s1_loadn} << (oo_tag_adr_wr & {5{~oo_s1_loadn}});
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)ee_val_s0_reg <= 0;
else if(inv)ee_val_s0_reg <= 0;
else ee_val_s0_reg <= ee_val_s0_reg | set_s0_ee;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)ee_val_s1_reg <= 0;
else if(inv)ee_val_s1_reg <= 0;
else ee_val_s1_reg <= ee_val_s1_reg | set_s1_ee;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)eo_val_s0_reg <= 0;
else if(inv)eo_val_s0_reg <= 0;
else eo_val_s0_reg <= eo_val_s0_reg | set_s0_eo;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)eo_val_s1_reg <= 0;
else if(inv)eo_val_s1_reg <= 0;
else eo_val_s1_reg <= eo_val_s1_reg | set_s1_eo;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oe_val_s0_reg <= 0;
else if(inv)oe_val_s0_reg <= 0;
else oe_val_s0_reg <= oe_val_s0_reg | set_s0_oe;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oe_val_s1_reg <= 0;
else if(inv)oe_val_s1_reg <= 0;
else oe_val_s1_reg <= oe_val_s1_reg | set_s1_oe;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oo_val_s0_reg <= 0;
else if(inv)oo_val_s0_reg <= 0;
else oo_val_s0_reg <= oo_val_s0_reg | set_s0_oo;
end
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)oo_val_s1_reg <= 0;
else if(inv)oo_val_s1_reg <= 0;
else oo_val_s1_reg <= oo_val_s1_reg | set_s1_oo;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; long long int power(long long int x, long long int y, long long int mod = 1000000007) { long long int ret = 1; x = x % mod; while (y) { if (y & 1) ret = (ret * x) % mod; y = y >> 1; x = (x * x) % mod; } return ret % mod; } long long int isprime(long long int x) { for (long long int i = 2; i * i <= x; i++) if (x % i == 0) return 0; return 1; } void solve() { long long int n, k; cin >> n >> k; if (n <= k) { cout << 1 << endl; return; } vector<long long int> fact; for (long long int i = 1; i * i <= n; i++) { if (n % i == 0) { if (i <= k) fact.push_back(i); if ((n / i) <= k) fact.push_back(n / i); } } sort(fact.begin(), fact.end()); cout << n / fact.back() << endl; } signed main() { long long int t; cin >> t; while (t--) solve(); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_2_V
`define SKY130_FD_SC_LP__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, a, b; cin >> n >> a >> b; int N = n; if (abs(a - b) > 1) { cout << -1 << n ; continue; } if (a + b > n - 2) { cout << -1 << n ; continue; } bool flag = false; if (a < b) { swap(a, b); flag = true; } int A = a; int B = b; int sol[n]; int i = 1; while (a--) { sol[i] = n; i += 2; n--; } i = 2; int temp = 1; while (b--) { sol[i] = temp; i += 2; temp++; } sol[0] = B + 1; temp = B + 2; int index = A + B + 1; if (B == A) { while (index != N) { sol[index] = temp; temp++; index++; } } else { temp = N - A; while (index != N) { sol[index] = temp; temp--; index++; } } if (flag) { for (int i = 0; i < N; i++) { sol[i] = N + 1 - sol[i]; } } for (int i = 0; i < N; i++) { cout << sol[i] << ; } cout << n ; } cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; return 0; }
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:50:25 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_xbar_0 -prefix
// DemoInterconnect_xbar_0_ DemoInterconnect_xbar_0_stub.v
// Design : DemoInterconnect_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
module DemoInterconnect_xbar_0(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[95:0],s_axi_awprot[8:0],s_axi_awvalid[2:0],s_axi_awready[2:0],s_axi_wdata[95:0],s_axi_wstrb[11:0],s_axi_wvalid[2:0],s_axi_wready[2:0],s_axi_bresp[5:0],s_axi_bvalid[2:0],s_axi_bready[2:0],s_axi_araddr[95:0],s_axi_arprot[8:0],s_axi_arvalid[2:0],s_axi_arready[2:0],s_axi_rdata[95:0],s_axi_rresp[5:0],s_axi_rvalid[2:0],s_axi_rready[2:0],m_axi_awaddr[223:0],m_axi_awprot[20:0],m_axi_awvalid[6:0],m_axi_awready[6:0],m_axi_wdata[223:0],m_axi_wstrb[27:0],m_axi_wvalid[6:0],m_axi_wready[6:0],m_axi_bresp[13:0],m_axi_bvalid[6:0],m_axi_bready[6:0],m_axi_araddr[223:0],m_axi_arprot[20:0],m_axi_arvalid[6:0],m_axi_arready[6:0],m_axi_rdata[223:0],m_axi_rresp[13:0],m_axi_rvalid[6:0],m_axi_rready[6:0]" */;
input aclk;
input aresetn;
input [95:0]s_axi_awaddr;
input [8:0]s_axi_awprot;
input [2:0]s_axi_awvalid;
output [2:0]s_axi_awready;
input [95:0]s_axi_wdata;
input [11:0]s_axi_wstrb;
input [2:0]s_axi_wvalid;
output [2:0]s_axi_wready;
output [5:0]s_axi_bresp;
output [2:0]s_axi_bvalid;
input [2:0]s_axi_bready;
input [95:0]s_axi_araddr;
input [8:0]s_axi_arprot;
input [2:0]s_axi_arvalid;
output [2:0]s_axi_arready;
output [95:0]s_axi_rdata;
output [5:0]s_axi_rresp;
output [2:0]s_axi_rvalid;
input [2:0]s_axi_rready;
output [223:0]m_axi_awaddr;
output [20:0]m_axi_awprot;
output [6:0]m_axi_awvalid;
input [6:0]m_axi_awready;
output [223:0]m_axi_wdata;
output [27:0]m_axi_wstrb;
output [6:0]m_axi_wvalid;
input [6:0]m_axi_wready;
input [13:0]m_axi_bresp;
input [6:0]m_axi_bvalid;
output [6:0]m_axi_bready;
output [223:0]m_axi_araddr;
output [20:0]m_axi_arprot;
output [6:0]m_axi_arvalid;
input [6:0]m_axi_arready;
input [223:0]m_axi_rdata;
input [13:0]m_axi_rresp;
input [6:0]m_axi_rvalid;
output [6:0]m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 40; int a[maxN][maxN]; int b[maxN][maxN]; int flips[maxN][maxN]; int n, x; int check(int mask) { memset(flips, 0, sizeof(flips)); for (int i = 0; i < x; ++i) { if (mask & (1 << i)) { flips[x - 1][i] = 1; } } for (int i = 0; i + 1 < x; ++i) { for (int j = 0; j < x; ++j) { flips[i + x][j] = flips[i][j] ^ flips[x - 1][j]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j + 1 < x; ++j) { flips[i][j + x] = flips[i][j] ^ flips[i][x - 1]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { b[i][j] = a[i][j]; if (flips[i][j]) { b[i][j] = -b[i][j]; } } } int res = 0; for (int i = 0; i < n; ++i) { res += b[x - 1][i]; } for (int i = 0; i + 1 < x; ++i) { for (int j = 0; j < n; ++j) { b[i][j] += b[i + x][j]; } } for (int i = 0; i + 1 < x; ++i) { int cres1 = 0, cres2 = 0; for (int j = 0; j + 1 < x; ++j) { cres1 += abs(b[i][j] + b[i][j + x]); cres2 += abs(b[i][j] - b[i][j + x]); } res += max(cres1 + b[i][x - 1], cres2 - b[i][x - 1]); } return res; } int solve(vector<vector<int> > a) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { ::a[i][j] = a[i][j]; } } x = (n + 1) / 2; int res = -1000000000LL; for (int i = 0; i < (1 << x); ++i) { res = max(res, check(i)); } return res; } int main() { scanf( %d , &n); vector<vector<int> > a(n, vector<int>(n)); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , &a[i][j]); } } cout << solve(a) << endl; return 0; }
|
// fpgaTop_illite.v - ssiegel 2009-03-17
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_rstn, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_illite ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_rstn),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) int idx, __attribute__((unused)) int LINE_NUM) { cerr << endl; } template <typename Head, typename... Tail> void debug_out(vector<string> args, int idx, int LINE_NUM, Head H, Tail... T) { if (idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } const long long MOD = (int)1e9 + 7; const long long INF = 2e18 + 5; struct hashLL { size_t operator()(long long x) const { x = (x ^ (x >> 30)) * UINT64_C(0xbf58476d1ce4e5b9); x = (x ^ (x >> 27)) * UINT64_C(0x94d049bb133111eb); x = x ^ (x >> 31); return x; } }; long long inv(long long a, long long b) { return 1 < a ? b - inv(b % a, a) * b / a : 1; } long long gcd(long long a, long long b, long long& x, long long& y) { if (a == 0) { x = 0; y = 1; return b; } long long x1, y1; long long d = gcd(b % a, a, x1, y1); x = y1 - (b / a) * x1; y = x1; return d; } long long distsq(long long x1, long long y1, long long x2, long long y2) { return (x2 - x1) * (x2 - x1) + (y2 - y1) * (y2 - y1); } const int N = 200001; long long n, m, k, t, u, v; string s; unordered_set<int> ks; unordered_map<int, vector<int>> g; int visited[N]; long long tosink[N]; long long tosource[N]; void bfs(int start, long long arr[]) { for (int i = 0; i < n + 1; i++) arr[i] = -1; deque<int> q; q.push_back(start); arr[start] = 0; while (!q.empty()) { int n = q.size(); for (int i = 0; i < (n); i++) { int curr = q.front(); q.pop_front(); for (int c : g[curr]) { if (arr[c] == -1) { arr[c] = arr[curr] + 1; q.push_back(c); } } } } } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; for (int i = 0; i < (k); i++) { cin >> u; ks.emplace(u); } for (int i = 0; i < (m); i++) { cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } bfs(1, tosource); bfs(n, tosink); vector<pair<int, int>> tok; map<int, unordered_set<int>> towardssink; for (auto& p : ks) { tok.push_back(make_pair(tosource[p], p)); towardssink[-tosink[p]].emplace(p); } sort((tok).begin(), (tok).end()); long long best = 0; for (auto& p : tok) { long long mintosource = p.first; long long node = p.second; towardssink[-tosink[node]].erase(node); if (towardssink[-tosink[node]].empty()) { towardssink.erase(-tosink[node]); } if (towardssink.empty()) break; auto& pr = *towardssink.begin(); long long mxtosink = -pr.first; long long curr = 1; curr = curr + mintosource + min(tosink[node], mxtosink); best = max(best, curr); } long long normaldist = tosink[1]; if (best < normaldist) { cout << best << endl; } else { cout << normaldist << endl; } }
|
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
`define NS_DBG_SRC_ADDR 3
`define NS_DBG_INIT_CK 14
`define NS_DBG_INIT_DAT 5
`define NS_DBG_INIT_RED 15
`define NS_DBG_MAX_SRC_CASE 4
module pakout_io
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
PSZ=`NS_PACKET_SIZE,
FSZ=`NS_PACKIN_FSZ,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src_clk,
input wire snk_clk,
input wire reset,
// SRC_0
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_PAKIN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk_clk, reset, i0)
localparam TOT_PKS = ((`NS_FULL_MSG_SZ / PSZ) + 1);
localparam FIFO_IDX_WIDTH = ((($clog2(FSZ)-1) >= 0)?($clog2(FSZ)-1):(0));
localparam PACKETS_IDX_WIDTH = ((($clog2(TOT_PKS)-1) >= 0)?($clog2(TOT_PKS)-1):(0));
reg [3:0] cnt_0 = `NS_DBG_INIT_DAT;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC_ADDR;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = `NS_DBG_INIT_DAT;
reg [RSZ-1:0] ro0_red = `NS_DBG_INIT_RED;
reg [0:0] ro0_req = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_err_0 = `NS_OFF;
reg [0:0] inp0_err_1 = `NS_OFF;
reg [0:0] inp0_err_2 = `NS_OFF;
reg [0:0] inp0_err_3 = `NS_OFF;
reg [0:0] sink_started = 0;
`NS_DECLARE_REG_MSG(inp0)
`NS_DECLARE_FIFO(bf0)
`NS_DECLARE_REG_PACKETS(rgi0)
reg [0:0] rgi0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_bak_dat = 15;
`NS_DECLARE_REG_DBG(rg_dbg)
//SRC_0
always @(posedge src_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk_clk)
begin
if(! sink_started) begin
sink_started <= 1;
inp0_err_0 <= `NS_OFF;
inp0_err_1 <= `NS_OFF;
inp0_err_2 <= `NS_OFF;
inp0_err_3 <= `NS_OFF;
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
`NS_FIFO_INIT(bf0)
`NS_PACKETS_INIT(rgi0, `NS_ON)
rgi0_ack <= `NS_OFF;
end else begin
`NS_PACKIN_TRY_INC(rgi0, i0, bf0, rgi0_ack)
`NS_FIFO_TRY_INC_TAIL(bf0, inp0, has_inp0)
else if(has_inp0) begin
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err_0) begin
if(inp0_src != `NS_DBG_SRC_ADDR) begin
inp0_err_0 <= `NS_ON;
rg_dbg_disp0 <= inp0_src[3:0];
end
end
if(! inp0_err_1) begin
if((inp0_bak_dat <= 14) && ((inp0_bak_dat + 1) != inp0_dat)) begin
inp0_err_1 <= `NS_ON;
rg_dbg_disp0 <= inp0_dst[3:0];
end else begin
inp0_bak_dat <= inp0_dat;
end
end
if(! inp0_err_2) begin
if(inp0_red != inp0_redun) begin
inp0_err_2 <= `NS_ON;
rg_dbg_disp0 <= inp0_red[3:0];
end
end
end
if(inp0_done_cks) begin
if(! inp0_err_0 && ! inp0_err_1 && ! inp0_err_2) begin
rg_dbg_disp0 <= inp0_dat[3:0];
rg_dbg_disp1 <= inp0_red[3:0];
end
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
end
end
end
end
//SRC_0
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = rgi0_ack;
assign dbg_leds[0:0] = inp0_err_0;
assign dbg_leds[1:1] = inp0_err_1;
assign dbg_leds[2:2] = inp0_err_2;
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; int x, y, root = -1; vector<int> g[200100]; int len[200100], viz[3][200100]; int dmax = 0, ind; int stacky[200100], l = 0; void dfs(int x) { viz[0][x] = 1; if (g[x].size() == 1) { len[x] = 1; } else { int okk = 1; int kiddo = -1, kiddo2 = -1; for (auto y : g[x]) { if (viz[0][y]) { continue; } dfs(y); if (x == root) { if (len[y] == 0) { okk = 0; } else if (kiddo == -1) { kiddo = len[y]; } else if (kiddo != len[y] && kiddo2 == -1) { kiddo2 = len[y]; } else if (kiddo2 != len[y] && kiddo != len[y]) { okk = 0; } } else { if (len[y] == 0) { okk = 0; continue; } if (kiddo == -1) { kiddo = len[y]; } else if (kiddo != len[y]) { okk = 0; } } } if (okk) { if (x != root || kiddo2 == -1) { len[x] = kiddo + 1; } else { len[x] = kiddo + kiddo2 + 1; } } } } void dfss(int x, int t, int d) { stacky[++l] = x; viz[t][x] = 1; if (d > dmax) { ind = x; dmax = d; root = stacky[(l + 1) / 2]; } for (auto y : g[x]) if (!viz[t][y]) dfss(y, t, d + 1); --l; } int main() { cin.sync_with_stdio(false); cin >> N; if (N == 2) { cout << 1; return 0; } for (int i = 1; i < N; ++i) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfss(1, 1, 0); dmax = 0; dfss(ind, 2, 0); dfs(root); if (len[root]) { int ret = len[root] - 1; while (ret % 2 == 0) ret /= 2; cout << ret; return 0; } else { cout << -1; return 0; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR4_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_FUNCTIONAL_PP_V
|
//======================================================================
//
// system_m6502.v
// --------------
// A simple test system that can be implemented a FPGA device.
// It basically instantiates a m6502 cpu core, provides some
// memory and some address mapped I/O.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module system_m6502(
input wire clk,
input wire reset_n,
output wire [7 : 0] leds
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter MEM_BASE_ADDR = 16'h0000;
parameter MEM_SIZE = 16'h03ff;
parameter IO_LED0_ADDR = 16'h1000;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [7 : 0] mem [0 : 1023];
reg mem_we;
reg [7 : 0] led0_reg;
reg [7 : 0] led0_new;
reg led0_we;
reg ready_reg;
reg valid_reg;
//----------------------------------------------------------------
// Wires for cpu connectivity.
//----------------------------------------------------------------
wire cpu_cs;
wire cpu_wr;
wire [15 : 0] cpu_address;
reg [7 : 0] cpu_read_data;
wire [7 : 0] cpu_write_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign leds = led0_reg;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
m6502 m6502_cpu(
.clk(clk),
.reset_n(reset_n),
.cs(cpu_cs),
.wr(cpu_wr),
.address(cpu_address),
.mem_ready(ready_reg),
.data_valid(valid_reg),
.read_data(cpu_read_data),
.write_data(cpu_write_data)
);
//----------------------------------------------------------------
// sync mem and I/O access.
// TODO Add I/O for reading pins.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_io_update
integer i;
if (!reset_n)
begin
led0_reg <= 8'h0;
for (i = 0 ; i <= MEM_SIZE ; i = i + 1)
mem[i] <= 8'h0;
end
else
begin
ready_reg <= 1;
valid_reg <= 0;
if ((cpu_address <= MEM_BASE_ADDR) && (cpu_address <= MEM_BASE_ADDR + MEM_SIZE))
begin
valid_reg <= 1;
cpu_read_data <= mem[cpu_address[9 : 0]];
if (cpu_wr)
mem[cpu_address[9 : 0]] <= cpu_write_data;
end
if (cpu_address == IO_LED0_ADDR)
begin
valid_reg <= 1;
cpu_read_data <= led0_reg;
if (cpu_wr)
led0_reg <= cpu_write_data;
end
end
end // mem_io_update
endmodule // system_6502
//======================================================================
// EOF system_m6502.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_BEHAVIORAL_PP_V
|
module top;
reg passed;
reg [9*8:1] check;
reg [71:0] value;
reg [7:0] nval;
real rval;
initial begin
passed = 1'b1;
// Look for the hex value using a runtime string.
check = "hex=%h";
if (! $value$plusargs(check, value)) begin
$display("FAILED: Unable to get hex value.");
passed = 1'b0;
end
if (value !== 72'h0123456789abcdefxz) begin
$display("FAILED: expected hex value 72'h0123456789abcdefxz, got %h",
value);
passed = 1'b0;
end
// Look for a hex (x) value.
if (! $value$plusargs("hex=%x", value)) begin
$display("FAILED: Unable to get hex value.");
passed = 1'b0;
end
if (value !== 72'h0123456789abcdefxz) begin
$display("FAILED: expected hex value 72'h0123456789abcdefxz, got %h",
value);
passed = 1'b0;
end
// Look for an octal value.
if (! $value$plusargs("oct=%o", value)) begin
$display("FAILED: Unable to get octal value.");
passed = 1'b0;
end
if (value !== 72'o01234567xz) begin
$display("FAILED: expected octal value 72'o01234567xz, got %o",
value);
passed = 1'b0;
end
// Look for a binary value.
if (! $value$plusargs("bin=%b", value)) begin
$display("FAILED: Unable to get binary value.");
passed = 1'b0;
end
if (value !== 72'b0101xz) begin
$display("FAILED: expected binary value 72'b0101xz, got %b",
value);
passed = 1'b0;
end
// Look for a negative binary value.
if (! $value$plusargs("neg=%b", value)) begin
$display("FAILED: Unable to get negative binary value.");
passed = 1'b0;
end
if (value !== 72'hfffffffffffffffffc) begin
$display("FAILED: expected binary value 72'hff...fc, got %h",
value);
passed = 1'b0;
end
// Look for a negative octal value.
if (! $value$plusargs("neg=%o", value)) begin
$display("FAILED: Unable to get negative octal value.");
passed = 1'b0;
end
if (value !== 72'hffffffffffffffffc0) begin
$display("FAILED: expected octal value 72'hff...fc0, got %h",
value);
passed = 1'b0;
end
// Look for a truncated negative hex value.
if (! $value$plusargs("neg=%h", nval)) begin
$display("FAILED: Unable to get negative hex value.");
passed = 1'b0;
end
if (nval !== 8'h00) begin
$display("FAILED: expected hex value 8'h00, got %h",
nval);
passed = 1'b0;
end
// Look for a bad binary value.
if (! $value$plusargs("bad_num=%b", value)) begin
$display("FAILED: Unable to get bad binary value.");
passed = 1'b0;
end
if (value !== 'bx) begin
$display("FAILED: expected bad binary value 'bx, got %d",
value);
passed = 1'b0;
end
// Look for a bad octal value.
if (! $value$plusargs("bad_num=%o", value)) begin
$display("FAILED: Unable to get bad octal value.");
passed = 1'b0;
end
if (value !== 'bx) begin
$display("FAILED: expected bad octal value 'bx, got %d",
value);
passed = 1'b0;
end
// Look for a bad hex value.
if (! $value$plusargs("bad_num=%h", value)) begin
$display("FAILED: Unable to get bad hex value.");
passed = 1'b0;
end
if (value !== 'bx) begin
$display("FAILED: expected bad hex value 'bx, got %d",
value);
passed = 1'b0;
end
// Look for a bad hex (x) value.
if (! $value$plusargs("bad_num=%x", value)) begin
$display("FAILED: Unable to get bad hex (x) value.");
passed = 1'b0;
end
if (value !== 'bx) begin
$display("FAILED: expected bad hex (x) value 'bx, got %d",
value);
passed = 1'b0;
end
// Look for a decimal value.
if (! $value$plusargs("dec=%d", value)) begin
$display("FAILED: Unable to get decimal value.");
passed = 1'b0;
end
if (value !== 'd0123456789) begin
$display("FAILED: expected decimal value 'd0123456789, got %d",
value);
passed = 1'b0;
end
// Look for a negative decimal value.
if (! $value$plusargs("neg=%d", value)) begin
$display("FAILED: Unable to get negative decimal value.");
passed = 1'b0;
end
if (value !== -100) begin
$display("FAILED: expected decimal value 72'hff...fc0, got %h",
value);
passed = 1'b0;
end
// Look for a bad decimal value.
if (! $value$plusargs("bad_num=%d", value)) begin
$display("FAILED: Unable to get bad decimal value.");
passed = 1'b0;
end
if (value !== 'bx) begin
$display("FAILED: expected bad decimal value 'bx, got %d",
value);
passed = 1'b0;
end
// Look for a decimal "x" value.
if (! $value$plusargs("dec_x=%d", value)) begin
$display("FAILED: Unable to get decimal \"x\" value.");
passed = 1'b0;
end
if (value !== 'dx) begin
$display("FAILED: expected decimal value 'dx, got %d",
value);
passed = 1'b0;
end
// Look for a decimal "z" value.
if (! $value$plusargs("dec_z=%d", value)) begin
$display("FAILED: Unable to get decimal \"z\" value.");
passed = 1'b0;
end
if (value !== 'dz) begin
$display("FAILED: expected decimal value 'dz, got %d",
value);
passed = 1'b0;
end
// Look for a real value.
if (! $value$plusargs("real=%f", rval)) begin
$display("FAILED: Unable to get real value.");
passed = 1'b0;
end
if (rval != 12.) begin
$display("FAILED: expected real value 12., got %f",
rval);
passed = 1'b0;
end
// Look for a negative real value.
if (! $value$plusargs("neg_real=%f", rval)) begin
$display("FAILED: Unable to get a negative real value.");
passed = 1'b0;
end
if (rval != -23456.0) begin
$display("FAILED: expected negative real value -23456.0, got %f",
rval);
passed = 1'b0;
end
// Look for an infinite real value.
if (! $value$plusargs("real_inf=%f", rval)) begin
$display("FAILED: Unable to get infinite real value.");
passed = 1'b0;
end
if (rval != 1.0/0.0) begin
$display("FAILED: expected infinite real value Inf, got %f",
rval);
passed = 1'b0;
end
// Look for a bad real value.
if (! $value$plusargs("bad_num=%f", rval)) begin
$display("FAILED: Unable to get bad real value.");
passed = 1'b0;
end
if (rval != 0.0) begin
$display("FAILED: expected bad real value 0.0, got %f",
rval);
passed = 1'b0;
end
// Look for a warning real value.
if (! $value$plusargs("warn_real=%f", rval)) begin
$display("FAILED: Unable to get warning real value.");
passed = 1'b0;
end
if (rval != 9.825) begin
$display("FAILED: expected warning real value 9.825, got %f",
rval);
passed = 1'b0;
end
// Put a decimal value into a real based value.
if (! $value$plusargs("dec=%d", rval)) begin
$display("FAILED: Unable to get decimal (real) value.");
passed = 1'b0;
end
if (rval != 123456789.0) begin
$display("FAILED: expected decimal as real value 12...89.0, got %f",
rval);
passed = 1'b0;
end
// Put a negative decimal into a real based value.
if (! $value$plusargs("neg=%d", rval)) begin
$display("FAILED: Unable to get negative decimal (real) value.");
passed = 1'b0;
end
if (rval != -100.0) begin
$display("FAILED: expected decimal as real value -100, got %f",
rval);
passed = 1'b0;
end
// Put a real value into a bit based value.
if (! $value$plusargs("real=%f", value)) begin
$display("FAILED: Unable to get real (bit) value.");
passed = 1'b0;
end
if (value !== 12) begin
$display("FAILED: expected real as bit value 12, got %d",
value);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long INFL = LLONG_MAX; int N, w, W[100100], b, B[100100], C[100100], S[100100]; int main() { ios_base::sync_with_stdio(0); cin >> N; for (int(i) = 1; (i) <= (N); (i)++) { cin >> C[i] >> S[i]; if (C[i]) B[b++] = i; else W[w++] = i; } w--, b--; while (w >= 0 && b >= 0) { int s = min(S[W[w]], S[B[b]]); cout << W[w] << << B[b] << << s << endl; S[W[w]] -= s; S[B[b]] -= s; if (S[B[b]]) w--; else b--; } w--; b--; while (w >= 0) cout << W[w] << << B[0] << << 0 << endl, w--; while (b >= 0) cout << W[0] << << B[b] << << 0 << endl, b--; }
|
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; for (int t = 0; t < test; t++) { int n; cin >> n; int k = 2; while (n % (int)(pow(2, k) - 1) != 0) { k++; } int ans = n / (pow(2, k) - 1); cout << ans << endl; } return 0; }
|
/*
* pll_adv_example.v: Example program working in simulation as well as it should on real hardware.
* To be tested on Digilent Basys 3.
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
module pll_adv_example (
input clk,
input RST,
output [7:0] led);
reg [6:0] DADDR;
reg [15:0] DI;
wire [15:0] DO;
reg DEN;
reg DWE;
wire DRDY;
wire CLKFB;
/* More information about the instantiiation can be found in Xilinx UG953 509ff. */
PLLE2_ADV #(
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(10.0),
.CLKIN2_PERIOD(10.0),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(2),
.CLKOUT2_DIVIDE(32),
.CLKOUT3_DIVIDE(16),
.CLKOUT4_DIVIDE(128),
.CLKOUT5_DIVIDE(128),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.9),
.CLKOUT5_DUTY_CYCLE(0.1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1))
pll (
.CLKOUT0(led[0]),
.CLKOUT1(led[1]),
.CLKOUT2(led[2]),
.CLKOUT3(led[3]),
.CLKOUT4(led[5]),
.CLKOUT5(led[6]),
.CLKFBOUT(CLKFB),
.LOCKED(led[7]),
.CLKIN1(clk),
.CLKIN2(clk),
.CLKINSEL(1'b1),
.DADDR(DADDR),
.DI(DI),
.DO(DO),
.DWE(DWE),
.DEN(DEN),
.DRDY(DRDY),
.DCLK(led[0]),
.PWRDWN(0),
.RST(RST),
.CLKFBIN(CLKFB));
integer step = 0;
/* CLKOUT1 will be dynamically reconfigured */
always @(posedge clk) begin
/* After some time to achieve LOCK & DRDY status, we can write the first value into ClkReg1
* for CLKOUT1 */
if (led[7] && DRDY && step == 0) begin
/* Address of ClkReg1 for CLKOUT1 */
DADDR <= 7'h0A;
/* PHASE MUX = 3
* RESERVED = 0
* HIGH TIME = 16
* LOW TIME = 32 */
/* This translates to a CLKOUT1_DIVDE of 48, a CLKOUT1_DUTY_CYCLE of 0.666
* and a phase offset of 3x45° relative to the VCO */
DI = 16'b011_0_010000_100000;
DEN <= 1;
DWE <= 1;
step <= 1;
/* Next, we will disable DEN and DWE, as soon as DRDY and LOCK are achieved again */
end else if (led[7] && step == 1) begin
DEN <= 0;
DWE <= 0;
step <= 2;
/* Now we will write into ClkReg2 for CLKOUT1 */
end else if (led[7] && DRDY && step == 2) begin
DEN <= 1;
DWE <= 1;
/* Address of ClkReg2 of CLKOUT1 */
DADDR = 7'h0B;
/* RESERVED = 000000
* MX = 2b'00
* EDGE = 0
* NO COUNT = 0
* DELAY TIME = 3 */
/* This will add an additional phase delay as high as 3 VCO clock cycles */
DI <= 16'b000000_00_0_0_000011;
step <= 3;
end else if (led[7] && step == 3) begin
/* Disable Read/Write again */
DEN <= 0;
DWE <= 0;
step <= 4;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { char s[200001], t1[200001]; long long n, x, y, t, con = 0; cin >> n >> x >> y; getchar(); gets(s); t = n - x; for (long long i = t; s[i] != 0 ; i++) { if (i == n - 1 - y && s[i] != 1 ) con++; if (i != n - 1 - y && s[i] != 0 ) con++; } cout << con << endl; return 0; }
|
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Tests accessing individual characters in a string
module string_index();
initial begin
int i;
string str = "that is a test string";
for(i = 0; i < $size(str); ++i)
begin
if(str[i] == "t")
str[i] = "w";
end
if(str != "whaw is a wesw swring")
begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CONB_PP_BLACKBOX_V
|
// Copyright (c) 2000-2013 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
module BypassWire0();
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y, c; int n; const int maxn = 300009; char str[maxn]; long long cnt = 0; int main() { cin >> n >> x >> y; cin >> str; int now = 0; for (int i = 0; i < n; ++i) { if (str[i] == 1 ) { if (now != 0) cnt++; now = 0; } else { now++; } } if (now) cnt++; if (!cnt) return 0 * puts( 0 ); if (y <= x) cout << cnt * y << endl; else { cout << (cnt - 1) * x + y << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 50005; const long long UP = 2.2e9; long long num[maxn], sum[maxn]; int cnt, wei[15]; inline void init() { long long up = 0, pre = 0, x = 0, cut = 0; cnt = 0; int flag = 0; for (int k = 1; k <= 9; ++k) { cut = x; x = x * 10 + 9; long long xx = x - cut; for (int i = 1; i <= xx; ++i) { up += pre + i * k; num[++cnt] = pre + i * k; if (up >= UP) { flag = 1; break; } } if (flag) break; pre += (x - x / 10) * k; } sum[0] = 0; sum[1] = num[1]; for (int i = 1; i <= cnt; ++i) sum[i] = sum[i - 1] + num[i]; } int main() { init(); int t, n, k, flag; scanf( %d , &t); while (t--) { scanf( %d , &n); for (k = 1; k <= cnt; ++k) if (n <= sum[k]) break; n -= sum[k - 1]; flag = 0; for (int i = 1; i <= k; ++i) { int t = i, j = 0; while (t) { wei[++j] = t % 10; t /= 10; } for (int l = j; l >= 1; --l) { --n; if (n == 0) { flag = 1; printf( %d n , wei[l]); break; } } if (flag) break; } } return 0; }
|
`default_nettype none
`include "processor.h"
module core_interrupt_manager(
//System
input wire iCLOCK,
input wire inRESET,
//Free
input wire iFREE_IRQ_SETCONDITION,
//Interrupt Configlation Table
input wire iICT_VALID,
input wire [5:0] iICT_ENTRY,
input wire iICT_CONF_MASK,
input wire iICT_CONF_VALID,
input wire [1:0] iICT_CONF_LEVEL,
//Core Info
input wire [31:0] iSYSREGINFO_PSR,
//External
input wire iEXT_ACTIVE,
input wire [5:0] iEXT_NUM,
output wire oEXT_ACK,
//output oEXT_BUSY,
//Core-ALU
input wire iFAULT_ACTIVE,
input wire [6:0] iFAULT_NUM,
input wire [31:0] iFAULT_FI0R,
///To Exception Manager
input wire iEXCEPTION_LOCK,
output wire oEXCEPTION_ACTIVE,
output wire [6:0] oEXCEPTION_IRQ_NUM,
output wire [31:0] oEXCEPTION_IRQ_FI0R,
input wire iEXCEPTION_IRQ_ACK
);
localparam STT_IDLE = 2'h0;
localparam STT_COMP_WAIT = 2'h1;
/****************************************************
Register and Wire
***************************************************/
//Interrupt Valid
wire software_interrupt_valid;
wire hardware_interrupt_valid;
//Interrupt Config Table
reg ict_conf_mask[0:63];
reg ict_conf_valid[0:63];
reg [1:0] ict_conf_level[0:63];
//Instruction State
reg [1:0] b_state;
reg [6:0] b_irq_num;
reg [31:0] b_irq_fi0r;
reg b_irq_type;
reg b_irq_ack;
//Generate
integer i;
/****************************************************
Instruction Config Table
***************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_valid [i] = 1'b0;
end
if(`PROCESSOR_DATA_RESET_EN)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_mask [i] = 1'b0;
ict_conf_level [i] = 2'h0;
end
end
end
else begin
if(iICT_VALID)begin
ict_conf_mask [iICT_ENTRY] <= iICT_CONF_MASK;
ict_conf_valid [iICT_ENTRY] <= iICT_CONF_VALID;
ict_conf_level [iICT_ENTRY] <= iICT_CONF_LEVEL;
end
end
end
assign software_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iFAULT_ACTIVE;
assign hardware_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM]));
//Hardware Irq Latch
reg b_hw_irq_valid;
reg [6:0] b_hw_irq_num;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_hw_irq_valid <= 1'b0;
b_hw_irq_num <= 7'h0;
end
else begin
if(!b_hw_irq_valid)begin
if(iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM])))begin
b_hw_irq_valid <= 1'b1;
b_hw_irq_num <= {1'b0, iEXT_NUM};
end
end
else begin
if(!software_interrupt_valid && b_state == STT_IDLE && !iEXCEPTION_LOCK)begin
b_hw_irq_valid <= 1'b0;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= STT_IDLE;
b_irq_num <= {7{1'b0}};
b_irq_fi0r <= 32'h0;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_state <= STT_COMP_WAIT;
b_irq_num <= iFAULT_NUM;
b_irq_fi0r <= iFAULT_FI0R;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b1;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_state <= STT_COMP_WAIT;
b_irq_num <= b_hw_irq_num;
b_irq_fi0r <= 32'h0;
b_irq_type <= 1'b1;
b_irq_ack <= 1'b1;
end
end
STT_COMP_WAIT :
begin
b_irq_ack <= 1'b0;
if(iEXCEPTION_IRQ_ACK)begin
b_state <= STT_IDLE;
end
end
default :
begin
b_state <= STT_IDLE;
end
endcase
end
end
assign oEXT_ACK = b_irq_ack && b_irq_type;//(b_state == `STT_COMP_WAIT && !software_interrupt_valid)? hardware_interrupt_valid : 1'b0;
assign oEXCEPTION_ACTIVE = (b_state == STT_COMP_WAIT)? !iEXCEPTION_IRQ_ACK : software_interrupt_valid || hardware_interrupt_valid || b_hw_irq_valid;//(b_state == `STT_COMP_WAIT)? !iFREE_IRQ_SETCONDITION : software_interrupt_valid || hardware_interrupt_valid;
assign oEXCEPTION_IRQ_NUM = (b_state == STT_COMP_WAIT)? b_irq_num : ((software_interrupt_valid)? iFAULT_NUM : {1'b0, iEXT_NUM});
assign oEXCEPTION_IRQ_FI0R = b_irq_fi0r;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int it[200041], n, io; int down(int x) { int s = 0, rs = x; while (x <= n * 2) { s = max(it[x], s); x += x & (-x); } return s; } void up(int x, int u) { while (x > 0) { it[x] = max(it[x], u); x -= x & (-x); } } int main() { int i, a[100005], o = 0, co; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = n - 1; i >= 0; i--) { co = down(a[i]); up(a[i], co + 1); o = max(co + 1, o); } cout << o << endl; }
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long base, long long exponent, long long mod) { long long result = 1; while (exponent > 0) { if (exponent % 2 == 0) { exponent /= 2; base = (base * base) % mod; } else { result = (result * base) % mod; exponent /= 2; base = (base * base) % mod; } } return result; } bool decresing(long long x, long long y) { return x > y; } long long trin(long long start, long long stop) { return (stop - start + 1) * (stop + start) / 2; } bool sortvectorf(pair<long long, long long> a, pair<long long, long long> b) { return ((a.first > b.first) || (a.first == b.first && a.second > b.second)); } bool sortvectorfv(pair<long long, long long> a, pair<long long, long long> b) { return ((a.first > b.first) || (a.first == b.first && a.second < b.second)); } bool sortvectors(pair<long long, long long> a, pair<long long, long long> b) { return ((a.second > b.second) || (a.second == b.second && a.first > b.first)); } bool negasortvectorf(pair<long long, long long> a, pair<long long, long long> b) { return ((a.first < b.first) || (a.first == b.first && a.second < b.second)); } bool negasortvectors(pair<long long, long long> a, pair<long long, long long> b) { return ((a.second < b.second) || (a.second == b.second && a.first < b.first)); } vector<vector<long long>> findPermutations(vector<long long> &a) { sort(a.begin(), a.end()); vector<vector<long long>> sol; do { sol.push_back(a); } while (next_permutation(a.begin(), a.end())); return sol; } long long gcd(long long a, long long b) { if (a == 0) { return b; } if (b == 0) { return a; } return gcd(b % a, a); } bool isprime(long long n) { for (int i = 2; i < n; i += 1) { if (i * i > n) { break; } if ((n / i) * i == n) { return false; } } return true; } long long fdivisor(long long n, long long fro) { for (int i = 1; i < n + 1; i += 1) { if ((n / i) * i == n && i >= fro) { return i; } } return -1; } vector<long long> divlist(long long n) { vector<long long> curr; for (int i = 2; i < n; i += 1) { if ((long long)i * i > n) { break; } if ((n / i) * i == n) { curr.push_back(i); curr.push_back(n / i); } if ((long long)i * i == n) { curr.pop_back(); } } sort(curr.begin(), curr.end()); return curr; } long long digsum(long long num) { long long cr = 0; while (num > 0) { cr += num % 10; num /= 10; } return cr; } long long modInverse(long long a, long long b) { long long m = b; long long y = 0, x = 1; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) { x += b; } return x; } long long azeret(long long num, long long mod) { long long sil = 1; while (num > 1) { sil *= num; sil %= mod; num--; } return sil; } long long moddiv(long long to, long long by, long long mod) { to %= mod; while (to % by != 0) { to += mod; if (to > (by + 1) * mod) { return -1; } } return (to / by) % mod; } pair<long long, long long> func(pair<long long, long long> a, pair<long long, long long> b) { if (a.first < b.first) { return a; } if (b.first < a.first) { return b; } return {a.first, (a.second + b.second) % 1000000007}; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<pair<long long, long long>> matrioskas(n); set<long long> alls; for (int i = 0; i < n; i += 1) { cin >> matrioskas[i].second >> matrioskas[i].first; alls.insert(matrioskas[i].first); alls.insert(matrioskas[i].second); } alls.insert(0); sort(matrioskas.begin(), matrioskas.end(), negasortvectorf); vector<long long> ral; for (auto it = alls.begin(); it != alls.end(); it++) { ral.push_back(*it); } long long siz = ral.size(); vector<vector<long long>> cons(siz); vector<pair<long long, long long>> pts(siz, {999999999999999, 99999999999999}); pts[0] = {0, 1}; for (int i = 0; i < n; i += 1) { long long left, right, mid; left = 0; right = siz - 1; while (right > left) { mid = (right + left + 1) / 2; if (ral[mid] > matrioskas[i].first) { right = mid - 1; } else { left = mid; } } long long inpart = left; left = 0; right = siz - 1; while (right > left) { mid = (right + left + 1) / 2; if (ral[mid] > matrioskas[i].second) { right = mid - 1; } else { left = mid; } } long long outpart = left; cons[inpart].push_back(outpart); } for (int i = 1; i < siz; i += 1) { pair<long long, long long> ptt = pts[i - 1]; ptt.first += ral[i] - ral[i - 1]; pts[i] = func(pts[i], ptt); for (int ii = 0; ii < cons[i].size(); ii += 1) { pts[cons[i][ii]] = func(pts[i], pts[cons[i][ii]]); } } pair<long long, long long> ans = {999999999999999, 99999999999999}; for (int i = siz - 1; i >= 0; i += -1) { if (cons[i].size() > 0) { break; } ans = func(ans, pts[i]); } cout << ans.second << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 10005; const int Inf = 1000000000; int n; int a[Maxn]; set<pair<int, int> > S; long long res; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) S.insert(pair<int, int>(i - a[i], i)); for (int i = 0; i < n; i++) { int add = 0, j = 0; set<pair<int, int> >::iterator it = S.begin(); while (j < n - 1) { int nxt = j; while (it != S.end() && j >= it->first - i) { nxt = max(nxt, it->second - i); it++; } j = nxt; add++; } res += add; S.erase(pair<int, int>(-a[i] + i, i)); S.insert(pair<int, int>(n - 1 - a[i] + i + 1, n - 1 + i + 1)); } printf( %I64d n , res); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_1_V
`define SKY130_FD_SC_MS__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_1_V
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; unsigned long long int gcd(unsigned long long int a, unsigned long long int b) { unsigned long long int max = a > b ? a : b; unsigned long long int min = a < b ? a : b; if (max % min == 0) return min; if (max % min == 1) return 1; return gcd(min, max % min); } int main() { int flag = 0; unsigned long long int l, r; cin >> l >> r; if (l - r < 2) { cout << -1 ; return 0; } unsigned long long int i, j, k; for (i = l; i <= r - 2; i++) { for (j = i + 1; j <= r - 1; j++) { if (gcd(i, j) == 1) { for (k = j + 1; k <= r; k++) { if (gcd(j, k) == 1 && gcd(i, k) != 1) { flag = 1; cout << i << << j << << k; break; } } } if (flag == 1) break; } if (flag == 1) break; } if (flag == 0) cout << -1 ; return 0; }
|
#include <bits/stdc++.h> bool choice_first(std::vector<size_t> a, std::vector<size_t> b) { uint64_t sum_a, sum_b; sum_a = sum_b = 0; for (auto elem : a) { sum_a += elem; } for (auto elem : b) { sum_b += elem; } return sum_a > sum_b || (sum_a == sum_b && a < b); } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); std::cout.tie(0); size_t n, m; std::cin >> n; std::vector<std::vector<std::vector<size_t>>> dp( n + 1, std::vector<std::vector<size_t>>(n + 1)); std::vector<size_t> a(n); for (size_t i = 0; i < n; i++) { std::cin >> a[i]; } std::cin >> m; for (size_t i = 0; i < n; i++) { if (i == 0) { dp[1][i] = {a[0]}; continue; } dp[1][i] = std::max(std::vector<size_t>{a[i]}, dp[1][i - 1]); } for (size_t i = 2; i <= n; i++) { for (size_t j = i - 1; j < n; j++) { if (j == i - 1) { std::vector<size_t> cur = dp[i - 1][j - 1]; cur.push_back(a[j]); dp[i][j] = cur; continue; } std::vector<size_t> first, second; first = dp[i - 1][j - 1]; first.push_back(a[j]); second = dp[i][j - 1]; if (choice_first(first, second)) { dp[i][j] = first; } else { dp[i][j] = second; } } } for (size_t i = 0; i < m; i++) { size_t k, pos; std::cin >> k >> pos; std::cout << dp[k][n - 1][pos - 1] << n ; } }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Analog Auxiliary SYSMON Input Buffer
// /___/ /\ Filename : IBUF_ANALOG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/30/13 - Initial version.
// 02/04/15 - 845545 - Remove pulldown and strength specification.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUF_ANALOG
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I
);
// define constants
localparam MODULE_NAME = "IBUF_ANALOG";
tri0 glblGSR = glbl.GSR;
// begin behavioral model
assign O = I;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
//
// ram.v -- main memory, using SDRAM
//
module ram(clk, clk_ok, reset,
en, wr, size, addr,
data_in, data_out, wt,
sdram_cke, sdram_cs_n,
sdram_ras_n, sdram_cas_n,
sdram_we_n, sdram_ba, sdram_a,
sdram_udqm, sdram_ldqm, sdram_dq);
// internal interface signals
input clk;
input clk_ok;
input reset;
input en;
input wr;
input [1:0] size;
input [24:0] addr;
input [31:0] data_in;
output reg [31:0] data_out;
output reg wt;
// SDRAM interface signals
output sdram_cke;
output sdram_cs_n;
output sdram_ras_n;
output sdram_cas_n;
output sdram_we_n;
output [1:0] sdram_ba;
output [12:0] sdram_a;
output sdram_udqm;
output sdram_ldqm;
inout [15:0] sdram_dq;
reg [3:0] state;
reg a0;
reg cntl_read;
reg cntl_write;
wire cntl_done;
wire [23:0] cntl_addr;
reg [15:0] cntl_din;
wire [15:0] cntl_dout;
wire sd_out_en;
wire [15:0] sd_out;
//--------------------------------------------------------------
sdramCntl sdramCntl1(
// clock
.clk(clk),
.clk_ok(clk_ok),
// host side
.rd(cntl_read & ~cntl_done),
.wr(cntl_write & ~cntl_done),
.done(cntl_done),
.hAddr(cntl_addr),
.hDIn(cntl_din),
.hDOut(cntl_dout),
// SDRAM side
.cke(sdram_cke),
.ce_n(sdram_cs_n),
.ras_n(sdram_ras_n),
.cas_n(sdram_cas_n),
.we_n(sdram_we_n),
.ba(sdram_ba),
.sAddr(sdram_a),
.sDIn(sdram_dq),
.sDOut(sd_out),
.sDOutEn(sd_out_en),
.dqmh(sdram_udqm),
.dqml(sdram_ldqm)
);
assign sdram_dq = (sd_out_en == 1) ? sd_out : 16'hzzzz;
//--------------------------------------------------------------
// the SDRAM is organized in 16-bit halfwords
// address line 0 is controlled by the state machine
// (this is necessary for word accesses)
assign cntl_addr[23:1] = addr[24:2];
assign cntl_addr[0] = a0;
// state machine for SDRAM access
always @(posedge clk) begin
if (reset == 1) begin
state <= 4'b0000;
wt <= 1;
end else begin
case (state)
4'b0000:
// wait for access
begin
if (en == 1) begin
// access
if (wr == 1) begin
// write
if (size[1] == 1) begin
// write word
state <= 4'b0001;
end else begin
if (size[0] == 1) begin
// write halfword
state <= 4'b0101;
end else begin
// write byte
state <= 4'b0111;
end
end
end else begin
// read
if (size[1] == 1) begin
// read word
state <= 4'b0011;
end else begin
if (size[0] == 1) begin
// read halfword
state <= 4'b0110;
end else begin
// read byte
state <= 4'b1001;
end
end
end
end
end
4'b0001:
// write word, upper 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b0010;
end
end
4'b0010:
// write word, lower 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b0011:
// read word, upper 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b0100;
data_out[31:16] <= cntl_dout;
end
end
4'b0100:
// read word, lower 16 bits
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[15:0] <= cntl_dout;
wt <= 0;
end
end
4'b0101:
// write halfword
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b0110:
// read halfword
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[31:16] <= 16'h0000;
data_out[15:0] <= cntl_dout;
wt <= 0;
end
end
4'b0111:
// write byte (read halfword cycle)
begin
if (cntl_done == 1) begin
state <= 4'b1000;
data_out[31:16] <= 16'h0000;
data_out[15:0] <= cntl_dout;
end
end
4'b1000:
// write byte (write halfword cycle)
begin
if (cntl_done == 1) begin
state <= 4'b1111;
wt <= 0;
end
end
4'b1001:
// read byte
begin
if (cntl_done == 1) begin
state <= 4'b1111;
data_out[31:8] <= 24'h000000;
if (addr[0] == 0) begin
data_out[7:0] <= cntl_dout[15:8];
end else begin
data_out[7:0] <= cntl_dout[7:0];
end
wt <= 0;
end
end
4'b1111:
// end of bus cycle
begin
state <= 4'b0000;
wt <= 1;
end
default:
// all other states: reset
begin
state <= 4'b0000;
wt <= 1;
end
endcase
end
end
// output of state machine
always @(*) begin
case (state)
4'b0000:
// wait for access
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0001:
// write word, upper 16 bits
begin
a0 = 1'b0;
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[31:16];
end
4'b0010:
// write word, lower 16 bits
begin
a0 = 1'b1;
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[15:0];
end
4'b0011:
// read word, upper 16 bits
begin
a0 = 1'b0;
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0100:
// read word, lower 16 bits
begin
a0 = 1'b1;
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0101:
// write halfword
begin
a0 = addr[1];
cntl_read = 0;
cntl_write = 1;
cntl_din = data_in[15:0];
end
4'b0110:
// read halfword
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b0111:
// write byte (read halfword cycle)
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b1000:
// write byte (write halfword cycle)
begin
a0 = addr[1];
cntl_read = 0;
cntl_write = 1;
if (addr[0] == 0) begin
cntl_din = { data_in[7:0], data_out[7:0] };
end else begin
cntl_din = { data_out[15:8], data_in[7:0] };
end
end
4'b1001:
// read byte
begin
a0 = addr[1];
cntl_read = 1;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
4'b1111:
// end of bus cycle
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
default:
// all other states: reset
begin
a0 = 1'bx;
cntl_read = 0;
cntl_write = 0;
cntl_din = 16'hxxxx;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_PP_SYMBOL_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ALU4_LA(a, b, c_in, c_out, less, sel, out, P, G);
input less;
input [3:0] a, b;
input [2:0] sel;
input c_in;
output [3:0] out;
output P,G;
output c_out;
wire [2:0] c;
wire [3:0] p, g;
alu_slice_LA a1(a[0], b[0], c_in, less, sel, out[0], p[0], g[0]);
alu_slice_LA a2(a[1], b[1], c[0], 1'b0, sel, out[1], p[1], g[1]);
alu_slice_LA a3(a[2], b[2], c[1], 1'b0, sel, out[2], p[2], g[2]);
alu_slice_LA a4(a[3], b[3], c[2], 1'b0, sel, out[3], p[3], g[3]);
lookahead l1(c_in, c_out, c, p, g, P, G);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n]; vector<long long> v; for (long long i = 0; i < n; i++) { cin >> a[i]; v.push_back(a[i]); } bool ans = true; sort(v.begin(), v.end()); for (long long i = 0; i < n; i++) { if (a[i] != v[i] && a[i] % v[0] > 0) { ans = false; break; } } if (ans) cout << YES ; else cout << NO ; cout << endl; } }
|
`timescale 1ns / 1ps
`include "cordic.vh"
// synopsys_ template
module cordic
#(
parameter DEC = 2, // decimal points
parameter FRAC = 14, // fraction points
parameter MOD = `MOD_CIR, // MOD = {`MOD_CIR=1,`MOD_LIN=0,`MOD_HYP=-1}
parameter DIR = `DIR_ROT // DIR = {`DIR_ROT=0, `DIR_VEC=1}
)
(
clk,
rst,
g_init,
e_init,
o,
terminate
);
localparam L = DEC + FRAC;
localparam ITER = FRAC + 1;
localparam LOG_ITER = $clog2(ITER);
input clk;
input rst;
input [2*L-1:0] g_init; // {x, y}
input [L-1:0] e_init; // {z}
output [3*L-1:0] o;
output terminate;
wire [L-1:0] a;
wire [L-1:0] b;
wire [L-1:0] c;
wire done;
assign terminate = done;
assign o = {a, b, c};
reg [L-1:0] xi;
reg [L-1:0] yi;
reg [L-1:0] zi;
reg [L-1:0] xd;
reg [L-1:0] yd;
reg [L-1:0] zd;
wire [L-1:0] xs;
wire [L-1:0] ys;
wire [L-1:0] xi_next;
wire [L-1:0] yi_next;
wire [L-1:0] zi_next;
reg [LOG_ITER:0] iter;
wire [L-1:0] alphai;
wire di;
wire [1:0] mu;
alpha_table
#(
.DEC(DEC),
.FRAC(FRAC),
.MOD(MOD)
)
_alpha_table
(
.iter(iter[LOG_ITER-1:0]),
.alphai(alphai)
);
generate
if(DIR==`DIR_ROT) begin :ROT
assign di = zi[L-1];
end else begin :VEC// if(DIR==`DIR_VEC)
assign di = xi[L-1]&yi[L-1];
end
endgenerate
// assign xs = (xi>>iter);
// assign ys = (yi>>iter);
barrel_shifter_left
#(
.N(L)
)
_barrel_shifter_left_1
(
.a(xi),
.shift(iter),
.o(xs)
);
barrel_shifter_left
#(
.N(L)
)
_barrel_shifter_left_2
(
.a(yi),
.shift(iter),
.o(ys)
);
always @(*) begin
if(di==0) begin // di == +1
yd = xs;
zd = -alphai;
if(MOD==`MOD_HYP) begin
xd = ys;
end else if(MOD==`MOD_LIN) begin
xd = 0;
end else begin //(MOD==`MOD_CIR)
xd = -ys;
end
end else begin // di == -1
yd = -xs;
zd = alphai;
if(MOD==`MOD_HYP) begin
xd = -ys;
end else if(MOD==`MOD_LIN) begin
xd = 0;
end else begin //(MOD==`MOD_CIR)
xd = ys;
end
end
end
/*
assign xi_next = xi + xd;
assign yi_next = yi + yd;
assign zi_next = zi + zd;
*/
ADD
#(
.N(L)
)
_ADD_1
(
.A(xi),
.B(xd),
.CI(1'b0),
.S(xi_next)
);
ADD
#(
.N(L)
)
_ADD_2
(
.A(yi),
.B(yd),
.CI(1'b0),
.S(yi_next)
);
ADD
#(
.N(L)
)
_ADD_3
(
.A(zi),
.B(zd),
.CI(1'b0),
.S(zi_next)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
xi <= g_init[2*L-1:L];
yi <= g_init[L-1:0];
zi <= e_init;
iter <= 0;
end else begin
if(iter < ITER) begin
iter <= iter + 1;
xi <= xi_next;
yi <= yi_next;
zi <= zi_next;
end
end
end
assign a = xi;
assign b = yi;
assign c = zi;
assign done = (iter == ITER);
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 17.1 cbx_altiobuf_out 2017:12:05:11:11:27:SJ cbx_mgl 2017:12:05:12:41:31:SJ cbx_stratixiii 2017:12:05:11:11:27:SJ cbx_stratixv 2017:12:05:11:11:27:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_hd__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_hd__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a, b; int c[4]; int minC = INT_MAX; for (int i = 0; i < 4; i++) { cin >> c[i]; if (minC > c[i]) minC = c[i]; } cin >> a >> b; int minXX = min(minC, b); int ans = minXX - a; bool baal = 0; if (minXX != minC) baal = 1; if (ans < 0) cout << 0 << endl; else if (a == b && minC > a) cout << 1 << endl; else if (baal == 1) cout << ans + 1 << endl; else cout << ans << endl; return 0; }
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xgmii_baser_dec_64
*/
module test_xgmii_baser_dec_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter HDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] encoded_rx_data = 0;
reg [HDR_WIDTH-1:0] encoded_rx_hdr = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire rx_bad_block;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
encoded_rx_data,
encoded_rx_hdr
);
$to_myhdl(
xgmii_rxd,
xgmii_rxc,
rx_bad_block
);
// dump file
$dumpfile("test_xgmii_baser_dec_64.lxt");
$dumpvars(0, test_xgmii_baser_dec_64);
end
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; vector<int> v(n); vector<int> cnt(n + 1, 0); for (int i = 0; i < n; i++) { cin >> v[i]; cnt[v[i]]++; } long long sum = 0, ans = 0, len = 0; for (int i = 0; i < n; i++) { sum = v[i], len = 1; for (int j = i + 1; j < n; j++) { sum += v[j]; len++; if (len >= 2) { if (sum <= n) { ans += cnt[sum]; cnt[sum] = 0; } else break; } } } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = ((ans % m) * (a % m)) % m; b /= 2; a = ((a % m) * (a % m)) % m; } return ans % m; } long long n, m; long long cnt[3005]; set<pair<long long, long long> > g[3005]; long long c[3005]; long long p[3005]; long long solve(long long x) { long long ans = cnt[1]; long long sum = 0; set<int> vis; priority_queue<long long, vector<long long>, greater<long long> > pq; for (long long i = 2; i <= m; i++) { if (g[i].size() < x) continue; long long k = g[i].size() - x + 1; long long t = k; for (set<pair<long long, long long> >::iterator it = g[i].begin(); it != g[i].end(); it++) { if (k == 0) break; sum += (*it).first; vis.insert((*it).second); k--; } ans += t; } for (long long i = 1; i <= n; i++) { if (p[i] == 1) continue; if (vis.find(i) == vis.end()) { pq.push(c[i]); } } while (ans < x && !pq.empty()) { sum += pq.top(); pq.pop(); ans++; } if (ans < x) { return (long long)1e18; } return sum; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (long long i = 1; i <= n; i++) { cin >> p[i] >> c[i]; g[p[i]].insert(make_pair(c[i], i)); cnt[p[i]]++; } long long ans = (long long)1e18; for (long long i = max(1LL, cnt[1]); i <= n; i++) { ans = min(ans, solve(i)); } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; struct trio { int64_t first, second, trd; friend ostream &operator<<(ostream &o, trio &a) { o << ( << a.first << , << a.second << , << a.trd << ) ; return o; } }; template <typename T> inline T max() { return numeric_limits<T>::max(); } template <typename T> inline T gcd(T a, T b) { return b == 0 ? a : gcd(b, a % b); } template <typename T> inline void get(T &&v) { cin >> v; } template <typename T, typename... Args> inline void get(T &&v, Args &&...args) { cin >> v; get(args...); } template <typename T> inline void put(T &&v) { cout << v << n ; } template <typename T, typename... Args> inline void put(T &&v, Args &&...args) { cout << v << ; put(args...); } template <typename T> inline void putc(T &&a, const string s = ) { { for (auto &v : a) cout << v << s; } cout << n ; } ostream &operator<<(ostream &out, pair<int32_t, int32_t> &a) { out << ( << a.first << , << a.second << ) ; return out; } ostream &operator<<(ostream &out, pair<int64_t, int64_t> &a) { out << ( << a.first << , << a.second << ) ; return out; } vector<int32_t> primes; inline void calc_primes(int32_t lmt) { vector<char> s(lmt); primes.push_back(2); for (int32_t i = 3; i < lmt; i += 2) { if (s[i]) continue; primes.push_back(i); for (int32_t j = i + (i << 1); j < lmt; j += (i << 1)) s[j] = 1; } } inline vector<pair<int32_t, int32_t> > factorize(int32_t n) { vector<pair<int32_t, int32_t> > a; int32_t cnt = __builtin_ctzl(n); a.push_back({2, cnt}); n >>= cnt; for (auto &d : primes) { cnt = 0; while (n % d == 0) n /= d, cnt++; a.push_back({d, cnt}); if (n == 1) break; } if (n != 1) a.push_back({n, 1}); return a; } int64_t mod = 1e9 + 9; inline int64_t mmul(int64_t a, int64_t n) { if (a < 0) a += mod; if (n < 0) n += mod; int64_t r = 0; while (n) { if (n & 1) r = (r + a) % mod; a = (a + a) % mod; n >>= 1; } return r; } inline int64_t mpow(int64_t a, int64_t n) { if (a < 0) a += mod; if (n < 0) n += mod; int64_t r = 1; while (n) { if (n & 1) r = mmul(r, a); a = mmul(a, a); n >>= 1; } return r; } int main() { { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout << setprecision(20); }; int64_t n, a, b, k; get(n, a, b, k); int64_t inv_a = mpow(a, mod - 2); int64_t aa = mpow(a, n); int64_t bb = 1; int64_t z = 0; for (int64_t i = 0; i < k; ++i) { char c; cin >> c; int64_t sgn = (c == + ? 1 : -1); z = (z + sgn * mmul(aa, bb)) % mod; aa = mmul(aa, inv_a); bb = mmul(bb, b); } int64_t q = mmul(bb, mpow(inv_a, k)); int64_t s = 0, t = (n + 1) / k; if (q == 1) s = t; else s = mmul((mod + 1 - mpow(q, t)), mpow(mod + 1 - q, mod - 2)); z = mmul(z, s); if (z < 0) z += mod; put(z); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_BEHAVIORAL_PP_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr4 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [3:0] Q,
input C0,
input C1,
input CE,
input [3:0] D0,
input [3:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
endmodule
|
// this is the sprite parallel to serial converter
// clk is 7.09379 MHz (low resolution pixel clock)
// the sprdata assign circuitry is constructed differently from the hardware
// as described in the amiga hardware reference manual
// this is to make sure that the horizontal start position of a sprite
// aligns with the bitplane/playfield start position
module denise_sprites_shifter
(
input clk, // 28MHz clock
input clk7_en,
input reset, // reset
input aen, // address enable
input [1:0] address, // register address input
input [8:0] hpos, // horizontal beam counter
input [15:0] fmode,
input shift,
input [48-1:0] chip48,
input [15:0] data_in, // bus data in
output [1:0] sprdata, // serialized sprite data out
output reg attach // sprite is attached
);
// register names and adresses
parameter POS = 2'b00;
parameter CTL = 2'b01;
parameter DATA = 2'b10;
parameter DATB = 2'b11;
// local signals
reg [63:0] datla; // data register A
reg [63:0] datlb; // data register B
reg [63:0] shifta; // shift register A
reg [63:0] shiftb; // shift register B
reg [8:0] hstart; // horizontal start value
reg armed; // sprite "armed" signal
reg load; // load shift register signal
reg load_del;
//--------------------------------------------------------------------------------------
// switch data according to fmode
reg [64-1:0] spr_fmode_dat;
always @ (*) begin
case(fmode[3:2])
2'b00 : spr_fmode_dat = {data_in, 48'h000000000000};
2'b11 : spr_fmode_dat = {data_in, chip48[47:0]};
default : spr_fmode_dat = {data_in, chip48[47:32], 32'h00000000};
endcase
end
// generate armed signal
always @(posedge clk)
if (clk7_en) begin
if (reset) // reset disables sprite
armed <= 0;
else if (aen && address==CTL) // writing CTL register disables sprite
armed <= 0;
else if (aen && address==DATA) // writing data register A arms sprite
armed <= 1;
end
//--------------------------------------------------------------------------------------
// generate load signal
always @(posedge clk)
if (clk7_en) begin
load <= armed && (hpos[7:0] == hstart[7:0]) && (fmode[15] || (hpos[8] == hstart[8])) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if (clk7_en) begin
load_del <= load;
end
//--------------------------------------------------------------------------------------
// POS register
always @(posedge clk)
if (clk7_en) begin
if (aen && address==POS)
hstart[8:1] <= data_in[7:0];
end
// CTL register
always @(posedge clk)
if (clk7_en) begin
if (aen && address==CTL)
{attach,hstart[0]} <= {data_in[7],data_in[0]};
end
// data register A
always @(posedge clk)
if (clk7_en) begin
if (aen && address==DATA)
datla[63:0] <= spr_fmode_dat;
end
// data register B
always @(posedge clk)
if (clk7_en) begin
if (aen && address==DATB)
datlb[63:0] <= spr_fmode_dat;
end
//--------------------------------------------------------------------------------------
// sprite shift register
always @(posedge clk)
if (clk7_en && load_del) // load new data into shift register
begin
shifta[63:0] <= datla[63:0];
shiftb[63:0] <= datlb[63:0];
end
else if (shift)
begin
shifta[63:0] <= {shifta[62:0],1'b0};
shiftb[63:0] <= {shiftb[62:0],1'b0};
end
// assign serialized output data
assign sprdata[1:0] = {shiftb[63],shifta[63]};
//--------------------------------------------------------------------------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; int ans[100009]; int cmp(int a, int b) { return a <= b; } int main() { int n; while (scanf( %d , &n) != EOF) { for (int i = 0; i < n; i++) scanf( %d , &ans[i]); sort(ans, ans + n); int vaule = 0; for (int i = 0; i < n; i++) { if (ans[i] > vaule) vaule++; } printf( %d n , vaule + 1); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 8; const int dxs[] = {2, 1, -1, -2, -2, -1, 1, 2}; const int dys[] = {-1, -2, -2, -1, 1, 2, 2, 1}; char s0[8], s1[8]; bool flds[N][N]; inline void readpos(char s[], int &x, int &y) { x = s[0] - a ; y = s[1] - 1 ; } inline void setknight(int x, int y) { for (int di = 0; di < 8; di++) { int vx = x + dxs[di], vy = y + dys[di]; if (vx >= 0 && vx < N && vy >= 0 && vy < N) flds[vy][vx] = true; } } int main() { scanf( %s%s , s0, s1); int rx, ry, kx, ky; readpos(s0, rx, ry); readpos(s1, kx, ky); flds[ry][rx] = flds[ky][kx] = true; for (int x = 0; x < N; x++) flds[ry][x] = true; for (int y = 0; y < N; y++) flds[y][rx] = true; setknight(kx, ky); setknight(rx, ry); int cnt = 0; for (int y = 0; y < N; y++) for (int x = 0; x < N; x++) if (!flds[y][x]) cnt++; printf( %d n , cnt); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; vector<int> level[MAXN]; vector<pair<int, int>> adj[MAXN]; vector<pair<int, pair<int, int>>> edges; int dp[MAXN], d[MAXN], prv[MAXN]; bool OnPath[MAXN]; int main() { int n, m, a, b, c, cnt = 0; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d%d , &a, &b, &c); adj[a].push_back(make_pair(b, c)); adj[b].push_back(make_pair(a, c)); edges.push_back({a, {b, c}}); cnt += c; } memset(d, -1, sizeof(d)); memset(dp, -1, sizeof(dp)); memset(prv, -1, sizeof(prv)); queue<int> q; d[1] = dp[1] = 0; q.push(1); while (!q.empty()) { int cur = q.front(); q.pop(); for (auto p : adj[cur]) { if (d[p.first] == -1) { d[p.first] = d[cur] + 1; q.push(p.first); } } } for (int i = 1; i <= n; i++) level[d[i]].push_back(i); for (int i = 1; i <= d[n]; i++) { for (int node : level[i]) { for (auto p : adj[node]) { int child = p.first; if (d[child] == i - 1 && dp[child] + p.second > dp[node]) { dp[node] = p.second + dp[child]; prv[node] = child; } } } } int cur = n; while (cur != -1) { OnPath[cur] = 1; cur = prv[cur]; } int k = d[n] - dp[n] + cnt - dp[n]; printf( %d n , k); for (int i = 0; i < m; i++) { a = edges[i].first, b = edges[i].second.first, c = edges[i].second.second; if (OnPath[a] && OnPath[b] && !c) printf( %d %d 1 n , a, b); if ((!OnPath[a] || !OnPath[b]) && c) printf( %d %d 0 n , a, b); } return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncrd_timeout.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_ncrd_timeout -- Determines transaction timeouts for out outstanding NCRD instructions on JBus.
// _____________________________________________________________________________
//
`include "sys.h"
module jbi_ncrd_timeout (/*AUTOARG*/
// Outputs
mout_nack, nack_error_id, mout_csr_err_read_to,
// Inputs
ncrd_sent, ncrd_id, rtn_data_seen, rtn_data_id, ncio_mout_nack_pop,
csr_jbi_log_enb_read_to, trans_timeout_timeval, clk, rst_l
);
// NCRD Tracking.
input ncrd_sent;
input [3:0] ncrd_id;
input rtn_data_seen;
input [3:0] rtn_data_id;
// Error reporting to jbi_min.
output mout_nack;
output [3:0] nack_error_id;
input ncio_mout_nack_pop;
// CSR Interface.
input csr_jbi_log_enb_read_to;
output mout_csr_err_read_to;
// Clock and reset.
input [31:0] trans_timeout_timeval; // tick counter interval.
input clk;
input rst_l;
// Wires and Regs.
wire tick, no_ncrds_outstanding, error_found;
wire [15:0] error, busy, error_reported;
wire [31:0] tick_cntr;
wire [3:0] scrub_id;
// Include functions: 4-to-16 Demultiplexer.
`include "jbi_demux_4to16.v"
// Tick counter.
wire [31:0] next_tick_cntr = (tick || no_ncrds_outstanding)? 1'b0: tick_cntr + 1'b1;
dffrl_ns #(32) tick_cntr_reg (.din(next_tick_cntr), .q(tick_cntr), .rst_l(rst_l), .clk(clk));
assign tick = (tick_cntr >= trans_timeout_timeval);
// 16 State machines. One for each possible outstanding NCRD that we issue.
wire [15:0] start = {16{ncrd_sent}} & jbi_demux_4to16(ncrd_id);
wire [15:0] stopnclear = ({16{rtn_data_seen}} & jbi_demux_4to16(rtn_data_id)) | error_reported[15:0];
//jbi_timer ncrd #(16) (
// .start (start[15:0]),
// .stopnclear (stopnclear[15:0]),
// .busy (busy[15:0]),
// .error (error[15:0]),
// .tick (tick),
// .clk (clk),
// .rst_l (rst_l)
// );
// (Needs a 'generate' statement badly.)
jbi_timer ncrd_15 (.start(start[15]), .stopnclear(stopnclear[15]), .busy(busy[15]), .error(error[15]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_14 (.start(start[14]), .stopnclear(stopnclear[14]), .busy(busy[14]), .error(error[14]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_13 (.start(start[13]), .stopnclear(stopnclear[13]), .busy(busy[13]), .error(error[13]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_12 (.start(start[12]), .stopnclear(stopnclear[12]), .busy(busy[12]), .error(error[12]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_11 (.start(start[11]), .stopnclear(stopnclear[11]), .busy(busy[11]), .error(error[11]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_10 (.start(start[10]), .stopnclear(stopnclear[10]), .busy(busy[10]), .error(error[10]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_09 (.start(start[ 9]), .stopnclear(stopnclear[ 9]), .busy(busy[ 9]), .error(error[ 9]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_08 (.start(start[ 8]), .stopnclear(stopnclear[ 8]), .busy(busy[ 8]), .error(error[ 8]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_07 (.start(start[ 7]), .stopnclear(stopnclear[ 7]), .busy(busy[ 7]), .error(error[ 7]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_06 (.start(start[ 6]), .stopnclear(stopnclear[ 6]), .busy(busy[ 6]), .error(error[ 6]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_05 (.start(start[ 5]), .stopnclear(stopnclear[ 5]), .busy(busy[ 5]), .error(error[ 5]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_04 (.start(start[ 4]), .stopnclear(stopnclear[ 4]), .busy(busy[ 4]), .error(error[ 4]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_03 (.start(start[ 3]), .stopnclear(stopnclear[ 3]), .busy(busy[ 3]), .error(error[ 3]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_02 (.start(start[ 2]), .stopnclear(stopnclear[ 2]), .busy(busy[ 2]), .error(error[ 2]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_01 (.start(start[ 1]), .stopnclear(stopnclear[ 1]), .busy(busy[ 1]), .error(error[ 1]), .tick(tick), .clk(clk), .rst_l(rst_l));
jbi_timer ncrd_00 (.start(start[ 0]), .stopnclear(stopnclear[ 0]), .busy(busy[ 0]), .error(error[ 0]), .tick(tick), .clk(clk), .rst_l(rst_l));
assign no_ncrds_outstanding = (busy[15:0] == 16'b0);
// Error reporting scrub machine.
wire errors_to_report = (error[15:0] != 16'b0);
wire [3:0] next_scrub_id = (!errors_to_report)? 1'b0:
(error_found)? scrub_id:
scrub_id + 1'b1;
dffrl_ns #(4) scrub_id_reg (.din(next_scrub_id), .q(scrub_id), .rst_l(rst_l), .clk(clk));
assign error_found = |(jbi_demux_4to16(scrub_id) & error[15:0]);
// Tell jbi_min block of error.
wire next_mout_nack = error_found && csr_jbi_log_enb_read_to;
dff_ns mout_nack_reg (.din(next_mout_nack), .q(mout_nack), .clk(clk));
assign nack_error_id = scrub_id;
// When jbi_min block acknowledges error, report to CSR logs.
assign mout_csr_err_read_to = ncio_mout_nack_pop;
// Clear the error.
assign error_reported[15:0] = {16{ncio_mout_nack_pop}} & jbi_demux_4to16(scrub_id);
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-module-parents:("jbi_mout_csr")
// End:
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Generated by harness_gen.py
* From: simpleuart.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 72;
localparam integer DOUT_N = 66;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
simpleuart dut(
.clk(clk),
.resetn(din[0]),
.ser_tx(dout[0]),
.ser_rx(din[1]),
.reg_div_we(din[5:2]),
.reg_div_di(din[37:6]),
.reg_div_do(dout[32:1]),
.reg_dat_we(din[38]),
.reg_dat_re(din[39]),
.reg_dat_di(din[71:40]),
.reg_dat_do(dout[64:33]),
.reg_dat_wait(dout[65])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, ans = 0; cin >> n; string x; cin >> x; for (long long int i = 0; i < x.length(); i++) { if (x[i] == 0 || x[i] == 2 || x[i] == 4 || x[i] == 6 || x[i] == 8 ) { ans += (i + 1); } } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; struct trie { trie* child[2]; int cnt; trie() { child[0] = child[1] = NULL; cnt = 0; } } * root; int n, k, sum; long long res; void add(int val) { trie* node = root; for (int i = 29; i >= 0; i--) { int j = (val >> i) & 1; if (!node->child[j]) node->child[j] = new trie; node = node->child[j]; node->cnt++; } } void get(trie* node, int i, int val, int remain) { if (i == -1) return; if (remain > (1 << (i + 1)) - 1) return; int j = (val >> i) & 1; if (node->child[j ^ 1]) { if ((1 << i) >= remain) res += node->child[j ^ 1]->cnt; else get(node->child[j ^ 1], i - 1, val, remain - (1 << i)); } if (node->child[j]) get(node->child[j], i - 1, val, remain); } int main(int argc, char const* argv[]) { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; root = new trie; add(0); for (int i = 1; i <= n; i++) { int a; cin >> a; sum ^= a; get(root, 29, sum, k); add(sum); } cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, x, a[200000]; long long bs(long long xx, long long yy, long long k) { long long m = (xx + yy) / 2; if (yy - xx <= 1) return xx; if (a[m] <= k) return bs(m, yy, k); else return bs(xx, m, k); } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); x = 1; for (int j = 0; j < 31; j++) { for (int i = 0; i < n; i++) { if (a[bs(0, n, a[i] - x)] == a[i] - x && a[bs(0, n, a[i] + x)] == a[i] + x) { return cout << 3 << endl << a[i] - x << << a[i] << << a[i] + x, 0; } } x *= 2; } x = 1; for (int j = 0; j < 31; j++) { for (int i = 0; i < n; i++) { if (a[bs(0, n, a[i] - x)] == a[i] - x) { return cout << 2 << endl << a[i] - x << << a[i], 0; } } x *= 2; } cout << 1 << endl << a[0]; return 0; }
|
#include <bits/stdc++.h> using namespace std; int H[100000][5], V[100000][5]; long long dp[32]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; for (int i = 1; i < m; ++i) for (int j = 0; j < n; ++j) cin >> H[i][j]; for (int i = 0; i < m; ++i) for (int j = 0; j < n; ++j) cin >> V[i][j]; for (int i = 1; i < (1 << n); ++i) dp[i] = 1e18; const int sz = 1 << n; for (int i = 1; i < m; ++i) { for (int j = 0; j < sz; ++j) { for (int k = 0; k < n; ++k) { if (!(j & (1 << k))) { auto &t = dp[j | (1 << k)]; const auto &nt = dp[j] + H[i][k]; if (nt < t) t = nt; } } for (int k = 0; k < n; ++k) { if ((((j >> k)) ^ ((j >> ((k + 1) % n)))) & 1) dp[j] += V[i][k]; } } } cout << dp[sz - 1] << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A21OI_PP_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxi = 1e6 + 6; int b, di; string a, c, t; pair<int, int> d[maxi], d1[maxi]; int ob[maxi]; int main() { cin >> b >> di; cin >> a; cin >> c; int n = a.size(); int m = c.size(); for (int i = 0; i < m; i++) { int id = 0; for (int j = 0; j < n; j++) if (c[i] == a[j]) id++; if (!id) { printf( %d n , 0); return 0; } } for (int i = 0; i < (m + 1); i++) t += a; int cur = 0; for (int j = 0; j < n; j++) { cur = 0; for (int i = j; i < (m + 1) * n; i++) { if (c[cur] == t[i]) cur++; if (cur == m) { d[j] = {i / n, i % n}; break; } } } for (int j = 0; j < n; j++) { int posl = -1; int cur = 0; int tt = 0; for (int k = j; k < n; k++) { if (a[k] == c[cur]) cur++; if (cur == m) { posl = k; cur = 0; tt++; } } d1[j] = {tt, posl}; } int tot = 0; int ans = 0; int c1 = 0; while (ans < b) { if (d[c1].first > 0) { tot++; ans += d[c1].first; c1 = d[c1].second; c1++; if (c1 == n) { c1 -= n; ans++; if (ans == b) { printf( %d n , tot / di); return 0; } } } else { tot += d1[c1].first; c1 = d1[c1].second; c1++; if (c1 == n) { c1 -= n; ans++; if (ans == b) { printf( %d n , tot / di); return 0; } } } } tot--; cout << tot / di << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long int n, a[101][101] = {0}, d = 0; cin >> n; for (long long int i = 1; i <= n; i++) { long long int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; for (long long int j = x1; j <= x2; j++) { for (long long int k = y1; k <= y2; k++) { d++; } } } cout << d << endl; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_LP_V
`define SKY130_FD_SC_LP__O311A_LP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311a_lp (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_LP_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { while (b) { int r = a % b; a = b; b = r; } return a; } int64_t lcm(int a, int b) { return 1LL * a * b / gcd(a, b); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<int> next(n + 1); for (int i = 1; i <= n; i++) cin >> next[i]; int64_t ans = 1; vector<bool> cycle(n + 1); for (int i = 1; i <= n; i++) if (!cycle[i]) { int node = i; vector<int> vis(n + 1); for (int j = 0; j < n + 1; j++) { vis[node]++; node = next[node]; } if (vis[i] >= 2) { int len = 0, node = i; while (!cycle[node]) { len++; cycle[node] = true; node = next[node]; } ans = lcm(ans, len); } } int mx = 0; for (int i = 1; i <= n; i++) if (!cycle[i]) { int dist = 0, node = i; while (!cycle[node]) { dist++; node = next[node]; } mx = max(mx, dist); } int it = 1; while (it * ans < mx) it++; cout << it * ans << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, p[200001], bl, cnt, cntbl, visited[200001], flag; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> p[i]; } for (int i = 1; i <= n; i++) { if (!visited[i]) { int j = i, tmp = j; while (!visited[j]) { visited[j] = 1; j = p[j]; } if (j != tmp) flag = 1; cnt++; } } for (int i = 0; i < n; i++) { cin >> bl; if (bl) cntbl++; } cout << ((cnt == 1 && !flag ? 0 : cnt) + (cntbl % 2 == 0 ? 1 : 0)); return 0; }
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