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#include <bits/stdc++.h> using namespace std; const int maxn = 500010; int n, m; char a[maxn], b[maxn]; char s[maxn * 2], c[maxn * 3]; int z[maxn * 3]; int lcp[maxn]; int lcs[maxn]; void z_init(int len) { int l = 1, r = 1; z[1] = len; for (int i = 2; i <= len; i++) { if (i > r) { l = i; r = i; while (r <= len && c[r - i + 1] == c[r]) r++; z[i] = r - l; r--; } else { int k = i - l + 1; if (z[k] < r - i + 1) z[i] = z[k]; else { l = i; while (r <= len && c[r - i + 1] == c[r]) r++; z[i] = r - l; r--; } } } } void init() { for (int i = 1; i <= m; i++) c[i] = s[i]; c[m + 1] = # ; for (int i = 1; i <= n; i++) c[m + 1 + i] = a[i]; c[n + m + 2] = 0 ; z_init(n + m + 1); for (int i = 1; i <= n; i++) lcp[i] = z[m + 1 + i]; for (int i = 1; i <= m; i++) c[i] = s[m + 1 - i]; c[m + 1] = # ; for (int i = 1; i <= n; i++) c[m + 1 + i] = b[n + 1 - i]; c[n + m + 2] = 0 ; z_init(n + m + 1); for (int i = 1; i <= n; i++) lcs[i] = z[m + 1 + n + 1 - i]; } long long cnt[maxn * 2], sum[maxn * 2]; int lowbit(int x) { return x & (-x); } void add(int v) { int x = v; while (x <= n) sum[x] += v, cnt[x]++, x += lowbit(x); } void sub(int v) { int x = v; while (x <= n) sum[x] -= v, cnt[x]--, x += lowbit(x); } long long get_sum(int x) { long long res = 0; while (x) res += sum[x], x -= lowbit(x); return res; } long long get_cnt(int x) { long long res = 0; while (x) res += cnt[x], x -= lowbit(x); return res; } int main() { scanf( %d%d , &n, &m); scanf( %s%s%s , a + 1, b + 1, s + 1); init(); long long ans = 0; for (int i = 1; i <= min(n, m - 1); i++) add(max(1, m - lcs[i])); for (int i = 1, r; i <= n; i++) { r = min(m - 1, lcp[i]); ans += 1LL * (r + 1) * get_cnt(r) - get_sum(r); sub(max(1, m - lcs[i])); if (i + m - 1 <= n) add(max(1, m - lcs[i + m - 1])); } printf( %I64d n , ans); }
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// Copyright (c) 2015 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Report & assert tests.
module vhdl_report_test;
logic start_test;
vhdl_report dut(start_test);
int a;
initial begin
// as of the moment of writing vhdlpp does not handle procedure calls
a = vhdl_report_pkg::test_asserts(0);
start_test = 1'b0;
#1 start_test = 1'b1;
end
endmodule
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#include <bits/stdc++.h> using namespace std; int n, m, x, q[100100]; char t; vector<int> d; bool used[100100]; void calc(int x) { d.resize(0); for (int i = 2; i * i <= x; i++) if (x % i == 0) { while (x % i == 0) x /= i; d.push_back(i); } if (x != 1) d.push_back(x); } int main() { scanf( %d%d n , &n, &m); memset((used), (false), sizeof((used))); memset((q), (0), sizeof((q))); for (int i = 0; i < (m); i++) { while (t = getchar(), t != + && t != - ) ; scanf( %d , &x); if (t == + ) { if (used[x]) { puts( Already on ); continue; } calc(x); bool ok = true; for (int j = 0; j < (d.size()); j++) if (q[d[j]]) { printf( Conflict with %d n , q[d[j]]); ok = false; break; } if (ok) { for (int j = 0; j < (d.size()); j++) q[d[j]] = x; used[x] = true; puts( Success ); } } else { if (!used[x]) { puts( Already off ); continue; } used[x] = false; calc(x); for (int j = 0; j < (d.size()); j++) q[d[j]] = 0; puts( Success ); } } }
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// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/14.1/ip/merlin/altera_avalon_mm_clock_crossing_bridge/altera_avalon_mm_clock_crossing_bridge.v#1 $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM clock crossing bridge
//
// Clock crosses MM commands and responses with the
// help of asynchronous FIFOs.
//
// This bridge will stop emitting read commands when
// too many read commands are in flight to avoid
// response FIFO overflow.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_clock_crossing_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter COMMAND_FIFO_DEPTH = 4,
parameter RESPONSE_FIFO_DEPTH = 4,
parameter MASTER_SYNC_DEPTH = 2,
parameter SLAVE_SYNC_DEPTH = 2,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input s0_clk,
input s0_reset,
input m0_clk,
input m0_reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
localparam CMD_WIDTH = BURSTCOUNT_WIDTH + DATA_WIDTH + HDL_ADDR_WIDTH
+ BYTEEN_WIDTH
+ 3; // read, write, debugaccess
localparam NUMSYMBOLS = DATA_WIDTH / SYMBOL_WIDTH;
localparam RSP_WIDTH = DATA_WIDTH;
localparam MAX_BURST = (1 << (BURSTCOUNT_WIDTH-1));
localparam COUNTER_WIDTH = log2ceil(RESPONSE_FIFO_DEPTH) + 1;
localparam NON_BURSTING = (MAX_BURST == 1);
localparam BURST_WORDS_W = BURSTCOUNT_WIDTH;
// --------------------------------------
// Signals
// --------------------------------------
wire [CMD_WIDTH-1:0] s0_cmd_payload;
wire [CMD_WIDTH-1:0] m0_cmd_payload;
wire s0_cmd_valid;
wire m0_cmd_valid;
wire m0_internal_write;
wire m0_internal_read;
wire s0_cmd_ready;
wire m0_cmd_ready;
reg [COUNTER_WIDTH-1:0] pending_read_count;
wire [COUNTER_WIDTH-1:0] space_avail;
wire stop_cmd;
reg stop_cmd_r;
wire m0_read_accepted;
wire m0_rsp_ready;
reg old_read;
wire [BURST_WORDS_W-1:0] m0_burstcount_words;
// --------------------------------------
// Command FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (CMD_WIDTH),
.FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.WR_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.RD_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.BACKPRESSURE_DURING_RESET (1)
)
cmd_fifo
(
.in_clk (s0_clk),
.in_reset_n (~s0_reset),
.out_clk (m0_clk),
.out_reset_n (~m0_reset),
.in_data (s0_cmd_payload),
.in_valid (s0_cmd_valid),
.in_ready (s0_cmd_ready),
.out_data (m0_cmd_payload),
.out_valid (m0_cmd_valid),
.out_ready (m0_cmd_ready),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty (1'b0),
.in_error (1'b0),
.in_channel (1'b0),
.in_csr_address (1'b0),
.in_csr_read (1'b0),
.in_csr_write (1'b0),
.in_csr_writedata (32'b0),
.out_csr_address (1'b0),
.out_csr_read (1'b0),
.out_csr_write (1'b0),
.out_csr_writedata (32'b0)
);
// --------------------------------------
// Command payload
// --------------------------------------
assign s0_waitrequest = ~s0_cmd_ready;
assign s0_cmd_valid = s0_write | s0_read;
assign s0_cmd_payload = {s0_address,
s0_burstcount,
s0_read,
s0_write,
s0_writedata,
s0_byteenable,
s0_debugaccess};
assign {m0_address,
m0_burstcount,
m0_internal_read,
m0_internal_write,
m0_writedata,
m0_byteenable,
m0_debugaccess} = m0_cmd_payload;
assign m0_cmd_ready = ~m0_waitrequest &
~(m0_internal_read & stop_cmd_r & ~old_read);
assign m0_write = m0_internal_write & m0_cmd_valid;
assign m0_read = m0_internal_read & m0_cmd_valid & (~stop_cmd_r | old_read);
assign m0_read_accepted = m0_read & ~m0_waitrequest;
// ---------------------------------------------
// the non-bursting case
// ---------------------------------------------
generate if (NON_BURSTING)
begin
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count + 1;
end
end
end
// ---------------------------------------------
// the bursting case
// ---------------------------------------------
else begin
assign m0_burstcount_words = m0_burstcount;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
pending_read_count <= 0;
end
else begin
if (m0_read_accepted & m0_readdatavalid)
pending_read_count <= pending_read_count +
m0_burstcount_words - 1;
else if (m0_readdatavalid)
pending_read_count <= pending_read_count - 1;
else if (m0_read_accepted)
pending_read_count <= pending_read_count +
m0_burstcount_words;
end
end
end
endgenerate
assign stop_cmd = (pending_read_count + 2*MAX_BURST) > space_avail;
always @(posedge m0_clk, posedge m0_reset) begin
if (m0_reset) begin
stop_cmd_r <= 1'b0;
old_read <= 1'b0;
end
else begin
stop_cmd_r <= stop_cmd;
old_read <= m0_read & m0_waitrequest;
end
end
// --------------------------------------
// Response FIFO
// --------------------------------------
(* altera_attribute = "-name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON" *) altera_avalon_dc_fifo
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (RSP_WIDTH),
.FIFO_DEPTH (RESPONSE_FIFO_DEPTH),
.WR_SYNC_DEPTH (SLAVE_SYNC_DEPTH),
.RD_SYNC_DEPTH (MASTER_SYNC_DEPTH),
.USE_SPACE_AVAIL_IF (1)
)
rsp_fifo
(
.in_clk (m0_clk),
.in_reset_n (~m0_reset),
.out_clk (s0_clk),
.out_reset_n (~s0_reset),
.in_data (m0_readdata),
.in_valid (m0_readdatavalid),
// ------------------------------------
// must never overflow, or we're in trouble
// (we cannot backpressure the response)
// ------------------------------------
.in_ready (m0_rsp_ready),
.out_data (s0_readdata),
.out_valid (s0_readdatavalid),
.out_ready (1'b1),
.space_avail_data (space_avail),
.in_startofpacket (1'b0),
.in_endofpacket (1'b0),
.in_empty (1'b0),
.in_error (1'b0),
.in_channel (1'b0),
.in_csr_address (1'b0),
.in_csr_read (1'b0),
.in_csr_write (1'b0),
.in_csr_writedata (32'b0),
.out_csr_address (1'b0),
.out_csr_read (1'b0),
.out_csr_write (1'b0),
.out_csr_writedata (32'b0)
);
// synthesis translate_off
always @(posedge m0_clk) begin
if (~m0_rsp_ready & m0_readdatavalid) begin
$display("%t %m: internal error, response fifo overflow", $time);
end
if (pending_read_count > space_avail) begin
$display("%t %m: internal error, too many pending reads", $time);
end
end
// synthesis translate_on
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); if (n % 2) printf( black n ); else printf( white n1 2 n ); }
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#include <bits/stdc++.h> using namespace std; const int N = 15e4 + 5; int n, b[N]; long long a[N]; int prev(int x) { int y = x - 1; if (y == 0) y = n; return y; } int nxt(int x) { return x % n + 1; } int main() { scanf( %d , &n); bool f = true; for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 2; i <= n; i++) if (b[i] != b[i - 1]) f = false; if (f) { if (b[1] != 0) return !printf( NO ); puts( YES ); for (int i = 1; i <= n; i++) printf( %d , 3122002); return 0; } int pos; for (int i = 1; i <= n; i++) { if (b[i] > b[prev(i)]) { pos = i; break; } } a[pos] = b[pos]; for (int i = pos - 1; i >= 1; i--) { int k = max(1LL, (b[prev(i)] - b[i] + a[nxt(i)]) / a[nxt(i)]); a[i] = 1LL * a[nxt(i)] * k + b[i]; } for (int i = n; i > pos; i--) { int k = max(1LL, (b[prev(i)] - b[i] + a[nxt(i)]) / a[nxt(i)]); a[i] = 1LL * a[nxt(i)] * k + b[i]; } puts( YES ); for (int i = 1; i <= n; i++) printf( %lld , a[i]); return 0; }
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#include <bits/stdc++.h> using namespace std; char str[25][25]; int cost[25][25]; const int maxc = 1 << 20; int dp[maxc]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , str + i); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) scanf( %d , &cost[i][j]); } int total = (1 << n) - 1; memset(dp, -1, sizeof(dp)); dp[0] = 0; for (int i = 0; i < total; i++) { if (dp[i] == -1) continue; int j = 0; while (((i >> j) & 1) == 1) j++; for (int k = 0; k < m; k++) { int cnt = 0, sumc = 0, maxc = 0, tmp = 0; for (int z = 0; z < n; z++) { if (str[z][k] == str[j][k]) { cnt++; sumc += cost[z][k]; maxc = max(maxc, cost[z][k]); tmp |= (1 << z); } } if (cnt == 1) { if (dp[i | (1 << j)] == -1) dp[i | (1 << j)] = dp[i]; else dp[i | (1 << j)] = min(dp[i | (1 << j)], dp[i]); } else { if (dp[i | (1 << j)] == -1) dp[i | (1 << j)] = dp[i] + cost[j][k]; else dp[i | (1 << j)] = min(dp[i | (1 << j)], dp[i] + cost[j][k]); if (dp[i | tmp] == -1) dp[i | tmp] = dp[i] + sumc - maxc; else dp[i | tmp] = min(dp[i | tmp], dp[i] + sumc - maxc); } } } printf( %d n , dp[total]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23.02.2016 23:02:44
// Design Name:
// Module Name: can_controller_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module can_controller_testbench();
reg GCLK;
reg RES;
wire CAN;
reg [107:0] DIN1;
wire [107:0] DOUT1;
reg tx_start1;
wire tx_ready1;
wire rx_ready1;
reg [107:0] DIN2;
wire [107:0] DOUT2;
reg tx_start2;
wire tx_ready2;
wire rx_ready2;
pullup(CAN);
always
#10 GCLK = ~GCLK;
initial
begin
GCLK = 1'b0;
RES = 1'b0;
#20
DIN1 = "HI";
DIN2 = "LOL";
#100
tx_start1 = 1'b1;
tx_start2 = 1'b1;
#46000
tx_start1 = 1'b0;
tx_start2 = 1'b0;
#100000
$finish;
end
can_controller CC1
(
.GCLK(GCLK),
.RES(RES),
.CAN(CAN),
.DIN(DIN1),
.DOUT(DOUT1),
.tx_start(tx_start1),
.tx_ready(tx_ready1),
.rx_ready(rx_ready1)
);
can_controller CC2
(
.GCLK(GCLK),
.RES(RES),
.CAN(CAN),
.DIN(DIN2),
.DOUT(DOUT2),
.tx_start(tx_start2),
.tx_ready(tx_ready2),
.rx_ready(rx_ready2)
);
endmodule
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
parameter N = 4;
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [N-1:0] intf_input,
a_if.source i_intf_source[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [N-1:0] a_out,
a_if.sink i_intf_sink[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
a_if #(.PARAM(1)) tl_intf [N-1:0] ();
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 03:23:40 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_stub.v
// Design : design_1_axi_intc_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_intc,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, irq)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[0:0],irq" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [0:0]intr;
output irq;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, p, cnt, r[1010]; pair<int, int> c[1010]; bool check[1010]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> c[i].second >> c[i].first; if (c[i].second > c[i].first) swap(c[i].second, c[i].first); } sort(c, c + n); while (1) { int i = 0; for (i = 0; i < n; i++) if (!check[i]) break; if (i == n) break; r[cnt] = c[i].first; for (i = 0; i < n; i++) if (c[i].first >= r[cnt] && c[i].second <= r[cnt]) check[i] = true; cnt++; } cout << cnt << endl; for (int i = 0; i < cnt; i++) cout << r[i] << ; cout << endl; return 0; }
|
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module ram #(
parameter DATA = 198,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem [(2**ADDR)-1:0];
initial begin : init
integer i;
for(i = 0; i < (2**ADDR); i = i + 1)
mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long ans = 0, now, a[14], b[14]; for (int i = 0; i < 14; i++) cin >> a[i]; for (int i = 0; i < 14; i++) { if (a[i] != 0) { for (int j = 0; j < 14; j++) b[j] = a[j]; int r = b[i] % 14, q = b[i] / 14; b[i] = 0; for (int j = 0; j < 14; j++) b[j] += q; for (int j = 1; j <= r; j++) b[(i + j) % 14]++; now = 0; for (int j = 0; j < 14; j++) if (b[j] % 2 == 0) now += b[j]; ans = max(ans, now); } } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 10; long long n; pair<char, long long> ar[N]; vector<long long> vec; set<long long> st; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; n *= 2; for (long long i = 0; i < n; i++) { char c; long long x; cin >> c; if (c == + ) ar[i].first = c; else { cin >> x; ar[i] = {c, x}; } } bool check = 1; for (long long i = 0; i < n; i++) { if (ar[i].first == + ) vec.push_back(i); else { if (!vec.size()) { check = 0; break; } long long indx = vec.back(); vec.pop_back(); ar[indx].second = ar[i].second; } } if (!check) return cout << NO n , 0; for (long long i = 0; i < n; i++) if (ar[i].first == + ) st.insert(ar[i].second); else { if (!st.size()) { check = 0; break; } long long x = (*st.begin()); st.erase(x); if (x != ar[i].second) { check = 0; break; } } if (!check) return cout << NO n , 0; cout << YES n ; for (long long i = 0; i < n; i++) if (ar[i].first == + ) cout << ar[i].second << ; cout << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:00:14 05/19/2015
// Design Name:
// Module Name: display2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display2(
input wire clk,
input wire rst,
input wire [31:0] instr,
input wire [31:0] reg_data,
input wire [31:0] stage,
input wire [7:0] clk_cnt,
input wire [7:0] reg_addr,
output wire lcd_e,
output wire lcd_rs,
output wire lcd_rw,
output wire [3:0] lcd_dat
);
reg [255:0] strdata = "";
wire [95:0] datain = {instr,reg_data,stage};
function [7:0] num2str;
input [3:0] number;
begin
if(number < 10)
num2str = "0" + number;
else
num2str = "A" - 10 + number;
end
endfunction
//instr
genvar i;
generate for (i=0; i<24; i=i+1) begin: NUM2STR
always @(posedge clk) begin
strdata[8*i+71-:8] <= num2str(datain[4*i+3-:4]);
end
end
endgenerate
generate for (i=0; i<2; i=i+1) begin: NUM2STR2
always @(posedge clk) begin
strdata[8*i+39-:8] <= num2str(clk_cnt[4*i+3-:4]);
end
end
endgenerate
generate for (i=0; i<2; i=i+1) begin: NUM2STR3
always @(posedge clk) begin
strdata[8*i+7-:8] <= num2str(reg_addr[4*i+3-:4]);
end
end
endgenerate
reg refresh = 0;
// reg [7:0] addr_buf;
// reg [31:0] data_buf;
reg [127:0] datain_buf;
reg [7:0] clk_cnt_buf;
reg [7:0] reg_addr_buf;
always @(posedge clk) begin
datain_buf <= datain;
clk_cnt_buf <= clk_cnt;
reg_addr_buf <= reg_addr;
refresh <= (datain_buf != datain) | (clk_cnt_buf != clk_cnt) | (reg_addr_buf != reg_addr);
end
displcd DISPLCD (
.CCLK(clk),
.reset(rst | refresh),
.strdata(strdata),
.rslcd(lcd_rs),
.rwlcd(lcd_rw),
.elcd(lcd_e),
.lcdd(lcd_dat)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using nagai = long long; using ll = long long; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int c = 0; int t = 1; while (t <= n) { n -= t, ++c, t *= 2; } if (n) ++c; cout << c << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> edges; vector<int> large; bool ok = true; vector<pair<long long, long long>> dfs(int cur) { vector<pair<long long, long long>> child; for (int i : edges[cur]) { auto temp = dfs(i); child.insert(child.end(), temp.begin(), temp.end()); } sort(child.begin(), child.end()); vector<pair<long long, long long>> res; int add = 0; if (large[cur] > child.size()) { ok = false; } for (auto it : child) { if (res.size() == large[cur]) { res.push_back({res.size() + 1, cur}); } res.push_back({res.size() + 1, it.second}); } if (res.size() == child.size()) { res.push_back({res.size() + 1, cur}); } return res; } void solve() { int n; cin >> n; edges.clear(); edges.resize(n + 1); vector<pair<long long, long long>> in(n); for (auto& it : in) { cin >> it.first >> it.second; } int par = -1; large.clear(); large.resize(n + 1); for (int i = 0; i < n; i++) { if (in[i].first != 0) { edges[in[i].first].push_back(i + 1); } else { par = i + 1; } large[i + 1] = in[i].second; } auto res = dfs(par); if (!ok) { cout << NO << endl; return; } cout << YES << endl; for (auto it : res) { large[it.second] = it.first; } for (int i = 1; i <= n; i++) { cout << large[i] << ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } }
|
`timescale 1ns / 1ps
module control_unit();
parameter ADDR_SIZE = 12;
parameter WORD_SIZE = 16;
reg sysclk;
initial begin //clock
sysclk <= 1'b1;
forever #1 sysclk = ~sysclk;
end
initial begin
$dumpfile("control_unit.vcd");
$dumpvars;
end
/*
* Instructions:
* 0: ACC := [S]
* 1: [S] := ACC
* 2: ACC:= ACC + [S]
* 3: ACC := ACC - [S]
* 4: PC := S
* 5: PC := S if ACC >=0
* 6: PC :=S if ACC != 0
* 7: HALT
* 8: [SP] := ACC, SP := SP + 1
* 9: ACC := [SP], SP := SP - 1
* a: IP := S, [SP] := IP, SP := SP + 1
* b: IP := [SP - 1], SP := SP - 1
* /
/*
* Specifications:
* posedge: exec
* negedge: fetch
*/
//Registers
reg [WORD_SIZE-1:0] acc;
reg [ADDR_SIZE-1:0] ip;
reg [WORD_SIZE-1:0] ir;
reg [ADDR_SIZE-1:0] sp;
//Memory
reg [ADDR_SIZE-1:0] mem_addr;
reg [WORD_SIZE-1:0] mem_in;
wire [WORD_SIZE-1:0] mem_out;
wire [WORD_SIZE-1:0] rom_out;
reg mem_write;
ram ram_blk(
.clk(sysclk),
.addr(mem_addr),
.data_in(mem_in),
.write_en(mem_write),
.data_out(mem_out),
.rom_addr(ip),
.rom_out(rom_out)
);
initial begin //default register values
ir <= 16'h4000;
ip <= 0;
sp <= 12'd191; //64 word stack
mem_addr <= 0;
mem_in <= 0;
mem_write <= 0;
acc <= 0;
end
//0/1 -> Fetch/Exec
reg state = 1;
//Determine pop operations
wire pop_op;
assign pop_op = (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'h9)
| (rom_out[WORD_SIZE-1:WORD_SIZE-4] == 4'hb);
always @(posedge sysclk) begin
state <= ~state; //Alternate state
if (state) begin //Exec
case (ir[WORD_SIZE-1:WORD_SIZE-4])
4'h0: begin //ACC := [S]
acc <= mem_out;
end
4'h1: begin //[S] := ACC
mem_in <= acc;
mem_addr <= ir[WORD_SIZE-5:0];
mem_write <= 1;
end
4'h2: begin //ACC:= ACC + [S]
acc <= acc + mem_out;
end
4'h3: begin //ACC := ACC - [S]
acc <= acc - mem_out;
end
4'h4: begin // PC := S
ip <= ir[WORD_SIZE-5:0];
end
4'h5: begin //PC := S if ACC >=0
if (acc[WORD_SIZE-1] == 1'b0)
ip <= ir[WORD_SIZE-5:0];
end
4'h6: begin //PC := S if ACC != 0
if (acc != 8'd0)
ip <= ir[WORD_SIZE-5:0];
end
4'h7: begin // HALT
$finish;
end
4'h8: begin // [SP] := ACC, SP := SP + 1
mem_addr <= sp;
mem_in <= acc;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'h9: begin // ACC := [SP - 1], SP := SP - 1
acc <= mem_out;
sp <= sp - 12'b1;
end
4'ha: begin // IP := S, [SP] := IP, SP := SP + 1
ip <= mem_addr ;
mem_addr <= sp;
mem_in <= ip;
mem_write <= 1;
sp <= sp + 12'b1;
end
4'hb: begin // IP := [SP - 1], SP := SP - 1
ip <= mem_out;
sp <= sp - 12'b1;
end
default: $finish;
endcase
end
else begin //Fetch
ir <= rom_out;
ip <= ip + 1;
mem_write <= 0;
//Get stack if pop/return
if (pop_op) //
mem_addr <= (sp - 12'b1);
else //Get memory
mem_addr <= rom_out[WORD_SIZE-5:0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; int n, x1, x2; pair<int, int> c[N], f[2]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> x1 >> x2; for (int i = 0; i < n; i++) cin >> c[i].first, c[i].second = i; sort(c, c + n); int i = n - 1; for (; ~i; --i) if (i + (x1 + c[i].first - 1) / c[i].first - 1 < n) { f[0] = {i, i + (x1 + c[i].first - 1) / c[i].first}; break; } int j = i; for (; ~i; --i) if (i + (x2 + c[i].first - 1) / c[i].first - 1 < j) { f[1] = {i, i + (x2 + c[i].first - 1) / c[i].first}; break; } if (i >= 0) { cout << Yes n ; cout << f[0].second - f[0].first << << f[1].second - f[1].first << n ; for (; f[0].first < f[0].second; f[0].first++) cout << c[f[0].first].second + 1 << ; cout << n ; for (; f[1].first < f[1].second; f[1].first++) cout << c[f[1].first].second + 1 << ; return 0; } i = n - 1; for (; ~i; --i) if (i + (x2 + c[i].first - 1) / c[i].first - 1 < n) { f[1] = {i, i + (x2 + c[i].first - 1) / c[i].first}; break; } j = i; for (; ~i; --i) if (i + (x1 + c[i].first - 1) / c[i].first - 1 < j) { f[0] = {i, i + (x1 + c[i].first - 1) / c[i].first}; break; } if (i >= 0) { cout << Yes n ; cout << f[0].second - f[0].first << << f[1].second - f[1].first << n ; for (; f[0].first < f[0].second; f[0].first++) cout << c[f[0].first].second + 1 << ; cout << n ; for (; f[1].first < f[1].second; f[1].first++) cout << c[f[1].first].second + 1 << ; return 0; } cout << No ; return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 3853 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w2,
w259,
w4112,
w3853;
assign w1 = i_data0;
assign w2 = w1 << 1;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w259 = w257 + w2;
assign w3853 = w4112 - w259;
assign w4112 = w257 << 4;
assign o_data0 = w3853;
//multiplier_block area estimate = 5585.02562337059;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T &chmin(T &a, const T &b) { return a = min(a, b); } template <typename T> T &chmax(T &a, const T &b) { return a = max(a, b); } template <typename T> T gcd(const T a, const T b) { return b ? gcd(b, a % b) : a; } template <typename T> T lcm(const T a, const T b) { return a / gcd(a, b) * b; } template <typename T> T ceil(const T a, const T b) { return (a + b - 1) / b; } template <typename T> long double dist(const T x1, const T y1, const T x2, const T y2) { long double x = x1 - x2; long double y = y1 - y2; return sqrt(x * x + y * y); } template <typename T> void aout(const T *a, const int n) { for (int i = 0; i < (n); ++i) cout << a[i] << ; cout << n ; } template <typename T> void vout(const vector<T> &v) { for (int i = 0; i < ((int)(v).size()); ++i) cout << v[i] << ; cout << n ; } const int di4[4] = {-1, 0, 1, 0}; const int dj4[4] = {0, 1, 0, -1}; const int di8[8] = {-1, -1, 0, 1, 1, 1, 0, -1}; const int dj8[8] = {0, 1, 1, 1, 0, -1, -1, -1}; const int dik[8] = {2, 1, -1, -2, -2, -1, 1, 2}; const int djk[8] = {1, 2, 2, 1, -1, -2, -2, -1}; const int maxn = 100100; const int mod = 1e9 + 7; const int inf = INT_MAX; const long double eps = 1e-9; const long double pi = acos(-1.0); int n; void solve() { cin >> n; long long ans = (long long)(n - 2) * (n - 2); cout << (ans) << n ; } void init() {} int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.precision(10); cout << fixed; int tc = 1; for (int i = 1; i <= (tc); ++i) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; unsigned long long f(unsigned long long x, int b) { for (int i = 0; i < 64; i++) if (__builtin_popcountll(x) < b) x |= 1ULL << i; return x; } unsigned long long brute(unsigned long long l, unsigned long long r) { unsigned long long ret = l; for (unsigned long long i = l; i <= r; i++) if (__builtin_popcountll(i) > __builtin_popcountll(ret)) ret = i; return ret; } int main() { int T; scanf( %d , &T); unsigned long long a, b; while (T--) { scanf( %llu%llu , &a, &b); unsigned long long ans = a; for (int i = __builtin_popcountll(a) + 1; i < 64; i++) { unsigned long long v = f(a, i); if (v <= b) ans = v; } printf( %lld n , ans); } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_FUNCTIONAL_PP_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2015/02/08 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// final sub module for text
module study_text
(
input wire clk,
input wire [9:0] pix_x, pix_y,
output wire [3:0] study_on,
output reg [2:0] study_rgb
// we output text_rgb only because we have to select it according to FSM
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_r;
// char_addr is the final address selected by MUX
// s stands for score (and ball, but I can not use sb...)
// l stands for logo (well, our special plalindrome logo WPPW)
// r stands for registration information (in this case, student ID and name)
// o stands for over (actually game over I assume, anyway)
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire word_on, font_bit;
wire [5:0] word_rom_addr;
wire [3:0] row_addr_r;
wire [2:0] bit_addr_r;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
assign word_on = (pix_x[9:7]==2) && (pix_y[9:6]==2);
assign row_addr_r = pix_y[3:0];
assign bit_addr_r = pix_x[2:0];
assign word_rom_addr = {pix_y[5:4], pix_x[6:3]};
always @*
case (word_rom_addr)
// row 1 generated by MATLAB
6'h00: char_addr_r = 7'h62;
6'h01: char_addr_r = 7'h6f;
6'h02: char_addr_r = 7'h79;
6'h03: char_addr_r = 7'h20;
6'h04: char_addr_r = 7'h20;
6'h05: char_addr_r = 7'h20;
6'h06: char_addr_r = 7'h20;
6'h07: char_addr_r = 7'h20;
6'h08: char_addr_r = 7'h20;
6'h09: char_addr_r = 7'h20;
6'h0A: char_addr_r = 7'h20;
6'h0B: char_addr_r = 7'h20;
6'h0C: char_addr_r = 7'h20;
6'h0D: char_addr_r = 7'h20;
// visualization
// well
6'h0E: char_addr_r = 7'h20;
6'h0F: char_addr_r = 7'h20;
// row 2
6'h10: char_addr_r = 7'h67;
6'h11: char_addr_r = 7'h69;
6'h12: char_addr_r = 7'h72;
6'h13: char_addr_r = 7'h6c;
6'h14: char_addr_r = 7'h20;
6'h15: char_addr_r = 7'h20;
6'h16: char_addr_r = 7'h20;
6'h17: char_addr_r = 7'h20;
6'h18: char_addr_r = 7'h20;
6'h19: char_addr_r = 7'h20;
6'h1A: char_addr_r = 7'h20;
6'h1B: char_addr_r = 7'h20;
6'h1C: char_addr_r = 7'h20;
6'h1D: char_addr_r = 7'h20;
// visualization
// well
6'h1E: char_addr_r = 7'h20;
6'h1F: char_addr_r = 7'h20;
// row 3
6'h20: char_addr_r = 7'h63;
6'h21: char_addr_r = 7'h61;
6'h22: char_addr_r = 7'h74;
6'h23: char_addr_r = 7'h20;
6'h24: char_addr_r = 7'h20;
6'h25: char_addr_r = 7'h20;
6'h26: char_addr_r = 7'h20;
6'h27: char_addr_r = 7'h20;
6'h28: char_addr_r = 7'h20;
6'h29: char_addr_r = 7'h20;
6'h2A: char_addr_r = 7'h20;
6'h2B: char_addr_r = 7'h20;
6'h2C: char_addr_r = 7'h20;
6'h2D: char_addr_r = 7'h20;
// visualization
// well
6'h2E: char_addr_r = 7'h20;
6'h2F: char_addr_r = 7'h20;
// row 4
6'h30: char_addr_r = 7'h20;
6'h31: char_addr_r = 7'h20;
6'h32: char_addr_r = 7'h20;
6'h33: char_addr_r = 7'h20;
6'h34: char_addr_r = 7'h20;
6'h35: char_addr_r = 7'h20;
6'h36: char_addr_r = 7'h20;
6'h37: char_addr_r = 7'h20;
6'h38: char_addr_r = 7'h20;
6'h39: char_addr_r = 7'h20;
6'h3A: char_addr_r = 7'h20;
6'h3B: char_addr_r = 7'h20;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20;
endcase
//-------------------------------------------
// game over region
// - display "Game Over" at center
// - scale to 32-by-64 fonts
//-----------------------------------------
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
// you can adjust color here
always @*
begin
study_rgb = 3'b110; // background, yellow
if (word_on)
begin
char_addr = char_addr_r;
row_addr = row_addr_r;
bit_addr = bit_addr_r;
if (font_bit)
study_rgb = 3'b001;
end
end
assign study_on = word_on;
//-------------------------------------------
// font rom interface (well)
//-------------------------------------------
// just concatenation
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long k, a, b; cin >> k >> a >> b; long long k1, k2, r1, r2; if (a >= 0) { k1 = a / k; r1 = a % k; } else { k1 = a / k; r1 = a % k; if (r1) { k1 -= 1; r1 += k; } } if (b >= 0) { k2 = b / k; r2 = b % k; } else { k2 = b / k; r2 = b % k; if (r2) { k2 -= 1; r2 += k; } } if (r1) { cout << (k2 - k1) << n ; ; } else { cout << (k2 - k1 + 1) << n ; ; } }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > E[200005]; int U[200005], V[200005], D[200005]; int n, m; int vs[200005]; queue<int> q; int dfs(int u, int in) { q.push(u); for (int len = 0;; len++) { int sz = q.size(); if (sz == 0) break; in = len % 2; for (int i = 0; i < sz; i++) { u = q.front(); q.pop(); if (vs[u] != -1) { if (vs[u] != in) return false; else continue; } vs[u] = in; for (auto e : E[u]) { if (vs[e.first] == -1) q.push(e.first); else if (vs[e.first] != in ^ 1) return false; } } } for (int i = 0; i < m; i++) { if (vs[U[i]] == 0 && vs[V[i]] == 1) { D[i] = 1; } else if (vs[U[i]] == 1 && vs[V[i]] == 0) { D[i] = 0; } else assert(1 == 2); } return true; } int main() { memset(vs, -1, sizeof(vs)); scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &U[i], &V[i]); D[i] = -1; E[U[i]].push_back(make_pair(V[i], i)); E[V[i]].push_back(make_pair(U[i], i)); } if (dfs(1, 0)) { printf( YES n ); for (int i = 0; i < m; i++) printf( %d , D[i]); printf( n ); } else { printf( NO n ); } return 0; }
|
//
// mbt 11/26/2014
//
// this module converts between the various link-level flow-control
// protocols.
//
// fixme: many of the cases have not been tested. naming convention might
// be better. more asserts would be good. send_v_and_ready_p does not seem to
// be implemented. clocked versions should be handled by separate module.
//
// USAGE:
//
// 1. You need exactly one send_ parameter set and one recv parameter set.
// 2. A parameter x_then_y says that the signal y is combinationally dependent on x.
// 3. A parameter x_and_y says that the signal x and y are not combinationally dependent.
// So for example, yumi by definition is combinationally dependent on v,
// since the downstream module looks at the v signal and then decides to assert yumi.
// Hence, v_then_yumi is appropriate.
//
// Similarly, if you have a module that asserts v, but only if the downstream
// module indicates that it is ready, then, you would have ready_then_v.
//
// On the other hand, if both upsteam and downstream module are supposed to
// assert their signals in parallel, then it would be v_and_ready.
//
// Here is an example usage:
//
// bsg_flow_convert #(.width_p(nodes_p)
// ,.send_v_and_ready_p(1)
// ,.recv_v_and_retry_p(1)
// ) s2b
// (.v_i (v_i)
// ,.fc_o(ready_o)
//
// ,.v_o(switch_2_blockValid)
// ,.fc_i(switch_2_blockRetry)
// );
//
`include "bsg_defines.v"
module bsg_flow_convert
#(parameter send_v_and_ready_p = 0
, parameter send_v_then_yumi_p = 0
, parameter send_ready_then_v_p = 0
, parameter send_retry_then_v_p = 0
, parameter send_v_and_retry_p = 0
, parameter recv_v_and_ready_p = 0
, parameter recv_v_then_yumi_p = 0
, parameter recv_ready_then_v_p = 0
// recv and retry are independent signals
, parameter recv_v_and_retry_p = 0
// retry is dependent on retry
, parameter recv_v_then_retry_p = 0
, parameter width_p = 1
)
(input [width_p-1:0] v_i
, output [width_p-1:0] fc_o
, output [width_p-1:0] v_o
, input [width_p-1:0] fc_i
);
// if yumi needs to be made conditional on valid
if ((send_v_then_yumi_p & recv_v_and_ready_p)
| (send_v_then_yumi_p & recv_ready_then_v_p)
)
assign fc_o = fc_i & v_i;
// similar case but retry must be inverted
else if (send_v_then_yumi_p & recv_v_and_retry_p)
assign fc_o = ~fc_i & v_i;
else if (send_ready_then_v_p & recv_v_then_yumi_p)
// fixme fifo
initial begin $display("### %m a unhandled case requires fifo"); $finish(); end
else if (send_ready_then_v_p & recv_v_then_retry_p)
// fixme fifo inverted retry
initial begin $display("### %m unhandled case requires fifo"); $finish();
end
// if retry needs to be inverted to be a ready signal
// or a ready needs to be inverted to be a retry
else if (send_retry_then_v_p & recv_v_then_yumi_p)
initial begin $display("### %m unhandled case requires fifo"); $finish();
end
else if ((send_retry_then_v_p | send_v_and_retry_p) ^ (recv_v_then_retry_p | recv_v_and_retry_p))
assign fc_o = ~fc_i;
else
assign fc_o = fc_i;
// if valid needs to be made conditional on ready
if (recv_ready_then_v_p & ~send_ready_then_v_p)
assign v_o = v_i & fc_i;
else
assign v_o = v_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long d[40000]; char s[4005]; void input() { int i, j, len, a, sum; long long res; scanf( %d %s , &a, &s); len = strlen(s); for ((i) = 0; (i) < (len); (i)++) { sum = 0; for ((j) = (i); (j) <= (len - 1); (j)++) { sum += s[j] - 0 ; d[sum]++; } } if (a == 0) { res = d[0] * len * (len + 1) - d[0] * d[0]; printf( %I64d n , res); return; } res = 0; for ((i) = (9 * len); (i) >= (1); (i)--) if (a % i == 0 && a / i <= 36000) res += d[i] * d[a / i]; printf( %I64d , res); } int main() { input(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, x, l; cin >> n; vector<int> tab; for (long long int i = 0; i < n; ++i) { l = 0; cin >> x; if (x <= 7) tab.push_back(1); else if (x % 7 == 0) tab.push_back(x / 7); else if (x % 6 == 0) tab.push_back(x / 6); else if (x % 5 == 0) tab.push_back(x / 5); else if (x % 4 == 0) tab.push_back(x / 4); else if (x % 3 == 0) tab.push_back(x / 3); else if (x % 2 == 0) tab.push_back(x / 2); else { while ((x >= 7) && (x / 7 != 1)) { x -= 7; ++l; } while ((x >= 6) && (x / 6 != 1)) { x -= 6; ++l; } while ((x >= 5) && (x / 5 != 1)) { x -= 5; ++l; } while ((x >= 4) && (x / 4 != 1)) { x -= 4; ++l; } while ((x >= 3) && (x / 3 != 1)) { x -= 3; ++l; } while ((x >= 2) && (x / 2 != 1)) { x -= 2; ++l; } tab.push_back(l); } } for (long long int i = 0; i < tab.size(); ++i) { cout << tab[i] << endl; } return 0; }
|
// -----------------------------------------------------------------------
//
// Copyright 2004,2007 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
//
// Main module
/*
4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
FF00_0000 - FF00_1FFF Peripherals
Read Write
0 rs232out busy rs232out data
1 rs232in data
2 rs232in count
3 TSC
*/
`timescale 1ns/10ps
`include "../../soclib/pipeconnect.h"
module main(
input wire clk,
//
// serial interface
//
output wire ser_txd,
input wire ser_rxd,
input wire ser_ncts,
output wire ser_nrts,
//
// watchdog
//
output wire wd,
//
// two ram banks
//
output wire [17:0] rama_a,
inout wire [15:0] rama_d,
output wire rama_ncs,
output wire rama_noe,
output wire rama_nlb,
output wire rama_nub,
output wire rama_nwe,
output wire [17:0] ramb_a,
inout wire [15:0] ramb_d,
output wire ramb_ncs,
output wire ramb_noe,
output wire ramb_nlb,
output wire ramb_nub,
output wire ramb_nwe);
wire clock;
pll pll(.inclk0(clk), // 20 MHz on Cycore
.c0(clock)); // xx MHz output
assign wd = rst_counter[22];
reg [26:0] rst_counter = 0;
always @(posedge clock)
// if (~USER_PB[0])
// rst_counter <= 'd48_000_000;
// else if (~rst_counter[26])
if (~rst_counter[26])
rst_counter <= rst_counter - 1;
wire rst = ~rst_counter[26];
assign ramb_a = rama_a;
assign ramb_ncs = rama_ncs;
assign ramb_noe = rama_noe;
assign ramb_nwe = rama_nwe;
parameter FREQ = 58_000_000; // match clock frequency
parameter BPS = 115_200; // Serial speed
wire [ 7:0] rs232out_d;
wire rs232out_w;
wire rs232out_busy;
wire [ 7:0] rs232in_data;
wire rs232in_attention;
wire mem_waitrequest;
wire [1:0] mem_id;
wire [29:0] mem_address;
wire mem_read;
wire mem_write;
wire [31:0] mem_writedata;
wire [3:0] mem_writedatamask;
wire [31:0] mem_readdata;
wire [1:0] mem_readdataid;
wire `REQ rs232_req;
wire `RES rs232_res;
yari yari_inst(
.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.peripherals_req(rs232_req)
,.peripherals_res(rs232_res)
);
sram_ctrl sram_ctrl
(.clock(clock)
,.rst(rst)
,.mem_waitrequest(mem_waitrequest)
,.mem_id(mem_id)
,.mem_address(mem_address)
,.mem_read(mem_read)
,.mem_write(mem_write)
,.mem_writedata(mem_writedata)
,.mem_writedatamask(mem_writedatamask)
,.mem_readdata(mem_readdata)
,.mem_readdataid(mem_readdataid)
,.sram_a(rama_a)
,.sram_d({rama_d,ramb_d})
,.sram_cs_n(rama_ncs)
,.sram_be_n({rama_nub,rama_nlb,ramb_nub,ramb_nlb})
,.sram_oe_n(rama_noe)
,.sram_we_n(rama_nwe)
);
defparam sram_ctrl.need_wait = 1;
rs232out rs232out_inst
(.clock(clock),
.serial_out(ser_txd),
.transmit_data(rs232out_d),
.we(rs232out_w),
.busy(rs232out_busy));
defparam rs232out_inst.frequency = FREQ,
rs232out_inst.bps = BPS;
rs232in rs232in_inst
(.clock(clock),
.serial_in(ser_rxd),
.received_data(rs232in_data),
.attention(rs232in_attention));
defparam rs232in_inst.frequency = FREQ,
rs232in_inst.bps = BPS;
rs232 rs232_inst(.clk(clock),
.rst(rst),
.rs232_req(rs232_req),
.rs232_res(rs232_res),
.rs232in_attention(rs232in_attention),
.rs232in_data(rs232in_data),
.rs232out_busy(rs232out_busy),
.rs232out_w(rs232out_w),
.rs232out_d(rs232out_d));
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/11.0sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2011/04/07 $
// $Author: max $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reset_out
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
wire merged_reset;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out)
);
end
endgenerate
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("block.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("block_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 42);
`assert(result_empty, 0);
$finish;
end
endmodule
|
//-------------------------------------------------------------------
//-- baudtx_tb.v
//-- Banco de pruebas para la tranmision de datos
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`include "baudgen.vh"
module baudtx_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx #(`B115200)
dut(
.clk(clk),
.load(dtr),
.tx(tx)
);
//-- Generador de reloj. Periodo 2 unidades
always
# 1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("baudtx_tb.vcd");
$dumpvars(0, baudtx_tb);
//-- Primer envio: cargar y enviar
#10 dtr <= 0;
#300 dtr <= 1;
//-- Segundo envio
#10000 dtr <=0;
#300 dtr <=1;
//-- Tercer envio
#10000 dtr <=0;
#300 dtr <=1;
#5000 $display("FIN de la simulacion");
$finish;
end
endmodule
|
`timescale 1ns/1ns
// 2K memory card (100ns 2048*8bit RAM)
module memcard(
input [23:0] CDA,
inout [15:0] CDD,
input nCE,
input nOE,
input nWE,
input nREG, // Ignore
output nCD1, nCD2,
output nWP
);
parameter nINSERTED = 1'b1; // Memcard not inserted !
//parameter nINSERTED = 1'b0; // Memcard inserted :)
parameter nPROTECT = 1'b1; // And not protected
reg [7:0] RAMDATA[0:2047];
wire [7:0] DATA_OUT;
integer k;
initial begin
//for (k = 0; k < 2047; k = k + 1)
// RAMDATA[k] = k & 255;
$readmemh("raminit_memcard.txt", RAMDATA);
end
assign nCD1 = nINSERTED;
assign nCD2 = nINSERTED;
assign nWP = nPROTECT;
assign #100 DATA_OUT = RAMDATA[CDA[10:0]];
assign CDD[15:8] = 8'b11111111; // 8bit memcard
assign CDD[7:0] = (!nCE && !nOE) ? DATA_OUT : 8'bzzzzzzzz;
always @(nCE or nWE)
if (!nCE && !nWE)
#50 RAMDATA[CDA[10:0]] = CDD[7:0];
// DEBUG begin
always @(nWE or nOE)
if (!nWE && !nOE)
$display("ERROR: MEMCARD: nOE and nWE are both active !");
always @(negedge nWE)
if (!nCE) $display("MEMCARD: Wrote value 0x%H @ 0x%H", CDD, CDA);
always @(negedge nOE)
if (!nCE) $display("MEMCARD: Read value 0x%H @ 0x%H", RAMDATA[CDA[10:0]], CDA);
// DEBUG end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:07:50 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_0_stub.v
// Design : zqynq_lab_1_design_axi_gpio_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { priority_queue<pair<unsigned long long int, int> > matches; unsigned long long int n; int m; unsigned long long int a; int b; unsigned long long int max = 0; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a >> b; pair<int, unsigned long long int> d; d.first = b; d.second = a; matches.push(d); } while (matches.size() != 0 && m != 0) { pair<int, unsigned long long int> d = matches.top(); if (d.second > n) { max += n * d.first; n = 0; } else { max += d.second * d.first; n -= d.second; } matches.pop(); } cout << max << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_BLACKBOX_V
`define SKY130_FD_SC_HS__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_a (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "../tv/cdatafile/c.matrix_mult.autotvin_a.dat",
TV_OUT = "../tv/rtldatafile/rtl.matrix_mult.autotvout_a.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 8;
parameter ADDR_WIDTH = 32'd 5;
parameter DEPTH = 32'd 25;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { vector<long> vt; long i = 0, n, temp, count = 1; cin >> n; for (int i = 0; i < n; i++) { cin >> temp; vt.push_back(temp); } sort(vt.begin(), vt.end()); while (i < n) { if (vt[i] <= count) { count++; } else { temp = count; bool check = true; for (int j = i; j < n; j++) { if (vt[j] <= temp) { check = true; temp++; i = j; break; } else { check = false; temp++; } } if (check == false) break; else count = temp; } i++; } cout << count << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int n, cnt[60], have, r = 1; int main() { ios_base::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> s; n = s.size(); s = + s; for (int i = (1); i <= (n); ++i) { while (r <= n && have < 26) { if (s[r] == ? ) ++have; else { int temp = s[r] - A ; if (!cnt[temp]) ++have; ++cnt[temp]; } ++r; } if (have == 26 && r - i == 26) { int q[50], top = 0; for (int j = (0); j <= (25); ++j) if (!cnt[j]) q[++top] = j; for (int j = (1); j <= (i - 1); ++j) if (s[j] == ? ) cout << A ; else cout << s[j]; for (int j = (i); j <= (min(r, n)); ++j) if (s[j] == ? ) { if (top) cout << (char)( A + q[top--]); else cout << A ; } else cout << s[j]; for (int j = (r + 1); j <= (n); ++j) if (s[j] == ? ) cout << A ; else cout << s[j]; return 0; } if (s[i] == ? ) --have; else { int temp = s[i] - A ; --cnt[temp]; if (!cnt[temp]) --have; } } cout << -1; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, m, k, i, j, a[200002], sum = 0; vector<long long int> v; set<pair<long long int, long long int>> s; cin >> n >> m >> k; for (i = 0; i < n; i++) { cin >> a[i]; s.insert(make_pair(a[i], i)); } set<pair<long long int, long long int>>::iterator it1, it2; it1 = s.begin(); it2 = s.end(); for (i = 0; i < m * k; i++) { it2--; } s.erase(it1, it2); for (i = 0; i < n; i++) { if (s.find(make_pair(a[i], i)) != s.end()) { sum += a[i]; } } long long int cnt = 0; for (i = 0; i < n; i++) { auto it = s.find(make_pair(a[i], i)); if (cnt == m * (k - 1)) { break; } if (it != s.end()) { cnt++; if (cnt % m == 0) { v.push_back(it->second + 1); } } } long long int sz = v.size(); cout << sum << endl; for (i = 0; i < sz; i++) { cout << v[i] << ; } cout << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N (
Q ,
D ,
GATE ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const long long LLINF = 9223372036854775807LL; const int maxn = 30010; int a[maxn] = {}; int used[maxn] = {}; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); vector<int> ans1, ans2; if (n == 2) { ans1.push_back(a[0]); ans2.push_back(a[1]); goto ooo; } if (n == 3) { ans1.push_back(a[0]); ans1.push_back(a[1]); ans2.push_back(a[2]); goto ooo; } if (n == 4) { ans1.push_back(a[0]); ans1.push_back(a[1]); ans2.push_back(a[2]); ans2.push_back(a[3]); goto ooo; } for (int i = 0; i < 5; ++i) for (int j = i + 1; j < 5; ++j) for (int k = j + 1; k < 5; ++k) { if (a[j] - a[i] == a[k] - a[j]) { memset(used, 0, sizeof(used)); used[i] = 1; used[j] = 1; used[k] = 1; int d = a[j] - a[i]; int cur = a[k] + d; int cused = 3; int lused = k; for (int t = k + 1; t < n; ++t) { if (a[t] == cur) { used[t] = 1; lused = t; cused++; cur += d; } } int pppp = 2; while (pppp--) { if (pppp == 0) used[lused] = 0; bool ok = true; int p1 = -1; int p2 = -1; int curd = 0; for (int t = 0; t < n; ++t) { if (used[t]) continue; int ccc = a[i]; if (curd == 0) { if (p2 == -1) { p2 = p1; p1 = t; if (p2 != -1) { curd = a[p1] - a[p2]; } } } else { if (a[t] - a[p1] != curd) { ok = false; break; } else { p1 = t; } } } if (ok) { if (cused == n) used[0] = 0; for (int t = 0; t < n; ++t) { if (used[t]) ans1.push_back(a[t]); else ans2.push_back(a[t]); } goto ooo; } } } } printf( No solution ); return 0; ooo: for (int i = 0; i < ans1.size(); ++i) printf( %d , ans1[i]); printf( n ); for (int i = 0; i < ans2.size(); ++i) printf( %d , ans2[i]); return 0; }
|
/*
verilog fetch/decode/memory stage module.
*/
`include "defines.v"
module stages(
input wire [`REGW-1:0] ins,
input wire [`STGW-1:0] cs,
input wire zf,
output reg [`REGO-1:0] gr_raddr1, gr_raddr2, gr_waddr,
output reg gr_we, pc_we, mem_we, pc_ie
);
reg pzf;
initial gr_we = 1'b0;
initial pc_ie = 1'b0;
initial mem_we = 1'b0;
initial pzf = 1'd0;
always @(cs) begin
/* initialize */
pc_we = 1'b0;
/* FETCH stage */
if(cs == `FETCH) begin
gr_we = 1'b0;
pc_ie = 1'b0;
mem_we= 1'b0;
end
/* DECODE stage */
if(cs == `DEC) begin
/* calculations */
/* 1st operand is result, 2nd & 3rd are arguments */
if(ins[`REGW-1:`REGW-4] < `REGO'd8) begin
gr_raddr1 = ins[`REGW-9:`REGW-12];
gr_raddr2 = ins[`REGW-13:0];
gr_waddr = ins[`REGW-5:`REGW-8];
gr_we = 1'b1;
end
/* not calculations */
else begin
case(ins[`REGW-1:`REGW-4])
`JMP : gr_raddr1 = ins[`REGW-5:`REGW-8];
`IN : begin
gr_waddr = ins[`REGW-5:`REGW-8]; // reg_addr
gr_raddr1= ins[`REGW-9:`REGW-12]; // mem_addr
gr_we = 1'b1;
end
`OUT : begin
gr_raddr1 = ins[`REGW-5:`REGW-8]; // mem_addr
gr_raddr2 = ins[`REGW-9:`REGW-12]; // reg_addr
mem_we = 1'b1;
end
`IMM : begin
gr_waddr = 4'h0;
gr_we = 1'b1;
end
`JZ : begin
gr_raddr1 = ins[`REGW-5:`REGW-8]; // jump address
end
default: pc_ie = 1'b0; // HLT
endcase
end
end
/* MEM stage */
else if(cs == `MEM) begin
/* calculations */
if(ins[`REGW-1:`REGW-4] < `REGO'd8) begin
pc_ie = 1'b1;
pzf = zf;
end
/* not calculations */
else begin
case(ins[`REGW-1:`REGW-4])
`JMP : begin
pc_we = 1'b1;
pc_ie = 1'b1;
end
`JZ : begin
if(pzf == 1'd1) begin
pc_we = 1'b1;
end
pc_ie = 1'b1;
end
`IN : pc_ie = 1'b1;
`OUT : pc_ie = 1'b1;
`IMM : pc_ie = 1'b1;
`NOP : pc_ie = 1'b1;
default: pc_ie = 1'b0; // HLT
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_0_V
`define SKY130_FD_SC_LP__OR2_0_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_0_V
|
//////////////////////////////////////////////////////////////////////
//
// clkgen
//
// Handles clock and reset generation for rest of design
//
//
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
`include "orpsoc-defines.v"
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
//
input ddr_init_done,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
output ddr_rst_o,
output pixel_clock,
output pixel_clock_x3
);
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
assign async_rst_n = rst_n_pad_i;
assign async_rst = ~async_rst_n;
// Everyone likes active-high reset signals...
assign async_rst_o = ~async_rst_n;
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
wire pll_lock;
pll pll0 (
.areset (async_rst),
.inclk0 (sys_clk_pad_i),
.c0 (wb_clk_o),
.c1 (pixel_clock),
.c2 (pixel_clock_x3),
.locked (pll_lock)
);
assign sync_rst_n = pll_lock;
//
// Reset generation
//
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else if (!ddr_init_done)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
// Reset generation for ddr
reg [15:0] ddr_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
ddr_rst_shr <= 16'hffff;
else
ddr_rst_shr <= {ddr_rst_shr[14:0], ~(sync_rst_n)};
assign ddr_rst_o = ddr_rst_shr[15];
endmodule // clkgen
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); int t; cin >> t; for (int i = 0; i < t; i++) { long long a, b; long long uns = 0; cin >> a >> b; uns = abs(a - b) / 5; if (abs(a - b) % 5 == 1) uns++; if (abs(a - b) % 5 == 2) uns += 1; if (abs(a - b) % 5 == 3) uns += 2; if (abs(a - b) % 5 == 4) uns += 2; cout << uns << endl; } }
|
//
// Copyright (c) 2002 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic expression assign with add
//
//
module adder (q,a,b );
input a,b;
output [1:0] q;
assign q = {1'b0,a} +{1'b0,b};
endmodule
module test ;
reg d;
wire [1:0] q;
adder u_add (.q(q),.a(d),.b(d));
(* ivl_synthesis_off *)
initial
begin
// $dumpfile("test.vcd");
// $dumpvars(0,test);
d = 0;
# 1;
if (q !== 2'b0)
begin
$display("FAILED - Q isn't 0 ");
$finish;
end
#1 ;
d = 1;
# 1;
if (q !== 2'b10)
begin
$display("FAILED - Q isn't 2 ");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a > b) swap(a, b); if (a == 0) return b; return gcd(b % a, a); } long long powerMod(long long x, long long y) { long long res = 1; x %= 1000000007; while (y > 0) { if (y & 1) res = (res * x) % 1000000007; y = y >> 1; x = (x * x) % 1000000007; } return res; } int main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); ; long long n, i, j, k, l; cin >> n; long long p[n + 1], q[n + 1]; for (i = 1; i <= n; i++) { cin >> p[i]; q[p[i]] = i; } long long m = 0; vector<pair<long long, long long> > swaps; for (i = 1; i <= n; i++) { if (p[i] != i) { j = q[i]; if (2 * abs(i - j) >= n) { m++; swaps.push_back({i, j}); p[j] = p[i]; q[p[i]] = j; p[i] = i; q[i] = i; } else if (i <= n / 2 && j <= n / 2) { k = max(i, j) + n / 2; m += 3; swaps.push_back({i, k}); swaps.push_back({j, k}); swaps.push_back({i, k}); p[j] = p[i]; q[p[i]] = j; p[i] = i; q[i] = i; } else if (i > n / 2 && j > n / 2) { k = min(i, j) - n / 2; m += 3; swaps.push_back({i, k}); swaps.push_back({j, k}); swaps.push_back({i, k}); p[j] = p[i]; q[p[i]] = j; p[i] = i; q[i] = i; } else { m += 5; if (i <= n / 2 && j > n / 2) k = i + n / 2, l = j - n / 2; else k = i - n / 2, l = j + n / 2; swaps.push_back({j, l}); swaps.push_back({l, k}); swaps.push_back({k, i}); swaps.push_back({k, l}); swaps.push_back({l, j}); p[j] = p[i]; q[p[i]] = j; p[i] = i; q[i] = i; } } } cout << m << endl; for (pair<long long, long long> p : swaps) { cout << p.first << << p.second << endl; } return 0; }
|
module ARM_CU_ALU_TestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
wire [17:0] signals;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);
reg [31:0] A,B;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(A,B, opcode, FLAGS, Out,FLAGS_OUT,S,ALUSTORE);
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
MFC = 0; Reset=1 ; Clk=0 ; FLAGS =0;
#1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench);
$display(" Test Results" );
$monitor("A=%4h,B=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,FLAGS=%3d,S=%3d,ALUSTORE=%3d",A,B,opcode,Out,FLAGS_OUT,FLAGS,S,ALUSTORE);
end
endmodule
//iverilog ARM_ALU.v controlunit.v Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v ARM_CU_ALU_TestBench.v
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10; long long n, a, cnt, ans, sum, l, r; string g; void DNM() { cin >> n; cin >> g; sort(g.begin(), g.end()); cout << g << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int Qu_l_uQ = 1; while (Qu_l_uQ--) DNM(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long pow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) { res = (res * a) % 1000000007; } b >>= 1; a = (a * a) % 1000000007; } return res; } int main() { long long n, k; cin >> n >> k; long long ans = (pow(k, k - 1) * pow(n - k, n - k)) % 1000000007; cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long v[2][200005]; long long c[2][200005]; int n, k, a, b, q, e, day, ord; const int maxn = 200005; void add(int i, int value, int z) { for (; i < maxn; i += (i + 1) & -(i + 1)) v[z][i] += value; } long long get(int i, int z) { long long res = 0; for (; i >= 0; i -= (i + 1) & -(i + 1)) res += v[z][i]; return res; } long long g = 0; int main() { scanf( %d%d%d%d%d , &n, &k, &a, &b, &q); while (q--) { scanf( %d , &e); if (e == 1) { scanf( %d %d , &day, &ord); long long ord1 = ord, ord2 = ord; if (c[0][day] <= b) { long long need = (long long)b - c[0][day]; if (need <= ord1) { ord1 = need; c[0][day] = b; } else c[0][day] += (long long)ord1; add(day, ord1, 0); } if (c[1][day] <= a) { long long need = (long long)a - c[1][day]; if (need <= ord2) { ord2 = need; c[1][day] = a; } else c[1][day] += ord2; add(day, ord2, 1); } } else { scanf( %d , &day); g = 0; if (day - 1) g = get(day - 1, 0); g += (long long)(get(200004, 1) - get(day + k - 1, 1)); printf( %I64d n , g); } } }
|
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: ballmover.v, instantiated by tehgame.v
// Calculates ball movement thoroughout the game.
//
// Pins description:
// clk input master clock
// reset input reset the ball and inner state
// advance input ball advance clock
// ball_x input ball x-coordinate
// ball_y input ball y-coordinate
// collide input paddle collision signal
// collidereset output collision acknowledge/reset signal
// deflect input deflection angle
// set_side input ball service side
// outA, outB output ball out left and right signals, mutually exclusive
// wall output up/down wall hit signal
//
module ballmover(clk, reset, advance, ball_x, ball_y, collide, collidereset, deflect, set_side, outA, outB, wall);
parameter SCREENWIDTH = 640;
parameter SCREENHEIGHT = 480;
parameter BALLSIZE = 8;
input clk;
input reset;
input advance;
output reg [9:0] ball_x;
output reg [9:0] ball_y;
input collide;
output reg collidereset;
input [9:0] deflect;
input set_side;
output reg outA, outB, wall;
reg sgnX;
reg sgnY;
parameter speedX = 4'd8;
reg [3:0] speedY = 8;
reg [3:0] lsb_x;
reg [3:0] lsb_y;
wire[3:0] woot;
assign woot[1:0] = {(ball_x < BALLSIZE/2), (ball_x > SCREENWIDTH - BALLSIZE/2)};
assign woot[3:2] = {(ball_y < BALLSIZE/2), (ball_y > SCREENHEIGHT - BALLSIZE/2)};
always @(posedge advance or posedge reset) begin
if (reset) begin
//if (outA) {ball_x,lsb_x} = {SCREENWIDTH/3, 4'b0};
//else if (outB) {ball_x, lsb_x} = {(SCREENWIDTH-SCREENWIDTH/3), 4'b0};
//else {ball_x, lsb_x} = {SCREENWIDTH/2, 4'b0};
{ball_x, lsb_x} = {(set_side ? (SCREENWIDTH/3) : (SCREENWIDTH-SCREENWIDTH/3)), 4'b0};
{ball_y, lsb_y} = SCREENHEIGHT/2 * 16;
speedY = 1;
outA = 0;
outB = 0;
end
else begin
if (collide) begin
sgnX = !sgnX;
sgnY = ~deflect[9];
speedY = deflect[5:2];
collidereset = 1;
end
else collidereset = 0;
if (woot[1]) begin ball_x = BALLSIZE/2; sgnX = 1; outA = 1; end
if (woot[0]) begin ball_x = 640-BALLSIZE/2; sgnX = 0; outB = 1; end
if (woot[3]) begin ball_y = BALLSIZE/2; sgnY = 1; end
if (woot[2]) begin ball_y = 480-BALLSIZE/2; sgnY = 0; end
{ball_x,lsb_x} = {ball_x,lsb_x} + (sgnX ? speedX : -speedX);
{ball_y,lsb_y} = {ball_y,lsb_y} + (sgnY ? speedY : -speedY);
wall <= woot[2] | woot[3];
//outA <= woot[1];
//outB <= woot[0];
end
end
endmodule
// $Id: ballmover.v,v 1.10 2007/08/27 22:14:47 svo Exp $
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> p(n, 0); for (int i = 0; i < n; i++) { int aux; cin >> aux; p[i] = aux - 1; } vector<long long int> dp(n + 1, 0); for (int i = 1; i < n + 1; i++) { dp[i] = (long long int)(dp[i - 1] * (long long int)2 - dp[p[i - 1]] + 2 + 1000000007) % 1000000007; } cout << dp[n] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; long long gcd(long long a, long long b) { while (b) { a %= b; swap(a, b); } return a; } int main() { long long l, r, x, y; cin >> l >> r >> x >> y; long long d = 1; long long res = 0; map<int, int> m; while (d * d <= y) { if (y % d == 0) { if (!m[min(y / d, d * x)] && d * x >= l && d * x <= r && y / d >= l && y / d <= r && gcd(d * x, y / d) == x) { res++; if (d * x != y / d) res++; m[min(y / d, d * x)]++; } } d++; } cout << res << endl; }
|
#include <bits/stdc++.h> using namespace std; void yala_bena() { cin.tie(0); std::ios::sync_with_stdio(0); } const int m_r = 999999; int k = -1; int bestsum, limit; vector<long long> ans; int binary(int number) { while (number) { k++; if (number % 2) return k; number /= 2; } } void sum_it_up(int sum, int index, vector<int> p) { if (sum + ans[index] <= bestsum) { sum += ans[index]; p.push_back(index + 1); } if (sum == bestsum) { cout << p.size() << endl; for (int i = 0; i < p.size(); i++) { if (i == p.size() - 1) cout << p[i] << endl; else cout << p[i] << ; } exit(0); } for (int i = index + 1; i < ans.size(); i++) { if (sum + ans[i] <= bestsum) sum_it_up(sum, i, p); } } int main() { yala_bena(); cin >> bestsum >> limit; for (int i = limit; i >= 1; i--) { int a = (int)pow(2, binary(i)); k = -1; if (a <= bestsum) bestsum -= a, ans.push_back(i); } if (bestsum == 0) { cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) i == ans.size() - 1 ? cout << ans[i] << endl : cout << ans[i] << ; return 0; } cout << -1 << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long qpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a; b >>= 1; a = a * a; } return res; } int a[500005]; int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); k = 8 * k / n; if (k >= ceil(log(n) / log(2))) { cout << 0; return 0; } long long q = pow(2, k); int min1 = n; int sum = 0; for (int l = 1, r = 1; r <= n && l <= n;) { while (r < n && a[r] == a[r + 1]) r++; sum++; if (sum == q) { min1 = min(min1, n - (r - l + 1)), sum--; while (l < n && a[l] == a[l + 1]) l++; l++; } r++; } if (min1 == n) cout << 0; else cout << min1; return 0; }
|
#include <bits/stdc++.h> using namespace std; unsigned long long int dist[1150][1150], visited[1150][1150]; char ans[1050][1050]; void solve() { long long n, i, j, m; cin >> n >> m; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) cin >> ans[i][j]; } int startx, starty, endx, endy; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (ans[i][j] == E ) { endx = i; endy = j; } if (ans[i][j] == S ) { startx = i; starty = j; } } } for (i = 0; i < n; i++) for (j = 0; j < m; j++) { dist[i][j] = INT_MAX; visited[i][j] = 0; } int rowcol[] = {0, 0, 1, -1}; int colcol[] = {1, -1, 0, 0}; dist[endx][endy] = 0; visited[endx][endy] = 1; queue<pair<int, int> > q; q.push({endx, endy}); while (q.empty() == 0) { pair<int, int> point = q.front(); q.pop(); int x = point.first; int y = point.second; for (i = 0; i < 4; i++) { int x1 = x + rowcol[i]; int y1 = y + colcol[i]; if (x1 >= 0 && y1 >= 0 && x1 < n && y1 < m && ans[x1][y1] != T ) { if (visited[x1][y1] == 0) { dist[x1][y1] = dist[x][y] + 1; visited[x1][y1] = 1; q.push({x1, y1}); } } } } unsigned long long int count = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (startx == i && starty == j) { continue; } if (dist[startx][starty] >= dist[i][j] && ans[i][j] != 0 && ans[i][j] != T && ans[i][j] != E ) count += ans[i][j] - 0 ; } } cout << count << endl; } int main() { long long n = 1, x1, y1, x2, y2, i; while (n--) { solve(); } }
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:06:40 03/19/2011
// Design Name:
// Module Name: jace_en_fpga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fpga_ace (
input wire clkram,
input wire clk65,
input wire clkcpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
input wire [4:0] columnas,
output wire video,
output wire hsync,
output wire vsync,
output wire mic,
output wire spk
);
// Los buses del Z80
wire [7:0] DinZ80;
wire [7:0] DoutZ80;
wire [15:0] AZ80;
// Señales de control, direccion y datos de parte de todas las memorias
wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
// Señales para la implementación de la habilitación de escritura en ROM
wire enable_write_to_rom;
wire [7:0] dout_modulo_enable_write;
wire modulo_enable_write_oe;
// Copia del bus de direcciones para las filas del teclado
assign filas = AZ80[15:8];
// Multiplexor para asignar un valor al bus de datos de entrada del Z80
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
// Memoria del equipo
ram1k_dualport sram (
.clk(clkram),
.ce(sram_enable),
.a1(AZ80[9:0]),
.a2(sram_addr),
.din(DoutZ80),
.dout1(dout_sram),
.dout2(sram_data),
.we(~wr_n)
);
ram1k_dualport cram (
.clk(clkram),
.ce(cram_enable),
.a1(AZ80[9:0]),
.a2(cram_addr),
.din(DoutZ80),
.dout1(dout_cram),
.dout2(cram_data),
.we(~wr_n)
);
ram1k uram(
.clk(clkram),
.ce(uram_enable),
.a(AZ80[9:0]),
.din(DoutZ80),
.dout(dout_uram),
.we(~wr_n)
);
ram16k xram(
.clk(clkram),
.ce(xram_enable),
.a(AZ80[13:0]),
.din(DoutZ80),
.dout(dout_xram),
.we(~wr_n)
);
ram32k eram(
.clk(clkram),
.ce(eram_enable),
.a(AZ80[14:0]),
.din(DoutZ80),
.dout(dout_eram),
.we(~wr_n)
);
/* La ROM */
rom the_rom(
.clk(clkram),
.ce(rom_enable),
.a(AZ80[12:0]),
.din(DoutZ80),
.dout(dout_rom),
.we(~wr_n & enable_write_to_rom)
);
/* La CPU */
tv80n cpu(
// Outputs
.m1_n(), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), .rfsh_n(), .halt_n(), .busak_n(), .A(AZ80), .do(DoutZ80),
// Inputs
.di(DinZ80), .reset_n(reset), .clk(clkcpu), .wait_n(wait_n), .int_n(int_n), .nmi_n(1'b1), .busrq_n(1'b1)
);
jace_logic todo_lo_demas (
.clk(clk65),
// CPU interface
.cpu_addr(AZ80),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.data_from_cpu(DoutZ80),
.data_to_cpu(data_from_jace),
.data_to_cpu_oe(data_from_jace_oe),
.wait_n(wait_n),
.int_n(int_n),
// CPU-RAM interface
.rom_enable(rom_enable),
.sram_enable(sram_enable),
.cram_enable(cram_enable),
.uram_enable(uram_enable),
.xram_enable(xram_enable),
.eram_enable(eram_enable),
// Screen RAM and Char RAM interface
.screen_addr(sram_addr),
.screen_data(sram_data),
.char_addr(cram_addr),
.char_data(cram_data),
// Devices
.kbdcols(columnas),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.hsync_pal(hsync),
.vsync_pal(vsync)
);
io_write_to_rom modulo_habilitador_escrituras (
.clk(clk65),
.a(AZ80),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(DoutZ80),
.dout(dout_modulo_enable_write),
.dout_oe(modulo_enable_write_oe),
.enable_write_to_rom(enable_write_to_rom)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo.v
// Author : Chih-Tsun Huang
// E-mail :
// Revision : 4
// Date : 2014/04/28
// Abstract :
// The top module of FIFO consists of FIFO controller and the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo (
input clk,
input rst_n,
input push,
input pop,
input [7:0] datain,
output empty,
output almost_empty,
output full,
output almost_full,
output error,
output [7:0] dataout
);
wire [4:0] addr;
wire cen;
wire oen;
wire wen;
wire [7:0] data_to_ram;
fifo_ctr controller (
.clk(clk),
.rst_n(rst_n),
.push(push),
.pop(pop),
.empty(empty),
.almost_empty(almost_empty),
.full(full),
.almost_full(almost_full),
.error(error),
.cen(cen),
.wen(wen),
.oen(oen),
.addr(addr)
);
// LAB NOTE:
// You should include the memory simulation model by your own
RAM32x8 ram (
.Q(dataout),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(addr),
.D(datain),
.OEN(oen)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int T, d; scanf( %d , &T); while (T--) { scanf( %d , &d); double a = 0, b = 0; double x = d * d - 4 * d; if (x < 0) { printf( N n ); continue; } else { a = (d - sqrt(x)) / 2.0; b = d - a; if (a < b) swap(a, b); printf( Y %.9lf %.9lf n , a, b); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long N = 610001; const long long inf = (long long)5e16; struct node { long long val, id; }; node a[N], b[N]; bool cmp(node x, node y) { if (x.val == y.val) return x.id < y.id; return x.val < y.val; } long long n, m, ans[N], pos[N]; signed main() { scanf( %lld%lld , &m, &n); for (long long i = 1; i <= n; i++) { scanf( %lld , &a[i].val); a[i].id = i; } for (long long i = n + 1; i <= n + n; i++) { scanf( %lld , &b[i].val); b[i].id = i - n; b[i + n].val = b[i].val + m; b[i + n].id = i - n; b[i - n].val = b[i].val - m; b[i - n].id = i - n; } sort(a + 1, a + n + 1, cmp); sort(b + 1, b + 3 * n + 1, cmp); for (long long i = 1, j = 1; i <= n; i++) { while (a[i].val >= b[j].val && j <= 3 * n) j++; ans[0] += a[i].val; ans[j - i + 1] -= (a[i].val + a[i].val); } for (long long i = 1, j = 1; j <= 3 * n; j++) { ans[max(j - n + 1, 0LL)] -= b[j].val; while (b[j].val > a[i].val && i <= n) i++; ans[j - i + 2] += b[j].val + b[j].val; ans[j + 1] -= b[j].val; } long long sum = ans[0], id = 0, mi = inf; for (long long i = 1; i <= 2 * n + 1; i++) { sum += ans[i]; ans[i] += ans[i - 1]; if (mi > sum) { mi = sum; id = i; } } cout << mi << endl; for (long long i = 1; i <= n; i++) pos[a[i].id] = b[i + id - 1].id; for (long long i = 1; i <= n; i++) printf( %d , pos[i]); return 0; }
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931276207744;
wire exception_139931276329976;
wire exception_139931273691576;
wire exception_139931279256392;
wire exception_139931273476792;
wire exception_139931279285064;
wire exception_139931284115112;
wire exception_139931283339240;
wire exception_139931274721040;
wire exception_139931279910528;
wire exception_139931279158952;
wire exception_139931276720176;
wire exception_139931279933952;
wire exception_139931278247408;
wire exception_139931279929216;
wire exception_139931284950696;
wire exception_139931275440568;
main_0 main_0_139931276207744(
.clk(clk),
.rst(rst),
.exception(exception_139931276207744),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_vga_out(output_vga),
.output_vga_out_stb(output_vga_stb),
.output_vga_out_ack(output_vga_ack));
main_1 main_1_139931276329976(
.clk(clk),
.rst(rst),
.exception(exception_139931276329976),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931273691576(
.clk(clk),
.rst(rst),
.exception(exception_139931273691576),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_139931279256392(
.clk(clk),
.rst(rst),
.exception(exception_139931279256392),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_4 main_4_139931273476792(
.clk(clk),
.rst(rst),
.exception(exception_139931273476792),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_5 main_5_139931279285064(
.clk(clk),
.rst(rst),
.exception(exception_139931279285064),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_6 main_6_139931284115112(
.clk(clk),
.rst(rst),
.exception(exception_139931284115112),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_7 main_7_139931283339240(
.clk(clk),
.rst(rst),
.exception(exception_139931283339240),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_8 main_8_139931274721040(
.clk(clk),
.rst(rst),
.exception(exception_139931274721040),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_9 main_9_139931279910528(
.clk(clk),
.rst(rst),
.exception(exception_139931279910528),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_10 main_10_139931279158952(
.clk(clk),
.rst(rst),
.exception(exception_139931279158952),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_11 main_11_139931276720176(
.clk(clk),
.rst(rst),
.exception(exception_139931276720176),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_12 main_12_139931279933952(
.clk(clk),
.rst(rst),
.exception(exception_139931279933952),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_13 main_13_139931278247408(
.clk(clk),
.rst(rst),
.exception(exception_139931278247408),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_14 main_14_139931279929216(
.clk(clk),
.rst(rst),
.exception(exception_139931279929216),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_15 main_15_139931284950696(
.clk(clk),
.rst(rst),
.exception(exception_139931284950696),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_16 main_16_139931275440568(
.clk(clk),
.rst(rst),
.exception(exception_139931275440568),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931276207744 || exception_139931276329976 || exception_139931273691576 || exception_139931279256392 || exception_139931273476792 || exception_139931279285064 || exception_139931284115112 || exception_139931283339240 || exception_139931274721040 || exception_139931279910528 || exception_139931279158952 || exception_139931276720176 || exception_139931279933952 || exception_139931278247408 || exception_139931279929216 || exception_139931284950696 || exception_139931275440568;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long iinf = 1 << 29; const long long inf = 1ll << 60; const long long mod = 1e9 + 7; void GG() { cout << No n ; exit(0); } long long mpow(long long a, long long n) { long long re = 1; while (n > 0) { if (n & 1) re = re * a % mod; a = a * a % mod; n >>= 1; } return re; } long long inv(long long b) { if (b == 1) return b; return (mod - mod / b) * inv(mod % b) % mod; } const long long maxn = 5e6 + 1; const double PI = acos(-1.0); void FFT(vector<complex<double> > &a, bool rev = 0) { long long n = (long long)a.size(); assert(__builtin_popcount(n) <= 1); for (long long i = 1, j = 0; i < n; i++) { long long bit = n / 2; while (j >= bit) j -= bit, bit /= 2; j += bit; if (i < j) swap(a[i], a[j]); } for (long long B = 2; B <= n; B *= 2) { double ang = 2 * PI / B * (rev ? -1 : 1); complex<double> w0(cos(ang), sin(ang)); for (long long i = 0; i < n; i += B) { complex<double> w(1, 0); for (long long j = 0; j < B / 2; j++) { complex<double> u = a[i + j], v = w * a[i + j + B / 2]; a[i + j] = u + v, a[i + j + B / 2] = u - v; w *= w0; } } } if (rev) for (long long i = 0; i < (n); i++) a[i] /= n; } vector<long long> mul(vector<long long> a, vector<long long> b) { long long n = 1; while (n < (long long)a.size() + (long long)b.size()) n *= 2; vector<complex<double> > x(n), y(n); for (long long i = 0; i < ((long long)a.size()); i++) x[i] = complex<double>(a[i], 0); for (long long j = 0; j < ((long long)b.size()); j++) y[j] = complex<double>(b[j], 0); FFT(x); FFT(y); for (long long i = 0; i < (n); i++) x[i] *= y[i]; FFT(x, 1); vector<long long> re(n); for (long long i = 0; i < (n); i++) re[i] = (long long)(round(x[i].real())); while (re.size() > 1 && re.back() == 0) re.pop_back(); return re; } signed main() { long long n, x; cin >> n >> x; vector<long long> a(n); vector<long long> b; long long cnt = 1; long long zed = 0; for (long long i = 0; i < (n); i++) { cin >> a[i]; if (a[i] < x) { b.push_back(cnt); cnt = 0; } cnt++; } b.push_back(cnt); for (long long y : b) zed += (y - 1) * (y) / 2; vector<long long> c = b; reverse(c.begin(), c.end()); vector<long long> d = mul(b, c); cout << zed << ; for (long long i = ((long long)b.size()); i < ((long long)b.size() + n); i++) { if (i < (long long)d.size()) cout << d[i] << ; else cout << 0 << ; } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000009; const double PI = acos(-1.0); const double eps = 1e-8; const int MAXN = 0; const int MAXM = 0; long long n, k, t, b, z; int main() { z = 1; int ans = 0; cin >> k >> b >> n >> t; while (z <= t) { ans++; z = z * k + b; } if (z == t) ans = n - ans; else { ans--; ans = n - ans; } cout << max(0, ans) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cerr << Time : << 1000 * ((double)clock()) / (double)CLOCKS_PER_SEC << ms n ; long long t; cin >> t; while (t--) { long long n, g = 0, s = 0, b = 0, i, gidx, bidx, cidx; cin >> n; int flag = 0; long long p[n]; for (i = 0; i < n; i++) { cin >> p[i]; } long long m = n / 2; cidx = m; cidx--; while (p[cidx + 1] == p[cidx]) { cidx--; if (cidx < 4) { cout << 0 0 0 << n ; flag = 1; break; } } if (flag) continue; gidx = 1; while (p[gidx] == p[gidx - 1]) { gidx++; if (gidx >= cidx) { cout << 0 0 0 << n ; flag = 1; break; } } if (flag) continue; bidx = 2 * gidx + 1; while (p[bidx] == p[bidx - 1]) { bidx++; if (bidx >= cidx) { cout << 0 0 0 << n ; flag = 1; break; } } if (flag) continue; g = gidx; b = bidx - gidx; s = cidx - bidx + 1; if (g == 0 || b == 0 || s <= 0 || g >= s) cout << 0 0 0 << n ; else cout << g << << b << << s << n ; } return 0; }
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Simple Clock Devider
*
* Devides a given input clock.
*
* parameters:
* div count which is used to devide the input clock
* inputs:
* clk_i input clock
* outputs:
* clk_o output clock
*/
module clkdiv(
input rst,
input clk_i,
input [15:0] div,
output clk_o
);
reg r_clk_o = 1'b0;
reg [15:0] count = 16'h0;
always @(posedge clk_i) begin
if(rst) begin
r_clk_o = 1'b0;
count = 16'h0;
end
else begin
count = count + 1;
if(count == div) begin
count = 16'h0;
r_clk_o = ~r_clk_o;
end
end
end
assign clk_o = r_clk_o;
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Rotor_To_Electrical_Position.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Rotor_To_Electrical_Position
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Rotor_To_Electrical_Position
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Rotor_To_Electrical_Position
(
R,
E
);
input signed [17:0] R; // sfix18_En14
output signed [17:0] E; // sfix18_En14
wire signed [35:0] number_of_pole_pairs_cast; // sfix36_En28
wire signed [17:0] number_of_pole_pairs_out1; // sfix18_En12
wire signed [17:0] Mod_2pi_Scale_And_Bit_Slice_out1; // sfix18_En14
// Rotor To Electrical Position
// <S8>/number_of_pole_pairs
assign number_of_pole_pairs_cast = {{2{R[17]}}, {R, 16'b0000000000000000}};
assign number_of_pole_pairs_out1 = number_of_pole_pairs_cast[33:16];
// <S8>/Mod_2pi_Scale_And_Bit_Slice
controllerHdl_Mod_2pi_Scale_And_Bit_Slice u_Mod_2pi_Scale_And_Bit_Slice (.u(number_of_pole_pairs_out1), // sfix18_En12
.y(Mod_2pi_Scale_And_Bit_Slice_out1) // sfix18_En14
);
assign E = Mod_2pi_Scale_And_Bit_Slice_out1;
endmodule // controllerHdl_Rotor_To_Electrical_Position
|
#include <bits/stdc++.h> using namespace std; struct grp { long long to, wt, edgeCode; char type; }; struct Node { long long x, dis; }; struct comp { inline bool operator()(const Node& n1, const Node& n2) const { if (n1.dis != n2.dis) return n1.dis < n2.dis; return n1.x < n2.x; } }; void dijkstra(long long n, vector<vector<grp> >& edges, vector<long long>& dis, vector<bool>& visited, vector<pair<long long, long long> >& par) { set<Node, comp> myset; for (long long i = 1; i <= n; ++i) { Node node; node.x = i, node.dis = dis[i]; myset.insert(node); } while (myset.size()) { set<Node>::iterator it = myset.begin(); Node node = *it; myset.erase(it); visited[node.x] = true; for (long long i = 0; i < edges[node.x].size(); ++i) { grp& edge = edges[node.x][i]; if (visited[edge.to]) { continue; } long long newDis = dis[node.x] + edge.wt; if (newDis < dis[edge.to] || (newDis == dis[edge.to] && edge.type == r )) { Node prevNode, newNode; prevNode.x = edge.to, prevNode.dis = dis[edge.to]; newNode.x = edge.to, newNode.dis = newDis; dis[edge.to] = newDis; par[edge.to] = {node.x, edge.edgeCode}; myset.erase(myset.find(prevNode)); myset.insert(newNode); } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, m, k; cin >> n >> m >> k; vector<vector<grp> > edges(n + 1); long long edgeCode = 0; for (long long i = 0; i < m; i++) { long long x, y, w; cin >> x >> y >> w; grp g; g.to = y, g.wt = w, g.type = r , g.edgeCode = edgeCode++; edges[x].push_back(g); g.to = x, g.edgeCode = edgeCode++; edges[y].push_back(g); } vector<pair<long long, long long> > trainPaths(k); for (long long i = 0; i < k; ++i) { long long y, w; cin >> y >> w; trainPaths[i] = {y, edgeCode}; grp g; g.to = y, g.wt = w, g.type = t , g.edgeCode = edgeCode++; edges[1].push_back(g); } vector<long long> dis(n + 1, 100000000000000000); vector<bool> visited(n + 1, false); vector<pair<long long, long long> > par(n + 1, {-1, -1}); dis[1] = 0; dijkstra(n, edges, dis, visited, par); long long ans = 0; for (long long i = 0; i < k; ++i) { long long dest = trainPaths[i].first, edgeCode = trainPaths[i].second; if (par[dest].first == 1 && par[dest].second == edgeCode) { continue; } ++ans; } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:51:19 05/03/2016
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_uart_tx8to8(
clk,
rst_n,
uart_ctl,
data_out,
data_sign,
data_valid,
rs_tx
);
input clk;
input rst_n;
input [2:0] uart_ctl;
input [7:0] data_out;
input data_sign;
output data_valid;
output rs_tx;
parameter bps9600 = 13'd5208, //baud is 9600bps
bps19200 = 13'd2603, //baud is 19200bps
bps38400 = 13'd1301, //baud is 38400bps
bps57600 = 13'd867, //baud is 57600bps
bps115200 = 13'd434, //baud is 115200bps
bps256000 = 13'd195; //baud is 115200bps
reg [12:0] cnt;
reg bps_sel;
reg [3:0] tran_cnt;
reg rs_tx;
reg sign_delay;
reg data_valid;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bps_sel <= 1'b0;
cnt <= 'h0;
end
else begin
case(uart_ctl)
3'h0: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
3'h1: cnt <= (cnt == bps19200) ? 'h0 : cnt + 1'b1;
3'h2: cnt <= (cnt == bps38400) ? 'h0 : cnt + 1'b1;
3'h3: cnt <= (cnt == bps57600) ? 'h0 : cnt + 1'b1;
3'h4: cnt <= (cnt == bps115200) ? 'h0 : cnt + 1'b1;
3'h5: cnt <= (cnt == bps256000) ? 'h0 : cnt + 1'b1;
default: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
endcase
bps_sel <= ~|cnt;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sign_delay <= 1'b0;
data_valid <= 1'b0;
end
else begin
if(bps_sel) sign_delay <= 1'b0;
else if(data_sign) sign_delay <= 1'b1;
if(data_sign | sign_delay) data_valid <= 1'b0;
else if(tran_cnt== 9) data_valid <= 1'b1;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
tran_cnt <= 'h9;
end
else if (bps_sel)begin
if(tran_cnt != 9) tran_cnt <= tran_cnt + 1'b1;
else if (data_sign|sign_delay) tran_cnt <= 'h0;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
rs_tx <= 1'b1;
end
else if (bps_sel) begin
if(tran_cnt == 0) rs_tx <= 1'b0 ;
else if(tran_cnt == 9) rs_tx <= 1'b1;
else rs_tx <= data_out[tran_cnt - 1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, cnt, flag; vector<int> graph[100005]; bool vis[100005]; void dfs(int node, int parent) { vis[node] = 1; int x, u, v, i; cnt++; for (i = 0; i < graph[node].size(); i++) { v = graph[node][i]; if (v == parent) continue; if (vis[v] == 1) flag = 1; else dfs(v, node); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; int i, j, k, u, v, x, sum = 0; for (i = 0; i < m; i++) { cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } for (i = 1; i <= n; i++) { if (vis[i] == 0) { cnt = 0; flag = 0; dfs(i, 0); if (flag == 1) sum += cnt; else sum += (cnt - 1); } } cout << n - sum << endl; }
|
#include <bits/stdc++.h> using namespace std; struct Query { int left; int right; int index; bool operator<(const Query &other) const { return right < other.right; } }; const int N = 1e6 + 100; int a[N]; int xorSum[N]; Query q[N]; int ans[N]; struct FenwickTree { FenwickTree() { fill(array, array + N, 0); } int lowbit(int a) { return a & -a; } void update(int i, int value) { while (i <= n) { array[i] ^= value; i += lowbit(i); } } int query(int i) { int res = 0; while (i > 0) { res ^= array[i]; i -= lowbit(i); } return res; } int n; int array[N]; } tr; int main() { int n, m, i, j; scanf( %d , &n); tr.n = n; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } scanf( %d , &m); for (i = 1; i <= m; i++) { scanf( %d%d , &q[i].left, &q[i].right); q[i].index = i; } sort(q + 1, q + 1 + m); map<int, int> last; for (i = 1, j = 1; i <= n; i++) { int &lastTmp = last[a[i]]; if (lastTmp > 0) { tr.update(lastTmp, a[i]); } lastTmp = i; tr.update(i, a[i]); xorSum[i] = xorSum[i - 1] ^ a[i]; for (; j <= m && q[j].right == i; j++) { ans[q[j].index] = xorSum[i] ^ xorSum[q[j].left - 1] ^ tr.query(q[j].right) ^ tr.query(q[j].left - 1); } } for (i = 1; i <= m; i++) { printf( %d n , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; char m[11], digit[10] = { 0 }, digitcount(0); scanf( %d%s , &n, &m); while (n != 0) { digit[digitcount++] = 0 + n % 10; n /= 10; } sort(digit, digit + digitcount); if (digit[0] == 0 ) { for (int i = 1; i < digitcount; ++i) { if (digit[i] != 0 ) { digit[0] = digit[i]; digit[i] = 0 ; break; } } } if (strcmp(m, digit) == 0) cout << OK << endl; else cout << WRONG_ANSWER << endl; return 0; }
|
//////////////////////////////////////////////////////////////////
// //
// Arithmetic Logic Unit (ALU) for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Supported functions: 32-bit add and subtract, AND, OR, //
// XOR, NOT, Zero extent 8-bit numbers //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_alu (
input [31:0] i_a_in,
input [31:0] i_b_in,
input i_barrel_shift_carry,
input i_status_bits_carry,
input [8:0] i_function,
output [31:0] o_out,
output [3:0] o_flags
);
wire [31:0] a, b, b_not;
wire [31:0] and_out, or_out, xor_out;
wire [31:0] sign_ex8_out, sign_ex_16_out;
wire [31:0] zero_ex8_out, zero_ex_16_out;
wire [32:0] fadder_out;
wire swap_sel;
wire not_sel;
wire [1:0] cin_sel;
wire cout_sel;
wire [3:0] out_sel;
wire carry_in;
wire carry_out;
wire overflow_out;
wire fadder_carry_out;
assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
// ========================================================
// A Select
// ========================================================
assign a = (swap_sel ) ? i_b_in : i_a_in ;
// ========================================================
// B Select
// ========================================================
assign b = (swap_sel ) ? i_a_in : i_b_in ;
// ========================================================
// Not Select
// ========================================================
assign b_not = (not_sel ) ? ~b : b ;
// ========================================================
// Cin Select
// ========================================================
assign carry_in = (cin_sel==2'd0 ) ? 1'd0 :
(cin_sel==2'd1 ) ? 1'd1 :
i_status_bits_carry ; // add with carry
// ========================================================
// Cout Select
// ========================================================
assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out :
i_barrel_shift_carry ;
// For non-addition/subtractions that incorporate a shift
// operation, C is set to the last bit
// shifted out of the value by the shifter.
// ========================================================
// Overflow out
// ========================================================
// Only assert the overflow flag when using the adder
assign overflow_out = out_sel == 4'd1 &&
// overflow if adding two positive numbers and get a negative number
( (!a[31] && !b_not[31] && fadder_out[31]) ||
// or adding two negative numbers and get a positive number
(a[31] && b_not[31] && !fadder_out[31]) );
// ========================================================
// ALU Operations
// ========================================================
`ifdef XILINX_FPGA
// XIlinx Spartan 6 DSP module
`ifdef XILINX_SPARTAN6_FPGA
xs6_addsub_n #(.WIDTH(33))
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_addsub_n #(.WIDTH(33))
`endif
u_xx_addsub_33(
.i_a ( {1'd0,a} ),
.i_b ( {1'd0,b_not} ),
.i_cin ( carry_in ),
.i_sub ( 1'd0 ),
.o_sum ( fadder_out ),
.o_co ( )
);
`else
assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
`endif
assign fadder_carry_out = fadder_out[32];
assign and_out = a & b_not;
assign or_out = a | b_not;
assign xor_out = a ^ b_not;
assign zero_ex8_out = {24'd0, b_not[7:0]};
assign zero_ex_16_out = {16'd0, b_not[15:0]};
assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]};
assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]};
// ========================================================
// Out Select
// ========================================================
assign o_out = out_sel == 4'd0 ? b_not :
out_sel == 4'd1 ? fadder_out[31:0] :
out_sel == 4'd2 ? zero_ex_16_out :
out_sel == 4'd3 ? zero_ex8_out :
out_sel == 4'd4 ? sign_ex_16_out :
out_sel == 4'd5 ? sign_ex8_out :
out_sel == 4'd6 ? xor_out :
out_sel == 4'd7 ? or_out :
and_out ;
assign o_flags = { o_out[31], // negative
|o_out == 1'd0, // zero
carry_out, // carry
overflow_out // overflow
};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int a[s.length()]; int ans = -1; int n = s.length(); for (int i = 0; i < s.length(); i++) { a[i] = int(s[i]) - 48; } for (int i = 0; i < n; i++) { if (a[i] % 8 == 0) { ans = a[i]; break; } else for (int j = i + 1; j < n; j++) { if ((a[i] * 10 + a[j]) % 8 == 0) { ans = a[i] * 10 + a[j]; break; } else for (int k = j + 1; k < n; k++) { if ((100 * a[i] + 10 * a[j] + a[k]) % 8 == 0) { ans = 100 * a[i] + 10 * a[j] + a[k]; break; } } } } if (ans != -1) { cout << YES << endl; cout << ans; } else cout << NO ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int n, x; int dist[501][501]; bool color[501]; unsigned short num_red; unsigned short ans[501][501][501], best[501][501], sizes[501]; unsigned short inf = ~0; vector<unsigned short> edge[501]; void dfs(unsigned short& now, unsigned short& before) { for (int i = 0; i < edge[now].size(); i++) { unsigned short& next = edge[now][i]; if (next == before) continue; dfs(next, now); } for (int i = 1; i <= n; i++) if (dist[now][i] <= x) { sizes[now] = 1; ans[now][i][1] = !color[i]; for (int j = 0; j < edge[now].size(); j++) { unsigned short& next = edge[now][j]; if (next == before) continue; int num_node; if (num_red < sizes[now] + sizes[next]) num_node = num_red; else num_node = sizes[now] + sizes[next]; for (unsigned short k = num_node;; k--) { unsigned short temp = inf; int num_node_1 = k - sizes[now]; if (num_node_1 < 0) num_node_1 = 0; int num_node_2 = k; if (k > sizes[next]) num_node_2 = sizes[next]; for (unsigned short j = num_node_1; j <= num_node_2; j++) { if (temp > ans[now][i][k - j] + best[next][j]) temp = ans[now][i][k - j] + best[next][j]; } num_node_1++; for (unsigned short j = num_node_1; j <= num_node_2; j++) { if (temp > ans[now][i][k - j + 1] + ans[next][i][j] - !color[i]) temp = ans[now][i][k - j + 1] + ans[next][i][j] - !color[i]; } ans[now][i][k] = temp; if (!k) break; } sizes[now] += sizes[next]; } } for (unsigned short i = 1; i <= num_red; i++) { best[now][i] = inf; for (unsigned short j = 1; j <= n; j++) { best[now][i] = min(best[now][i], ans[now][j][i]); } } } int main() { num_red = 0; memset(ans, 0xff, sizeof ans); memset(best, 0xff, sizeof best); memset(dist, 0x3f3f, sizeof dist); cin >> n >> x; unsigned short col; for (int i = 1; i <= n; i++) { cin >> col; num_red += col; color[i] = col == 1; } unsigned short a, b; int cost; for (int i = 1; i < n; i++) { cin >> a >> b >> cost; edge[a].push_back(b); edge[b].push_back(a); dist[a][b] = dist[b][a] = cost; } for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dist[i][j] = i == j ? 0 : min(dist[i][j], dist[i][k] + dist[k][j]); } } } unsigned short start = 1; unsigned short before = 0; dfs(start, before); if (best[1][num_red] == inf) cout << -1 << endl; else cout << best[1][num_red] << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int a[200], n, c = 0; double sum = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; sum += a[i]; } sort(a, a + n); while (double(sum / n) < 4.5) { sum += (5 - a[c]); c++; } cout << c; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int oo = numeric_limits<int>::max(); const int n_oo = numeric_limits<int>::min(); const int ALF = 26; struct SuffixAutomaton { int toInt(char c) { return c - a ; } char toChar(int j) { return char(j + a ); } struct Nodo { vector<int> hijos; int r; int l; int sl; Nodo(int L = 0) : hijos(ALF, -1), l(L), sl(0), r(1) {} int& operator[](int idx) { return hijos[idx]; } }; vector<int> orden; vector<long long int> seen; int n, ult; vector<Nodo> t; void extender(char c) { int act = n++; t.push_back(Nodo(t[ult].l + 1)); int p = ult; while (~p && t[p][toInt(c)] == -1) { t[p][toInt(c)] = act; p = t[p].sl; } if (~p) { int q = t[p][toInt(c)]; if (t[q].l == t[p].l + 1) { t[act].sl = q; } else { int clon = n++; t.push_back(t[q]); t[clon].l = t[p].l + 1; t[clon].r = 0; t[q].sl = t[act].sl = clon; while (~p && t[p][toInt(c)] == q) { t[p][toInt(c)] = clon; p = t[p].sl; } } } ult = act; } SuffixAutomaton(string s = ) : n(1), ult(0), t(1) { t[0].sl = -1; for (int i = 0; i < s.size(); i++) extender(s[i]); } void rTopoSort() { int m = t[ult].l; vector<vector<int> > bks(m + 1); for (int i = 0; i < n; i++) bks[t[i].l].push_back(i); for (int i = m; i >= 0; i--) for (int j = 0; j < bks[i].size(); j++) orden.push_back(bks[i][j]); } void cuentaRepeticiones() { rTopoSort(); for (int i = 0; i < n - 1; i++) { int u = orden[i]; int v = t[u].sl; t[v].r += t[u].r; } t[0].r = 1; } long long int dfs(int u) { if (seen[u]) return seen[u]; long long int& ret = seen[u]; ret = t[u].r; for (int i = 0; i < ALF; i++) { if (t[u][i] == -1) continue; ret += dfs(t[u][i]); } return ret; } void cuentaCaminos() { seen = vector<long long int>(n); dfs(0); } string kth(long long int k) { int u = 0; k++; string ans; if (k > seen[0]) return No such line. ; while (true) { k -= t[u].r; if (k <= 0) return ans; for (int i = 0; i < ALF; i++) { if (t[u][i] == -1) continue; if (k > seen[t[u][i]]) k -= seen[t[u][i]]; else { ans.push_back(toChar(i)), u = t[u][i]; break; } } } return ans; } void imprime() { for (int i = 0; i < n; i++) { cout << i << n ; cout << suffix link: << t[i].sl << n ; cout << length: << t[i].l << n ; cout << reps: << t[i].r << n ; for (int j = 0; j < ALF; j++) { if (t[i][j] == -1) continue; cout << toChar(j) << : << t[i][j] << ; } cout << n ; cout << n ; } } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); string s; cin >> s; SuffixAutomaton SA(s); SA.cuentaRepeticiones(); SA.cuentaCaminos(); int k; cin >> k; cout << SA.kth(k) << n ; return 0; }
|
`define STATE_BYTE_START 3'h0
`define STATE_BYTE_WAIT_FOR_BUSY 3'h1
`define STATE_BYTE_WAIT_FOR_NOT_BUSY 3'h2
`define STATE_STOPPED 3'h3
`define MESSAGE "Hello, world!\r\n"
`define MESSAGE_LEN 15
`define MESSAGE_LEN_BITS `MESSAGE_LEN * 8
module hello(
input clk_50,
input reset_n,
output tx);
reg [7:0] data;
reg dataReady;
wire busy;
reg [0:`MESSAGE_LEN_BITS - 1] message;
reg [1:0] state;
always @(posedge clk_50 or negedge reset_n)
if (reset_n == 1'b0) begin
data <= 0;
dataReady <= 0;
message <= `MESSAGE;
state <= `STATE_BYTE_START;
end else begin
case (state)
`STATE_BYTE_START:
if (message[0:7] != 0) begin
data <= message[0:7];
message <= {message[8:`MESSAGE_LEN_BITS - 1], 8'd0};
dataReady <= 1;
state <= `STATE_BYTE_WAIT_FOR_BUSY;
end else
state <= `STATE_STOPPED;
`STATE_BYTE_WAIT_FOR_BUSY:
if (busy) begin
dataReady <= 0;
state <= `STATE_BYTE_WAIT_FOR_NOT_BUSY;
end
`STATE_BYTE_WAIT_FOR_NOT_BUSY:
if (!busy)
state <= `STATE_BYTE_START;
default: state <= `STATE_STOPPED;
endcase
end
uart yuart(
.clk(clk_50),
.reset(!reset_n),
.data(data),
.dataReady(dataReady),
.busy(busy),
.tx(tx)
);
endmodule
|
#include <bits/stdc++.h> int main() { int n, input; int count = 1; int s = 3; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &input); if (input == 10) { if (s == 1) { count++; } s = 0; } else if (input == 1) { if (s == 0) { count++; } s = 1; } } printf( %d , count); return 0; }
|
module ft245_sync_if
#(
parameter DEBUG=0, // Enable it for simulation
parameter EXTRA_READ_GUARD=0, // Add an extra guard in the bus turn-around after read
parameter FAST_WRITE_OLD=0, // Jump from WRITE_OLD to WRITE
parameter USE_STATE_RESET=0) // Add an extra state for the reset state
(
/////////////////////////////////////////////////////
// Interface to the FTDI chip
/////////////////////////////////////////////////////
inout [7:0] adbus_io,
input rxf_n_i,
input txe_n_i,
output rd_n_o,
output wr_n_o,
input clk_i,
output oe_n_o,
output siwu_o,
/////////////////////////////////////////////////////
// Interface to the internal logic
/////////////////////////////////////////////////////
input rst_i,
// FPGA -> FTDI
input [7:0] tx_data_i,
input tx_empty_i,
output tx_read_o,
// FTDI -> FPGA
output [7:0] rx_data_o,
output rx_valid_o,
input rx_full_i);
`include "ft245_sync_if.v"
endmodule // ft245_sync_if
|
#include <bits/stdc++.h> using namespace std; int main() { int i, j, A, B, x, y; while (cin >> x >> y >> A >> B) { int Count = 0; for (i = A; i <= x; i++) { for (j = B; j <= y; j++) { if (i > j) { Count++; } } } cout << Count << endl; for (i = A; i <= x; i++) { for (j = B; j <= y; j++) { if (i > j) { cout << i << << j << endl; } } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuflp (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long Bpow(long long a, long long s) { if (s == 0) { return 1; } long long u = Bpow(a, s / 2); if (s & 1) return u * u % mod * a % mod; else return u * u % mod; } int32_t main() { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } long long ans = 0; for (long long i = 0; i < n - 2; i++) { long long now = a[i + 1]; for (long long j = i + 2; j < n; j++) { if (now > a[i] * 2) break; if ((a[i] ^ a[j]) == now && a[i] > a[j]) ++ans; now += a[j]; } } for (long long i = n - 1; i > 1; i--) { long long now = a[i - 1]; for (long long j = i - 2; j >= 0; j--) { if (now > a[i] * 2) break; if ((a[i] ^ a[j]) == now && a[i] > a[j]) ++ans; now += a[j]; } } cout << ans; }
|
// Module SEQUENCER
//
// Author: Goran Devic
// https://baltazarstudios.com/poem-fpga/
//
// Sequences the ASCII character data from display ROM, through the font ROM, and out
// as a monochrome wire data
module TXT (
input clk, // Input 25.175 MHz clock, this is a pixel clock for this VGA mode
input reset, // Input async. active low reset signal
output [9:0] pix_x, // The exact X coordinate of a pixel that is currently being drawn
output [9:0] pix_y, // The exact Y coordinate of a pixel that is currently being drawn
output reg[11:0] ascii_address, // Address into memory containing a current character code
input [7:0] char_line_data, // Currect character single line data (8 bit at a time)
output reg vga_out, // Final VGA out signal (monochrome)
output reg disp_mem_en, // Enable display memory to read
output reg font_mem_en, // Enable font memory to read
output hsync, output vsync
);
VGA vga0 (
.clk (clk),
.pixv (pix_x),
.pixh (pix_y),
.hsync(hsync),
.vsync(vsync)
);
reg [7:0] line_data; // Current character line data shifter
reg [11:0] xp = 0; // Temp
reg [11:0] yp = 0; // Temp
always @( posedge clk or negedge reset )
begin
if (!reset) begin
line_data <= 0; // Do a mandatory reset of all registers
ascii_address <= 0;
disp_mem_en <= 0;
font_mem_en <= 0;
end else begin
ascii_address <= 0;
// The sequence of getting a pixel to display is clocked by pix_x[2:0]
// Font it 16x16 pixels, that is two 8-bit words for each line
case (pix_x[2:0])
// State 1: send the address of a character to pick up onto the
// address bus of the display ROM. Enable both memories
// so the output of the first one propagates to the second one
// and make it output a line of character definition
3'b110: begin
// Calculate the address within the display memory of a current
// character based on the current pixel X and Y coordinates
// There are 40 chars/line, hence multiply Y by 40
xp[11:0] <= { 6'd0, pix_x[9:4] };
yp[11:0] <= { 6'd0, pix_y[9:4] };
ascii_address[11:0] <= (yp << 5) + (yp << 3) + xp;
//ascii_address[11:0] <= xp + yp * 40;
disp_mem_en <= 1;
font_mem_en <= 1;
end
// State 2: At this time clock the outputs of both memories should have
// stabilized and we can read a line of character definition
3'b111: begin
line_data <= char_line_data;
end
// State 3: This is timed to coencide with pix'000 when a new character
// line is going to be displayed (@always loop below).
// Disable outputs of display and font memories for now
3'b000: begin
font_mem_en <= 0;
disp_mem_en <= 0;
end
endcase
end
end
always @( posedge clk )
begin
// Depending on the position of a current character pixel, display individual pixels
// using a buffer that was loaded in a state machine (@always loop above)
case (pix_x[2:0])
3'b000: vga_out <= line_data[7];
3'b001: vga_out <= line_data[6];
3'b010: vga_out <= line_data[5];
3'b011: vga_out <= line_data[4];
3'b100: vga_out <= line_data[3];
3'b101: vga_out <= line_data[2];
3'b110: vga_out <= line_data[1];
3'b111: vga_out <= line_data[0];
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b) { return gcd(b, a % b); } else return a; } int main() { long long int l, r; cin >> l >> r; if (abs(l - r) < 2) { cout << -1 << endl; return 0; } long long int i = 0, j = 0, k = 0; long long int ans1 = 0, ans2 = 0, ans3 = 0; bool a = false; for (i = l; i <= r; i += 1) { for (j = i + 1; j <= r; j += 1) { if (gcd(i, j) == 1) { for (k = j + 1; j < r; j += 1) { if (gcd(j, k) == 1 and gcd(i, k) != 1) { a = true; break; } } } if (a == true) break; } if (a == true) break; } if (a == true) cout << i << << j << << k << endl; else cout << -1 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300 + 10; int n, a[maxn], b[maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , a + i); for (int i = 0; i < n; ++i) scanf( %d , b + i); vector<int> seq; for (int i = 0; i < n; ++i) if (b[i] != a[i]) { for (int j = i + 1; j < n; ++j) if (b[j] == a[i]) { for (int k = j; k > i; --k) { seq.push_back(k); swap(b[k], b[k - 1]); } break; } } printf( %d n , (int)seq.size()); for (int i = 0; i < seq.size(); ++i) printf( %d %d n , seq[i], seq[i] + 1); return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_cos (
enable,
clock,
dataa,
resetn,
result);
input enable;
input clock;
input resetn;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_cos fpc_cos(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(sub_wire0[31]),
.exponentout(sub_wire0[30:23]),
.mantissaout(sub_wire0[22:0])
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : adc.v
// Description : Behavioral ADC Model
// Author : Philip Tracton
// Created On : Wed Dec 16 12:36:20 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 16 12:36:20 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`include "wb_dsp_includes.vh"
module adc (/*AUTOARG*/
// Outputs
data_out, data_ready,
// Inputs
adc_clk, wb_clk, wb_rst, enable
) ;
parameter dw = 8;
parameter adc_image = "";
input adc_clk;
input wb_clk;
input wb_rst;
input enable;
output reg [dw-1:0] data_out;
output wire data_ready;
reg [2:0] shift_delay;
reg data_ready_local;
reg [dw-1:0] memory [1023:0];
reg [31:0] index;
reg [31:0] previous_index;
initial begin
$readmemh(adc_image, memory);
end
//
// Detect a change in the index (different clock domain) and
// if we are a new sample (data_ready). If so indicate this
// via the data_ready signal which we will hold for a single clock
// cycle. This is meant for the next block to know it is time
// to read and capture the output from the ADC
//
always @(posedge wb_clk)
if (wb_rst) begin
data_ready_local <= 0;
previous_index <=0;
end else begin
if ((index != previous_index)) begin
data_ready_local <= 1;
previous_index <= index;
end else begin
data_ready_local <= 0;
end
end
//
// Get data from file for this model. This is done
// in the ADC_CLK domain. Needs to synch data to WB_CLK
// domain.
//
always @(posedge adc_clk)
if (wb_rst) begin
data_out <=0;
index <= 0;
end else begin
if (enable) begin
data_out <= memory[index];
index <= index + 1;
end else begin
data_out <= 0;
index = 0;
end
end // else: !if(rst)
//
// Synchronize from ADC_CLK domain to
// WB_CLK domain. Next block should sample
// data_out on the data_ready signal.
//
assign data_ready = shift_delay[2];
always @(posedge wb_clk)
if (wb_rst) begin
shift_delay <= 1'b0;
end else begin
shift_delay <= {shift_delay[1:0], data_ready_local};
end
endmodule // adc
|
#include <bits/stdc++.h> using namespace std; template <class A, class B> inline bool mina(A &first, B second) { return (first > second) ? (first = second, 1) : 0; } template <class A, class B> inline bool maxa(A &first, B second) { return (first < second) ? (first = second, 1) : 0; } int mod_count[(105)]; void mult(long long c[(105)][(105)], long long a[(105)][(105)], long long b[(105)][(105)], int D, int mod) { for (int(i) = 0; (i) < (D); ++(i)) { for (int(j) = 0; (j) < (D); ++(j)) { c[i][j] = 0; for (int(k) = 0; (k) < (D); ++(k)) { c[i][j] += a[i][k] * b[k][j]; c[i][j] %= mod; } } } } long long temp[(105)][(105)]; long long res[(105)][(105)]; int main() { int N, B, K, X; int a; scanf( %d %d %d %d , &N, &B, &K, &X); for (int(i) = 0; (i) < (N); ++(i)) { scanf( %d , &a); mod_count[a % X]++; } long long mat[(105)][(105)]; memset(mat, 0, sizeof(mat)); for (int i = 0; i < X; i++) { for (int j = 0; j < X; j++) { for (int k = 0; k < X; k++) { if ((j * 10 + k) % X == i) { mat[i][j] += mod_count[k]; } } } } B--; memset(res, 0, sizeof(res)); for (int(i) = 0; (i) < (X); ++(i)) res[i][i] = 1; while (B) { if (B & 1) { mult(temp, res, mat, X, 1000000007); memcpy(res, temp, sizeof(temp)); } mult(temp, mat, mat, X, 1000000007); memcpy(mat, temp, sizeof(temp)); B >>= 1; } long long ans = 0; for (int(i) = 0; (i) < (X); ++(i)) { ans += res[K][i] * mod_count[i]; ans %= 1000000007; } cout << ans << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> int main() { long long int m, n, a; scanf( %lld %lld %lld , &m, &n, &a); if (m % a == 0 && n % a == 0) { printf( %lld , m * n / a / a); } if (m % a != 0 && n % a == 0) { printf( %lld , ((m + a) / a) * (n / a)); } if (m % a != 0 && n % a != 0) { printf( %lld , ((m + a) / a) * ((n + a) / a)); } if (m % a == 0 && n % a != 0) { printf( %lld , m / a * ((n + a) / a)); } }
|
/*
* Copyright (c) 2000 Chris Lattner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Really, this only tests the ability to compile the ~i expression as
* a parameter to a system task.
*/
module test;
reg i;
initial begin
i = 0;
$display("~i = %d", ~i);
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * f; } inline long long fast_pow(long long a, long long b, long long p) { long long t = 1; a %= p; while (b) { if (b & 1) t = t * a % p; b >>= 1ll; a = a * a % p; } return t; } long long inv[1010101], fac[1010101], n, h[1010101], K; inline long long C(long long n, long long m) { if (n < 0 || m < 0 || n < m) return 0; return fac[n] * inv[m] % 998244353 * inv[n - m] % 998244353; } int main() { n = read(), K = read(); long long ttt = 0; for (int i = 1; i <= n; i++) { h[i] = read(); } for (int i = 1; i <= n; i++) { if (h[i] != h[(i + 1 == n + 1) ? 1 : (i + 1)]) ttt++; } fac[0] = inv[0] = inv[1] = 1; for (long long i = 2; i <= n; i++) inv[i] = (998244353 - (998244353 / i) * inv[998244353 % i] % 998244353) % 998244353; for (int i = 2; i <= n; i++) inv[i] = inv[i - 1] * inv[i] % 998244353; for (long long i = 1; i <= n; i++) fac[i] = fac[i - 1] * i % 998244353; long long ans = 0; long long inv2 = fast_pow(2ll, 998244353 - 2, 998244353); for (long long i = 0; i <= ttt; i++) { ans = (ans + C(ttt, i) * fast_pow(K - 2 + 998244353, ttt - i, 998244353) % 998244353 * ((fast_pow(2ll, i, 998244353) - ((i % 2 == 1) ? 0 : C(i, i / 2))) * inv2 % 998244353 + 998244353) % 998244353) % 998244353; } cout << ans * fast_pow(K, n - ttt, 998244353) % 998244353; return 0; }
|
#include <bits/stdc++.h> using namespace std; bool cmp(int u, int y) { return u > y; } int main() { int i, j; int n, m, x; int a[100009], b[100009]; int cnt; while (scanf( %d %d , &n, &x) != EOF) { for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n, cmp); for (i = 0; i < n; i++) scanf( %d , &b[i]); sort(b, b + n); cnt = 0; int k = 0; for (i = 0; i < n; i++) { for (j = k; j < n; j++) { if (a[i] != -0x3fffffff && b[j] != -0x3fffffff) { if (a[i] + b[j] >= x) { a[i] = -0x3fffffff; b[j] = -0x3fffffff; cnt++; k = j; break; } } } } printf( 1 %d n , cnt); } }
|
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