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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_LP_V
`define SKY130_FD_SC_LP__HA_LP_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_lp (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_lp (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_LP_V
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#include <bits/stdc++.h> using namespace std; long long nC2(int n) { if (n == 0) return 0; return ((long long)n * (n - 1)) / 2; } void solve() { int n, m; scanf( %d %d , &n, &m); long long Kmin, Kmax; int r = n % m; Kmin = nC2((n + m - 1) / m) * r + nC2(n / m) * (m - r); Kmax = nC2(n - m + 1); printf( %lld %lld n , Kmin, Kmax); } int main() { int tt; tt = 1; for (int i = 0; i < tt; ++i) { solve(); } return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; const long long MOD = 1e9 + 7; const long long N = 1e6 + 10; const long long INF = 1e18 + 10; bool isPrime(long long x) { if (x <= 1) return false; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) return false; } return true; } vector<bool> prime(N, true); vector<long long> primes; void seive() { prime[0] = prime[1] = false; for (long long i = 2; i * i <= N; i++) { if (prime[i]) { for (long long j = i + i; j < N; j += i) prime[j] = false; } } for (long long i = 0; i < N; i++) { if (prime[i]) { primes.emplace_back(i); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); seive(); long long n; cin >> n; if (isPrime(n)) { cout << 1 << endl; cout << n << endl; return 0; } long long cur = n; while (cur--) { if (isPrime(cur)) { debug() << [ << cur : << (cur) << ] ; if (cur + 2 == n) { cout << 2 << endl; cout << 2 << << cur << endl; return 0; } int target = n - cur; debug() << [ << target : << (target) << ] ; int L = 0, R = (int)primes.size() - 1; while (L <= R) { if (primes[L] + primes[R] == target) { cout << 3 << endl; cout << primes[L] << << primes[R] << << cur << endl; return 0; } else if (primes[L] + primes[R] > target) R--; else { debug() << [ << L : << (L) << ] [ << R : << (R) << ] ; debug() << [ << primes[L] : << (primes[L]) << ] [ << primes[R] : << (primes[R]) << ] ; L++; } } } } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s6s (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
|
module arbitrator(
//input
reset,
clk,
request0,
release0,
request1,
release1,
request2,
release2,
request3,
release3,
request4,
release4,
request5,
release5,
//output
permit0,
permit1,
permit2,
permit3,
permit4,
permit5
//state
);
input reset;
input clk;
input request0;
input release0;
input request1;
input release1;
input request2;
input release2;
input request3;
input release3;
input request4;
input release4;
input request5;
input release5;
output permit0;
output permit1;
output permit2;
output permit3;
output permit4;
output permit5;
//output [3:0] state;
reg permit0;
reg permit1;
reg permit2;
reg permit3;
reg permit4;
reg permit5;
parameter REQUEST0 =4'b0000;
parameter REQUEST1 =4'b0001;
parameter REQUEST2 =4'b0010;
parameter REQUEST3 =4'b0011;
parameter REQUEST4 =4'b0100;
parameter REQUEST5 =4'b0101;
parameter WAIT_RELEASE =4'b0110;
parameter WAIT_CYCLES =4'b0111;
parameter FINISH =4'b1111;
reg [3:0] state;
reg [2:0] count;
reg [3:0] index;
always@ (posedge clk or negedge reset)
begin
if(!reset)
begin
state <= REQUEST0;
permit0 <= 0;
permit1 <= 0;
permit2 <= 0;
permit3 <= 0;
permit4 <= 0;
permit5 <= 0;
index <= 0;
count <=0;
end
else
begin
case (state)
REQUEST0:
begin
if(request0)
begin
permit0 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST1;
end
else
begin
state <= REQUEST1;
end
end
REQUEST1:
begin
if(request1)
begin
permit1 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST2;
end
else
begin
state <= REQUEST2;
end
end
REQUEST2:
begin
if(request2)
begin
permit2 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST3;
end
else
begin
state <= REQUEST3;
end
end
REQUEST3:
begin
if(request3)
begin
permit3 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST4;
end
else
begin
state <= REQUEST4;
end
end
REQUEST4:
begin
if(request4)
begin
permit4 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST5;
end
else
begin
state <= REQUEST5;
end
end
REQUEST5:
begin
if(request5)
begin
permit5 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST0;
end
else
begin
state <= REQUEST0;
end
end
WAIT_RELEASE:
begin
if(release0 | release1 | release2 | release3 | release4 | release5)
begin
permit0 <= 0;
permit1 <= 0;
permit2 <= 0;
permit3 <= 0;
permit4 <= 0;
permit5 <= 0;
count <= 0;
state <= WAIT_CYCLES;
end
else
state <= WAIT_RELEASE;
end
WAIT_CYCLES:
begin
if(count==4)
state <= FINISH;
else
count <= count+1;
end
FINISH:
begin
state <= index;
end
default:state <= REQUEST0;
endcase
end
end
endmodule
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#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> inline T1 max(T1 a, T2 b) { return a < b ? b : a; } template <typename T1, typename T2> inline T1 min(T1 a, T2 b) { return a < b ? a : b; } const char lf = n ; namespace ae86 { const int bufl = 1 << 15; char buf[bufl], *s = buf, *t = buf; inline int fetch() { if (s == t) { t = (s = buf) + fread(buf, 1, bufl, stdin); if (s == t) return EOF; } return *s++; } inline int ty() { int a = 0; int b = 1, c = fetch(); while (!isdigit(c)) b ^= c == - , c = fetch(); while (isdigit(c)) a = a * 10 + c - 48, c = fetch(); return b ? a : -a; } inline double td() { double a = 0, d = 0.1; int b = 1, c = fetch(); while (!isdigit(c)) b ^= c == - , c = fetch(); while (isdigit(c)) a = a * 10 + c - 48, c = fetch(); if (c != . ) return b ? a : -a; while (c = fetch(), isdigit(c)) a += d * (c - 48), d *= 0.1; return b ? a : -a; } } // namespace ae86 using ae86::td; using ae86::ty; const int _ = 23, __ = 1 << 20; int n, nn, lim, bcnt[__] = {0}; double ps[_], sps[__] = {0}, f[__] = {0}, ans[_] = {0}; int main() { ios::sync_with_stdio(0), cout.tie(nullptr); n = ty(), nn = 1 << n, lim = ty(); int cnts = 0; for (int i = 0; i < n; i++) ps[i] = td(), cnts += ps[i] > 0; if (cnts < lim) { for (int i = 0; i < n; i++) cout << 01 [ps[i] > 0] << n [i == n - 1]; return 0; } for (int i = 0; i < nn; i++) for (int j = 0; j < n; j++) if ((((i) >> (j)) & 1)) sps[i] += ps[j]; bcnt[0] = 0; for (int i = 1; i < nn; i++) bcnt[i] = bcnt[i >> 1] + (i & 1); f[0] = 1; for (int i = 0; i < nn; i++) { if (bcnt[i] == lim) for (int j = 0; j < n; j++) if ((((i) >> (j)) & 1)) ans[j] += f[i]; if (bcnt[i] >= lim) continue; for (int j = 0; j < n; j++) if (!(((i) >> (j)) & 1)) f[i | (1 << (j))] += f[i] * ps[j] / (1 - sps[i]); } for (int i = 0; i < n; i++) cout << setprecision(11) << fixed << ans[i] << n [i == n - 1]; return 0; }
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#include <bits/stdc++.h> using namespace std; int n, m, k; vector<vector<int> > v; bool transponer; void escribe() { if (transponer) { vector<vector<int> > nextv(m + 2, vector<int>(n + 2, 0)); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) nextv[j][i] = v[i][j]; swap(n, m); v = nextv; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (v[i][j]) cout << * ; else cout << . ; cout << endl; } } int valor(int i, int j) { if (i == 1) return 0; if (j == 1) return 1; if (j == m) return 3; return 4; } void genera() { int act = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (act + valor(i, j) > k) { int resta = k - act; if (resta == 1) { if (m > j) v[i][m] = 1; else v[i + 1][1] = 1; } else if (resta == 2) { if (m - j + 1 >= 3) v[i][m - 1] = 1; else if (m - j + 1 == 2) v[i][m] = v[i + 1][m] = v[i + 1][m - 1] = 1; else v[i + 1][2] = 1; } else { if (m - j + 1 >= 4) v[i][m] = v[i][m - 2] = 1; else if (j == 2) { if (i < n) v[i][m] = v[i + 1][m] = v[i + 1][m - 1] = v[i + 1][1] = v[i + 1][2] = 1; else { v[i][1] = 0; v[i][2] = v[i][4] = 1; } } else v[i][m] = v[i + 1][m] = v[i + 1][m - 1] = v[i + 1][1] = 1; } escribe(); return; } v[i][j] = 1; act += valor(i, j); if (act == k) { escribe(); return; } } } } int main() { ios::sync_with_stdio(false); int casos; cin >> casos; for (int cas = 0; cas < casos; cas++) { if (cas > 0) cout << endl; cin >> n >> m >> k; transponer = false; if (n > m) { swap(n, m); transponer = true; } v = vector<vector<int> >(n + 2, vector<int>(m + 2, 0)); int total = (n - 1) + (n - 1) * (m - 2) * 4 + (n - 1) * 3; if (k > total or k == total - 1 or k == total - 2 or k == total - 4 or k == total - 5) { cout << -1 << endl; continue; } if (k == total - 8) { if (n > 3) { cout << -1 << endl; continue; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m - 1; j++) v[i][j] = 1; escribe(); continue; } if (m == 3 and k == 7) { for (int i = 1; i <= 3; i++) for (int j = 1; j <= 3; j++) v[i][j] = 1; v[1][1] = v[3][1] = v[1][3] = 0; escribe(); continue; } genera(); } }
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////////////////////////////////////////////////////////////////////////////////
//
// MIT License
//
// Copyright (c) 2017 Smartfox Data Solutions Inc.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
////////////////////////////////////////////////////////////////////////////////
// A super simple DUT
module starter_dut (
// Outputs
data_out, valid_out,
// Inputs
clk, rst, data_in, valid_in
) ;
input clk;
input rst;
input [7:0] data_in;
input valid_in;
output [7:0] data_out;
output valid_out;
reg [7:0] data_out;
reg valid_out;
always @(posedge clk or posedge rst) begin
if (rst) begin
data_out <= 'h0;
valid_out <= 'h0;
end
else begin
data_out <= data_in;
valid_out <= valid_in;
end
end
endmodule // dut
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#include <bits/stdc++.h> using namespace std; int n, mm, s, it; int a[200005], r[200005], so[200005], ne[200005]; bool u[200005]; string ss, na[200005]; vector<int> v[200005]; queue<int> q; map<string, int> m; inline string sb(string v) { for (int i = 0; i < v.size(); i++) if (v[i] < a ) v[i] += 32; return v; } inline void ope(string &x) { x = sb(x); if (m[x]) return; m[x] = ++s; for (int i = 0; i < x.size(); i++) r[s] += (x[i] == r ); na[s] = x; so[s] = s; return; } inline bool cmp(int x, int y) { if (r[x] != r[y]) return r[x] < r[y]; return na[x].size() < na[y].size(); } inline bool same(int x, int y) { return r[x] == r[y] && na[x].size() == na[y].size(); } inline void dfs(int x, int y) { if (u[x]) return; u[x] = 1; ne[x] = y; for (int i = 0; i < v[x].size(); i++) dfs(v[x][i], y); } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> ss; ope(ss); a[i] = m[ss]; } m[ ] = 200002; r[200002] = 2147483640; cin >> mm; for (int i = 1; i <= mm; i++) { string p, q; cin >> p >> q; ope(p); ope(q); v[m[q]].push_back(m[p]); } sort(so + 1, so + s + 1, cmp); for (int i = 1; i <= s; i++) dfs(so[i], so[i]); long long rr = 0, ll = 0; for (int i = 1; i <= n; i++) rr += r[ne[a[i]]], ll += na[ne[a[i]]].size(); cout << rr << << ll << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MAX = 2e5 + 10; int n; string s, xx = RGB ; int getID(char c) { if (c == R ) return 1; else if (c == G ) return 2; return 3; } int last[4]; int dp[MAX][4][4][4]; int mn = 1e9; vector<char> v, ans; int tokyoGhoul(int cur, int cnt) { if (cur == n) { if (cnt < mn) { mn = cnt; ans = v; } return cnt; } int &ret = dp[cur][last[0]][last[1]][last[2]]; if (~ret) return ret; ret = 1e18; for (int i = 0; i < xx.size(); i++) { int id = getID(xx[i]); int prev = last[id]; char ch = xx[i]; if (prev == -1 || (cur - prev) != 1) { v.push_back(ch); last[id] = cur; if (xx[i] != s[cur]) ret = min(ret, tokyoGhoul(cur + 1, cnt + 1)); else ret = min(ret, tokyoGhoul(cur + 1, cnt)); last[id] = prev; v.pop_back(); } } return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> s; vector<string> vv; int cnt = 0, cnt2 = 0; string s1 = , s2 = ; for (int j = 0; j < 3; j++) { cnt = 0, s1 = ; s1 += xx[j]; if (s[0] != s1[0]) cnt++; for (int i = 1; i < n; i++) { if (s[i] == s1[i - 1]) { cnt++; bool f = 1; for (int j = 0; j < xx.size(); j++) { if (s1[i - 1] != xx[j] && (i + 1 == n || s[i + 1] != xx[j])) { s1 += xx[j]; f = 0; break; } } if (f) for (int j = 0; j < xx.size(); j++) { if (s[i - 1] != xx[j]) { s1 += xx[j]; break; } } } else s1 += s[i]; } if (cnt < mn) { mn = cnt; s2 = s1; } } cout << mn << endl; for (auto i : s2) cout << i; cout << endl; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 5; int n, a[maxn], belong[maxn], bn = 1; int ans[maxn][maxn]; struct node { int l, r; } block[maxn]; bool cmp(node x, node y) { return (x.r - x.l) > (y.r - y.l); } int main() { int l, r, flag; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], belong[i] = 1; belong[0] = 1; block[1].l = 0; block[1].r = n; for (int i = 1; i <= n; i++) { sort(block + 1, block + 1 + bn, cmp); flag = 0; int bto = bn; for (int b = 1; b <= bto; b++) { l = block[b].l; r = block[b].r; if (a[i] > bto - b + 1) { if (flag == 0) while (a[i] > bto - b && l < r) ans[i][l++] = 1, a[i]--; else while (a[i] > bto - b && l <= r) ans[i][l++] = 1, a[i]--; if (--l < r) { flag = 1; block[++bn].l = block[b].l; block[bn].r = l; block[b].l = l + 1; for (int j = block[bn].l; j <= l; j++) belong[j] = bn; } } else if (a[i] > 0) { ans[i][l] = 1; a[i]--; if (l < r) { flag = 1; belong[l] = ++bn; block[bn].l = block[bn].r = l; block[b].l = l + 1; } } } } cout << bn << endl; for (int j = 0; j <= n; j++) { for (int i = 1; i <= n; i++) { cout << ans[i][j]; } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int size_c = 26; const int Maxn = 500010 << 1; string s[100020]; int w[100020]; int n; struct Suffix_Automaton { int ch[Maxn][size_c]; int f[Maxn]; int ml[Maxn]; int sz, head, tail; long long val[Maxn]; int cnt[Maxn], id[Maxn]; inline int getidx(char c) { return c - a ; } int node() { sz++; f[sz] = ml[sz] = 0; memset(ch[sz], 0, sizeof(ch[sz])); return sz; } void init() { head = tail = 1; sz = 0; node(); } void insert(int idx) { head = tail = 1; for (int i = 0; i < s[idx].size(); i++) add(getidx(s[idx][i])); } void add(int c) { int p = tail; if (ch[p][c]) { int q = ch[p][c]; if (ml[q] == ml[p] + 1) { tail = ch[p][c]; } else { int nq = node(); memcpy(ch[nq], ch[q], sizeof(ch[q])); f[nq] = f[q]; f[q] = nq; ml[nq] = ml[p] + 1; for (; p && ch[p][c] == q; p = f[p]) ch[p][c] = nq; tail = nq; } return; } int np = node(); ml[np] = ml[p] + 1; tail = np; for (; p && !ch[p][c]; p = f[p]) ch[p][c] = np; if (!p) f[np] = head; else if (ml[ch[p][c]] == ml[p] + 1) f[np] = ch[p][c]; else { int q = ch[p][c]; int nq = node(); memcpy(ch[nq], ch[q], sizeof(ch[q])); f[nq] = f[q]; f[q] = f[np] = nq; ml[nq] = ml[p] + 1; for (; p && ch[p][c] == q; p = f[p]) ch[p][c] = nq; } } void solve() { init(); cin >> n; for (int i = 1; i <= n; i++) cin >> s[i]; for (int i = 1; i <= n; i++) scanf( %d , w + i); for (int i = 1; i <= n; i++) insert(i); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= sz; i++) cnt[ml[i]]++; for (int i = 1; i <= sz; i++) cnt[i] += cnt[i - 1]; for (int i = 1; i <= sz; i++) id[cnt[ml[i]]--] = i; memset(cnt, 0, sizeof(cnt)); for (int idx = 1; idx <= n; idx++) { int rt = 1; for (int i = 0; i < s[idx].size(); i++) { rt = ch[rt][getidx(s[idx][i])]; val[rt] += w[idx]; } } for (int i = sz; i >= 1; i--) { int cur = id[i]; val[f[cur]] += val[cur]; } long long ans = 0; for (int i = 1; i <= sz; i++) ans = max(ans, 1LL * ml[i] * val[i]); cout << ans << endl; } } suf; int main() { suf.solve(); }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n + 1]; for (int i = 1; i <= n; i++) cin >> arr[i]; int x; cin >> x; int w, l; while (x--) { cin >> w >> l; if (w == 1) { arr[2] += arr[1] - l; arr[1] = 0; continue; } if (w == n) { arr[n - 1] += l - 1; arr[n] = 0; continue; } arr[w - 1] += l - 1; arr[w + 1] += arr[w] - l; arr[w] = 0; } for (int i = 1; i <= n; i++) { cout << arr[i] << endl; } return 0; }
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring signed by unsigned divider ////
//// Uses the non-restoring unsigned by unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_su.v,v 1.7 2009-02-06 03:48:26 zeus Exp $
//
// $Date: 2009-02-06 03:48:26 $
// $Revision: 1.7 $
// $Author: zeus $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:09 rherveille
//
//
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_su(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width :0] s; // remainder
output div0;
output ovf;
reg [d_width:0] q, s;
reg div0;
reg ovf;
//
// variables
//
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] szpipe, sdpipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// module body
//
// check d, take abs value
always @(posedge clk)
if (ena)
if (d[d_width-1])
id <= ~d +1'h1;
else
id <= d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= ~z +1'h1;
else
iz <= z;
// generate szpipe (z sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
szpipe[0] <= z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
szpipe[n] <= szpipe[n-1];
end
// generate sdpipe (d sign bit pipe)
integer m;
always @(posedge clk)
if(ena)
begin
sdpipe[0] <= d[d_width-1];
for(m=1; m <= d_width+1; m=m+1)
sdpipe[m] <= sdpipe[m-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
begin
q <= (szpipe[d_width+1]^sdpipe[d_width+1]) ?
((~iq) + 1'h1) : ({1'b0, iq});
s <= (szpipe[d_width+1]) ?
((~is) + 1'h1) : ({1'b0, is});
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= idiv0;
ovf <= iovf;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300000; int parent[N], size[N]; vector<pair<int, pair<int, int>>> v; pair<int, int> q[N]; long long ans[N]; int Find(int a) { if (parent[a] == a) return a; return parent[a] = Find(parent[a]); } void Union(int a, int b) { parent[Find(b)] = Find(a); } long long doit(int a, int b) { int x = Find(a); int y = Find(b); long long p = size[x]; long long qq = size[y]; long long anss = p * qq; size[x] += size[y]; Union(x, y); return anss; } int main(int argc, char const *argv[]) { for (int i = 0; i < N; i++) parent[i] = i, size[i] = 1; int n, m, a, b, c; scanf( %d%d , &n, &m); for (int i = 0; i < n - 1; ++i) { scanf( %d%d%d , &a, &b, &c); v.push_back({c, {a, b}}); } sort(v.begin(), v.end()); for (int i = 0; i < m; i++) { scanf( %d , &a); q[i] = {a, i}; } sort(q, q + m); int at = 0; long long sum = 0; for (int i = 0; i < m; i++) { if (at < v.size()) { while (v[at].first <= q[i].first) { if (at >= v.size()) break; long long kk = doit(v[at].second.first, v[at].second.second); sum += kk; at++; if (at >= v.size()) break; } } ans[q[i].second] = sum; } for (int i = 0; i < m; i++) { printf( %lld , ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[41][1001][1001]; int bir(int n) { int s = 0; while (n > 0) { s += n % 2; n /= 2; } return s; } bool fun(int x, int i) { if (i < 0) return 0; return ((x >> i) & 1); } bool funk(int a, int b, int c, int m) { for (int i = 0; i < m; i++) { if (!(fun(a, i) || fun(b, i) || fun(c, i) || fun(b, i - 1) || fun(b, i + 1))) return 1; } return 0; } int main() { int n, m, i, j, msk, pmsk, tmsk, ans = 1e9; cin >> n >> m; if (n < m) swap(n, m); for (i = 0; i <= n; i++) { for (pmsk = 0; pmsk < (1 << m); pmsk++) { for (msk = 0; msk < (1 << m); msk++) { a[i][pmsk][msk] = 1e9; } } } for (i = 0; i < (1 << m); i++) a[0][0][i] = bir(i); for (i = 1; i <= n; i++) { for (pmsk = 0; pmsk < (1 << m); pmsk++) { for (msk = 0; msk < (1 << m); msk++) { for (tmsk = 0; tmsk < (1 << m); tmsk++) { if (funk(tmsk, pmsk, msk, m)) continue; a[i][pmsk][msk] = min(a[i][pmsk][msk], a[i - 1][tmsk][pmsk] + bir(msk)); } } } } for (i = 0; i < (1 << m); i++) { ans = min(ans, a[n][i][0]); } cout << n * m - ans; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_4_V
`define SKY130_FD_SC_HDLL__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_4_V
|
`define Seq_NO 4'h0
`define Seq_CI 4'h1
`define Seq_CR 4'h2
`define Seq_JI 4'h3
`define Seq_JR 4'h4
`define Seq_JZ 4'h5
`define Seq_JN 4'h6
`define Seq_WZ 4'h7
`define Seq_WN 4'h8
`define Seq_State_Reset 3'h0
`define Seq_State_Ready 3'h1
`define Seq_State_WaitZ 3'h2
`define Seq_State_WaitN 3'h3
`define Seq_State_Error 3'h4
// Instruction Format
// no -> 0000_xxxx_xxxx_xxxx_xxxx
// ci dev(d):cmd(c) -> 0001_xddd_cccc_xxxx_xxxx
// ci dev(d):cmd(c) arg(a) -> 0001_xddd_cccc_iiii_iiii
// cr dev(d):cmd(c) src(s) -> 0010_xddd_cccc_xxxx_xxss
// ji label(l) -> 0011_aaaa_aaaa_xxxx_xxxx
// jr src(s) -> 0100_xxxx_xxxx_xxxx_xxss
// jz label(l) src(s) -> 0101_aaaa_aaaa_xxxx_xxss
// jn label(l) src(s) -> 0110_aaaa_aaaa_xxxx_xxss
// wz src(s) -> 0111_xxxx_xxxx_xxxx_xxss
// wn src(s) -> 1000_xxxx_xxxx_xxxx_xxss
module Seq(clock,reset,inst,inst_text,inst_en,ireg_0,ireg_1,ireg_2,ireg_3,next,oreg,oreg_wen);
input wire clock;
input wire reset;
input wire [19:0] inst;
input wire [4095:0] inst_text;
input wire inst_en;
input wire [7:0] ireg_0;
input wire [7:0] ireg_1;
input wire [7:0] ireg_2;
input wire [7:0] ireg_3;
output wire [7:0] next;
output wire [11:0] oreg;
output wire [7:0] oreg_wen;
reg [2:0] s_State;
reg [7:0] s_Address;
reg [11:0] s_OReg;
reg [7:0] s_ORegWen;
wire [3:0] w_InstCode;
wire [2:0] w_InstDst;
wire [3:0] w_InstDstCmd;
wire [7:0] w_InstImm0;
wire [7:0] w_InstImm1;
wire [1:0] w_InstSrc;
wire [7:0] w_IregMux;
wire [7:0] w_OregWen;
reg [515*8-1:0] d_Instruction;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign next = s_Address;
assign oreg = s_OReg;
assign oreg_wen = s_ORegWen;
assign w_InstCode = inst[19:16];
assign w_InstDst = inst[14:12];
assign w_InstDstCmd = inst[11:8];
assign w_InstImm0 = inst[15:8];
assign w_InstImm1 = inst[7:0];
assign w_InstSrc = inst[1:0];
assign w_IregMux = w_InstSrc == 0 ? ireg_0 :
w_InstSrc == 1 ? ireg_1 :
w_InstSrc == 2 ? ireg_2 :
ireg_3;
assign w_OregWen = w_InstDst == 0 ? 8'b00000001 :
w_InstDst == 1 ? 8'b00000010 :
w_InstDst == 2 ? 8'b00000100 :
w_InstDst == 3 ? 8'b00001000 :
w_InstDst == 4 ? 8'b00010000 :
w_InstDst == 5 ? 8'b00100000 :
w_InstDst == 6 ? 8'b01000000 :
8'b10000000;
always @ (posedge clock) begin
if (reset) begin
s_State <= `Seq_State_Reset;
s_Address <= 0;
s_OReg <= 0;
s_ORegWen <= 0;
end
else begin
case (s_State)
`Seq_State_Reset: begin
s_State <= `Seq_State_Ready;
s_Address <= 0;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Seq_NO: begin
s_State <= `Seq_State_Ready;
s_Address <= s_Address + 1;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_CI: begin
s_State <= `Seq_State_Ready;
s_Address <= s_Address + 1;
s_OReg <= {w_InstDstCmd,w_InstImm1};
s_ORegWen <= w_OregWen;
end
`Seq_CR: begin
s_State <= `Seq_State_Ready;
s_Address <= s_Address + 1;
s_OReg <= {w_InstDstCmd,w_IregMux};
s_ORegWen <= w_OregWen;
end
`Seq_JI: begin
s_State <= `Seq_State_Ready;
s_Address <= w_InstImm0;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_JR: begin
s_State <= `Seq_State_Ready;
s_Address <= w_IregMux;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_JZ: begin
s_State <= `Seq_State_Ready;
s_Address <= w_IregMux == 0 ? w_InstImm0 : s_Address + 1;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_JN: begin
s_State <= `Seq_State_Ready;
s_Address <= w_IregMux != 0 ? w_InstImm0 : s_Address + 1;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_WZ: begin
s_State <= w_IregMux == 0 ? `Seq_State_Ready : `Seq_State_WaitZ;
s_Address <= w_IregMux == 0 ? s_Address + 1 : s_Address;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_WN: begin
s_State <= w_IregMux != 0 ? `Seq_State_Ready : `Seq_State_WaitN;
s_Address <= w_IregMux != 0 ? s_Address + 1 : s_Address;
s_OReg <= 0;
s_ORegWen <= 0;
end
default: begin
s_State <= `Seq_State_Error;
s_Address <= 0;
s_OReg <= 0;
s_ORegWen <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `Seq_State_Ready;
s_Address <= s_Address;
s_OReg <= 0;
s_ORegWen <= 0;
end // else: !if(inst_en)
end // case: `Seq_State_Ready
`Seq_State_WaitZ: begin
s_State <= w_IregMux == 0 ? `Seq_State_Ready : `Seq_State_WaitZ;
s_Address <= w_IregMux == 0 ? s_Address + 1 : s_Address;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_State_WaitN: begin
s_State <= w_IregMux != 0 ? `Seq_State_Ready : `Seq_State_WaitN;
s_Address <= w_IregMux != 0 ? s_Address + 1 : s_Address;
s_OReg <= 0;
s_ORegWen <= 0;
end
`Seq_State_Error: begin
s_State <= `Seq_State_Error;
s_Address <= 0;
s_OReg <= 0;
s_ORegWen <= 0;
end
default: begin
s_State <= `Seq_State_Error;
s_Address <= 0;
s_OReg <= 0;
s_ORegWen <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
d_Instruction = {"EN"," ",inst_text};
end
else begin
d_Instruction = {"NN"};
end
end
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Seq_NO: begin
$sformat(d_Input,"EN NO %2X %2X %2X %2X",ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_CI: begin
$sformat(d_Input,"EN (CI %1D %1X %2X) %2X %2X %2X %2X",w_InstDst,w_InstDstCmd,w_InstImm1,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_CR: begin
$sformat(d_Input,"EN (CR %1D %1X %1D) %2X %2X %2X %2X",w_InstDst,w_InstDstCmd,w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_JI: begin
$sformat(d_Input,"EN (JI %2X) %2X %2X %2X %2X",w_InstImm0,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_JR: begin
$sformat(d_Input,"EN (JR %1D) %2X %2X %2X %2X",w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_JZ: begin
$sformat(d_Input,"EN (JZ %2X %1D) %2X %2X %2X %2X",w_InstImm0,w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_JN: begin
$sformat(d_Input,"EN (JN %2X %1D) %2X %2X %2X %2X",w_InstImm0,w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_WZ: begin
$sformat(d_Input,"EN (WZ %2X %1D) %2X %2X %2X %2X",w_InstImm0,w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
`Seq_WN: begin
$sformat(d_Input,"EN (WN %2X %1D) %2X %2X %2X %2X",w_InstImm0,w_InstSrc,ireg_0,ireg_1,ireg_2,ireg_3);
end
default: begin
$sformat(d_Input,"EN (? %4X) %2X %2X %2X %2X",inst[15:0],ireg_0,ireg_1,ireg_2,ireg_3);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Seq_State_Reset: begin
$sformat(d_State,"X");
end
`Seq_State_Ready: begin
$sformat(d_State,"R %2X %3X %8B",s_Address,s_OReg,s_ORegWen);
end
`Seq_State_WaitZ: begin
$sformat(d_State,"Z %2X %3X %8B",s_Address,s_OReg,s_ORegWen);
end
`Seq_State_WaitN: begin
$sformat(d_State,"N %2X %3X %8B",s_Address,s_OReg,s_ORegWen);
end
`Seq_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // Seq
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_2_V
`define SKY130_FD_SC_LS__DLRBP_2_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, a[N], fa[N], head[N], p, deep[N]; long long Chuan1[N], Chuan2[N], Ans; queue<int> q; struct wfh { int to, last; } d[N << 1]; inline void add(int a, int b) { d[++p] = (wfh){b, head[a]}, head[a] = p; } inline long long max(long long A, long long B) { return A > B ? A : B; } inline long long min(long long A, long long B) { return A < B ? A : B; } void dfs(int u, int fa) { for (int i = head[u], v; i; i = d[i].last) { v = d[i].to; if (v == fa) continue; dfs(v, u); Chuan1[u] = max(Chuan1[u], Chuan1[v]); Chuan2[u] = max(Chuan2[u], Chuan2[v]); } a[u] += Chuan2[u] - Chuan1[u]; if (a[u] >= 0) Chuan1[u] += a[u]; else Chuan2[u] -= a[u]; } int main() { scanf( %d , &n); for (int i = 1, u, v; i < n; i++) scanf( %d%d , &u, &v), add(u, v), add(v, u); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); dfs(1, -1); printf( %lld n , Chuan1[1] + Chuan2[1]); return 0; }
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module efifo_module
#(
parameter DATA_WIDTH = 16,
parameter DEPTH = 2
)(
// inputs:
clk,
rd,
rst_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ DATA_WIDTH - 1 : 0 ] rd_data;
input clk;
input rd;
input rst_n;
input wr;
input [ DATA_WIDTH - 1 : 0 ] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ DEPTH - 1 : 0 ] entries;
reg [ DATA_WIDTH - 1 : 0 ] entry_0;
reg [ DATA_WIDTH - 1 : 0 ] entry_1;
wire full;
reg rd_address;
reg [ DATA_WIDTH - 1 : 0 ] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == DEPTH;
assign almost_full = entries >= DEPTH - 1;
assign empty = entries == 0;
assign almost_empty = entries <= DEPTH - 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
|
// DM9000A.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module DM9000A (
input wire iCLK, // clk.clk
input wire iOSC_50, // avalon_slave_0_export.export
inout wire [15:0] ENET_DATA, // .export
output wire ENET_CMD, // .export
output wire ENET_RD_N, // .export
output wire ENET_WR_N, // .export
output wire ENET_CS_N, // .export
output wire ENET_RST_N, // .export
output wire ENET_CLK, // .export
input wire ENET_INT, // .export
input wire [15:0] iDATA, // avalon_slave_0.writedata
input wire iCMD, // .address
input wire iRD_N, // .read_n
input wire iWR_N, // .write_n
input wire iCS_N, // .chipselect_n
output wire [15:0] oDATA, // .readdata
output wire oINT, // avalon_slave_0_irq.irq
input wire iRST_N // reset_n.reset_n
);
DM9000A_IF dm9000a (
.iCLK (iCLK), // clk.clk
.iOSC_50 (iOSC_50), // avalon_slave_0_export.export
.ENET_DATA (ENET_DATA), // .export
.ENET_CMD (ENET_CMD), // .export
.ENET_RD_N (ENET_RD_N), // .export
.ENET_WR_N (ENET_WR_N), // .export
.ENET_CS_N (ENET_CS_N), // .export
.ENET_RST_N (ENET_RST_N), // .export
.ENET_CLK (ENET_CLK), // .export
.ENET_INT (ENET_INT), // .export
.iDATA (iDATA), // avalon_slave_0.writedata
.iCMD (iCMD), // .address
.iRD_N (iRD_N), // .read_n
.iWR_N (iWR_N), // .write_n
.iCS_N (iCS_N), // .chipselect_n
.oDATA (oDATA), // .readdata
.oINT (oINT), // avalon_slave_0_irq.irq
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file sdp_ram_10x14_11x7.v when simulating
// the core, sdp_ram_10x14_11x7. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module sdp_ram_10x14_11x7(
clka,
dina,
addra,
wea,
clkb,
addrb,
doutb);
input clka;
input [13 : 0] dina;
input [9 : 0] addra;
input [0 : 0] wea;
input clkb;
input [10 : 0] addrb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(14),
.C_READ_WIDTH_B(7),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(14),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.DOUTA(),
.DINB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of sdp_ram_10x14_11x7 is "black_box"
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:32 EST 2017
//
// Method conflict info:
// Method: outport_encoder
// Conflict-free: outport_encoder
//
//
// Ports:
// Name I/O size props
// outport_encoder O 4
// outport_encoder_vec I 5
//
// Combinational paths from inputs to outputs:
// outport_encoder_vec -> outport_encoder
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_outport_encoder(outport_encoder_vec,
outport_encoder);
// value method outport_encoder
input [4 : 0] outport_encoder_vec;
output [3 : 0] outport_encoder;
// signals for module outputs
wire [3 : 0] outport_encoder;
// value method outport_encoder
assign outport_encoder =
{ outport_encoder_vec[0] || outport_encoder_vec[1] ||
outport_encoder_vec[2] ||
outport_encoder_vec[3] ||
outport_encoder_vec[4],
outport_encoder_vec[0] ?
3'd0 :
(outport_encoder_vec[1] ?
3'd1 :
(outport_encoder_vec[2] ?
3'd2 :
(outport_encoder_vec[3] ? 3'd3 : 3'd4))) } ;
endmodule // module_outport_encoder
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_mask_write_bit_macro(bits,words) \
if (els_p == words && width_p == bits) \
begin: macro \
saed90_``bits``x``words``_1P_bit mem \
(.CE1 (clk_lo) \
,.WEB1 (~w_i) \
,.OEB1 (1'b0) \
,.CSB1 (~v_i) \
,.A1 (addr_i) \
,.I1 (data_i) \
,.O1 (data_o) \
,.WBM1 (w_mask_i) \
); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter enable_clock_gating_p=1'b0
)
(input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [width_p-1:0] w_mask_i
, output [width_p-1:0] data_o
);
wire clk_lo;
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( v_i )
,.bypass_i( ~enable_clock_gating_p )
,.gated_clock_o( clk_lo )
);
// TODO: ADD ANY NEW RAM CONFIGURATIONS HERE
`bsg_mem_1rw_sync_mask_write_bit_macro (736, 64) else
`bsg_mem_1rw_sync_mask_write_bit_macro ( 96, 64) else
// Hack fo 7 bit ram to use 8 bit ram
if (els_p == 64 && width_p == 7)
begin: macro
logic [7:0] data_lo;
saed90_8x64_1P_bit mem
(.CE1 (clk_lo)
,.WEB1 (~w_i)
,.OEB1 (1'b0)
,.CSB1 (~v_i)
,.A1 (addr_i)
,.I1 ({1'b0, data_i})
,.O1 (data_lo)
,.WBM1 ({1'b0, w_mask_i})
);
assign data_o = data_lo[6:0];
end
else
// no hardened version found
begin: notmacro
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.data_i
,.addr_i
,.v_i
,.w_mask_i
,.w_i
,.data_o
);
end // block: notmacro
// synopsys translate_off
always_ff @(posedge clk_lo)
if (v_i === 1)
assert ((reset_i === 'X) || (reset_i === 1'b1) || (addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", addr_i, els_p, reset_i, v_i, clk_lo);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
module master(
input wire [6:0] address,
input wire [7:0] register,
input wire refresh_clk,
input wire sys_clk,
input wire mode,
input wire en,
input wire reset,
input wire Start,
input wire Stop,
input wire repeat_start,
output reg [7:0] out,
output reg ack,
inout wire sda,
inout wire scl
);
reg [3:0] state;
reg [4:0] counter;
wire sda_in, scl_in;
reg sda_enable, sda_out, scl_enable, scl_out, clk_enable, sda_output, sda_en;
assign sda = ( sda_en ) ? (sda_output) ? 1'bz : 1'b0 : 1'bz;
assign sda_in = sda;
assign scl = ( scl_enable ) ? ( clk_enable ) ? (sys_clk) ? 1'bz : 1'b0 : scl_out : 1'bZ;
assign scl_in = scl;
always@(posedge refresh_clk)
begin
sda_en <= sda_enable;
sda_output <= sda_out;
end
always@(posedge sys_clk or negedge reset)
begin
if( ~reset )
begin
state <= 0;
sda_enable <= 0;
sda_out <= 0;
scl_enable <= 0;
clk_enable <= 0;
scl_out <= 0;
out <= 0;
counter <= 0;
ack <= 1'b0;
end
else
begin
case( state )
0:
begin
if((( Start || repeat_start ) ) && ( en ))
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 0;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
1:
begin
if(counter < 7)
begin
state <= 1;
sda_enable <= 1'b1;
sda_out <= address[6-counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 2;
sda_enable <= 1'b1;
sda_out <= mode;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
2:
begin
state <= 3;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
3:
begin
if( ~sda_in )
begin
if( mode )
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
else
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
4:
begin
if(counter < 7)
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
if( Stop )
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 1'b1;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
else
begin
state <= 8;
sda_enable <= 1'b1;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out[7-counter] <= sda_in;
counter <= 0;
ack <= 1'b1;
end
end
end
5:
begin
if(counter < 8)
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
else
begin
state <= 6;
sda_enable <= 1'b0;
sda_out <= 1'b0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b1;
end
end
6:
begin
if(( Stop ) || ( sda_in ))
begin
state <= 7;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 5;
sda_enable <= 1'b1;
sda_out <= register[7 - counter];
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= counter + 1;
ack <= 1'b0;
end
end
7:
begin
state <= 9;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
8:
begin
if( repeat_start )
begin
state <= 0;
sda_enable <= 1'b1;
sda_out <= 1;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
else
begin
state <= 4;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b1;
scl_out <= 1'b0;
out <= out;
counter <= 0;
ack <= 1'b0;
end
end
9:
begin
state <= 15;
sda_enable <= 1'b1;
sda_out <= 0;
scl_enable <= 1'b1;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
15:
begin
state <= 15;
sda_enable <= 1'b0;
sda_out <= 0;
scl_enable <= 1'b0;
clk_enable <= 1'b0;
scl_out <= 1'b1;
out <= out;
counter <= 0;
ack <= 1'b0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int mod; long long int power(long long int a, long long int b) { if (b == 0) return 1; if (b % 2 == 1) return (power(a, b - 1) * a) % mod; long long int q = power(a, b / 2); return (q * q) % mod; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; } long long int ans = 1; for (long long int i = 0; i < n; i++) { long long int cnt = 0; long long int prev = a[i]; for (long long int j = i - 1; j >= 0; j--) { if (a[j] <= prev) { prev = a[j]; cnt++; } else break; } prev = a[i]; for (long long int j = i + 1; j < n; j++) { if (a[j] <= prev) { prev = a[j]; cnt++; } else break; } cnt++; ans = max(ans, cnt); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100 + 10; char s[maxn]; int f(char ch) { if (ch == A ) return 1; if (ch == B ) return 2; if (ch == C ) return 4; return 0; } int main() { scanf( %s , s + 1); int l = strlen(s + 1); for (int i = 1; i <= l - 2; ++i) { int t = f(s[i]) | f(s[i + 1]) | f(s[i + 2]); if (t == 7) { cout << Yes << endl; return 0; } } cout << No ; return 0; }
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:44:40 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/gcd_zynq_snick_gcd_0_0_stub.v
// Design : gcd_zynq_snick_gcd_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module gcd_zynq_snick_gcd_0_0(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, i, j, sum = 0, x, y, b; cin >> n >> m; int a[n][m]; vector<pair<int, int>> v; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cin >> a[i][j]; sum += a[i][j]; if (a[i][j] == 0) v.push_back(make_pair(i, j)); } } for (i = v.size() - 1; i >= 0; i--) { x = v[i].first; y = v[i].second; a[x][y] = min(a[x + 1][y], a[x][y + 1]); a[x][y] -= 1; sum += a[x][y]; } for (i = 0; i < n - 1; i++) { for (j = 0; j < m - 1; j++) { if (a[i][j] >= a[i + 1][j] || a[i][j] >= a[i][j + 1]) { cout << -1; return 0; } } } for (i = 0; i < m - 1; i++) { if (a[n - 1][i] >= a[n - 1][i + 1]) { cout << -1; return 0; } } for (j = 0; j < n - 1; j++) { if (a[j][m - 1] >= a[j + 1][m - 1]) { cout << -1; return 0; } } cout << sum; }
|
#include <bits/stdc++.h> using namespace std; char s[200000], t[200000]; int equi(int a, int b, int c, int d) { bool x = 1; for (int i = 0; i <= b - a; i++) { x &= (s[i + a] == t[i + c]); } if (x) return 1; if (b <= a) return 0; int n = b - a + 1; if (n % 2 == 1) return 0; if (equi(a, a + n / 2 - 1, c, c + n / 2 - 1)) { if (equi(a + n / 2, b, c + n / 2, d)) return 1; } if (equi(a, a + n / 2 - 1, c + n / 2, d)) { if (equi(a + n / 2, b, c, c + n / 2 - 1)) return 1; } return 0; } int main() { int n = 0; scanf( %s , s); scanf( %s , t); while (s[n++] != 0 ) ; n--; if (equi(0, n - 1, 0, n - 1)) printf( YES ); else printf( NO ); }
|
#include <bits/stdc++.h> using namespace std; const long long int N = 1e5 + 5; map<long long int, long long int> m; long long int n, ans; void init() { m[-1] = -1; m[2e9] = 2e9; m[1] = n; ans = n; } void add(long long int l, long long int r) { m[l] = r; ans += r - l + 1; } void remove(long long int l, long long int r) { long long int rem = 0; auto it = m.lower_bound(l); it--; if (it->second >= l) { m[l] = it->second; it->second = l - 1; } it++; while (it->first <= r) { if (it->second > r) { rem += r + 1 - it->first; m[r + 1] = it->second; } else rem += it->second - it->first + 1; auto it2 = it; it++; m.erase(it2); } ans -= rem; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int q; cin >> n >> q; init(); while (q--) { long long int l, r, k; cin >> l >> r >> k; remove(l, r); if (k == 2) add(l, r); cout << ans << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND_SYMBOL_V
`define SKY130_FD_SC_HDLL__TAPVGND_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND_SYMBOL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: tx_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tx_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrusedw);
input aclr;
input [35:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [35:0] q;
output rdempty;
output [9:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [9:0] sub_wire1;
wire [35:0] sub_wire2;
wire rdempty = sub_wire0;
wire [9:0] wrusedw = sub_wire1[9:0];
wire [35:0] q = sub_wire2[35:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
dcfifo_component.lpm_numwords = 1024,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 36,
dcfifo_component.lpm_widthu = 10,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "36"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "36"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 36 0 INPUT NODEFVAL data[35..0]
// Retrieval info: USED_PORT: q 0 0 36 0 OUTPUT NODEFVAL q[35..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
// Retrieval info: CONNECT: @data 0 0 36 0 data 0 0 36 0
// Retrieval info: CONNECT: q 0 0 36 0 @q 0 0 36 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100000; int a, b, m, n, C[MAXN], I[MAXN]; queue<int> Q; vector<int> A, B, E[MAXN]; int main() { cin >> n >> m; while (m--) { cin >> a >> b; --a; --b; E[a].push_back(b); E[b].push_back(a); I[a] = I[b] = 1; } for (int i = 0; i < n; ++i) { C[i] = -1; } for (int i = 0; i < n; ++i) { if (C[i] > -1 || !I[i]) { continue; } C[i] = 1; Q.push(i); while (!Q.empty()) { a = Q.front(); Q.pop(); for (auto j : E[a]) { if (C[j] == -1) { C[j] = !C[a]; Q.push(j); } else if (C[j] == C[a]) { cout << -1 << endl; return 0; } } } } for (int i = 0; i < n; ++i) { if (C[i] == 0) { A.push_back(i); } else if (C[i] == 1) { B.push_back(i); } } cout << A.size() << endl; for (auto i : A) { cout << i + 1 << ; } cout << endl; cout << B.size() << endl; for (auto i : B) { cout << i + 1 << ; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int solve(int i, int a, int b, int c) { if (i == 0) return a + b + c; if (i == 1) return max((a + b) * c, a + b * c); if (i == 2) return max(a * (b + c), a * b + c); return a * b * c; } int main() { ios::sync_with_stdio(0); cin.tie(0); int a, b, c; cin >> a >> b >> c; int ans = 0; for (int i = 0; i < 4; ++i) { ans = max(ans, solve(i, a, b, c)); ans = max(ans, solve(i, c, b, a)); } cout << ans << endl; return 0; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macc_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macc_l(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_crit_px_l, data_ncrit_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_crit_px_l;
input [129:0] data_ncrit_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_crit_px_l[129:0] & data_ncrit_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; long long flag = 0, p = 0, ne = 0; if (a[0] != b[0]) { flag = 1; cout << NO << endl; continue; } if (a[0] == 1) p++; if (a[0] == -1) ne++; for (int i = 1; i < n; i++) { if ((a[i] > b[i] && ne == 0) || (a[i] < b[i] && p == 0)) { flag = 1; cout << NO << endl; break; } if (a[i] == 1) p++; if (a[i] == -1) ne++; } if (flag == 0) cout << YES << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 30); const int N = 100005; int n, k; int g[105][105]; int main() { int i, j, t, cas = 0; memset(g, 0, sizeof(g)); scanf( %d , &k); for (n = 3; n <= 100; n++) { if ((n) * (n - 1) * (n - 2) / 6 > k) break; } n--; k -= (n) * (n - 1) * (n - 2) / 6; for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (i == j) continue; g[i][j] = 1; } } while (k) { for (i = 2;; i++) { if ((i) * (i - 1) / 2 > k) break; } i--; n++; for (j = 1; j <= i; j++) g[j][n] = g[n][j] = 1; k -= (i) * (i - 1) / 2; } printf( %d n , n); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { printf( %d , g[i][j]); } puts( ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFSBP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfsbp (
CLK ,
D ,
Q ,
Q_N ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:00:08 11/01/2013
// Design Name: divider
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/divider_test.v
// Project Name: proyecto-final
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module divider_test;
// Inputs
reg in;
reg [3:0] N;
reg reset;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
divider uut (
.in(in),
.out(out),
.N(N),
.reset(reset)
);
initial begin
// Initialize Inputs
in = 0;
N = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
N = 2;
#1000;
reset = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 10; long long ans[MAXN]; int vis[MAXN], in[MAXN], worst[MAXN]; vector<int> adj[MAXN], idx[MAXN], path; vector<pair<int, int> > bad, qs[MAXN]; struct BIT { long long b[MAXN]; BIT() { fill(b, b + MAXN, 0); } void upd(int p, long long v) { for (; p < MAXN; p += (p & -p)) b[p] += v; } long long sum(int p) { long long res = 0; for (; p; p -= (p & -p)) res += b[p]; return res; } long long qry(int l, int r) { return sum(r) - sum(l - 1); } }; BIT wo, cn; void dfs(int s, int p = 0) { vis[s] = 1; in[s] = 1; path.push_back(s); for (auto v : adj[s]) { if (v == p) continue; if (!vis[v]) dfs(v, s); else if (in[v]) { int u, mi = MAXN, ma = -MAXN; do { u = path.back(); path.pop_back(); in[u] = 0; ma = max(ma, u); mi = min(mi, u); } while (u != v); worst[ma] = max(worst[ma], mi); } } } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int u = 1; u <= n; u++) if (!vis[u]) dfs(u); int cur = 0; for (int i = 1; i <= n; i++) { worst[i] = max(worst[i], cur); cur = worst[i]; wo.upd(i, worst[i]); idx[cur].push_back(i); } int q; cin >> q; for (int i = 0; i < q; i++) { int l, r; cin >> l >> r; qs[l].push_back({r, i}); } for (int l = 1; l <= n; l++) { for (auto i : idx[l - 1]) { wo.upd(i, -worst[i]); cn.upd(i, 1); } for (auto p : qs[l]) { int r = p.first; long long d = r - l + 1; long long tot = (long long)r * (r + 1) / 2 - (long long)l * (l - 1) / 2; tot -= wo.qry(l, r); tot -= cn.qry(l, r) * (l - 1); ans[p.second] = tot; } } for (int i = 0; i < q; i++) cout << ans[i] << n ; }
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module ParityTest;
wire w_parity_e1;
wire w_parity_e8;
wire w_parity_o1;
wire w_parity_o8;
wire w_error_e1;
wire w_error_e8;
wire w_error_o1;
wire w_error_o8;
reg [7:0] r_data;
integer i;
EvenParityGenerator parity_generator_e1(r_data[0], w_parity_e1);
EvenParityGenerator #(.width(8)) parity_generator_e8(r_data, w_parity_e8);
EvenParityChecker parity_checker_e1(r_data[0], w_parity_e1, w_error_e1);
EvenParityChecker #(.width(8)) parity_checker_e8(
r_data, w_parity_e8, w_error_e8);
OddParityGenerator parity_generator_o1(r_data[0], w_parity_o1);
OddParityGenerator #(.width(8)) parity_generator_o8(r_data, w_parity_o8);
OddParityChecker parity_checker_o1(r_data[0], w_parity_o1, w_error_o1);
OddParityChecker #(.width(8)) parity_checker_o8(
r_data, w_parity_o8, w_error_o8);
always @ (w_error_e8 or w_error_e1 or w_error_o8 or w_error_o1) begin
if (w_error_e8 == 1'b1) begin
$display("parity error on e8");
end
if (w_error_e1 == 1'b1) begin
$display("parity error on e1");
end
if (w_error_o8 == 1'b1) begin
$display("parity error on o8");
end
if (w_error_o1 == 1'b1) begin
$display("parity error on o1");
end
if (w_parity_e1 == w_parity_o1) begin
$display("1-bit even and odd parities are the same unexpectedly");
end
if (w_parity_e8 == w_parity_o8) begin
$display("8-bit even and odd parities are the same unexpectedly");
end
end
initial begin
//$dumpfile("Parity.vcd");
//$dumpvars(0, parity_generator_e8);
r_data <= 8'h00;
#1
r_data <= 8'h11;
#1
r_data <= 8'h08;
for (i = 0; i < 256; i = i + 1) begin
#1
r_data <= i;
end
#1
$finish;
end
endmodule // ParityTest
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_1_V
`define SKY130_FD_SC_HS__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_1_V
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; signed main() { long long n, sum = 0, temp; multiset<long long> a; cin >> n; for (long long i = 0; i < n; ++i) { cin >> temp; a.insert(temp); } while (a.size() > 1) { long long temp_sum = 0, sz = a.size(); for (long long j = 0; j < ((sz % 2 == 0) ? 2 : min(3ll, sz)); ++j) { temp_sum += *a.begin(); a.erase(a.begin()); } sum += temp_sum; a.insert(temp_sum); } cout << sum; return 0; }
|
module fifo(datain, rd, wr, rst, clk, full, empty,led_n,wei);
input [3:0] datain;
input rd, wr, rst, clk;
output [6:0] led_n;
output full, empty, wei;
reg [3:0] dataout;
reg full_in, empty_in,wei_in,div;
reg [3:0] mem [15:0];
reg [23:0]cnt;
reg [3:0] rp, wp;
reg [6:0] led_n;
assign full = full_in;
assign empty = empty_in;
assign wei=wei_in;
parameter
reg0=7'b0000001,
reg1=7'b1001111,
reg2=7'b0010010,
reg3=7'b0000110,
reg4=7'b1001100,
reg5=7'b0100100,
reg6=7'b0100000,
reg7=7'b0001101,
reg8=7'b0000000,
reg9=7'b0000100,
rega=7'b0001000,
regb=7'b1100000,
regc=7'b0110001,
regd=7'b1000010,
rege=7'b0110000,
regf=7'b0111000;
// memory read out
//assign dataout = mem[rp];
// memory write in
always@(posedge clk)
begin
if(cnt==24'b111111111111111111111111)
begin
div=~div;
cnt<=0;
end
else
begin
cnt<=cnt+1;
end
end
always@(posedge clk)
begin
wei_in<=1'b0;
end
always@(posedge div)
begin
if(~wr && ~full_in)
mem[wp]<=datain;
end
// memory write pointer increment
always@(posedge div)
begin
if(!rst)
wp<=0;
else
begin
if(~wr && ~full_in)
wp<= wp+1'b1;
end
end
// memory read pointer increment
always@(posedge div)
begin
if(!rst)
rp <= 0;
else
begin
if(~rd && ~empty_in)
rp <= rp + 1'b1;
end
end
// Full signal generate
always@(posedge div)
begin
if(!rst)
full_in <= 1'b0;
else
begin
if(rd && ~wr)
begin
if((wp==rp-1)||(rp==4'h0&&wp==4'hf))
full_in <= 1'b1;
end
else if(full_in && ~rd)
full_in <= 1'b0;
end
end
// Empty signal generate
always@(posedge div )
begin
if(!rst)
empty_in <= 1'b1;
else
begin
if(~rd&&wr)
begin
if(rp==wp-1 || (rp==4'hf&&wp==4'h0))
empty_in<=1'b1;
end
else if(empty_in && ~wr)
empty_in<=1'b0;
end
end
always@(posedge div)
begin
if(~rd && ~empty_in)
dataout<=mem[rp];
case(dataout)
4'h0: led_n<=reg0;
4'h1: led_n<=reg1;
4'h2: led_n<=reg2;
4'h3: led_n<=reg3;
4'h4: led_n<=reg4;
4'h5: led_n<=reg5;
4'h6: led_n<=reg6;
4'h7: led_n<=reg7;
4'h8: led_n<=reg8;
4'h9: led_n<=reg9;
4'ha: led_n<=rega;
4'hb: led_n<=regb;
4'hc: led_n<=regc;
4'hd: led_n<=regd;
4'he: led_n<=rege;
4'hf: led_n<=regf;
default:;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #define S size() #define EN end() #define BE begin() #define LEN length() #define endl n #define cnt count #define in insert #define er erase #define fi first #define se second #define ld double #define int long long #define gcd __gcd #define mp make_pair #define pb push_back #define lb lower_bound #define ub upper_bound #define bs binary_search #define np next_permutation #define si set<int> #define sc set<char> #define mll map<int,int> #define vi vector<int> #define vc vector<char> #define pll pair<int,int> #define vpi vector<pll> #define msi multiset<int> #define msc multiset<char> #define vvi vector<vector<int>> #define mod1 1000000007 #define mod2 998244353 #define inf (int)1e9 #define eness(x) __builtin_ctzll(x) #define nhigh(x) __builtin_popcountll(x) #define PI 3.1415926535897932384626433832 #define iter(s) for(auto it:s) #define forl(i,n) for(int i=0;i<n;i++) #define fore(i,n) for(int i=1;i<=n;i++) #define forn(i,n) for(int i=n-1;i>=0;i--) #define forls(i,l,r) for(int i=l;i<r;i++) #define forns(i,l,r) for(int i=r-1;i>=l;i--) #define all(v) v.BE,v.EN #define SORT(ar,n) sort(ar,ar+n) #define rall(v) v.rbegin(),v.rend() #define RSORT(ar,n) sort(ar,ar+n,greater<int>()) #define pat int n;cin>>n; #define wq int q;cin>>q;fore(_,q) #define nokay cout<<(ok? Yes n : No n ); #define tak(s) string s;cin>>s;int n=s.LEN; #define pat1 int n;cin>>n;int ar[n];forl(i,n) cin>>ar[i]; #define pat2 int n,k;cin>>n>>k;int ar[n];forl(i,n) cin>>ar[i]; #define fastio ios::sync_with_stdio(0);cin.tie(0);cout.tie(0); //********************************** vi mf,mi; int POW(int x,int y); int MI(int x,int mod); void pre_f(int x,int mod); void pre_i(int x,int mod); int C(int x,int y,int mod); int bpow(int x,int y,int mod); int POW(int x,int y){ return bpow(x,y,inf); } int MI(int x,int mod=mod1){ return bpow(x,mod-2,mod); } void pre_f(int x,int mod=mod1){ mf=vi(x+1,1); forls(i,2,x+1){ mf[i]=mf[i-1]*i; mf[i]%=mod; } return; } void pre_i(int x,int mod=mod1){ mi=vi(x+1); forl(i,x+1){ mi[i]=MI(mf[i],mod); } return; } int C(int x,int y,int mod=mod1){ if(x<y) return 0; int n1=mf[x]; int n2=mi[y]; int n3=mi[x-y]; int res=(n1*n2)%mod; res=(res*n3)%mod; return res; } int bpow(int x,int y,int mod=mod1){ x%=mod; int res=1; while(y>0){ if(y&1){ res=res*x%mod; } x=x*x%mod; y>>=1; } return res; } //********************************** const int N=200001; vector<vector<array<int,2>>> adj(N); int32_t main(){ #ifndef ONLINE_JUDGE freopen( ./input.txt , r , stdin); freopen( ./output.txt , w , stdout); #endif fastio; int n,m; cin>>n>>m; int dis[n+1][51]; forl(i,n+1){ forl(j,51){ dis[i][j]=inf; } } forl(i,m){ int u,v,w; cin>>u>>v>>w; adj[u].pb({v,w}); adj[v].pb({u,w}); } dis[1][0]=0; //i*51+j -> row dom. set<array<int,2>> pq; pq.in({0,51}); //int t=100; while(!pq.empty()/* && t--*/){ //auto itt=pq.BE set<array<int,2>>::iterator itt=pq.BE; array<int,2> x=*itt; pq.er(itt); int d=x[0],p=x[1]%51,u=x[1]/51; iter(adj[u]){ int v=it[0],w=it[1]; //cout<<u<< <<v<< <<p<< n ; if(p==0){ int dd=(d); if(dis[v][w]>dd){ set<array<int,2>>::iterator fin=pq.find({dis[v][w],v*51+w}); if(fin!=pq.end()){ pq.er(fin); } dis[v][w]=dd; pq.in({dd,v*51+w}); } } else{ int dd=(d+(p+w)*(p+w)); if(dis[v][0]>dd){ set<array<int,2>>::iterator fin=pq.find({dis[v][0],v*51}); if(fin!=pq.end()){ pq.er(fin); } dis[v][0]=dd; pq.in({dd,v*51}); } } } } fore(i,n){ if(dis[i][0]==inf){ cout<<-1<< ; } else{ cout<<dis[i][0]<< ; } } }
|
#include <bits/stdc++.h> using namespace std; char s[100010], s1[100010], s2[100010], s3[100010], s11[100010]; int main() { scanf( %s , &s); int len; len = strlen(s); int sum = 0, a = 0; for (int i = 0; i < len; i++) { sum += s[i] - 0 ; if (s[i] == 0 ) a = 1; } if (sum % 3 == 0) { int cnt = 0; for (int i = 0; i < len - 1; i++) { if (s[i] != 0 ) break; else cnt++; } int j = 0; for (int i = cnt; i < len; i++) s1[j++] = s[i]; cout << s1 << endl; } else { int num = sum % 3; int cnt1 = -1, cnt2 = -1, cnt3 = -1; int t1 = 0, t2 = 0; for (int i = len - 1; i >= 0; i--) { if ((s[i] - 0 ) % 3 == num) { cnt1 = i; break; } } if (cnt1 != -1) { int j = 0; for (int i = 0; i < len; i++) { if (i == cnt1) continue; else s1[j++] = s[i]; } int cnt = 0; for (int i = 0; i < j - 1; i++) { if (s1[i] != 0 ) break; else cnt++; } for (int i = cnt; i < j; i++) s2[t1++] = s1[i]; } for (int i = len - 1; i >= 1; i--) { if ((s[i] - 0 ) % 3 == 0) continue; for (int j = i - 1; j >= 0; j--) { int cnt = s[i] - 0 + s[j] - 0 ; if (cnt % 3 == num) { cnt2 = i; cnt3 = j; break; } } if (cnt2 != -1 && cnt3 != -1) break; } if (cnt2 != -1 && cnt3 != -1) { int j = 0; for (int i = 0; i < len; i++) { if (i == cnt2 || i == cnt3) continue; s11[j++] = s[i]; } int cnt = 0; for (int i = 0; i < j - 1; i++) { if (s11[i] != 0 ) break; else cnt++; } for (int i = cnt; i < j; i++) s3[t2++] = s11[i]; } if (!a && t1 == 0 && t2 == 0) cout << -1 << endl; else if (t1 == 0 && t2 == 0) cout << 0 << endl; else if (t1 >= t2) cout << s2 << endl; else cout << s3 << endl; } return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:40000000 ) using namespace std; const double EPS = 1e-10; const double PI = acos(-1.0); const int mod = 1000000007; const int MAXN = 200 * 200; int a[111]; int n; int main() { cin >> n; bool p = 1; for (int(i) = (0); (i) < (n); ++(i)) { int x; cin >> x; a[x]++; if (x == 25) continue; if (x == 50) { a[25]--; if (a[25] < 0) p = 0; } if (x == 100) { if (a[50] && a[25]) { a[50]--; a[25]--; } else { a[25] -= 3; if (a[25] < 0) p = 0; } } } if (p) cout << YES << endl; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100010, C = 1000000000; int n, num; int kd[N], t[N], x[N], fr[N], nxt[N], ans[N]; map<int, int> S; int lc[N * 40], rc[N * 40], s[N * 40]; void change(int &i, int l, int r, int k, int d) { if (i == 0) i = ++num; s[i] += d; if (l == r) return; int mid = (l + r) >> 1; if (k <= mid) change(lc[i], l, mid, k, d); if (k > mid) change(rc[i], mid + 1, r, k, d); } int query(int i, int l, int r, int rr) { if (i == 0) return 0; if (r <= rr) return s[i]; int mid = (l + r) >> 1, res = 0; res += query(lc[i], l, mid, rr); if (mid < rr) res += query(rc[i], mid + 1, r, rr); return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , &kd[i], &t[i], &x[i]); fr[i] = 1; if (S.count(x[i])) { nxt[S[x[i]]] = i; fr[i] = 0; } S[x[i]] = i; } for (int i = 1; i <= n; i++) if (fr[i]) { for (int j = 1; j <= num; j++) lc[j] = rc[j] = s[j] = 0; num = 1; int rt = 1; for (int j = i; j; j = nxt[j]) { if (kd[j] == 1) change(rt, 1, C, t[j], 1); if (kd[j] == 2) change(rt, 1, C, t[j], -1); if (kd[j] == 3) ans[j] = query(1, 1, C, t[j]); } } for (int i = 1; i <= n; i++) if (kd[i] == 3) printf( %d n , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; char r[100]; if (s.length() < 6) { cout << no << endl; return 0; } int val = 0; for (int i = s.length() - 1; i >= 0; i--) { if (val == 6) { if (s[i] == 1 ) { cout << yes << endl; return 0; } } else if (s[i] == 0 ) { val++; } } cout << no << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 22:16:58 05/10/2016
// Design Name:
// Module Name: receptor_teclado_ps2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module receptor_teclado_ps2
(
input wire clk, reset,
input wire ps2data, ps2clk, rx_en,
output reg rx_done_tick,
output wire [10:0] dout
);
// Declaración simbólica de estados
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// Declaración de señales
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2clk_reg;
wire f_ps2clk_next;
reg [3:0] n_reg, n_next;//Contador auxiliar para manejar el número de bits ensamblados
reg [10:0] assembled_data_reg, assembled_data_next; //Buffer para guardar el dato
wire fall_edge;
//======================================================
// Filtrado y detección del flanco negativo de ps2_clk
//======================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2clk_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2clk_reg <= f_ps2clk_next;
end
assign filter_next = {ps2clk, filter_reg[7:1]};
assign f_ps2clk_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2clk_reg;
assign fall_edge = f_ps2clk_reg & ~f_ps2clk_next;//Detección del flanco negativo del clk del teclado
//=================================================
// FSMD
//=================================================
// Estado FSMD y registros de datos
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
assembled_data_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
assembled_data_reg <= assembled_data_next;
end
// Lógica de siguiente estado de la FSMD
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
assembled_data_next = assembled_data_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift al bit entrante
assembled_data_next = {ps2data, assembled_data_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: //Ensamblar 8 bits de datos + 1 paridad + 1 parada
if (fall_edge)
begin
assembled_data_next = {ps2data, assembled_data_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1'b1;
end
load: // Ciclo de reloj extra para terminar el ensamblaje del dato del teclado
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// Salida
assign dout = assembled_data_reg[10:0]; // bits de datos (se incluyen bit de inicio, paridad y parada)
//Nota: Bits del código de la teclado [8:1]
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long res = 1; a = a % 1000000007; while (b > 0) { if (b & 1) { res = (res * a) % 1000000007; b--; } a = (a * a) % 1000000007; b >>= 1; } return res; } long long fermat_inv(long long y) { return power(y, 1000000007 - 2); } long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { int n, q; cin >> n >> q; set<int> s; for (int i = 0; i < n; i++) { int a; cin >> a; s.insert(a); } map<long long, int> m; for (auto it = s.begin(); it != s.end();) { int val = *it; val = -val; it++; if (it == s.end()) break; val += (*it); m[val]++; } auto it = m.end(); if (it == m.begin()) cout << 0 n ; else { auto it1 = s.begin(); auto it2 = s.end(); it2--; long long ans = (*it2) - (*it1); it--; ans -= it->first; cout << ans << n ; } while (q--) { int ty, x; cin >> ty >> x; if (ty == 0) { auto it = s.lower_bound(x); int ctr = 0; long long val1 = 0; if (it != s.begin()) { it--; long long val = x - (*it); val1 += val; ctr++; m[val]--; if (m[val] == 0) m.erase(val); } auto it1 = s.upper_bound(x); if (it1 != s.end()) { long long val = (*it1) - x; m[val]--; ctr++; val1 += val; if (m[val] == 0) m.erase(val); } if (ctr == 2) m[val1]++; s.erase(x); } else { int ctr = 0; auto it = s.lower_bound(x); long long val1 = 0; if (it != s.begin()) { it--; long long val = x - (*it); val1 += val; ctr++; m[val]++; } auto it1 = s.upper_bound(x); if (it1 != s.end()) { long long val = (*it1) - x; val1 += val; ctr++; m[val]++; } if (ctr == 2) m[val1]--; if (m[val1] == 0) m.erase(val1); s.insert(x); } auto it = m.end(); if (it == m.begin()) cout << 0 n ; else { auto it1 = s.begin(); auto it2 = s.end(); it2--; long long ans = (*it2) - (*it1); it--; ans -= it->first; cout << ans << n ; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& _p) { return os << ( << _p.first << , << _p.second << ) ; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& _V) { bool f = true; os << [ ; for (auto v : _V) { os << (f ? : , ) << v; f = false; } return os << ] ; } template <typename T> ostream& operator<<(ostream& os, const set<T>& _S) { bool f = true; os << ( ; for (auto s : _S) { os << (f ? : , ) << s; f = false; } return os << ) ; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& _M) { return os << set<pair<T, U>>(_M.begin(), _M.end()); } const signed long long INF = 1000000100; const long double EPS = 1e-9; template <typename T, typename F> T bin_search(T a, T b, F f) { while (a < b) { T c = a + (b - a) / 2; if (f(c)) { b = c; } else { a = c + 1; } } return a; } const int MAXN = 1000100; int A[MAXN]; int S1[MAXN]; int S2[MAXN]; int N; void read_data() { scanf( %d , &N); for (int(i) = (1); (i) <= (N); (i)++) scanf( %d , A + i); } void solve() { vector<pair<int, int>> results; for (int(i) = (1); (i) <= (N); (i)++) S1[i] = S1[i - 1] + (A[i] == 1); for (int(i) = (1); (i) <= (N); (i)++) S2[i] = S2[i - 1] + (A[i] == 2); for (int(i) = (N); (i) >= (1); (i)--) { int t = 0; int z1 = 0; int z2 = 0; bool fail = false; int last = -1; while (t < N) { int k1 = bin_search(t + 1, N + 1, [&](int x) { return x == N + 1 or S1[x] - S1[t] >= i; }); int k2 = bin_search(t + 1, N + 1, [&](int x) { return x == N + 1 or S2[x] - S2[t] >= i; }); if (k1 < k2) { if (S1[k1] - S1[t] != i) { fail = true; break; } ++z1; last = 1; } else if (k1 > k2) { if (S2[k2] - S2[t] != i) { fail = true; break; } ++z2; last = 2; } else fail = true; t = min(k1, k2); } if (z1 > z2 and last != 1) continue; if (z1 < z2 and last != 2) continue; if (fail) continue; if (z1 == z2) continue; results.emplace_back(max(z1, z2), i); } sort(results.begin(), results.end()); printf( %d n , int(results.size())); for (auto r : results) printf( %d %d n , r.first, r.second); } int main() { read_data(); solve(); }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1 << 20; int bio[MAX]; vector<int> V[MAX]; int a[MAX], b[MAX]; int deg[MAX]; void dfs(int x) { if (bio[x]++) return; for (auto it : V[x]) dfs(it); } int main() { int n, m; scanf( %d%d , &n, &m); int usebe = 0; for (int i = 0; i < m; i++) { scanf( %d%d , &a[i], &b[i]); a[i]--; b[i]--; V[a[i]].push_back(b[i]); V[b[i]].push_back(a[i]); if (a[i] == b[i]) usebe++; else { deg[a[i]]++; deg[b[i]]++; } } for (int i = 0; i < n; i++) { if (V[i].size()) { dfs(i); break; } } for (int i = 0; i < n; i++) if (!bio[i] && V[i].size()) { printf( 0 n ); return 0; } long long rje = 0; rje += (long long)usebe * (usebe - 1) / 2; rje += (long long)usebe * (m - usebe); for (int i = 0; i < n; i++) rje += (long long)deg[i] * (deg[i] - 1) / 2; printf( %lld n , rje); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_debug_if.v.rca $
//
// Revision: 1.1.1.1 Tue Jun 7 09:39:01 2011 copew1
// first stab at merging s0903a branch.
//
// Revision: 1.1 Fri Jun 3 12:44:14 2011 tractp1
// UART in test bench to send/receive ASCII bytes with FPGA UART and
// command processing task in firmware
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Palette file.
module Palette(
clk_a, wr_a, rd_a, addr_a, data_in_a, data_out_a, byte_en_a,
clk_b, wr_b, rd_b, addr_b, data_in_b, data_out_b);
parameter NUM_CHANNELS = 3;
localparam BITS_PER_BYTE = 8;
localparam DATA_WIDTH = NUM_CHANNELS * BITS_PER_BYTE;
localparam ADDR_WIDTH = 10;
input clk_a;
input wr_a;
input rd_a;
input [NUM_CHANNELS-1:0] byte_en_a;
input [ADDR_WIDTH-1:0] addr_a;
input [DATA_WIDTH-1:0] data_in_a;
output [DATA_WIDTH-1:0] data_out_a;
input clk_b;
input wr_b;
input rd_b;
input [ADDR_WIDTH-1:0] addr_b;
input [DATA_WIDTH-1:0] data_in_b;
output [DATA_WIDTH-1:0] data_out_b;
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : RAM
// Instantiate 1Kx8 RAMs in parallel.
palette_ram_1Kx8 ram(.clock_a(clk_a), .clock_b(clk_b),
.address_a(addr_a), .address_b(addr_b),
.wren_a(wr_a), .wren_b(wr_b),
.rden_a(rd_a), .rden_b(rd_b),
.data_a(data_in_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.data_b(data_in_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_a(data_out_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_b(data_out_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.byteena_a(byte_en_a[i]));
end
endgenerate
endmodule
|
`timescale 1 ns / 100 ps
`include "sm_cpu.vh"
`ifndef SIMULATION_CYCLES
`define SIMULATION_CYCLES 120
`endif
module sm_testbench;
// simulation options
parameter Tt = 20;
reg clk;
reg rst_n;
reg [ 4:0] regAddr;
wire [31:0] regData;
wire cpuClk;
// ***** DUT start ************************
sm_top sm_top
(
.clkIn ( clk ),
.rst_n ( rst_n ),
.clkDevide ( 4'b0 ),
.clkEnable ( 1'b1 ),
.clk ( cpuClk ),
.regAddr ( regAddr ),
.regData ( regData )
);
defparam sm_top.sm_clk_divider.bypass = 1;
// ***** DUT end ************************
`ifdef ICARUS
//iverilog memory dump init workaround
initial $dumpvars;
genvar k;
for (k = 0; k < 32; k = k + 1) begin
initial $dumpvars(0, sm_top.sm_cpu.rf.rf[k]);
end
`endif
// simulation init
initial begin
clk = 0;
forever clk = #(Tt/2) ~clk;
end
initial begin
rst_n = 0;
repeat (4) @(posedge clk);
rst_n = 1;
end
//register file reset
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
sm_top.sm_cpu.rf.rf[i] = 0;
end
task disasmInstr
(
input [31:0] instr
);
reg [ 5:0] cmdOper;
reg [ 5:0] cmdFunk;
reg [ 4:0] cmdRs;
reg [ 4:0] cmdRt;
reg [ 4:0] cmdRd;
reg [ 4:0] cmdSa;
reg [15:0] cmdImm;
reg signed [15:0] cmdImmS;
begin
cmdOper = instr[31:26];
cmdFunk = instr[ 5:0 ];
cmdRs = instr[25:21];
cmdRt = instr[20:16];
cmdRd = instr[15:11];
cmdSa = instr[10:6 ];
cmdImm = instr[15:0 ];
cmdImmS = instr[15:0 ];
$write(" ");
casez( {cmdOper,cmdFunk} )
default : if (instr == 32'b0)
$write ("nop");
else
$write ("new/unknown");
{ `C_SPEC, `F_ADDU } : $write ("addu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_OR } : $write ("or $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SRL } : $write ("srl $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SLTU } : $write ("sltu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_SPEC, `F_SUBU } : $write ("subu $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
{ `C_ADDIU, `F_ANY } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
{ `C_LUI, `F_ANY } : $write ("lui $%1d, %1d", cmdRt, cmdImm);
{ `C_BEQ, `F_ANY } : $write ("beq $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
{ `C_BNE, `F_ANY } : $write ("bne $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
endcase
end
endtask
//simulation debug output
integer cycle; initial cycle = 0;
initial regAddr = 0; // get PC
always @ (posedge clk)
begin
$write ("%5d pc = %2d pcaddr = %h instr = %h v0 = %1d",
cycle, regData, (regData << 2), sm_top.sm_cpu.instr, sm_top.sm_cpu.rf.rf[2]);
disasmInstr(sm_top.sm_cpu.instr);
$write("\n");
cycle = cycle + 1;
if (cycle > `SIMULATION_CYCLES)
begin
$display ("Timeout");
$stop;
end
end
endmodule
|
`timescale 1 ns / 1 ps
module axi_axis_writer #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Master side
output wire [AXI_DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg int_awready_reg, int_awready_next;
reg [AXI_DATA_WIDTH-1:0] int_wdata_reg, int_wdata_next;
reg int_wready_reg, int_wready_next;
reg int_bvalid_reg, int_bvalid_next;
wire int_awdone_wire, int_wdone_wire, int_bdone_wire;
wire [AXI_DATA_WIDTH-1:0] int_wdata_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awready_reg <= 1'b1;
int_wdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
int_wready_reg <= 1'b1;
int_bvalid_reg <= 1'b0;
end
else
begin
int_awready_reg <= int_awready_next;
int_wdata_reg <= int_wdata_next;
int_wready_reg <= int_wready_next;
int_bvalid_reg <= int_bvalid_next;
end
end
assign int_awdone_wire = ~int_awready_reg | s_axi_awvalid;
assign int_wdone_wire = ~int_wready_reg | s_axi_wvalid;
assign int_bdone_wire = ~int_bvalid_reg | s_axi_bready;
assign int_wdata_wire = int_wready_reg ? s_axi_wdata : int_wdata_reg;
always @*
begin
int_awready_next = ~int_awdone_wire | (int_wdone_wire & int_bdone_wire);
int_wdata_next = int_wdata_reg;
int_wready_next = ~int_wdone_wire | (int_awdone_wire & int_bdone_wire);
int_bvalid_next = ~int_bdone_wire | (int_awdone_wire & int_wdone_wire);
if(int_wready_reg)
begin
int_wdata_next = s_axi_wdata;
end
end
assign s_axi_awready = int_awready_reg;
assign s_axi_wready = int_wready_reg;
assign s_axi_bresp = 2'd0;
assign s_axi_bvalid = int_bvalid_reg;
assign s_axi_arready = 1'b0;
assign s_axi_rdata = {(AXI_DATA_WIDTH){1'b0}};
assign s_axi_rresp = 2'd0;
assign s_axi_rvalid = 1'b0;
assign m_axis_tdata = int_wdata_wire;
assign m_axis_tvalid = int_awdone_wire & int_wdone_wire & int_bdone_wire;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct P { int x, y; }; P me; P other; bool white; int N, M; P operator+(P a, P b) { return {a.x + b.x, a.y + b.y}; } P operator-(P a, P b) { return {a.x - b.x, a.y - b.y}; } bool operator==(P a, P b) { return a.x == b.x && a.y == b.y; } bool isItAStep(P a, P b) { a = a - b; int dx = abs(a.x); int dy = abs(a.y); return (dx == 1 && dy == 2) || (dx == 2 && dy == 1); } P winWhite, winBlack; void step(P newP) { if (white && isItAStep(winWhite, me)) { cout << winWhite.x << << winWhite.y << endl << flush; exit(0); } if (!white && isItAStep(winBlack, me)) { cout << winBlack.x << << winBlack.y << endl << flush; exit(0); } if (isItAStep(other, me)) { cout << other.x << << other.y << endl << flush; exit(0); } me = newP; cout << me.x << << me.y << endl << flush; if (white && me.x == N / 2 && me.y == M / 2) exit(0); if (!white && me.x == N / 2 + 1 && me.y == M / 2) exit(0); } void getStep() { cin >> other.x >> other.y; if (other == me) exit(1); if (other.x == -1) exit(0); } const vector<P> ize = { {+1, +2}, {-1, +2}, {+1, -2}, {-1, -2}, {+2, +1}, {-2, +1}, {+2, -1}, {-2, -1}, }; vector<P> dfs(P from, P to, int K) { if (from == to) return vector<P>(1, to); if (K == 0) return vector<P>(); vector<P> best; for (const P& x : ize) { P to2 = to + x; if (to2.x < 1 || to2.y < 1) continue; if (to2.x > N || to2.y > M) continue; vector<P> c = dfs(from, to2, K - 1); if (best.size() == 0 || (!c.empty() && c.size() < best.size())) best = c; } if (best.empty()) return best; best.push_back(to); return best; } vector<P> closestDistance_(P from, P to) { int dx = abs(to.x - from.x); int dy = abs(to.y - from.y); int ix = (to.x > from.x ? 1 : -1); int iy = (to.y > from.y ? 1 : -1); vector<P> S; while (dx > 5 || dy > 5) { int wx = 2, wy = 1; if (dx < dy) { wx = 1; wy = 2; } ix = (to.x > from.x ? 1 : -1); iy = (to.y > from.y ? 1 : -1); from.x += wx * ix; from.y += wy * iy; S.push_back(from); dx = abs(to.x - from.x); dy = abs(to.y - from.y); } vector<P> ize = dfs(from, to, 6); assert(!ize.empty()); auto it = ize.begin(), end = ize.end(); it++; while (it != end) { S.push_back(*it); it++; } return S; } void check(vector<P>& S, P from, P to) { if (S.empty()) return; P last = from; assert(to == S.back()); for (const P& p : S) { assert(isItAStep(last, p)); last = p; } } int main() { int xw, yw, xb, yb; cin >> N >> M; cin >> xw >> yw >> xb >> yb; winWhite = {N / 2, M / 2}; winBlack = {N / 2 + 1, M / 2}; P whitee = {xw, yw}; P blackk = {xb, yb}; vector<P> cdww = closestDistance_(whitee, winWhite); vector<P> cdbw = closestDistance_(blackk, winWhite); vector<P> cdwb = closestDistance_(whitee, winBlack); vector<P> cdbb = closestDistance_(blackk, winBlack); vector<P> cd; white = true; bool white_kerget = ((xw ^ xb ^ yw ^ yb) & 1) == 1; cerr << W->w: << cdww.size() << endl; cerr << W->b: << cdwb.size() << endl; cerr << B->w: << cdbw.size() << endl; cerr << B->b: << cdbb.size() << endl; cerr << (white_kerget ? White kerget : Black kerget ) << endl; if (white_kerget) { cerr << white kerget << endl; if (cdwb.size() <= cdbb.size() + 1) { cerr << white bevarja << endl; white = true; cd = move(cdwb); } else if (cdww.size() <= cdbb.size()) { cerr << white megelozi << endl; white = true; cd = move(cdww); } else { white = false; cd = move(cdbb); } } else { cerr << black kerget << endl; if (cdbw.size() <= cdww.size()) { cerr << black bevarja << endl; white = false; cd = move(cdbw); } else if (cdbb.size() < cdww.size()) { cerr << black megelozi << endl; white = false; cd = move(cdbb); } else { white = true; cd = move(cdww); } } cdww.clear(); cdwb.clear(); cdbw.clear(); cdbb.clear(); if (white) { me = whitee; other = blackk; cout << WHITE << endl; } else { me = blackk; other = whitee; cout << BLACK << endl; getStep(); } if (!white) { cd.push_back(winWhite + P{2, 1}); cd.push_back(winWhite + P{0, 2}); cd.push_back(winWhite + P{1, 0}); } else if (white) { cd.push_back(winBlack - P{2, 1}); cd.push_back(winBlack - P{0, 2}); cd.push_back(winBlack - P{1, 0}); } int i = 0; while (i < cd.size()) { step(cd[i]); getStep(); i++; } return 0; }
|
`timescale 1 ns / 1 ps
module led_controller_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire[7:0] LEDs_out,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
led_controller_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) led_controller_v1_0_S00_AXI_inst (
.LEDs_out(LEDs_out),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
//assign LEDs_out[7:0] = LEDs_out[7:0];
// User logic ends
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: 6551tx.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ()
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
//
////////////////////////////////////////////////////////////////////////////////
module uart51_tx(
BAUD_CLK,
RESET_N,
TX_DATA,
TX_START,
TX_DONE,
TX_STOP,
TX_WORD,
TX_PAR_DIS,
TX_PARITY,
CTS,
TX_BUFFER
);
input BAUD_CLK;
input RESET_N;
output TX_DATA;
reg TX_DATA;
input TX_START;
output TX_DONE;
reg TX_DONE;
input TX_STOP;
input [1:0] TX_WORD;
input TX_PAR_DIS;
input [1:0] TX_PARITY;
input CTS;
input [7:0] TX_BUFFER;
reg [6:0] STATE;
reg [2:0] BIT;
wire PARITY;
reg TX_START0;
reg TX_START1;
assign PARITY = (~TX_PARITY[1]
& ((TX_BUFFER[0] ^ TX_BUFFER[1])
^ (TX_BUFFER[2] ^ TX_BUFFER[3]))
^ (TX_BUFFER[4]
^ (TX_BUFFER[5] & (TX_WORD != 2'b00)))
^ ((TX_BUFFER[6] & (TX_WORD[1] == 1'b1))
^ (TX_BUFFER[7] & (TX_WORD == 2'b11)))) // clear bit #8 if only 7 bits
^ ~TX_PARITY[0];
always @ (negedge BAUD_CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
STATE <= 7'b0000000;
TX_DATA <= 1'b1;
TX_DONE <= 1'b1;
BIT <= 3'b000;
TX_START0 <= 1'b0;
TX_START1 <= 1'b0;
end
else
begin
TX_START0 <= TX_START;
TX_START1 <= TX_START0;
case (STATE)
7'b0000000:
begin
BIT <= 3'b000;
TX_DATA <= 1'b1;
if(TX_START1 == 1'b1)
begin
TX_DONE <= 1'b0;
STATE <= 7'b0000001;
end
end
7'b0000001: // Start bit
begin
TX_DATA <= 1'b0;
STATE <= 7'b0000010;
end
7'b0010001:
begin
TX_DATA <= TX_BUFFER[BIT];
STATE <= 7'b0010010;
end
7'b0100000:
begin
BIT <= BIT + 1'b1;
if((TX_WORD == 2'b00) && (BIT != 3'b111))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b01) && (BIT != 3'b110))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b10) && (BIT != 3'b101))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b11) && (BIT != 3'b100))
begin
STATE <= 7'b0010001;
end
else
begin
if(!TX_PAR_DIS)
begin
STATE <= 7'b0100001; // do parity
end
else
begin
STATE <= 7'b0110001; // do stop
end
end
end
end
end
end
// Start parity bit
7'b0100001:
begin
TX_DATA <= PARITY;
STATE <= 7'b0100010;
end
// start stop
7'b0110001:
begin
TX_DONE <= 1'b1;
TX_DATA <= 1'b1;
STATE <= 7'b0110010;
end
// end of first stop bit-1
7'b0111111:
begin
if(!TX_STOP)
STATE <= 7'b1001111; // go check for CTS
else
STATE <= 7'b1000000;
end
7'b1001111:
begin
if(!CTS) // this is not correct for a 6551
begin
STATE <= 7'b0000000;
end
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct tc { int cnt, count; long long p[5001]; } q[5001]; struct sc { int id; long long num; } anss[200010], s[200010]; void merge(int l, int mid, int r) { int i = l, j = mid + 1; int cc = l; while (i <= mid && j <= r) { if (anss[i].num <= anss[j].num) { s[cc].id = anss[i].id; s[cc++].num = anss[i++].num; } else { s[cc].id = anss[j].id; s[cc++].num = anss[j++].num; } } while (i <= mid) { s[cc].id = anss[i].id; s[cc++].num = anss[i++].num; } while (j <= r) { s[cc].id = anss[j].id; s[cc++].num = anss[j++].num; } for (i = l; i < cc; i++) { anss[i].id = s[i].id; anss[i].num = s[i].num; } return; } void mergesort(int x, int y) { if (x < y) { int mid = (x + y) / 2; mergesort(x, mid); mergesort(mid + 1, y); merge(x, mid, y); } return; } int main() { int i, j; long long n, a, x, y, m; int ans = -1, k, sum, l = 0; cin >> n; for (i = 0; i < n; i++) { scanf( %d %I64d %I64d %I64d %I64d , &k, &a, &x, &y, &m); sum = 0; l += k; q[i].cnt = 1; q[i].count = k; q[i].p[1] = a; for (j = 2; j <= k; j++) { q[i].p[j] = (x * q[i].p[j - 1] + y) % m; if (q[i].p[j] < q[i].p[j - 1]) sum++; } ans = max(ans, sum); } printf( %d n , ans); int st = 0, end = 0; if (l <= 2e5) { while (end < l) { for (i = 0; i < n; i++) { for (j = q[i].cnt; j <= q[i].count; j++) { if (j != q[i].cnt && q[i].p[j] < q[i].p[j - 1]) { q[i].cnt = j; break; } anss[end].id = i; anss[end++].num = q[i].p[j]; } if (j > q[i].count) q[i].cnt = j; } mergesort(st, end - 1); st = end; } for (i = 0; i < l; i++) printf( %I64d %d n , anss[i].num, anss[i].id + 1); } return 0; }
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter NC0 = (necessary_condition == `OVL_TRIGGER_ON_MOST_PIPE);
parameter NC1 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_PIPE);
parameter NC2 = (necessary_condition == `OVL_TRIGGER_ON_FIRST_NOPIPE);
// Guarded parameters for num_cks < 2 (which is bad usage - see warning in top-level file)
parameter NUM_CKS_1 = (num_cks > 0) ? (num_cks - 1) : 0;
parameter NUM_CKS_2 = (num_cks > 1) ? (num_cks - 2) : 0;
parameter LSB_1 = (num_cks > 1) ? 1 : 0;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [NUM_CKS_1:0] seq_queue; // REVISIT: bit [0] is redundant (Mantis #1812)
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
seq_queue <= {num_cks{1'b0}};
end
else begin
seq_queue[NUM_CKS_2:0] <= seq_queue[NUM_CKS_1:1] & event_sequence[NUM_CKS_2:0];
seq_queue[NUM_CKS_1] <= NC2 ? event_sequence[NUM_CKS_1] && (~(|seq_queue[NUM_CKS_1:1]))
: event_sequence[NUM_CKS_1];
end
end
`endif // OVL_SHARED_CODE
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1, fire_2state_2;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"First event occured but it is not followed by the rest of the events in sequence");
end
if (fire_2state_2) begin
ovl_error_t(`OVL_FIRE_2STATE,"First num_cks-1 events occured but they are not followed by the last event in sequence");
end
end
end
assign fire_2state_1 = ((NC1 || NC2) && (&((seq_queue[NUM_CKS_1:LSB_1] & event_sequence[NUM_CKS_2:0]) | ~(seq_queue[NUM_CKS_1:LSB_1])) == 1'b0));
assign fire_2state_2 = ( NC0 && ((!seq_queue[1] || ((seq_queue[1] && event_sequence[0]))) == 1'b0));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3, fire_xcheck_4, fire_xcheck_5, fire_xcheck_6;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First event in the sequence contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Subsequent events in the sequence contain X or Z");
end
if (fire_xcheck_4) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
if (fire_xcheck_5) begin
ovl_error_t(`OVL_FIRE_XCHECK,"Last event in the sequence contains X or Z");
end
if (fire_xcheck_6) begin
ovl_error_t(`OVL_FIRE_XCHECK,"First num_cks-1 events in the sequence contain X or Z");
end
end
end
wire valid_first_event = ~( event_sequence[NUM_CKS_1] ^
event_sequence[NUM_CKS_1] );
wire valid_sequence = (~((^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}})) ^
(^(seq_queue[NUM_CKS_1:LSB_1] &
event_sequence[NUM_CKS_2:0] &
{{(NUM_CKS_2){1'b1}},{~(|NC0)}}))));
wire valid_last_event = ~((seq_queue[1] && event_sequence[0]) ^
(seq_queue[1] && event_sequence[0]));
always @ (valid_first_event or seq_queue) begin
if (valid_first_event) begin
fire_xcheck_1 = 1'b0;
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_1 = (NC0 || NC1);
fire_xcheck_2 = (NC2 && ~(|seq_queue[NUM_CKS_1:1]));
end
end
always @ (valid_sequence) begin
if (valid_sequence) begin
fire_xcheck_3 = 1'b0;
fire_xcheck_4 = 1'b0;
end
else begin
fire_xcheck_3 = (NC1 || NC2);
fire_xcheck_4 = (NC0);
end
end
always @ (valid_last_event or seq_queue) begin
if (valid_last_event) begin
fire_xcheck_5 = 1'b0;
fire_xcheck_6 = 1'b0;
end
else begin
fire_xcheck_5 = (NC0 && seq_queue[1]);
fire_xcheck_6 = (NC0 && ~seq_queue[1]);
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("sequence_trigger covered"); // basic
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (NC1 || NC2) && event_sequence[NUM_CKS_1]);
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && NC0 && (&seq_queue[1])); // REVISIT: Reduction-AND is redundant
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; unsigned long long int MOD = 1000000007; unsigned long long int B = 13331; bool cmp(const int &a, const int &b) { return a < b; } int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int lcm(int a, int b) { return a * (b / gcd(a, b)); } double func(double mod, double x) { int n = (int)(x / (2.0 * mod)); x -= n * 2.0 * mod; while (x < 0.0) x += 2.0 * mod; while (x > 2.0 * mod) x -= 2.0 * mod; if (x > mod) x = 2.0 * mod - x; return x; } int main(void) { int i; double a, b, m, vx, vy, vz; cin >> a >> b >> m >> vx >> vy >> vz; double x = func(a, a / 2.0 + vx * (m / (-vy))); double z = func(b, vz * (m / (-vy))); printf( %.9f %.9f n , x, z); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct info { long long int val, in; }; long long int arr[100010]; info tree[100010 * 4], temp; void init(long long int node, long long int b, long long int e) { if (b == e) { tree[node].val = arr[b]; tree[node].in = b; return; } long long int Left = node * 2; long long int Right = node * 2 + 1; long long int mid = (b + e) / 2; init(Left, b, mid); init(Right, mid + 1, e); if (tree[Left].val >= tree[Right].val) { tree[node].val = tree[Right].val; tree[node].in = tree[Right].in; } else { tree[node].val = tree[Left].val; tree[node].in = tree[Left].in; } } info query(long long int node, long long int b, long long int e, long long int i, long long int j) { if (i > e || j < b) { temp.in = temp.val = 30; return temp; } if (b >= i && e <= j) return tree[node]; long long int Left = node * 2; long long int Right = node * 2 + 1; long long int mid = (b + e) / 2; info p1 = query(Left, b, mid, i, j); info p2 = query(Right, mid + 1, e, i, j); if (p1.val >= p2.val) return p2; else return p1; } int main() { long long int i, j, len, mn = 30, m, last = 1, in; long long int used = -1; string s; vector<char> v, ans; char mxx = a - 1; cin >> m >> s; len = s.length(); for (i = 0; i < s.length(); i++) { arr[i + 1] = s[i] - a + 1; } init(1, 1, len); for (i = 1; i <= len - m + 1; i++) { info ret = query(1, 1, len, i, i + m - 1); if (used == -1) { used = ret.in; i = ret.in; last = ret.val; v.push_back(last - 1 + a ); mxx = max(mxx, (char)(last - 1 + a )); } else { if (ret.val == last && used == ret.in) { } else { used = ret.in; i = ret.in; last = ret.val; v.push_back(last - 1 + a ); mxx = max(mxx, (char)(last - 1 + a )); } } } if (v.size() == 0) v.push_back(s[0]); sort(v.begin(), v.end()); long long int inx = v.size() - 1; long long int cnt = 0; for (i = 0; i < v.size(); i++) { if (v[i] == v[inx]) cnt++; } for (i = 0; i < s.length(); i++) { if (s[i] < v[inx]) ans.push_back(s[i]); } for (i = 1; i <= cnt; i++) { ans.push_back(v[inx]); } sort(ans.begin(), ans.end()); for (i = 0; i < ans.size(); i++) { cout << ans[i]; } cout << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[2 * (int)(1e5 + 51)], b[2 * (int)(1e5 + 51)]; bool visited[2 * (int)(1e5 + 51)]; vector<int> g[2 * (int)(1e5 + 51)]; void dfs(int x) { visited[x] = 1; for (auto v : g[x]) { if (!visited[v]) dfs(v); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; a[i] = {x, i}; } for (int i = 1; i <= n; i++) { int x; cin >> x; b[i] = {x, i}; } sort(a + 1, a + 1 + n); reverse(a + 1, a + 1 + n); sort(b + 1, b + 1 + n); reverse(b + 1, b + 1 + n); for (int i = 1; i < n; i++) g[a[i + 1].second].push_back({a[i].second}); for (int i = 1; i < n; i++) if (((int)g[b[i + 1].second].size() && g[b[i + 1].second][0] != b[i].second) || !(int)g[b[i + 1].second].size()) g[b[i + 1].second].push_back(b[i].second); dfs(b[1].second); dfs(a[1].second); string ans = ; for (int i = 1; i <= n; i++) { if (visited[i]) ans += 1 ; else ans += 0 ; visited[i] = 0; g[i].clear(); } cout << ans << n ; } }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const double PI = acos(-1.0); const double E = exp(1.0); const int M = 200010; long long a[M]; long long ans[M][2]; int main() { int n, k, x; cin >> n >> k >> x; long long temp = 1; while (k--) temp *= x; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); ans[i][0] = (ans[i - 1][0] | a[i]); } long long mx = 0; for (int i = n; i > 0; --i) { mx = max(mx, ans[i + 1][1] | ans[i - 1][0] | (a[i] * temp)); ans[i][1] = ans[i + 1][1] | a[i]; } cout << mx << endl; return 0; }
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///====================== TEMPLATE STARTS HERE =====================/// #include <bits/stdc++.h> using namespace std; #define endl n #define pb push_back #define MP make_pair #define ff first #define ss second #define ABS(x) ((x)<0?-(x):(x)) #define FABS(x) ((x)+eps<0?-(x):(x)) #define LCM(x,y) (((x)/gcd((x),(y)))*(y)) #define POPCOUNT __builtin_popcountll #define Set(N,p) ((N)|((1LL)<<(p))) #define Reset(N,p) ((N)&(~((1LL)<<(p)))) #define Check(N,p) (!(((N)&((1LL)<<(p)))==(0))) #define fast_cin ios_base::sync_with_stdio(false);cin.tie(NULL) #define LL long long #define LLU long long unsigned int typedef pair < int, int > pii; typedef pair < LL, LL > pll; typedef vector<int> vi; typedef vector<LL> vl; typedef vector<pll> vll; #ifdef s_da_sailor #define line cout << n=================== n #define trace(...) __f( #__VA_ARGS__ , __VA_ARGS__ ) template <typename Arg1> void __f(const char* name, Arg1&& arg1){ cerr << name << = << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args){ const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << = << arg1 << , ; __f(comma + 1, args...); } #else #define line #define trace(...) #endif // s_da_sailor inline LL gcd ( LL a, LL b ) { a = ABS ( a ); b = ABS ( b ); while ( b ) { a = a % b; swap ( a, b ); } return a; } LL ext_gcd ( LL A, LL B, LL *X, LL *Y ){ LL x2, y2, x1, y1, x, y, r2, r1, q, r; x2 = 1; y2 = 0; x1 = 0; y1 = 1; for (r2 = A, r1 = B; r1 != 0; r2 = r1, r1 = r, x2 = x1, y2 = y1, x1 = x, y1 = y ) { q = r2 / r1; r = r2 % r1; x = x2 - (q * x1); y = y2 - (q * y1); } *X = x2; *Y = y2; return r2; } inline LL modInv ( LL a, LL m ) { LL x, y; ext_gcd( a, m, &x, &y ); x %= m; if ( x < 0 ) x += m; return x; } inline LL bigmod ( LL a, LL p, LL m ) { LL res = 1 % m, x = a % m; while ( p ) { if ( p & 1 ) res = ( res * x ) % m; x = ( x * x ) % m; p >>= 1; /// For bigmod2 multiply here using mulmod } return res; } //int knightDir[8][2] = { {-2,1},{-1,2},{1,2},{2,1},{2,-1},{-1,-2},{1,-2},{-2,-1} }; //int dir4[4][2] = {{-1,0},{0,1},{1,0},{0,-1}}; //int dir8[8][2] = {{-1,0},{0,1},{1,0},{0,-1},{-1,-1},{1,1},{1,-1},{-1,1}}; const LL inf = 2147383647; const LL mod = 1000000007; const double pi = 2 * acos ( 0.0 ); const double eps = 1e-11; //mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); /// For generating random numbers ///====================== TEMPLATE ENDS HERE =====================/// #define SIZE 100005 int ks; string S; int n, A[SIZE]; void solve() { cin >> S; n = S.size(); for(int i=0; i<n; i++) { A[i] = S[i] - a ; } int curr = 30; for(int i=0; i<n; i++) { if(i>=1 && A[i-1]==A[i]) { A[i] = curr; curr++; } else if(i>=2 && A[i-2]==A[i]) { A[i] = curr; curr++; } } cout << curr-30 << endl; } int main () { #ifdef s_da_sailor freopen ( input.txt , r , stdin ); //freopen ( output.txt , w , stdout ); #endif // s_da_sailor fast_cin; int tc; cin >> tc; for(ks=1; ks<=tc; ks++) { solve(); } return 0; }
|
//-----------------------------------------------------------------------------
//-- Divisor de frecuencia generico
//-- (c) BQ. August 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- Entrada: clk_in. Señal original
//-- Salida: clk_out. Señal de frecuencia 1/M de la original
module divider(input wire clk_in, output wire clk_out);
//-- Valor por defecto del divisor
//-- Lo ponemos a 1 Hz
parameter M = `F_2KHz;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con la funcion de verilog $clog2, que nos devuelve el
//-- numero de bits necesarios para representar el numero M
//-- Es un parametro local, que no se puede modificar al instanciar
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk_in)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar el bit mas significativo por clk_out
assign clk_out = divcounter[N-1];
endmodule
//-- Contador módulo M: Otra manera de implementarlo
/*
always @(posedge clk_in)
if (divcounter == M - 1)
divcounter <= 0;
else
divcounter <= divcounter + 1;
*/
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//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
`include "ethmac_defines.v"
`include "timescale.v"
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifdef ETH_FIFO_XILINX
`else
`ifdef ETH_ALTERA_ALTSYNCRAM
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
`endif
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <= 0;
else
if(clear)
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <= cnt - 1;
else
cnt <= cnt + 1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <= 0;
else
if(clear)
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <= 0;
else
if(clear)
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <= write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst
(
.data (data_in),
.wren (write & ~full),
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
.clock (clk),
.q (data_out)
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
always @ (posedge clk)
begin
if(write & clear)
fifo[0] <= data_in;
else
if(write & ~full)
fifo[write_pointer] <= data_in;
end
always @ (posedge clk)
begin
if(clear)
data_out <= fifo[0];
else
data_out <= fifo[read_pointer];
end
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_FIFO_XILINX
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, string> a[3005]; int h[3005]; vector<pair<string, int> > ans; int main() { int n, m; cin >> n; for (int i = 0; i < n; i++) cin >> a[i].second >> a[i].first; sort(a, a + n); for (int i = 0; i < n; i++) if (a[i].first > i) { cout << -1 n ; return 0; } m = h[0] = 0; for (int i = 1; i < n; i++) m = max(m, h[i] = h[i - 1] + (a[i].first > a[i - 1].first)); for (int i = 0; i < n; i++) ans.insert(ans.begin() + a[i].first, make_pair(a[i].second, h[i])); for (int i = 0; i < n; i++) cout << ans[i].first << << m - ans[i].second + 1 << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: FSM_Convert_Float_To_Fixed
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Convert_Float_To_Fixed(
//INPUTS
input wire CLK, //system clock
input wire RST_FF, //system reset
input wire Exp_out, // INDICA SI EL VALOR DEL EXPONENTE ES MAYOR QUE 127
input wire Begin_FSM_FF, //inicia la maquina de estados
input wire [7:0] Exp, //CONTIENE EL EXPONENTE DEL NUMERO EN PUNTO FLOTANTE
// OUTPUTS
output reg EN_REG1, //ENABLE PARA EL REGISTRO QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
output reg LOAD, //SELECCION PARA EL REGISTRO DE DESPLAZAMIENTOS
output reg MS_1, // SELECCION DEL MUX 1 (VALOR INICIAL DEL EXPONENTE , VALOR MODIFICADO DEL EXPONENTE)
output reg ACK_FF, // INDICA QUE LA CONVERSION FUE REALIZADA
output reg EN_MS_1,
output reg EN_REG2,
output reg RST
);
parameter [3:0] //se definen los estados que se utilizaran en la maquina
a = 4'b0000,
b = 4'b0001,
c = 4'b0010,
d = 4'b0011,
e = 4'b0100,
f = 4'b0101,
g = 4'b0110,
h = 4'b0111,
i = 4'b1000;
reg [3:0] state_reg, state_next ; //state registers declaration
always @(posedge CLK, posedge RST_FF)
if (RST_FF) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
always @*
begin
state_next = state_reg;
EN_REG1 = 1'b0;
EN_REG2 = 1'b0;
ACK_FF = 1'b0;
EN_MS_1=1'b0;
MS_1=1'b0;
LOAD = 1'b0;
RST = 1'b0;
case(state_reg)
a:
begin
if(Begin_FSM_FF)
begin
RST = 1'b1;
ACK_FF = 1'b0;
state_next = b;
end
else
state_next = a;
end
b:
begin
EN_REG1 = 1'b1;
state_next = c;
end
c:
begin
EN_MS_1 = 1'b1;
if(Exp == 8'b01111111)
state_next = i;
else
state_next = d;
end
d:
begin
EN_MS_1 = 1'b1;
MS_1 = 1'b1;
state_next = e;
end
e:
begin
state_next = f;
end
f:
begin
LOAD = 1'b1;
state_next = g;
end
g:
begin
EN_REG2 = 1'b1;
state_next = h;
end
h:
begin
ACK_FF = 1'b1;
if(RST_FF)
state_next = a;
else
state_next = h;
end
i:
begin
state_next = f;
end
default:
state_next=a;
endcase
end
endmodule
|
//---------------------------------------------------------------------//
// Name: eval_node.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Evaluates a single node in the Binomial Lattice.
//---------------------------------------------------------------------//
module eval_node(
clk,
nrst,
p_up,
p_down,
v_up,
v_down,
v_ex,
result
);
input clk;
input nrst;
input [63:0] p_up;
input [63:0] p_down;
input [63:0] v_up;
input [63:0] v_down;
input [63:0] v_ex;
output [63:0] result;
wire [63:0] upside_value;
wire [63:0] downside_value;
wire [63:0] v_hold;
wire [63:0] v_ex_delayed;
wire [63:0] v_hold_delayed;
wire exercise;
reg [63:0] result;
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
fp_mult_v1 upside_mult (
.clock ( clk ),
.dataa ( p_up ),
.datab ( v_up ),
.result ( upside_value )
);
fp_mult_v1 downside_mult (
.clock ( clk ),
.dataa ( p_down ),
.datab ( v_down ),
.result ( downside_value )
);
fp_add_v1 fp_mult_vhold (
.clock ( clk ),
.dataa ( upside_value ),
.datab ( downside_value ),
.result ( v_hold )
);
// Exercise when v_ex > v_hold.
fp_compare_v1 fp_compare_v1_inst (
.clock ( clk ),
.dataa ( v_ex ),
.datab ( v_hold ),
.agb ( exercise )
);
// Delay v_hold, v_ex by 1 clock.
lpm_ff_v1 lpm_ff_v_ex (
.clock ( clk ),
.data ( v_ex ),
.q ( v_ex_delayed )
);
// Delay v_exercise by 1 clock.
lpm_ff_v1 lpm_ff_v_hold (
.clock ( clk ),
.data ( v_hold ),
.q ( v_hold_delayed )
);
// Assign output.
always@(posedge clk)
begin
if( exercise ) result <= v_ex_delayed[63:0];
else result <= v_hold_delayed[63:0];
end
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 5;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("if1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("if1_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 3);
`assert(result_type, `i32);
`assert(result_empty, 0);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e9 + 7; const int N = 0; int a[5], m; long long sum(int len, int x) { return 1LL * len * x - 1LL * (x + 1) * x / 2 + x; } long long cal(int x, int y, int bar, int len) { if (len < 0) return 0; int R = min(bar - y, len), L = min(len - (bar - x), R); long long ans = 0; if (L >= 0) ans += 1LL * (L + 1) * (bar - x + 1); else L = -1; ans += sum(len, R) - sum(len, L); return ans; } long long solve(int x, int y, int z, int len) { int tmp = max(max(y, z) + 1, x); len -= tmp - x; x = tmp; long long ans = 0; for (auto i = 0; i <= len; i++) { int cur = x + i, rem = min(2 * (cur - 1) - y - z, len - i); if (rem > cur - y - z) ans += cal(y, z, cur - 1, rem) - cal(y, z, cur - 1, (cur - y - z)); } return ans; } long long solve2(int x, int y, int z, int len) { int tmp = max(x, y); len -= 2 * tmp - x - y; x = tmp; if (x <= z) len -= 2 * (z + 1 - x), x = z + 1; long long ans = 0; if (len >= 0) for (auto i = 0; i <= len / 2; i++) { int rem = len - 2 * i; ans += min(x + i - 1 - z, rem) + 1; } return ans; } int main() { for (auto i = 0; i <= 2; i++) cin >> a[i]; cin >> m; long long ans = 0; for (auto i = 0; i <= 2; i++) ans += solve(a[i], a[(i + 1) % 3], a[(i + 2) % 3], m); for (auto i = 0; i <= 2; i++) ans += solve2(a[i], a[(i + 1) % 3], a[(i + 2) % 3], m); int tmp = *max_element(a, a + 3), v = 0; for (auto i = 0; i <= 2; i++) v += tmp - a[i]; if (v <= m) ans += (m - v) / 3 + 1; cout << ans; }
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#include <bits/stdc++.h> using namespace std; int dp[26][26]; int main(void) { int n, i, j, a, b, l, ans = 0; char s[20]; memset(dp, 0, sizeof dp); scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %s , s); l = strlen(s); a = s[0] - a ; b = s[l - 1] - a ; for (j = 0; j < 26; j++) { if (dp[j][a]) { dp[j][b] = max(dp[j][b], dp[j][a] + l); } } dp[a][b] = max(dp[a][b], l); } for (i = 0; i < 26; i++) { ans = max(ans, dp[i][i]); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 5e3 + 3; const int INF = 2000000000; inline long long ab(long long x) { return x < 0 ? -x : x; } long long a[MAXN]; int c_a[MAXN]; int l[MAXN], r[MAXN], x[MAXN], t[MAXN]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { a[i] = INF; } for (int q = 0; q < m; q++) { cin >> t[q] >> l[q] >> r[q] >> x[q]; --l[q], --r[q]; } for (int q = m - 1; q >= 0; q--) { if (t[q] == 1) { for (int i = l[q]; i <= r[q]; i++) { a[i] -= x[q]; } } else { bool found = false; for (int i = l[q]; i <= r[q]; i++) { if (a[i] >= x[q]) { a[i] = x[q]; found = true; } } if (!found) { cout << NO ; return 0; } } } for (int i = 0; i < n; i++) { if (a[i] < 0) { if (ab(a[i]) > INF / 2) a[i] = -INF / 2; } else { if (a[i] > INF / 2) a[i] = INF / 2; } } for (int i = 0; i < n; i++) { c_a[i] = a[i]; } for (int q = 0; q < m; q++) { if (t[q] == 1) { for (int i = l[q]; i <= r[q]; i++) { a[i] += x[q]; } } else { long long maxv = -INF; for (int i = l[q]; i <= r[q]; i++) { maxv = max(maxv, a[i]); } if (maxv != x[q]) { cout << NO ; return 0; } } } cout << YES n ; for (int i = 0; i < n; i++) { if (i > 0) cout << ; cout << c_a[i]; } return 0; }
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#include <bits/stdc++.h> int n, m, i, j, k, l, a, b, c; char s[200][200]; bool bo; void fail() { bo = false; } bool work(int x, int y, int o, int p, int a, int b, int c) { int i, j; if (x > o) { return true; } if ((a < 0) || (b < 0) || (c < 0)) return false; if (x == o) { j = 0; for (i = 1; i <= m; i += 2) { s[1][i] = s[1][i + 1] = a + j; j = (j ^ 1); } return true; } else if (y == p) { j = 0; for (i = 1; i <= n; i += 2) { s[i][1] = s[i + 1][1] = a + j; j = (j ^ 1); } return true; } else { bool bo[29]; for (i = 0; i < 26; i++) { bo[i] = false; } if (s[x - 1][y] != 0) { bo[s[x - 1][y] - a ] = true; } if (s[x - 1][y + 1] != 0) { bo[s[x - 1][y + 1] - a ] = true; } if (s[x][y - 1] != 0) { bo[s[x][y - 1] - a ] = true; } if (s[x + 1][y - 1] != 0) { bo[s[x + 1][y - 1] - a ] = true; } if (c >= 1) { char ch; for (i = 0; i < 26; i++) if (!bo[i]) { break; } ch = a + i; s[x][y] = s[x][y + 1] = s[x + 1][y] = s[x + 1][y + 1] = ch; c--; } else if (a >= 2) { char ch[2]; int k; k = 0; for (i = 0; i < 26; i++) if (!bo[i]) { ch[k] = a + i; k++; if (k == 2) { break; } } s[x][y] = s[x][y + 1] = ch[0]; s[x + 1][y] = s[x + 1][y + 1] = ch[1]; a -= 2; } else if (b >= 2) { char ch[2]; int k; k = 0; for (i = 0; i < 26; i++) if (!bo[i]) { ch[k] = a + i; k++; if (k == 2) { break; } } s[x][y] = s[x + 1][y] = ch[0]; s[x][y + 1] = s[x + 1][y + 1] = ch[1]; b -= 2; } else { return false; } y += 2; if (y > m) { x += 2; y = 1; if ((m & 1) == 1) { y = 2; } } } return work(x, y, o, p, a, b, c); } void rect(int x, int y, int o, int p, int a, int b, int c) { if (!work(x, y, o, p, a, b, c)) { fail(); } } int main() { bo = true; scanf( %d%d%d%d%d , &n, &m, &a, &b, &c); for (i = 0; i <= n; i++) for (j = 0; j <= m; j++) { s[i][j] = 0; } if ((((n * m) & 1) == 1) || (a * 2 + b * 2 + c * 4 < n * m)) { fail(); } else if ((n & 1) == 1) { rect(1, 1, 1, m, m / 2, 0, 0); if (n > 1) { rect(2, 1, n, m, a - m / 2, b, c); } else { if (a < m / 2) { fail(); } } } else if ((m & 1) == 1) { rect(1, 1, n, 1, 0, n / 2, 0); if (m > 1) { rect(1, 2, n, m, a, b - n / 2, c); } else { if (b < n / 2) { fail(); } } } else { rect(1, 1, n, m, a, b, c); } if (bo) { for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { printf( %c , s[i][j]); } printf( n ); } } else { printf( IMPOSSIBLE n ); } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int TC; cin >> TC; while (TC--) { int p, f, cnts, cntw, s, w; cin >> p >> f >> cnts >> cntw >> s >> w; if (s < w) { swap(s, w); swap(cnts, cntw); } int maxi = 0; for (int i = 0; i <= min(p / w, cntw); i++) { int pw = i; int ps = min((p - i * w) / s, cnts); int fw, fs; int cntW = cntw - i; int cntS = cnts - ps; fw = min(cntW, f / w); if (f / w > cntW) { fs = min(cntS, (f - cntW * w) / s); } else { fs = 0; } int total = ps + pw + fs + fw; maxi = max(maxi, total); } cout << maxi << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int n; int main() { ios::sync_with_stdio(false); cin.tie(0); int test; cin >> test; while (test--) { cin >> n; vector<int> a; int mini = -1; int ii; for (ii = 2; ii * ii < n; ii++) { if (n % ii != 0) continue; if (mini < 0) mini = ii; a.push_back(ii); a.push_back(n / ii); } if (ii * ii == n) a.push_back(ii); a.push_back(n); bool pk = true; for (int x : a) { if (x % mini != 0) { pk = false; break; } } if (pk) { for (int x : a) cout << x << ; cout << n ; cout << 0 << n ; continue; } if (a.size() == 3) { for (int x : a) cout << x << ; cout << n ; cout << 1 << n ; continue; } vector<int> primes; int m = n; int cnt = 2; while (cnt * cnt <= m) { if (m % cnt == 0) { primes.push_back(cnt); while (m % cnt == 0) m /= cnt; } cnt++; } if (m > 1) primes.push_back(m); map<int, bool> ma; for (int pi = 0; pi + 1 < primes.size(); pi++) { ma[primes[pi]] = true; ma[primes[pi] * primes[pi + 1]] = true; } ma[primes.back()] = true; ma[n] = true; vector<bool> was(a.size(), false); for (int i = 0; i < a.size(); i++) { if (ma[a[i]]) was[i] = true; } vector<int> ans; for (int pi = 0; pi + 1 < primes.size(); pi++) { ans.push_back(primes[pi]); for (int i = 0; i < a.size(); i++) { if (!was[i] && a[i] % primes[pi] == 0 && a[i] != primes[pi + 1] * primes[pi]) { was[i] = true; ans.push_back(a[i]); } } ans.push_back(primes[pi + 1] * primes[pi]); } ans.push_back(primes.back()); for (int i = 0; i < a.size(); i++) { if (!was[i] && a[i] % primes.back() == 0) { was[i] = true; ans.push_back(a[i]); } } ans.push_back(n); for (int x : ans) cout << x << ; cout << n ; cout << 0 << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; typedef struct { int freq; char l; } db; int comp(const void *a, const void *b) { db *x = (db *)a; db *y = (db *)b; return x->freq - y->freq; } int main() { db aa[30]; db e; string str; int let[30], sz, i, cnt, k, d, j; while (cin >> str) { cin >> d; memset(let, 0, sizeof(let)); sz = str.length(); for (i = 0; i < sz; i++) { let[str[i] - a ]++; } cnt = 0; k = 0; for (i = 0; i < 26; i++) { if (let[i]) { cnt++; aa[k].l = i + a ; aa[k].freq = let[i]; k++; } } qsort(aa, k, sizeof(db), comp); sz = str.size(); for (i = 0; i < k; i++) { if (d == 0) break; for (j = 0; j < str.size() && d > 0; j++) { if (str[j] == aa[i].l) { str.erase(j, 1); j--; let[aa[i].l - a ]--; d--; } } } cnt = 0; for (i = 0; i < 26; i++) { if (let[i]) cnt++; } cout << cnt << endl; cout << str << endl; } return 0; }
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//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( bool_expr) statement else ;
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5E always if ( bool_expr) statementelse ;");
else
$display("PASSED");
$finish;
end
always if( 1'b1 & 1'b1) begin
# 1;
value1 = value1 + 1;
end
else ;
endmodule
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#include <bits/stdc++.h> using namespace std; template <class _T> inline _T sqr(const _T& first) { return first * first; } template <class _T> inline string tostr(const _T& a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; const long double EPS = 5e-12; char TEMPORARY_CHAR; const int INF = 1e9; inline void input(int& a) { a = 0; while (((TEMPORARY_CHAR = getchar()) > 9 || TEMPORARY_CHAR < 0 ) && (TEMPORARY_CHAR != - )) { } char neg = 0; if (TEMPORARY_CHAR == - ) { neg = 1; TEMPORARY_CHAR = getchar(); } while (TEMPORARY_CHAR <= 9 && TEMPORARY_CHAR >= 0 ) { a = 10 * a + TEMPORARY_CHAR - 0 ; TEMPORARY_CHAR = getchar(); } if (neg) a = -a; } inline void out(int a) { if (!a) putchar( 0 ); if (a < 0) { putchar( - ); a = -a; } char s[10]; int i; for (i = 0; a; ++i) { s[i] = 0 + a % 10; a /= 10; } for (int j = (i)-1; j >= 0; j--) putchar(s[j]); } inline int nxt() { int(ret); input((ret)); ; return ret; } char can[8][8]; bool check(const vector<int>& a) { for (int i : a) for (int j : a) if (!can[i][j]) return false; return true; } int main() { long long n; cin >> n; long long tri = 1; while (n % tri == 0) tri *= 3; cout << (n + tri - 1) / tri << endl; return 0; }
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//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple round-robin arbiter for multiple Wishbone masters ////
/// ////
/// Olof Kindgren, ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 2)
(
input wb_clk_i,
input wb_rst_i,
// Wishbone Master Interface
input [num_masters*aw-1:0] wbm_adr_i,
input [num_masters*dw-1:0] wbm_dat_i,
input [num_masters*4-1:0] wbm_sel_i,
input [num_masters-1:0] wbm_we_i,
input [num_masters-1:0] wbm_cyc_i,
input [num_masters-1:0] wbm_stb_i,
input [num_masters*3-1:0] wbm_cti_i,
input [num_masters*2-1:0] wbm_bte_i,
output [num_masters*dw-1:0] wbm_dat_o,
output [num_masters-1:0] wbm_ack_o,
output [num_masters-1:0] wbm_err_o,
output [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [dw-1:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [dw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
`include "verilog_utils.vh"
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
localparam master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire active;
wire [$clog2(num_masters)-1:0] select;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select(select),
.active (active));
assign master_sel = ff1(grant, num_masters);
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel] & active;
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel] & active;
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
endmodule // wb_arbiter
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#include <bits/stdc++.h> using namespace std; int main() { int n, m, x = 0, y = 0; cin >> n >> m; x = max(m, n); for (int a = 0; a <= x; a++) { for (int b = 0; b <= x; b++) { if ((a * a) + b == n && (b * b) + a == m) { y++; } } } cout << y << endl; }
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#include <bits/stdc++.h> using namespace std; using namespace std; string best; void LongestPalindromicPrefix(string str) { string temp = str + ? ; reverse(str.begin(), str.end()); temp += str; int n = temp.length(); int lps[n]; fill(lps, lps + n, 0); for (int i = 1; i < n; i++) { int len = lps[i - 1]; while (len > 0 && temp[len] != temp[i]) { len = lps[len - 1]; } if (temp[i] == temp[len]) { len++; } lps[i] = len; } if (best.length() < lps[n - 1]) { best = temp.substr(0, lps[n - 1]); } } int solve() { int n, i, j; best.erase(); string s; cin >> s; n = s.length(); i = 0, j = n - 1; string temp; long long ans = 0; while (s[i] == s[j] && i <= j) { temp.push_back(s[i]); i++; j--; ans++; if (i != j) { ans++; } if (i >= j) { break; } } int k; string res; for (k = i; k <= j; k++) { res.push_back(s[k]); } if (res.length() == 0) { cout << s << n ; return 0; } cout << temp; LongestPalindromicPrefix(res); reverse(res.begin(), res.end()); LongestPalindromicPrefix(res); cout << best; reverse(temp.begin(), temp.end()); cout << temp << n ; return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
`include "xrs.vh"
module integration_tb();
reg [11:0] story_to;
reg fault_to;
reg clk_i, reset_i, inst_en_i;
reg [31:0] inst_i;
wire illegal_o;
wire [63:0] xrs_dec_rs1val, xrs_dec_rs2val;
wire [63:0] dec_ex_inpa, dec_ex_inpb;
wire dec_ex_invB, dec_ex_cflag, dec_ex_lsh_en, dec_ex_rsh_en;
wire dec_ex_ltu_en, dec_ex_lts_en, dec_ex_sum_en, dec_ex_and_en;
wire dec_ex_xor_en, dec_ex_we, dec_ex_nomem, dec_ex_mem;
wire [4:0] dec_ex_rd, dec_xrs_rs1, dec_xrs_rs2;
wire [63:0] dec_ex_dat;
wire [2:0] dec_ex_xrs_rwe;
wire [4:0] ex_mem_rd;
wire [63:0] ex_mem_addr, ex_mem_dat;
wire ex_mem_we;
wire ex_mem_nomem;
wire ex_mem_mem;
wire [2:0] ex_mem_xrs_rwe;
wire [2:0] mem_xrs_rwe;
wire [63:0] mem_xrs_dat;
wire [4:0] mem_xrs_rd;
wire [4:0] ex_dec_rd, mem_dec_rd;
wire [63:0] ex_dec_q, mem_dec_q;
wire [63:0] wbmadr_o;
wire [15:0] wbmdat_o;
wire wbmwe_o, wbmstb_o;
wire [1:0] wbmsel_o;
reg wbmack_i, wbmstall_i;
reg [15:0] wbmdat_i;
always begin
#10 clk_i <= ~clk_i;
end
decode decode(
.clk_i(clk_i),
.reset_i(reset_i),
.inst_i(inst_i),
.inst_en_i(inst_en_i),
.rs1val_i(xrs_dec_rs1val),
.rs2val_i(xrs_dec_rs2val),
.ex_rd_i(ex_dec_rd),
.mem_rd_i(mem_dec_rd),
.ex_q_i(ex_dec_q),
.mem_q_i(mem_dec_rd),
.inpa_o(dec_ex_inpa),
.inpb_o(dec_ex_inpb),
.invB_o(dec_ex_invB),
.cflag_o(dec_ex_cflag),
.lsh_en_o(dec_ex_lsh_en),
.rsh_en_o(dec_ex_rsh_en),
.ltu_en_o(dec_ex_ltu_en),
.lts_en_o(dec_ex_lts_en),
.sum_en_o(dec_ex_sum_en),
.and_en_o(dec_ex_and_en),
.xor_en_o(dec_ex_xor_en),
.rd_o(dec_ex_rd),
.rs1_o(dec_xrs_rs1),
.rs2_o(dec_xrs_rs2),
.we_o(dec_ex_we),
.nomem_o(dec_ex_nomem),
.mem_o(dec_ex_mem),
.dat_o(dec_ex_dat),
.xrs_rwe_o(dec_ex_xrs_rwe),
.illegal_o(illegal_o)
);
exec exec(
.clk_i(clk_i),
.reset_i(reset_i),
.inpa_i(dec_ex_inpa),
.inpb_i(dec_ex_inpb),
.invB_i(dec_ex_invB),
.cflag_i(dec_ex_cflag),
.lsh_en_i(dec_ex_lsh_en),
.rsh_en_i(dec_ex_rsh_en),
.ltu_en_i(dec_ex_ltu_en),
.lts_en_i(dec_ex_lts_en),
.sum_en_i(dec_ex_sum_en),
.and_en_i(dec_ex_and_en),
.xor_en_i(dec_ex_xor_en),
.rd_i(dec_ex_rd),
.we_i(dec_ex_we),
.nomem_i(dec_ex_nomem),
.mem_i(dec_ex_mem),
.dat_i(dec_ex_dat),
.xrs_rwe_i(dec_ex_xrs_rwe),
.busy_i(1'b0),
.rd_o(ex_mem_rd),
.addr_o(ex_mem_addr),
.we_o(ex_mem_we),
.nomem_o(ex_mem_nomem),
.mem_o(ex_mem_mem),
.dat_o(ex_mem_dat),
.xrs_rwe_o(ex_mem_xrs_rwe)
);
assign ex_dec_rd = ex_mem_rd;
assign ex_dec_q = ex_mem_addr;
lsu ls(
.clk_i(clk_i),
.reset_i(reset_i),
.addr_i(ex_mem_addr),
.dat_i(ex_mem_dat),
.we_i(ex_mem_we),
.nomem_i(ex_mem_nomem),
.mem_i(ex_mem_mem),
.xrs_rwe_i(ex_mem_xrs_rwe),
.xrs_rd_i(ex_mem_rd),
.busy_o(),
.rwe_o(mem_xrs_rwe),
.dat_o(mem_xrs_dat),
.rd_o(mem_xrs_rd),
.wbmadr_o(wbmadr_o),
.wbmdat_o(wbmdat_o),
.wbmwe_o(wbmwe_o),
.wbmstb_o(wbmstb_o),
.wbmsel_o(wbmsel_o),
.wbmack_i(wbmack_i),
.wbmstall_i(wbmstall_i),
.wbmdat_i(wbmdat_i)
);
assign mem_dec_rd = mem_xrs_rd;
assign mem_dec_q = mem_xrs_dat;
xrs x(
.clk_i(clk_i),
.rd_i(mem_xrs_rd),
.rdat_i(mem_xrs_dat),
.rwe_i(mem_xrs_rwe),
.rdata_o(xrs_dec_rs1val),
.rdatb_o(xrs_dec_rs2val),
.ra_i(dec_xrs_rs1),
.rb_i(dec_xrs_rs2)
);
task zero;
begin
{
reset_i, inst_i, inst_en_i,
wbmack_i, wbmstall_i, wbmdat_i,
story_to, fault_to
} <= 0;
end
endtask
`STANDARD_FAULT
initial begin
$dumpfile("integration.vcd");
$dumpvars;
zero;
clk_i <= 0;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
inst_en_i <= 1;
inst_i <= 32'b000100000000_00000_000_00001_0010011; // ADDI X1, X0, 256
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000000000000_00000_000_00000_0010011;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000100000000_00001_000_00001_0010011; // ADDI X1, X1, 256
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000000000000_00000_000_00000_0010011;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b0000000_00001_00000_011_00000_0100011; // SD X1, 0(X0)
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000000000000_00000_000_00000_0010011;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
story_to <= 12'h010;
inst_en_i <= 1;
inst_i <= 32'b000100000000_00000_000_00001_0010011; // ADDI X1, X0, 256
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000100000000_00001_000_00001_0010011; // ADDI X1, X1, 256
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b0000000_00001_00000_011_00000_0100011; // SD X1, 0(X0)
wait(~clk_i); wait(clk_i); #1;
inst_i <= 32'b000000000000_00000_000_00000_0010011;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
#100;
$display("@Done.");
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; scanf( %d%d , &n, &t); string s; cin >> s; string s1 = , s2 = ; bool ck = 0; for (int i = 0; i < s.size(); i++) { if (s[i] == . ) ck = 1; else if (ck) s2 += s[i]; else s1 += s[i]; } if (ck == 0) { cout << s << endl; return 0; } int cnt = 0; ck = 0; for (int i = 0; i < s2.size(); i++) { if (s2[i] >= 5 ) { cnt = i; ck = 1; break; } } int cp = 0; if (ck) { while (cnt >= 0) { if (cp == t) break; cp++; cnt--; int val = (s2[cnt] - 0 ) + 1; s2[cnt] = (val + 0 ); if (val < 5) break; } if (cnt == -1) { int len = s1.size(); string sl = ; for (int i = 0; i < len - 1; i++) sl += 0 ; sl += 1 ; int ca = 0; string s9 = ; for (int i = len - 1; i >= 0; i--) { int val = (s1[i] - 0 ) + (sl[i] - 0 ) + ca; ca = val / 10; s9 += (val % 10 + 0 ); } if (ca) s9 += (ca + 0 ); reverse(s9.begin(), s9.end()); cout << s9 << endl; } else { cout << s1 << . ; if (ck) for (int i = 0; i <= cnt; i++) cout << s2[i]; else cout << s2 << endl; cout << endl; } } else { cout << s << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000006; int n, k; int main() { int i, j; cin >> n >> k; if (k > n) { printf( -1 ); return 0; } if (k == 1 && n == 1) { printf( a ); return 0; } if (k == 1 && n > 1) { puts( -1 ); return 0; } int e = k - 2; if (e >= 0) { for (i = 0; i < n - e; i++) if (i & 1) printf( b ); else printf( a ); for (i = 0; i < e; i++) printf( %c , c + i); } else if (e < 0) { for (i = 0; i < n; i++) if (i & 1) printf( b ); else printf( a ); } }
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)(1e9 + 17); const long long mod = (long long)(1e9 + 7); int n, k; string s, t; int dp[201][201][201]; int recurse(int idx, int tot, int ct) { if (tot > k) { return -inf; } if (idx == n) { if (tot > k) return -inf; return 0; } int &ans = dp[idx][tot][ct]; if (ans != -1) { return ans; } ans = -inf; if (s[idx] != t[1] or s[idx] != t[0]) ans = max(ans, recurse(idx + 1, tot, ct)); ans = max(ans, recurse(idx + 1, tot + (s[idx] != t[0]), ct + 1)); ans = max(ans, ct + recurse(idx + 1, tot + (s[idx] != t[1]), ct + (t[0] == t[1]))); return ans; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> k; cin >> s >> t; memset(dp, -1, sizeof dp); int ans = recurse(0, 0, 0); cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, h, v[1100]; multiset<long long> s; cin >> n >> h; for (int i = 0; i < n; i++) cin >> v[i]; long long k, ht; for (int i = 0; i < n; i++) { s.insert(v[i]); k = 0; ht = 0; for (multiset<long long>::reverse_iterator rit = s.rbegin(); rit != s.rend(); ++rit) { if (k % 2 == 0) ht += *rit; k++; } if (ht > h) { cout << i << n ; return 0; } } cout << n << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1010; int n, t, pop = -1, p[2 * MAX], para[2 * MAX], odw[2 * MAX]; inline void dodaj_pare(int a, int b) { para[a] = b; para[b] = a; } void wczytaj_dane() { int m; cin >> n >> m; for (int i = 0; i < (2 * n); i++) cin >> p[i]; fill(para, para + 2 * n, -1); while (m--) { int a, b; cin >> a >> b; dodaj_pare(a - 1, b - 1); } cin >> t; } void wypisz(int x) { assert(!odw[x]); odw[x] = true; cout << (x + 1) << n ; fflush(stdout); } int najsilniejszy_sparowany() { int x = -1; for (int i = 0; i < (2 * n); i++) if ((!odw[i]) && para[i] != -1 && (x == -1 || p[x] < p[i])) x = i; return x; } int najsilniejszy() { int x = -1; for (int i = 0; i < (2 * n); i++) if ((!odw[i]) && (x == -1 || p[x] < p[i])) x = i; assert(x != -1); return x; } int rozwiaz() { int x = najsilniejszy_sparowany(); if (x != -1) return x; return najsilniejszy(); } void moj_ruch() { if (pop != -1 && para[pop] != -1 && (!odw[para[pop]])) { wypisz(para[pop]); return; } wypisz(rozwiaz()); } inline int wczytaj() { int x; cin >> x; if (x == -1) exit(1); return x - 1; } void twoj_ruch() { int x = wczytaj(); odw[x] = true; pop = x; } void zrob_test() { wczytaj_dane(); fill(odw, odw + 2 * n, false); if (t == 1) { for (int q = 0; q < (n); q++) { moj_ruch(); twoj_ruch(); } } else { for (int q = 0; q < (n); q++) { twoj_ruch(); moj_ruch(); } } } int main() { zrob_test(); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_rx.v
//----------------------------------------------------------------------------//
// File: axi_basic_rx.v //
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // tkeep width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [STRB_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.STRB_WIDTH( STRB_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: FIFO control
-- Description: Unidad de control para FIFO. Implementa los punteros de
escritura/lectura para las operaciones PUSH y POP.
Esta implementacion no ofrece una señal para indicar que
el FIFO se encuentra vacio. existe la señal de buffer
vacio, simplemente no se expone como linea para
interactuar con el diseño.
-- Dependencies: -- system.vh
-- Parameters: -- CHANNEL_WIDTH: Ancho de palabra de los canales
de comunicacion entre routers.
-- BUFFER_DEPTH: Numero de direcciones en la
estructura de memoria.
-- ADDR_WIDTH: Numero de bits requerido para
representar el espacio de
direcciones del elemento de
memoria del FIFO.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 07 de Junio 2015
*/
`include "system.vh"
module fifo_control_unit
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire write_strobe_din,
input wire read_strobe_din,
// -- outputs ------------------------------------------------ >>>>>
output wire full_dout,
output wire empty_dout,
output wire [ADDR_WIDTH-1:0] write_addr_dout,
output wire [ADDR_WIDTH-1:0] read_addr_dout
);
// --- Definiciones Locales -------------------------------------- >>>>>
localparam ADDR_WIDTH = clog2(`BUFFER_DEPTH);
// --- Señales --------------------------------------------------- >>>>>
reg [ADDR_WIDTH-1:0] write_ptr_reg;
reg [ADDR_WIDTH-1:0] write_ptr_next;
reg [ADDR_WIDTH-1:0] read_ptr_reg;
reg [ADDR_WIDTH-1:0] read_ptr_next;
reg full_reg;
reg full_next;
reg empty_reg;
reg empty_next;
assign write_addr_dout = write_ptr_reg;
assign read_addr_dout = read_ptr_reg;
assign full_dout = full_reg;
assign empty_dout = empty_reg;
/*
-- Descripcion: Maquina de estados finito para la administracion del
espacio de almacenamiento.
Se especifican 3 tipos de operaciones:
-- Escritura: Si el buffer no se encuentra repleto
se ordena la escritura del dato
presente en el puerto de entrada.
Puntero de escritura mas uno.
-- Lectura: Si el buffer no se encuentra vacio, se
muestra a la salida del FIFO el
siguiente dato almacenado.
Puntero de lectura mas uno.
-- Escritura/Lectura:
Operacion concurrente de lectura y
escritura, los punteros no se avanzan.
*/
// --- Elementos de Memoria ---------------------------------- >>>>>
always @(posedge clk)
if (reset)
begin
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
full_reg <= full_next;
empty_reg <= empty_next;
end
// --- Elementos de Memoria ---------------------------------- >>>>>
always @(posedge clk)
if (reset)
write_ptr_reg <= {ADDR_WIDTH{1'b0}};
else
write_ptr_reg <= write_ptr_next;
always @(posedge clk)
if (reset)
read_ptr_reg <= {ADDR_WIDTH{1'b0}};
else
read_ptr_reg <= read_ptr_next;
// --- Logica de punteros de estado -------------------------- >>>>>
wire [ADDR_WIDTH-1:0] write_ptr_succ;
wire [ADDR_WIDTH-1:0] read_ptr_succ;
assign write_ptr_succ = (write_ptr_reg == `BUFFER_DEPTH-1) ? {ADDR_WIDTH{1'b0}} : write_ptr_reg + 1'b1;
assign read_ptr_succ = (read_ptr_reg == `BUFFER_DEPTH-1) ? {ADDR_WIDTH{1'b0}} : read_ptr_reg + 1'b1;
always @(*)
begin
write_ptr_next = write_ptr_reg;
read_ptr_next = read_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({write_strobe_din, read_strobe_din})
2'b01: // Read
begin
if(~empty_reg)
begin
read_ptr_next = read_ptr_succ;
full_next = 1'b0;
if (read_ptr_succ == write_ptr_reg)
empty_next = 1'b1;
end
end
2'b10: // Write
begin
if(~full_reg)
begin
write_ptr_next = write_ptr_succ;
empty_next = 1'b0;
if (write_ptr_succ == read_ptr_reg)
full_next = 1'b1;
end
end
2'b11: // Concurrent Read - Write
begin
write_ptr_next = write_ptr_succ;
read_ptr_next = read_ptr_succ;
end
endcase
end
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Funciones ---------------------------------------------- >>>>>
// Funcion de calculo: log2(x) ---------------------- >>>>>
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
wire full;
wire empty;
wire [ADDR_WIDTH-1:0] write_addr;
wire [ADDR_WIDTH-1:0] read_addr;
fifo_control_unit fifo_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.write_strobe_din (write_strobe_din),
.read_strobe_din (read_strobe_din),
// -- outputs ------------------------------------------------ >>>>>
.full_dout (full),
//.empty_dout (empty),
.write_addr_dout (write_addr),
.read_addr_dout (read_addr)
);
*/
|
// Model a simple flip flop with asynchronous reset
//
// Notes:
// - Including the reset signal in the sensitivity list is
// what makes the reset asynchronous
//
// - Most flip-flops have an asynchronous reset pin.
// This pin is inferred from the behavioral statement below.
//
// Advantages:
// - Asynchronous resets do not add combinational path delay
// resulting in higher frequency circuits. Most vendor libraries
// include flops with async resets that can be directly inferred
// from the logic below.
//
// - The circuit can be reset without a clock being present
//
// Disadvantages:
// - Async reset can be asserted/deasserted at anytime (e.g.
// from a board pin). The assertion/de-assertion may not
// be clean (i.e. can glitch/bounce). If the reset removal
// happens during during the setup/hold time of the flop,
// flop output can go metastable (this is true for sync
// reset as well - but the problem is more common in async flops).
// It is recommended to use a reset removal circuit to
// remove any glitching for async reset.
// - Suppose the async reset is applied to two flops.
// Each flop could recieve the reset signal at different times
// and cause reset at different times. This will cause
// different registers to exit the reset state at different time.
// This behavior can cascade through the design.
//
// - As a general guideline, always synchronize asynchronous
// reset inputs using a reset synchronizer circuit
// (see reset_synchronizer.v)
//
//
module flop_async_rst(
input clk,
input arst,
input din,
output reg q
);
always@(posedge clk or posedge arst)
if(rst)
q <= 0;
else
q <= din;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:44:45 11/19/2015
// Design Name: MPU_controller
// Module Name: C:/Users/Camilo/Documents/Xilinx_Workspace/I2C_Module/controller_tst.v
// Project Name: I2C_Module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MPU_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module controller_tst;
// Inputs
reg clk;
reg clk_frame;
reg rst;
reg en;
// Outputs
wire busy;
wire [15:0] AcX;
wire [15:0] AcY;
wire [15:0] AcZ;
wire [15:0] GyX;
wire [15:0] GyY;
wire [15:0] GyZ;
wire error_i2c;
wire SCL;
// Bidirs
wire SDA;
reg SDA_out, SDA_oen;
wire SDA_in;
assign SDA = SDA_oen? 1'bz : SDA_out;
assign SDA_in = SDA;
// Instantiate the Unit Under Test (UUT)
MPU_controller uut (
.clk(clk),
.clk_frame(clk_frame),
.rst(rst),
.en(en),
.busy(busy),
.AcX(AcX),
.AcY(AcY),
.AcZ(AcZ),
.GyX(GyX),
.GyY(GyY),
.GyZ(GyZ),
.error_i2c(error_i2c),
.SCL(SCL),
.SDA(SDA)
);
initial begin
// Initialize Inputs
clk = 0;
clk_frame = 0;
rst = 1;
en = 0;
SDA_oen = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
#150 en = 1;
#150 en = 0;
#3600;
SDA_oen = 0;
SDA_out = 0;
#335;
SDA_oen = 1;
#3665 SDA_oen = 0;
#335 SDA_oen = 1;
#3630 SDA_oen = 0;
#335 SDA_oen = 1;
#4505 SDA_oen = 0;
#335 SDA_oen = 1;
#3628 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#4460 SDA_oen = 0;
#385 SDA_oen = 1;
#3580 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#4460 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#4460 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#4000 en = 1;
#150 en = 0;
#3810 SDA_oen = 0;
#385 SDA_oen = 1;
#3570 SDA_oen = 0;
#385 SDA_oen = 1;
#4040 SDA_oen = 0;
#440 SDA_out = 1; // b7
#440 SDA_out = 1; // b6
#440 SDA_out = 0; // b5
#440 SDA_out = 0; // b4
#440 SDA_out = 1; // b3
#440 SDA_out = 0; // b2
#440 SDA_out = 1; // b1
#440 SDA_out = 0; // b0
#440 SDA_oen = 1; // ACK
#385 SDA_oen = 0;
SDA_out = 1; // b7
#440 SDA_out = 1; // b6
#440 SDA_out = 0; // b5
#440 SDA_out = 0; // b4
#440 SDA_out = 1; // b3
#440 SDA_out = 0; // b2
#440 SDA_out = 1; // b1
#440 SDA_out = 0; // b0
#495 SDA_oen = 1; // ACK
#413 SDA_oen = 0;
SDA_out = 0; // b7
#440 SDA_out = 1; // b6
#440 SDA_out = 0; // b5
#440 SDA_out = 1; // b4
#440 SDA_out = 0; // b3
#440 SDA_out = 1; // b2
#440 SDA_out = 0; // b1
#440 SDA_out = 1; // b0
#495 SDA_oen = 1; // ACK
#413 SDA_oen = 0;
SDA_out = 1; // b7
#440 SDA_out = 1; // b6
#440 SDA_out = 1; // b5
#440 SDA_out = 1; // b4
#440 SDA_out = 0; // b3
#440 SDA_out = 0; // b2
#440 SDA_out = 0; // b1
#440 SDA_out = 0; // b0
#495 SDA_oen = 1; // ACK
#370 SDA_oen = 0;
SDA_out = 1;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
#425 SDA_oen = 0;
#3535 SDA_oen = 1;
//#425 SDA_oen = 0;
end
always #5 clk = ~clk;
always #55 clk_frame = ~clk_frame;
endmodule
|
module RAM_TEST #(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 1,
parameter IS_DUAL_PORT = 1,
parameter RANDOM_ITERATION_PER_LOOP = 10,
parameter LFSR_WIDTH = 16,
parameter LFSR_POLY = 16'hD008,
// How much to increment the address to move 1 full data width.
parameter ADDRESS_STEP = 1,
// Max address for this memory
parameter MAX_ADDRESS = 63
) (
input rst,
input clk,
// Memory connection
input [DATA_WIDTH-1:0] read_data,
output reg [DATA_WIDTH-1:0] write_data,
output reg write_enable,
output reg [ADDR_WIDTH-1:0] read_address,
output reg [ADDR_WIDTH-1:0] write_address,
// INIT ROM
// When the memory is first initialized, it is expected to match the ROM
// port.
input [DATA_WIDTH-1:0] rom_read_data,
output reg [ADDR_WIDTH-1:0] rom_read_address,
// When an iteration is complete, success will be 1 for 1 cycle
output reg loop_complete,
// If an error occurs during a test, error will be 1 for each cycle
// with an error.
output reg error,
// error_state will contain the state of test FSM when the error occured.
output reg [7:0] error_state,
// error_address will be the read address where the error occurred.
output reg [ADDR_WIDTH-1:0] error_address,
// expected_data will be the read value expected.
output reg [DATA_WIDTH-1:0] expected_data,
// actual_data will be the read value read.
output reg [DATA_WIDTH-1:0] actual_data
);
reg [7:0] state;
reg [DATA_WIDTH-1:0] test_value;
reg [$clog2(RANDOM_ITERATION_PER_LOOP)-1:0] rand_count;
localparam START = 8'd1,
VERIFY_INIT = 8'd2,
WRITE_ZEROS = 8'd3,
VERIFY_ZEROS = 8'd4,
WRITE_ONES = 8'd5,
VERIFY_ONES = 8'd6,
WRITE_10 = 8'd7,
VERIFY_10 = 8'd8,
WRITE_01 = 8'd9,
VERIFY_01 = 8'd10,
WRITE_RANDOM = 8'd11,
VERIFY_RANDOM = 8'd12,
RESTART_LOOP = 8'd13;
reg pause;
reg lfsr_reset;
reg wait_for_lfsr_reset;
reg [LFSR_WIDTH-1:0] lfsr_seed;
reg [LFSR_WIDTH-1:0] start_lfsr_seed;
wire [LFSR_WIDTH-1:0] rand_data;
LFSR #(
.WIDTH(LFSR_WIDTH),
.POLY(LFSR_POLY)
) lfsr (
.rst(lfsr_reset),
.clk(clk),
.seed(lfsr_seed),
.r(rand_data)
);
always @(posedge clk) begin
if(rst) begin
state <= START;
error <= 0;
write_enable <= 0;
lfsr_reset <= 1;
lfsr_seed <= 1;
end else begin
case(state)
START: begin
lfsr_reset <= 0;
state <= VERIFY_INIT;
read_address <= 0;
rom_read_address <= 0;
write_enable <= 0;
error <= 0;
end
VERIFY_INIT: begin
if(rom_read_data != read_data) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rom_read_data;
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
rom_read_address <= rom_read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
end
WRITE_ZEROS: begin
loop_complete <= 0;
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
pause <= 1;
state <= VERIFY_ZEROS;
end
end
VERIFY_ZEROS: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b1}};
state <= WRITE_ONES;
end
end
end
WRITE_ONES: begin
// If dual port, data should still be zero.
if(IS_DUAL_PORT) begin
if(read_data != {DATA_WIDTH{1'b0}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b0}};
actual_data <= read_data;
end else begin
error <= 0;
end
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
end
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
write_address <= write_address + ADDRESS_STEP;
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_ONES;
pause <= 1;
end
end
VERIFY_ONES: begin
if(pause) begin
pause <= 0;
end else begin
if(read_data != {DATA_WIDTH{1'b1}}) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= {DATA_WIDTH{1'b1}};
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= WRITE_RANDOM;
write_enable <= 1;
write_address <= 0;
lfsr_seed <= rand_data;
write_data <= rand_data[DATA_WIDTH-1:0];
read_address <= 0;
end
end
end
WRITE_RANDOM: begin
if(write_address + ADDRESS_STEP <= MAX_ADDRESS) begin
write_address <= write_address + ADDRESS_STEP;
write_data <= rand_data[DATA_WIDTH-1:0];
end else begin
read_address <= 0;
write_address <= 0;
write_enable <= 0;
state <= VERIFY_RANDOM;
// Return LFSR to state at beginning of WRITE_RANDOM.
lfsr_reset <= 1;
wait_for_lfsr_reset <= 1;
end
end
VERIFY_RANDOM: begin
if(wait_for_lfsr_reset) begin
wait_for_lfsr_reset <= 0;
lfsr_reset <= 1;
end else begin
lfsr_reset <= 0;
if(read_data != rand_data[DATA_WIDTH-1:0]) begin
error <= 1;
error_state <= state;
error_address <= read_address;
expected_data <= rand_data[DATA_WIDTH-1:0];
actual_data <= read_data;
end else begin
error <= 0;
end
if(read_address + ADDRESS_STEP <= MAX_ADDRESS) begin
read_address <= read_address + ADDRESS_STEP;
end else begin
state <= RESTART_LOOP;
end
end
end
RESTART_LOOP: begin
loop_complete <= 1;
error <= 0;
read_address <= 0;
write_address <= 0;
write_enable <= 1;
write_data <= {DATA_WIDTH{1'b0}};
state <= WRITE_ZEROS;
end
default: begin
state <= START;
error <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, a, b, p, q, z, k; cin >> t; while (t--) { z = 0; k = 0; cin >> a >> b >> n; p = max(a, b); q = min(a, b); while (k <= n) { z++; k = q + p; q = p; p = k; } cout << z << endl; } }
|
#include <bits/stdc++.h> using namespace std; const string st = AHIMOTUVWXY ; string s; int main() { ios::sync_with_stdio(0); cin >> s; int n = s.size(); for (int i = 0; i <= n - 1; ++i) if (st.find(s[i], 0) == -1) { cout << NO ; return 0; } string s1 = s; reverse(s1.begin(), s1.end()); if (s1 == s) cout << YES ; else cout << NO ; return 0; }
|
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