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#include <bits/stdc++.h> using namespace std; long long a[1111]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long n, ans = 0; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + 1 + n); for (long long i = 1; i < n; i++) { ans = ans + (a[i + 1] - a[i] - 1); } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; string s, t; cin >> n >> s >> t; string ss = s, tt = t; sort(ss.begin(), ss.end()); sort(tt.begin(), tt.end()); if (ss != tt) cout << -1 << n ; else { vector<int> ans; for (int j = (int)(n - 1); j >= int(0); j--) { char target = t[j]; ; int pos = n - j - 1; ; while (target != s[pos]) pos++; ; ; ans.push_back(n); reverse(s.begin(), s.end()); ; ans.push_back(pos); string temp(s.begin() + n - pos, s.end()); reverse(temp.begin(), temp.end()); s.erase(s.begin() + n - pos, s.end()); s.insert(s.begin(), temp.begin(), temp.end()); ; ans.push_back(1); char c = s[n - 1]; s.erase(s.begin() + n - 1); s.insert(s.begin(), c); ; } cout << int((ans).size()) << n ; for (int i = 0; i < int(int((ans).size())); i++) { if (i) cout << ; cout << ans[i]; } cout << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 58, SQ = 500; int LE[maxn], LO[maxn], par[maxn], a[maxn], root[maxn], lazy[maxn], m; inline void make(int j) { int lase = -1, laso = -1; int l = j * SQ; for (int i = l; i - l < SQ; i++) { a[i] ^= lazy[j]; if (a[i]) laso = i; else lase = i; LE[i] = lase; LO[i] = laso; if (i - l >= m + 1) { if (a[i]) par[i] = LO[i - (m + 1)]; else par[i] = LE[i - (m + 1)]; } else par[i] = -1; if (par[i] == -1) root[i] = i; else root[i] = root[par[i]]; } lazy[j] = 0; } inline int getlast(int r) { while ((lazy[r / SQ] && (LE[r] == -1 || LE[r] / SQ != r / SQ)) || (!lazy[r / SQ] && (LO[r] == -1 || LO[r] / SQ != r / SQ))) { r = r / SQ * SQ - 1; } if (lazy[r / SQ]) return LE[r]; return LO[r]; } inline bool P(int r, int l) { while (r / SQ > l / SQ) { r = root[r]; r = getlast(r - m - 1); } while (r > l) { r = par[r]; } return r == l; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, q; cin >> n >> m >> q; int lase = -1, laso = -1; for (int i = 0; i < n; i++) { long long b; cin >> b; b &= 1; a[i] = b; if (b) laso = i; else lase = i; LE[i] = lase; LO[i] = laso; if (i % SQ >= m + 1) { if (b) par[i] = LO[i - (m + 1)]; else par[i] = LE[i - (m + 1)]; if (par[i] == -1 || par[i] / SQ < i / SQ) par[i] = -1; } else par[i] = -1; if (par[i] == -1) root[i] = i; else root[i] = root[par[i]]; } while (q--) { int t; cin >> t; if (t == 1) { int l, r; long long d; cin >> l >> r >> d; d &= 1; l--; r--; if (!d) continue; for (int i = l / SQ + 1; i < r / SQ; i++) { lazy[i] ^= 1; } if (l / SQ != r / SQ) { for (int i = l; i / SQ == l / SQ; i++) { a[i] ^= 1; } for (int i = r / SQ * SQ; i <= r; i++) { a[i] ^= 1; } make(l / SQ); make(r / SQ); } else { for (int i = l; i <= r; i++) { a[i] ^= 1; } make(l / SQ); } } else { int l, r; cin >> l >> r; l--; r--; if (a[l] == lazy[l / SQ]) { cout << 1 n ; continue; } int x = getlast(r); if (P(x, l)) cout << 2 n ; else cout << 1 n ; } } }
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/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ns / 1ps
`default_nettype none
module qmca_clk_gen(
input CLKIN, // 48M
output BUS_CLK, // BUS_CLK is 48M output from 1. DCM
output SPI_CLK, // SPI_CLK is 12 MHz (48M / 4 = 12M) output from 1. DCM
output ADC_ENC, // ADC_ENC is 10 MHz ( 80M / 8 = 10 M) output from 2. DCM
output ADC_CLK, // ADC_CLK is 160 MHz ( 80M * 2 = 160 M) output from 1. DCM
output LOCKED
);
wire GND_BIT;
assign GND_BIT = 0;
wire CLKD10MHZ;
wire CLKFX_BUF, CLKOUTFX, CLKDV, CLKDV_BUF;
wire CLK0_BUF; // Buffered input of DCM1
wire CLKFX_160FB; // Feedback to DCM2 (buffered input of DCM2)
wire CLKOUT160, CLKDV_10;
wire CLK2_0;
wire CLKFX_40;
wire CLKFX_160;
wire U2_RST_IN;
wire CLK0_XU2_BUF;
assign ADC_ENC = CLKD10MHZ;
//assign ADC_CLK = CLKFX_160FB; //CLK0_XU2_BUF
//assign ADC_CLK = CLK0_XU2_BUF;
assign ADC_CLK = CLKOUT160;
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), .O(CLKOUTFX));
BUFG CLKFB_BUFG_INST (.I(CLK0_BUF), .O(BUS_CLK));
BUFG CLKDV_BUFG_INST (.I(CLKDV), .O(CLKDV_BUF));
assign SPI_CLK = CLKDV_BUF;
wire LOCKED_U1;
// First DCM gets 48 MHz clock
// --> Makes 160 MHz output on CLKFX (48 * 10/3) for next DCM as input and for ADC_CLK
DCM #(
.CLKDV_DIVIDE(16), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(3), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(10), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(20.833), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_BUS (
.CLKFB(BUS_CLK),
.CLKIN(CLKIN),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV),
.CLKFX(CLKFX_160),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_U1),
.PSDONE(),
.STATUS());
// buffer 160 M output from DCM1 and use buffered 160 M as input to DCM2
BUFG CLKFX_2_BUFG_INST (.I(CLKFX_160), .O(CLKOUT160));
BUFG CLKDV_2_BUFG_INST (.I(CLKDV_10), .O(CLKD10MHZ));
// buffer input to DCM2 (160 MHz) and use as feedback for DCM2
BUFG CLKFB_2_BUFG_INST (.I(CLK2_0), .O(CLKFX_160FB));
wire CLK0_XU2;
BUFG CLKFB_2_BUFG_CLK0_XU2 (.I(CLK0_XU2), .O(CLK0_XU2_BUF));
// Second DCM gets 160 MHz clock
// --> Makes 320 MHz output on CLK2X for TDC_320_CLK
// --> Makes 40 MHz output on CLKFX (1 / 4) for TDC_40_CLK
// --> Makes 10 MHz output on CLKDV (1 / 16) for ADC_ENC
DCM #(
.CLKDV_DIVIDE(16), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(8), // Can be any Integer from 1 to 32
.CLKFX_MULTIPLY(2), // Can be any Integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(25.0), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an Integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'h8080), // FACTORY JF values
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
) DCM_CMD (
.DSSEN(GND_BIT),
.CLK0(CLK2_0), // 0 degree DCM_SP CLK output
.CLK180(), // 180 degree DCM_SP CLK output
.CLK270(), // 270 degree DCM_SP CLK output
.CLK2X(), // 2X DCM_SP CLK output
.CLK2X180(), // 2X, 180 degree DCM_SP CLK out
.CLK90(CLK0_XU2), // 90 degree DCM_SP CLK output
.CLKDV(CLKDV_10), // Divided DCM_SP CLK out (CLKDV_DIVIDE)
.CLKFX(), // DCM_SP CLK synthesis out (M/D)
.CLKFX180(), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM_SP LOCK status output
.PSDONE(), // Dynamic phase adjust done output
.STATUS(), // 8-bit DCM_SP status bits output
.CLKFB(CLKFX_160FB), // DCM_SP clock feedback
.CLKIN(CLKOUT160), // Clock input (from IBUFG, BUFG or DCM_SP)
.PSCLK(GND_BIT), // Dynamic phase adjust clock input
.PSEN(GND_BIT), // Dynamic phase adjust enable input
.PSINCDEC(GND_BIT), // Dynamic phase adjust increment/decrement
.RST(U2_RST_IN)// // DCM_SP asynchronous reset input
);
reg [3:0] rst_dly;
initial rst_dly = 0;
always@(posedge BUS_CLK)
rst_dly <= {rst_dly[2:0], !LOCKED_U1};
assign U2_RST_IN = rst_dly[3];
endmodule
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#include <bits/stdc++.h> using namespace std; int n, step; vector<string> ans; bool isi[256]; int now[26]; string eb(int p) { return string( e ) + char(p + a ) + x ; } string sz(int p) { return string( ) + char(p + 0 ); } void dfs(int x) { if (x == step) { if (isi[n]) { printf( %d n , step); for (int i = 0; i < ans.size(); i++) cout << ans[i] << endl; exit(0); } return; } for (int i = 0; i <= x; i++) for (int k = 1; k <= 8; k <<= 1) { now[x + 1] = now[i] * k; if (now[x + 1] > n || isi[now[x + 1]]) continue; ans.push_back(string( lea ) + eb(x + 1) + , [ + sz(k) + * + eb(i) + ] ); isi[now[x + 1]] = 1; dfs(x + 1); ans.pop_back(); isi[now[x + 1]] = 0; } for (int i = 0; i <= x; i++) for (int j = 0; j <= x; j++) for (int k = 1; k <= 8; k <<= 1) { now[x + 1] = now[i] + now[j] * k; if (now[x + 1] > n || isi[now[x + 1]]) continue; ans.push_back(string( lea ) + eb(x + 1) + , [ + eb(i) + + + sz(k) + * + eb(j) + ] ); isi[now[x + 1]] = 1; dfs(x + 1); ans.pop_back(); isi[now[x + 1]] = 0; } } int main() { scanf( %d , &n); for (step = 0;; step++) now[0] = isi[1] = 1, dfs(0); return 0; }
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,sse4.2,popcnt,abm,mmx,avx ) using namespace std; template <class U, class V> istream& operator>>(istream& is, pair<U, V>& p) { is >> p.first >> p.second; return is; } template <class T> istream& operator>>(istream& is, vector<T>& v) { for (auto& x : v) { is >> x; } return is; } template <class T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& x : v) { os << x << ; } return os; } const int N = 1e5 + 5; int n, x, y; vector<int> b; int freq[N]; int match_indices[N]; set<pair<int, int>> cnt; vector<int> match_colors[N]; void init() { cnt.clear(); for (int i = 0; i < n + 3; ++i) { freq[i] = 0; match_indices[i] = 0; match_colors[i].clear(); } } void buildFreq() { for (int x : b) { ++freq[x]; } for (int i = 1; i <= n + 1; ++i) { if (freq[i] != 0) { cnt.emplace(freq[i], i); } } } int getMissingElement() { for (int i = 1; i <= n + 1; ++i) { if (freq[i] == 0) return i; } assert(false); return -1; } void buildMatchIndices() { for (int i = 0; i < x; ++i) { auto it = cnt.end(); --it; auto curr = *it; cnt.erase(it); --curr.first; ++match_indices[curr.second]; if (curr.first != 0) { cnt.emplace(curr); } } } bool buildMatchColors() { if (y == 0) return true; if (cnt.empty()) return false; int y = ::y; vector<int> v1; for (auto p : cnt) { while (p.first--) { v1.emplace_back(p.second); } } auto v2 = v1; rotate(begin(v2), begin(v2) + ((int)(v1.size())) - cnt.rbegin()->first, end(v2)); for (int i = 0; i < ((int)(v1.size())); ++i) { if (v1[i] == v2[i]) continue; if (y == 0) break; --y; match_colors[v1[i]].emplace_back(v2[i]); } return y == 0; } void check(const vector<int>& a) { int x = ::x; int y = ::y; y += x; for (int i = 0; i < n; ++i) { x -= (a[i] == b[i]); } assert(x == 0); multiset<int> ms(begin(a), end(a)); for (int i = 0; i < n; ++i) { auto it = ms.find(b[i]); if (it == end(ms)) continue; ms.erase(it); --y; } assert(y == 0); } void solve() { if (y < x) { cout << NO << endl; return; } y -= x; init(); buildFreq(); buildMatchIndices(); if (!buildMatchColors()) { cout << NO << endl; return; } int missing_element = getMissingElement(); vector<int> res(n, missing_element); for (int i = 0; i < n; ++i) { if (match_indices[b[i]] > 0) { --match_indices[b[i]]; res[i] = b[i]; continue; } if (!match_colors[b[i]].empty()) { res[i] = match_colors[b[i]].back(); match_colors[b[i]].pop_back(); } } check(res); cout << YES << endl; cout << res << endl; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { cin >> n >> x >> y; b.resize(n); cin >> b; solve(); } return 0; }
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:10:02
// Design Name:
// Module Name: DD
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module unsigned_to_bcd
(
input clk, // Reloj
input trigger, // Inicio de conversión
input [31:0] in, // Número binario de entrada
output reg idle, // Si vale 0, indica una conversión en proceso
output reg [31:0] bcd // Resultado de la conversión
);
/*
* Por "buenas prácticas" parametrizamos las constantes numéricas de los estados
* del módulo y evitamos trabajar con números "mágicos" en el resto del código.
*
* https://en.wikipedia.org/wiki/Magic_number_(programming)
* http://stackoverflow.com/questions/47882/what-is-a-magic-number-and-why-is-it-bad
*/
localparam S_IDLE = 'b001;
localparam S_SHIFT = 'b010;
localparam S_ADD3 = 'b100;
reg [2:0] state, state_next; /* Contiene al estado actual y al siguiente */
reg [31:0] shift, shift_next;
reg [31:0] bcd_next;
localparam COUNTER_MAX = 32;
reg [5:0] counter, counter_next; /* Contador 6 bit para las iteraciones */
always @(*) begin
/*
* Por defecto, los estados futuros mantienen el estado actual. Esto nos
* ayuda a no tener que ir definiendo cada uno de los valores de las señales
* en cada estado posible.
*/
state_next = state;
shift_next = shift;
bcd_next = bcd;
counter_next = counter;
idle = 1'b0; /* LOW para todos los estados excepto S_IDLE */
case (state)
S_IDLE: begin
counter_next = 'd1;
shift_next = 'd0;
idle = 1'b1;
if (trigger) begin
state_next = S_SHIFT;
end
end
S_ADD3: begin
/*
* Sumamos 3 a cada columna de 4 bits si el valor de esta es
* mayor o igual a 5
*/
if (shift[31:28] >= 5)
shift_next[31:28] = shift[31:28] + 4'd3;
if (shift[27:24] >= 5)
shift_next[27:24] = shift[27:24] + 4'd3;
if (shift[23:20] >= 5)
shift_next[23:20] = shift[23:20] + 4'd3;
if (shift[19:16] >= 5)
shift_next[19:16] = shift[19:16] + 4'd3;
if (shift[15:12] >= 5)
shift_next[15:12] = shift[15:12] + 4'd3;
if (shift[11:8] >= 5)
shift_next[11:8] = shift[11:8] + 4'd3;
if (shift[7:4] >= 5)
shift_next[7:4] = shift[7:4] + 4'd3;
if (shift[3:0] >= 5)
shift_next[3:0] = shift[3:0] + 4'd3;
state_next = S_SHIFT;
end
S_SHIFT: begin
/* Desplazamos un bit de la entrada en el registro shift */
shift_next = {shift[30:0], in[COUNTER_MAX - counter_next]};
/*
* Si el contador actual alcanza la cuenta máxima, actualizamos la salida y
* terminamos el proceso.
*/
if (counter == COUNTER_MAX) begin
bcd_next = shift_next;
state_next = S_IDLE;
end else
state_next = S_ADD3;
/* Incrementamos el contador (siguiente) en una unidad */
counter_next = counter + 'd1;
end
default: begin
state_next = S_IDLE;
end
endcase
end
always @(posedge clk) begin
state <= state_next;
shift <= shift_next;
bcd <= bcd_next;
counter <= counter_next;
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Double port RAM (1 read-only + 1 write-only), read-through */
module tmu2_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32
) (
input sys_clk,
input [depth-1:0] ra,
input re,
output [width-1:0] rd,
input [depth-1:0] wa,
input we,
input [width-1:0] wd
);
reg [width-1:0] ram[0:(1 << depth)-1];
reg [depth-1:0] rar;
always @(posedge sys_clk) begin
if(re)
rar <= ra;
if(we)
ram[wa] <= wd;
end
assign rd = ram[rar];
// synthesis translate_off
integer i;
initial begin
for(i=0;i<(1 << depth);i=i+1)
ram[i] = 0;
end
// synthesis translate_on
endmodule
|
//
// Copyright (c) 2002 Stephen Williams (steve at icarus.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
module main;
reg [3:0] val_drv = 4'b0101;
wire [3:0] val = val_drv;
initial begin
#50 if (val !== val_drv) begin
$display("FAILED -- initial val %b !== %b", val, val_drv);
$finish;
end
force val = 4'b1010;
#1 if (val !== 4'b1010) begin
$display("FAILED -- force 1010 failed, val=%b", val);
$finish;
end
// Use force to "lift" the driver.
force val = 4'bzzzz;
if (val !== 4'bzzzz) begin
$display("FAILED -- force z failed, val=%b", val);
$finish;
end
release val;
#1 if (val !== 4'b0101) begin
$display("FAILED -- unforced val = %b", val);
$finish;
end
val_drv = 4'b1010;
#1 if (val !== 4'b1010) begin
$display("FAILED -- val_drv=%b, val=%b", val_drv, val);
$finish;
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 150007; const double eps = 1e-8; int n; double l, r, mid, sm[N], mxp[N], mnp[N]; struct note { double p, t, c; int id; } a[N], b[N]; int cmp(note x, note y) { return x.c > y.c; } int cmp0(note x, note y) { return x.p < y.p; } int check() { double mxv = 0; for (int i = 1, j, lb, rb; i <= n; i = j) { j = i; while (j <= n && a[j].c == a[i].c) ++j; lb = i, rb = j - 1; for (int k = i; k < j; ++k) { mnp[a[k].id] = a[k].p * (1 - mid * sm[rb] / sm[n]); mxp[a[k].id] = a[k].p * (1 - mid * (sm[lb - 1] + a[k].t) / sm[n]); } } for (int i = 1, j; i <= n; i = j) { j = i; while (j <= n && b[j].p == b[i].p) ++j; for (int k = i; k < j; ++k) if (mxv > mnp[b[k].id]) return 0; for (int k = i; k < j; ++k) mxv = max(mxv, mxp[b[k].id]); } return 1; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %lf , &a[i].p), a[i].id = i; for (int i = 1; i <= n; ++i) scanf( %lf , &a[i].t), a[i].c = a[i].p / a[i].t; memcpy(b, a, sizeof(a)); sort(b + 1, b + n + 1, cmp0); sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n; ++i) sm[i] = sm[i - 1] + a[i].t; l = 0, r = 1; while (r - l > eps) { mid = (l + r) / 2; if (check()) l = mid; else r = mid; } printf( %.7lf n , l); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); int n, p, k; cin >> n >> p >> k; map<int, int> mp; long long sol = 0; for (int i = 0; i < n; i++) { int x; cin >> x; int y = x * 1ll * x % p; y = y * 1ll * y % p; y = ((y - k * 1ll * x) % p + p) % p; sol += mp[y]++; } cout << sol << n ; }
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dexp_64ns_64ns_64_18_full_dsp
#(parameter
ID = 9,
NUM_STAGE = 18,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dexp_16_full_dsp_64 ANN_ap_dexp_16_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int num[100 + 5][100 + 5], ans[100 + 5][100 + 5]; int row[100 + 5], col[100 + 5]; int main() { int n, m; while (scanf( %d%d , &m, &n) != EOF) { int i, j, k; int ii, jj, kk; memset(row, 0, sizeof(row)); memset(col, 0, sizeof(col)); for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { scanf( %d , &num[i][j]); row[i] += num[i][j]; col[j] += num[i][j]; } } for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { ans[i][j] = 1; } } for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { if (num[i][j] == 0) { for (ii = 0; ii < m; ii++) ans[ii][j] = 0; for (jj = 0; jj < n; jj++) ans[i][jj] = 0; } } } bool ok = true; for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { int tp = 0; for (ii = 0; ii < m; ii++) tp |= ans[ii][j]; for (jj = 0; jj < n; jj++) tp |= ans[i][jj]; if (tp != num[i][j]) { ok = false; break; } } if (!ok) break; } if (ok) { printf( YES n ); for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { if (j) printf( ); printf( %d , ans[i][j]); } printf( n ); } } else printf( NO n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; set<long long> myset; int base; int N; long long A[100005]; map<long long, int> Map; int ANS[600000]; int T[1200000]; int Lo[300000]; int ql, qu; int P[300000]; void update(int ind) { ind += base; T[ind] = ind - base; while (1) { ind /= 2; if (ind < 1) break; T[ind] = T[2 * ind]; if (ANS[T[2 * ind + 1]] > ANS[T[ind]]) T[ind] = T[2 * ind + 1]; } } int query(int ind, int cl, int cu) { if (cu < ql || cl > qu) return -1; if (cl >= ql && cu <= qu) return T[ind]; int ansl = query(2 * ind, cl, (cl + cu) / 2); int ansr = query(1 + 2 * ind, 1 + (cl + cu) / 2, cu); if (ansl == -1 || ansr == -1) return (ansl + ansr + 1); if (ANS[ansl] >= ANS[ansr]) return ansl; return ansr; } int main() { int n; int d; cin >> n >> d; for (__typeof((__typeof(n))0) i((__typeof(n))0); i < n; i++) { scanf( %lld , &A[i]); myset.insert(A[i]); myset.insert(A[i] - d); myset.insert(A[i] + d); } int c = 0; for (__typeof(myset.begin()) it(myset.begin()); it != myset.end(); it++) Map[*it] = c++; N = c; base = 1; while (base < N) base *= 2; for (int i = base; i < 2 * base; i++) T[i] = i - base; for (int i = base - 1; i > 0; i--) { T[i] = T[2 * i]; if (ANS[T[2 * i + 1]] > ANS[T[i]]) T[i] = T[2 * i + 1]; } for (int i = 0; i < n; i++) { long long h = A[i]; int x = Map[h]; int ans = -1; qu = Map[h - d]; ql = 0; ans = query(1, 0, base - 1); ql = Map[h + d]; qu = N - 1; int ans2 = query(1, 0, base - 1); if (ans == -1 || ANS[ans] < ANS[ans2]) ans = ans2; if (ans == -1 || ANS[ans] == 0) { ANS[x] = 1; P[i] = -1; } else { ANS[x] = 1 + ANS[ans]; P[i] = Lo[ans]; } update(x); Lo[x] = i; } int p = 0; for (int i = 0; i < N; i++) if (ANS[i] > ANS[p]) p = i; p = Lo[p]; vector<int> TP; while (p >= 0) { TP.push_back(p + 1); p = P[p]; } reverse(TP.begin(), TP.end()); cout << (int)(TP.size()) << endl; for (__typeof(TP.begin()) i(TP.begin()); i != TP.end(); i++) cout << *i << ; cout << endl; return 0; }
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int Maxn3 = 1e3 + 10; const long long int Maxn4 = 1e4 + 10; const long long int Maxn5 = 1e5 + 10; const long long int Maxn6 = 1e6 + 10; const long long int Maxn7 = 1e7 + 10; const long long int Maxn8 = 1e8 + 10; const long long int Maxn9 = 1e9 + 10; const long long int Maxn18 = 1e18 + 10; const long long int Mod1 = 1e7 + 7; const long long int Mod2 = 1e9 + 7; const long long int LLMax = LLONG_MAX; const long long int LLMin = LLONG_MIN; const long long int INTMax = INT_MAX; const long long int INTMin = INT_MIN; long long int mn = LLMax, mx = LLMin; char s[Maxn6]; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); string s1( ... n.X. n ), s2( .X. n ), s; long long int res = 0; cin >> s; for (long long int i = 0; i < s.size(); i++) { if (res < s[i]) res += 256; while (res > s[i]) { res--; cout << s1; } cout << s2; } }
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( avx2 ) #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; void solve() { int n; cin >> n; vector<int> ans; for (int i = 1; i <= 1000; i += 2) { ans.push_back(i); ans.push_back(i); } if (ans.size() < n) { for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } n -= ans.size(); for (int i = 0; i < n; i++) { cout << ans[i] << ; } cout << endl; return; } for (int i = int(0); i < int(n); i++) { cout << ans[i] << ; } cout << endl; } signed main() { int t; cin >> t; while (t--) { solve(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_4_V
`define SKY130_FD_SC_HDLL__AND4BB_4_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_4_V
|
#include <bits/stdc++.h> using namespace std; int n, m, a[300100], b[300100], pos[300100]; vector<pair<int, int> > ans; inline void ws(int xx, int yy) { ans.push_back(make_pair(xx, yy)); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); pos[a[i]] = i; } if (a[1] != 1) { int p = pos[1]; int x = a[1]; if (p - 1 >= n / 2) { ws(1, p); a[1] = 1; pos[1] = 1; pos[x] = p; a[p] = x; } else if (n - p >= n / 2) { ws(p, n); ws(1, n); ws(p, n); a[1] = 1; pos[1] = 1; pos[x] = p; a[p] = x; } } if (a[n] != n) { int p = pos[n]; int x = a[1]; int z = a[n]; if (p - 1 >= n / 2) { ws(1, p); ws(1, n); ws(1, p); a[p] = z; pos[z] = p; pos[n] = n; a[n] = n; } else if (n - p >= n / 2) { ws(p, n); a[p] = z; pos[z] = p; pos[n] = n; a[n] = n; } } for (int i = 2; i < n; ++i) { if (pos[i] == i) continue; int p = pos[i]; int x = a[1]; int y = a[i]; int z = a[n]; if (p - 1 >= n / 2 && i - 1 >= n / 2) { ws(1, p); ws(1, i); ws(1, p); swap(a[i], a[pos[i]]); pos[y] = p; pos[i] = i; } else if (p - 1 >= n / 2 && n - i >= n / 2) { ws(1, p); ws(1, n); ws(i, n); ws(1, n); ws(1, p); swap(a[i], a[p]); pos[y] = p; pos[i] = i; } else if (n - p >= n / 2 && i - 1 >= n / 2) { ws(p, n); ws(1, n); ws(1, i); ws(1, n); ws(p, n); swap(a[i], a[p]); pos[y] = p; pos[i] = i; } else if (n - p >= n / 2 && n - i >= n / 2) { ws(p, n); ws(i, n); ws(p, n); swap(a[i], a[p]); pos[y] = p; pos[i] = i; } } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); ++i) { printf( %d %d n , ans[i].first, ans[i].second); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire myevent; // From test of Test.v
wire myevent_pending; // From test of Test.v
wire [1:0] state; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.state (state[1:0]),
.myevent (myevent),
.myevent_pending (myevent_pending),
// Inputs
.clk (clk),
.reset (reset));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, myevent_pending,myevent,state};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x me=%0x mep=%x\n", $time, cyc, crc, result, myevent, myevent_pending);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
reset <= (cyc<2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e93a74bd97b25ef
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
state, myevent, myevent_pending,
// Inputs
clk, reset
);
input clk;
input reset;
output [1:0] state;
output myevent;
output myevent_pending;
reg [5:0] count = 0;
always @ (posedge clk)
if (reset) count <= 0;
else count <= count + 1;
reg myevent = 1'b0;
always @ (posedge clk)
myevent <= (count == 6'd27);
reg myevent_done;
reg hickup_ready;
reg hickup_done;
localparam STATE_ZERO = 0;
localparam STATE_ONE = 1;
localparam STATE_TWO = 2;
reg [1:0] state = STATE_ZERO;
reg state_start_myevent = 1'b0;
reg state_start_hickup = 1'b0;
reg myevent_pending = 1'b0;
always @ (posedge clk) begin
state <= state;
myevent_pending <= myevent_pending || myevent;
state_start_myevent <= 1'b0;
state_start_hickup <= 1'b0;
case (state)
STATE_ZERO:
if (myevent_pending) begin
state <= STATE_ONE;
myevent_pending <= 1'b0;
state_start_myevent <= 1'b1;
end else if (hickup_ready) begin
state <= STATE_TWO;
state_start_hickup <= 1'b1;
end
STATE_ONE:
if (myevent_done)
state <= STATE_ZERO;
STATE_TWO:
if (hickup_done)
state <= STATE_ZERO;
default:
; /* do nothing */
endcase
end
reg [3:0] myevent_count = 0;
always @ (posedge clk)
if (state_start_myevent)
myevent_count <= 9;
else if (myevent_count > 0)
myevent_count <= myevent_count - 1;
initial myevent_done = 1'b0;
always @ (posedge clk)
myevent_done <= (myevent_count == 0);
reg [4:0] hickup_backlog = 2;
always @ (posedge clk)
if (state_start_myevent)
hickup_backlog <= hickup_backlog - 1;
else if (state_start_hickup)
hickup_backlog <= hickup_backlog + 1;
initial hickup_ready = 1'b1;
always @ (posedge clk)
hickup_ready <= (hickup_backlog < 3);
reg [3:0] hickup_count = 0;
always @ (posedge clk)
if (state_start_hickup)
hickup_count <= 10;
else if (hickup_count > 0)
hickup_count <= hickup_count - 1;
initial hickup_done = 1'b0;
always @ (posedge clk)
hickup_done <= (hickup_count == 1);
endmodule
|
#include <bits/stdc++.h> namespace chtholly { char buf[1 << 23], *p1 = buf, *p2 = buf; inline int read() { int x = 0, f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) f ^= c == - ; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + (c ^ 0 ); return f ? x : -x; } template <typename mitsuha> inline bool read(mitsuha &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c) && ~c; c = getchar()) f ^= c == - ; if (!~c) return 0; for (; isdigit(c); c = getchar()) x = (x << 3) + (x << 1) + (c ^ 0 ); return x = f ? x : -x, 1; } template <typename mitsuha> inline int write(mitsuha x) { if (!x) return 0 & putchar(48); if (x < 0) putchar( - ), x = -x; int bit[20], i, p = 0; for (; x; x /= 10) bit[++p] = x % 10; for (i = p; i; --i) putchar(bit[i] + 48); return 0; } inline char fuhao() { char c = getchar(); for (; isspace(c); c = getchar()) ; return c; } } // namespace chtholly using namespace chtholly; using namespace std; const int yuzu = 2e5, mod = 1e9 + 7; typedef long long rize[yuzu | 10]; rize a[115], jic = {1}, inv; namespace quick { long long kasumi(long long a, long long b = mod - 2) { long long s = 1; for (; b; b >>= 1, a = a * a % mod) if (b & 1) s = s * a % mod; return s; } void add(long long &a, long long b) { if ((a += b) >= mod) a -= mod; } void sub(long long &a, long long b) { if ((a -= b) < 0) a += mod; } long long zuhe(int n, int m) { return jic[n] * inv[m] % mod * inv[n - m] % mod; } } // namespace quick using namespace quick; void preget(int n, int i = 1) { for (; i <= n; ++i) jic[i] = jic[i - 1] * i % mod; inv[n] = kasumi(jic[n]); for (i = n - 1; ~i; --i) inv[i] = inv[i + 1] * (i + 1) % mod; } int main() { int i, j, n, m, l, r, k; read(n), read(m), preget(yuzu); static rize p; for (i = 1; i <= n; ++i) p[i] = read(); for (i = 1; i <= m; ++i) { l = read(), r = read(), k = read(); add(a[k][l], 1); for (j = 0; j <= k; ++j) sub(a[j][r + 1], zuhe(k - j + r - l, k - j)); } for (i = 100; ~i; --i) for (j = 1; j <= n; ++j) a[i][j] = (a[i][j] + a[i + 1][j] + a[i][j - 1]) % mod; for (i = 1; i <= n; ++i) write((a[0][i] + p[i]) % mod), putchar( ); }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); string s; cin >> s; int n = (int)s.size(); vector<vector<int>> a(26, vector<int>(n + 1)); for (int i = 1; i < n + 1; ++i) { a[s[i - 1] - a ][i] += 1; } for (int i = 0; i < 26; ++i) { for (int j = 1; j < n + 1; ++j) { a[i][j] += a[i][j - 1]; } } int q; cin >> q; while (q--) { int l, r; cin >> l >> r; if (l == r) { cout << Yes << n ; continue; } int cnt = 0; for (int i = 0; i < 26; ++i) { cnt += !!(a[i][r] - a[i][l - 1]); } if (cnt == 1) { cout << No << n ; continue; } if (cnt == 2) { cout << (s[l - 1] == s[r - 1] ? No : Yes ) << n ; continue; } cout << Yes << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c; cin >> a >> b >> c; long long d; d = min(a, b) * 2 + c * 2; if (a != b) { d++; } cout << d; }
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:09:17 06/06/2009
// Design Name:
// Module Name: RCB_FRL_COUNT_TO_64
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_COUNT_TO_64(clk, rst, count, ud, counter_value);
//This module counts up/down between 0 to 63
input clk, rst, count, ud;
output [5:0] counter_value;
wire [5:0] counter_value_preserver;
reg [5:0] counter_value/*synthesis syn_noprune = 1*/;
always@(posedge clk or posedge rst)
begin
if(rst == 1'b1)
counter_value = 6'h00;
else
begin
case({count,ud})
2'b00: counter_value = counter_value_preserver;
2'b01: counter_value = counter_value_preserver;
2'b10: counter_value = counter_value_preserver - 1;
2'b11: counter_value = counter_value_preserver + 1;
default: counter_value = 6'h00;
endcase
end
end
assign counter_value_preserver = counter_value;
endmodule
|
#include <bits/stdc++.h> int GCD(int u, int v) { while (v != 0) { int r = u % v; u = v; v = r; } return u; } int main() { int amtV; int amtE; std::vector<std::pair<int, int>> graph; std::cin >> amtV >> amtE; int connected = 0; int remaining = amtE; if (amtE >= amtV - 1) { for (int i = 2; i <= amtV; i++) { graph.push_back(std::pair<int, int>(i, 1)); } remaining = amtE - (amtV - 1); for (int i = 3; i <= amtV; i += 2) { if (remaining == 0) break; graph.push_back(std::pair<int, int>(i, 2)); remaining--; } int currInd = 3; int currCompare; while (remaining > 0 && currInd < amtV) { currCompare = currInd + 1; while (remaining > 0 && currCompare <= amtV) { if (GCD(currInd, currCompare) == 1) { graph.push_back(std::pair<int, int>(currInd, currCompare)); remaining--; } currCompare++; } currInd++; } } if (remaining == 0) { std::cout << Possible << std::endl; for (auto it = graph.begin(); it != graph.end(); it++) { std::cout << it->first << << it->second << std::endl; } } else { std::cout << Impossible << std::endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; string onezero(int n) { string s = 1 ; for (int i = 1; i < n; ++i) { s += 0 ; } return s; } string findSum(string str1, string str2) { if (str1.length() > str2.length()) swap(str1, str2); string str = ; int n1 = str1.length(), n2 = str2.length(); reverse(str1.begin(), str1.end()); reverse(str2.begin(), str2.end()); int carry = 0; for (int i = 0; i < n1; i++) { int sum = ((str1[i] - 0 ) + (str2[i] - 0 ) + carry); str.push_back(sum % 10 + 0 ); carry = sum / 10; } for (int i = n1; i < n2; i++) { int sum = ((str2[i] - 0 ) + carry); str.push_back(sum % 10 + 0 ); carry = sum / 10; } if (carry) str.push_back(carry + 0 ); reverse(str.begin(), str.end()); return str; } int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); int l; string s, ans; cin >> l >> s; if (s.size() % l != 0) { string zero = onezero(l); for (int i = 0; i < s.size() / l + 1; ++i) { ans += zero; } } else { string temp = s.substr(0, l); for (int i = 0; i < s.size() / l; ++i) { ans += temp; } if (ans <= s) { ans = ; temp = findSum(temp, 1 ); if (temp.size() != l) { temp = onezero(l); ans = onezero(l); } for (int i = 0; i < s.size() / l; ++i) { ans += temp; } } } cout << ans << endl; }
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg2_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bg2_new (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bg2-new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bg2-new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg2_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAN = 110; const int MAM = 60; int dp[MAN][MAM][2]; int INF = -100000000; int main() { string str; int m; while (cin >> str >> m) { int len = str.size(); memset(dp, 0, sizeof(dp)); for (int i = 0; i <= len; ++i) { for (int j = 0; j <= m; ++j) { dp[i][j][0] = INF; dp[i][j][1] = INF; } } dp[0][0][0] = 0; dp[0][0][1] = 0; for (int i = 1; i <= len; ++i) { for (int j = 0; j <= m; ++j) { if (str[i - 1] == F ) { dp[i][j][0] = max(dp[i - 1][j][0] != INF ? dp[i - 1][j][0] + 1 : INF, j > 0 ? dp[i - 1][j - 1][1] : INF); dp[i][j][1] = max(dp[i - 1][j][1] != INF ? dp[i - 1][j][1] - 1 : INF, j > 0 ? dp[i - 1][j - 1][0] : INF); } else { dp[i][j][0] = max(dp[i - 1][j][1], (j > 0 && dp[i - 1][j - 1][0] != INF) ? dp[i - 1][j - 1][0] + 1 : INF); dp[i][j][1] = max(dp[i - 1][j][0], (j > 0 && dp[i - 1][j - 1][1] != INF) ? dp[i - 1][j - 1][1] - 1 : INF); } } } int ans = INF; for (int i = m; i >= 0; i -= 2) { ans = max(ans, max(dp[len][i][0], dp[len][i][1])); } cout << ans << endl; } return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N8_M8_P6
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GDA_St_N8_M8_P6(
input [7:0] in1,
input [7:0] in2,
output [8:0] res
);
wire [2:0] temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;
wire p0,p1,p2,p3,p4,p5,p6,g0,g1,g2,g3,g4,g5,g6,c1,c2,c3,c4,c5,c6,c7;
wire p1c1,p2c2,p3c3,p4c4,p5c5,p6c6,p2p1c1,p3p2c2,p4p3c3,p5p4c4,p6p5c5,p3p2p1c1,p4p3p2c2,p4p3p2p1c1,p5p4p3c3,p5p4p3p2c2,p5p4p3p2p1c1;
wire p6p5p4c4,p6p5p4p3c3,p6p5p4p3p2c2;
wire carry_pred_1,carry_pred_2,carry_pred_3,carry_pred_4,carry_pred_5,carry_pred_6;
wire carry_pred_2_1;
wire carry_pred_3_1,carry_pred_3_2;
wire carry_pred_4_1,carry_pred_4_2,carry_pred_4_3;
wire carry_pred_5_1,carry_pred_5_2,carry_pred_5_3,carry_pred_5_4;
wire carry_pred_6_2,carry_pred_6_3,carry_pred_6_4,carry_pred_6_5;
and and_0(g0,in1[0],in2[0]);
and and_1(g1,in1[1],in2[1]);
and and_2(g2,in1[2],in2[2]);
and and_3(g3,in1[3],in2[3]);
and and_4(g4,in1[4],in2[4]);
and and_5(g5,in1[5],in2[5]);
and and_6(g6,in1[6],in2[6]);
xor xor_0(p0,in1[0],in2[0]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_4(p4,in1[4],in2[4]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_6(p6,in1[6],in2[6]);
assign c1 = g0;
assign c2 = g1;
and and_7(p1c1,p1,c1);
or or_0(carry_pred_1,c2,p1c1);
assign c3 = g2;
and and_8(p2c2,p2,c2);
and and_9(p2p1c1,p2,p1c1);
or or_1(carry_pred_2_1,p2c2,p2p1c1);
or or_2(carry_pred_2,c3,carry_pred_2_1);
assign c4 = g3;
and and_10(p3c3,p3,c3);
and and_11(p3p2c2,p3,p2c2);
and and_12(p3p2p1c1,p3,p2p1c1);
or or_3(carry_pred_3_1,p3p2c2,p3p2p1c1);
or or_4(carry_pred_3_2,p3c3,carry_pred_3_1);
or or_5(carry_pred_3,c4,carry_pred_3_2);
assign c5 = g4;
and and_13(p4c4,p4,c4);
and and_14(p4p3c3,p4,p3c3);
and and_15(p4p3p2c2,p4,p3p2c2);
and and_16(p4p3p2p1c1,p4,p3p2p1c1);
or or_6(carry_pred_4_1,p4p3p2c2,p4p3p2p1c1);
or or_7(carry_pred_4_2,p4p3c3,carry_pred_4_1);
or or_8(carry_pred_4_3,p4c4,carry_pred_4_2);
or or_9(carry_pred_4,c5,carry_pred_4_3);
assign c6 = g5;
and and_17(p5c5,p5,c5);
and and_18(p5p4c4,p5,p4c4);
and and_19(p5p4p3c3,p5,p4p3c3);
and and_20(p5p4p3p2c2,p5,p4p3p2c2);
and and_21(p5p4p3p2p1c1,p5,p4p3p2p1c1);
or or_10(carry_pred_5_1,p5p4p3p2c2,p5p4p3p2p1c1);
or or_11(carry_pred_5_2,p5p4p3c3,carry_pred_5_1);
or or_12(carry_pred_5_3,p5p4c4,carry_pred_5_2);
or or_13(carry_pred_5_4,p5c5,carry_pred_5_3);
or or_14(carry_pred_5,c6,carry_pred_5_4);
assign c7 = g6;
and and_22(p6c6,p6,c6);
and and_23(p6p5c5,p6,p5c5);
and and_24(p6p5p4c4,p6,p5p4c4);
and and_25(p6p5p4p3c3,p6,p5p4p3c3);
and and_26(p6p5p4p3p2c2,p6,p5p4p3p2c2);
or or_16(carry_pred_6_2,p6p5p4p3c3,p6p5p4p3p2c2);
or or_17(carry_pred_6_3,p6p5p4c4,carry_pred_6_2);
or or_18(carry_pred_6_4,p6p5c5,carry_pred_6_3);
or or_19(carry_pred_6_5,p6c6,carry_pred_6_4);
or or_20(carry_pred_6,c7,carry_pred_6_5);
// Results
assign temp1[1:0] = in1[0] + in2[0];
assign temp2[1:0] = in1[1] + in2[1] + c1;
assign temp3[1:0] = in1[2] + in2[2] + carry_pred_1;
assign temp4[1:0] = in1[3] + in2[3] + carry_pred_2;
assign temp5[1:0] = in1[4] + in2[4] + carry_pred_3;
assign temp6[1:0] = in1[5] + in2[5] + carry_pred_4;
assign temp7[1:0] = in1[6] + in2[6] + carry_pred_5;
assign temp8[1:0] = in1[7] + in2[7] + carry_pred_6;
assign res[8:0] = {temp8[1:0],temp7[0],temp6[0],temp5[0],temp4[0],temp3[0],temp2[0],temp1[0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 0; i < n; i++) { cout << 1 << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 4e4 + 44; const long long INF = 1e11 + 9; const double eps = 1e-12; int main() { int t; scanf( %d , &t); long long x1, y1, x2, y2, n, m; long long x3, y3, x4, y4; long long answ = 0, ansb = 0; while (t--) { scanf( %lld , &n); scanf( %lld , &m); if (n % 2 == 0 || m % 2 == 0) { answ = ansb = n * m / 2; } else { answ = (n * m) / 2 + 1; ansb = answ - 1; } scanf( %lld , &x1); scanf( %lld , &y1); scanf( %lld , &x2); scanf( %lld , &y2); long long dx = x2 - x1 + 1, dy = y2 - y1 + 1; if (dx % 2 == 0 || dy % 2 == 0) { answ += (dx * dy) / 2; ansb -= (dx * dy) / 2; } else { if (x1 % 2 && y1 % 2 || x1 % 2 == 0 && y1 % 2 == 0) { answ += (dx * dy) / 2; ansb -= (dx * dy) / 2; } else { answ += (dx * dy) / 2 + 1; ansb -= (dx * dy) / 2 + 1; } } scanf( %lld , &x3); scanf( %lld , &y3); scanf( %lld , &x4); scanf( %lld , &y4); dx = x4 - x3 + 1, dy = y4 - y3 + 1; if (dx % 2 == 0 || dy % 2 == 0) { answ -= (dx * dy) / 2; ansb += (dx * dy) / 2; } else { if (x3 % 2 && y3 % 2 || x3 % 2 == 0 && y3 % 2 == 0) { answ -= (dx * dy) / 2 + 1; ansb += (dx * dy) / 2 + 1; } else { answ -= (dx * dy) / 2; ansb += (dx * dy) / 2; } } long long x5, y5, x6, y6; if (y3 > y2 || y4 < y1 || x3 > x2 || x4 < x1) { printf( %lld %lld n , answ, ansb); continue; } x5 = max(x1, x3); y5 = max(y1, y3); x6 = min(x2, x4); y6 = min(y2, y4); dx = x6 - x5 + 1, dy = y6 - y5 + 1; if (dx % 2 == 0 || dy % 2 == 0) { if (x5 % 2 == 0 && y5 % 2 == 0 || x5 % 2 && y5 % 2) { answ -= dx * dy / 2; ansb += dx * dy / 2; } else { answ -= dx * dy / 2; ansb += dx * dy / 2; } } else { if (x5 % 2 && y5 % 2 || x5 % 2 == 0 && y5 % 2 == 0) { answ -= dx * dy / 2; ansb += dx * dy / 2; } else { answ -= dx * dy / 2 + 1; ansb += dx * dy / 2 + 1; } } printf( %lld %lld n , answ, ansb); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__mux2 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
S
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input S ;
// Local signals
wire u_mux_20_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (u_mux_20_out_X , A0, A1, S );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_20_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_BEHAVIORAL_PP_V
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#include <bits/stdc++.h> using namespace std; int n, m, s, d; vector<int> a; map<int, int> p, q; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m >> s >> d; a.resize(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); if (a[0] <= s) { cout << IMPOSSIBLE << endl; return 0; } p[a[0] - 1] = 0; for (int i = 0; i < n; ++i) { int next = a[i] + 1; if (binary_search(a.begin(), a.end(), next)) { continue; } int prev = next - d; auto pi = p.lower_bound(prev); if (pi == p.end()) { continue; } q[next] = pi->first; if (i < n - 1 && next + s < a[i + 1]) { p[a[i + 1] - 1] = next; } else { if (i == n - 1) { p[m] = next; } } } if (p.find(m) != p.end()) { int last = m; vector<pair<int, bool>> res; while (last != 0) { int prev = p[last]; if (prev < last) { res.push_back(make_pair(last - prev, true)); last = prev; } if (last > 0) { int prev_j = q[last]; res.push_back(make_pair(last - prev_j, false)); last = prev_j; } } reverse(res.begin(), res.end()); for (auto x : res) { if (x.second) { cout << RUN << x.first << n ; } else { cout << JUMP << x.first << n ; } } } else { cout << IMPOSSIBLE << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { long long w1, h1, w2, h2; cin >> w1 >> h1 >> w2 >> h2; cout << 2 * (w1 + h1 + h2) + 4 << endl; return 0; }
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#include <bits/stdc++.h> inline int A(int x, int y) { return x && y; } inline int O(int x, int y) { return x ^ y; } inline int X(int x, int y) { return x || y; } int main() { int t1, t2, t3, t4; scanf( %d%d%d%d , &t1, &t2, &t3, &t4); int a1 = O(t1, t2); int a2 = X(t3, t4); int a3 = A(t2, t3); int a4 = O(t1, t4); int b1 = A(a1, a2); int b2 = X(a3, a4); int c1 = O(b1, b2); printf( %d , c1); }
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#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 10; long long inf = 1e18; set<pair<long long, pair<int, int> > > s; vector<pair<pair<int, int>, long long> > vec; long long dp[2][maxn][maxn], arr[maxn][maxn]; long long ps[maxn][maxn]; int n, m, a, b; bool mark[maxn][maxn]; void input() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> m >> a >> b; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> arr[i][j]; } void cal_ps() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) ps[i + 1][j + 1] = ps[i][j + 1] + ps[i + 1][j] - ps[i][j] + arr[i][j]; } void cal_dp() { for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) dp[0][i][j] = dp[1][i][j] = inf; for (int j = 0; j < m; j++) { deque<int> dq; for (int i = 0; i < a; i++) { while (!dq.empty() && arr[dq.back()][j] >= arr[i][j]) dq.pop_back(); dq.push_back(i); } dp[0][a - 1][j] = arr[dq.front()][j]; for (int i = a; i < n; i++) { while (!dq.empty() && arr[dq.back()][j] >= arr[i][j]) dq.pop_back(); dq.push_back(i); if (dq.front() == i - a) dq.pop_front(); dp[0][i][j] = arr[dq.front()][j]; } } for (int i = 0; i < n; i++) { deque<int> dq; for (int j = 0; j < b; j++) { while (!dq.empty() && dp[0][i][dq.back()] >= dp[0][i][j]) dq.pop_back(); dq.push_back(j); } dp[1][i][b - 1] = dp[0][i][dq.front()]; for (int j = b; j < m; j++) { while (!dq.empty() && dp[0][i][dq.back()] >= dp[0][i][j]) dq.pop_back(); dq.push_back(j); if (dq.front() == j - b) dq.pop_front(); dp[1][i][j] = dp[0][i][dq.front()]; } } } void init() { for (int i = a - 1; i < n; i++) for (int j = b - 1; j < m; j++) { long long sum = ps[i + 1][j + 1] - ps[i + 1][j + 1 - b] - ps[i + 1 - a][j + 1] + ps[i + 1 - a][j + 1 - b] - a * b * dp[1][i][j]; s.insert({sum, {i - a + 1, j - b + 1}}); } } bool valid(int x, int y) { if (mark[x][y]) return false; int xx = max(0, x - a + 1), yy = max(0, y - b + 1); for (int i = x + a - 1; i >= xx; i--) for (int j = y + b - 1; j >= yy; j--) mark[i][j] = true; return true; } int main() { input(); cal_ps(); cal_dp(); init(); while (!s.empty()) { auto tmp = *s.begin(); int x = tmp.second.first, y = tmp.second.second; long long p = tmp.first; if (valid(x, y)) vec.push_back({{x, y}, p}); s.erase(tmp); } cout << vec.size() << n ; for (auto tmp : vec) { cout << tmp.first.first + 1 << << tmp.first.second + 1 << << tmp.second << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, a[N], to[N]; vector<int> idx[N]; int is[N]; bool ok() { for (int i = 0; i < n; ++i) is[a[i]] ^= 1; bool prv = 0; for (int i = 1; i <= n; ++i) { if (!is[i]) continue; if (prv) return 0; prv = 1; } return 1; } bool plind() { for (int i = 0; i * 2 + 1 < n; ++i) if (a[i] != a[n - i - 1]) return 0; return 1; } bool vis[N]; int main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , a + i); idx[a[i]].push_back(i); } if (!ok()) return cout << 0, 0; if (plind()) return cout << 1ll * n * (n + 1) / 2, 0; int indx = n / 2; for (int i = 1; i <= n; ++i) { for (int j = 0; j * 2 + 1 < idx[i].size(); ++j) { to[idx[i][j]] = idx[i][idx[i].size() - j - 1]; to[idx[i][idx[i].size() - j - 1]] = idx[i][j]; } if (idx[i].size() % 2 == 0) continue; indx = idx[i][idx[i].size() / 2]; to[idx[i][idx[i].size() / 2]] = n / 2; } for (int i = 0; i < n; ++i) if (to[i] == n - i - 1) vis[i] = 1; int prel = 0; while (a[prel] == a[n - prel - 1]) ++prel; int prer = prel; if (n % 2 && indx != n / 2) prer = max(prer, indx); if (n % 2 && indx == n / 2) vis[n / 2] = 1; for (int i = n - 1; i >= 0; --i) if (to[i] >= 0 && !vis[i]) { prer = max(prer, to[i]); vis[to[i]] = 1; } long long ans = 1ll * (prel + 1) * (n - prer); int sufr = n - 1; while (a[sufr] == a[n - sufr - 1]) --sufr; int sufl = sufr; if (n % 2 && indx != n / 2) sufl = min(sufl, indx); memset(vis, 0, sizeof vis); if (n % 2 && indx == n / 2) vis[n / 2] = 1; for (int i = 0; i < n; ++i) if (to[i] == n - i - 1) vis[i] = 1; for (int i = 0; i < n; ++i) if (to[i] >= 0 && !vis[i]) { sufl = min(sufl, to[i]); vis[to[i]] = 1; } if (sufl <= prel) return cout << ans, 0; ans += 1ll * (n - sufr) * (sufl - prel); cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<long long> v; void SieveOfEratosthenes(long long n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } for (long long p = 2; p <= n; p++) if (prime[p]) v.push_back(p); } signed main() { long long n; cin >> n; SieveOfEratosthenes(n); long long m = v.size(); vector<long long> ans; long long ct = 0; for (long long i = 0; i < m; i++) { long long p = v[i]; while (p <= n) { ct++; ans.push_back(p); p = p * v[i]; } } cout << ct << n ; long long k = ans.size(); for (long long i = 0; i < k; i++) { cout << ans[i] << ; } }
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#include <bits/stdc++.h> using namespace std; int main() { long int quant, mul; scanf( %ld %ld , &quant, &mul); long int *nums = (long int *)calloc(quant, sizeof(long int)); set<long int> s; for (long int i = 0; i < quant; i++) { scanf( %ld , &nums[i]); } sort(nums, nums + quant); for (long int i = 0; i < quant; i++) { if (nums[i] % mul != 0 || s.count(nums[i] / mul) == 0) { s.insert(nums[i]); } } printf( %ld n , s.size()); free(nums); return 0; }
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#include <bits/stdc++.h> const double PI = 3.1415926535897932384626433; const int KL = 1e5 + 10; const long long MOD = 1e9 + 7; using namespace std; struct point { long double x, y; void go(long long x1, long long y1) { x = x1; y = y1; } void read() { cin >> x >> y; } point operator-(point b) { return point{x - b.x, y - b.y}; } point operator+(point b) { return point{x + b.x, y + b.y}; } }; long double fnd_angle(point p) { long double len = sqrt(p.x * p.x + p.y * p.y); long double angle = acos(fabs(p.x) / len); if (p.y < 0) { if (p.x >= 0) angle = 2 * PI - angle; else angle += PI; } else if (p.x < 0) angle = PI - angle; return angle; } int n, k; vector<point> A; vector<pair<long double, long double>> a, b; multiset<long double> s; bool ok(long double mid) { if (k <= 0) return 1; a.clear(); b.clear(); for (int i = 0; i < n; i++) { long double dis = sqrt(A[i].x * A[i].x + A[i].y * A[i].y); if (dis > 2 * mid) continue; long double angle = fnd_angle(A[i]); long double angle2 = acos(dis / (2.0 * mid)); a.push_back({angle - angle2, 2 * angle2}); b.push_back({angle + angle2, -2.0 * angle2}); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); reverse(b.begin(), b.end()); int sz = a.size(); for (int i = 0; i < sz; i++) a.push_back({a[i].first + 2 * PI, a[i].second}); for (int i = 0; i < sz; i++) b.push_back({b[i].first - 2 * PI, b[i].second}); int mx = 0; s.clear(); for (int i = 0; i < a.size(); i++) { while (s.size() > 0 && *s.begin() < a[i].first) s.erase(s.begin()); if (s.size() + 1 >= k) return 1; s.insert(a[i].first + a[i].second); } s.clear(); for (int i = 0; i < b.size(); i++) { while (s.size() > 0 && *(--s.end()) > b[i].first) s.erase(--s.end()); if (s.size() + 1 >= k) return 1; s.insert(b[i].first + b[i].second); } return 0; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) { point pp; pp.read(); if (pp.x == 0 && pp.y == 0) { k--; continue; } A.push_back(pp); } n = A.size(); long double lo = 0.0, hi = 2e5; int cnt = 33; while (cnt--) { long double mid = (lo + hi) / 2.0; if (ok(mid)) hi = mid; else lo = mid; } cout << fixed << setprecision(8) << lo << n ; return 0; }
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/*
* Titor - System - Simulation testbench
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_TESTBED
`else
`define INC_TESTBED
`timescale 1 ns / 100 ps
module testbed();
`include "definition/Definition.v"
reg CLK_50MHZ;
reg BTN_SOUTH;
Core_Test mut(
.CLK_50MHZ (CLK_50MHZ),
.BTN_SOUTH (BTN_SOUTH)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0,mut);
BTN_SOUTH <= 1;
CLK_50MHZ <= 0; #100;
CLK_50MHZ <= 1; #100;
BTN_SOUTH <= 0;
while(1'b1) begin
CLK_50MHZ <= 0; # 100;
CLK_50MHZ <= 1; # 100;
end
end
endmodule
`endif
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, temp; cin >> n; map<int, int> a, b; for (int i = 0; i < n; i++) { cin >> temp; a[temp]++; } for (int i = 0; i < n; i++) { cin >> temp; b[temp]++; } int ans = 0, sum = 0; vector<int> bal(6); for (int i = 1; i < 6; i++) { if ((a[i] + b[i]) % 2) { cout << -1; return 0; } bal[i] = a[i] - b[i]; bal[i] /= 2; sum += bal[i]; if (bal[i] > 0) ans += bal[i]; } if (sum) { cout << -1; return 0; } cout << abs(ans); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a; vector<vector<int> > gr(n + 1, a); int any; int th; for (int i = 1; i <= n; i++) { cin >> th; if (th != 0) { gr[i].push_back(th); gr[th].push_back(i); } } vector<int> chet(n + 1, 0); for (int i = 1; i <= n; i++) { if (gr[i].size() % 2 == 0) { chet[i] = 1; any = i; } } if (n % 2 == 0) { cout << NO ; } else { cout << YES n ; queue<int> q; q.push(any); vector<int> dist(n + 1, 0); vector<int> bfu(n + 1, 0); vector<int> pred(n + 1, 0); vector<vector<int> > next(n + 1, a); bfu[any] = 1; pred[any] = -1; while (q.size() != 0) { int v = q.front(); q.pop(); for (int i = 0; i < gr[v].size(); i++) { if (bfu[gr[v][i]] == 0) { pred[gr[v][i]] = v; q.push(gr[v][i]); bfu[gr[v][i]] = 1; next[v].push_back(gr[v][i]); dist[gr[v][i]] = dist[v] + 1; } } } vector<int> ans; int maxd = dist[max_element(dist.begin(), dist.end()) - dist.begin()]; vector<int> ansu(n + 1, 0); set<int> sss; vector<set<int> > ch(maxd + 1, sss); for (int i = 1; i <= n; i++) { if (chet[i] == 1) { ch[dist[i]].insert(i); } } for (int i = ch.size() - 1; i >= 0; i--) { for (auto j : ch[i]) { queue<int> qq; qq.push(j); if (i != 0) { if (ch[i - 1].find(pred[j]) != ch[i - 1].end()) { ch[i - 1].erase(pred[j]); } else { ch[i - 1].insert(pred[j]); } } while (qq.size() != 0) { int v = qq.front(); qq.pop(); if (ansu[v] == 0) { cout << v << n ; ansu[v] = 1; for (int jj = 0; jj < next[v].size(); jj++) { qq.push(next[v][jj]); } } } } } } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11,
o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp_eth_rx
*/
module test_arp_eth_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_frame_ready = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire m_frame_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [15:0] m_arp_htype;
wire [15:0] m_arp_ptype;
wire [7:0] m_arp_hlen;
wire [7:0] m_arp_plen;
wire [15:0] m_arp_oper;
wire [47:0] m_arp_sha;
wire [31:0] m_arp_spa;
wire [47:0] m_arp_tha;
wire [31:0] m_arp_tpa;
wire busy;
wire error_header_early_termination;
wire error_invalid_header;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_frame_ready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_frame_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_arp_htype,
m_arp_ptype,
m_arp_hlen,
m_arp_plen,
m_arp_oper,
m_arp_sha,
m_arp_spa,
m_arp_tha,
m_arp_tpa,
busy,
error_header_early_termination,
error_invalid_header
);
// dump file
$dumpfile("test_arp_eth_rx_64.lxt");
$dumpvars(0, test_arp_eth_rx_64);
end
arp_eth_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// ARP frame output
.m_frame_valid(m_frame_valid),
.m_frame_ready(m_frame_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_arp_htype(m_arp_htype),
.m_arp_ptype(m_arp_ptype),
.m_arp_hlen(m_arp_hlen),
.m_arp_plen(m_arp_plen),
.m_arp_oper(m_arp_oper),
.m_arp_sha(m_arp_sha),
.m_arp_spa(m_arp_spa),
.m_arp_tha(m_arp_tha),
.m_arp_tpa(m_arp_tpa),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination),
.error_invalid_header(error_invalid_header)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); const int N = 100010; int n; long long x, y, a[N]; void solve() { for (int i = 0; i < (int)(n); ++i) a[i] = 1; a[0] = y - n + 1; for (int i = 0; i < (int)(n); ++i) x -= ((a[i]) * (a[i])); if (y < n || x > 0) puts( -1 ); else { for (int i = 0; i < (int)(n); ++i) printf( %I64d n , a[i]); } } int main() { while ( ~scanf( %d %I64d %I64d , &n, &x, &y)) { solve(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0N_1_V
`define SKY130_FD_SC_HDLL__INPUTISO0N_1_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog wrapper for inputiso0n with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso0n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso0n_1 (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso0n_1 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inputiso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0N_1_V
|
#include <bits/stdc++.h> const int maxn = (int)1e6; const int mod = (int)1e9 + 7; using namespace std; int n; long long dp[maxn]; long long a[maxn]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { cin >> a[i]; } dp[0] = abs(a[0]); for (int i = 1; i < n; i++) { dp[i] = abs(a[i] - a[i - 1]) + dp[i - 1]; } cout << dp[n - 1]; return 0; }
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [3:0] test;
initial begin
/* A zero count repeat by it self is not allowed by the standard,
test = {0{1'b1}};
if (test !== 4'b0000) begin
$display("FAILED -- {0{1'b1} == %b", test);
$finish;
end
but it can be used in a valid concatenation (1364-2005). */
test = {{0{1'b1}}, 1'b0};
if (test !== 4'b0000) begin
$display("FAILED -- {0{1'b1} == %b", test);
$finish;
end
test = {1{1'b1}};
if (test !== 4'b0001) begin
$display("FAILED -- {1{1'b1} == %b", test);
$finish;
end
test = {2{1'b1}};
if (test !== 4'b0011) begin
$display("FAILED -- {2{1'b1} == %b", test);
$finish;
end
test = {3{1'b1}};
if (test !== 4'b0111) begin
$display("FAILED -- {3{1'b1} == %b", test);
$finish;
end
test = {4{1'b1}};
if (test !== 4'b1111) begin
$display("FAILED -- {4{1'b1} == %b", test);
$finish;
end
test = {5{1'b1}};
if (test !== 4'b1111) begin
$display("FAILED -- {5{1'b1} == %b", test);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Avalon MM Slave for parallel input/output camera registers
//
module avalon_camera (
// Avalon clock interface signals
input clk,
input reset_n,
// Signals for Avalon-MM slave port
input [4:0] avs_s1_address,
input avs_s1_read,
output reg [31:0] avs_s1_readdata,
input avs_s1_write,
input [31:0] avs_s1_writedata,
// Control signals to export to the image_capture
output avs_export_start_capture,
output [23:0] avs_export_capture_imgsize,
output [31:0] avs_export_buff,
input avs_export_image_captured,
input avs_export_capture_standby,
// Registers to export to the camera_config
output [15:0] avs_export_width,
output [15:0] avs_export_height,
output [15:0] avs_export_start_row,
output [15:0] avs_export_start_column,
output [15:0] avs_export_row_size,
output [15:0] avs_export_column_size,
output [15:0] avs_export_row_mode,
output [15:0] avs_export_column_mode,
output [15:0] avs_export_exposure,
//soft reset
output avs_export_cam_soft_reset_n
);
// Addresses of the registers to control image_capture
`define ADDR_START_CAPTURE 5'h00
`define ADDR_CAPTURE_IMGSIZE 5'h01
`define ADDR_BUFF 5'h02
`define ADDR_IMGCAPTURED 5'h03
`define ADDR_CAPTURE_STANDBY 5'h04
// Addresses of the registers to control camera_config
`define ADDR_WIDTH 5'h09
`define ADDR_HEIGHT 5'h0a
`define ADDR_START_ROW 5'h0b
`define ADDR_START_COLUMN 5'h0c
`define ADDR_ROW_SIZE 5'h0d
`define ADDR_COLUMN_SIZE 5'h0e
`define ADDR_ROW_MODE 5'h0f
`define ADDR_COLUMN_MODE 5'h10
`define ADDR_EXPOSURE 5'h11
// Address of the soft reset
`define SOFT_RESET_N 5'h1F //last address
// Camera configuration registers default values.
parameter WIDTH = 16'd320;
parameter HEIGHT = 16'd240;
parameter START_ROW = 16'h0036;
parameter START_COLUMN = 16'h0010;
parameter ROW_SIZE = 16'h059f;
parameter COLUMN_SIZE = 16'h077f;
parameter ROW_MODE = 16'h0002;
parameter COLUMN_MODE = 16'h0002;
parameter EXPOSURE = 16'h07c0;
// image_capture registers
reg start_capture;
reg [23:0] capture_imgsize;
reg [31:0] buff;
reg imgcaptured;
wire standby;
// camera_config registers
reg [15:0] data_width;
reg [15:0] data_height;
reg [15:0] data_start_row;
reg [15:0] data_start_column;
reg [15:0] data_row_size;
reg [15:0] data_column_size;
reg [15:0] data_row_mode;
reg [15:0] data_column_mode;
reg [15:0] data_exposure;
//soft_reset reg
reg cam_soft_reset_n;
// Read/Write registers
always @(posedge clk or negedge reset_n)
begin
if (!reset_n) begin
start_capture <= 1'b0;
capture_imgsize <= 24'd0;
buff[31:0] <= 32'd0;
data_width[15:0] <= WIDTH[15:0];
data_height[15:0] <= HEIGHT[15:0];
data_start_row[15:0] <= START_ROW[15:0];
data_start_column[15:0] <= START_COLUMN[15:0];
data_row_size[15:0] <= ROW_SIZE[15:0];
data_column_size[15:0] <= COLUMN_SIZE[15:0];
data_row_mode[15:0] <= ROW_MODE[15:0];
data_column_mode[15:0] <= COLUMN_MODE[15:0];
data_exposure[15:0] <= EXPOSURE[15:0];
cam_soft_reset_n <= 1;
end
else begin
if (avs_s1_read) begin
case (avs_s1_address)
// image_capture
`ADDR_START_CAPTURE:
avs_s1_readdata[31:0] <= {31'b0, start_capture};
`ADDR_CAPTURE_IMGSIZE:
avs_s1_readdata[31:0] <= {8'b0, capture_imgsize};
`ADDR_BUFF:
avs_s1_readdata[31:0] <= buff;
`ADDR_IMGCAPTURED:
avs_s1_readdata[31:0] <= {31'b0, imgcaptured};
`ADDR_CAPTURE_STANDBY:
avs_s1_readdata[31:0] <= {31'b0, standby};
// camera_config
`ADDR_WIDTH:
avs_s1_readdata[15:0] <= data_width[15:0];
`ADDR_HEIGHT:
avs_s1_readdata[15:0] <= data_height[15:0];
`ADDR_START_ROW:
avs_s1_readdata[15:0] <= data_start_row[15:0];
`ADDR_START_COLUMN:
avs_s1_readdata[15:0] <= data_start_column[15:0];
`ADDR_ROW_SIZE:
avs_s1_readdata[15:0] <= data_row_size[15:0];
`ADDR_COLUMN_SIZE:
avs_s1_readdata[15:0] <= data_column_size[15:0];
`ADDR_ROW_MODE:
avs_s1_readdata[15:0] <= data_row_mode[15:0];
`ADDR_COLUMN_MODE:
avs_s1_readdata[15:0] <= data_column_mode[15:0];
`ADDR_EXPOSURE:
avs_s1_readdata[15:0] <= data_exposure[15:0];
// soft reset
`SOFT_RESET_N:
avs_s1_readdata[31:0] <= {31'b0, cam_soft_reset_n};
default:
avs_s1_readdata[31:0] <= {32'b0};
endcase
end
// Routine when avs_s1_read is FALSE.
else begin
if (avs_s1_write) begin
case (avs_s1_address)
// image_capture
`ADDR_START_CAPTURE:
start_capture <= avs_s1_writedata[0];
`ADDR_CAPTURE_IMGSIZE:
capture_imgsize <= avs_s1_writedata[23:0];
`ADDR_BUFF:
buff <= avs_s1_writedata[31:0];
//`ADDR_CAPTURE_STANDBY://not writable
// camera_config
`ADDR_WIDTH:
data_width[15:0] <= avs_s1_writedata[15:0];
`ADDR_HEIGHT:
data_height[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_ROW:
data_start_row[15:0] <= avs_s1_writedata[15:0];
`ADDR_START_COLUMN:
data_start_column[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_SIZE:
data_row_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_SIZE:
data_column_size[15:0] <= avs_s1_writedata[15:0];
`ADDR_ROW_MODE:
data_row_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_COLUMN_MODE:
data_column_mode[15:0] <= avs_s1_writedata[15:0];
`ADDR_EXPOSURE:
data_exposure[15:0] <= avs_s1_writedata[15:0];
// soft reset
`SOFT_RESET_N:
cam_soft_reset_n <= avs_s1_writedata[0];
endcase
end
end
end
end
// imgcaptured registers
// This signals come from the capture_image component and may be clocked
// by a different clock. That is why asynchronous set is done here
// to set this signal. The processor uses this signals to know that
// one line has been captured and can read the buffer. The processor is
// in charge of erasing these signals through the avalon bus.
// The standby signal can also be used to know when a capture finished.
always @(posedge clk or negedge reset_n or posedge avs_export_image_captured)
begin
if (avs_export_image_captured)
imgcaptured <= 1'b1;
else if (!reset_n)
imgcaptured <= 1'b0;
else begin
if (avs_s1_write == 1) begin
case (avs_s1_address)
`ADDR_IMGCAPTURED: imgcaptured <= avs_s1_writedata[0];
endcase
end
end
end
// Control signals to export to the image capture
assign avs_export_start_capture = start_capture;
assign avs_export_capture_imgsize = capture_imgsize;
assign avs_export_buff = buff;
assign standby = avs_export_capture_standby;
// Registers to export to the camera_config
assign avs_export_start_row[15:0] = data_start_row[15:0];
assign avs_export_start_column[15:0] = data_start_column[15:0];
assign avs_export_row_size[15:0] = data_row_size[15:0];
assign avs_export_column_size[15:0] = data_column_size[15:0];
assign avs_export_row_mode[15:0] = data_row_mode[15:0];
assign avs_export_column_mode[15:0] = data_column_mode[15:0];
assign avs_export_exposure[15:0] = data_exposure[15:0];
// Registers to export to the camera_config an
assign avs_export_width[15:0] = data_width[15:0];
assign avs_export_height[15:0] = data_height[15:0];
//soft reset
assign avs_export_cam_soft_reset_n = cam_soft_reset_n;
endmodule
|
module mojo_com_logic #(
parameter ADDR_SPACE = 256
)(
input clk,
input rst,
//SPI Addressing Interface
input [ADDR_SPACE_BITS-1:0] reg_addr,
input write,
input new_req,
input [7:0] write_value,
output [7:0] read_value,
input in_transaction,
//Interface, doesn't guarantee atomicity
output [8*ADDR_SPACE-1:0] rx_arr,
output rx_busy,
output new_rx,
input [8*ADDR_SPACE-1:0] tx_arr,
output tx_busy
//DEBUG params
/*
, output [ADDR_BIT_COUNT - 1:0] cur_addr,
output [ADDR_BIT_COUNT - 1:0] end_addr,
output [STATE_SIZE - 1:0] cur_state
*/
);
parameter ADDR_SPACE_BITS = $clog2(ADDR_SPACE);
parameter WORD_SIZE = 8;
parameter ADDR_BITS = ADDR_SPACE * 8; //Number of bits in addressable arrs
parameter ADDR_BIT_COUNT = $clog2(ADDR_BITS); //Number of bits to address all bits
//Interface setup
reg [ADDR_BITS-1:0] rx_arr_q, rx_arr_d;
reg rx_busy_q, rx_busy_d, tx_busy_q, tx_busy_d, new_rx_q, new_rx_d;
assign rx_arr = rx_arr_q;
assign rx_busy = rx_busy_q;
assign new_rx = new_rx_q;
assign tx_busy = tx_busy_q;
//SPI addressing setup
reg [7:0] read_value_d, read_value_q;
assign read_value = read_value_q;
//Other stuff
reg old_write_d, old_write_q, old_transaction_d, old_transaction_q;
always @(*) begin
read_value_d = read_value_q;
old_write_d = old_write_q;
old_transaction_d = in_transaction;
rx_busy_d = in_transaction;
tx_busy_d = in_transaction;
new_rx_d = new_rx_q;
rx_arr_d = rx_arr_q;
if (new_req) begin
//Read by default
read_value_d = tx_arr[{reg_addr,3'b0}+:WORD_SIZE];
//Write in certain cases
if (write) begin
rx_arr_d[{reg_addr,3'b0}+:WORD_SIZE] = write_value;
end
end
if (in_transaction) begin
old_write_d = write;
end else begin
//Falling edge of transaction and was written
new_rx_d = old_transaction_q & old_write_q;
end
end
always @(posedge clk) begin
if (rst) begin
read_value_q <= 0;
rx_busy_q <= 0;
tx_busy_q <= 0;
new_rx_q <= 0;
rx_arr_q <= 0;
old_write_q <= 0;
old_transaction_q <= 0;
end else begin
read_value_q <= read_value_d;
rx_busy_q <= rx_busy_d;
tx_busy_q <= tx_busy_d;
new_rx_q <= new_rx_d;
rx_arr_q <= rx_arr_d;
old_write_q <= old_write_d;
old_transaction_q <= old_transaction_d;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y, m, aux, rs = 0; void neg() { rs = (-y) / x; rs++; y = y + rs * x; } void rec() { aux = x + y; rs++; if (aux < m) { y = x; x = aux; rec(); } } int main() { cin >> x >> y >> m; aux = max(x, y); y = min(x, y); x = aux; if (x >= m) { cout << 0 << endl; return 0; } if (x < 1) { cout << -1 << endl; return 0; } if (y < 1 && x > 0) { neg(); } rec(); cout << rs << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int testCases = 1; cin >> testCases; while (testCases--) { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } if (n % 2 == 0) { for (int i = 0; i < n; i += 2) { cout << a[i + 1] << << -a[i] << ; } } else { for (int i = 0; i < n - 3; i += 2) { cout << a[i + 1] << << -a[i] << ; } if (a[n - 3] + a[n - 2] != 0) { cout << a[n - 1] << << a[n - 1] << << -(a[n - 3] + a[n - 2]); } else if (a[n - 2] + a[n - 1] != 0) { cout << -(a[n - 2] + a[n - 1]) << << a[n - 3] << << a[n - 3]; } else { cout << a[n - 2] << << -(a[n - 1] + a[n - 3]) << << a[n - 2]; } } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, k; cin >> n >> k; string x; cin >> x; string ans = x; string y = ; long long p = n; for (long long i = 1; i < n; i++) { long long j; y = ; for (j = 0; i + j < n; j++) { if (x[i + j] != ans[j]) break; y += ans[j]; } if (i + j == n) { p = i; break; } } p = n - p; while (p--) { ans.erase(ans.begin()); } cout << x; while (--k) { cout << ans; } cout << endl; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int N, cn = 0, Z = 0, max = 0; cin >> N; int arr[N]; for (int i = 0; i < N; i++) { cin >> arr[i]; } for (int i = 0; i < N; i++) { cn = 0; for (int j = i + 1; j < N; j++) { if (arr[i] == arr[j] && arr[j] != 0) { cn++; arr[j] = 0; } } if (max <= cn) { max = cn; } if (cn >= 1) { Z += cn; } } cout << max + 1 << << N - Z; return 0; }
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_wrp_reg
(
input logic clock,
input logic resetn,
acl_ic_wrp_intf wrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_wrp_intf wrp_out
);
always @(posedge clock or negedge resetn)
if( ~resetn ) begin
wrp_out.ack <= 1'b0;
wrp_out.id <= 'x;
end
else begin
wrp_out.ack <= wrp_in.ack;
wrp_out.id <= wrp_in.id;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.1
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module filesystem_encrypbkb_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 128;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module filesystem_encrypbkb(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd128;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
filesystem_encrypbkb_ram filesystem_encrypbkb_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nand0_out ;
wire nand1_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_TB_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:33:40 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/fifo_generator_3_stub.v
// Design : fifo_generator_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *)
module fifo_generator_3(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[9:0],wr_en,rd_en,dout[9:0],full,empty" */;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [9:0]din;
input wr_en;
input rd_en;
output [9:0]dout;
output full;
output empty;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2lv_simple.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg LVPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__lsbufhv2lv_simple dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LVPWR(LVPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long MAXN = 810, maxn = 200010; long long n, m, k, top, cnt, num; struct wy { long long x, y, z; } t[maxn]; inline long long cmp(wy a, wy b) { return a.z < b.z; } long long b[MAXN], c[MAXN], a[MAXN][MAXN], w[maxn]; inline void discrete() { sort(b + 1, b + 1 + top); for (long long i = 1; i <= top; ++i) if (b[i] != b[i - 1]) c[++cnt] = b[i]; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (long long i = 1; i <= m; ++i) { long long x, y, z; cin >> x >> y >> z; t[i] = (wy){x, y, z}; } sort(t + 1, t + 1 + m, cmp); for (long long i = 1; i <= ((m) > (k) ? (k) : (m)); ++i) { b[++top] = t[i].x; b[++top] = t[i].y; } discrete(); for (long long i = 1; i <= cnt; ++i) for (long long j = 1; j <= cnt; ++j) a[i][j] = 20000000000000000ll; for (long long i = 1; i <= ((m) > (k) ? (k) : (m)); ++i) { long long x = lower_bound(c + 1, c + 1 + cnt, t[i].x) - c; long long y = lower_bound(c + 1, c + 1 + cnt, t[i].y) - c; a[y][x] = a[x][y] = t[i].z; } for (long long p = 1; p <= cnt; ++p) { for (long long i = 1; i <= cnt; ++i) for (long long j = 1; j <= cnt; ++j) { a[i][j] = ((a[i][j]) > (a[i][p] + a[p][j]) ? (a[i][p] + a[p][j]) : (a[i][j])); } } for (long long i = 1; i <= cnt; ++i) for (long long j = i + 1; j <= cnt; ++j) c[++num] = a[i][j]; sort(c + 1, c + 1 + num); printf( %lld , c[k]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long vis[200005], cnt[200005], arr[200005]; void solve() { long long i, j, k, l, m, n, x, sz = 0, flag = 1, mx = 0; cin >> n; for (i = 0; i <= n; i++) vis[i] = cnt[i] = 0; for (i = 0; i < n; i++) { cin >> arr[i]; cnt[arr[i]]++; if (cnt[arr[i]] == 2) sz = max(sz, arr[i]); mx = max(mx, arr[i]); if (cnt[arr[i]] == 3) flag = 0; } vector<long long> ans; if (sz + mx != n) flag = 0; if (!flag) { cout << 0 << endl; return; } for (i = 0; i < sz; i++) { vis[arr[i]] = 1; } flag = 1; for (i = 1; i <= sz; i++) { if (vis[i]) continue; else flag = 0; } if (flag) ans.push_back(sz); flag = 1; if (sz != mx) { for (i = 0; i <= mx; i++) vis[i] = 0; for (i = 0; i < mx; i++) { vis[arr[i]] = 1; } for (i = 1; i <= mx; i++) if (!vis[i]) flag = 0; if (flag) ans.push_back(mx); } cout << ans.size() << endl; for (i = 0; i < ans.size(); i++) { cout << ans[i] << << n - ans[i] << endl; } } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long t; t = 1; cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e5 + 5; int head[maxn], e[maxn << 1], nxt[maxn << 1], cnt = 1; void addedge(int u, int v) { e[++cnt] = v, nxt[cnt] = head[u], head[u] = cnt; e[++cnt] = u, nxt[cnt] = head[v], head[v] = cnt; } int s[maxn], t[maxn]; int f[maxn], num; int d[maxn]; int n, C = 2e5; void dfs(int u) { while (head[u] && f[head[u] >> 1]) head[u] = nxt[head[u]]; if (head[u]) { f[head[u] >> 1] = ++num; dfs(e[head[u]]); } } int main() { scanf( %d , &n); for (int i = 1, x, y; i <= n; i++) { scanf( %d%d , &x, &y); d[x]++, d[y + C]++; s[i] = x, t[i] = y + C; addedge(x, y + C); } int last, tot = 0; for (int i = 1; i <= 2 * C; i++) if (d[i] % 2) addedge(i, 2 * C + 1); dfs(2 * C + 1); for (int i = 1; i <= 2 * C; i++) dfs(i); memset(d, 0, sizeof(d)); for (int i = 1; i <= n; i++) { if (f[i] % 2) d[s[i]]++, d[t[i]]++; else d[s[i]]--, d[t[i]]--; } for (int i = 1; i <= 2 * C; i++) if (d[i] > 1 || d[i] < -1) { printf( shaleba n ); return 0; } for (int i = 1; i <= n; i++) { if (f[i] % 2) printf( r ); else printf( b ); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
// Very simple test for interface pathclearing
`ifdef VCS
`define UNSUPPORTED_MOD_IN_GENS
`endif
`ifdef VERILATOR
`define UNSUPPORTED_MOD_IN_GENS
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itopa();
ifc #(2) itopb();
sub #(1) ca (.isub(itopa),
.i_value(4));
sub #(2) cb (.isub(itopb),
.i_value(5));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (itopa.MODE != 1) $stop;
if (itopb.MODE != 2) $stop;
end
if (cyc==20) begin
if (itopa.get_value() != 4) $stop;
if (itopb.get_value() != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
#(parameter MODE = 0)
(
ifc.out_modport isub,
input integer i_value
);
`ifdef UNSUPPORTED_MOD_IN_GENS
always @* isub.value = i_value;
`else
generate if (MODE == 1) begin
always @* isub.valuea = i_value;
end
else if (MODE == 2) begin
always @* isub.valueb = i_value;
end
endgenerate
`endif
endmodule
interface ifc;
parameter MODE = 0;
// Modports under generates not supported by all commercial simulators
`ifdef UNSUPPORTED_MOD_IN_GENS
integer value;
modport out_modport (output value);
function integer get_value(); return value; endfunction
`else
generate if (MODE == 0) begin
integer valuea;
modport out_modport (output valuea);
function integer get_valuea(); return valuea; endfunction
end
else begin
integer valueb;
modport out_modport (output valueb);
function integer get_valueb(); return valueb; endfunction
end
endgenerate
`endif
endinterface
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long w, h, k, arr[4], brr[1000000], ans; cin >> w >> h; for (int i = 0; i < 4; i++) { cin >> k; for (int j = 0; j < k; j++) { cin >> brr[j]; } arr[i] = (brr[k - 1] - brr[0]); } arr[0] = max(arr[0], arr[1]); arr[2] = max(arr[2], arr[3]); ans = max(arr[0] * h, arr[2] * w); cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { long int mx = 0, n; cin >> n; vector<long int> vec; for (int i = 0; i < n; i++) { long int x; cin >> x; vec.push_back(x); } if (vec.size() == 1) { cout << 1 << endl; return 0; } for (int i = 0; i < n; i++) { long int len = 1, temp = vec[i]; for (int j = i + 1; j < n; j++) { if (vec[j] >= temp) { temp = vec[j]; len++; } else { break; } } mx = max(mx, len); } cout << mx << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int test; cin >> test; while (test--) { int n; cin >> n; string s; cin >> s; for (int i = 0; i < n; i++) { if (s[i] != ? ) { int j = i - 1; while (j >= 0 && s[j] == ? ) { if (s[j + 1] == R ) { s[j] = B ; } else { s[j] = R ; } j--; } } } reverse((s).begin(), (s).end()); for (int i = 0; i < n; i++) { if (s[i] != ? ) { int j = i - 1; while (j >= 0 && s[j] == ? ) { if (s[j + 1] == R ) { s[j] = B ; } else { s[j] = R ; } j--; } } } reverse((s).begin(), (s).end()); if (s[0] == ? ) { for (int i = 0; i < n; i++) { if (i % 2) { s[i] = R ; } else { s[i] = B ; } } } cout << s << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 510; bitset<510> can[maxn][2][64]; int N, M; long long ans, best[maxn][2]; inline long long dfs(int now, int last) { if (best[now][last ^ 1] != -1) return best[now][last ^ 1]; else best[now][last ^ 1] = 0; for (int i = 59; i >= 0; --i) if (can[now][last ^ 1][i].any()) { for (int j = 1; j <= N; ++j) if (can[now][last ^ 1][i][j]) best[now][last ^ 1] = max(dfs(j, last ^ 1) + (1LL << i), best[now][last ^ 1]); break; } return best[now][last ^ 1]; } int main() { scanf( %d %d , &N, &M); while (M--) { int a, b, c; scanf( %d %d %d , &a, &b, &c); can[a][c][0][b] = 1; } for (int i = 1; i <= 62; ++i) for (int j = 1; j <= N; ++j) for (int k = 0; k < 2; ++k) for (int l = 1; l <= N; ++l) { if (!can[j][k][i - 1][l]) continue; can[j][k][i] |= can[l][k ^ 1][i - 1]; } for (int i = 1; i <= N; ++i) if (can[i][0][60].any()) puts( -1 ), exit(0); memset(best, -1, sizeof(best)); for (int i = 1; i <= N; ++i) ans = max(ans, dfs(i, 1)); if (ans > 1000000000000000000LL) ans = -1; printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int b[5005], cnt, pr[800], f[800][5001], n, at[5005], sum[800][5001]; long long ans; int ss[5005], tmp[5005], sa, st; int main() { for (int i = 2; i <= 5000; i++) { if (b[i]) continue; for (int j = 2; j * i <= 5000; j++) b[i * j] = 1; } for (int i = 2; i <= 5000; i++) if (b[i] == 0) pr[++cnt] = i; for (int i = 1; i <= cnt; i++) { for (int j = 1; j <= 5000; j++) { if (j >= pr[i]) f[i][j] = j / pr[i] + f[i][j / pr[i]]; sum[i][j] = sum[i - 1][j] + f[i][j]; } } scanf( %d , &n); for (int i = 1, x; i <= n; i++) { scanf( %d , &x); if (x == 0) x = 1; ++at[x]; ans += sum[cnt][x]; } for (int i = 1; i <= 5000; i++) if (at[i]) ss[++sa] = i; for (int i = cnt; i >= 1;) { int s = 0, minn = 0x7fffffff; st = 0; for (int j = 1, a; j <= sa; j++) { a = ss[j]; if (f[i][a]) s += at[a], minn = min(minn, f[i][a]); } if (s > n - s) { ans -= 1ll * minn * (s - n + s); for (int j = 1, a; j <= sa; j++) { a = ss[j]; if (f[i][a]) f[i][a] -= minn, tmp[++st] = a; } for (int i = 1; i <= st; i++) ss[i] = tmp[i]; sa = st; } else if (n - s > s) { for (int j = 1, a; j <= sa; j++) { a = ss[j]; if (!f[i][a]) tmp[++st] = a; } for (int i = 1; i <= st; i++) ss[i] = tmp[i]; sa = st; --i; } else { break; } } printf( %lld , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, c; while (~scanf( %d %d %d %d , &n, &a, &b, &c)) { if (1 == n || n == 0) { printf( 0 n ); } else if (2 == n) { printf( %d n , min(a, b)); } else { if (c > max(a, b)) { printf( %d n , (n - 1) * min(a, b)); } else { if (c > min(a, b)) printf( %d n , (n - 1) * min(a, b)); else printf( %d n , min(a, b) + (n - 2) * c); } } } return 0; }
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/byte2wordsel.v:1" *)
module Byte2WordSel(H_i, L_i, Y_o, Shift_i, Mask_i);
wire [15:0] \$auto$splice.cc:141:get_spliced_signal$6 ;
(* src = "../../verilog/byte2wordsel.v:13" *)
wire [15:0] \$auto$splice.cc:237:run$7 ;
(* src = "../../verilog/byte2wordsel.v:15" *)
wire [31:0] \$sub$../../verilog/byte2wordsel.v:15$2_Y ;
(* src = "../../verilog/byte2wordsel.v:13" *)
wire [15:0] Concat;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/byte2wordsel.v:3" *)
input [7:0] H_i;
(* intersynth_conntype = "Byte" *)
(* src = "../../verilog/byte2wordsel.v:5" *)
input [7:0] L_i;
(* src = "../../verilog/byte2wordsel.v:15" *)
wire [15:0] Mask;
(* intersynth_config = 4 *)
(* src = "../../verilog/byte2wordsel.v:11" *)
input [3:0] Mask_i;
(* src = "../../verilog/byte2wordsel.v:16" *)
wire [15:0] Masked;
(* intersynth_config = 4 *)
(* src = "../../verilog/byte2wordsel.v:9" *)
input [3:0] Shift_i;
(* src = "../../verilog/byte2wordsel.v:14" *)
wire [15:0] Shifted;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/byte2wordsel.v:7" *)
output [15:0] Y_o;
(* src = "../../verilog/byte2wordsel.v:16" *)
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$and$../../verilog/byte2wordsel.v:16$4 (
.A(Shifted),
.B(Mask),
.Y(Y_o)
);
\$concat #(
.A_WIDTH(32'b00000000000000000000000000001000),
.B_WIDTH(32'b00000000000000000000000000001000)
) \$auto$splice.cc:135:get_spliced_signal$5 (
.A(L_i),
.B(H_i),
.Y(\$auto$splice.cc:141:get_spliced_signal$6 )
);
(* src = "../../verilog/byte2wordsel.v:14" *)
\$shr #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$shr$../../verilog/byte2wordsel.v:14$1 (
.A(\$auto$splice.cc:141:get_spliced_signal$6 ),
.B(Shift_i),
.Y(Shifted)
);
(* src = "../../verilog/byte2wordsel.v:15" *)
\$shr #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$shr$../../verilog/byte2wordsel.v:15$3 (
.A(16'b1111111111111111),
.B(\$sub$../../verilog/byte2wordsel.v:15$2_Y ),
.Y(Mask)
);
(* src = "../../verilog/byte2wordsel.v:15" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/byte2wordsel.v:15$2 (
.A(15),
.B(Mask_i),
.Y(\$sub$../../verilog/byte2wordsel.v:15$2_Y )
);
assign \$auto$splice.cc:237:run$7 = { H_i, L_i };
assign Masked = Y_o;
assign Concat = \$auto$splice.cc:141:get_spliced_signal$6 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int lim = sqrt(n) + 1; if (!(n & 1)) { cout << n / 2 << endl; return 0; } for (long long int i = 3; i <= lim + 1; i++) { if (n % i == 0) { cout << (n - i) / 2 + 1 << endl; return 0; } } puts( 1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; bool vis[100][100]; char g[100][100]; void dfs(int a, int b) { if (vis[a][b] || a > n || a < 1 || b < 1 || b > n || g[a][b] == 1 ) return; vis[a][b] = 1; dfs(a + 1, b); dfs(a, b + 1); dfs(a - 1, b); dfs(a, b - 1); } int dist(pair<int, int> a, pair<int, int> b) { return (a.first - b.first) * (a.first - b.first) + (a.second - b.second) * (a.second - b.second); } int main() { cin >> n; int r1, c1, r2, c2; cin >> r1 >> c1 >> r2 >> c2; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cin >> g[i][j]; } } set<pair<int, int>> a; set<pair<int, int>> b; dfs(r1, c1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (vis[i][j]) a.insert({i, j}); vis[i][j] = 0; } } dfs(r2, c2); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (vis[i][j]) b.insert({i, j}); } } if (a == b) cout << 0 << endl; else { int s = 10000000; for (auto x : a) { for (auto y : b) { s = min(s, dist(x, y)); } } cout << s << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, pair<int, int> > > g[300043]; int main() { int n, m, k; scanf( %d %d %d , &n, &m, &k); for (int i = 0; i < m; i++) { int x, y, w; scanf( %d %d %d , &x, &y, &w); --x; --y; g[x].push_back(make_pair(y, make_pair(w, i))); g[y].push_back(make_pair(x, make_pair(w, i))); } set<pair<long long, int> > q; vector<long long> d(n, (long long)(1e18)); d[0] = 0; q.insert(make_pair(0, 0)); vector<int> last(n, -1); int cnt = 0; vector<int> ans; while (!q.empty() && cnt < k) { set<pair<long long, int> >::iterator it = q.begin(); q.erase(q.begin()); pair<int, int> top = *it; int k = top.second; if (last[k] != -1) { cnt++; ans.push_back(last[k]); } vector<pair<int, pair<int, int> > >::iterator ii; for (ii = g[k].begin(); ii != g[k].end(); ii++) { pair<int, pair<int, int> > y = *ii; int to = y.first; int w = y.second.first; int idx = y.second.second; if (d[to] > d[k] + w) { q.erase(make_pair(d[to], to)); d[to] = d[k] + w; last[to] = idx; q.insert(make_pair(d[to], to)); } } } printf( %d n , ans.size()); vector<int>::iterator x; for (x = ans.begin(); x != ans.end(); x++) printf( %d , *x + 1); }
|
#include <bits/stdc++.h> const int N = 1010; int n, k, a[N], a2[N], used[N], m, d, ans; std::list<int> list; int t; void spendTimeUntil(int setSz) { while (list.size() > setSz) { d = round(100 * (double)m / (double)n); for (int x : list) { if (a2[x] + 1 == d && !used[x]) { used[x] = 1; ans++; } } for (auto it = list.begin(); it != list.end();) { if (++a2[*it] != a[*it]) it++; else { it = list.erase(it); m++; } } } } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , a + i); if (list.size() < k) list.push_back(i); else { spendTimeUntil(k - 1); list.push_back(i); } } spendTimeUntil(0); printf( %d n , ans); return 0; }
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Export NumPrelude NZAxioms.
Require Import NZBase NZOrder NZAddOrder Plus Minus.
(** In this file, we investigate the shape of domains satisfying
the [NZDomainSig] interface. In particular, we define a
translation from Peano numbers [nat] into NZ.
*)
Local Notation "f ^ n" := (fun x => nat_rect _ x (fun _ => f) n).
Instance nat_rect_wd n {A} (R:relation A) :
Proper (R==>(R==>R)==>R) (fun x f => nat_rect (fun _ => _) x (fun _ => f) n).
Proof.
intros x y eq_xy f g eq_fg; induction n; [assumption | now apply eq_fg].
Qed.
Module NZDomainProp (Import NZ:NZDomainSig').
Include NZBaseProp NZ.
(** * Relationship between points thanks to [succ] and [pred]. *)
(** For any two points, one is an iterated successor of the other. *)
Lemma itersucc_or_itersucc n m : exists k, n == (S^k) m \/ m == (S^k) n.
Proof.
revert n.
apply central_induction with (z:=m).
{ intros x y eq_xy; apply ex_iff_morphism.
intros n; apply or_iff_morphism.
+ split; intros; etransitivity; try eassumption; now symmetry.
+ split; intros; (etransitivity; [eassumption|]); [|symmetry];
(eapply nat_rect_wd; [eassumption|apply succ_wd]).
}
exists 0%nat. now left.
intros n. split; intros [k [L|R]].
exists (Datatypes.S k). left. now apply succ_wd.
destruct k as [|k].
simpl in R. exists 1%nat. left. now apply succ_wd.
rewrite nat_rect_succ_r in R. exists k. now right.
destruct k as [|k]; simpl in L.
exists 1%nat. now right.
apply succ_inj in L. exists k. now left.
exists (Datatypes.S k). right. now rewrite nat_rect_succ_r.
Qed.
(** Generalized version of [pred_succ] when iterating *)
Lemma succ_swap_pred : forall k n m, n == (S^k) m -> m == (P^k) n.
Proof.
induction k.
simpl; auto with *.
simpl; intros. apply pred_wd in H. rewrite pred_succ in H. apply IHk in H; auto.
rewrite <- nat_rect_succ_r in H; auto.
Qed.
(** From a given point, all others are iterated successors
or iterated predecessors. *)
Lemma itersucc_or_iterpred : forall n m, exists k, n == (S^k) m \/ n == (P^k) m.
Proof.
intros n m. destruct (itersucc_or_itersucc n m) as (k,[H|H]).
exists k; left; auto.
exists k; right. apply succ_swap_pred; auto.
Qed.
(** In particular, all points are either iterated successors of [0]
or iterated predecessors of [0] (or both). *)
Lemma itersucc0_or_iterpred0 :
forall n, exists p:nat, n == (S^p) 0 \/ n == (P^p) 0.
Proof.
intros n. exact (itersucc_or_iterpred n 0).
Qed.
(** * Study of initial point w.r.t. [succ] (if any). *)
Definition initial n := forall m, n ~= S m.
Lemma initial_alt : forall n, initial n <-> S (P n) ~= n.
Proof.
split. intros Bn EQ. symmetry in EQ. destruct (Bn _ EQ).
intros NEQ m EQ. apply NEQ. rewrite EQ, pred_succ; auto with *.
Qed.
Lemma initial_alt2 : forall n, initial n <-> ~exists m, n == S m.
Proof. firstorder. Qed.
(** First case: let's assume such an initial point exists
(i.e. [S] isn't surjective)... *)
Section InitialExists.
Hypothesis init : t.
Hypothesis Initial : initial init.
(** ... then we have unicity of this initial point. *)
Lemma initial_unique : forall m, initial m -> m == init.
Proof.
intros m Im. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p. now simpl in *. destruct (Initial _ H).
destruct p. now simpl in *. destruct (Im _ H).
Qed.
(** ... then all other points are descendant of it. *)
Lemma initial_ancestor : forall m, exists p, m == (S^p) init.
Proof.
intros m. destruct (itersucc_or_itersucc init m) as (p,[H|H]).
destruct p; simpl in *; auto. exists O; auto with *. destruct (Initial _ H).
exists p; auto.
Qed.
(** NB : We would like to have [pred n == n] for the initial element,
but nothing forces that. For instance we can have -3 as initial point,
and P(-3) = 2. A bit odd indeed, but legal according to [NZDomainSig].
We can hence have [n == (P^k) m] without [exists k', m == (S^k') n].
*)
(** We need decidability of [eq] (or classical reasoning) for this: *)
Section SuccPred.
Hypothesis eq_decidable : forall n m, n==m \/ n~=m.
Lemma succ_pred_approx : forall n, ~initial n -> S (P n) == n.
Proof.
intros n NB. rewrite initial_alt in NB.
destruct (eq_decidable (S (P n)) n); auto.
elim NB; auto.
Qed.
End SuccPred.
End InitialExists.
(** Second case : let's suppose now [S] surjective, i.e. no initial point. *)
Section InitialDontExists.
Hypothesis succ_onto : forall n, exists m, n == S m.
Lemma succ_onto_gives_succ_pred : forall n, S (P n) == n.
Proof.
intros n. destruct (succ_onto n) as (m,H). rewrite H, pred_succ; auto with *.
Qed.
Lemma succ_onto_pred_injective : forall n m, P n == P m -> n == m.
Proof.
intros n m. intros H; apply succ_wd in H.
rewrite !succ_onto_gives_succ_pred in H; auto.
Qed.
End InitialDontExists.
(** To summarize:
S is always injective, P is always surjective (thanks to [pred_succ]).
I) If S is not surjective, we have an initial point, which is unique.
This bottom is below zero: we have N shifted (or not) to the left.
P cannot be injective: P init = P (S (P init)).
(P init) can be arbitrary.
II) If S is surjective, we have [forall n, S (P n) = n], S and P are
bijective and reciprocal.
IIa) if [exists k<>O, 0 == S^k 0], then we have a cyclic structure Z/nZ
IIb) otherwise, we have Z
*)
(** * An alternative induction principle using [S] and [P]. *)
(** It is weaker than [bi_induction]. For instance it cannot prove that
we can go from one point by many [S] _or_ many [P], but only by many
[S] mixed with many [P]. Think of a model with two copies of N:
0, 1=S 0, 2=S 1, ...
0', 1'=S 0', 2'=S 1', ...
and P 0 = 0' and P 0' = 0.
*)
Lemma bi_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A ->
A 0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros. apply bi_induction; auto.
clear n. intros n; split; auto.
intros G; apply H2 in G. rewrite pred_succ in G; auto.
Qed.
Lemma central_induction_pred :
forall A : t -> Prop, Proper (eq==>iff) A -> forall n0,
A n0 -> (forall n, A n -> A (S n)) -> (forall n, A n -> A (P n)) ->
forall n, A n.
Proof.
intros.
assert (A 0).
destruct (itersucc_or_iterpred 0 n0) as (k,[Hk|Hk]); rewrite Hk; clear Hk.
clear H2. induction k; simpl in *; auto.
clear H1. induction k; simpl in *; auto.
apply bi_induction_pred; auto.
Qed.
End NZDomainProp.
(** We now focus on the translation from [nat] into [NZ].
First, relationship with [0], [succ], [pred].
*)
Module NZOfNat (Import NZ:NZDomainSig').
Definition ofnat (n : nat) : t := (S^n) 0.
Notation "[ n ]" := (ofnat n) (at level 7) : ofnat.
Local Open Scope ofnat.
Lemma ofnat_zero : [O] == 0.
Proof.
reflexivity.
Qed.
Lemma ofnat_succ : forall n, [Datatypes.S n] == succ [n].
Proof.
now unfold ofnat.
Qed.
Lemma ofnat_pred : forall n, n<>O -> [Peano.pred n] == P [n].
Proof.
unfold ofnat. destruct n. destruct 1; auto.
intros _. simpl. symmetry. apply pred_succ.
Qed.
(** Since [P 0] can be anything in NZ (either [-1], [0], or even other
numbers, we cannot state previous lemma for [n=O]. *)
End NZOfNat.
(** If we require in addition a strict order on NZ, we can prove that
[ofnat] is injective, and hence that NZ is infinite
(i.e. we ban Z/nZ models) *)
Module NZOfNatOrd (Import NZ:NZOrdSig').
Include NZOfNat NZ.
Include NZBaseProp NZ <+ NZOrderProp NZ.
Local Open Scope ofnat.
Theorem ofnat_S_gt_0 :
forall n : nat, 0 < [Datatypes.S n].
Proof.
unfold ofnat.
intros n; induction n as [| n IH]; simpl in *.
apply lt_succ_diag_r.
apply lt_trans with (S 0). apply lt_succ_diag_r. now rewrite <- succ_lt_mono.
Qed.
Theorem ofnat_S_neq_0 :
forall n : nat, 0 ~= [Datatypes.S n].
Proof.
intros. apply lt_neq, ofnat_S_gt_0.
Qed.
Lemma ofnat_injective : forall n m, [n]==[m] -> n = m.
Proof.
induction n as [|n IH]; destruct m; auto.
intros H; elim (ofnat_S_neq_0 _ H).
intros H; symmetry in H; elim (ofnat_S_neq_0 _ H).
intros. f_equal. apply IH. now rewrite <- succ_inj_wd.
Qed.
Lemma ofnat_eq : forall n m, [n]==[m] <-> n = m.
Proof.
split. apply ofnat_injective. intros; now subst.
Qed.
(* In addition, we can prove that [ofnat] preserves order. *)
Lemma ofnat_lt : forall n m : nat, [n]<[m] <-> (n<m)%nat.
Proof.
induction n as [|n IH]; destruct m; repeat rewrite ofnat_zero; split.
intro H; elim (lt_irrefl _ H).
inversion 1.
auto with arith.
intros; apply ofnat_S_gt_0.
intro H; elim (lt_asymm _ _ H); apply ofnat_S_gt_0.
inversion 1.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
rewrite !ofnat_succ, <- succ_lt_mono, IH; auto with arith.
Qed.
Lemma ofnat_le : forall n m : nat, [n]<=[m] <-> (n<=m)%nat.
Proof.
intros. rewrite lt_eq_cases, ofnat_lt, ofnat_eq.
split.
destruct 1; subst; auto with arith.
apply Lt.le_lt_or_eq.
Qed.
End NZOfNatOrd.
(** For basic operations, we can prove correspondance with
their counterpart in [nat]. *)
Module NZOfNatOps (Import NZ:NZAxiomsSig').
Include NZOfNat NZ.
Local Open Scope ofnat.
Lemma ofnat_add_l : forall n m, [n]+m == (S^n) m.
Proof.
induction n; intros.
apply add_0_l.
rewrite ofnat_succ, add_succ_l. simpl. now f_equiv.
Qed.
Lemma ofnat_add : forall n m, [n+m] == [n]+[m].
Proof.
intros. rewrite ofnat_add_l.
induction n; simpl. reflexivity.
now f_equiv.
Qed.
Lemma ofnat_mul : forall n m, [n*m] == [n]*[m].
Proof.
induction n; simpl; intros.
symmetry. apply mul_0_l.
rewrite plus_comm.
rewrite ofnat_add, mul_succ_l.
now f_equiv.
Qed.
Lemma ofnat_sub_r : forall n m, n-[m] == (P^m) n.
Proof.
induction m; simpl; intros.
apply sub_0_r.
rewrite sub_succ_r. now f_equiv.
Qed.
Lemma ofnat_sub : forall n m, m<=n -> [n-m] == [n]-[m].
Proof.
intros n m H. rewrite ofnat_sub_r.
revert n H. induction m. intros.
rewrite <- minus_n_O. now simpl.
intros.
destruct n.
inversion H.
rewrite nat_rect_succ_r.
simpl.
etransitivity. apply IHm. auto with arith.
eapply nat_rect_wd; [symmetry;apply pred_succ|apply pred_wd].
Qed.
End NZOfNatOps.
|
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; long long xabs(long long a) { return a < 0 ? -a : +a; } bool check(long long p, long long q, long long x, long long y, long long a, long long b) { if (a * x + b * y == p && a * y - b * x == q) return true; else return false; } bool can(long long ax, long long ay, long long bx, long long by, long long x, long long y) { long long p = bx - ax; long long q = by - ay; if (x == 0 && y == 0) { if (p == 0 && q == 0) return true; else return false; } if (y != 0) swap(x, y), swap(p, q); long long b = (p * y - q * x) / (y * y + x * x); long long a = (p - b * y) / x; if (check(p, q, x, y, a, b)) return true; else return false; } int main() { long long ax, ay, bx, by, x, y; cin >> ax >> ay >> bx >> by >> x >> y; bool fl = false; for (int i = 0; i < 4; ++i) { fl |= can(ax, ay, bx, by, x, y); swap(ax, ay); ax = -ax; } if (fl) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int rdi() { int d; scanf( %d , &d); return d; } inline char rdc() { scanf( ); return getchar(); } inline string rds() { string s; cin >> s; return s; } inline double rddb() { double d; scanf( %lf , &d); return d; } template <class T> inline bool setmin(T& a, T b) { return a > b ? a = b, true : false; } template <class T> inline bool setmax(T& a, T b) { return a < b ? a = b, true : false; } struct debugger { template <typename T> debugger& operator,(const T& x) { cerr << x << , ; return *this; } } dbgr; const int N = 131072, M = 128; char s[N]; int n, c[3], cnt[N][3]; int Abs(int x) { return x < 0 ? -x : +x; } int main() { scanf( %s , s + 1), n = strlen(s + 1); for (int i = (1); i <= (n); ++i) memcpy(cnt[i], cnt[i - 1], sizeof cnt[i]), ++cnt[i][s[i] - x ]; for (int repp_b = (rdi()), repp = 0; repp < repp_b; ++repp) { int l = rdi(), r = rdi(); for (int i = (0); i < (3); ++i) c[i] = cnt[r][i] - cnt[l - 1][i]; int mx = *max_element(c, c + 3); int mn = *min_element(c, c + 3); puts(r - l + 1 < 3 || mx - mn <= 1 ? YES : NO ); } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON128_NEXT 6'b00_0001
`define S_TXPORTMON128_EVT_2 6'b00_0010
`define S_TXPORTMON128_TXN 6'b00_0100
`define S_TXPORTMON128_READ 6'b00_1000
`define S_TXPORTMON128_END_0 6'b01_0000
`define S_TXPORTMON128_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE4Lo=0, _rLenLE4Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON128_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
assign TXN = rState[2]; // S_TXPORTMON128_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON128_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_EVT_2;
end
`S_TXPORTMON128_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_TXN;
end
`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);
end
`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON128_END_0;
end
`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
end
`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_NEXT;
end
default: begin
_rState = `S_TXPORTMON128_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE4Lo <= #1 _rLenLE4Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[63:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 4, we want to trigger the almost all received flag
_rLenLE4Lo = (LEN[15:0] <= 16'd4);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({201'd0,
rWordsRecvd, // 32
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 129
rState}) // 5
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void write(int x) { if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int N = 200005, inf = 1e9; int a[N], t[N], id[N], fa[N], dep[N], num[N], son[N], q[N], dfn[N]; int top[N], ans[N], n, m, cnt = 0, fd; struct tree { int mx, lazy; } tr[N << 2]; bool cmp(int x, int y) { if (t[x] + dep[a[x]] != t[y] + dep[a[y]]) return t[x] + dep[a[x]] < t[y] + dep[a[y]]; return a[x] < a[y]; } inline void pushup(int x) { tr[x].mx = max(tr[x << 1].mx, tr[x << 1 | 1].mx); } inline void pushdown(int x, int l, int mid, int r) { if (tr[x].lazy < -inf) return; tr[x << 1].lazy = tr[x << 1 | 1].lazy = tr[x].lazy; tr[x << 1].mx = mid * 2 + tr[x].lazy; tr[x << 1 | 1].mx = r * 2 + tr[x].lazy; tr[x].lazy = -inf - 1; } void modify(int now, int l, int r, int x, int y, int z) { if (x <= l && r <= y) { tr[now].lazy = z; tr[now].mx = r * 2 + z; return; } int mid = (l + r) >> 1; pushdown(now, l, mid, r); if (x <= mid) modify(now << 1, l, mid, x, y, z); if (y > mid) modify(now << 1 | 1, mid + 1, r, x, y, z); pushup(now); } void query(int now, int l, int r, int x, int y, int z) { if (tr[now].mx <= z) return; if (l == r) { fd = q[l]; return; } int mid = (l + r) >> 1; pushdown(now, l, mid, r); if (fd == -1 && y > mid) query(now << 1 | 1, mid + 1, r, x, y, z); if (fd == -1 && x <= mid) query(now << 1, l, mid, x, y, z); pushup(now); } int work(int x, int t) { int y = x; while (1) { fd = -1; query(1, 0, n, dfn[top[y]], dfn[y], t + dfn[y]); if (fd >= 0) { t += dep[y] - dep[fd]; y = fd; break; } if (!y) break; t += dep[y] - dep[fa[top[y]]]; y = fa[top[y]]; } int z = t + dep[x] - dep[y]; while (1) { if (top[x] == top[y]) { if (x != y) modify(1, 0, n, dfn[y] + 1, dfn[x], t - dfn[y]); break; } modify(1, 0, n, dfn[top[x]], dfn[x], dep[x] - dep[y] + t - dfn[x]); x = fa[top[x]]; } return z; } int main() { n = read(); m = read(); for (int i = 1; i <= n; ++i) { fa[i] = read(); dep[i] = dep[fa[i]] + 1; num[i] = 1; } for (int i = n; i; i--) { if (num[i] > num[son[fa[i]]]) son[fa[i]] = i; if (fa[i]) num[fa[i]] += num[i]; } for (int i = son[0]; i; i = son[i]) q[dfn[i] = ++cnt] = i; for (int i = 0; i <= n; ++i) if (!dfn[i]) for (int j = i; j; j = son[j]) top[q[dfn[j] = ++cnt] = j] = i; for (int i = 1; i <= m; ++i) a[i] = read(), t[i] = read(); for (int i = 1; i <= m; ++i) id[i] = i; sort(id + 1, id + m + 1, cmp); tr[1].mx = tr[1].lazy = -inf; for (int i = 1; i <= m; ++i) ans[id[i]] = work(a[id[i]], t[id[i]]); for (int i = 1; i <= m; ++i) write(ans[i]), putchar( ); puts( ); return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_misc.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_misc.v //
// Description : Implements the PIPE interface PIPELINE for all per link //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_mics.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_misc #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire [1:0] pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
input wire [5:0] pipe_tx_eqfs_i , // PIPE Tx
input wire [5:0] pipe_tx_eqlf_i , // PIPE Tx
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire [1:0] pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
output wire [5:0] pipe_tx_eqfs_o , // PIPE Tx
output wire [5:0] pipe_tx_eqlf_o , // PIPE Tx
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg [1:0] pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_eqfs_q ;
reg pipe_tx_eqlf_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg [1:0] pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
reg pipe_tx_eqfs_qq ;
reg pipe_tx_eqlf_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 3'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_q;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 1'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
pipe_tx_rcvr_det_qq <= #TCQ 1'b0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 2'b0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 1'b0;
pipe_tx_swing_qq <= #TCQ 1'b0;
pipe_tx_eqfs_qq <= #TCQ 5'b0;
pipe_tx_eqlf_qq <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
pipe_tx_eqfs_qq <= #TCQ pipe_tx_eqfs_q;
pipe_tx_eqlf_qq <= #TCQ pipe_tx_eqlf_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_qq;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_2_V
`define SKY130_FD_SC_HD__NAND2B_2_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2b_2 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand2b_2 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_2_V
|
//-----------------------------------------------------------------
// MPX 32-bit Soft-Core Processor
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "mpx_defs.v"
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module mpx_alu
(
input_a,
input_b,
func,
result
);
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input [31:0] input_a /*verilator public*/;
input [31:0] input_b /*verilator public*/;
input [3:0] func /*verilator public*/;
output [31:0] result /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [31:0] result;
//-----------------------------------------------------------------
// ALU
//-----------------------------------------------------------------
always @ (func or input_a or input_b )
begin
case (func)
`ALU_SHIFTL : result = shift_left(input_a, input_b);
`ALU_SHIFTR : result = shift_right(input_a, input_b);
`ALU_SHIRTR_ARITH: result = shift_right_arith(input_a, input_b);
`ALU_ADD : result = (input_a + input_b);
`ALU_SUB : result = (input_a - input_b);
`ALU_AND : result = (input_a & input_b);
`ALU_OR : result = (input_a | input_b);
`ALU_XOR : result = (input_a ^ input_b);
`ALU_NOR : result = (~(input_a | input_b));
`ALU_SLT :
begin
if (less_than_signed(input_a, input_b) == 1'b1)
result = 32'h00000001;
else
result = 32'h00000000;
end
`ALU_SLTE :
begin
if ((less_than_signed(input_a, input_b) == 1'b1) || (input_a == input_b))
result = 32'h00000001;
else
result = 32'h00000000;
end
`ALU_SLTU :
begin
if (less_than(input_a, input_b) == 1'b1)
result = 32'h00000001;
else
result = 32'h00000000;
end
default :
result = 32'h00000000;
endcase
end
`include "mpx_funcs.v"
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[27] = {0}; int main() { int i, j, m, n, t; string s; cin >> n; cin >> s; for (i = 0; i < n; i++) a[s[i] - a + 1]++; for (i = 1; i <= 26; i++) if (a[i] == n) { cout << NO << endl; return 0; } for (i = 0; i < n - 1; i++) { if (s[i] != s[i + 1]) { cout << YES << endl; cout << s[i] << s[i + 1] << endl; return 0; } } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 10:10:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; template <class T> void chmin(T& a, const T& b) { if (a > b) a = b; } template <class T> void chmax(T& a, const T& b) { if (a < b) a = b; } int n, d; const int geta = 260; const int MX = 30000; int dp[30010][520]; int cnt[30010]; int main() { scanf( %d %d , &n, &d); for (int i = 0; i < n; i++) { int k; scanf( %d , &k); cnt[k]++; } memset(dp, -1, sizeof(dp)); dp[d][geta] = cnt[d]; int ans = 0; for (int i = d; i <= MX; i++) { for (int j = 0; j < 520; j++) { if (dp[i][j] == -1) continue; chmax(ans, dp[i][j]); int len = d + (j - geta); if (len > 1 && i + len - 1 <= MX) chmax(dp[i + len - 1][j - 1], dp[i][j] + cnt[i + len - 1]); if (i + len <= MX) chmax(dp[i + len][j], dp[i][j] + cnt[i + len]); if (i + len + 1 <= MX) chmax(dp[i + len + 1][j + 1], dp[i][j] + cnt[i + len + 1]); } } printf( %d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int ntest = 0, test = 0; inline void init(); inline void run(); inline void stop() { ntest = test - 1; } int main() { init(); while (++test <= ntest) { run(); } return 0; } const int INF = (int)1E9 + 5; const double EPS = 1E-11; const long long MOD = (long long)1E9 + 7; const int dx[] = {-1, 0, 0, 1}; const int dy[] = {0, -1, 1, 0}; inline void init() { ntest = 1; } int cnt[(int)(1e6 + 5)]; inline void run() { int n, m, a, b; cin >> n >> m; for (int i = 0; i < (m); i++) { scanf( %d%d , &a, &b); cnt[a]++; cnt[b]++; } long long x = 0; for (int i = (1); i <= (n); i++) x += (n - 1 - cnt[i]) * cnt[i]; x /= 2; cout << (n - 1ll) * n * (n - 2ll) / 6 - x; }
|
//=======================================================
// Ports generated by Terasic System Builder
//=======================================================
module vid_io_demo(
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// LED //////////
output [8:0] LEDG,
output [17:0] LEDR,
//////////// KEY //////////
input [3:0] KEY,
//////////// VGA //////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// I2C for Tv-Decoder //////////
output I2C_SCLK,
inout I2C_SDAT,
//////////// TV Decoder //////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
//////////// SDRAM //////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [31:0] DRAM_DQ,
output [3:0] DRAM_DQM,
output DRAM_RAS_N,
output DRAM_WE_N
);
//Global Reset
wire aresetn;
assign aresetn = KEY[0];
//Video IO Pipeline
pipeline_wrapper pipeline_wrapper_inst
(
.clk (CLOCK_50),
.aresetn (aresetn),
//////// VGA //////////
.VGA_B (VGA_B),
.VGA_BLANK_N (VGA_BLANK_N),
.VGA_CLK (VGA_CLK),
.VGA_G (VGA_G),
.VGA_HS (VGA_HS),
.VGA_R (VGA_R),
.VGA_SYNC_N (VGA_SYNC_N),
.VGA_VS (VGA_VS),
//////// TV Decoder //////////
.TD_CLK27 (TD_CLK27),
.TD_DATA (TD_DATA),
.TD_HS (TD_HS),
.TD_RESET_N (TD_RESET_N),
.TD_VS (TD_VS),
//////// SDRAM //////////
.DRAM_ADDR (DRAM_ADDR),
.DRAM_BA (DRAM_BA),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQ (DRAM_DQ),
.DRAM_DQM (DRAM_DQM),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INFINITE = (int)(0xffffffff >> 2); int n; int gs[600]; int dp[600][600]; int run(int l, int r) { if (l > r) return 0; if (l == r) return 1; if (dp[l][r] != INFINITE) { return dp[l][r]; } dp[l][r] = min(dp[l][r], run(l + 1, r) + 1); for (int k = l + 2; k <= r; k++) { if (gs[l] == gs[k]) { dp[l][r] = min(dp[l][r], run(l + 1, k - 1) + run(k + 1, r)); } } if (gs[l] == gs[l + 1]) { dp[l][r] = min(dp[l][r], run(l + 2, r) + 1); return dp[l][r]; } return dp[l][r]; } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> gs[i]; for (int i = 0; i < 600; i++) { int *row = dp[i]; for (int j = 0; j < 600; j++) { row[j] = INFINITE; } } cout << run(1, n) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 2 == 0) cout << (n * n) / 2 << endl; else cout << (n / 2) * (n / 2) + (n / 2 + 1) * (n / 2 + 1) << endl; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if ((i + j) % 2 == 0) cout << C ; else cout << . ; cout << endl; } }
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* S/GMII cycle asynchronous fifo.
*
*/
module sgmii_fifo
(
input rst_in,
input clk_in,
input clk_out,
input [8:0] fifo_in,
input push,
output full,
output [8:0] fifo_out,
input pop,
output empty
);
parameter DEPTH = 32; // max 64 (can hold DEPTH-1 before full)
parameter TRIG_DEPTH = 12; // Hold sync until push stops or X in a row
reg [5:0] trig_cnt;
wire trig_en = (!push || (trig_cnt == TRIG_DEPTH));
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
trig_cnt <= 6'd0;
else if (!push)
trig_cnt <= 6'd0;
else if (!trig_en)
trig_cnt <= trig_cnt + 6'd1;
reg [1:0] cross_in;
reg [5:0] head_in;
reg [5:0] head_snapshot;
reg [5:0] tail_in;
reg [1:0] cross_out;
reg [5:0] head_out;
reg [5:0] tail_out;
reg [5:0] tail_snapshot;
always @ (posedge clk_in)
cross_in <= (trig_en) ? cross_out : 2'd0;
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
cross_out <= 2'b00;
else
case (cross_in)
2'b00: cross_out <= 2'b01;
2'b01: cross_out <= 2'b11;
2'b11: cross_out <= 2'b10;
default: cross_out <= 2'b00;
endcase
wire [5:0] head_in_next = (head_in == (DEPTH - 1)) ? 6'd0 : head_in + 6'd1;
wire fifo_full = (head_in_next == tail_in);
always @ (posedge clk_in or posedge rst_in)
if (rst_in)
begin
head_in <= 6'd0;
head_snapshot <= 6'd0;
tail_in <= 6'd0;
end
else
begin
if (push && !fifo_full)
head_in <= head_in_next;
case (cross_in)
2'b01: head_snapshot <= head_in;
2'b10: tail_in <= tail_snapshot;
endcase
end
wire [5:0] tail_out_next = (tail_out == (DEPTH - 1)) ? 6'd0 : tail_out + 6'd1;
wire fifo_empty = (tail_out == head_out);
always @ (posedge clk_out or posedge rst_in)
if (rst_in)
begin
head_out <= 6'd0;
tail_out <= 6'd0;
tail_snapshot <= 6'd0;
end
else
begin
if (pop && !fifo_empty)
tail_out <= tail_out_next;
case (cross_out)
2'b01: tail_snapshot <= tail_out;
2'b10: head_out <= head_snapshot;
endcase
end
reg [8:0] fifo[(DEPTH - 1):0];
always @ (posedge clk_in)
if (push)
fifo[head_in] <= fifo_in[8:0];
assign full = fifo_full;
assign empty = fifo_empty;
assign fifo_out = fifo[tail_out];
endmodule
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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const int maxnnn = (int)1e6 + 10; int aaaa[maxnnn]; int bbbb[maxnnn]; int l[maxnnn]; int r[maxnnn]; int nnnnn; vector<int> gggg[maxnnn]; vector<int> tttt[4 * maxnnn]; int cnttttt; void build(int v, int tl, int tr) { if (tl == tr) tttt[v] = vector<int>(1, aaaa[tl]); else { int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); merge(tttt[v * 2].begin(), tttt[v * 2].end(), tttt[v * 2 + 1].begin(), tttt[v * 2 + 1].end(), back_inserter(tttt[v])); } } void query(int v, int tl, int tr, int l, int r, int x) { if (l > r) return; if (l == tl && tr == r) { int i = (int)tttt[v].size() - 1; while (i >= 0 && tttt[v][i] > x && cnttttt < nnnnn) { cnttttt++; gggg[bbbb[x]].push_back(bbbb[tttt[v][i]]); gggg[bbbb[tttt[v][i]]].push_back(bbbb[x]); i--; } return; } int tm = (tl + tr) / 2; query(v * 2, tl, tm, l, min(r, tm), x); query(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r, x); } int used[maxnnn]; void dfs(int v) { cnttttt++; used[v] = 1; for (int u : gggg[v]) { if (!used[u]) { dfs(u); } } } void solution() { cin >> nnnnn; for (int i = 1; i <= nnnnn; i++) { cin >> l[i] >> r[i]; aaaa[l[i]] = r[i]; aaaa[r[i]] = -1; bbbb[r[i]] = bbbb[l[i]] = i; } build(1, 1, 2 * nnnnn); for (int i = 1; i <= nnnnn; i++) { query(1, 1, 2 * nnnnn, l[i], r[i], r[i]); } if (cnttttt != nnnnn - 1) { cout << NO << endl; return; } cnttttt = 0; dfs(1); if (cnttttt == nnnnn) { cout << YES << endl; } else { cout << NO << endl; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); solution(); }
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#include <bits/stdc++.h> using namespace std; int test, n, mx, i; double l, r, m, eps = 0.000001, a[100005]; double pref(double tm) { double pos = 0, speed = 1; for (int i = 0; i < n; i++) { if ((a[i] - pos) <= tm * speed) tm -= (a[i] - pos) / speed, pos = a[i], speed += 1; else { pos += speed * tm; tm = 0; break; } } pos += speed * tm; return pos; } double suff(double tm) { double pos = mx, speed = 1; for (int i = n - 1; i >= 0; i--) { if ((pos - a[i]) <= tm * speed) tm -= (pos - a[i]) / speed, pos = a[i], speed += 1; else { pos -= speed * tm; tm = 0; break; } } pos -= speed * tm; return pos; } int main() { scanf( %d , &test); while (test--) { cin >> n >> mx; for (i = 0; i < n; i++) cin >> a[i]; l = 0., r = 2000000000.; while (r - l > eps) { m = (l + r) / 2.; if (pref(m) <= suff(m)) l = m; else r = m - eps; } cout << fixed << setprecision(9) << l << n ; } }
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