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//////////////////////////////////////////////////////////////////////
//// ////
//// fifoMux.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module fifoMux (
currEndP,
//TxFifo
TxFifoREn,
TxFifoEP0REn,
TxFifoEP1REn,
TxFifoEP2REn,
TxFifoEP3REn,
TxFifoData,
TxFifoEP0Data,
TxFifoEP1Data,
TxFifoEP2Data,
TxFifoEP3Data,
TxFifoEmpty,
TxFifoEP0Empty,
TxFifoEP1Empty,
TxFifoEP2Empty,
TxFifoEP3Empty,
//RxFifo
RxFifoWEn,
RxFifoEP0WEn,
RxFifoEP1WEn,
RxFifoEP2WEn,
RxFifoEP3WEn,
RxFifoFull,
RxFifoEP0Full,
RxFifoEP1Full,
RxFifoEP2Full,
RxFifoEP3Full
);
input [3:0] currEndP;
//TxFifo
input TxFifoREn;
output TxFifoEP0REn;
output TxFifoEP1REn;
output TxFifoEP2REn;
output TxFifoEP3REn;
output [7:0] TxFifoData;
input [7:0] TxFifoEP0Data;
input [7:0] TxFifoEP1Data;
input [7:0] TxFifoEP2Data;
input [7:0] TxFifoEP3Data;
output TxFifoEmpty;
input TxFifoEP0Empty;
input TxFifoEP1Empty;
input TxFifoEP2Empty;
input TxFifoEP3Empty;
//RxFifo
input RxFifoWEn;
output RxFifoEP0WEn;
output RxFifoEP1WEn;
output RxFifoEP2WEn;
output RxFifoEP3WEn;
output RxFifoFull;
input RxFifoEP0Full;
input RxFifoEP1Full;
input RxFifoEP2Full;
input RxFifoEP3Full;
wire [3:0] currEndP;
//TxFifo
wire TxFifoREn;
reg TxFifoEP0REn;
reg TxFifoEP1REn;
reg TxFifoEP2REn;
reg TxFifoEP3REn;
reg [7:0] TxFifoData;
wire [7:0] TxFifoEP0Data;
wire [7:0] TxFifoEP1Data;
wire [7:0] TxFifoEP2Data;
wire [7:0] TxFifoEP3Data;
reg TxFifoEmpty;
wire TxFifoEP0Empty;
wire TxFifoEP1Empty;
wire TxFifoEP2Empty;
wire TxFifoEP3Empty;
//RxFifo
wire RxFifoWEn;
reg RxFifoEP0WEn;
reg RxFifoEP1WEn;
reg RxFifoEP2WEn;
reg RxFifoEP3WEn;
reg RxFifoFull;
wire RxFifoEP0Full;
wire RxFifoEP1Full;
wire RxFifoEP2Full;
wire RxFifoEP3Full;
//internal wires and regs
//combinatorially mux TX and RX fifos for end points 0 through 3
always @(currEndP or
TxFifoREn or
RxFifoWEn or
TxFifoEP0Data or
TxFifoEP1Data or
TxFifoEP2Data or
TxFifoEP3Data or
TxFifoEP0Empty or
TxFifoEP1Empty or
TxFifoEP2Empty or
TxFifoEP3Empty or
RxFifoEP0Full or
RxFifoEP1Full or
RxFifoEP2Full or
RxFifoEP3Full)
begin
case (currEndP[1:0])
2'b00: begin
TxFifoEP0REn <= TxFifoREn;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP0Data;
TxFifoEmpty <= TxFifoEP0Empty;
RxFifoEP0WEn <= RxFifoWEn;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP0Full;
end
2'b01: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= TxFifoREn;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP1Data;
TxFifoEmpty <= TxFifoEP1Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= RxFifoWEn;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP1Full;
end
2'b10: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= TxFifoREn;
TxFifoEP3REn <= 1'b0;
TxFifoData <= TxFifoEP2Data;
TxFifoEmpty <= TxFifoEP2Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= RxFifoWEn;
RxFifoEP3WEn <= 1'b0;
RxFifoFull <= RxFifoEP2Full;
end
2'b11: begin
TxFifoEP0REn <= 1'b0;
TxFifoEP1REn <= 1'b0;
TxFifoEP2REn <= 1'b0;
TxFifoEP3REn <= TxFifoREn;
TxFifoData <= TxFifoEP3Data;
TxFifoEmpty <= TxFifoEP3Empty;
RxFifoEP0WEn <= 1'b0;
RxFifoEP1WEn <= 1'b0;
RxFifoEP2WEn <= 1'b0;
RxFifoEP3WEn <= RxFifoWEn;
RxFifoFull <= RxFifoEP3Full;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, u, r; int a[30], b[30], p[30], k[30]; long long res; bool first; void doit(int v[]) { long long tmp = 0; for (int i = 0; i < n; i++) { tmp += v[i] * k[i]; } res = max(res, tmp); if (first) { first = false; res = tmp; } } void dfs(int v[], int _u, bool can) { int next[30]; if (_u % 2 == 0) { doit(v); } if (_u == 0) { return; } if (can) { for (int i = 0; i < n; i++) { next[i] = v[i] ^ b[i]; } dfs(next, _u - 1, 0); } for (int i = 0; i < n; i++) { next[i] = v[p[i]] + r; } dfs(next, _u - 1, 1); } int main() { cin >> n >> u >> r; for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) scanf( %d , &b[i]); for (int i = 0; i < n; i++) scanf( %d , &k[i]); for (int i = 0; i < n; i++) scanf( %d , &p[i]); for (int i = 0; i < n; i++) p[i]--; first = 1; res = 0; dfs(a, u, 1); cout << res; return 0; }
|
// file: clk_gen_83M_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_gen_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_gen_83M_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); mt19937 rnf(2106); const int N = 100005; bool c[(1 << 22)]; int d[(1 << 22)]; int p[(1 << 22)]; void solv0(int n) { vector<int> v; for (int x = 0; x < n; ++x) { for (int y = x + 1; y < n; ++y) { for (int z = y + 1; z < n; ++z) { if (y - x == z - y) { v.push_back(((1 << x) | (1 << y) | (1 << z))); } } } } for (int x = 0; x < (1 << n); ++x) c[x] = false; queue<int> q; c[0] = true; d[0] = 0; q.push(0); while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < ((int)(v).size()); ++i) { int h = (x ^ v[i]); if (!c[h]) { c[h] = true; d[h] = d[x] + 1; p[h] = v[i]; q.push(h); } } } return; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) { for (int i = 0; i < n; ++i) { if ((x & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; } } int maxu = 0; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) continue; maxu = max(maxu, d[x]); } cout << maxu << n ; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) continue; if (maxu == d[x]) { for (int i = 0; i < n; ++i) { if ((x & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; cout << endl; while (x) { for (int i = 0; i < n; ++i) { if ((p[x] & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; x ^= p[x]; } return; } } } void solv6() { int n = 6; vector<int> v; for (int x = 0; x < n; ++x) { for (int y = x + 1; y < n; ++y) { for (int z = y + 1; z < n; ++z) { if (y - x == z - y) { v.push_back(((1 << x) | (1 << y) | (1 << z))); } } if (x - (y - x) < 0) v.push_back(((1 << x) | (1 << y))); } v.push_back((1 << x)); } for (int x = 0; x < (1 << n); ++x) c[x] = false; queue<int> q; c[0] = true; d[0] = 0; q.push(0); while (!q.empty()) { int x = q.front(); q.pop(); for (int i = 0; i < ((int)(v).size()); ++i) { int h = (x ^ v[i]); if (!c[h]) { c[h] = true; d[h] = d[x] + 1; p[h] = v[i]; q.push(h); } } } return; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) { for (int i = 0; i < n; ++i) { if ((x & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; } } int maxu = 0; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) continue; maxu = max(maxu, d[x]); } cout << maxu << n ; for (int x = 0; x < (1 << n); ++x) { if (!c[x]) continue; if (maxu == d[x]) { for (int i = 0; i < n; ++i) { if ((x & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; cout << endl; while (x) { for (int i = 0; i < n; ++i) { if ((p[x] & (1 << i))) cout << 1 ; else cout << 0 ; } cout << endl; x ^= p[x]; } return; } } } int n; int a[N]; vector<tuple<int, int, int> > ans; void ubd(int x, int y, int z) { assert(x >= 1 && x <= n && y >= 1 && y <= n && z >= 1 && z <= n); assert(x < y && y < z && (y - x) == (z - y)); ans.push_back(tie(x, y, z)); a[x] ^= 1; a[y] ^= 1; a[z] ^= 1; } void solv() { cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; solv6(); while (n >= 14) { int x = 0; for (int i = n - 5; i <= n; ++i) { x += (a[i] * (1 << (i - (n - 5)))); } while (x) { vector<int> v; for (int i = 0; i < 6; ++i) { if ((p[x] & (1 << i))) v.push_back(n - 5 + i); } if (((int)(v).size()) == 3) ubd(v[0], v[1], v[2]); else if (((int)(v).size()) == 2) ubd(v[0] - (v[1] - v[0]), v[0], v[1]); else ubd(n - 6 - (v[0] - (n - 6)), n - 6, v[0]); x ^= p[x]; } n -= 6; } solv0(n); int x = 0; for (int i = 1; i <= n; ++i) x += (a[i] * (1 << (i - 1))); if (!c[x]) { cout << NO n ; return; } while (x) { vector<int> v; for (int i = 0; i < n; ++i) { if ((p[x] & (1 << i))) v.push_back(i + 1); } ubd(v[0], v[1], v[2]); x ^= p[x]; } for (int i = 1; i <= n; ++i) assert(!a[i]); cout << YES n ; cout << ((int)(ans).size()) << n ; for (int i = 0; i < ((int)(ans).size()); ++i) cout << get<0>(ans[i]) << << get<1>(ans[i]) << << get<2>(ans[i]) << n ; } int main() { ios_base::sync_with_stdio(false), cin.tie(0); int tt = 1; while (tt--) { solv(); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_12_V
`define SKY130_FD_SC_HDLL__MUX2_12_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_12 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__mux2_12 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_12_V
|
#include <bits/stdc++.h> using namespace std; long long a, b; int ans[60]; void dfs(int dep) { long long cur = ans[dep - 1]; long long x = cur << 1; long long y = cur * 10 + 1; if (x == b || y == b) { puts( YES ); cout << dep + 1 << endl; for (int i = 0; i < dep; i++) cout << ans[i] << ; cout << b << endl; exit(0); } ans[dep] = x; if (x < b) dfs(dep + 1); ans[dep] = y; if (y < b) dfs(dep + 1); } int main() { cin >> a >> b; ans[0] = a; dfs(1); puts( NO ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; int a, num, res; while (cin >> n) { num = 0; for (int i = 0; i < n; i++) { cin >> a; if (a % 2 == 0) { num++; } if (num % 2 == 1) { res = 1; } else { res = 2; } if (i == 0) { cout << res; } else { cout << << res; } } cout << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; int n; string s; vector<string> precalced = { !x&x , !(x|y|z) , !x&!y&z , !x&!y , !x&!z&y , !x&!z , !(!y&!z|x|y&z) , !(x|y&z) , !x&y&z , !(!y&z|!z&y|x) , !x&z , !(!z&y|x) , !x&y , !(!y&z|x) , !x&(y|z) , !x , !y&!z&x , !y&!z , !(!x&!z|x&z|y) , !(x&z|y) , !(!x&!y|x&y|z) , !(x&y|z) , !(!x&!y|x&y|z)|!x&!y&z , !((x|y)&z|x&y) , !x&y&z|!y&!z&x , !x&y&z|!y&!z , !x&z|!y&!z&x , !x&z|!y&!z , !x&y|!y&!z&x , !x&y|!y&!z , !x&(y|z)|!y&!z&x , !x|!y&!z , !y&x&z , !(!x&z|!z&x|y) , !y&z , !(!z&x|y) , !x&!z&y|!y&x&z , !x&!z|!y&x&z , !x&!z&y|!y&z , !x&!z|!y&z , !x&y&z|!y&x&z , !(!x&z|!z&x|y)|!x&y&z , !(x&y)&z , !(!z&x|y)|!x&z , !x&y|!y&x&z , !(!y&z|x)|!y&x&z , !x&y|!y&z , !x|!y&z , !y&x , !(!x&z|y) , !y&(x|z) , !y , !x&!z&y|!y&x , !x&!z|!y&x , !x&!z&y|!y&(x|z) , !x&!z|!y , !x&y&z|!y&x , !(!x&z|y)|!x&y&z , !x&z|!y&x , !x&z|!y , !x&y|!y&x , !(!x&!y&z|x&y) , !x&(y|z)|!y&x , !x|!y , !z&x&y , !(!x&y|!y&x|z) , !x&!y&z|!z&x&y , !x&!y|!z&x&y , !z&y , !(!y&x|z) , !x&!y&z|!z&y , !x&!y|!z&y , !x&y&z|!z&x&y , !(!x&y|!y&x|z)|!x&y&z , !x&z|!z&x&y , !(!z&y|x)|!z&x&y , !(x&z)&y , !(!y&x|z)|!x&y , !x&z|!z&y , !x|!z&y , !z&x , !(!x&y|z) , !x&!y&z|!z&x , !x&!y|!z&x , !z&(x|y) , !z , !x&!y&z|!z&(x|y) , !x&!y|!z , !x&y&z|!z&x , !(!x&y|z)|!x&y&z , !x&z|!z&x , !(!x&!z&y|x&z) , !x&y|!z&x , !x&y|!z , !x&(y|z)|!z&x , !x|!z , !y&x&z|!z&x&y , !(!x&y|!y&x|z)|!y&x&z , !y&z|!z&x&y , !(!z&x|y)|!z&x&y , !y&x&z|!z&y , !(!y&x|z)|!y&x&z , !y&z|!z&y , !(!y&!z&x|y&z) , !x&y&z|!y&x&z|!z&x&y , !(!x&y|!y&x|z)|!x&y&z|!y&x&z , !(x&y)&z|!z&x&y , !(!z&x|y)|!x&z|!z&x&y , !(x&z)&y|!y&x&z , !(!y&x|z)|!x&y|!y&x&z , !(x&y)&z|!z&y , !x|!y&z|!z&y , !(y&z)&x , !(!x&y|z)|!y&x , !y&z|!z&x , !y|!z&x , !y&x|!z&y , !y&x|!z , !y&(x|z)|!z&y , !y|!z , !(y&z)&x|!x&y&z , !(!x&y|z)|!x&y&z|!y&x , !(x&y)&z|!z&x , !x&z|!y|!z&x , !(x&z)&y|!y&x , !x&y|!y&x|!z , !x&y|!y&z|!z&x , !(x&y&z) , x&y&z , !(x|y|z)|x&y&z , !x&!y&z|x&y&z , !x&!y|x&y&z , !x&!z&y|x&y&z , !x&!z|x&y&z , !(!y&!z|x|y&z)|x&y&z , !(x|y&z)|x&y&z , y&z , !(x|y|z)|y&z , !x&z|y&z , !x&!y|y&z , !x&y|y&z , !x&!z|y&z , !x&(y|z)|y&z , !x|y&z , !y&!z&x|x&y&z , !y&!z|x&y&z , !(!x&!z|x&z|y)|x&y&z , !(x&z|y)|x&y&z , !(!x&!y|x&y|z)|x&y&z , !(x&y|z)|x&y&z , !(!x&!y|x&y|z)|!x&!y&z|x&y&z , !((x|y)&z|x&y)|x&y&z , !y&!z&x|y&z , !y&!z|y&z , !x&z|!y&!z&x|y&z , !(x&z|y)|y&z , !x&y|!y&!z&x|y&z , !(x&y|z)|y&z , !x&(y|z)|!y&!z&x|y&z , !x|!y&!z|y&z , x&z , !(x|y|z)|x&z , !y&z|x&z , !x&!y|x&z , !x&!z&y|x&z , !x&!z|x&z , !x&!z&y|!y&z|x&z , !(x|y&z)|x&z , (x|y)&z , !(x|y|z)|(x|y)&z , z , !x&!y|z , !x&y|x&z , !(!y&z|x)|x&z , !x&y|z , !x|z , !y&x|x&z , !y&!z|x&z , !y&(x|z)|x&z , !y|x&z , !x&!z&y|!y&x|x&z , !(x&y|z)|x&z , !x&!z&y|!y&(x|z)|x&z , !x&!z|!y|x&z , !y&x|y&z , !(!x&z|y)|y&z , !y&x|z , !y|z , !x&y|!y&x|x&z , !x&!z|!y&x|y&z , !x&y|!y&x|z , !x|!y|z , x&y , !(x|y|z)|x&y , !x&!y&z|x&y , !x&!y|x&y , !z&y|x&y , !x&!z|x&y , !x&!y&z|!z&y|x&y , !(x|y&z)|x&y , (x|z)&y , !(x|y|z)|(x|z)&y , !x&z|x&y , !(!z&y|x)|x&y , y , !x&!z|y , !x&z|y , !x|y , !z&x|x&y , !y&!z|x&y , !x&!y&z|!z&x|x&y , !(x&z|y)|x&y , !z&(x|y)|x&y , !z|x&y , !x&!y&z|!z&(x|y)|x&y , !x&!y|!z|x&y , !z&x|y&z , !(!x&y|z)|y&z , !x&z|!z&x|x&y , !x&!y|!z&x|y&z , !z&x|y , !z|y , !x&z|!z&x|y , !x|!z|y , (y|z)&x , !(x|y|z)|(y|z)&x , !y&z|x&y , !(!z&x|y)|x&y , !z&y|x&z , !(!y&x|z)|x&z , !y&z|!z&y|x&y , !x&!y|!z&y|x&z , (x|y)&z|x&y , !(x|y|z)|(x|y)&z|x&y , x&y|z , !x&!y|x&y|z , x&z|y , !x&!z|x&z|y , y|z , !x|y|z , x , !y&!z|x , !y&z|x , !y|x , !z&y|x , !z|x , !y&z|!z&y|x , !y|!z|x , x|y&z , !y&!z|x|y&z , x|z , !y|x|z , x|y , !z|x|y , x|y|z , !x|x }; int main() { cin >> n; for (int i = 0; i < n; ++i) { cin >> s; int x = 0; for (int j = 0; j < 8; ++j) { x += (s[j] - 0 ) * (1 << j); } cout << precalced[x] << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; string tolower(string str) { for (int i = 0; i < str.size(); i++) str[i] = tolower(str[i]); return str; } int main() { int n; cin >> n; vector<string> store; for (int i = 0; i < n; i++) { string str; cin >> str; store.push_back(tolower(str)); } string str, temp, ans = ; cin >> temp; vector<int> color(temp.size()); str = tolower(temp); char letter; cin >> letter; for (int i = 0; i < str.size(); i++) { for (int j = 0; j < store.size(); j++) { string& here = store[j]; if (i + here.size() <= str.size()) { string substr = str.substr(i, here.size()); if (substr == here) { for (int k = i; k < i + here.size(); k++) color[k] = 1; } } } } char second = (letter == a ) ? b : a ; for (int i = 0; i < str.size(); i++) { if (color[i]) ans += (str[i] == letter) ? second : letter; else ans += str[i]; if (isupper(temp[i])) ans[i] = toupper(ans[i]); } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; long long a[1010000]; inline bool read(long long &num) { char in; bool IsN = false; in = getchar(); if (in == EOF) return false; while (in != - && (in < 0 || in > 9 )) in = getchar(); if (in == - ) { IsN = true; num = 0; } else num = in - 0 ; while (in = getchar(), in >= 0 && in <= 9 ) { num *= 10, num += in - 0 ; } if (IsN) num = -num; return true; } int main() { long long n; scanf( %lld , &n); long long sum = 0; for (long long i = 1; i <= n; i++) { read(a[i]); sum += a[i]; } if (n == 1) { printf( %lld n , a[1]); return 0; } if ((sum - (n * (n - 1) / 2)) % n == 0) { long long x = (sum - (n * (n - 1) / 2)) / n; for (long long i = 1; i < n; i++) printf( %lld , x + i - 1); printf( %lld n , x + n - 1); return 0; } for (long long i = 1; i <= n; i++) { if ((sum - (n * (n - 1) / 2) + i) % n == 0) { long long x = (i + sum - (n * (n - 1) / 2)) / n, nd = x + n - i - 1; for (long long j = 1; j < n - 1; j++) { printf( %lld , x); if (x == nd) printf( %lld , x); x++; } if (x == nd) printf( %lld , x); printf( %lld n , x); return 0; } } }
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// file: pll_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module pll_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
localparam NUM_C = 2;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk_n;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
pll clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]));
genvar clk_out_pins;
generate
for (clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1)
begin: gen_outclk_oddr
assign clk_n[clk_out_pins] = ~clk[clk_out_pins];
ODDR2 clkout_oddr
(.Q (CLK_OUT[clk_out_pins]),
.C0 (clk[clk_out_pins]),
.C1 (clk_n[clk_out_pins]),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "i2c/i2c.v"
`include "i2c/i2c_core.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/clock_divider.v"
`include "utils/ODDR_sim.v"
`include "utils/IDDR_sim.v"
module i2c_slave_model (
input wire SCL,
inout wire SDA
);
parameter ADDRESS = 7'b1001001;
reg START;
//initial START = 1;
always @(negedge SDA or negedge SCL)
if(~SCL)
START <= 0;
else
START <= 1;
reg [7:0] REC_ADDRESS;
localparam STATE_IDLE = 0, STATE_START = 1, STATE_ADDR = 2, STATE_AACK = 4, STATE_DATA_W = 5, STATE_DATA_R = 6, STATE_DACK_W = 7, STATE_DACK_R = 8, STATE_DACK_LAST = 9, STATE_STOP = 10;
reg [3:0] state, next_state;
reg [2:0] bit_count;
reg [15:0] byte_count;
initial state = STATE_IDLE;
always @(posedge SCL or posedge START) begin
if (START)
state <= STATE_ADDR;
else
state <= next_state;
end
//rec stop
always @(*) begin
next_state = state;
case(state)
STATE_IDLE:
next_state = state;
STATE_ADDR:
if(bit_count==7)
next_state = STATE_AACK;
STATE_AACK:
if(REC_ADDRESS[7:1] == ADDRESS) begin
if(REC_ADDRESS[0])
next_state = STATE_DATA_R;
else
next_state = STATE_DATA_W;
end
else
next_state = STATE_IDLE;
STATE_DATA_R:
if(bit_count==7)
next_state = STATE_DACK_R;
STATE_DATA_W:
if(bit_count==7)
next_state = STATE_DACK_W;
STATE_DACK_W:
next_state = STATE_DATA_W;
STATE_DACK_R:
if(SDA==0)
next_state = STATE_DATA_R;
else
next_state = STATE_IDLE;
endcase
end
always @(posedge SCL or posedge START) begin
if(START)
bit_count <= 0;
else if (state == STATE_AACK | state == STATE_DACK_R | state == STATE_DACK_W )
bit_count <= 0;
else
bit_count <= bit_count + 1;
end
always @(posedge SCL or posedge START) begin
if (START)
byte_count <= 0;
else if(next_state == STATE_DACK_W | next_state == STATE_DACK_R)
byte_count <= byte_count + 1;
end
always @(posedge SCL)
if(state == STATE_ADDR)
REC_ADDRESS[7-bit_count] = SDA;
reg [7:0] BYTE_DATA_IN;
always @(posedge SCL)
if(state == STATE_DATA_W)
BYTE_DATA_IN[7-bit_count] = SDA;
reg [7:0] mem_addr;
always @(posedge SCL) begin
if(byte_count == 0 & next_state == STATE_DACK_W )
mem_addr <= BYTE_DATA_IN;
else if(next_state == STATE_DACK_R | next_state == STATE_DACK_W)
mem_addr <= mem_addr + 1;
end
reg [7:0] mem [255:0];
wire MEM_WE;
assign MEM_WE = next_state == STATE_DACK_W & byte_count != 0;
always @(posedge SCL or posedge START)
if(MEM_WE) begin
mem[mem_addr] <= BYTE_DATA_IN;
end
wire [7:0] BYTE_DATA_OUT;
assign BYTE_DATA_OUT = mem[mem_addr];
wire SDA_PRE;
assign SDA_PRE = ((state == STATE_AACK & REC_ADDRESS[7:1] == ADDRESS) | state == STATE_DACK_W) ? 1'b0 : state == STATE_DATA_R ? BYTE_DATA_OUT[7-bit_count] : 1;
reg SDAR;
initial SDAR = 1;
always @(negedge SCL)
SDAR <= SDA_PRE;
assign SDA = SDAR ? 1'bz : 1'b0;
endmodule
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam I2C_BASEADDR = 32'h1000;
localparam I2C_HIGHADDR = 32'h2000-1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire I2C_CLK;
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(I2C_CLK)
);
wire SDA, SCL;
pullup isda (SDA);
pullup iscl (SCL);
i2c #(
.BASEADDR(I2C_BASEADDR),
.HIGHADDR(I2C_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(32)
) i_i2c (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.I2C_CLK(I2C_CLK),
.I2C_SDA(SDA),
.I2C_SCL(SCL)
);
i2c_slave_model ii2c_slave_model (.SDA(SDA), .SCL(SCL));
initial begin
$dumpfile("i2c.vcd");
$dumpvars(0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_TB_V
`define SKY130_FD_SC_HVL__AND3_TB_V
/**
* and3: 3-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__and3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hvl__and3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_TB_V
|
#include <bits/stdc++.h> using namespace std; int isTandom(string s, int n) { if (n > s.size() / 2) return 0; for (int i = 0; i < n; i++) if (s[i + n] != && s[i] != s[i + n]) return 0; return 1; } int main() { string s; int k; cin >> s >> k; int len = s.size(); for (int i = 0; i < k; i++) s += ; for (int i = s.size() / 2; i >= 1; i--) for (int j = 0; j + i < s.size(); j++) if (isTandom((s.substr(j, 2 * i)), i)) { cout << 2 * i << endl; return 0; } return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:12 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_util_vector_logic_0_0 -prefix
// RAT_util_vector_logic_0_0_ RAT_util_vector_logic_0_0_stub.v
// Design : RAT_util_vector_logic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_vector_logic,Vivado 2016.4" *)
module RAT_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__XOR3_PP_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_PP_BLACKBOX_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: fr_cycle_shifter.v
//
// The fr-cycle shifter shifts the input data by X number of full-rate-cycles, where X is specified by the shift_by port.
// datain is a bus that combines data of multiple full rate cycles, in specific time order. For example,
// in a quarter-rate system, the datain bus must be ordered as {T3, T2, T1, T0}, where Ty represents the y'th fr-cycle
// data item, of width DATA_WIDTH. The following illustrates outputs at the dataout port for various values of shift_by.
// "__" means don't-care.
//
// shift_by dataout in current cycle dataout in next clock cycle
// 00 {T3, T2, T1, T0} {__, __, __, __}
// 01 {T2, T1, T0, __} {__, __, __, T3}
// 10 {T1, T0, __, __} {__, __, T3, T2}
// 11 {T0, __, __, __} {__, T3, T2, T1}
//
// In full-rate or half-rate systems, only the least-significant bit of shift-by has an effect
// (i.e. you can only shift by 0 or 1 fr-cycle).
// In quarter-rate systems, all bits of shift_by are used (i.e. you can shift by 0, 1, 2, or 3 fr-cycles).
//
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module altera_mem_if_ddr3_phy_0001_fr_cycle_shifter(
clk,
reset_n,
shift_by,
datain,
dataout
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DATA_WIDTH = "";
parameter REG_POST_RESET_HIGH = "false";
localparam RATE_MULT = 2;
localparam FULL_DATA_WIDTH = DATA_WIDTH*RATE_MULT;
// END PARAMETER SECTION
// ********************************************************************************************************************************
input clk;
input reset_n;
input [1:0] shift_by;
input [FULL_DATA_WIDTH-1:0] datain;
output [FULL_DATA_WIDTH-1:0] dataout;
reg [FULL_DATA_WIDTH-1:0] datain_r;
always @(posedge clk or negedge reset_n)
begin
if (~reset_n) begin
if (REG_POST_RESET_HIGH == "true")
datain_r <= {FULL_DATA_WIDTH{1'b1}};
else
datain_r <= {FULL_DATA_WIDTH{1'b0}};
end else begin
datain_r <= datain;
end
end
wire [DATA_WIDTH-1:0] datain_t0 = datain[(DATA_WIDTH*1)-1:(DATA_WIDTH*0)];
wire [DATA_WIDTH-1:0] datain_t1 = datain[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
wire [DATA_WIDTH-1:0] datain_r_t1 = datain_r[(DATA_WIDTH*2)-1:(DATA_WIDTH*1)];
assign dataout = (shift_by[0] == 1'b1) ? {datain_t0, datain_r_t1} : {datain_t1, datain_t0};
endmodule
|
`timescale 1 ns / 1 ps
module axis_histogram #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 14
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
output wire bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [BRAM_DATA_WIDTH-1:0] int_data_reg, int_data_next;
reg [2:0] int_case_reg, int_case_next;
reg int_tready_reg, int_tready_next;
reg int_wren_reg, int_wren_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_data_reg <= {(BRAM_DATA_WIDTH){1'b0}};
int_case_reg <= 3'd0;
int_tready_reg <= 1'b0;
int_wren_reg <= 1'b0;
end
else
begin
int_addr_reg <= int_addr_next;
int_data_reg <= int_data_next;
int_case_reg <= int_case_next;
int_tready_reg <= int_tready_next;
int_wren_reg <= int_wren_next;
end
end
always @*
begin
int_addr_next = int_addr_reg;
int_data_next = int_data_reg;
int_case_next = int_case_reg;
int_tready_next = int_tready_reg;
int_wren_next = int_wren_reg;
case(int_case_reg)
0:
begin
int_addr_next = {(BRAM_ADDR_WIDTH){1'b0}};
int_data_next = {(BRAM_DATA_WIDTH){1'b0}};
int_wren_next = 1'b1;
int_case_next = 3'd1;
end
1:
begin
// write zeros
int_addr_next = int_addr_reg + 1'b1;
if(&int_addr_reg)
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 3'd2;
end
end
2:
begin
if(s_axis_tvalid)
begin
int_addr_next = s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
int_tready_next = 1'b0;
int_case_next = 3'd3;
end
end
3:
begin
int_case_next = 3'd4;
end
4:
begin
int_data_next = bram_porta_rddata + 1'b1;
int_wren_next = ~&bram_porta_rddata;
int_case_next = 3'd5;
end
5:
begin
int_tready_next = 1'b1;
int_wren_next = 1'b0;
int_case_next = 3'd2;
end
endcase
end
assign s_axis_tready = int_tready_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_wren_reg ? int_addr_reg : s_axis_tdata[BRAM_ADDR_WIDTH-1:0];
assign bram_porta_wrdata = int_data_reg;
assign bram_porta_we = int_wren_reg;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iob_jbi_rptr_0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module iob_jbi_rptr_0 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
endmodule
|
`define bsg_dff_reset_macro(bits) \
if (harden_p && width_p==bits) \
begin: macro \
bsg_rp_tsmc_250_dff_nreset_s1_b``bits dff(.clock_i \
,.data_i \
,.nreset_i(~reset_i) \
,.data_o); \
end
module bsg_dff_reset #(width_p=-1, harden_p=1)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_reset_macro(90)
else `bsg_dff_reset_macro(89)
else `bsg_dff_reset_macro(88)
else `bsg_dff_reset_macro(87)
else `bsg_dff_reset_macro(86)
else `bsg_dff_reset_macro(85)
else `bsg_dff_reset_macro(84)
else `bsg_dff_reset_macro(83)
else `bsg_dff_reset_macro(82)
else `bsg_dff_reset_macro(81)
else `bsg_dff_reset_macro(80)
else `bsg_dff_reset_macro(79)
else `bsg_dff_reset_macro(78)
else `bsg_dff_reset_macro(77)
else `bsg_dff_reset_macro(76)
else `bsg_dff_reset_macro(75)
else `bsg_dff_reset_macro(74)
else `bsg_dff_reset_macro(73)
else `bsg_dff_reset_macro(72)
else `bsg_dff_reset_macro(71)
else `bsg_dff_reset_macro(70)
else `bsg_dff_reset_macro(69)
else `bsg_dff_reset_macro(68)
else `bsg_dff_reset_macro(67)
else `bsg_dff_reset_macro(66)
else `bsg_dff_reset_macro(65)
else `bsg_dff_reset_macro(64)
else `bsg_dff_reset_macro(63)
else `bsg_dff_reset_macro(62)
else `bsg_dff_reset_macro(61)
else `bsg_dff_reset_macro(60)
else `bsg_dff_reset_macro(59)
else `bsg_dff_reset_macro(58)
else `bsg_dff_reset_macro(57)
else `bsg_dff_reset_macro(56)
else `bsg_dff_reset_macro(55)
else `bsg_dff_reset_macro(54)
else `bsg_dff_reset_macro(53)
else `bsg_dff_reset_macro(52)
else `bsg_dff_reset_macro(51)
else `bsg_dff_reset_macro(50)
else `bsg_dff_reset_macro(49)
else `bsg_dff_reset_macro(48)
else `bsg_dff_reset_macro(47)
else `bsg_dff_reset_macro(46)
else `bsg_dff_reset_macro(45)
else `bsg_dff_reset_macro(44)
else `bsg_dff_reset_macro(43)
else `bsg_dff_reset_macro(42)
else `bsg_dff_reset_macro(41)
else `bsg_dff_reset_macro(40)
else `bsg_dff_reset_macro(39)
else `bsg_dff_reset_macro(38)
else `bsg_dff_reset_macro(37)
else `bsg_dff_reset_macro(36)
else `bsg_dff_reset_macro(35)
else `bsg_dff_reset_macro(34)
else `bsg_dff_reset_macro(33)
else `bsg_dff_reset_macro(32)
else `bsg_dff_reset_macro(31)
else `bsg_dff_reset_macro(30)
else `bsg_dff_reset_macro(29)
else `bsg_dff_reset_macro(28)
else `bsg_dff_reset_macro(27)
else `bsg_dff_reset_macro(26)
else `bsg_dff_reset_macro(25)
else `bsg_dff_reset_macro(24)
else `bsg_dff_reset_macro(23)
else `bsg_dff_reset_macro(22)
else `bsg_dff_reset_macro(21)
else `bsg_dff_reset_macro(20)
else `bsg_dff_reset_macro(19)
else `bsg_dff_reset_macro(18)
else `bsg_dff_reset_macro(17)
else `bsg_dff_reset_macro(16)
else `bsg_dff_reset_macro(15)
else `bsg_dff_reset_macro(14)
else `bsg_dff_reset_macro(13)
else `bsg_dff_reset_macro(12)
else `bsg_dff_reset_macro(11)
else `bsg_dff_reset_macro(10)
else `bsg_dff_reset_macro(9)
else `bsg_dff_reset_macro(8)
else `bsg_dff_reset_macro(7)
else `bsg_dff_reset_macro(6)
else `bsg_dff_reset_macro(5)
else `bsg_dff_reset_macro(4)
else `bsg_dff_reset_macro(3)
else
begin: notmacro_dff_reset
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
begin
if (reset_i)
data_r <= width_p ' (0);
else
data_r <= data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_reset)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_BEHAVIORAL_V
|
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file Data_Mem.v when simulating
// the core, Data_Mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module Data_Mem(
a,
d,
clk,
we,
spo);
input [5 : 0] a;
input [31 : 0] d;
input clk;
input we;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("spartan3"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("Data_Mem.mif"),
.C_MEM_TYPE(1),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.D(d),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPRA(),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of Data_Mem is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, fact[200001], a[200005]; long long power(long long a, long long b) { if (b == 0) return 1; long long p = power(a, b / 2); p = ((p % 1000000007) * (p % 1000000007)) % 1000000007; if (b & 1) { return (a * p) % 1000000007; } return p; } long long mod_inv(long long n, long long m) { long long div = power((fact[n - m] * fact[m]) % 1000000007, 1000000007 - 2); return (fact[n] * div) % 1000000007; } int main() { fact[0] = 1; for (int i = 1; i <= 200000; i++) { fact[i] = (fact[i - 1] * i) % 1000000007; } scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); } long long ans = 0; if (n % 4 == 0) { n = n - 2; n /= 2; for (int i = 0; i < n * 2 + 2; i++) { if (i & 1) { ans -= ((mod_inv(n, i / 2)) * a[i]) % 1000000007; ans = (ans + 1000000007) % 1000000007; } else { ans += ((mod_inv(n, i / 2)) * a[i]) % 1000000007; ; ans = (ans + 1000000007) % 1000000007; } } } else if (n % 4 == 1) { long long sz = n; n = n - 1; n /= 2; for (int i = 0; i < sz; i += 2) { ans += ((mod_inv(n, i / 2)) * a[i]) % 1000000007; ans = (ans + 1000000007) % 1000000007; } } else if (n % 4 == 2) { long long sz = n; n = n - 2; n /= 2; for (int i = 0; i < sz; i++) { ans += ((mod_inv(n, i / 2)) * a[i]) % 1000000007; ; ans = (ans + 1000000007) % 1000000007; } } else { long long sz = n; n = n - 3; n /= 2; ans = (a[0] * mod_inv(n, 0)) % 1000000007; for (int i = 1; i < sz; i++) { if (i & 1) { ans += (2 * (mod_inv(n, i / 2)) * a[i]) % 1000000007; ; ans = ans = (ans + 1000000007) % 1000000007; } else { ans += ((mod_inv(n, i / 2) - mod_inv(n, (i / 2) - 1)) * a[i]) % 1000000007; ans = (ans + 1000000007) % 1000000007; } } } cout << ans << endl; return 0; }
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - always release net_lvalue ;
// D: No dependancy
module main ;
wire [3:0] value1 ;
initial
begin
#15;
if(value1 != 4'h5)
$display("FAILED - 3.1.3H always release net_lvalue;\n");
else
begin
$display("PASSED\n");
$finish;
end
end
always release value1 ;
endmodule
|
#include <bits/stdc++.h> using int_t = long long int; template <typename T, typename FirstOp = std::plus<T>, typename SecondOp = std::multiplies<T>, typename UpdateOp = std::plus<T>> class SegmentTree { public: explicit SegmentTree(std::size_t size, FirstOp first_operation = FirstOp(), SecondOp second_operation = SecondOp(), UpdateOp update_operation = UpdateOp(), T identity = T()) : m_size(size), m_tree(std::max(size * 4, std::size_t(4)), identity), m_lazy_tag(std::max(size * 4, std::size_t(4)), identity), m_first_operation(first_operation), m_second_operation(second_operation), m_update_operation(update_operation), m_identity(identity) {} void update(std::size_t pos, const T& value) { update(pos + 1, value, 1, 1, m_size); } void update(std::size_t start, std::size_t end, const T& value) { update(start + 1, end, value, 1, 1, m_size); } T query(std::size_t start, std::size_t end) { return query(start + 1, end, 1, 1, m_size); } private: std::size_t m_size; std::vector<T> m_tree; std::vector<T> m_lazy_tag; FirstOp m_first_operation; SecondOp m_second_operation; UpdateOp m_update_operation; const T m_identity; void push_up(std::size_t root) { m_tree[root] = m_first_operation(m_tree[left(root)], m_tree[right(root)]); } void push_down(std::size_t root, std::size_t length) { m_tree[left(root)] = m_update_operation( m_tree[left(root)], m_second_operation(m_lazy_tag[root], length - length / 2)); m_lazy_tag[left(root)] = m_update_operation(m_lazy_tag[left(root)], m_lazy_tag[root]); m_tree[right(root)] = m_update_operation( m_tree[right(root)], m_second_operation(m_lazy_tag[root], length / 2)); m_lazy_tag[right(root)] = m_update_operation(m_lazy_tag[right(root)], m_lazy_tag[root]); m_lazy_tag[root] = m_identity; } void update(std::size_t pos, const T& value, std::size_t root, std::size_t l, std::size_t r) { if (l == r) { m_tree[root] = m_update_operation(m_tree[root], value); return; } std::size_t m = (l + r) / 2; if (pos <= m) { update(pos, value, left(root), l, m); } else { update(pos, value, right(root), m + 1, r); } push_up(root); } void update(std::size_t start, std::size_t end, const T& value, std::size_t root, std::size_t l, std::size_t r) { if (start <= l && r <= end) { m_tree[root] = m_update_operation(m_tree[root], m_second_operation(value, r - l + 1)); m_lazy_tag[root] = m_update_operation(m_lazy_tag[root], value); return; } if (m_lazy_tag[root] != m_identity) { push_down(root, r - l + 1); } std::size_t m = (l + r) / 2; if (start <= m) { update(start, end, value, left(root), l, m); } if (m < end) { update(start, end, value, right(root), m + 1, r); } push_up(root); } T query(std::size_t start, std::size_t end, std::size_t root, std::size_t l, std::size_t r) { if (start <= l && r <= end) { return m_tree[root]; } if (m_lazy_tag[root] != m_identity) { push_down(root, r - l + 1); } std::size_t m = (l + r) / 2; if (start <= m && m < end) { return m_first_operation(query(start, end, left(root), l, m), query(start, end, right(root), m + 1, r)); } else if (end <= m) { return query(start, end, left(root), l, m); } else { return query(start, end, right(root), m + 1, r); } } static std::size_t left(std::size_t root) { return root * 2; } static std::size_t right(std::size_t root) { return root * 2 + 1; } }; int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); int_t m; std::cin >> m; std::vector<int_t> x(m); struct FirstOp { int_t operator()(int_t lhs, int_t rhs) const { return std::max(lhs, rhs); } }; struct SecondOp { int_t operator()(int_t x, std::size_t) const { return x; } }; SegmentTree<int_t, FirstOp, SecondOp> segment_tree(m); for (int_t i = 0; i < m; ++i) { int_t p; int_t t; std::cin >> p >> t; int_t index = m - p; if (t == 0) { segment_tree.update(index, m, -1); } else { std::cin >> x[index]; segment_tree.update(index, m, 1); } if (m == 1) { if (segment_tree.query(0, 1) > 0) { std::cout << x[0] << n ; } else { std::cout << -1 << n ; } continue; } int_t start = 0; int_t end = m; while (start < end - 1) { int_t mid = (start + end - 1) / 2; if (segment_tree.query(start, mid + 1) > 0) { end = mid + 1; } else if (segment_tree.query(mid, end) > 0) { start = mid + 1; } else { start = end = -1; } } if (start == -1) { std::cout << -1 << n ; } else { std::cout << x[start] << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int gi() { char cc = getchar(); int cn = 0, flus = 1; while (cc < 0 || cc > 9 ) { if (cc == - ) flus = -flus; cc = getchar(); } while (cc >= 0 && cc <= 9 ) cn = cn * 10 + cc - 0 , cc = getchar(); return cn * flus; } const int N = 3e5 + 5; int n, q, a[N], g[20], f[N][20]; signed main() { n = gi(), q = gi(); for (register int i = (1); i <= (n); ++i) a[i] = gi(); for (register int i = (0); i <= (19); ++i) g[i] = n + 1; memset(f, 63, sizeof(f)); for (register int i = n; i >= 1; --i) { for (register int j = (0); j <= (19); ++j) if ((1 << j) & a[i]) f[i][j] = i; for (register int j = (0); j <= (19); ++j) if ((1 << j) & a[i]) for (register int k = (0); k <= (19); ++k) f[i][k] = min(f[i][k], f[g[j]][k]); for (register int j = (0); j <= (19); ++j) if ((1 << j) & a[i]) g[j] = i; } while (q--) { int x = gi(), y = gi(); int flag = 0; for (register int j = (0); j <= (19); ++j) if ((1 << j) & a[y]) flag |= (f[x][j] <= y); (flag) ? puts( Shi ) : puts( Fou ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k, tlen = 0, dir, i; string temp; cin >> n >> m >> k; cin >> temp >> temp; if (temp == head ) dir = -1; else dir = 1; cin >> temp; if (m < k) m = 1; else m = n; for (i = 0; i < temp.size(); ++i) { if (k == 1) dir = 1; else if (k == n) dir = -1; k += dir; if (temp[i] != 1 ) { if (k == m) { cout << Controller << i + 1; return 0; } } else { if (dir == -1) m = n; else m = 1; } } cout << Stowaway ; return 0; }
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [11:0] c;
// Output of stage 2
wire [11:0] cx;
// Output of stage 3
wire [7:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [7:0] b;
reg [7:0] r_b;
reg [11:0] e;
reg [11:0] r_e;
// 2nd stage
reg [11:0] r_c;
reg [11:0] rr_e;
reg [7:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [11:0] cx;
//reg [10:0] qx;
reg [11:0] r_qx;
reg [7:0] rb;
reg clk,reset;
reg [11:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000100000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000100000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:51:28 08/18/2015
// Design Name:
// Module Name: Comparator_Equal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//This comparator is exclusive to comparate the sign bits (1 Bit width) of the operands,
//the result is useful to take decisions about add or subtract significands
//in the third phase of execution
module Comparator_Equal
//It needs to be adjustable because it's used in two modules,
//but this parameter is not a function of the width of the format
# (parameter S = 1)
(
input wire [S-1:0] Data_A,
input wire [S-1:0] Data_B,
output wire equal_sgn
);
assign equal_sgn = (Data_A == Data_B) ? 1'b1 : 1'b0;
//The result is 1 if the signs are equal otherwise is 0.
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_fpext_32ns_64_1
#(parameter
ID = 3,
NUM_STAGE = 1,
din0_WIDTH = 32,
dout_WIDTH = 64
)(
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
//------------------------Instantiation------------------
HLS_accel_ap_fpext_0_no_dsp_32 HLS_accel_ap_fpext_0_no_dsp_32_u (
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign a_tvalid = 1'b1;
assign a_tdata = din0==='bx ? 'b0 : din0;
assign dout = r_tdata;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_PP_SYMBOL_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue <= # (mintypmax_expression) boolean_expr ;
// D: This guy doesn't stop..
module main ;
reg [3:0] value1 ;
initial
begin
# 3; /* Wait till here to verify didn't see 2ns delay! */
if(value1 !== 4'hx)
$display("FAILED - always reg_lvalue <= # (mintypmax_expression) boolean_expr \n");
#12 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue <= # (mintypmax_expression) boolean_expr \n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 <= # (2:10:17) 1'b1 && 1'b1 ;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_outputcontrol.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
// Revision 1.2 2005/04/27 15:58:46 Administrator
// no message
//
// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
// no message
//
// Revision 1.4 2002/07/09 20:11:59 mohor
// Comment removed.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:56 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`timescale 1ns/10ps
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= #Tp 1'b0;
MdoEn_d <= #Tp 1'b0;
MdoEn <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
MdoEn_d <= #Tp MdoEn_2d;
MdoEn <= #Tp MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= #Tp 1'b0;
Mdo_d <= #Tp 1'b0;
Mdo <= #Tp 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
Mdo_d <= #Tp ShiftedBit | Mdo_2d;
Mdo <= #Tp Mdo_d;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_LP__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int fin(int rem) { for (auto p : mp) { if (p.first >= rem) return p.first; } return -1; } int main() { long long ans = 0, rem = 0, p, x, y, n, RES = 1e9; cin >> n >> x >> y; long long a[] = {x, x, x, x, y, y}; sort(a, a + 6); do { mp.clear(); ans = 0; for (int i = 0; i < 6; ++i) { if ((x = fin(a[i])) == -1) { ++ans; ++mp[n - a[i]]; } else { ++mp[x - a[i]]; if (!--mp[x]) mp.erase(x); } } RES = min(RES, ans); } while (next_permutation(a, a + 6)); cout << RES; }
|
#include <bits/stdc++.h> using namespace std; vector<int> print; const int Maxn = int(1e2) + 10; int primes[20] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59}; int n, a[Maxn], xrn[60 + 10], dp[Maxn][(1 << 18) + 1000], adad[Maxn][(1 << 18) + 1000]; void xr() { for (int(i) = (1); (i) < (60); ++(i)) { for (int(j) = (0); (j) < (17); ++(j)) if (i % primes[j] == 0) xrn[i] |= (1 << j); } } int main() { xr(); cin >> n; for (int(i) = (1); (i) < (n + 1); ++(i)) cin >> a[i]; for (int(i) = (0); (i) < (n + 1); ++(i)) for (int(j) = (0); (j) < ((1 << 17)); ++(j)) dp[i][j] = int(1e9) + 10; dp[0][0] = 0; for (int(i) = (1); (i) < (n + 1); ++(i)) for (int(j) = (0); (j) < ((1 << 17)); ++(j)) for (int(m) = (1); (m) < (60); ++(m)) if ((j & xrn[m]) == xrn[m]) { if (dp[i - 1][j - xrn[m]] + abs(m - a[i]) < dp[i][j]) dp[i][j] = dp[i - 1][j - xrn[m]] + abs(m - a[i]), adad[i][j] = m; } int ans = int(1e9) + 1000, ansj = 0; for (int(j) = (0); (j) < ((1 << 17)); ++(j)) if (dp[n][j] < ans) ans = dp[n][j], ansj = j; int r = n; while (r) { print.push_back(adad[r][ansj]); ansj -= xrn[adad[r][ansj]]; r--; } for (int i = print.size() - 1; i >= 0; --i) cout << print[i] << ; cout << endl; return 0; }
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ebc_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ebc_e.v,v 1.1 2004/04/06 10:50:49 wig Exp $
// $Date: 2004/04/06 10:50:49 $
// $Log: inst_ebc_e.v,v $
// Revision 1.1 2004/04/06 10:50:49 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ebc_e
//
// No `defines in this module
module inst_ebc_e
//
// Generated module inst_ebc
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ebc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long n, m, k; map<string, long long> mm; string a[100005]; long long c[100005]; long long min(long long a, long long b) { return a < b ? a : b; } int main() { cin >> n >> k >> m; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { long long x; cin >> x; mm[a[i]] = x; } for (int i = 0; i < k; i++) { long long x; cin >> x; long long minn = 0x3f3f3f3f; for (int j = 0; j < x; j++) { cin >> c[j]; minn = min(minn, mm[a[c[j]]]); } for (int j = 0; j < x; j++) { mm[a[c[j]]] = minn; } } string b; long long s = 0; for (int i = 0; i < m; i++) { cin >> b; s += mm[b]; } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 10; int arr[MAX]; int n; vector<int> v[MAX]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { cin >> n; for (int i = 0; i < n; ++i) v[i].clear(); for (int i = 0; i < n; ++i) { int x, y; cin >> x >> y; v[x].push_back(y); } long long ans = 0; priority_queue<int, vector<int>, greater<int> > q; for (int i = n - 1; i >= 0; --i) { for (auto &j : v[i]) q.push(j); while (q.size() > n - i) ans += q.top(), q.pop(); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long N, W; cin >> N >> W; long long lowest = 0, highest = W; long long current = 0, sum = 0; while (N--) { cin >> current; sum += current; lowest = max(lowest, -sum); highest = min(highest, W - sum); } cout << max(0ll, highest - lowest + 1) << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1510, INF = 1e9 + 9; int n, s, m, k, last[N], a[N], dp[N][N]; bool check(int x) { memset(dp, 0, sizeof dp); for (int i = 0; i < n; i++) { int val = 0; for (int j = last[i]; j <= i; j++) val += a[j] <= x; for (int j = 1; j <= m; j++) dp[i + 1][j] = max(dp[i][j], dp[last[i]][j - 1] + val); } return k <= dp[n][m]; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> s >> m >> k; for (int i = 0; i < n; i++) cin >> a[i]; fill(last, last + n, n + 1); while (s--) { int l, r; cin >> l >> r; for (int i = --l; i < r; i++) last[i] = min(last[i], l); } int l = 0, r = INF; while (r - l > 1) { int mid = l + r >> 1; check(mid) ? r = mid : l = mid; } cout << (r == INF ? -1 : r) << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; int a[MAXN]; int cnt[101][101]; int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { cin >> a[i]; cnt[i % k][a[i]]++; } int ans = 0; for (int i = 0; i < k; i++) { ans += min(cnt[i][1], cnt[i][2]); } cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:500000000 ) using namespace std; int A[105]; int f[105]; int main() { int n, i, p, x, y; cin >> n; for (i = 0; i < n; i++) cin >> A[i], f[A[i]] = i; int q; cin >> q; while (q--) { scanf( %d %d %d , &p, &x, &y); if (p == 1) { int res = 0; while (x <= y) { while (x < y && f[x + 1] > f[x]) x++; x++; res++; } printf( %d n , res); } else { x--; y--; int L = A[x], R = A[y]; swap(A[x], A[y]); f[L] = y; f[R] = x; } } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2021 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module testbench(
/*AUTOARG*/
// Inputs
clk
);
input clk; // Top level input clock
logic other_clk; // Dependent clock set via DPI
logic third_clk; // Additional dependent clock set via DPI
export "DPI-C" function set_other_clk;
function void set_other_clk(bit val);
other_clk = val;
endfunction;
export "DPI-C" function set_third_clk;
function void set_third_clk(bit val);
third_clk = val;
endfunction;
bit even_other = 1;
import "DPI-C" context function void toggle_other_clk(bit val);
always @(posedge clk) begin
even_other <= ~even_other;
toggle_other_clk(even_other);
end
bit even_third = 1;
import "DPI-C" context function void toggle_third_clk(bit val);
always @(posedge other_clk) begin
even_third <= ~even_third;
toggle_third_clk(even_third);
end
int n = 0;
wire final_clk = $c1("1") & third_clk;
always @(posedge final_clk) begin
$display("t=%d n=%d", $time, n);
if ($time != (8*n+1) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
n += 1;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_32s_39_3_Mul3S_1(clk, ce, a, b, p);
input clk;
input ce;
input[7 - 1 : 0] a; // synthesis attribute keep a "true"
input[32 - 1 : 0] b; // synthesis attribute keep b "true"
output[39 - 1 : 0] p;
reg [7 - 1 : 0] a_reg0;
reg signed [32 - 1 : 0] b_reg0;
wire signed [39 - 1 : 0] tmp_product;
reg signed [39 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = $signed({1'b0, a_reg0}) * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_mul_7ns_32s_39_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
feedforward_mul_7ns_32s_39_3_Mul3S_1 feedforward_mul_7ns_32s_39_3_Mul3S_1_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
///////Courtsey: design from asic-world.com////////////
//-----------------------------------------------------
// Design Name : lfsr
// File Name : lfsr.v
// Function : Linear feedback shift register
// Coder : Deepak Kumar Tala
// Modified by : Deepak Unnikrishnan, UMass Amherst
//-----------------------------------------------------
module lfsr #(
parameter ADDR_WIDTH=8,
parameter MAX_ADDR_VAL=256
) (
num_keys,
lfsr_out,
lfsr_start,
enable,
clk,
reset
);
//----------Output Ports--------------
//output wire [ADDR_WIDTH-1:0] lfsr_out;
output wire [31:0] lfsr_out;
//output reg [ADDR_WIDTH-1:0] lfsr_start;
output reg [31:0] lfsr_start;
//wire [ADDR_WIDTH-1:0] lfsr_start_next;
wire [31:0] lfsr_start_next;
//------------Input Ports--------------
input [31:0] num_keys;
input enable, clk, reset;
//------------Internal Variables--------
//reg [ADDR_WIDTH-1:0] out;
reg [31:0] out;
wire linear_feedback;
//wire [ADDR_WIDTH-1:0] out_shifted;
wire [31:0] out_shifted;
reg state, state_next;
reg [5:0] select;
wire [31:0] mask;
localparam NORMAL=0;
localparam PAUSE=1;
//assign lfsr_out = (state==NORMAL)?out:{ADDR_WIDTH{1'b1}};
assign lfsr_out = (state==NORMAL)?(out&mask):32'b1;
assign lfsr_start_next = lfsr_start;
assign mask = ~(~0<<select);
//-------------Code Starts Here-------
//---Define Linear Feedback polynomial here
/*
assign linear_feedback =
(ADDR_WIDTH==2) ? !(out[1] ^ out[0]): //1+x+x2
(ADDR_WIDTH==3) ? !(out[2] ^ out[1]): //1+x2+x3
(ADDR_WIDTH==4) ? !(out[3] ^ out[2]): //1+x3+x4
(ADDR_WIDTH==5) ? !(out[4] ^ out[2]): //1+x3+x5
(ADDR_WIDTH==6) ? !(out[5] ^ out[4]): //1+x5+x6
(ADDR_WIDTH==7) ? !(out[6] ^ out[5]): //1+x6+x7
(ADDR_WIDTH==8) ? !(out[7] ^ out[5] ^ out[4] ^ out[3]): //1+x4+x5+x6+x8
(ADDR_WIDTH==9) ? !(out[8] ^ out[4]): //1+x5+x9
(ADDR_WIDTH==10) ? !(out[9] ^ out[6]): //1+x7+x10
(ADDR_WIDTH==11) ? !(out[8] ^ out[10]): //1+x9+x11
(ADDR_WIDTH==12) ? !(out[11] ^ out[10] ^ out[9] ^ out[3]): //x12+x11+x10+x4+1
(ADDR_WIDTH==13) ? !(out[12] ^ out[11] ^ out[10] ^ out[7]): //x13+x12+x11+x8+1
(ADDR_WIDTH==14) ? !(out[13] ^ out[12] ^ out[11] ^ out[1]): //x14+x13+x12+x2+1
(ADDR_WIDTH==15) ? !(out[14] ^ out[13]): //x15+x14+1
(ADDR_WIDTH==16) ? !(out[15] ^ out[13] ^ out[12] ^ out[10]): //x16+x14+x13+x11+1
(ADDR_WIDTH==17) ? !(out[16] ^ out[13]): //x17+x14+1
(ADDR_WIDTH==18) ? !(out[17] ^ out[10]): //x18+x11+1
(ADDR_WIDTH==19) ? !(out[18] ^ out[17] ^ out[16] ^ out[13]): //x19+x18+x17+x14+1
(ADDR_WIDTH==20) ? !(out[19] ^ out[16]): //x20+x17+1
!(out[0] ^ out[1]);
*/
assign linear_feedback =
(select==2) ? !(out[1] ^ out[0]): //1+x+x2
(select==3) ? !(out[2] ^ out[1]): //1+x2+x3
(select==4) ? !(out[3] ^ out[2]): //1+x3+x4
(select==5) ? !(out[4] ^ out[2]): //1+x3+x5
(select==6) ? !(out[5] ^ out[4]): //1+x5+x6
(select==7) ? !(out[6] ^ out[5]): //1+x6+x7
(select==8) ? !(out[7] ^ out[5] ^ out[4] ^ out[3]): //1+x4+x5+x6+x8
(select==9) ? !(out[8] ^ out[4]): //1+x5+x9
(select==10) ? !(out[9] ^ out[6]): //1+x7+x10
(select==11) ? !(out[8] ^ out[10]): //1+x9+x11
(select==12) ? !(out[11] ^ out[10] ^ out[9] ^ out[3]): //x12+x11+x10+x4+1
(select==13) ? !(out[12] ^ out[11] ^ out[10] ^ out[7]): //x13+x12+x11+x8+1
(select==14) ? !(out[13] ^ out[12] ^ out[11] ^ out[1]): //x14+x13+x12+x2+1
(select==15) ? !(out[14] ^ out[13]): //x15+x14+1
(select==16) ? !(out[15] ^ out[13] ^ out[12] ^ out[10]): //x16+x14+x13+x11+1
(select==17) ? !(out[16] ^ out[13]): //x17+x14+1
(select==18) ? !(out[17] ^ out[10]): //x18+x11+1
(select==19) ? !(out[18] ^ out[17] ^ out[16] ^ out[13]): //x19+x18+x17+x14+1
(select==20) ? !(out[19] ^ out[16]): //x20+x17+1
(select==21) ? !(out[20] ^ out[18]): //x21+x19
(select==22) ? !(out[21] ^ out[20]): //x22+x21
(select==23) ? !(out[22] ^ out[17]): //x23+x18
!(out[0] ^ out[1]);
//use a priority encoder to choose the LFSR feedback selection
always@(*)
begin
casex(num_keys)
32'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: select = 32;
32'b01xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: select = 31;
32'b001xxxxxxxxxxxxxxxxxxxxxxxxxxxxx: select = 30;
32'b0001xxxxxxxxxxxxxxxxxxxxxxxxxxxx: select = 29;
32'b00001xxxxxxxxxxxxxxxxxxxxxxxxxxx: select = 28;
32'b000001xxxxxxxxxxxxxxxxxxxxxxxxxx: select = 27;
32'b0000001xxxxxxxxxxxxxxxxxxxxxxxxx: select = 26;
32'b00000001xxxxxxxxxxxxxxxxxxxxxxxx: select = 25;
32'b000000001xxxxxxxxxxxxxxxxxxxxxxx: select = 24;
32'b0000000001xxxxxxxxxxxxxxxxxxxxxx: select = 23;
32'b00000000001xxxxxxxxxxxxxxxxxxxxx: select = 22;
32'b000000000001xxxxxxxxxxxxxxxxxxxx: select = 21;
32'b0000000000001xxxxxxxxxxxxxxxxxxx: select = 20;
32'b00000000000001xxxxxxxxxxxxxxxxxx: select = 19;
32'b000000000000001xxxxxxxxxxxxxxxxx: select = 18;
32'b0000000000000001xxxxxxxxxxxxxxxx: select = 17;
32'b00000000000000001xxxxxxxxxxxxxxx: select = 16;
32'b000000000000000001xxxxxxxxxxxxxx: select = 15;
32'b0000000000000000001xxxxxxxxxxxxx: select = 14;
32'b00000000000000000001xxxxxxxxxxxx: select = 13;
32'b000000000000000000001xxxxxxxxxxx: select = 12;
32'b0000000000000000000001xxxxxxxxxx: select = 11;
32'b00000000000000000000001xxxxxxxxx: select = 10;
32'b000000000000000000000001xxxxxxxx: select = 9;
32'b0000000000000000000000001xxxxxxx: select = 8;
32'b00000000000000000000000001xxxxxx: select = 7;
32'b000000000000000000000000001xxxxx: select = 6;
32'b0000000000000000000000000001xxxx: select = 5;
32'b00000000000000000000000000001xxx: select = 4;
32'b000000000000000000000000000001xx: select = 3;
32'b0000000000000000000000000000001x: select = 2;
32'b00000000000000000000000000000001: select = 1;
default: select = 0;
endcase
end
//(ADDR_WIDTH==2) ? !(out[7] ^ out[3]):
genvar i;
generate
for(i=0;i<32;i=i+1) begin: lfeedback
if(i==0)
assign out_shifted[i] = linear_feedback;
else
assign out_shifted[i] = out[i-1];
end
endgenerate
always @(posedge clk or posedge reset)
if (reset) begin // active high reset
out <= 0 ;
end else if (enable && state==NORMAL) begin
out <= out_shifted;
end
always@(*) begin
state_next = state;
case(state)
NORMAL: begin
if(out_shifted==0)
state_next = (enable)?PAUSE:NORMAL;
end
PAUSE: begin
state_next = (enable)?NORMAL:PAUSE;
end
default: state_next = NORMAL;
endcase
end
always@(posedge clk or posedge reset) begin
if(reset)
//lfsr_start <= out_shifted[ADDR_WIDTH-1:0]; //Capture the start value of the LFSR registe
lfsr_start <= out_shifted; //Capture the start value of the LFSR registe
else
lfsr_start <= lfsr_start_next;
end
always@(posedge clk or posedge reset) begin
if(reset)
state <= NORMAL;
else
state <= state_next;
end
endmodule // End Of Module counter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_pwrgood_pp$G (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_SYMBOL_V
|
//#############################################################################
//# Function: A digital debouncer circuit #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_debouncer #( parameter BOUNCE = 100, // bounce time (s)
parameter CLKPERIOD = 0.00001 // period (10ns=0.0001ms)
)
(
input clk, // clock to synchronize to
input nreset, // syncronous active high reset
input noisy_in, // noisy input signal to filter
output clean_out // clean signal to logic
);
//################################
//# wires/regs/ params
//################################
parameter integer CW = $clog2(BOUNCE/CLKPERIOD);// counter width needed
//regs
reg noisy_reg;
reg clean_out;
// synchronize incoming signal
oh_dsync dsync (.dout (noisy_synced),
.clk (clk),
.nreset (nreset),
.din (noisy_in));
// synchronize reset to clk
oh_rsync rsync (.nrst_out (nreset_synced),
.clk (clk),
.nrst_in (nreset));
// detecting change in state on input
always @ (posedge clk or negedge nreset)
if(!nreset)
noisy_reg <= 1'b0;
else
noisy_reg <= noisy_synced;
assign change_detected = noisy_reg ^ noisy_synced;
// synchronous counter "filter"
oh_counter #(.DW(CW))
oh_counter (// Outputs
.count (),
.carry (carry),
.zero (),
// Inputs
.clk (clk),
.in (1'b1),
.en (~carry), //done if you reach carry
.load (change_detected | ~nreset_synced),
.load_data ({(CW){1'b0}})
);
// sample noisy signal safely
always @ (posedge clk or negedge nreset)
if(!nreset)
clean_out <= 'b0;
else if(carry)
clean_out <= noisy_reg;
endmodule // oh_debouncer
|
#include <bits/stdc++.h> using namespace std; int a[111]; char in[1000]; int main() { int t, m, i, j; scanf( %d%d , &t, &m); int aid = 1; while (t--) { scanf( %s , in); int k; if (in[0] == a ) { scanf( %d , &k); for (i = 0; i <= m - k; i++) { for (j = i; j < i + k; j++) if (a[j] != 0) break; if (j == i + k) break; } if (i <= m - k) { printf( %d n , aid); for (j = i; j < i + k; j++) a[j] = aid; aid++; } else { puts( NULL ); } } else if (in[0] == e ) { bool f = 0; scanf( %d , &k); for (i = 0; i < m; i++) if (a[i] && a[i] == k) { a[i] = 0; f = 1; } if (!f) puts( ILLEGAL_ERASE_ARGUMENT ); } else { for (i = 0, j = 0; i < m; i++) if (a[i]) { a[j++] = a[i]; } for (; j < m; j++) a[j] = 0; } } }
|
#include <bits/stdc++.h> using namespace std; int N, Q, T; bool matr[300][300]; int amounts[300]; vector<int> chains[300]; bool was[300]; int sorted[300]; int s = 0; long long mas[2][100010]; void srt(int v) { was[v] = true; for (int i = 0; i < N; i++) if (!was[i] && matr[v][i]) srt(i); sorted[s] = v; s++; } bool z = false; void f(int v, int c) { was[v] = true; for (int i = 0; i < N; i++) if (matr[v][i]) { if (was[i]) z = true; else f(i, c); } chains[c].push_back(v); } int main() { scanf( %d%d%d , &N, &Q, &T); for (int i = 0; i < N; i++) scanf( %d , &amounts[i]); for (int i = 0; i < 300; i++) for (int j = 0; j < 300; j++) matr[i][j] = false; for (int i = 0; i < Q; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; matr[a][b] = true; } for (int i = 0; i < 300; i++) was[i] = false; for (int i = 0; i < N; i++) if (!was[i]) srt(i); reverse(sorted, sorted + N); for (int i = 0; i < 300; i++) was[i] = false; int cCnt = 0; for (int i = 0; i < N; i++) if (!was[sorted[i]]) { f(sorted[i], cCnt); cCnt++; } for (int i = 0; i < cCnt; i++) { for (int j = chains[i].size() - 1; j >= 0; j--) { chains[i][j] = amounts[chains[i][j]]; if (j + 1 < chains[i].size()) chains[i][j] += chains[i][j + 1]; } } if (z) { printf( %d n , 0); return 0; } memset(mas, 0, sizeof(long long) * 100010 * 2); mas[0][0] = 1; int index = 0; for (int i = 0; i < cCnt; i++) { for (int j = 0; j < chains[i].size(); j++) { int amount = chains[i][j]; for (int k = 0; k < 100010; k++) mas[(index + 1) % 2][k] = 0; for (int k = 0; k < 100010; k++) { if (k - amount >= 0) mas[index % 2][k] = (mas[index % 2][k] + mas[index % 2][k - amount]) % 1000000007; if (j == 0) mas[(index + 1) % 2][k] = mas[index % 2][k]; else if (k - amount >= 0) mas[(index + 1) % 2][k] = mas[index % 2][k - amount]; } index++; } } cout << mas[index % 2][T] << n ; return 0; }
|
#include <bits/stdc++.h> int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::string s; std::cin >> s; std::string_view view = s; size_t n = 0; while (!view.empty()) { const size_t id = view.find( > ) + 1; const auto tag = view.substr(0, id); view.remove_prefix(id); if (tag[1] == / ) { n -= 2; } std::cout << std::string(n, ) << tag << n ; if (tag[1] != / ) { n += 2; } } }
|
module sys_command(input [47:0] cmd, input cl_size, input [15:0] o, r0, r1, r2, r3, r4, r5, r6, r7, flag, input en);
always @(posedge en) begin
case (cmd[39:36])
`CMD_TYPE_DFIN : begin
$finish();
end
`CMD_TYPE_DDIS1, `CMD_TYPE_DDIS2 : begin
case (cmd[35:32])
`CMDARG_DIS_C : begin
if (cl_size)
$write("%C", o);
else
$write("%C", o[7:0]);
end
`CMDARG_DIS_B : begin
if (cl_size)
$write("%b", o);
else
$write("%b", o[7:0]);
end
`CMDARG_DIS_O : begin
if (cl_size)
$write("%o", o);
else
$write("%o", o[7:0]);
end
`CMDARG_DIS_D : begin
if (cl_size)
$write("%h", $signed(o));
else
$write("%h", $signed(o[7:0]));
end
`CMDARG_DIS_H : begin
if (cl_size)
$write("%h", o);
else
$write("%h", o[7:0]);
end
`CMDARG_DIS_U : begin
if (cl_size)
$write("%d", o);
else
$write("%d", o[7:0]);
end
endcase
end
`CMD_TYPE_DMPR : begin
$display("[Register]");
$display("R0:%h R1:%h R2:%h R3:%h R4:%h R5:%h R6:%h R7:%h", r0, r1, r2, r3, r4, r5, r6, r7);
$display("ZF:%b SF:%b CF:%b OF:%b", flag[`ALUF_ZF], flag[`ALUF_SF], flag[`ALUF_CF], flag[`ALUF_OF]);
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; static const int INF = 500000000; template <class T> void debug(T a, T b) { for (; a != b; ++a) cerr << *a << ; cerr << endl; } long long int n; pair<long long int, int> factor[100]; long long int tot[100]; int m = 0; long long int ans; bool f(long long int a) { if (a <= 0 || a & 1) return true; return false; } void check(long long int a, long long int b, long long int c) { if (f(b + c - a) || f(c + a - b) || f(a + b - c)) ; else ++ans; } void dfs(int d, long long int a, long long int b, long long int c) { if (d == m) { check(a, b, c); return; } long long int mul1 = 1; for (int i = 0; i < factor[d].second + 1; ++i) { long long int mul2 = 1; for (int j = 0; j < factor[d].second + 1 - i; ++j) { long long int mul3 = tot[d] / mul1 / mul2; dfs(d + 1, a * mul1, b * mul2, c * mul3); mul2 *= factor[d].first; } mul1 *= factor[d].first; } } int main() { cin >> n; if (n % 3) { puts( 0 ); return 0; } n /= 3; long long int t = n; for (long long int i = 2; i * i <= t; ++i) if (t % i == 0) { factor[m].first = i; long long int tmp = 1; while (t % i == 0) { t /= i; tmp *= i; factor[m].second++; } tot[m] = tmp; ++m; } if (t > 1) factor[m++] = make_pair(t, 1), tot[m - 1] = t; ; dfs(0, 1, 1, 1); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int nm = 2e5 + 3; const long long mod = 1e9 + 7; int n; int pos[nm]; int main() { ios::sync_with_stdio(0), cin.tie(0); while (cin >> n) { for (int i = 0; i < n; i++) cin >> pos[i]; sort(pos, pos + n); int step = n / 2 - 1; int res = pos[n - 1] - pos[0]; pair<double, int> loc; for (int i = 0; i <= step; i++) { if (pos[i + n - step - 1] - pos[i] < res) { res = pos[i + n - step - 1] - pos[i]; loc.first = i, loc.second = i + n - step - 1; } } cout << res << endl; } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Synchronous RAM 128-Deep by 1-Wide
// /___/ /\ Filename : RAM128X1S.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module RAM128X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [127:0] INIT = 128'h00000000000000000000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input A6,
input D,
input WCLK,
input WE
);
reg [127:0] mem;
wire [6:0] A_dly, A_in;
reg notifier;
wire D_dly, WCLK_dly, WE_dly;
wire D_in, WCLK_in, WE_in;
assign O = mem[A_in];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_in == 1'b1)
mem[A_in] <= #100 D_in;
always @(notifier)
mem[A_in] <= 1'bx;
`ifndef XIL_TIMING
assign A_dly[0] = A0;
assign A_dly[1] = A1;
assign A_dly[2] = A2;
assign A_dly[3] = A3;
assign A_dly[4] = A4;
assign A_dly[5] = A5;
assign A_dly[6] = A6;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign WCLK_in = IS_WCLK_INVERTED ^ WCLK_dly;
assign WE_in = WE_dly;
assign A_in = A_dly;
assign D_in = D_dly;
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A0 => O) = (0:0:0, 0:0:0);
(A1 => O) = (0:0:0, 0:0:0);
(A2 => O) = (0:0:0, 0:0:0);
(A3 => O) = (0:0:0, 0:0:0);
(A4 => O) = (0:0:0, 0:0:0);
(A5 => O) = (0:0:0, 0:0:0);
(A6 => O) = (0:0:0, 0:0:0);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A0 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A1 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A2 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A3 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A4 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A5 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A6 &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int ans[1000005]; int main() { int n; cin >> n; int a[n], b[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; int l = 0; for (int i = 0; i < n; i++) { for (int j = i; j < n; j++) { if (b[j] == a[i]) { for (int k = j; k > i; k--) { ans[l++] = k; swap(b[k - 1], b[k]); } break; } } } cout << l << endl; for (int i = 0; i < l; i++) { cout << ans[i] << << ans[i] + 1 << endl; } }
|
#include <bits/stdc++.h> using namespace std; const double pi = 2.0 * acos(0.0); const double eps = 1.0e-9; const int dr[] = {-1, 0, 1, 0}, dc[] = {0, 1, 0, -1}; const int dr6[] = {1, 1, 0, -1, -1, 0}, dc6[] = {0, 1, 1, 0, -1, -1}; const int dr8[] = {-1, -1, 0, 1, 1, 1, 0, -1}, dc8[] = {0, 1, 1, 1, 0, -1, -1, -1}; int main(void) { int kase = 1000000000; for (int ks = 1, n; ks <= kase && cin >> n; ++ks) { int c[32] = {0}; for (int i = 0, x; i < n && cin >> x; ++i) ++c[x + 16]; long long s = (long long)c[16] * (c[16] - 1) / 2; for (int i = 1; i <= 10; ++i) s += (long long)c[16 - i] * c[16 + i]; cout << s << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22AI_4_V
`define SKY130_FD_SC_HS__O22AI_4_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o22ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o22ai_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22AI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_PP_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvgndnovpb (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int t; cin >> t; while (t--) { int n, a[100005]; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; int MIN = INT_MAX, MAX = -100; for (int i = 0; i < n; ++i) { if (a[i] != -1 && ((i > 0 && a[i - 1] == -1) || (i < n - 1 && a[i + 1] == -1))) { MIN = min(MIN, a[i]); MAX = max(MAX, a[i]); } } if (MIN == INT_MAX && MAX == -100) cout << 0 << << 0; else { int ans = (MAX + MIN) / 2, d = 0; for (int i = 0; i < n - 1; ++i) { if (a[i] == -1 && a[i + 1] != -1) d = max(d, abs(ans - a[i + 1])); else if (a[i] != -1 && a[i + 1] != -1) d = max(d, abs(a[i] - a[i + 1])); else if (a[i] != -1 && a[i + 1] == -1) d = max(d, abs(a[i] - ans)); } cout << d << << ans; } cout << endl; } return 0; }
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Remover
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_remover (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & in_ready) begin
if (escape_char & ~received_esc) begin
received_esc <= 1;
end else if (out_valid) begin
received_esc <= 0;
end
end
end
end
always @* begin
in_ready = out_ready;
//out valid when in_valid. Except when we get idle or escape
//however, if we have received an escape character, then we are valid
out_valid = in_valid & ~idle_char & (received_esc | ~escape_char);
out_data = received_esc ? (in_data ^ 8'h20) : in_data;
end
endmodule
|
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test file_open() function.
module file_open_test;
logic active, ok;
vhdl_file_open dut(active, ok);
initial begin
active = 1;
#1;
if(ok !== 1'b1) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int sq = (int)sqrt((int)1e6); const int maxnb = (int)1e9 + 7; const double pi = acos(-1.0); const int maxnl = 100500; const double eps = 1e-9; set<pair<long long, int> > se; int n, pos[50500]; char c[50500]; long long price; string s; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> s; int n = s.size(), bal = 0; for (int i = 0; i < n; i++) { if (s[i] == ( ) bal++; if (s[i] == ) ) bal--; if (s[i] == ? ) { long long a, b; cin >> a >> b; se.insert(make_pair(a - b, i)); price += b; s[i] = ) ; bal--; } while (bal < 0) { if (!se.size()) { cout << -1; return 0; } pair<long long, int> p = *se.begin(); price += p.first; s[p.second] = ( ; bal += 2; se.erase(se.begin()); } } if (bal != 0) { cout << -1; return 0; } cout << price << n ; for (int i = 0; i < n; i++) { cout << s[i]; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; const int md = 1e9 + 7; int mul(int a, int b) { return (long long)a * b % md; } char s[N]; int n, m, nn, x[N], z[N]; bool start[N]; int main() { scanf( %d %d %s , &n, &m, s); nn = strlen(s); for (int i = 0; i < m; i++) { scanf( %d , &x[i]); x[i]--; start[x[i]] = true; } for (int i = 1, l = -1, r = -1; i < nn; i++) { int &k = z[i]; if (i < r) { k = min(r - i, z[i - l]); } for (; i + k < nn && s[k] == s[i + k]; k++) ; if (i + k > r) { l = i; r = i + k; } } for (int i = 0; i < m - 1; i++) { int p = x[i + 1] - x[i]; if (p + z[p] < nn) { puts( 0 ); return 0; } } int ans = 1; int r = -1; for (int i = 0; i < n; i++) { if (start[i]) { r = i + nn; } if (i >= r) { ans = mul(ans, 26); } } printf( %d n , ans); return 0; }
|
/* 同步 FIFO 4*128 */
// 一种4bit 128深度的 同步FIFO设计
// @`13
// 2017年6月6日
// 哈尔滨工业大学（威海） EDA课程设计
module fifo(clock, reset, read, write, fifo_in, digitron_out, fifo_empty, fifo_full);
parameter DEPTH = 128; // 128 深
parameter DEPTH_BINARY = 7; // 深度的二进制位数
parameter WIDTH = 4; // 4bit宽
parameter MAX_CONT = 7'b1111111; // 计数器最大值127 [0~127]
// LED 灯的二进制表示
// 根据 《数字系统设计与Verilog DHL (6th Edition)》P153 所提供的7段数码管电路图
/*
—— a
| | f b
—— g
| | e c
—— d
*/
// Len_N = abcdefg
// 使用一个七段数码管基于16进制显示 4bit 数据
parameter
digitron_0 = 7'b1111110,
digitron_1 = 7'b0110000,
digitron_2 = 7'b1101101,
digitron_3 = 7'b0000110,
digitron_4 = 7'b0110011,
digitron_5 = 7'b1011011,
digitron_6 = 7'b1011111,
digitron_7 = 7'b1110000,
digitron_8 = 7'b1111111,
digitron_9 = 7'b1111011,
digitron_a = 7'b1100111,
digitron_b = 7'b0011111,
digitron_c = 7'b1001110,
digitron_d = 7'b0111101,
digitron_e = 7'b0110000,
digitron_f = 7'b1001111;
input clock,reset,read,write; // 时钟，重置，读开关，写开关
input [WIDTH-1:0]fifo_in; // FIFO 数据输入
output [6:0] digitron_out; // 数码管 FIFO 数据输出
output fifo_empty,fifo_full; // 空标志,满标志
reg div; // 驱动信号
reg [23:0] clock_count; // 时钟计数器
reg [6:0] digitron_out; // 数据输出寄存器
reg [WIDTH-1:0]fifo_out; // 数据输出寄存器
reg [WIDTH-1:0]ram[DEPTH-1:0]; // 128深度 8宽度的 RAM 寄存器
reg [DEPTH_BINARY-1:0]read_ptr,write_ptr,counter; // 读指针，写指针，计数器 长度为2^7
wire fifo_empty,fifo_full; // 空标志,满标志
initial
begin
counter = 0;
read_ptr = 0;
write_ptr = 0;
fifo_out = 0;
div = 0;
clock_count = 0;
digitron_out = digitron_0;
end
always@(posedge clock)
begin
if(clock_count == 24'b111111111111111111111111)
begin
div =~ div;
clock_count <= 0;
end
else
begin
clock_count <= clock_count+1;
end
end
assign fifo_empty = (counter == 0); //标志位赋值
assign fifo_full = (counter == DEPTH-1);
always@(posedge div) // 时钟同步驱动
if(reset) // Reset 重置FIFO
begin
read_ptr = 0;
write_ptr = 0;
counter = 0;
fifo_out = 0;
end
else
case({read,write}) // 相应读写开关
2'b00:; //没有读写指令
2'b01: //写指令，数据输入FIFO
begin
if (counter < DEPTH - 1) // 判断是否可写
begin
ram[write_ptr] = fifo_in;
counter = counter + 1;
write_ptr = (write_ptr == DEPTH-1)?0:write_ptr + 1;
end
end
2'b10: //读指令，数据读出FIFO
begin
if (counter > 0) // 判断是否可读
begin
fifo_out = ram[read_ptr];
case(fifo_out)
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
counter = counter - 1;
read_ptr = (read_ptr == DEPTH-1)?0:read_ptr + 1;
end
end
2'b11: //读写指令同时，数据可以直接输出
begin
if(counter == 0)
begin
fifo_out = fifo_in; // 直接输出
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
end
else
begin
ram[write_ptr]=fifo_in;
fifo_out=ram[read_ptr];
case(fifo_out) // todo : 去除case的冗余代码 2017.6.13
4'b0000 : digitron_out <= digitron_0;
4'b0001 : digitron_out <= digitron_1;
4'b0010 : digitron_out <= digitron_2;
4'b0011 : digitron_out <= digitron_3;
4'b0100 : digitron_out <= digitron_4;
4'b0101 : digitron_out <= digitron_5;
4'b0110 : digitron_out <= digitron_6;
4'b0111 : digitron_out <= digitron_7;
4'b1000 : digitron_out <= digitron_8;
4'b1001 : digitron_out <= digitron_9;
4'b1010 : digitron_out <= digitron_a;
4'b1011 : digitron_out <= digitron_b;
4'b1100 : digitron_out <= digitron_c;
4'b1101 : digitron_out <= digitron_d;
4'b1110 : digitron_out <= digitron_e;
4'b1111 : digitron_out <= digitron_f;
endcase
write_ptr=(write_ptr==DEPTH-1)?0:write_ptr+1;
read_ptr=(read_ptr==DEPTH-1)?0:write_ptr+1;
end
end
endcase
endmodule
// module debouncing(
// BJ_CLK, //采集时钟
// RESET, //系统复位信号 [低电平有效]
// BUTTON_IN, //按键输入信号
// BUTTON_OUT //消抖后的输出信号
// );
// input BJ_CLK;
// input RESET;
// input BUTTON_IN;
// output BUTTON_OUT;
// reg BUTTON_IN_Q, BUTTON_IN_2Q, BUTTON_IN_3Q;
// always @(posedge BJ_CLK or negedge RESET)
// begin
// if(~RESET)
// begin
// BUTTON_IN_Q <= 1'b1;
// BUTTON_IN_2Q <= 1'b1;
// BUTTON_IN_3Q <= 1'b1;
// end
// else
// begin
// BUTTON_IN_Q <= BUTTON_IN;
// BUTTON_IN_2Q <= BUTTON_IN_Q;
// BUTTON_IN_3Q <= BUTTON_IN_2Q;
// end
// end
// wire BUTTON_OUT = BUTTON_IN_2Q | BUTTON_IN_3Q;
// endmodule
|
// ps2mouse.v
// ps2 mouse model
// 2014,
module ps2mouse (
input wire clk,
input wire rst,
inout wire mclk,
inout wire mdat
);
//// constants ////
localparam [8-1:0]
PS2_SELFTEST = 8'haa,
PS2_ID00 = 8'h00,
PS2_ID03 = 8'h03,
PS2_ACK = 8'hfa;
//// bus tri-state buffers ////
reg mclk_en=1'b0, mdat_en=1'b0;
reg mclk_o = 1'b1, mdat_o = 1'b1;
wire mclk_i, mdat_i;
assign mclk = mclk_en ? mclk_o : 1'bz;
assign mdat = mdat_en ? mdat_o : 1'bz;
assign mclk_i = mclk;
assign mdat_i = mdat;
//// bus states ////
wire bus_idle, bus_inhibit, bus_rts, bus_busy;
assign bus_idle = ((mclk_i !== 1'b0) && (mdat_i !== 1'b0));
assign bus_inhibit = ((mclk_i === 1'b0) && (mdat_i !== 1'b0));
assign bus_rts = ((mclk !== 1'b0) && (mdat === 1'b0));
assign bus_busy = ((mclk === 1'b0) && (mdat === 1'b0));
//// mouse states ////
reg [8-1:0] dat = 0;
reg [8-1:0] cmd = 0;
reg [8-1:0] sample_rate = 8'd100;
reg [2:0] intellimouse_state = 0;
reg intellimouse = 0;
reg data_reporting = 0;
reg status = 0;
//// tasks ////
// wait_ms
task wait_ms;
input integer t;
begin
repeat (t) #1000;
end
endtask
// ps2_tick
task ps2_tick;
begin
mclk_o = 1;
wait_ms(30);
mclk_o = 0;
wait_ms(30);
end
endtask
// ps2_rx
task ps2_rx;
output reg [8-1:0] dat;
output reg status;
reg parity;
integer i;
begin
status = 0;
wait(bus_rts);
wait_ms(30);
mclk_en = 1;
wait_ms(30);
for (i=0; i<8; i=i+1) begin
mclk_o = 0;
wait_ms(30);
mclk_o = 1;
wait_ms(30);
dat = {mdat_i, dat[7:1]};
end
mclk_o = 0;
wait_ms(30);
mclk_o = 1;
wait_ms(30);
parity = mdat_i;
if (parity != (!(^dat))) $display("Parity mismatch!");
mclk_o = 0;
wait_ms(30);
mclk_o = 1;
wait_ms(30);
mdat_en = 1;
mdat_o = 0;
mclk_o = 0;
wait_ms(30);
mclk_o = 1;
wait_ms(30);
mclk_en = 0;
mdat_en = 0;
mclk_o = 1;
mdat_o = 1;
ps2_tx(PS2_ACK, status);
end
endtask
// ps2_tx
task ps2_tx;
input reg [8-1:0] dat;
output reg status;
reg parity;
integer i;
begin
parity = !(^dat);
status = 0;
wait_ms(100);
if (!bus_idle) begin
status = 1;
end else begin
mclk_en = 1;
mdat_en = 1;
mdat_o = 0;
ps2_tick;
for (i=0; i<8; i=i+1) begin
mdat_o = dat[0];
ps2_tick;
dat = {1'b0, dat[7:1]};
end
mdat_o = parity;
ps2_tick;
mdat_o = 1;
ps2_tick;
mclk_en = 0;
mdat_en = 0;
mclk_o = 1;
mdat_o = 1;
end
end
endtask
// init
task init;
reg status;
begin
ps2_tx(PS2_SELFTEST, status);
if (!status) ps2_tx(PS2_ID00, status);
end
endtask
// configure
task configure;
reg configured;
begin
configured = 0;
while (!configured) begin
ps2_rx(cmd, status);
case (cmd)
8'hff : begin
$display("Host reset (0xff)");
ps2_tx(PS2_SELFTEST, status);
ps2_tx(PS2_ID00, status);
end
8'hf3 : begin
$display("Host set resample rate (0xf3)");
ps2_rx(dat, status);
$display("Host resample rate = 0x%02x", dat);
if ((dat == 8'hc8) && (intellimouse_state == 0)) intellimouse_state = 1;
else if ((dat == 8'h64) && (intellimouse_state == 1)) intellimouse_state = 2;
else if ((dat == 8'h50) && (intellimouse_state == 2)) intellimouse_state = 3;
if (intellimouse_state == 3) intellimouse = 1;
end
8'hf2 : begin
$display("Host read device type (0xf2)");
if (intellimouse)
ps2_tx(PS2_ID03, status);
else
ps2_tx(PS2_ID00, status);
end
8'hf4 : begin
$display("Host enable data reporting (0xf4)");
data_reporting = 1;
configured = 1;
end
endcase
end
end
endtask
// report
task report;
begin
forever begin
#100000;
ps2_tx(8'h0f, status);
ps2_tx(8'h03, status);
ps2_tx(8'h02, status);
ps2_tx(8'h01, status);
end
end
endtask
//// mouse model ////
initial begin
init;
configure;
#200000;
report;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i = 0; cin >> n; long long a; vector<long long> vc; while (n--) { cin >> a; vc.push_back(a); } sort(vc.begin(), vc.end()); i = vc.size(); long long ans = vc[i - 1]; for (int j = i - 2; j >= 0; j--) { if (vc[j] >= vc[j + 1]) { vc[j] = vc[j + 1] - 1; } if (vc[j] > 0) ans += vc[j]; } cout << ans << endl; }
|
#include <bits/stdc++.h> using namespace std; int sta[10][100005]; int top[10]; int tail[10]; int a[100005][10]; int ans[10]; int main() { int n, m; int k; scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); } } for (int i = 1; i <= m; i++) { top[i] = 1; } int ma = -1; int i = 1; for (int l = 1; l <= n; l++) { if (l > 1) { for (int j = 1; j <= m; j++) { if (top[j] <= tail[j] && sta[j][top[j]] < l) { top[j]++; } } } for (i = max(i, l); i <= n; i++) { int sum = 0; for (int j = 1; j <= m; j++) { sum += max(a[sta[j][top[j]]][j], a[i][j]); } if (sum > k) break; for (int j = 1; j <= m; j++) { while (tail[j] >= top[j] && a[sta[j][tail[j]]][j] < a[i][j]) { tail[j]--; } sta[j][++tail[j]] = i; } if (i - l + 1 > ma) { ma = i - l + 1; for (int j = 1; j <= m; j++) ans[j] = a[sta[j][top[j]]][j]; } } } for (int i = 1; i <= m; i++) printf( %d , ans[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, a, b; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; if (a > b) { cout << b * (b + 1) / 2 << endl; } else { cout << a * (a - 1) / 2 + 1 << endl; } } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_1_V
`define SKY130_FD_SC_LP__NOR2B_1_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_1 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_1 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_1_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:11:49 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/clk_193MHz/clk_193MHz_funcsim.v
// Design : clk_193MHz
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_193MHz,clk_wiz_v5_1,{component_name=clk_193MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_193MHz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_193MHz;
wire locked;
clk_193MHzclk_193MHz_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_193MHz(clk_193MHz),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_193MHz_clk_wiz" *)
module clk_193MHzclk_193MHz_clk_wiz
(clk_100MHz,
clk_193MHz,
locked);
input clk_100MHz;
output clk_193MHz;
output locked;
(* IBUF_LOW_PWR *) wire clk_100MHz;
wire clk_100MHz_clk_193MHz;
wire clk_193MHz;
wire clk_193MHz_clk_193MHz;
wire clkfbout_buf_clk_193MHz;
wire clkfbout_clk_193MHz;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_193MHz),
.O(clkfbout_buf_clk_193MHz));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_100MHz),
.O(clk_100MHz_clk_193MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_193MHz_clk_193MHz),
.O(clk_193MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(45.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.750000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_193MHz),
.CLKFBOUT(clkfbout_clk_193MHz),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_100MHz_clk_193MHz),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_193MHz_clk_193MHz),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:09 02/22/2015
// Design Name:
// Module Name: SpecialAdd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SpecialAdd(
input [31:0] cin_Special,
input [31:0] zin_Special,
input reset,
input clock,
output reg idle_Special = 1'b0,
output reg [7:0] difference_Special,
output reg [35:0] cout_Special,
output reg [35:0] zout_Special,
output reg [31:0] sout_Special
);
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign c_sign = cin_Special[31];
assign c_exponent = {cin_Special[30:23] - 127};
assign c_mantissa = {cin_Special[22:0],3'd0};
assign z_sign = {zin_Special[31]};
assign z_exponent = {zin_Special[30:23] - 127};
assign z_mantissa = {zin_Special[22:0],3'd0};
parameter no_idle = 1'b0,
put_idle = 1'b1;
always @ (posedge clock)
begin
if (reset == 1'b1) begin
idle_Special <= 1'b0;
end
else begin
if ($signed(z_exponent) > $signed(c_exponent)) begin
difference_Special <= z_exponent - c_exponent;
end
else if ($signed(z_exponent) <= $signed(c_exponent)) begin
difference_Special <= c_exponent - z_exponent;
end
// Most of the special cases will never occur except the case where one input is zero.
// The HCORDIC module will not receive NaN and inf at input stage.
//if c is NaN or z is NaN return NaN
if ((c_exponent == 128 && c_mantissa != 0) || (z_exponent == 128 && z_mantissa != 0)) begin
sout_Special[31] <= 1;
sout_Special[30:23] <= 255;
sout_Special[22] <= 1;
sout_Special[21:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is inf return inf
end else if (c_exponent == 128) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is inf return inf
end else if (z_exponent == 128) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= 255;
sout_Special[22:0] <= 0;
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if ((($signed(c_exponent) == -127) && (c_mantissa == 0)) && (($signed(z_exponent) == -127) && (z_mantissa == 0))) begin
sout_Special[31] <= c_sign & z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if c is zero return z
end else if (($signed(c_exponent) == -127) && (c_mantissa == 0)) begin
sout_Special[31] <= z_sign;
sout_Special[30:23] <= z_exponent[7:0] + 127;
sout_Special[22:0] <= z_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
//if z is zero return c
end else if (($signed(z_exponent) == -127) && (z_mantissa == 0)) begin
sout_Special[31] <= c_sign;
sout_Special[30:23] <= c_exponent[7:0] + 127;
sout_Special[22:0] <= c_mantissa[26:3];
zout_Special <= zin_Special;
cout_Special <= cin_Special;
idle_Special <= put_idle;
end else begin
sout_Special <= 0;
//Denormalised Number
if ($signed(c_exponent) == -127) begin
cout_Special[34:27] <= -126;
cout_Special[35] <= c_sign;
cout_Special[26:0] <= c_mantissa;
end else begin
cout_Special[34:27] <= c_exponent + 127;
cout_Special[35] <= c_sign;
cout_Special[26] <= 1;
cout_Special[25:0] <= c_mantissa[25:0];
idle_Special <= no_idle;
end
//Denormalised Number
if ($signed(z_exponent) == -127) begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= -126;
zout_Special[26:0] <= z_mantissa;
end else begin
zout_Special[35] <= z_sign;
zout_Special[34:27] <= z_exponent + 127;
zout_Special[25:0] <= z_mantissa[25:0];
zout_Special[26] <= 1;
idle_Special <= no_idle;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d %d , &n, &m); vector<pair<int, int> > f(n); vector<int> b(m); vector<int> array(1000005, 0); for (int i = 0; i < n; i++) { int temp; scanf( %d , &temp); array[temp]++; f.push_back(make_pair(temp, i)); } int ambuiguity = 0; int impossible = 0; sort(f.begin(), f.end()); vector<int> ans; for (int i = 0; i < m; i++) { int temp; scanf( %d , &temp); vector<pair<int, int> >::iterator it = upper_bound(f.begin(), f.end(), make_pair(temp, -1)); if (it == f.end()) { impossible = 1; break; } if (it->first == temp) { if (array[temp] > 1) { ambuiguity = 1; } else { ans.push_back(it->second + 1); } } else { impossible = 1; break; } } if (impossible == 1) { cout << Impossible << endl; } else if (ambuiguity == 1) { cout << Ambiguity << endl; } else { cout << Possible << endl; for (int i = 0; i < ans.size() - 1; i++) { printf( %d , ans[i]); } cout << ans[ans.size() - 1] << endl; } return 0; }
|
#include <bits/stdc++.h> const long double eps = 1e-9; const long long mod = 1e9 + 7, ll_max = (long long)1e18; const int MX = 2e5 + 10, int_max = 0x3f3f3f3f; using namespace std; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n, k; long long arr[MX]; int solve() { cin >> n >> k; for (int i = 0; i < k; i++) { arr[i] += i + 1; n -= i + 1; } if (n < 0) return 0; for (int i = 0; i < k; i++) { arr[i] += (n / k); } n %= k; for (int i = k - 1; i > 0; i--) { int del = min(2 * arr[i - 1] - arr[i], n); n -= del; arr[i] += del; } return (n == 0); } int main() { cin.tie(0)->sync_with_stdio(0); if (solve()) { cout << YES n ; for (int i = 0; i < k; i++) cout << arr[i] << ; cout << n ; } else { cout << NO n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, ans, du[2010], d[2010], mx, sz, dp[2010]; int num, k, now, a[2010], dfn[2010], low[2010], st[2010], b[2010]; bool in[2010]; int cnt, head[2010], to[200010], nxt[200010]; vector<int> v[2010]; void add(int x, int y) { cnt++; to[cnt] = y; nxt[cnt] = head[x]; head[x] = cnt; } void tarjan(int x, int fa) { now++; dfn[x] = low[x] = now; st[k] = x; k++; in[x] = true; for (int i = head[x]; i; i = nxt[i]) { int y = to[i]; if (y == fa) { continue; } if (!dfn[y]) { tarjan(y, x); low[x] = min(low[x], low[y]); } else if (in[y]) { low[x] = min(low[x], dfn[y]); } } if (low[x] == dfn[x]) { num++; int y; do { y = st[k - 1]; a[y] = num; in[y] = false; k--; } while (k > 0 && y != x); } } void dfs(int x) { dfn[x] = true; for (int i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (dfn[y]) { continue; } dfs(y); if (du[y] > 1) { mx = max(mx, dp[x] + dp[y] + 1); dp[x] = max(dp[x], dp[y]); } } if (du[x] <= 1) { return; } sz++; dp[x]++; mx = max(mx, dp[x]); } void work(int x) { if (du[x] > 1) { dfs(x); return; } for (int i = 0; i < v[x].size(); i++) { int y = v[x][i]; if (du[y] > 1) { dfs(y); return; } } dfs(x); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); add(x, y); add(y, x); } for (int i = 1; i <= n; i++) { if (!dfn[i]) { tarjan(i, 0); } } for (int i = 1; i <= n; i++) { for (int j = head[i]; j; j = nxt[j]) { int y = to[j]; if (a[i] != a[y]) { v[a[i]].push_back(a[y]); du[a[i]]++; } } } ans = n - num; memset(dfn, 0, sizeof(dfn)); for (int i = 1; i <= num; i++) { if (!dfn[i]) { ans++; mx = sz = 0; work(i); ans += sz - mx; } } ans--; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cout.tie(0); cin.tie(0); string s; cin >> s; long long dp[s.length() + 1], mod = 1e9 + 7, f = 0; dp[0] = 1; dp[1] = 1; if (s[0] == m || s[0] == w ) f = 1; for (long long i = 2; i <= s.length(); i++) { if (s[i - 1] == m || s[i - 1] == w ) f = 1; else if ((s[i - 1] == n || s[i - 1] == u ) && (s[i - 1] == s[i - 2])) dp[i] = (dp[i - 2] + dp[i - 1]) % mod; else dp[i] = dp[i - 1]; } if (f) cout << 0 << endl; else cout << dp[s.length()] << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; void fastio() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int main() { fastio(); int n, m, temp; cin >> n >> m; vector<int> boys(n); vector<int> girls(m); int hb; cin >> hb; for (int i = 0; i < hb; i++) cin >> temp, boys[temp] = 1; int hg; cin >> hg; for (int i = 0; i < hg; i++) cin >> temp, girls[temp] = 1; int len = 100 * 100; int a, b; for (int i = 0; i < len; i++) { a = i % n; b = i % m; if (boys[a] == 1 || girls[b] == 1) boys[a] = 1, girls[b] = 1; } for (int i = 0; i < n; i++) if (boys[i] == 0) { cout << No n ; return 0; } for (int i = 0; i < m; i++) if (girls[i] == 0) { cout << No n ; return 0; } cout << Yes n ; return 0; }
|
/*
* Copyright (c) 2002 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test the display of very wide vectors in decimal.
*/
module test;
reg signed [127:0] value;
initial begin
value = 1;
while (value != 0) begin
$display("value=%d", value);
value = value << 1;
end
value = -1;
while (value != 0) begin
$display("value=%d", value);
value = value << 1;
end
end
endmodule // test
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e4 + 100; const int maxq = 2e4 + 100; const int maxd = 15; const int ha1 = 317, ha2 = 443, mod = 364417; struct Que_Typ { int y, id; Que_Typ(int a = 0, int b = 0) { y = a, id = b; } }; int N, Que; vector<Que_Typ> ope[maxn]; long long Ans[maxq]; struct Hash { int x, y; Hash(int a = 0, int b = 0) { x = a, y = b; } friend Hash operator+(const Hash &a, const Hash &b) { return Hash((a.x + b.x) % mod, (a.y + b.y) % mod); } friend Hash operator*(const Hash &a, const Hash &b) { return Hash((long long)a.x * b.x % mod, (long long)a.y * b.y % mod); } friend bool operator==(const Hash &a, const Hash &b) { return (a.x == b.x && a.y == b.y); } friend bool operator<(const Hash &a, const Hash &b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } void printt() { printf( Hash %d %d n , x, y); } }; Hash po[(1 << maxd) + 10]; struct Edge { int node, next, cha; Edge(int a = 0, int b = 0, int c = 0) { node = a, next = b, cha = c; } } E[maxn * 2]; int e_cnt, head[maxn]; int bary[maxn]; int siz[maxn], wei, minf; struct Trie { int root, cnt, go[maxn][26], val[maxn]; long long sum[maxn], sum2[maxn]; map<Hash, int> Map; int create() { ++cnt; memset(go[cnt], 0, sizeof(go[cnt])); sum[cnt] = 0; sum2[cnt] = 0; val[cnt] = 0; return cnt; } void dfs(int last, int x, int p, Hash v, int d) { Map[v] = p; ++val[p]; for (int i = head[x]; i != -1; i = E[i].next) { int y = E[i].node, c = E[i].cha; if (bary[y] || y == last) continue; if (!go[p][c - 1]) go[p][c - 1] = create(); dfs(x, y, go[p][c - 1], v + Hash(c, c) * po[d], d + 1); } } void Pre_sum(int p, long long &ret) { sum[p] = ret; ret += val[p]; for (int i = (0), _i = (25); i <= _i; ++i) if (go[p][i]) Pre_sum(go[p][i], ret); sum2[p] = ret; } void build(int last, int x, int c = 0) { cnt = 0; root = create(); Map.clear(); if (c) { int p = root, d = 1; Hash v = Hash(0, 0); Map[v] = p; go[p][c - 1] = create(); dfs(last, x, go[p][c - 1], v + Hash(c, c) * po[d], d + 1); } else dfs(last, x, root, Hash(0, 0), 1); val[root] = 0; long long tt = 0; Pre_sum(root, tt); } } Trie1, Trie2; struct Tree { int wei, tim, id[maxn], fa[maxd][maxn]; Hash dtu[maxd][maxn], utd[maxd][maxn]; int siz[maxn], path[maxn], dep[maxn]; void get_skip_table(int x) { for (int j = (1), _j = (maxd - 1); j <= _j; ++j) { int y = fa[j - 1][x]; int z = fa[j - 1][y]; fa[j][x] = z; dtu[j][x] = dtu[j - 1][x] + dtu[j - 1][y] * po[1 << (j - 1)]; utd[j][x] = utd[j - 1][y] + utd[j - 1][x] * po[1 << (j - 1)]; } } int get_lca(int x, int y) { if (x == y) return x; if (id[x] > id[y]) swap(x, y); for (int j = (maxd - 1), _j = (0); j >= _j; --j) if (id[x] < id[fa[j][y]]) y = fa[j][y]; return fa[0][y]; } int skip(int x, int k) { for (; k; k -= (k & (-k))) { x = fa[__builtin_ctz(k)][x]; } return x; } int move(int x, int y, int k) { int lca = get_lca(x, y); int lenx = dep[x] - dep[lca]; int len = lenx + dep[y] - dep[lca]; return (k <= lenx ? skip(x, k) : skip(y, len - k)); } Hash get_dtu(int x, int k) { Hash ret = Hash(0, 0), s = Hash(1, 1); for (; k; k -= (k & (-k))) { int j = __builtin_ctz(k); ret = ret + dtu[j][x] * s; s = s * po[1 << j]; x = fa[j][x]; } return ret; } Hash get_utd(int x, int k) { Hash ret = Hash(0, 0); for (; k; k -= (k & (-k))) { int j = __builtin_ctz(k); ret = ret * po[1 << j] + utd[j][x]; x = fa[j][x]; } return ret; } void dfs(int last, int x) { siz[x] = 1; id[x] = ++tim; get_skip_table(x); for (int i = head[x]; i != -1; i = E[i].next) { int y = E[i].node, c = E[i].cha; if (y == last || bary[y]) continue; fa[0][y] = x; utd[0][y] = dtu[0][y] = Hash(c, c) * po[1]; dep[y] = dep[x] + 1; path[y] = c; dfs(x, y); siz[x] += siz[y]; } } void build(int x) { tim = 0; wei = x; fa[0][wei] = wei; utd[0][wei] = dtu[0][wei] = Hash(0, 0); dep[wei] = 0; path[wei] = 0; dfs(0, wei); } } T0, T1; void add_Edge(int x, int y, int c) { E[e_cnt] = Edge(y, head[x], c); head[x] = e_cnt++; } int compare(int x, int y, int wei) { int lca = T0.get_lca(x, y); int lenx = T0.dep[x] - T0.dep[lca]; int len = lenx + T0.dep[y] - T0.dep[lca]; int towei = T1.dep[x] - T1.dep[wei]; int le = 0, ri = min(towei, len) + 1; while (le + 1 < ri) { int mid = (le + ri) >> 1; Hash s1 = T1.get_dtu(x, mid); Hash s0 = (mid <= lenx ? T0.get_dtu(x, mid) : T0.get_dtu(x, lenx) + T0.get_utd(T0.skip(y, len - mid), mid - lenx) * po[lenx]); (s1 == s0 ? le = mid : ri = mid); } if (le == towei) return 0; int c1 = T1.path[T1.skip(x, le)]; int c0 = (le < len ? T0.path[(le < lenx ? T0.skip(x, le) : T0.skip(y, len - le - 1))] : 0); return c1 - c0; } long long calc_cmp0(int x, int y, Trie &Tr, int &flag) { x = T0.move(x, y, T1.dep[x] - T1.dep[wei]); int lca = T0.get_lca(x, y); int lenx = T0.dep[x] - T0.dep[lca]; int len = lenx + T0.dep[y] - T0.dep[lca]; flag = (len > 0); int le = 0, ri = len + 1; while (le + 1 < ri) { int mid = (le + ri) >> 1; Hash s0 = (mid <= lenx ? T0.get_dtu(x, mid) : T0.get_dtu(x, lenx) + T0.get_utd(T0.skip(y, len - mid), mid - lenx) * po[lenx]); (Tr.Map.find(s0) != Tr.Map.end() ? le = mid : ri = mid); } Hash s0 = (le <= lenx ? T0.get_dtu(x, le) : T0.get_dtu(x, lenx) + T0.get_utd(T0.skip(y, len - le), le - lenx) * po[lenx]); int c0 = (le < len ? T0.path[(le < lenx ? T0.skip(x, le) : T0.skip(y, len - le - 1))] : 0); int num = (le == 0 ? Tr.root : Tr.Map[s0]); long long ret = Tr.sum[num]; if (c0 == 0) return Tr.sum[num]; for (int i = (c0 - 1), _i = (25); i <= _i; ++i) if (Tr.go[num][i]) return Tr.sum[Tr.go[num][i]]; return Tr.sum2[num]; } void work(int last, int x, int &gg) { for (int i = (0), _i = (ope[x].size() - 1); i <= _i; ++i) { int y = ope[x][i].y, id = ope[x][i].id; int cmp = compare(x, y, wei); if (cmp < 0) { Ans[id] += gg; } else if (cmp == 0) { int flag; Ans[id] += calc_cmp0(x, y, Trie1, flag) - calc_cmp0(x, y, Trie2, flag); Ans[id] += flag; } } for (int i = head[x]; i != -1; i = E[i].next) { int y = E[i].node; if (bary[y] || y == last) continue; work(x, y, gg); } } void solve() { Trie1.build(0, wei); for (int i = (0), _i = (ope[wei].size() - 1); i <= _i; ++i) { int y = ope[wei][i].y, id = ope[wei][i].id; int flag; Ans[id] += calc_cmp0(wei, y, Trie1, flag); } for (int i = head[wei]; i != -1; i = E[i].next) { int y = E[i].node, c = E[i].cha; if (bary[y]) continue; Trie2.build(wei, y, c); int gg = T1.siz[wei] - T1.siz[y]; work(wei, y, gg); } } void find_bary(int last, int x, int &n) { siz[x] = 1; int maxf = 0; for (int i = head[x]; i != -1; i = E[i].next) { int y = E[i].node; if (y == last || bary[y]) continue; find_bary(x, y, n); siz[x] += siz[y]; maxf = max(maxf, siz[y]); } maxf = max(maxf, n - siz[x]); if (maxf < minf) minf = maxf, wei = x; } void vdc(int x, int n) { minf = N + 2, wei = x; find_bary(0, x, n); T1.build(wei); solve(); bary[wei] = 1; for (int i = head[wei]; i != -1; i = E[i].next) { int y = E[i].node; if (bary[y]) continue; vdc(y, siz[y]); } } int main() { po[0] = Hash(1, 1); po[1] = Hash(ha1, ha2); for (int i = (2), _i = ((1 << maxd)); i <= _i; ++i) po[i] = po[i - 1] * po[1]; for (; scanf( %d%d , &N, &Que) != EOF;) { e_cnt = 0; memset(head, 255, sizeof(head[0]) * (N + 2)); for (int i = (1), _i = (N - 1); i <= _i; ++i) { int x, y; char c[5]; scanf( %d%d%s , &x, &y, c); add_Edge(x, y, c[0] - a + 1); add_Edge(y, x, c[0] - a + 1); } for (int i = (1), _i = (N); i <= _i; ++i) ope[i].clear(); for (int i = (1), _i = (Que); i <= _i; ++i) { int x, y; scanf( %d%d , &x, &y); ope[x].push_back(Que_Typ(y, i)); } memset(bary, 0, sizeof(bary[0]) * (N + 2)); memset(Ans, 0, sizeof(Ans[0]) * (N + 2)); T0.build(1); vdc(1, N); for (int i = (1), _i = (Que); i <= _i; ++i) printf( %I64d n , Ans[i]); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Point { long double x, y; Point(){}; long double dist(Point b) { return sqrt((b.x - x) * (b.x - x) + (b.y - y) * (b.y - y)); } }; int main() { Point a, b, c; cin >> a.x >> a.y >> b.x >> b.y >> c.x >> c.y; long double k = a.dist(b); long double l = c.dist(b); if (k == l && k + l != a.dist(c)) cout << YES ; else cout << NO ; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
sub #(.IDX(0), .CHK(10)) i0;
sub #(.IDX(2), .CHK(12)) i2;
sub #(.IDX(7), .CHK(17)) i7;
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub ();
function integer get_element;
input integer index;
input integer array_arg[7:0];
get_element = array_arg[index];
endfunction
parameter integer IDX = 5;
parameter integer CHK = 5;
localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17};
localparam element1 = array[IDX];
localparam elementf = get_element(IDX, array);
initial begin
`checkh (element1, CHK);
`checkh (elementf, CHK);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int key; vector<int> v; for (int i = 0; i < n; ++i) { cin >> key; v.push_back(key); } int max = v[0]; int min = v[0]; int amz = 0; for (int i = 1; i < n; ++i) { if (v[i] > max) { amz++; max = v[i]; } if (v[i] < min) { amz++; min = v[i]; } } cout << amz; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void pr(vector<T> &v) { for (int i = 0; i < (int)(v).size(); i++) cout << v[i] << ; cout << n ; ; } template <typename T> void pr(vector<vector<T>> &v) { for (int i = 0; i < (int)(v).size(); i++) { pr(v[i]); } } template <typename T> void re(T &x) { cin >> x; } template <typename T> void re(vector<T> &a) { for (int i = 0; i < (int)(a).size(); i++) re(a[i]); } template <class Arg, class... Args> void re(Arg &first, Args &...rest) { re(first); re(rest...); } template <typename T> void pr(T x) { cout << x << n ; ; } template <class Arg, class... Args> void pr(const Arg &first, const Args &...rest) { cout << first << ; pr(rest...); cout << n ; ; } void ps() { cout << n ; ; } template <class T, class... Ts> void ps(const T &t, const Ts &...ts) { cout << t; if (sizeof...(ts)) cout << ; ps(ts...); } const long long MOD = 1000000007; long double PI = 4 * atan(1); long double eps = 1e-12; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; long long powk = k; long long exp = 1; long long nexp = n - 1; if (k == 1) { nexp = n; } if (k != 0 && k != 1) { while (powk % n != 1) { powk *= k; powk %= n; exp++; } nexp = (n - 1) / exp; } long long powp = 1; for (int i = 0; i < nexp; i++) { powp *= n; powp %= MOD; } cout << powp << n ; ; }
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#include <bits/stdc++.h> using namespace std; const long long maxn = (int)1e6; long long n, m, a; int main() { cin >> a; if (a == 1) { cout << 1 1 n 1 ; return 0; } cout << (a - 1) * 2 << << 2 << n ; cout << 1 2 ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_2_V
`define SKY130_FD_SC_HDLL__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_2_V
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> s; long long n, b[500005], c[500005]; int main() { cin >> n; for (int i = 0; i < n; i++) { long long x; cin >> x; s[x]++; } long long m, mx1 = 0, mx2 = 0, index = 1; cin >> m; for (int i = 0; i < m; i++) { cin >> b[i]; } for (int i = 0; i < m; i++) { cin >> c[i]; } for (int i = 0; i < m; i++) { if (s[b[i]] > mx1) { mx1 = s[b[i]]; index = i + 1; } } for (int i = 0; i < m; i++) { if (s[b[i]] == mx1) { if (s[c[i]] > mx2) { index = i + 1; mx2 = s[c[i]]; } } } cout << index << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxN = 110000; int t[4 * maxN], m; int get(int k) { int res = 0; for (int i = k; i >= 0; i = (i & (i + 1)) - 1) { res = max(res, t[i]); } return res; } void update(int k, int delta) { for (int i = k; i <= m; i |= (i + 1)) { t[i] = max(t[i], delta); } } int calculate(vector<pair<int, int> > borders) { pair<int, int> start = borders[0]; sort(borders.rbegin(), borders.rend()); for (int i = 0; i < borders.size(); ++i) { int current = get(borders[i].second - 1); update(borders[i].second, current + 1); if (borders[i] == start) { return current; } } } int a, b, c, d, n; struct rational { long long x, y; rational(long long x, long long y) : x(x), y(y) {} rational() : x(0), y(1) {} bool operator<(const rational &other) const { return x * other.y < other.x * y; } }; vector<pair<int, int> > compress(vector<rational> a, vector<rational> b) { set<rational> S; for (int i = 0; i < a.size(); ++i) { S.insert(a[i]); S.insert(b[i]); } map<rational, int> M; m = 0; for (set<rational>::iterator it = S.begin(); it != S.end(); ++it) { M[*it] = ++m; } vector<pair<int, int> > borders; for (int i = 0; i < a.size(); ++i) { borders.push_back(make_pair(M[a[i]], M[b[i]])); } return borders; } int main() { scanf( %d , &n); scanf( %d/%d%d/%d , &a, &b, &c, &d); vector<rational> u, v; for (int i = 0; i <= n; ++i) { long long x, y; if (i == 0) { x = y = 0; } else { cin >> x >> y; } u.push_back(rational(1000000LL * a + y * b - x * a, a + b)); v.push_back(rational(1000000LL * c + y * d - x * c, c + d)); } printf( %d n , calculate(compress(u, v))); return 0; }
|
#include<bits/stdc++.h> using namespace std; int main() { int t,n; cin >> t; while(t--) { cin >> n; int ans=0,k=n,p=n,h=0; while(ceil(sqrt(k))>=2 && k>2) { ans++; k=ceil(sqrt(k)); } cout << ans+n-2 << endl; k=n; int i=k-1; while(k>2) { int p=ceil(sqrt(k)); while(i>p) { cout << i << << k << endl; i--; } cout<< k << << i << endl; cout << k << << i << endl; k=ceil(sqrt(k)); i=k-1; } } return 0; }
|
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p + 1;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic [width_p-1:0] a_r;
logic signed_r;
logic v_r;
logic [width_p-1:0] z_lo;
logic invalid_lo;
bsg_fpu_f2i #(
.e_p(8)
,.m_p(23)
) dut (
.a_i(a_r)
,.signed_i(signed_r)
,.z_o(z_lo)
,.invalid_o(invalid_lo)
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_r)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
assign {signed_li, a_li} = tr_data_lo;
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
invalid_lo
,z_lo
};
logic [width_p-1:0] a_n;
logic signed_n;
logic v_n;
always_comb begin
if (v_r == 1'b0) begin
tr_yumi_li = tr_v_lo;
v_n = tr_v_lo;
signed_n = tr_v_lo
? tr_data_lo[width_p]
: signed_r;
a_n = tr_v_lo
? tr_data_lo[0+:width_p]
: a_r;
end
else begin
tr_yumi_li = 1'b0;
v_n = ~tr_ready_lo;
a_n = a_r;
end
end
always_ff @ (posedge clk) begin
if (reset) begin
a_r <= '0;
v_r <= 1'b0;
signed_r <= 1'b0;
end
else begin
a_r <= a_n;
v_r <= v_n;
signed_r <= signed_n;
end
end
initial begin
wait(done_lo);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_8_V
`define SKY130_FD_SC_HS__INV_8_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_8 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__inv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_8_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [C_ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [C_ADDRESS_WIDTH:0] s_axis_room
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr = _m_axis_raddr[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= 2**C_ADDRESS_WIDTH;
end else begin
s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**C_ADDRESS_WIDTH;
end
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_jid_to_yid.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_jid_to_yid -- JBus JID to YID translator.
// _____________________________________________________________________________
//
// Description:
// Responsible for performing the YID to JID translations for outbound local PIO
// transactions, and inbound local data returns.
// For outbound local transactions, an interface is provided for allocating an unused JID
// and remembering the JID to YID translation.
// For inbound local data returns, an interface is provided to perform a JID to YID lookup,
// and to free a JID translation from the table.
// The PIO JID pool has 16 JIDs which can be associated with any 9-bit YID value.
//
// Interface:
// Translation request:
// A JID 'trans_jid0' is given to the 'jid_to_yid_table' which returns the YID 'trans_yid0'
// on the same cycle. There are no qualifier signals.
//
// Allocating an assignment request:
// When 'alloc' is asserted, the YID 'alloc_yid' will be associated with the next available
// JID and that associated JID returned in 'alloc_jid'. Note that 'alloc_jid' is only valid
// during the current cycle that 'alloc' is valid. 'alloc_stall' denotes that there are
// no more available JIDs and 'alloc' must not be asserted until one is freed. When a JID
// is allocated, it is removed from the free jid pool 'free_jid_pool'.
//
// Freeing an assignment request:
// When '*' is asserted, the JID in 'free*_jid' is added to the JID free space
// pool maintained by 'free_jid_pool'.
// _____________________________________________________________________________
`include "sys.h"
module jbi_jid_to_yid (/*AUTOARG*/
// Outputs
trans_yid0, trans_valid0, trans_yid1, trans_valid1, alloc_stall, alloc_jid,
// Inputs
trans_jid0, trans_jid1, alloc, alloc_yid, free0, free_jid0, free1, free_jid1,
clk, rst_l
);
// Translation, port 0.
input [3:0] trans_jid0;
output [9:0] trans_yid0;
output trans_valid0;
// Translation, port 1.
input [3:0] trans_jid1;
output [9:0] trans_yid1;
output trans_valid1;
// Allocating an assignment.
output alloc_stall;
input alloc;
input [9:0] alloc_yid;
output [3:0] alloc_jid;
// Free an assignment, port 0.
input free0;
input [3:0] free_jid0;
// Free an assignment, port 1.
input free1;
input [3:0] free_jid1;
// Clock and reset.
input clk;
input rst_l;
// Wires and Regs.
// JID to YID translation table.
jbi_jid_to_yid_table jid_to_yid_table (
//
// Translation, port 0.
.trans_jid0 (trans_jid0),
.trans_yid0 (trans_yid0),
//
// Translation, port 1.
.trans_jid1 (trans_jid1),
.trans_yid1 (trans_yid1),
//
// Allocating an assignment.
.alloc (alloc),
.alloc_jid (alloc_jid),
.alloc_yid (alloc_yid),
//
// Clock and reset.
.clk (clk),
.rst_l (rst_l)
);
// Free JID pool.
jbi_jid_to_yid_pool jid_to_yid_pool (
//
// Removing from pool (allocating jid).
.jid_is_avail (jid_is_avail),
.jid (alloc_jid),
.remove (alloc),
//
// Adding to pool, port 0.
.add0 (free0),
.add_jid0 (free_jid0),
//
// Adding to pool, port 1.
.add1 (free1),
.add_jid1 (free_jid1),
//
// Translation validation, port0.
.trans_jid0 (trans_jid0),
.trans_valid0 (trans_valid0),
//
// Translation validation, port1.
.trans_jid1 (trans_jid1),
.trans_valid1 (trans_valid1),
//
// System interface.
.clk (clk),
.rst_l (rst_l)
);
assign alloc_stall = ~jid_is_avail;
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Checks: 'alloc' not asserted while 'alloc_stall'.
always @(posedge clk) begin
if (alloc_stall && alloc) begin
$dispmon ("jbi_mout_jbi_jid_to_yid", 49, "%d %m: ERROR - Attempt made to allocate a JID when none are available.", $time);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../include")
// verilog-module-parents:("jbi_mout")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; if ((x == n / 2 || x == n / 2 + 1) and (y == n / 2 || y == n / 2 + 1)) cout << NO << endl; else cout << YES << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_PP_V
/**
* lsbuf: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbuf (
X ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, VPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 7; vector<long long> v[N]; long long vis[N], prt[N], bip[N], cs, ce; void dfs(long long ver, long long par) { bip[ver] = (!bip[par]); vis[ver] = 1; prt[ver] = par; for (auto it : v[ver]) { if (vis[it] == 2 || it == par) continue; if (vis[it] == 1) { cs = it; ce = ver; break; } dfs(it, ver); } vis[ver] = 2; } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, m, k; cin >> n >> m >> k; for (long long i = (long long)(1); i <= (long long)(m); i++) { long long x, y; cin >> x >> y; if (x > k || y > k) continue; v[x].push_back(y); v[y].push_back(x); } for (long long i = (long long)(1); i <= (long long)(k); i++) { if (vis[i]) continue; dfs(i, 0); } if (cs) { cout << 2 << n ; vector<long long> ans; while (cs != ce) { ans.push_back(ce); ce = prt[ce]; } ans.push_back(ce); cout << ans.size() << n ; for (auto it : ans) cout << it << ; } else { cout << 1 << n ; long long kk = k / 2 + k % 2; long long tmp = count(bip + 1, bip + k + 1, 0); if (tmp >= kk) { for (long long i = (long long)(1); i <= (long long)(k); i++) { if (kk > 0 && bip[i] == 0) { cout << i << ; kk--; } } } else { for (long long i = (long long)(1); i <= (long long)(k); i++) { if (kk > 0 && bip[i]) { cout << i << ; kk--; } } } } }
|
//=============================================================================
// Verilog module generated by IPExpress 08/21/2007 16:22:41
// Filename: USERNAME_bb.v
// Copyright(c) 2005 Lattice Semiconductor Corporation. All rights reserved.
//=============================================================================
/* WARNING - Changes to this file should be performed by re-running IPexpress
or modifying the .LPC file and regenerating the core. Other changes may lead
to inconsistent simulation and/or implemenation results */
//---------------------------------------------------------------
// USERNAME synthesis black box definition
//---------------------------------------------------------------
module pcie (
input wire sys_clk_250, // 250 Mhz Clock
input wire sys_clk_125, // 125 Mhz Clock
input wire rst_n, // asynchronous system reset.
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
input wire [7:0] rxp_data, // CH0:PCI Express data from External Phy
input wire rxp_data_k, // CH0:PCI Express Control from External Phy
input wire rxp_valid, // CH0:Indicates a symbol lock and valid data on rx_data /rx_data_k
input wire rxp_elec_idle, // CH0:Inidicates receiver detection of an electrical signal
input wire [2:0] rxp_status, // CH0:Indicates receiver Staus/Error codes
input wire phy_status, // Indicates PHY status info
// From User logic
// From User logic
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p , // Completor abort.
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// User Loop back data
input wire [15:0] tx_lbk_data, // TX User Master Loopback data
input wire [1:0] tx_lbk_kcntl, // TX User Master Loopback control
output wire tx_lbk_rdy, // TX loop back is ready to accept data
output wire [15:0] rx_lbk_data, // RX User Master Loopback data
output wire [1:0] rx_lbk_kcntl, // RX User Master Loopback control
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire [7:0] txp_data, // CH0:PCI Express data to External Phy
output wire txp_data_k, // CH0:PCI Express control to External Phy
output wire txp_elec_idle, // CH0:Tells PHY to output Electrical Idle
output wire txp_compliance, // CH0:Sets the PHY running disparity to -ve
output wire rxp_polarity, // CH0:Tells PHY to do polarity inversion on the received data
output wire txp_detect_rx_lb, // Tells PHY to begin receiver detection or begin Loopback
output wire reset_n, // Async reset to the PHY
output wire [1:0] power_down, // Tell sthe PHY to power Up or Down
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// To ASPM implementation outside the IP
output wire tx_rbuf_empty, // Transmit retry buffer is empty
output wire tx_dllp_pend, // DLPP is pending to be transmitted
output wire rx_tlp_rcvd, // Received a TLP
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up // Data Link Layer is UP
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int Read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x; } void Write(int x) { if (x < 0) putchar( - ), x = -x; if (x == 0) putchar( 0 ); int stk[55], tp = 0; while (x) stk[++tp] = x % 10, x /= 10; for (int i = tp; i; i--) putchar(stk[i] + 0 ); } int Add(int a, int b) { return (a + b >= 998244353) ? a + b - 998244353 : a + b; } int Dec(int a, int b) { return (a - b < 0) ? a - b + 998244353 : a - b; } int mul(int a, int b) { return 1ll * a * b % 998244353; } unsigned int qpow(unsigned int a, int b) { unsigned int res = 1; for (; b; b >>= 1, a = mul(a, a)) if (b & 1) res = mul(res, a); return res; } namespace NTT { int sz; unsigned int w[2500005], w_mf[2500005]; int mf(int x) { return (1ll * x << 32) / 998244353; } void init(int n) { for (sz = 2; sz < n; sz <<= 1) ; unsigned int pr = qpow(3, (998244353 - 1) / sz); w[sz / 2] = 1; w_mf[sz / 2] = mf(1); for (int i = 1; i <= sz / 2; i++) w[sz / 2 + i] = mul(w[sz / 2 + i - 1], pr), w_mf[sz / 2 + i] = mf(w[sz / 2 + i]); for (int i = sz / 2 - 1; i; i--) w[i] = w[i << 1], w_mf[i] = w_mf[i << 1]; } void ntt(vector<unsigned int>& A, int L) { for (int d = L >> 1; d; d >>= 1) for (int i = 0; i < L; i += (d << 1)) for (int j = 0; j < d; j++) { unsigned int x = A[i + j] + A[i + d + j]; if (x >= 998244353 * 2) x -= 998244353 * 2; long long t = A[i + j] + 998244353 * 2 - A[i + d + j], q = t * w_mf[d + j] >> 32, y = t * w[d + j] - q * 998244353; A[i + j] = x; A[i + d + j] = y; } for (int i = 0; i < L; i++) if (A[i] >= 998244353) A[i] -= 998244353; } void intt(vector<unsigned int>& A, int L) { for (int d = 1; d < L; d <<= 1) for (int i = 0; i < L; i += (d << 1)) for (int j = 0; j < d; j++) { unsigned int x = A[i + j]; if (x >= 998244353 * 2) x -= 998244353 * 2; long long t = A[i + d + j], q = t * w_mf[d + j] >> 32, y = t * w[d + j] - q * 998244353; A[i + j] = x + y, A[i + d + j] = x + 2 * 998244353 - y; } int k = __builtin_ctz(L); reverse(A.begin() + 1, A.end()); for (int i = 0; i < L; i++) { long long m = -A[i] & (L - 1); A[i] = (A[i] + m * 998244353) >> k; if (A[i] >= 998244353) A[i] -= 998244353; } } } // namespace NTT struct poly { vector<unsigned int> a; poly(int d = 0, int t = 0) { a.resize(d + 1); a[d] = t; } int deg() { return a.size() - 1; } unsigned int& operator[](const int& b) { return a[b]; } poly extend(int x) { poly c = *this; c.a.resize(x + 1); return c; } void resize(int x) { a.resize(x); } int size() { return a.size(); } void Get(int n) { a.resize(n + 1); for (int i = 0; i <= n; i++) a[i] = Read(); } void Print(int n) { for (int i = 0; i <= n; i++) Write(a[i]), putchar( ); puts( ); } friend poly operator*(poly A, poly B) { int n = A.deg() + B.deg() + 1, lim = 2; for (; lim < n; lim <<= 1) ; NTT::init(lim); A.resize(lim); B.resize(lim); NTT::ntt(A.a, lim); NTT::ntt(B.a, lim); for (int i = 0; i < lim; i++) A[i] = mul(A[i], B[i]); NTT::intt(A.a, lim); return A.extend(n - 1); } poly inv(poly A) { int n = A.a.size(), lim = 2; if (n == 1) return A[0] = qpow(A[0], 998244353 - 2), A; poly B = A; B.resize((n + 1) >> 1); B = inv(B); for (; lim < (n << 1); lim <<= 1) ; NTT::init(lim); A.resize(lim), B.resize(lim), NTT::ntt(A.a, lim); NTT::ntt(B.a, lim); for (int i = 0; i < lim; i++) A[i] = mul(Dec(2, mul(A[i], B[i])), B[i]); NTT::intt(A.a, lim); return A.extend(n - 1); } poly getinv() { return inv(*this); } poly getdao() { poly A = *this, B; int n = A.a.size(); B.resize(n); for (int i = 1; i < n; i++) B[i - 1] = mul(A[i], i); B[n - 1] = 0; return B; } poly getjf() { poly A = *this, B; int n = A.a.size(); B.resize(n); for (int i = 1; i < n; i++) B[i] = mul(A[i - 1], qpow(i, 998244353 - 2)); B[0] = 0; return B; } poly getln() { poly A = *this; return (A.getdao() * A.getinv()).extend(A.deg()).getjf(); } poly exp(poly A) { int n = A.a.size(); if (n == 1) return A[0] = 1, A; poly B = A; B.resize((n + 1) >> 1); B = exp(B); poly C = B.getln(); C.resize(n); for (int i = 0; i < n; i++) C[i] = Dec(A[i], C[i]); ++C[0]; return (B * C).extend(n - 1); } poly getexp() { return exp(*this); } poly getmi(int k) { poly A = *this; int n = A.a.size(); poly B = A.getln(); for (int i = 0; i < n; i++) B[i] = mul(B[i], k); return B.getexp(); } poly sqrt(poly A) { int n = A.size(), lim = 2; if (n == 1) return A[0] = 1, A; poly B = A; B.resize((n + 1) >> 1); B = sqrt(B); poly C = A.extend(n - 1), D = B.getinv(); for (; lim < (n << 1); lim <<= 1) ; NTT::init(lim); B.resize(lim), C.resize(lim), D.resize(lim), NTT::ntt(B.a, lim); NTT::ntt(C.a, lim); NTT::ntt(D.a, lim); for (int i = 0; i < lim; i++) B[i] = mul(Add(B[i], mul(C[i], D[i])), 499122177); NTT::intt(B.a, lim); return B.extend(n - 1); } poly getsqrt() { return sqrt(*this); } }; signed main() { int n = Read(), k = Read(); poly A, B; A.resize(k * 3), B.resize(k * 3); A[0] = 1; A[1] = 6; A[2] = 1; A = A.getsqrt(); B = A.getinv(); ++A[1]; ++A[0]; for (int i = 0; i <= k; i++) A[i] = 1ll * A[i] * 499122177 % 998244353; A = A.getmi(n + 1); A = (A * B).extend(k * 3); for (int i = 1; i <= k; i++) { if (i <= n) printf( %d , A[i]); else printf( %d , 0); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_4_V
`define SKY130_FD_SC_LS__A211OI_4_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_4_V
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