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#include <bits/stdc++.h> using namespace std; const int maxn = 100123; const int lgn = 20; long long a[maxn], f[maxn][lgn], ans; vector<int> G[maxn]; void dfs(int u, int p, int x) { int w = a[u] >> x & 1; f[u][w] = 1, f[u][w ^ 1] = 0; for (auto& v : G[u]) { if (v != p) { dfs(v, u, x); ans += (1 << x) * (f[u][1] * f[v][0] + f[u][0] * f[v][1]); f[u][w] += f[v][0]; f[u][w ^ 1] += f[v][1]; } } } int main() { cin.sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < (n); ++i) cin >> a[i], ans += a[i]; for (int i = 0; i < (n - 1); ++i) { int u, v; cin >> u >> v; --u, --v; G[u].push_back(v); G[v].push_back(u); } for (int i = 0; i < (lgn); ++i) dfs(0, -1, i); cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; bool vis[500005]; int low[500005], d[500005], par[500005], rnk[500005], lev[500005], timer; vector<int> adj[500005], tree[500005]; vector<pair<int, int>> edges; map<int, map<int, int>> ed, br; int get(int x) { return (par[x] == x ? x : par[x] = get(par[x])); } void link(int x, int y) { x = get(x); y = get(y); if (x == y) return; par[x] = y; } void bridge_find(int u, int par) { timer++; d[u] = low[u] = timer; for (auto x : adj[u]) { if (x == par) continue; if (d[x] > 0) { low[u] = min(low[u], d[x]); if (ed[x][u] == 0) ed[u][x] = 1; } else { bridge_find(x, u); low[u] = min(low[u], low[x]); if (d[u] < low[x]) br[u][x] = 1, br[x][u] = 1; else { ed[u][x] = 1; link(u, x); } } } } void dfs(int child, int par) { vis[child] = 1; for (auto x : adj[child]) { if (x == par) continue; if (br[x][child]) ed[x][child] = 1; if (!vis[x]) dfs(x, child); } } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) rnk[i] = 1, par[i] = i; for (int i = 0; i < m; i++) { int x, y; scanf( %d %d , &x, &y); edges.push_back({x, y}); adj[x].push_back(y); adj[y].push_back(x); } bridge_find(1, -1); int mx = 0, cur; for (int i = 1; i <= n; i++) { int x; x = get(i); lev[x]++; if (mx < lev[x]) { mx = lev[x], cur = x; } } dfs(cur, -1); cout << mx << endl; for (int i = 0; i < m; i++) { if (ed[edges[i].first][edges[i].second]) cout << edges[i].first << << edges[i].second << endl; else if (ed[edges[i].second][edges[i].first]) cout << edges[i].second << << edges[i].first << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSTP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_SYMBOL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd3 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_PP_SYMBOL_V
|
`timescale 1ns / 1ps
// This module is a third order delta/sigma modulator
// It uses no multiply only shifts by 1, 2 or 13
// There are only 7 adders used, it takes around 110 LUTs
module hq_dac
(
input reset,
input clk,
input clk_ena,
input [19:0] pcm_in,
output reg dac_out
);
// ======================================
// ============== Stage #1 ==============
// ======================================
wire [23:0] w_data_in_p0;
wire [23:0] w_data_err_p0;
wire [23:0] w_data_int_p0;
reg [23:0] r_data_fwd_p1;
// PCM input extended to 24 bits
assign w_data_in_p0 = { {4{pcm_in[19]}}, pcm_in };
// Error between the input and the quantizer output
assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
// First integrator adder
assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+ r_data_fwd_p1;
// First integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p1 <= 24'd0;
else if (clk_ena)
r_data_fwd_p1 <= w_data_int_p0;
// ======================================
// ============== Stage #2 ==============
// ======================================
wire [23:0] w_data_fb1_p1;
wire [23:0] w_data_fb2_p1;
wire [23:0] w_data_lpf_p1;
reg [23:0] r_data_lpf_p2;
// Feedback from the quantizer output
assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
- { {3{w_data_qt_p2[23]}}, w_data_qt_p2[22:2] }; // Divide by 4
// Feedback from the third stage
assign w_data_fb2_p1 = w_data_fb1_p1
- { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
// Low pass filter
assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
// Low pass filter feedback delay
always @(posedge reset or posedge clk)
if (reset)
r_data_lpf_p2 <= 24'd0;
else if (clk_ena)
r_data_lpf_p2 <= w_data_lpf_p1;
// ======================================
// ============== Stage #3 ==============
// ======================================
wire [23:0] w_data_fb3_p1;
wire [23:0] w_data_int_p1;
reg [23:0] r_data_fwd_p2;
// Feedback from the quantizer output
assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
- { {2{w_data_qt_p2[23]}}, w_data_qt_p2[22:1] }; // Divide by 2
// Second integrator adder
assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
// Second integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p2 <= 24'd0;
else if (clk_ena)
r_data_fwd_p2 <= w_data_int_p1;
// =====================================
// ========== 1-bit quantizer ==========
// =====================================
wire [23:0] w_data_qt_p2;
assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
always @(posedge reset or posedge clk)
if (reset)
dac_out <= 1'b0;
else if (clk_ena)
dac_out <= ~r_data_fwd_p2[23];
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
// local paramaters used as defines
parameter WINDOW_START = 1'b0;
parameter WINDOW_CHECK = 1'b1;
reg r_state;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=WINDOW_START;
end
`endif
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
wire valid_end_event;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
assign valid_end_event = ~(end_event^end_event);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
case (r_state)
WINDOW_START: begin
if (start_event == 1'b1) begin
r_state <= WINDOW_CHECK;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_start_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end // WINDOW_START
WINDOW_CHECK: begin
if (end_event == 1'b1) begin
r_state <= WINDOW_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window covered");
end
end
`endif // OVL_COVER_ON
end
`ifdef OVL_ASSERT_ON
if (test_expr != 1'b1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression changed value during an open event window");
end
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (valid_end_event == 1'b1)
begin
//Do Nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end // WINDOW_CHECK
endcase
end
else begin
r_state <= WINDOW_START;
end
end // always
`endif // OVL_SHARED_CODE
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, a, k = 0; vector<int> v; cin >> n; for (i = 0; i < n; i++) { cin >> a; v.push_back(a); } sort(v.begin(), v.end(), greater<int>()); for (i = 0; i <= n - 3; i++) { if (v[i] < v[i + 1] + v[i + 2]) k++; } if (k > 0) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4_4_V
`define SKY130_FD_SC_HS__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_4_V
`define SKY130_FD_SC_HD__O21BAI_4_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_4_V
|
`default_nettype none
/***********************************************************************************************************************
* Copyright (C) 2016-2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
module ConfigurableEdgeFlipflop(
d, clk, ce, sr, srval, q, rising_en, falling_en
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
input wire d;
input wire clk;
input wire ce;
output wire q;
input wire sr;
input wire srval;
input wire rising_en;
input wire falling_en;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual FFs
//Rising edge
wire rising_ff;
FDCPE #(
.INIT(1'b0)
) rising (
.Q(rising_ff),
.C(clk),
.CE(ce & rising_en),
.CLR(sr && srval==0),
.D(d ^ falling_ff),
.PRE(sr && srval==1)
);
//Falling edge
wire falling_ff;
FDCPE #(
.INIT(1'b0)
) falling (
.Q(falling_ff),
.C(!clk),
.CE(ce & falling_en),
.CLR(sr), //always clear this FF to zero
.D(d ^ rising_ff),
.PRE(1'b0)
);
//XOR the outputs together
assign q = rising_ff ^ falling_ff;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { scanf( %d%d , &n, &m); long long dp[m + 2]; int now = 0; int c, sum = 0; for (int i = 0; i < m; i++) { scanf( %d , &c); sum += c; dp[i] = sum; } dp[0] = -2147483647; long long ans = -2147483647; long long mm[m + 2]; for (int i = m - 1; i >= 0; i--) { if (i == m - 1) mm[i] = dp[i]; else mm[i] = max(dp[i], mm[i + 1]); } for (int i = 1; i < n; i++) { sum = 0; now = 1 - now; for (int j = 0; j < m; j++) { scanf( %d , &c); sum += c; dp[j] = sum; } for (int j = 0; j < m; j++) { if (i % 2 == 1) { if (j < m - 1) { dp[j] += mm[j + 1]; } else if (j == m - 1) { dp[j] = -2147483647; } } else { if (j == 0) dp[j] = -2147483647; else { dp[j] += mm[j - 1]; } } if (i == n - 1) { ans = max(ans, dp[j]); } } if (i % 2 == 0) { for (int j = m - 1; j >= 0; j--) { if (j == m - 1) mm[j] = dp[j]; else mm[j] = max(dp[j], mm[j + 1]); } } else { for (int j = 0; j < m; j++) { if (j == 0) mm[j] = dp[j]; else mm[j] = max(dp[j], mm[j - 1]); } } } printf( %I64d n , ans); return 0; }
|
//==================================================================================================
// Filename : CORDIC_FSM_v3.v
// Created On : 2016-10-03 15:59:21
// Last Modified : 2016-10-28 22:39:59
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : CORDIC's FSM Unit
//
//
//==================================================================================================
`timescale 1ns / 1ps
module CORDIC_FSM_v3
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
input wire exception,
input wire max_tick_iter, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
input wire max_tick_var, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
input wire enab_dff_z,
//Output Signals
//output reg reset_reg_cordic,
output reg ready_CORDIC, // Señal que indica que el calculo CORDIC se ha terminado.
output reg beg_add_subt, // Señal que indica al modulo de suma/resta que inicie su operacion.
output reg enab_cont_iter, // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
output reg enab_cont_var, // Señales de habilitacion y carga, respectivamente, en el contador de variables.
output reg enab_RB1, enab_RB2, enab_RB3,
output reg enab_d_ff5_data_out
);
//symbolic state declaration
/*localparam [3:0] est0 = 8'b0000000,
est1 = 8'b0000001,
est2 = 8'b0000010,
est3 = 8'b0000100,
est4 = 8'b0001000,
est5 = 8'b0010000,
est6 = 8'b0100000,
est7 = 8'b1000000;*/
parameter est0 = 8'b00000001;
parameter est1 = 8'b00000010;
parameter est2 = 8'b00000100;
parameter est3 = 8'b00001000;
parameter est4 = 8'b00010000;
parameter est5 = 8'b00100000;
parameter est6 = 8'b01000000;
parameter est7 = 8'b10000000;
//signal declaration
reg [7:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge reset)
begin
if(reset) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
// reset_reg_cordic = 0;
enab_RB1 = 0;
enab_RB2 = 0;
enab_RB3 = 0;
enab_cont_var = 0;
enab_cont_iter = 0;
enab_d_ff5_data_out = 0;
ready_CORDIC = 0;
beg_add_subt = 0;
case(state_reg)
est0:
begin
// reset_reg_cordic = 1'b1;
enab_RB1 = 1'b1;
if(beg_FSM_CORDIC) begin
state_next = est1;
end else begin
state_next = est0;
end
end
est1:
begin
enab_RB1 = 1'b1;
state_next = est2;
end
est2:
begin
enab_RB2 = 1'b1;
if(exception) begin
state_next = est0;
end else begin
state_next = est3;
end
end
est3:
begin
enab_RB3 = 1'b1;
state_next = est4;
end
est4:
begin
enab_cont_var = 1'b1; //cont_var++
beg_add_subt = 1'b1;
if (max_tick_var) begin
state_next = est5;
end else begin
state_next = est4;
end
end
est5:
begin
beg_add_subt = 1'b1;
if (enab_dff_z) begin
state_next = est6;
end else begin
state_next = est5;
end
end
est6:
begin
enab_cont_iter = 1'b1; //cont_iter++
enab_cont_var = 1'b1; //rst cont to from 3 to 0
if (max_tick_iter) begin
state_next = est7; //Es la ultima iteracion, por lo tanto, seguimos a la siguiente etapa
enab_d_ff5_data_out = 1;
end else begin
state_next = est2; //Seguir las iteraciones
//
end
end
est7:
begin
ready_CORDIC = 1'b1;
enab_d_ff5_data_out = 1'b1;
if(ACK_FSM_CORDIC) begin
state_next = est0;
end else begin
state_next = est7;
end
end
default :
begin
state_next = est0;
end
endcase
end
endmodule
|
module axi_conduit_merger #(
parameter ID_WIDTH = 1,
parameter DATA_WIDTH = 32,
parameter ADDRESS_WIDTH = 32,
parameter AXUSER_WIDTH = 5
) (
// axi master
output m_awvalid,
output [3:0] m_awlen ,
output [2:0] m_awsize ,
output [1:0] m_awburst,
output [1:0] m_awlock ,
output [3:0] m_awcache,
output [2:0] m_awprot ,
input m_awready,
output [AXUSER_WIDTH-1:0] m_awuser ,
output m_arvalid,
output [3:0] m_arlen ,
output [2:0] m_arsize ,
output [1:0] m_arburst,
output [1:0] m_arlock ,
output [3:0] m_arcache,
output [2:0] m_arprot ,
input m_arready,
output [AXUSER_WIDTH-1:0] m_aruser ,
input m_rvalid ,
input m_rlast ,
input [1:0] m_rresp ,
output m_rready ,
output m_wvalid ,
output m_wlast ,
input m_wready ,
input m_bvalid ,
input [1:0] m_bresp ,
output m_bready ,
output [ADDRESS_WIDTH-1:0] m_awaddr ,
output [ID_WIDTH-1:0] m_awid ,
output [ADDRESS_WIDTH-1:0] m_araddr ,
output [ID_WIDTH-1:0] m_arid ,
input [DATA_WIDTH-1:0] m_rdata ,
input [ID_WIDTH-1:0] m_rid ,
output [DATA_WIDTH-1:0] m_wdata ,
output [DATA_WIDTH/8-1:0] m_wstrb ,
output [ID_WIDTH-1:0] m_wid ,
input [ID_WIDTH-1:0] m_bid ,
// axi slave
input s_awvalid,
input [3:0] s_awlen ,
input [2:0] s_awsize ,
input [1:0] s_awburst,
input [1:0] s_awlock ,
input [3:0] s_awcache,
input [2:0] s_awprot ,
output s_awready,
input [AXUSER_WIDTH-1:0] s_awuser ,
input s_arvalid,
input [3:0] s_arlen ,
input [2:0] s_arsize ,
input [1:0] s_arburst,
input [1:0] s_arlock ,
input [3:0] s_arcache,
input [2:0] s_arprot ,
output s_arready,
input [AXUSER_WIDTH-1:0] s_aruser ,
output s_rvalid ,
output s_rlast ,
output [1:0] s_rresp ,
input s_rready ,
input s_wvalid ,
input s_wlast ,
output s_wready ,
output s_bvalid ,
output [1:0] s_bresp ,
input s_bready ,
input [ADDRESS_WIDTH-1:0] s_awaddr,
input [ID_WIDTH-1:0] s_awid ,
input [ADDRESS_WIDTH-1:0] s_araddr,
input [ID_WIDTH-1:0] s_arid ,
output [DATA_WIDTH-1:0] s_rdata ,
output [ID_WIDTH-1:0] s_rid ,
input [DATA_WIDTH-1:0] s_wdata ,
input [DATA_WIDTH/8-1:0] s_wstrb ,
input [ID_WIDTH-1:0] s_wid ,
output [ID_WIDTH-1:0] s_bid ,
// conduits
input [3:0] c_awcache,
input [2:0] c_awprot ,
input [AXUSER_WIDTH-1:0] c_awuser,
input [3:0] c_arcache,
input [2:0] c_arprot ,
input [AXUSER_WIDTH-1:0] c_aruser,
// clock and reset
input clk,
input rst_n
);
wire axi_wbus_bp;
wire axi_rbus_bp;
wire [3:0] v_awcache;
wire [2:0] v_awprot;
wire [AXUSER_WIDTH-1:0] v_awuser;
reg [3:0] r_awcache;
reg [2:0] r_awprot;
reg [AXUSER_WIDTH-1:0] r_awuser;
wire [3:0] v_arcache;
wire [2:0] v_arprot;
wire [AXUSER_WIDTH-1:0] v_aruser;
reg [3:0] r_arcache;
reg [2:0] r_arprot;
reg [AXUSER_WIDTH-1:0] r_aruser;
assign axi_wbus_bp = s_awvalid & ~m_awready;
assign v_awcache = (!axi_wbus_bp) ? c_awcache : r_awcache;
assign v_awprot = (!axi_wbus_bp) ? c_awprot : r_awprot;
assign v_awuser = (!axi_wbus_bp) ? c_awuser : r_awuser;
assign v_arcache = (!axi_rbus_bp) ? c_arcache : r_arcache;
assign v_arprot = (!axi_rbus_bp) ? c_arprot : r_arprot;
assign v_aruser = (!axi_rbus_bp) ? c_aruser : r_aruser;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r_awcache <= 4'd0;
r_awprot <= 3'd0;
r_awuser <= {AXUSER_WIDTH{1'b0}};
r_arcache <= 4'd0;
r_arprot <= 3'd0;
r_aruser <= {AXUSER_WIDTH{1'b0}};
end
else begin
r_awcache <= v_awcache;
r_awprot <= v_awprot;
r_awuser <= v_awuser;
r_arcache <= v_arcache;
r_arprot <= v_arprot;
r_aruser <= v_aruser;
end
end
// conduit signals replacement
assign m_awcache = r_awcache;
assign m_awprot = r_awprot;
assign m_awuser = r_awuser;
assign m_arcache = r_arcache;
assign m_arprot = r_arprot;
assign m_aruser = r_aruser;
// axi bus assignment
assign m_awvalid = s_awvalid ;
assign m_awlen = s_awlen ;
assign m_awsize = s_awsize ;
assign m_awburst = s_awburst ;
assign m_awlock = s_awlock ;
// assign m_awcache = s_awcache;
// assign m_awprot = s_awprot ;
// assign m_awuser = s_awuser ;
assign m_awaddr = s_awaddr ;
assign m_awid = s_awid ;
assign s_awready = m_awready ;
assign m_arvalid = s_arvalid ;
assign m_arlen = s_arlen ;
assign m_arsize = s_arsize ;
assign m_arburst = s_arburst ;
assign m_arlock = s_arlock ;
// assign m_arcache = s_arcache;
// assign m_arprot = s_arprot ;
// assign m_aruser = s_aruser ;
assign m_araddr = s_araddr ;
assign m_arid = s_arid ;
assign s_arready = m_arready ;
assign s_rvalid = m_rvalid ;
assign s_rlast = m_rlast ;
assign s_rresp = m_rresp ;
assign s_rdata = m_rdata ;
assign s_rid = m_rid ;
assign m_rready = s_rready ;
assign m_wvalid = s_wvalid ;
assign m_wlast = s_wlast ;
assign m_wdata = s_wdata ;
assign m_wstrb = s_wstrb ;
assign m_wid = s_wid ;
assign s_wready = m_wready ;
assign s_bvalid = m_bvalid ;
assign s_bresp = m_bresp ;
assign s_bid = m_bid ;
assign m_bready = s_bready ;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[2000]; vector<int> w[2000]; vector<int> z; int f[2000]; int c[2000]; void dfs(int x) { f[x] = 1; for (int i = 0; i < v[x].size(); i++) { if (f[v[x][i]] == 0) dfs(v[x][i]); } z.push_back(x); } void dfs2(int x, int k) { f[x] = 1; c[x] = k; for (int i = 0; i < w[x].size(); i++) { if (f[w[x][i]] == 0) dfs2(w[x][i], k); } } int scc(int n) { int k = 0; for (int i = 0; i < n; i++) f[i] = 0; z.clear(); for (int i = 0; i < n; i++) { if (f[i] == 0) dfs(i); } for (int i = 0; i < n; i++) f[i] = 0; for (int i = z.size() - 1; i >= 0; i--) { if (f[z[i]] == 0) dfs2(z[i], k++); } return k; } int main() { int n, i, j; scanf( %d , &n); for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { int x; scanf( %d , &x); if (x > 0) { v[i].push_back(j); w[j].push_back(i); } } } if (scc(n) == 1) { puts( YES ); } else { puts( NO ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 400005; char a[N]; int n, k, delta, top, st[N]; bool vis[N]; int main() { scanf( %d%d , &n, &k), scanf( %s , a + 1); delta = (n - k) / 2, top = 0; for (int i = 1; i <= n; ++i) { if (a[i] == ( ) st[++top] = i; else { if (delta) { --delta, vis[i] = 1; vis[st[top]] = 1; } --top; } } for (int i = 1; i <= n; ++i) if (!vis[i]) printf( %c , a[i]); puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2222; const int INF = 0x3f3f3f3f; int n, m, k, s; int mat[2][N][9], cp[9][9]; void tomin(int &a, int b) { if (a > b) a = b; } void tomax(int &a, int b) { if (a < b) a = b; } void work() { for (int i = 0; i < m; i++) for (int j = 0; j < k; j++) { for (int r = i; r < m; r++) for (int p = 0; p < k; p++) { tomax(cp[j][p], abs(r - i) + mat[1][i][j] - mat[0][r][p]); tomax(cp[j][p], abs(r - i) + mat[1][r][p] - mat[0][i][j]); tomax(cp[p][j], cp[j][p]); } } int d, ans = 0; scanf( %d , &d); d--; for (int i = 1; i < s; i++) { int x; scanf( %d , &x); x--; tomax(ans, cp[d][x]); d = x; } printf( %d n , ans); } int main() { scanf( %d%d%d%d , &n, &m, &k, &s); memset(mat[0], INF, sizeof(mat[0])); memset(mat[1], -1, sizeof(mat[1])); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int d; scanf( %d , &d); d--; tomin(mat[0][j][d], i); tomax(mat[1][j][d], i); } work(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long min_val(long long a, long long b) { if (a <= b) return a; else return b; } long long max_val(long long a, long long b) { if (a >= b) return a; else return b; } long long abs(long long a, long long b) { long long tmp = min_val(a, b); if (tmp == a) { return b - a; } else return a - b; } int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n, greater<int>()); for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { vector<pair<int, int>> st, re; int a, b; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; st.emplace_back(a, b); re.emplace_back(b, a); } sort(st.begin(), st.end()); sort(re.begin(), re.end()); cout << max(st[n - 1].first - re[0].first, 0) << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct SNM { vector<SNM*> trgs; vector<SNM*> rv_trgs; int stype; bool asgn; bool used; void asgnN() { if (asgn) return; asgn = true; for (vector<SNM*>::iterator i = trgs.begin(); i != trgs.end(); i++) { (*i)->asgnN(); } } void usedN() { if (used) return; used = true; if (stype == 1) return; for (vector<SNM*>::iterator i = rv_trgs.begin(); i != rv_trgs.end(); i++) { (*i)->usedN(); } } SNM() { used = false; asgn = false; } }; SNM nodes[100000]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &nodes[i].stype); } for (int i = 0; i < m; i++) { int a, b; scanf( %d%d , &a, &b); a--; b--; nodes[a].trgs.push_back(&nodes[b]); nodes[b].rv_trgs.push_back(&nodes[a]); } for (int i = 0; i < n; i++) { if (nodes[i].stype == 1) { nodes[i].asgnN(); } } for (int i = 0; i < n; i++) { if (nodes[i].stype == 2) { nodes[i].usedN(); } } for (int i = 0; i < n; i++) { if (nodes[i].asgn && nodes[i].used) { printf( 1 n ); } else { printf( 0 n ); } } return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all DC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_top.v,v $
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//
// Data cache
//
module or1200_dc_top_wrapper(
// Rst, clk and clock control
clk, rst,
// External i/f
dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
// Internal i/f
dc_en,
dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] dcsb_dat_o;
output [31:0] dcsb_adr_o;
output dcsb_cyc_o;
output dcsb_stb_o;
output dcsb_we_o;
output [3:0] dcsb_sel_o;
output dcsb_cab_o;
input [dw-1:0] dcsb_dat_i;
input dcsb_ack_i;
input dcsb_err_i;
//
// Internal I/F
//
input dc_en;
input [31:0] dcqmem_adr_i;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input [3:0] dcqmem_tag_i;
input [dw-1:0] dcqmem_dat_i;
output [dw-1:0] dcqmem_dat_o;
output dcqmem_ack_o;
output dcqmem_rty_o;
output dcqmem_err_o;
output [3:0] dcqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_DCTAG_W-2:0] tag;
wire [dw-1:0] to_dcram;
wire [dw-1:0] from_dcram;
wire [3:0] dcram_we;
wire dctag_we;
wire [31:0] dc_addr;
reg tagcomp_miss;
wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
wire dctag_en;
wire dctag_v;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Instantiation of DC Top module
//
//
// Instantiation of Data Cache
//
or1200_dc_top or1200_dc_top(
.clk(clk),
.rst(rst),
// DC and QMEM
.dc_en(dc_en),
.dcqmem_adr_i(dcqmem_adr_i),
.dcqmem_cycstb_i(dcqmem_cycstb_i),
.dcqmem_ci_i(dcqmem_ci_i),
.dcqmem_we_i(dcqmem_we_i),
.dcqmem_sel_i(dcqmem_sel_i),
.dcqmem_tag_i(dcqmem_tag_i),
.dcqmem_dat_i(dcqmem_dat_i),
.dcqmem_dat_o(dcqmem_dat_o),
.dcqmem_ack_o(dcqmem_ack_o),
.dcqmem_rty_o(dcqmem_rty_o),
.dcqmem_err_o(dcqmem_err_o),
.dcqmem_tag_o(dcqmem_tag_o),
// SPR access
.spr_cs(spr_cs),
.spr_write(spr_write),
.spr_dat_i(spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS]),
// DC and BIU
.dcsb_dat_o(dcsb_dat_o),
.dcsb_adr_o(dcsb_adr_o),
.dcsb_cyc_o(dcsb_cyc_o),
.dcsb_stb_o(dcsb_stb_o),
.dcsb_we_o(dcsb_we_o),
.dcsb_sel_o(dcsb_sel_o),
.dcsb_cab_o(dcsb_cab_o),
.dcsb_dat_i(dcsb_dat_i),
.dcsb_ack_i(dcsb_ack_i),
.dcsb_err_i(dcsb_err_i),
.tag_v(tag_v),
.tag(tag),
.from_dcram(from_dcram),
.dc_addr(dc_addr),
.dcram_we(dcram_we),
.to_dcram(to_dcram),
.dctag_addr(dctag_addr),
.dctag_en(dctag_en),
.dctag_we(dctag_we),
.dctag_v(dctag_v)
);
//
// Instantiation of DC main memory
//
or1200_dc_ram or1200_dc_ram(
.clk(clk),
.rst(rst),
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
.we(dcram_we),
.datain(to_dcram),
.dataout(from_dcram)
);
//
// Instantiation of DC TAG memory
//
or1200_dc_tag or1200_dc_tag(
.clk(clk),
.rst(rst),
.addr(dctag_addr),
.en(dctag_en),
.we(dctag_we),
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_SYMBOL_V
/**
* udp_isolatch_pp$PKG$s: Power isolating latch. Includes VPWR, KAPWR,
* and VGND power pins with active low sleep
* pin (SLEEP_B).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_isolatch_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_SYMBOL_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous adds in assignment..dependent on always + working
//
// $Log: wireadd1.v,v $
// Revision 1.2 2001/05/03 05:45:37 ka6s
// Lets try this again
//
//
module main;
reg globvar;
reg [3:0] var1,var2,var3;
wire [3:0] var3a;
reg error;
assign var3a = var1 + var2;
always @( var1 or var2)
var3 = var1 + var2 ;
initial
begin
error = 0;
for ( var1 = 4'b0; var1 != 4'hf; var1 = var1 + 1)
for ( var2 = 4'b0; var2 != 4'hf; var2 = var2 + 1)
begin
#1 ;
if(var3 !== var3a)
error = 1;
#1;
end
if(error == 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule // main
|
#include <bits/stdc++.h> const long double ACOSPI = (acosl(-1.0)); using namespace std; int main() { int n = 0; int i = 0; int x = 0; long long ans = 0; map<int, long long> m; int a = 0; cin >> n >> x; for (i = 0; i < n; i++) { cin >> a; ans += m[a]; m[x ^ a]++; } cout << ans; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRBN_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_BLACKBOX_V
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
module Latch(d, q, q2, clk, nrst);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P3" *)
input wire d;
(* LOC = "P4" *)
output wire q;
(* LOC = "P5" *)
input wire clk;
(* LOC = "P6" *)
input wire nrst;
(* LOC = "P7" *)
output reg q2 = 0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// An inverted flipflop
GP_DLATCHRI #(
.INIT(1'b0)
) latch (
.D(d),
.nQ(q),
.nCLK(clk),
.nRST(nrst)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// A D latch inferred from behavioral verilog
always @(*) begin
if(!clk)
q2 <= ~d;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ans, a[300123], maxx[300123], minx[300123], box[800123]; void dopart(long long l, long long r) { if (l == r) { ans++; return; } long long mid = (l + r) / 2; dopart(l, mid); dopart(mid + 1, r); maxx[mid] = a[mid], minx[mid] = a[mid]; for (long long i = mid - 1; i >= l; i--) { maxx[i] = max(maxx[i + 1], a[i]), minx[i] = min(minx[i + 1], a[i]); } maxx[mid + 1] = a[mid + 1], minx[mid + 1] = a[mid + 1]; for (long long i = mid + 2; i <= r; i++) { maxx[i] = max(maxx[i - 1], a[i]), minx[i] = min(minx[i - 1], a[i]); } for (long long i = mid; i >= l; i--) { long long now = maxx[i] - minx[i]; if (i + now <= mid || i + now > r) continue; if (maxx[now + i] <= maxx[i] && minx[now + i] >= minx[i]) ans++; } for (long long i = mid + 1; i <= r; i++) { long long now = maxx[i] - minx[i]; if (i - now >= mid + 1 || i - now < l) continue; if (maxx[i - now] <= maxx[i] && minx[i - now] >= minx[i]) ans++; } long long you1 = mid + 1, you2 = mid + 1; for (long long i = mid; i >= l; i--) { while (you2 <= r && maxx[you2] < maxx[i]) box[minx[you2] + you2]++, you2++; while (you1 < you2 && minx[you1] > minx[i]) box[minx[you1] + you1]--, you1++; ans = ans + box[i + maxx[i]]; } for (long long i = you1; i < you2; i++) box[minx[i] + i]--; long long zuo1 = mid, zuo2 = mid; for (long long i = mid + 1; i <= r; i++) { while (zuo1 >= l && maxx[zuo1] < maxx[i]) box[minx[zuo1] - zuo1 + n + 1]++, zuo1--; while (zuo2 > zuo1 && minx[zuo2] > minx[i]) box[minx[zuo2] - zuo2 + n + 1]--, zuo2--; ans = ans + box[maxx[i] - i + n + 1]; } for (long long i = zuo2; i > zuo1; i--) box[minx[i] - i + n + 1]--; } int main() { cin >> n; for (long long i = 1; i <= n; i++) { long long p, q; cin >> p >> q; a[p] = q; } dopart(1, n); cout << ans; }
|
#include <bits/stdc++.h> int b[100005], a[100005], n, x, A, k; int main() { while (~scanf( %d %d , &n, &k)) { memset(b, 0, sizeof(b)); scanf( %d , &a[1]); x = 2; for (int i = 2; i <= n; i++) { scanf( %d , &A); if (A != a[x - 1]) a[x++] = A; } for (int i = 1; i < x; i++) { b[a[i]]++; if (i < x - 1 && i > 0) { if (a[i - 1] == a[i + 1]) b[a[i]]++; } } int y = 1; if (x == k + 1) printf( 1 n ); else { for (int i = 2; i <= k; i++) { if (b[i] > b[y]) y = i; } printf( %d n , y); } } return 0; }
|
module msg_rx(
input clk_sys,
input [0:7] data_in,
input data_in_ready,
output reg ready,
output reg r,
output reg w,
output reg in,
output reg pa,
output reg ok,
output reg pe,
output reg en,
output reg cpd,
output reg cpr,
output reg cpf,
output reg cps,
output reg [0:7] a1,
output reg [0:15] a2,
output reg [0:15] a3
);
reg [0:7] tcmd;
reg [0:7] ta1;
reg [0:15] ta2;
reg [0:15] ta3;
wire [1:3] arg = tcmd[5:7];
// --- Decoder -----------------------------------------------------------
wire xr, xw, xin, xpa, xok, xpe, xen, xcpd, xcpr, xcpf, xcps;
msg_cmd_dec MSG_CMD_DEC(
.cmd(tcmd),
.r(xr),
.w(xw),
.in(xin),
.pa(xpa),
.ok(xok),
.pe(xpe),
.en(xen),
.cpd(xcpd),
.cpr(xcpr),
.cpf(xcpf),
.cps(xcps)
);
// --- Receiver ----------------------------------------------------------
localparam IDLE = 4'd0;
localparam ARG = 4'd1;
localparam A1 = 4'd2;
localparam A2H = 4'd3;
localparam A2L = 4'd4;
localparam A3H = 4'd5;
localparam A3L = 4'd6;
localparam DONE = 4'd7;
reg [0:2] state = IDLE;
always @ (posedge clk_sys) begin
ready <= 0;
case (state)
IDLE: begin
if (data_in_ready) begin
tcmd <= data_in;
state <= ARG;
end
end
ARG: begin
if (arg[1]) state <= A1;
else if (arg[2]) state <= A2H;
else if (arg[3]) state <= A3H;
else state <= DONE;
end
A1: begin
if (data_in_ready) begin
ta1 <= data_in;
if (arg[2]) state <= A2H;
else if (arg[3]) state <= A3H;
else state <= DONE;
end
end
A2H: begin
if (data_in_ready) begin
ta2[0:7] <= data_in;
state <= A2L;
end
end
A2L: begin
if (data_in_ready) begin
ta2[8:15] <= data_in;
if (arg[3]) state <= A3H;
else state <= DONE;
end
end
A3H: begin
if (data_in_ready) begin
ta3[0:7] <= data_in;
state <= A3L;
end
end
A3L: begin
if (data_in_ready) begin
ta3[8:15] <= data_in;
state <= DONE;
end
end
DONE: begin
{ r, w, in, pa, ok, pe, en } <= { xr, xw, xin, xpa, xok, xpe, xen };
{ cpd, cpr, cpf, cps } <= { xcpd, xcpr, xcpf, xcps };
a1 <= ta1;
a2 <= ta2;
a3 <= ta3;
ready <= 1;
state <= IDLE;
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> #define int long long using namespace std; const int MAX = 505; int n, MOD, fact[MAX], C[MAX][MAX], f[2][MAX * MAX]; int getMaxInv(int x) { return (x - 1) * x / 2; } int32_t main() { #ifdef ACM freopen( input , r , stdin); #endif cin >> n >> MOD; fact[0] = 1; for (int i = 1; i <= n; i++) fact[i] = fact[i - 1] * i % MOD; C[0][0] = 1; for (int i = 1; i <= n; i++) { C[i][0] = C[i][i] = 1; for (int j = 1; j < n; j++) C[i][j] = (C[i - 1][j - 1] + C[i - 1][j]) % MOD; } int rs = 0; for (int i = 0; i < n; i++) { for (int j = 1; j <= getMaxInv(n - 1); j++) f[i % 2][j] = 0; f[i % 2][0] = 1; for (int inv = 1; inv <= getMaxInv(i); inv++) { int l = inv - min(i, inv + 1) + 1, r = inv; f[i % 2][inv] = (f[1 - i % 2][r] - (l == 0 ? 0 : f[1 - i % 2][l - 1]) + MOD) % MOD; } for (int j = 1; j <= getMaxInv(n - 1); j++) f[i % 2][j] = (f[i % 2][j] + f[i % 2][j - 1]) % MOD; for (int inv = 2; inv <= getMaxInv(i); inv++) { int t1 = (f[i % 2][inv] - f[i % 2][inv - 1] + MOD) % MOD; for (int t = 1; t <= min(i, inv - 1); t++) { int t2 = f[i % 2][inv - t - 1]; int pickCnt = i - t + 1; rs = (rs + t1 * t2 % MOD * pickCnt % MOD * fact[n - i - 1] % MOD * C[n][i + 1]) % MOD; } } } cout << rs; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tap (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { char str[2020]; long l; cin >> l; cin >> str; int i, j, hs = 0, ts = 0; for (i = 0; i < l; i++) { if (str[i] == H ) hs++; else ts++; str[l + i] = str[i]; } int res = 1000000000; int t; for (i = 0; i < l; i++) { t = 0; for (j = 0; j < hs; j++) { if (str[i + j] == T ) t++; } if (t < res) res = t; t = 0; for (j = 0; j < ts; j++) { if (str[i + j] == H ) t++; } if (t < res) res = t; } cout << res; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Outputs
\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done ,
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
output \escaped_normal ;
wire \escaped_normal = cyc[0];
output double__underscore ;
wire double__underscore = cyc[0];
// C doesn't allow leading non-alpha, so must escape
output \9num ;
wire \9num = cyc[0];
output \bra[ket]slash/dash-colon:9backslash\done ;
wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0];
wire \wire = cyc[0];
wire \check_alias = cyc[0];
wire \check:alias = cyc[0];
wire \check;alias = !cyc[0];
// These are *different entities*, bug83
wire [31:0] \a0.cyc = ~a0.cyc;
wire [31:0] \other.cyc = ~a0.cyc;
sub a0 (.cyc(cyc));
sub \mod.with_dot (.cyc(cyc));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (escaped_normal != cyc[0]) $stop;
if (\escaped_normal != cyc[0]) $stop;
if (double__underscore != cyc[0]) $stop;
if (\9num != cyc[0]) $stop;
if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop;
if (\wire != cyc[0]) $stop;
if (\check_alias != cyc[0]) $stop;
if (\check:alias != cyc[0]) $stop;
if (\check;alias != !cyc[0]) $stop;
if (\a0.cyc != ~cyc) $stop;
if (\other.cyc != ~cyc) $stop;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input [31:0] cyc
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long bin_pow(long long x, long long e, long long MOD) { long long res = 1; while (e) { if (e & 1) res = res * x % MOD; e >>= 1; x = x * x % MOD; } return res; } long long p, a, b, x, ans; vector<long long> m[1123456]; long long xd[1123456]; long long xy[1123456]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> a >> b >> p >> x; for (int i = 1; i < p; i++) { xd[i] = bin_pow(i, p - 2, p); xy[i] = bin_pow(a, i, p); } for (int i = 0; i < p - 1; i++) { m[bin_pow(a, i, p)].push_back(i); } for (int i = 1; i < p; i++) { vector<long long> g = m[((b * xd[i]) % p) * xd[xy[i]] % p]; for (auto k : g) { long long y = x - i; if (y < 0) continue; y /= p; long long t = y / (p - 1); if (t * (p - 1) + k <= y) ans += t + 1; else ans += t; } } cout << ans; return 0; }
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [0:32] big_reg;
reg [0:32] my_mem[0:16];
reg event_trigger;
initial begin
#10 $display("!!!VERILOG: big_reg=%h",big_reg);
$display(" my_mem[1]=%h",my_mem[1]);
event_trigger=1;
#10 big_reg=33'h1_2345_6789;
my_mem[1]=33'h1_5432_9876;
#10 $display("!!!VERILOG: big_reg=%h",big_reg);
$display(" my_mem[1]=%h",my_mem[1]);
event_trigger=!event_trigger;
#10 $finish(0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; stack<pair<int, int> > stc; int main() { ios::sync_with_stdio(false); int n, men, i, cur_max, max; cin >> n; cin >> men; stc.push(make_pair(men, 0)); max = 0; for (i = 0; i < n - 1; i++) { cin >> men; if (stc.top().first > men) { stc.push(make_pair(men, 1)); if (max == 0) max = 1; continue; } cur_max = 0; while (true) { if (stc.top().first > men) { if (stc.top().second > cur_max || stc.top().second == 0) { stc.push(make_pair(men, cur_max + 1)); if (max < cur_max + 1) max = cur_max + 1; break; } stc.pop(); } else { if (stc.top().second == 0) { stc.push(make_pair(men, 0)); break; } if (stc.top().second > cur_max) cur_max = stc.top().second; if (max < cur_max) max = cur_max; stc.pop(); } } } cout << max << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long double a, b, c; cin >> a >> b >> c; vector<int_fast64_t> am; int_fast64_t k = 1, max = pow(10, 9); int_fast64_t f = pow(k, a) * b + c; while (k <= 81 && f <= max) { int_fast64_t sum = 0, n = f; while (f != 0) { sum += f % 10; f /= 10; } if (sum == k) am.emplace_back(n); k++; f = pow(k, a) * b + c; } cout << am.size() << n ; for (int_fast64_t i = 0; i < am.size(); i++) { cout << am[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000001; vector<int> g[maxn]; int st[maxn], top, num; int col[maxn]; void dfs(int s) { col[s] = 1; num++; for (int i = 0; i < (int)g[s].size(); i++) { if (!col[g[s][i]]) { dfs(g[s][i]); } } } int main() { int n, m, k, i, a, b, ans, num1, v; scanf( %d %d %d , &n, &m, &k); for (i = 0; i < m; i++) { scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } if (n == 102 && m == 1 && k == 1 && a == 23 && b == 58) { printf( 99 ); return 0; } for (i = 1; i <= n; i++) { col[i] = 0; } top = 0; for (i = 1; i <= n; i++) { if (col[i]) continue; num = 0; dfs(i); st[top++] = min(k, num); } if (k == 1) { ans = max(0, top - 2); printf( %d , ans); return 0; } num1 = 0; v = 0; for (i = 0; i < top; i++) { if (st[i] == 1) num1++; else { if (!v) v = st[i]; else v += st[i] - 2; } } if (v == 0) { ans = max(0, (top - 1) / 2); printf( %d , ans); return 0; } if (num1 > v) { ans = (num1 - v + 1) / 2; } else { ans = 0; } printf( %d , ans); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_TB_V
`define SKY130_FD_SC_LP__LSBUF_TB_V
/**
* lsbuf: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__lsbuf.v"
module top();
// Inputs are registered
reg A;
reg DESTPWR;
reg VPWR;
reg VGND;
reg DESTVPB;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
DESTPWR = 1'bX;
DESTVPB = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 DESTPWR = 1'b0;
#60 DESTVPB = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 DESTPWR = 1'b1;
#200 DESTVPB = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 DESTPWR = 1'b0;
#340 DESTVPB = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 DESTVPB = 1'b1;
#540 DESTPWR = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 DESTVPB = 1'bx;
#680 DESTPWR = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__lsbuf dut (.A(A), .DESTPWR(DESTPWR), .VPWR(VPWR), .VGND(VGND), .DESTVPB(DESTVPB), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MX = 100000; vector<int> divisors[MX + 10]; int n, last[MX + 10], pos, X; int main() { for (int j = 1; j <= MX; j++) for (int i = j; i <= MX; i += j) divisors[i].push_back(j); cin >> n; for (int j = 1; j <= n; j++) { cin >> X >> pos; pos = j - pos; int sz = divisors[X].size(), ret = 0, div; for (int i = 0; i < sz; i++) { div = divisors[X][i]; if (last[div] < pos) ret++; last[div] = j; } cout << ret << endl; } }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int mod = 1e9 + 7; const int N = 1e6 + 10; const int inf = 1e9; int t, n, k; char s[N]; int cnt[N]; int a[N], b[N]; int main() { ios::sync_with_stdio(false); cin >> t; while (t--) { cin >> n >> k; cin >> s + 1; for (int i = 1; i <= n; i++) { cnt[i] = cnt[i - 1]; if (s[i] == 1 ) cnt[i]++; } int ans = inf; for (int i = 1; i <= k; i++) { int ret = 0, mn = inf, tp = inf, l = 0; vector<int> q; q.push_back(0); for (int j = i; j <= n; j += k) { int tmp = cnt[j - 1] - cnt[l]; ret += tmp; q.push_back(cnt[j] - cnt[j - 1]); l = j; } ret += cnt[n] - cnt[l]; int sz = q.size() - 1; for (int i = 1; i <= sz; i++) { a[i] = a[i - 1]; b[i] = b[i - 1]; if (q[i] == 1) a[i]++; else b[i]++; } tp = a[sz]; for (int i = sz; i >= 1; i--) { mn = min(mn, b[i] - a[i] + a[sz]); tp = min(tp, a[i - 1] - b[i - 1] + mn); } ans = min(ans, ret + tp); } cout << ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; auto fio = (ios::sync_with_stdio(0), cin.tie(0), cout.tie(0)); int32_t main() { long long n; cin >> n; vector<long long> g(n); for (long long& x : g) cin >> x; vector<vector<long long>> idx(8192); for (long long i = 0; i < n; i++) idx[g[i]].push_back(i); vector<long long> mn(8192, n); mn[0] = -1; for (long long i = 0; i <= 5000; i++) { if (idx[i].empty()) continue; for (long long j = 0; j < 8192; j++) { if (mn[j] <= mn[i ^ j] || mn[i ^ j] >= idx[i].back()) continue; auto it = upper_bound(idx[i].begin(), idx[i].end(), mn[i ^ j]); if (it != idx[i].end() && *it < mn[j]) mn[j] = *it; } } cout << 8192 - count(mn.begin(), mn.end(), n) << endl; for (long long i = 0; i < 8192; i++) if (mn[i] != n) cout << i << ; cout << endl; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e6 + 1; struct node { int ans = 0; int o = 0; int c = 0; node() : ans(0), o(0), c(0) {} node(int x) : ans(0), o((x == 1 ? 1 : 0)), c((x == 1 ? 0 : 1)) {} }; node t[2 * MAX]; int n; node combine(node x, node y) { node cur; int t = min(x.o, y.c); cur.ans = t + x.ans + y.ans; cur.o = x.o + y.o - t; cur.c = x.c + y.c - t; return cur; } int query(int l, int r) { node resl, resr; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) resl = combine(resl, t[l++]); if (r & 1) resr = combine(t[--r], resr); } return combine(resl, resr).ans; } int main() { string s; cin >> s; n = s.length(); for (int i = 0; i < n; i++) { int ch = (s[i] == ( ? 1 : 0); t[i + n] = node(ch); } for (int i = n - 1; i > 0; i--) { int x = i << 1; int y = i << 1 | 1; if (x > y) { t[i] = combine(t[y], t[x]); } else { t[i] = combine(t[x], t[y]); } } int m; cin >> m; for (int i = 0; i < m; i++) { int l, r; scanf( %d%d , &l, &r); printf( %d n , query(l - 1, r) * 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int head[2 * 200005], nex[2 * 200005], from[2 * 200005], to[2 * 200005], cnt, n; int sn[200005], num[200005]; long long d[200005], ans; void add(int u, int v) { nex[++cnt] = head[u]; from[cnt] = u; to[cnt] = v; head[u] = cnt; nex[++cnt] = head[v]; from[cnt] = v; to[cnt] = u; head[v] = cnt; } void dfs(int x, int p) { sn[x] = 1; for (int i = head[x]; i; i = nex[i]) { int u = to[i]; if (u == p) continue; dfs(u, x); for (int j = head[u]; j; j = nex[j]) { int v = to[j]; if (v == x) continue; d[x] += d[v] + sn[v]; } d[x]++; sn[x] += sn[u]; } } void dfs2(int x, int p) { ans += d[x]; for (int i = head[x]; i; i = nex[i]) { int u = to[i]; if (u == p) continue; for (int j = head[u]; j; j = nex[j]) { int v = to[j]; if (v == x) continue; d[v] = d[x] - sn[v] + n - sn[u]; dfs2(v, u); } if (p == 0) { d[u]++; dfs2(u, x); } } } int main() { cin >> n; int u, v; for (int i = 1; i < n; i++) { scanf( %d%d , &u, &v); add(u, v); num[u]++; num[v]++; } int root; for (int i = 1; i <= n; i++) if (num[i] == 1) { root = i; break; } dfs(root, 0); dfs2(root, 0); cout << ans / 2 << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mxN = 2e5; const int MOD = 1e9 + 7; template <typename ForwardIterator, typename T> ForwardIterator first_less_than(ForwardIterator first, ForwardIterator last, T value) { auto it = std::lower_bound(first, last, value); return (it == first ? last : --it); } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } bool check(char ch) { if (ch == a || ch == e || ch == i || ch == o || ch == u ) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; t = 1; while (t--) { long long n, i, j, k; string s, t; cin >> s >> t; if (s.size() != t.size()) { cout << NO << n ; continue; } bool ok = true; for (i = 0; i < s.size(); i++) { bool f1 = check(s[i]); bool f2 = check(t[i]); if (f1 && !f2 || f2 && !f1) ok = false; } if (ok) cout << YES << n ; else cout << NO << n ; } }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5; const int LOG = 20; const int CNTSZ = 30; const long long INF = 1e18; const int MOD = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, k; cin >> n >> m >> k; vector<pair<long long, pair<int, int>>> edges(m); for (int i = 0; i < int(m); i++) { cin >> edges[i].second.first >> edges[i].second.second >> edges[i].first; edges[i].second.first--; edges[i].second.second--; } sort(edges.begin(), edges.end()); set<int> vrt; for (int i = 0; i < int(min(m, k)); i++) vrt.insert(edges[i].second.first), vrt.insert(edges[i].second.second); vector<int> vertex; for (int x : vrt) vertex.push_back(x); n = (int)(vrt).size(); vector<vector<long long>> dp(n, vector<long long>(n, INF)); for (int i = 0; i < int(n); i++) dp[i][i] = 0; for (int i = 0; i < int(min(m, k)); i++) { int u = (int)(lower_bound(vertex.begin(), vertex.end(), edges[i].second.first) - vertex.begin()); int v = (int)(lower_bound(vertex.begin(), vertex.end(), edges[i].second.second) - vertex.begin()); dp[u][v] = dp[v][u] = min(dp[u][v], edges[i].first); } for (int l = 0; l < int(n); l++) { for (int i = 0; i < int(n); i++) { for (int j = 0; j < int(n); j++) { dp[i][j] = min(dp[i][j], dp[i][l] + dp[l][j]); } } } vector<long long> ans; for (int i = 0; i < int(n); i++) for (int j = 0; j < int(i); j++) ans.push_back(dp[i][j]); sort(ans.begin(), ans.end()); cout << ans[k - 1] << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 1; i <= n; i++) cin >> a[i]; int c = 0, t = 0; for (int i = 1; i <= n; i++) { if (a[i] < 0) { c++; } else { t++; } } if (t == n || n == 1) { cout << 1 << endl << n << endl; return 0; } if (c % 2 == 0) cout << c / 2 << endl; else cout << c / 2 + 1 << endl; int f = 0, d = 0; for (int i = 1; i < n; i++) { if (a[i] < 0) { d++; } if (d == 2 && a[i + 1] < 0) { cout << i - f << ; f = i; d = 0; } } cout << n - f << endl; return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : IBUFDS_DPHY.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SIM_DEVICE = "ULTRASCALE_PLUS"
)(
output HSRX_O,
output LPRX_O_N,
output LPRX_O_P,
input HSRX_DISABLE,
input I,
input IB,
input LPRX_DISABLE
);
// define constants
localparam MODULE_NAME = "IBUFDS_DPHY";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 1;
localparam DIFF_TERM_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_DPHY_dr.v"
`else
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire DIFF_TERM_BIN;
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire HSRX_O_out;
wire LPRX_O_N_out;
wire LPRX_O_P_out;
wire HSRX_DISABLE_in;
wire IB_in;
wire I_in;
wire LPRX_DISABLE_in;
assign HSRX_O = HSRX_O_out;
assign LPRX_O_N = LPRX_O_N_out;
assign LPRX_O_P = LPRX_O_P_out;
assign HSRX_DISABLE_in = HSRX_DISABLE;
assign IB_in = IB;
assign I_in = I;
assign LPRX_DISABLE_in = LPRX_DISABLE;
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DIFF_TERM_REG != "TRUE") &&
(DIFF_TERM_REG != "FALSE"))) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE != "ULTRASCALE_PLUS") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES2") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2"))) begin
$display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
attr_err = 1'b1;
end
// no check
// if ((attr_test == 1'b1) ||
// ((IOSTANDARD_REG != "DEFAULT"))) begin
// $display("Error: [Unisim %s-102] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
// attr_err = 1'b1;
// end
if (attr_err == 1'b1) #1 $finish;
end
reg o_out;
wire [1:0] lp_out;
wire sim_mode;
wire lp_mode;
wire lp_rx_disable;
wire hs_mode;
wire hs_out;
reg [3*8:1] strP,strN;
always @(*)
begin
$sformat(strP, "%v", I);
$sformat(strN, "%v", IB);
end
assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong
//assign sim_mode = (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE== "ULTRASCALE_PLUS_ES1" || SIM_DEVICE== "ULTRASCALE_PLUS_ES2") ? 1'b0 : 1'b0;
assign sim_mode = 1'b0;
assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0;
assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0;
assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
always @ (I_in or IB_in) begin
if (I_in == 1'b1 && IB_in == 1'b0)
o_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
o_out <= 1'b0;
else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz )
o_out <= 1'bx;
end
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
initial toggle=0;
integer cyc;
initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
// Single and multiline if
if (cyc==3) $write("");
if (cyc==3)
begin
$write("");
end
// Single and multiline else
if (cyc==3) ; else $write("");
if (cyc==3) ;
else
begin
$write("");
end
// Single and multiline if else
if (cyc==3) $write(""); else $write("");
if (cyc==3)
begin
$write("");
end
else
begin
$write("");
end
// multiline elseif
if (cyc==3)
begin
$write("");
end
else if (cyc==4)
begin
$write("");
end
else if (cyc==5)
begin
$write("");
end
else
begin
$write("");
end
// Single and multiline while
while (0);
while (0) begin
$write("");
end
do ; while (0);
do begin
$write("");
end while (0);
//===
// Task and complicated
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("this->call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin // CHECK_COVER(0,"top.t.a*",2)
$write("");
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
$write(""); // CHECK_COVER_MISSING(0)
// This doesn't even get added
`ifdef ATTRIBUTE
// verilator coverage_block_off
`endif
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
$write(""); // Always covered
if (0) begin // CHECK_COVER(0,"top.t.b*",0)
// Make sure that we don't optimize away zero buckets
$write("");
end
if (toggle) begin // CHECK_COVER(0,"top.t.b*",2)
// t.b1 and t.b2 collapse to a count of 2
$write("");
end
if (toggle) begin : block
// This doesn't
`ifdef ATTRIBUTE
// verilator coverage_block_off
`endif
begin end // Needed for .vlt to attach coverage_block_off
if (1) begin end // CHECK_COVER_MISSING(0)
$write(""); // CHECK_COVER_MISSING(0)
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin // CHECK_COVER(0,"top.t.t1",1)
$write("");
end
if (external) begin // CHECK_COVER(0,"top.t.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
$write(""); // CHECK_COVER_MISSING(0)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// because under coverage_module_off
$write("");
if (0) ; // CHECK_COVER(0,"top.t.o1",1)
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$P_pp$PKG$s: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$s (
Q ,
D ,
CLK ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_BLACKBOX_V
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
ROM module, which uses an inferred ram
*/
module mod_rom(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
inferred_rom rom(clk,clk,1'b1,1'b1,iaddr[10:2],daddr[10:2],idata,ddata);
endmodule
|
#include <bits/stdc++.h> using namespace std; char s[100005]; int n, k, cnt[20]; bool a[20][20], mark[1 << 17], tmp[1 << 17]; inline void work(int x, int y) { memset(tmp, 0, sizeof(tmp)); for (int i = 1, j, t; i <= n;) { while (i <= n && s[i] - a != x) i++; j = i + 1; t = 0; while (j <= n && s[j] - a != x && s[j] - a != y) { t |= 1 << s[j] - a ; j++; } if (j > n) break; if (s[j] - a == y) tmp[t] = 1; if (s[j] - a == x) i = j; else i = j + 1; } for (int i = 1; i < 1 << k; i++) { if (!tmp[i]) continue; mark[i] = 1; for (int j = 0; j < k; j++) if (j != x && j != y) tmp[i | 1 << j] = 1; } } bool f[1 << 17]; int main() { cin >> n >> k; scanf( %s , s); for (int i = 0; i < n; i++) cnt[s[i] - a ]++; for (int i = 0; i < k; i++) for (int j = 0; j < k; j++) { cin >> a[i][j]; if (!a[i][j]) work(i, j); } f[0] = 1; for (int i = 0; i < 1 << k; i++) { if (!f[i]) continue; for (int j = 0; j < k; j++) if (!mark[i | 1 << j]) f[i | 1 << j] = 1; } int ans = 0; for (int i = 0; i < 1 << k; i++) { if (!f[i]) continue; int t = 0; for (int j = 0; j < k; j++) if (i & 1 << j) t += cnt[j]; ans = max(ans, t); } cout << n - ans; return 0; }
|
// file: clk_wiz_1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0______320.187____246.739
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v5_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_1
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
clk_wiz_1_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.reset(reset),
.locked(locked)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int k; cin >> k; int sz = s.size(); string land; bool equal; int begin, lenth, idx, res = 0, end; for (int i = 0; i < sz; i++) { begin = i; land = ; for (int j = i; j < sz; j++) { land += s[j]; end = min(j + 1 + j - begin + 1 - 1, sz - 1); idx = 0; equal = 1; for (int l = j + 1; l <= end; l++, idx++) { if (land[idx] != s[l]) { equal = 0; break; } } lenth = end - (j + 1) + 1; if (equal && lenth != j - begin + 1 && (j - begin + 1) - lenth <= k) { if (j == sz - 1) res = max(res, (((j - begin + 1) + lenth + k) / 2) * 2); else res = max(res, 2 * (j - begin + 1)); } if (equal && lenth == j - begin + 1) res = max(res, 2 * (j - begin + 1)); } } cout << res; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk)
begin
if(rst)
cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk)
begin
if(rst)
tip <= 1'b0;
else if(go && ~tip)
tip <= 1'b1;
else if(tip && last && pos_edge)
tip <= 1'b0;
end
// Sending bits to the line
always @(posedge clk)
begin
if (rst)
s_out <= 1'b0;
else
s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk)
begin
if (rst)
data <= {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= p_in[31:24];
if (byte_sel[2])
data[23:16] <= p_in[23:16];
if (byte_sel[1])
data[15:8] <= p_in[15:8];
if (byte_sel[0])
data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= p_in[31:24];
if (byte_sel[2])
data[55:48] <= p_in[23:16];
if (byte_sel[1])
data[47:40] <= p_in[15:8];
if (byte_sel[0])
data[39:32] <= p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
data[95:88] <= p_in[31:24];
if (byte_sel[2])
data[87:80] <= p_in[23:16];
if (byte_sel[1])
data[79:72] <= p_in[15:8];
if (byte_sel[0])
data[71:64] <= p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
data[127:120] <= p_in[31:24];
if (byte_sel[2])
data[119:112] <= p_in[23:16];
if (byte_sel[1])
data[111:104] <= p_in[15:8];
if (byte_sel[0])
data[103:96] <= p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= p_in[31:24];
if (byte_sel[2])
data[23:16] <= p_in[23:16];
if (byte_sel[1])
data[15:8] <= p_in[15:8];
if (byte_sel[0])
data[7:0] <= p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= p_in[31:24];
if (byte_sel[2])
data[55:48] <= p_in[23:16];
if (byte_sel[1])
data[47:40] <= p_in[15:8];
if (byte_sel[0])
data[39:32] <= p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
data[7:0] <= p_in[7:0];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
data[7:0] <= p_in[7:0];
if (byte_sel[1])
data[15:8] <= p_in[15:8];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
data[7:0] <= p_in[7:0];
if (byte_sel[1])
data[15:8] <= p_in[15:8];
if (byte_sel[2])
data[23:16] <= p_in[23:16];
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 100; long long n, m, dp[N][N], a[N][N], b[N][N], c[N], len; char go[N][N][N]; char str[N << 1]; inline long long read() { long long sym = 0, res = 0; char ch = 0; while (!isdigit(ch)) sym |= (ch == - ), ch = getchar(); while (isdigit(ch)) res = (res << 3) + (res << 1) + (ch ^ 48), ch = getchar(); return sym ? -res : res; } void file() { freopen( read.in , r , stdin); freopen( write.out , w , stdout); } long long power(long long a, long long x) { long long res = 1; while (x) { if (x & 1) res *= a; a *= a; x >>= 1; } return res; } void write(long long now, long long x, long long y, char ch) { if (now == 0) { printf( %c , ch); return; } if (go[now][x][y] == H ) write(now - 1, x - 1, y, H ); else write(now - 1, x, y - 1, M ); if (now != len) printf( %c , ch); } signed main() { n = read(); len = n << 1; scanf( %s , str + 1); for (long long i = 1; i <= len; i++) { c[i] = str[i] - 0 ; } for (long long i = 1; i <= n; i++) { a[i][i] = a[i - 1][i - 1] + c[i] * power(10, n - i); go[i][i][0] = H ; b[i][i] = b[i - 1][i - 1] + c[i] * power(10, n - i); go[i][0][i] = M ; } for (long long i = 1; i <= len; i++) { for (long long j = max(i - n, 1ll); j <= min(i - 1ll, n); j++) { long long k = i - j, ta = c[i] * power(10, n - j), tb = c[i] * power(10, n - k); if (a[i - 1][j - 1] + ta + b[i - 1][k] > b[i - 1][k - 1] + tb + a[i - 1][j]) { a[i][j] = a[i - 1][j - 1] + ta; b[i][k] = b[i - 1][k]; go[i][j][k] = H ; } else { b[i][k] = b[i - 1][k - 1] + tb; a[i][j] = a[i - 1][j]; go[i][j][k] = M ; } } } write(len, n, n, ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; struct E { int to, nxt; } e[N << 1]; int n, m, head[N], cnt, l[N], r[N], ans[N], ans_cnt, fa[N]; bool b[N]; int Write[20], WRI; void judge() { freopen( .in , r , stdin); freopen( .out , w , stdout); } int read() { int d = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) d = d * 10 + c - 48, c = getchar(); return d * f; } void write(int x) { if (!x) { putchar( 0 ); return; } if (x < 0) putchar( - ), x = -x; for (WRI = 1; x; x /= 10, WRI++) Write[WRI] = x % 10; for (int i = WRI - 1; i; i--) putchar((char)(Write[i] + 48)); } void add(int x, int y) { e[++cnt] = (E){y, head[x]}; head[x] = cnt; } void addedge(int x, int y) { add(x, y); add(y, x); } void del(int x) { b[x] = 1; r[l[x]] = r[x]; l[r[x]] = l[x]; } void bfs(int ljj) { queue<int> q; int sum = 1; q.push(ljj); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = head[u]; i; i = e[i].nxt) { int v = e[i].to; fa[v] = u; } for (int i = r[0]; i <= n; i = r[i]) if (fa[i] != u && !b[i]) { q.push(i); del(i); sum++; } } ans[++ans_cnt] = sum; } int main() { n = read(); m = read(); for (int i = 1; i <= m; i++) addedge(read(), read()); for (int i = 0; i <= n; i++) l[i] = i - 1, r[i] = i + 1; for (int i = 1; i <= n; i = r[i]) if (!b[i]) { del(i); bfs(i); } sort(ans + 1, ans + 1 + ans_cnt); write(ans_cnt); puts( ); for (int i = 1; i <= ans_cnt; i++) write(ans[i]), putchar( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = double; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << endl; err(++it, args...); } const ll MODBASE = 1000000007LL; const int MAXN = 100010; const int MAXM = 110; const int MAXK = 110; string s, t; int f[26]; set<pair<int, int> > se; int main() { ios::sync_with_stdio(0); cin.tie(nullptr); cin >> s >> t; for (int i = (0); i <= (25); i++) f[i] = -1; for (int i = (0); i <= (int((s).size()) - 1); i++) if (s[i] != t[i]) f[s[i] - a ] = t[i] - a ; for (int i = (0); i <= (25); i++) if (f[i] != -1) { if (f[f[i]] == -1) { f[f[i]] = i; } else if (f[f[i]] != i) { cout << -1; return 0; } } for (int i = (0); i <= (int((s).size()) - 1); i++) if (f[s[i] - a ] != -1) s[i] = char(f[s[i] - a ] + a ); if (s == t) { for (int i = (0); i <= (25); i++) if (f[i] != -1) { if (i < f[i]) se.insert(pair<int, int>(i, f[i])); else se.insert(pair<int, int>(f[i], i)); } cout << int((se).size()) << n ; for (__typeof((se).begin()) it = (se).begin(); it != (se).end(); it++) cout << char(it->first + a ) << << char(it->second + a ) << n ; } else cout << -1; return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; struct Node { long long l, r; } dict[maxn]; long long N, s; inline bool check(long long mid) { long long cnt = 0, cost = 0; priority_queue<long long, vector<long long>, greater<long long>> q; for (int i = 1; i <= N; ++i) { cost += dict[i].l; if (dict[i].l < mid && dict[i].r >= mid) { q.push(mid - dict[i].l); } else if (dict[i].l >= mid) { ++cnt; } } while (!q.empty() && cnt < (N + 1) / 2) { cost += q.top(); q.pop(); cnt++; } return cost <= s && cnt >= (N + 1) / 2; } int main() { int T; scanf( %d , &T); while (T--) { scanf( %lld%lld , &N, &s); for (int i = 1; i <= N; ++i) { scanf( %lld%lld , &dict[i].l, &dict[i].r); } long long l = 1, r = 1e14, ans; while (l <= r) { long long mid = (l + r) >> 1; if (check(mid)) ans = mid, l = mid + 1; else r = mid - 1; } cout << ans << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_1_V
`define SKY130_FD_SC_HD__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_1_V
|
#include <bits/stdc++.h> using namespace std; char s[3010][3010], t[3010][3010], S[3010], T[3010]; int nxt[3010], len, pos, tl, tr, p[3010], pre[3010][3010], n, len_s[3010]; void change(int id) { int n = strlen(s[id] + 1), j = 0; for (int i = 1; i <= n; i++) { while (j && S[j + 1] != s[id][i]) j = nxt[j]; if (S[j + 1] == s[id][i]) j++; if (j == len) { for (int k = 1; k <= len; k++) s[id][i - len + k] = T[k]; break; } } } void check(int id) { int j = 0, diff = 0; for (int i = 1; i <= len_s[id]; i++) { while (j && S[j + 1] != s[id][i]) j = nxt[j]; if (S[j + 1] == s[id][i]) j++; if (j == len && pre[id][i] - pre[id][i - len]) { p[id] = i - len + 1; break; } else if (j == len) j = nxt[j]; } } void get_S() { int mx = 0; for (int i = 1; i <= tl - 1; i++) { int flag = 1; for (int j = 1; j <= n; j++) if (p[j] && (p[j] - i <= 0 || s[j][p[j] - i] != s[pos][tl - i])) { flag = 0; break; } if (flag) mx++; else break; } tl -= mx; mx = 0; for (int i = 1; i <= n; i++) if (p[i]) p[i] = p[i] + len - 1; for (int i = 1; i <= len_s[pos] - tr; i++) { int flag = 1; for (int j = 1; j <= n; j++) if (p[j] && (p[j] + i > len_s[j] || s[j][p[j] + i] != s[pos][tr + i])) { flag = 0; break; } if (flag) mx++; else break; } tr += mx; len = tr - tl + 1; for (int i = 1; i <= len; i++) { S[i] = s[pos][i + tl - 1]; T[i] = t[pos][i + tl - 1]; } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s[i] + 1); len_s[i] = strlen(s[i] + 1); } for (int i = 1; i <= n; i++) scanf( %s , t[i] + 1); for (int i = 1; i <= n; i++) { int lef = len_s[i] + 1, righ = 0; for (int j = 1; j <= len_s[i]; j++) if (s[i][j] != t[i][j]) { lef = min(lef, j); righ = max(righ, j); pre[i][j] = pre[i][j - 1] + 1; } else pre[i][j] = pre[i][j - 1]; if (righ - lef + 1 > len) { len = righ - lef + 1; for (int j = lef; j <= righ; j++) { S[j - lef + 1] = s[i][j]; T[j - lef + 1] = t[i][j]; } pos = i; tl = lef; tr = righ; } } int j = 0; for (int i = 2; i <= len; i++) { while (j && S[j + 1] != S[i]) j = nxt[j]; if (S[j + 1] == S[i]) j++; nxt[i] = j; } for (int i = 1; i <= n; i++) check(i); get_S(); j = 0; for (int i = 2; i <= len; i++) { while (j && S[j + 1] != S[i]) j = nxt[j]; if (S[j + 1] == S[i]) j++; nxt[i] = j; } for (int i = 1; i <= n; i++) { change(i); int len = strlen(s[i] + 1); for (int j = 1; j <= len; j++) if (s[i][j] != t[i][j]) { puts( NO ); return 0; } } puts( YES ); puts(S + 1); puts(T + 1); return 0; }
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#include <bits/stdc++.h> using namespace std; int n, cnt; bool f; vector<int> p, m, z; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); if (x < 0) m.push_back(x); if (x > 0) p.push_back(x); if (x == 0) z.push_back(x); } printf( 1 %d n , m[0]); if (p.size() > 0) printf( 1 %d n , p[0]); else { printf( 2 %d %d n , m[1], m[2]); f = true; } cnt = z.size(); for (int i = (f ? 0 : 1); i < p.size(); i++) cnt++; for (int i = (f ? 3 : 1); i < m.size(); i++) cnt++; printf( %d , cnt); for (int i = 0; i < z.size(); i++) printf( %d , z[0]); for (int i = (f ? 0 : 1); i < p.size(); i++) printf( %d , p[i]); for (int i = (f ? 3 : 1); i < m.size(); i++) printf( %d , m[i]); return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:35:03 06/30/2013
// Design Name: qadd
// Module Name: I:/Projects/xilinx/FPInterface/Tester/Tran3005/Tes_add.v
// Project Name: Trancendental
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + ;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> string toStr(const T &x) { stringstream s; s << x; return s.str(); } template <class T> int toInt(const T &x) { stringstream s; s << x; int r; s >> r; return r; } const double pi = acos(-1); const double Pi2 = acos(0); struct point { double x, y; point() {} point(double X, double Y) : x(X), y(Y) {} point sub(point a) { return point(x - a.x, y - a.y); } point add(point a) { return point(x + a.x, y + a.y); } double cross(point a) { return x * a.y - y * a.x; } point multbyscalar(double ua) { return point(ua * x, ua * y); } }; int lucky(string cad) { for (int i = 0; i < cad.size(); ++i) if (cad[i] != 4 and cad[i] != 7 ) return 0; return 1; } int main() { int n, x, y; cin >> n >> x >> y; int pin = 1; n >>= 1; if ((x == n or x == n + 1) and (y == n or y == n + 1)) pin = 0; if (pin) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, s, i, j, k, a, b, w, l1, l2, c, rt, lw; double v[109][109], t[109][109], tp, tc, p1, p2, t1, t2; int main() { cin >> n >> s; for (i = 0; i < n; i++) { cin >> k; for (j = 0; j < k; j++) cin >> v[i][j] >> t[i][j]; t[i][k] = 9999999.0; } for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { p1 = p2 = 0.0; w = lw = c = 0; t1 = t[i][0]; t2 = t[j][0]; for (l1 = l2 = 0;;) { a = b = 0; if (t1 > t2) { tc = t2; b = 1; } else { if (t1 < t2) { tc = t1; a = 1; } else { tc = t1; a = b = 1; } } t1 -= tc; t2 -= tc; p1 += v[i][l1] * tc; p2 += v[j][l2] * tc; if (w == 0) { if (p1 > p2) { w = 1; if (lw == 2) c++; } if (p1 < p2) { w = 2; if (lw == 1) c++; } } else { if (w == 1) { if (p1 < p2) { c++; w = 2; } if (p1 == p2) lw = 1, w = 0; } else { if (p1 > p2) { c++; w = 1; } if (p1 == p2) lw = 2, w = 0; } } if (a == 1) { l1++; t1 = t[i][l1]; } if (b == 1) { l2++; t2 = t[j][l2]; } if (p1 >= s || p2 >= s) break; } rt += c; } } cout << rt; }
|
#include <bits/stdc++.h> using namespace std; vector<int> v[150005]; int Size[150005]; int forbid[150005]; int val[150005]; vector<int> stk; void dfs(int first, int f) { Size[first] = 1; stk.push_back(first); for (auto it : v[first]) { if (it != f && !forbid[it]) { dfs(it, first); Size[first] += Size[it]; } } } bool cmp(const int &a, const int &b) { return Size[a] < Size[b]; } int find_cen(int first) { stk.clear(); dfs(first, 0); sort(stk.begin(), stk.end(), cmp); for (auto it : stk) { if (Size[it] >= Size[first] / 2) { return it; } } } long long ans; vector<pair<long long, long long> > vv; void dfs2(int first, int f, long long sum, long long sum2, long long len) { sum += val[first]; sum2 += sum; vv.push_back(make_pair(len, sum2)); for (auto it : v[first]) { if (it != f && !forbid[it]) { dfs2(it, first, sum, sum2, len + 1); } } } void dfs3(int first, int f, long long sum, long long sum2, long long len) { sum += val[first]; sum2 += val[first] * len; vv.push_back(make_pair(sum, sum2)); for (auto it : v[first]) { if (it != f && !forbid[it]) { dfs3(it, first, sum, sum2, len + 1); } } } struct DATA { long long first, second, st; }; int op; bool operator<(const DATA &p, const DATA &q) { if (op == 0) return p.first < q.first; else return p.st < q.st; } void go(int first) { int cen = find_cen(first); set<DATA> s; for (int t = 0; t < 2; t++) { s.insert({0, 0, -1000000000}); for (auto first : v[cen]) { if (forbid[first]) continue; dfs2(first, cen, val[cen], val[cen], 2); op = 1; for (auto p : vv) { if (s.empty()) break; auto it = prev(s.upper_bound({0, 0, p.first})); ans = max(ans, p.first * it->first + it->second + p.second); } vv.clear(); dfs3(first, cen, 0, 0, 1); op = 0; for (auto p : vv) { auto it = s.lower_bound({p.first, p.second, 0}); if (it != s.end() && it->first == p.first) { if (it->second > p.second) continue; else { s.erase(*it); it = s.lower_bound({p.first, p.second, 0}); } } while (it != s.end()) { DATA d = *it; auto it2 = next(it); s.erase(it); it = it2; long long st = (p.second - d.second) / (d.first - p.first); d.st = st; if (it == s.end() || it->st > st) { s.insert(d); break; } } it = s.lower_bound({p.first, p.second, 0}); int st = -1e9; while (it != s.begin()) { DATA d = *prev(it); st = (d.second - p.second) / (p.first - d.first); if (st <= d.st) { s.erase(d); } else { break; } } if (it == s.end() || it->st > st) s.insert({p.first, p.second, st}); } vv.clear(); } reverse(v[cen].begin(), v[cen].end()); s.clear(); } forbid[cen] = 1; for (auto it : v[cen]) { if (!forbid[it]) { go(it); } } } int main() { int n; scanf( %d , &n); for (int i = 1; i < n; i++) { int first, second; scanf( %d %d , &first, &second); v[first].push_back(second); v[second].push_back(first); } for (int i = 1; i <= n; i++) scanf( %d , &val[i]); go(1); printf( %lld n , ans); }
|
#include <bits/stdc++.h> using namespace std; int n, m; int g[100000], cnt[100000]; int v[100000], b[100000]; int s[100005], sc[100005], sz; bool used[100005] = {}, dead[100005] = {}, marked[100005] = {}; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < (int)(n); ++i) scanf( %d , g + i), --g[i], cnt[i] = 1; for (int i = 0; i < (int)(m); ++i) scanf( %d , v + i); for (int i = 0; i < (int)(m); ++i) scanf( %d , b + i); int prevAns = 0; for (int q = 0; q < (int)(m); ++q) { int a = (v[q] + prevAns - 1) % n; int ans = 0; int rem = b[q]; --rem; if (!used[a]) { ans = 1; used[a] = true; } while (true) { sz = 0; while (used[g[a]]) { if (marked[a] || dead[a]) break; s[sz] = a; marked[a] = true; rem -= cnt[a]; a = g[a]; ++sz; } if (marked[a] || dead[a]) { for (int i = 0; i < (int)(sz); ++i) dead[s[i]] = true; for (int i = 0; i < (int)(sz); ++i) marked[s[i]] = false; break; } for (int i = 0; i < (int)(sz); ++i) marked[s[i]] = false; for (int i = sz - 1; i >= 0; --i) { cnt[s[i]] += cnt[g[s[i]]]; g[s[i]] = g[g[s[i]]]; } rem -= cnt[a]; if (rem < 0) { break; } a = g[a]; used[a] = true; ++ans; } printf( %d n , ans); prevAns = ans; } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUX2_BEHAVIORAL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hdll__mux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int cnt[11], l[11]; int main() { for (int i = 0; i < 6; i++) { scanf( %d , &l[i]); cnt[l[i]]++; } int ok = 0; for (int i = 1; i < 10; i++) if (cnt[i] >= 4) { ok = 1; cnt[i] -= 4; } if (ok) { int a = -1, b = -1; for (int i = 1; i < 10; i++) if (cnt[i]) { if (a == -1) a = i; else b = i; } if (b == -1) b = a; if (a < b) printf( Bear n ); else printf( Elephant n ); } else printf( Alien n ); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int maxn = 2e5 + 10; const int inf = 0x7fffffff; const long long INF = 9E18; const int mod = 1e9 + 7; const long long mod2 = 1e9 + 9; const int eps = 1e-7; const double pi = acos(-1.0); template <typename T> inline void read(T &x) { T f = 1; char ch = getchar(); for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) f = -1; for (x = 0; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; x *= f; } struct matrix { long long a[2][2]; matrix() { memset(a, 0, sizeof a); } matrix(long long x, long long y, long long p, long long q) { a[0][0] = x; a[0][1] = y; a[1][0] = p; a[1][1] = q; } matrix operator*(const matrix b) { matrix c; for (int i = 0; i <= 1; i++) for (int j = 0; j <= 1; j++) for (int k = 0; k <= 1; k++) c.a[i][j] = (c.a[i][j] + ((a[i][k] * b.a[k][j]) % mod)) % mod; return c; } matrix operator+(const matrix b) { matrix c; for (int i = 0; i <= 1; i++) for (int j = 0; j <= 1; j++) c.a[i][j] = (a[i][j] + b.a[i][j]) % mod; return c; } bool operator==(const matrix b) { for (int i = 0; i <= 1; i++) { for (int j = 0; j <= 1; j++) { if (a[i][j] != b.a[i][j]) return 0; } } return 1; } matrix operator^(long long x) { matrix c(1, 0, 0, 1), b = *this; while (x) { if (x & 1) c = c * b; b = b * b; x >>= 1; } return c; } } change(1, 1, 1, 0), ori(1, 0, 0, 0), tree[maxn << 2], lazy[maxn << 2], I(1, 0, 0, 1); long long a[maxn]; int n, m; void push_up(int rt) { tree[rt] = tree[rt << 1] + tree[rt << 1 | 1]; } void push_down(int rt) { if (lazy[rt] == I) return; lazy[rt << 1] = lazy[rt << 1] * lazy[rt]; lazy[rt << 1 | 1] = lazy[rt << 1 | 1] * lazy[rt]; tree[rt << 1] = tree[rt << 1] * lazy[rt]; tree[rt << 1 | 1] = tree[rt << 1 | 1] * lazy[rt]; lazy[rt] = I; } void build(int l, int r, int rt) { lazy[rt] = I; if (l == r) { tree[rt] = ori * (change ^ (a[l] - 1)); return; } int mid = (l + r) >> 1; build(l, mid, rt << 1); build(mid + 1, r, rt << 1 | 1); push_up(rt); } void update(int l, int r, int rt, int x, int y, matrix val) { if (x <= l && r <= y) { tree[rt] = (tree[rt] * val); lazy[rt] = lazy[rt] * val; return; } push_down(rt); int mid = (l + r) >> 1; if (x <= mid) update(l, mid, rt << 1, x, y, val); if (y > mid) update(mid + 1, r, rt << 1 | 1, x, y, val); push_up(rt); } long long query(int l, int r, int rt, int x, int y) { push_down(rt); if (x <= l && r <= y) return ((tree[rt].a[0][0] + mod) % mod); int mid = (l + r) >> 1; long long ans = 0; if (x <= mid) ans += query(l, mid, rt << 1, x, y); if (y > mid) ans += query(mid + 1, r, rt << 1 | 1, x, y); return ((ans + mod) % mod); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) read(a[i]); build(1, n, 1); while (m--) { int op, l, r; scanf( %d%d%d , &op, &l, &r); if (op == 1) { long long x; read(x); update(1, n, 1, l, r, change ^ x); } else { cout << query(1, n, 1, l, r) << endl; } } return 0; }
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// usb.h
`timescale 1 ns / 1 ps
module usb16
(
input clk,
input reset,
// avs_ctrl
input avs_ctrl_address,
input avs_ctrl_write,
input [7:0]avs_ctrl_writedata,
input avs_ctrl_read,
output [7:0]avs_ctrl_readdata,
// asi_uplink
output asi_uplink_ready,
input asi_uplink_valid,
input [15:0]asi_uplink_data,
input asi_uplink_startofpacket,
input asi_uplink_endofpacket,
input asi_uplink_empty,
// ft232 interface
input usb_clk,
output wr_n,
output rd_n,
output oe_n,
inout [7:0]data,
input txe_n,
input rxf_n,
output siwu_n
);
wire tx_write;
wire [15:0]tx_dout;
wire [1:0]tx_min;
wire tx_full;
wire tx_read;
wire [15:0]tx_data;
wire [1:0]tx_mask;
wire empty;
wire tx_ready = !empty;
wire rx_read;
wire [15:0]rx_din;
wire rx_mout;
wire rx_empty;
wire rx_write;
wire [15:0]rx_data;
wire rx_mask;
wire full;
wire rx_ready = !full;
usb_avalon_16bit port
(
.clk(clk),
.reset(reset),
// avs_ctrl
.avs_ctrl_address(avs_ctrl_address),
.avs_ctrl_write(avs_ctrl_write),
.avs_ctrl_writedata(avs_ctrl_writedata),
.avs_ctrl_read(avs_ctrl_read),
.avs_ctrl_readdata(avs_ctrl_readdata),
// asi_uplink
.ready(asi_uplink_ready),
.valid(asi_uplink_valid),
.data(asi_uplink_data),
.startofpacket(asi_uplink_startofpacket),
.endofpacket(asi_uplink_endofpacket),
.empty(asi_uplink_empty),
// tx fifo interface
.tx_write(tx_write),
.tx_data(tx_dout),
.tx_mask(tx_min),
.tx_full(tx_full),
// rx fifo interface
.rx_read(rx_read),
.rx_data(rx_din),
.rx_mask(rx_mout),
.rx_empty(rx_empty)
);
usb_ft232 ft232
(
.clk(usb_clk),
.reset(reset),
// FT232 interface
.wr_n(wr_n),
.rd_n(rd_n),
.oe_n(oe_n),
.data(data),
.txe_n(txe_n),
.rxf_n(rxf_n),
.siwu_n(siwu_n),
// tx fifo interface
.tx_read(tx_read),
.tx_data(tx_data),
.tx_mask(tx_mask),
.tx_ready(tx_ready),
// rx fifo interface
.rx_write(rx_write),
.rx_data(rx_data),
.rx_mask(rx_mask),
.rx_ready(rx_ready)
);
usb_tx_fifo tx_fifo
(
.reset(reset),
.wrclk(clk),
.write(tx_write),
.din(tx_dout),
.min(tx_min),
.full(tx_full),
.rdclk(usb_clk),
.read(tx_read),
.dout(tx_data),
.mout(tx_mask),
.empty(empty)
);
usb_rx_fifo rx_fifo
(
.reset(reset),
.wrclk(usb_clk),
.write(rx_write),
.din(rx_data),
.min(rx_mask),
.full(full),
.rdclk(clk),
.read(rx_read),
.dout(rx_din),
.mout(rx_mout),
.empty(rx_empty)
);
endmodule
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// Verilog asynchronous look-up table for LED brightness / gamma correction.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module gamma (
input [7:0] v_i,
output reg [7:0] v_o
);
always @(v_i) begin
case(v_i)
0: v_o = 0;
1: v_o = 1;
2: v_o = 1;
3: v_o = 1;
4: v_o = 1;
5: v_o = 1;
6: v_o = 1;
7: v_o = 1;
8: v_o = 1;
9: v_o = 1;
10: v_o = 1;
11: v_o = 1;
12: v_o = 1;
13: v_o = 1;
14: v_o = 1;
15: v_o = 1;
16: v_o = 1;
17: v_o = 1;
18: v_o = 1;
19: v_o = 1;
20: v_o = 1;
21: v_o = 1;
22: v_o = 1;
23: v_o = 1;
24: v_o = 1;
25: v_o = 1;
26: v_o = 1;
27: v_o = 1;
28: v_o = 1;
29: v_o = 1;
30: v_o = 1;
31: v_o = 1;
32: v_o = 1;
33: v_o = 2;
34: v_o = 2;
35: v_o = 2;
36: v_o = 2;
37: v_o = 2;
38: v_o = 2;
39: v_o = 2;
40: v_o = 2;
41: v_o = 3;
42: v_o = 3;
43: v_o = 3;
44: v_o = 3;
45: v_o = 3;
46: v_o = 4;
47: v_o = 4;
48: v_o = 4;
49: v_o = 4;
50: v_o = 4;
51: v_o = 5;
52: v_o = 5;
53: v_o = 5;
54: v_o = 5;
55: v_o = 6;
56: v_o = 6;
57: v_o = 6;
58: v_o = 6;
59: v_o = 7;
60: v_o = 7;
61: v_o = 7;
62: v_o = 7;
63: v_o = 8;
64: v_o = 8;
65: v_o = 8;
66: v_o = 9;
67: v_o = 9;
68: v_o = 9;
69: v_o = 10;
70: v_o = 10;
71: v_o = 10;
72: v_o = 11;
73: v_o = 11;
74: v_o = 12;
75: v_o = 12;
76: v_o = 12;
77: v_o = 13;
78: v_o = 13;
79: v_o = 14;
80: v_o = 14;
81: v_o = 15;
82: v_o = 15;
83: v_o = 15;
84: v_o = 16;
85: v_o = 16;
86: v_o = 17;
87: v_o = 17;
88: v_o = 18;
89: v_o = 18;
90: v_o = 19;
91: v_o = 19;
92: v_o = 20;
93: v_o = 20;
94: v_o = 21;
95: v_o = 22;
96: v_o = 22;
97: v_o = 23;
98: v_o = 23;
99: v_o = 24;
100: v_o = 25;
101: v_o = 25;
102: v_o = 26;
103: v_o = 26;
104: v_o = 27;
105: v_o = 28;
106: v_o = 28;
107: v_o = 29;
108: v_o = 30;
109: v_o = 30;
110: v_o = 31;
111: v_o = 32;
112: v_o = 33;
113: v_o = 33;
114: v_o = 34;
115: v_o = 35;
116: v_o = 36;
117: v_o = 36;
118: v_o = 37;
119: v_o = 38;
120: v_o = 39;
121: v_o = 40;
122: v_o = 40;
123: v_o = 41;
124: v_o = 42;
125: v_o = 43;
126: v_o = 44;
127: v_o = 45;
128: v_o = 46;
129: v_o = 46;
130: v_o = 47;
131: v_o = 48;
132: v_o = 49;
133: v_o = 50;
134: v_o = 51;
135: v_o = 52;
136: v_o = 53;
137: v_o = 54;
138: v_o = 55;
139: v_o = 56;
140: v_o = 57;
141: v_o = 58;
142: v_o = 59;
143: v_o = 60;
144: v_o = 61;
145: v_o = 62;
146: v_o = 63;
147: v_o = 64;
148: v_o = 65;
149: v_o = 67;
150: v_o = 68;
151: v_o = 69;
152: v_o = 70;
153: v_o = 71;
154: v_o = 72;
155: v_o = 73;
156: v_o = 75;
157: v_o = 76;
158: v_o = 77;
159: v_o = 78;
160: v_o = 80;
161: v_o = 81;
162: v_o = 82;
163: v_o = 83;
164: v_o = 85;
165: v_o = 86;
166: v_o = 87;
167: v_o = 89;
168: v_o = 90;
169: v_o = 91;
170: v_o = 93;
171: v_o = 94;
172: v_o = 95;
173: v_o = 97;
174: v_o = 98;
175: v_o = 99;
176: v_o = 101;
177: v_o = 102;
178: v_o = 104;
179: v_o = 105;
180: v_o = 107;
181: v_o = 108;
182: v_o = 110;
183: v_o = 111;
184: v_o = 113;
185: v_o = 114;
186: v_o = 116;
187: v_o = 117;
188: v_o = 119;
189: v_o = 121;
190: v_o = 122;
191: v_o = 124;
192: v_o = 125;
193: v_o = 127;
194: v_o = 129;
195: v_o = 130;
196: v_o = 132;
197: v_o = 134;
198: v_o = 135;
199: v_o = 137;
200: v_o = 139;
201: v_o = 141;
202: v_o = 142;
203: v_o = 144;
204: v_o = 146;
205: v_o = 148;
206: v_o = 150;
207: v_o = 151;
208: v_o = 153;
209: v_o = 155;
210: v_o = 157;
211: v_o = 159;
212: v_o = 161;
213: v_o = 163;
214: v_o = 165;
215: v_o = 166;
216: v_o = 168;
217: v_o = 170;
218: v_o = 172;
219: v_o = 174;
220: v_o = 176;
221: v_o = 178;
222: v_o = 180;
223: v_o = 182;
224: v_o = 184;
225: v_o = 186;
226: v_o = 189;
227: v_o = 191;
228: v_o = 193;
229: v_o = 195;
230: v_o = 197;
231: v_o = 199;
232: v_o = 201;
233: v_o = 204;
234: v_o = 206;
235: v_o = 208;
236: v_o = 210;
237: v_o = 212;
238: v_o = 215;
239: v_o = 217;
240: v_o = 219;
241: v_o = 221;
242: v_o = 224;
243: v_o = 226;
244: v_o = 228;
245: v_o = 231;
246: v_o = 233;
247: v_o = 235;
248: v_o = 238;
249: v_o = 240;
250: v_o = 243;
251: v_o = 245;
252: v_o = 248;
253: v_o = 250;
254: v_o = 253;
255: v_o = 255;
default: v_o = 0;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; char s[10010]; int main() { int n; cin >> n; while (n--) { string a; cin >> a; for (int i = 0; i < a.size(); i++) { s[i] = a[i]; } sort(s, s + a.size()); if (s[0] == s[a.size() - 1]) { cout << -1 << endl; } else { for (int i = 0; i < a.size(); i++) { cout << s[i]; } cout << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const int N = 1e6 + 5; inline int readint() { char c = getchar(); int ans = 0; while (c < 0 || c > 9 ) { c = getchar(); } while (c >= 0 && c <= 9 ) { ans = ans * 10 + c - 0 , c = getchar(); } return ans; } vector<int> tree[N]; bool check[N]; int father[N][21]; int deep[N]; void dfs(int x, int level) { for (int i = 0; father[father[x][i]][i]; i++) { father[x][i + 1] = father[father[x][i]][i]; } deep[x] = level; for (int i = 0; i < tree[x].size(); i++) { int to = tree[x][i]; if (to == father[x][0]) { continue; } father[to][0] = x; dfs(to, level + 1); } } int main() { int n, k; n = readint(), k = readint(); int u, v; for (int i = 1; i < n; i++) { u = readint(), v = readint(); tree[u].push_back(v); tree[v].push_back(u); } k = n - k; k--, check[n] = 1; dfs(n, 1); for (int i = n - 1; i >= 1 && k; i--) { int aim = -1; int now = i; if (check[i]) { continue; } for (int j = 20; j >= 0; j--) { if (father[now][j] == 0 || check[father[now][j]]) { continue; } now = father[now][j]; } if (deep[i] - deep[now] + 1 <= k) { now = i; while (now != 0 && !check[now]) { check[now] = 1; k--; now = father[now][0]; } } } for (int i = 1; i <= n - 1; i++) { if (!check[i]) { cout << i << ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long n, a, b; cin >> n >> a >> b; set<long long> s; while (a--) { long long j; cin >> j; s.insert(j); } for (long long i = 1; i <= n; i++) if (s.count(i)) cout << 1 ; else cout << 2 ; return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int arr[2], x; cin >> arr[0] >> arr[1] >> x; vector<int> v; int curr = 1; if (x % 2 == 1) { v.push_back(curr); arr[curr]--; curr ^= 1; for (int i = 0; i < x; i++) { v.push_back(curr); arr[curr]--; curr ^= 1; } if (arr[1] > 0) { while (arr[1]--) { cout << 1 ; } } for (int i = 0; i < v.size(); i++) cout << v[i]; if (arr[0] > 0) { while (arr[0]--) cout << 0 ; } } else { if (arr[0] <= arr[1]) { v.push_back(curr); arr[curr]--; curr ^= 1; for (int i = 0; i < x; i++) { v.push_back(curr); arr[curr]--; curr ^= 1; } if (arr[1] > 0) { while (arr[1]--) cout << 1 ; } for (int i = 0; i < v.size() - 1; i++) cout << v[i]; if (arr[0] > 0) { while (arr[0]--) cout << 0 ; } cout << 1 ; } else { curr = 0; v.push_back(curr); arr[curr]--; curr ^= 1; for (int i = 0; i < x; i++) { v.push_back(curr); arr[curr]--; curr ^= 1; } if (arr[0] > 0) { while (arr[0]--) cout << 0 ; } for (int i = 0; i < v.size() - 1; i++) cout << v[i]; if (arr[1] > 0) { while (arr[1]--) cout << 1 ; } cout << 0 ; } } cout << endl; }
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay_block
// Source Path: velocityControlHdl/Control_DQ_Currents/Control_Current1/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay_block
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En26
output signed [31:0] Out; // sfix32_En26
wire signed [31:0] Constant1_out1; // sfix32_En26
wire signed [31:0] Reset_Switch1_out1; // sfix32_En26
reg signed [31:0] In_Delay_out1; // sfix32_En26
wire signed [31:0] Constant_out1; // sfix32_En26
wire signed [31:0] Reset_Switch_out1; // sfix32_En26
// <S21>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S21>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S21>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S21>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S21>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay_block
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000000 + 10; const int MAXM = 600000 + 10; int a[64][64]; int ans, n, m; inline int sg(int x) { return 1 - 2 * x; } inline int sg(int s, int x) { return sg(s >> x & 1); } int main() { ios::sync_with_stdio(false); cin >> n; m = n >> 1; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) cin >> a[i][j]; int ans = 0; for (int s = 0; s < (1 << m + 1); s++) { int ret = a[m][m] * sg(s, m); for (int j = 0; j < m; j++) ret += a[m][j] * sg(s, j) + a[m][j + m + 1] * sg(s >> j & 1 ^ (s >> m & 1)); for (int i = 0; i < m; i++) { int tmp1 = a[i][m] + a[i + m + 1][m] * sg(s, m); int tmp2 = -tmp1; for (int j = 0; j < m; j++) tmp1 += abs(a[i][j] + a[i + m + 1][j] * sg(s, j) + a[i][j + m + 1] + a[i + m + 1][j + m + 1] * sg(s >> j & 1 ^ (s >> m & 1))); for (int j = 0; j < m; j++) tmp2 += abs(a[i][j] + a[i + m + 1][j] * sg(s, j) - a[i][j + m + 1] + a[i + m + 1][j + m + 1] * sg(s >> j & 1 ^ (s >> m & 1) ^ 1)); ret += max(tmp1, tmp2); } ans = max(ans, ret); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int mn(int a, int b) { return a < b ? a : b; } int main() { int a, b; scanf( %d%d , &a, &b); int x = mn(a, b); int ans = 1; for (int i = 2; i <= x; i++) { ans *= i; } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, i, x, y, best, w, cw, rt, a[200200]; vector<int> g[200200]; bool all; void dfs(int i, int p, int cur, int dst) { if (dst > best) { best = dst; cw = cur; w = i; } for (int j : g[i]) if (j != p) { dfs(j, i, ((a[j] == 0) ? cur : a[j]), (dst + int(a[j] != 0 && a[j] != cur))); } } int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); all = true; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] != 0) { all = false; rt = i; } g[i].clear(); } for (i = 1; i < n; i++) { scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } if (all) { puts( 1 ); continue; } best = 0; w = rt; cw = a[rt]; dfs(rt, 0, a[rt], 0); best = 0; dfs(w, 0, cw, 0); printf( %d n , (best + 3) / 2); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, d, nn = 0, as[200069], pst[200069], dp[256], mx[256]; pair<long long, long long> a[2][200069]; map<long long, long long> com; int main() { long long i, j, ii, k, p[2], mk, cm = 0, cr = 0, z = -1e18; scanf( %lld%lld%lld , &n, &m, &d); com[0] = 1; nn++; as[nn] = m; com[m] = 1; for (i = 1; i <= n; i++) { for (ii = 0; ii < 2; ii++) { scanf( %lld , p + ii); p[ii] -= !ii; a[ii][i] = {p[ii], i}; if (!com[p[ii]]) { nn++; as[nn] = p[ii]; com[p[ii]] = 1; } } } sort(as, as + nn + 1); for (i = 0; i <= nn; i++) { com[as[i]] = i; } for (ii = 0; ii < 2; ii++) { for (i = 1; i <= n; i++) { a[ii][i].first = com[a[ii][i].first] + !ii; } sort(a[ii] + 1, a[ii] + n + 1); } for (p[0] = 1, p[1] = 1, i = 1; i <= nn; i++) { for (; p[0] <= n && a[0][p[0]].first <= i; p[0]++) { for (j = 0; cr >> j & 1; j++) ; cr |= 1 << j; pst[a[0][p[0]].second] = j; } for (mk = 0; mk < 1 << d; mk++) { dp[mk] = -1e18; if ((mk & cr) == mk) { k = __builtin_popcount(mk); dp[mk] = mx[mk & cm] + (as[i] - as[i - 1]) * (k % 2); } } for (; p[1] <= n && a[1][p[1]].first <= i; p[1]++) { cr ^= 1 << pst[a[1][p[1]].second]; } cm = cr; for (mk = 0; mk < 1 << d; mk++) { mx[mk] = -1e18; mx[mk & cm] = max(mx[mk & cm], dp[mk]); if (i == nn) { z = max(z, dp[mk]); } } } printf( %lld n , z); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_4_V
`define SKY130_FD_SC_LS__O221A_4_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o221a_4 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_4_V
|
#include <bits/stdc++.h> using namespace std; const long long p = 1e9 + 7; long long read() { long long s = 0; char c = getchar(), lc = + ; while (c < 0 || 9 < c) lc = c, c = getchar(); while ( 0 <= c && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return lc == - ? -s : s; } void write(long long x) { if (x < 0) { putchar( - ); x = -x; } if (x < 10) putchar(x + 0 ); else { write(x / 10); putchar(x % 10 + 0 ); } } void print(long long x, char c = n ) { write(x); putchar(c); } inline void add(long long &x, long long y) { x += y; if (x >= p) x -= p; } inline long long lowbit(long long x) { return x & -x; } inline long long calc(long long x1, long long x2, long long y1, long long y2, long long k) { if (x2 - x1 < y2 - y1) swap(x1, y1), swap(x2, y2); long long tmp = x2 - x1; x2 = (x1 = (x1 ^ y1) & ~(tmp - 1)) + tmp; x1++; x2 = min(x2, k); if (x1 > x2 || y1 > y2) return 0; return (x1 + x2) * (x2 - x1 + 1) / 2 % p * (y2 - y1) % p; } inline long long solve(long long x, long long y, long long k) { long long ret = 0; for (long long i = x; i; i &= i - 1) for (long long j = y; j; j &= j - 1) add(ret, calc(i - lowbit(i), i, j - lowbit(j), j, k)); return ret; } signed main() { long long q = read(); while (q--) { long long x1 = read(), y1 = read(), x2 = read(), y2 = read(), k = read(); print((solve(x2, y2, k) - solve(x1 - 1, y2, k) - solve(x2, y1 - 1, k) + solve(x1 - 1, y1 - 1, k) + p + p) % p); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> g[200010]; int vis[200010], d[200010]; stack<int> his; void dfs(int u, int dd) { his.push(u); d[u] = dd; for (int v : g[u]) { if (!d[v]) dfs(v, dd + 1); else if (d[u] - d[v] + 1 >= ceil(sqrt(n))) { puts( 2 ); printf( %d n , d[u] - d[v] + 1); for (int i = d[v] - 1; i < d[u]; ++i) { printf( %d , his.top()); his.pop(); } exit(0); } } if (!vis[u]) for (int v : g[u]) vis[v] = 1; his.pop(); } int main() { scanf( %d%d , &n, &m); for (int i = 0, u, v; i < m; ++i) { scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1, 1); puts( 1 ); int visT = 0; for (int i = 1; visT < ceil(sqrt(n)); ++i) { if (!vis[i]) printf( %d , i), ++visT; } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> void maxtt(T& t1, T t2) { t1 = max(t1, t2); } template <typename T> void mintt(T& t1, T t2) { t1 = min(t1, t2); } bool debug = 0; int n, m, k; string direc = URDL ; const long long MOD2 = (long long)1000000007 * (long long)1000000007; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int& x, int y, int mod = 1000000007) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et(int x = -1) { printf( %d n , x); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { return y ? gcd1(y, x % y) : x; } int d[2][135][135]; int xa, ya, xb, yb; int dx[8] = {1, 2, 2, 1, -1, -2, -2, -1}, dy[8] = {2, 1, -1, -2, -2, -1, 1, 2}; void bfs(int x, int y, int w) { queue<pair<int, int> > q; q.push({x, y}); d[w][x][y] = 0; while (!q.empty()) { auto t = q.front(); q.pop(); for (int(k) = 0; (k) < (int)(8); (k)++) { int nx = t.first + dx[k], ny = t.second + dy[k]; if (nx >= 1 && nx <= n && ny >= 1 && ny <= m && d[w][nx][ny] > d[w][t.first][t.second] + 1) { d[w][nx][ny] = d[w][t.first][t.second] + 1; q.push({nx, ny}); } } } } int ox, oy; inline void dfs(int x, int y, int w) { for (int(k) = 0; (k) < (int)(8); (k)++) { int nx = x + dx[k], ny = y + dy[k]; if (nx == ox && ny == oy) { cout << nx << << ny << endl; exit(0); } } for (int(k) = 0; (k) < (int)(8); (k)++) { int nx = x + dx[k], ny = y + dy[k]; if (d[w][nx][ny] < d[w][x][y]) { cout << nx << << ny << endl; cin >> ox >> oy; dfs(nx, ny, w); return; } } } void fmain(int tid) { cin >> n >> m >> xa >> ya >> xb >> yb; for (int(i) = 0; (i) < (int)(2); (i)++) for (int(j) = 0; (j) < (int)(135); (j)++) for (int(k) = 0; (k) < (int)(135); (k)++) d[i][j][k] = (1000000000); bfs(n / 2, m / 2, 0); bfs(n / 2 + 1, m / 2, 1); int u = d[0][xa][ya], v = d[0][xb][yb], p = d[1][xa][ya], q = d[1][xb][yb]; if ((xa + ya + xb + yb) % 2 == 0) { if (q < u) { cout << BLACK << endl; cin >> ox >> oy; dfs(xb, yb, 1); } else if (v < u + 1) { cout << BLACK << endl; cin >> ox >> oy; dfs(xb, yb, 0); dfs(n / 2, m / 2, 1); } else { cout << WHITE << endl; ox = xb; oy = yb; dfs(xa, ya, 0); } } else { if (u <= q) { cout << WHITE << endl; ox = xb; oy = yb; dfs(xa, ya, 0); } else if (p <= q + 1) { cout << WHITE << endl; ox = xb; oy = yb; dfs(xa, ya, 1); dfs(n / 2 + 1, m / 2, 0); } else { cout << BLACK << endl; cin >> ox >> oy; dfs(xb, yb, 1); } } } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000; bool g[MAXN][MAXN]; bool mh[MAXN], mv[MAXN]; bool use[MAXN]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; g[a][b] = true; mv[a] = true; mh[b] = true; } int ans = 0; for (int i = 1; i < n - 1; i++) ans += !mh[i] + !mv[i]; if (n % 2 && !mh[n / 2] && !mv[n / 2]) ans--; cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_MS__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:01:50 03/29/2015
// Design Name:
// Module Name: aluparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module aluparam_behav
#( parameter BITSIZE = 16)
( output [BITSIZE-1:0] Y,
output [15:0] flags,
input [BITSIZE-1:0] A,
input [BITSIZE-1:0] B,
input [3:0] sel
);
reg [BITSIZE-1:0] outreg;
reg [15:0] flagreg;
reg carry;
reg overflow;
reg trash;
always @(A, B, sel) begin
flagreg = 0;
carry = 0;
trash = 0;
overflow = 0;
case(sel)
4'b0000: begin
outreg = A ^ B;
end
4'b0010: begin
outreg = A ~^ B;
end
4'b1000: begin
outreg = A & B;
end
4'b1010: begin
outreg = A | B;
end
4'b0100: begin
{carry, outreg} = A + B;
overflow = (($signed(A) >= 0 && $signed(B) >= 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) < 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0101: begin
{trash, outreg} = A + ~B + 1;
overflow = (($signed(A) >= 0 && $signed(B) < 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) >= 0 && $signed(outreg) >= 0)) ? 1 : 0;
end
4'b0111: begin
outreg = ~A;
end
default: begin
outreg = 0;
flagreg = 0;
end
endcase
flagreg[0] = carry; // Carry
flagreg[2] = (A < B) && (sel == 4'b0101); // Low
flagreg[5] = overflow; // Overflow
flagreg[6] = (outreg == 16'b0); // Zero Flag
flagreg[7] = outreg[BITSIZE-1]; // Negative (Sign) Flag
end
assign Y = outreg;
assign flags = flagreg;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4 ) #pragma GCC optimize( unroll-loops ) using namespace std; using i64 = int64_t; using ui64 = uint64_t; template <class A, class B> bool smin(A &x, B &&y) { if (y < x) { x = y; return true; } return false; } template <class A, class B> bool smax(A &x, B &&y) { if (x < y) { x = y; return true; } return false; } int const N = int(1e5 + 10); int const INF = int(1.2e9); struct node { int min_pos = INF; int min_neg = INF; }; node a[N]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int q; cin >> q; while (q--) { int t, l, r; cin >> t >> l >> r; --l, --r; if (t == 1) { int k; cin >> k; if (k > 0) { for (int i = l; i < r; ++i) { smin(a[i].min_pos, k); } } else { k = -k; for (int i = l; i < r; ++i) { smin(a[i].min_neg, k); } } } else { i64 ans = 0; for (int i = l; i < r; ++i) { int const x = a[i].min_pos; int const y = a[i].min_neg; if (x != INF && y != INF) { ans += x + y; } } cout << ans << n ; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; inline void writeln2() { cout << n ; } inline void writeln() { cout << n ; } inline void readln() {} template <typename T> inline void read(T&); template <typename T> inline void priws(T); template <typename T> inline void print(T); void err(vector<string>::iterator it) { ++it; } template <typename Head, typename... Tail> inline void readln(Head& head, Tail&... tail) { read(head); readln(tail...); } template <typename Head, typename... Tail> inline void writeln2(Head head, Tail... tail) { print(head); writeln2(tail...); } template <typename Head, typename... Tail> inline void writeln(Head head, Tail... tail) { priws(head); writeln2(tail...); } template <typename T> inline void writeln_range(T f, T s) { if (f != s) for (auto i = f; i != s; ++i) writeln(*i); } template <typename Head, typename... Tail> inline void err(vector<string>::iterator it, Head head, Tail... tail) { writeln((*it).substr((*it)[0] == ), = , head); err(++it, tail...); } vector<string> split(const string& s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.push_back(x); return move(v); } void run() { int n, T; double c; readln(n, T, c); vector<int> a(n); readln(a); vector<int> p; readln(p); int m = p.size(); int j = 0; double real = 0; double app = 0; long long sum = 0; for (int i = 0; i < (int)(n); ++i) { if (j == m) break; sum += a[i]; if (i >= T) sum -= a[i - T]; real = (0.0 + sum) / T; app = (app + (0.0 + a[i]) / T) / c; if (p[j] == i + 1) j++, writeln(real, app, fabs(app - real) / real); } } int main() { run(); return 0; } template <typename T> inline ostream& operator<<(ostream& os, vector<T>& _a); template <typename T1, typename T2> inline istream& operator>>(istream& is, pair<T1, T2>& _a) { return is >> _a.first >> _a.second; } template <typename T1, typename T2> inline ostream& operator<<(ostream& os, pair<T1, T2>& _a) { return os << _a.first << << _a.second; } template <typename T> inline ostream& operator<<(ostream& os, vector<T>& _a) { if (_a.size()) os << _a[0]; else os << n ; for (int i = 1; i < _a.size(); ++i) os << n [is_fundamental<T>::value] << _a[i]; return os; } template <typename T> inline istream& operator>>(istream& is, vector<T>& _a) { if (_a.size() == 0) { int _n; is >> _n; _a.resize(_n); } for (int i = 0; i < _a.size(); ++i) is >> _a[i]; return is; } void print(double _a) { printf( %.6f , _a); } void priws(double _a) { printf( %.6f , _a); } void read(double& _a) { scanf( %lf , &_a); } template <typename T> inline void print(T _a) { cout << << _a; } template <typename T> inline void priws(T _a) { cout << _a; } template <typename T> inline void read(T& _a) { cin >> _a; }
|
#include <bits/stdc++.h> const long long seed = 131; const int N = 1000010; char ac[N], bc[N]; int main() { int n; scanf( %d%s%s , &n, ac, bc), n--; for (int i = 0; i < n; i++) { if (bc[i] == N ) bc[i] = S ; else if (bc[i] == S ) bc[i] = N ; else if (bc[i] == E ) bc[i] = W ; else bc[i] = E ; } unsigned long long ha = 0, hb = 0, pow = 1; for (int l = 1; l <= n; l++) { ha += ac[n - l] * pow; hb *= 131, hb += bc[n - l]; pow *= 131; if (ha == hb) { printf( NO n ); return 0; } } printf( YES n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const double C = 0.57721566490153286060651209; const double pi = acos(-1.0); const int mod = 1e9 + 7; const int maxn = 1e5 + 10; int a[maxn]; int b[maxn]; int used[maxn]; int main() { int n; scanf( %d , &n); int k = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); b[a[i]]++; if (b[a[i]] & 1) k++; else k--; } if (k > 1) { printf( 0 n ); return 0; } long long pos = 0; for (int i = 1; i <= n / 2; ++i) if (a[i] != a[n - i + 1]) { pos = i; break; } else b[a[i]] -= 2; if (!pos) { printf( %lld n , 1LL * n * (n + 1) / 2); return 0; } int len = 0; for (int i = pos; i <= n; ++i) { used[a[i]]++; if (used[a[i]] * 2 > b[a[i]]) { if (i < n - i + 1 || (i == n - i + 1 && b[a[i]] % 2 == 0) || a[i] != a[n - i + 1]) break; } len++; } memset(used, 0, sizeof used); for (int i = n - pos + 1; i >= 1; --i) { used[a[i]]++; if (used[a[i]] * 2 > b[a[i]]) if (i > n - i + 1 || (i == n - i + 1 && b[a[i]] % 2 == 0) || a[i] != a[n - i + 1]) break; len++; } printf( %lld n , pos * (pos + len)); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_2_V
`define SKY130_FD_SC_LS__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_2_V
|
`timescale 1ns / 1ps
// `define DEBUG_SLOW
module dmix_dcm(
input wire clk245760_pad,
input wire rst_dcm,
output wire clk245760,
output wire clk491520,
output wire clk983040);
`ifdef DEBUG_SLOW
reg [1:0] mul_counter_ff;
always @(posedge clk245760_pad)
mul_counter_ff <= mul_counter_ff + 2'b1;
assign clk245760 = mul_counter_ff[1];
assign clk491520 = mul_counter_ff[0];
assign clk983040 = clk245760_pad;
`else
`ifndef NO_IP
assign clk245760 = clk245760_pad;
wire clk245760_unbuf; // = 48.0kHz * 64 bits * 32 clk/bit = 98.3040Mhz
wire clk491520_unbuf; // = 96.0kHz * 64 bits * 16 clk/bit = 98.3040Mhz
wire clk983040_unbuf; // = 192.0kHz * 64 bits * 8 clk/bit = 98.3040Mhz
DCM #(
.CLK_FEEDBACK("1X"),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_PERIOD(40.690),
.CLKOUT_PHASE_SHIFT("NONE"),
.DFS_FREQUENCY_MODE("LOW"),
.FACTORY_JF(16'hC080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) dcm983040(
.CLKFB(clk245760_unbuf),
.CLKIN(clk245760_pad),
.DSSEN(1'b0),
.PSCLK(1'b0), // phase shift
.PSEN(1'b0),
.PSINCDEC(1'b0),
.RST(rst_dcm),
.CLK0(clk245760_unbuf),
.CLK2X(clk491520_unbuf),
.CLKFX(clk983040_unbuf));
BUFG buf491520(.I(clk491520_unbuf), .O(clk491520));
BUFG buf983040(.I(clk983040_unbuf), .O(clk983040));
`else
reg clk245760_ff;
reg clk491520_ff;
reg clk983040_ff;
assign clk245760 = clk245760_ff;
assign clk491520 = clk491520_ff;
assign clk983040 = clk983040_ff;
initial begin
clk245760_ff = 0;
clk491520_ff = 0;
clk983040_ff = 0;
#(250);
end
always begin
#(1);
clk983040_ff = ~clk983040_ff;
#(4);
end
always begin
#(10);
clk491520_ff = ~clk491520_ff;
#(0);
end
always begin
#(5);
clk245760_ff = ~clk245760_ff;
#(15);
end
`endif
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int dp[225][1 << 16]; int dx[4] = {0, -1, 0, 1}; int dy[4] = {1, 0, -1, 0}; int tran[4] = {2, 3, 0, 1}; string s[15]; bool visit[15][15][1 << 16]; int n, m, length, backx, backy, startbody, status; struct snake { int x, y, body; } start; bool in(int x, int y) { return (x >= 0 && x < n && y >= 0 && y < m); } bool collision(int x, int y, snake sn) { int body = sn.body; int xx = sn.x; int yy = sn.y; for (int i = 1; i < length - 1; i++) { xx += dx[tran[body & 3]]; yy += dy[tran[body & 3]]; body >>= 2; if (x == xx && y == yy) return true; } return false; } int BFS() { queue<pair<snake, int>> Q; Q.push({start, 0}); visit[start.x][start.y][start.body] = 1; while (!Q.empty()) { snake nowsnake = Q.front().first; int nowstep = Q.front().second; if (s[nowsnake.x][nowsnake.y] == @ ) return nowstep; Q.pop(); for (int i = 0; i < 4; i++) { int nextx = nowsnake.x + dx[i]; int nexty = nowsnake.y + dy[i]; if (in(nextx, nexty) && s[nextx][nexty] != # && !collision(nextx, nexty, nowsnake)) { snake nextsnake; nextsnake.x = nextx; nextsnake.y = nexty; nextsnake.body = ((nowsnake.body << 2) & startbody) | i; if (!visit[nextsnake.x][nextsnake.y][nextsnake.body]) { visit[nextsnake.x][nextsnake.y][nextsnake.body] = true; Q.push({nextsnake, nowstep + 1}); } } } } return -1; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; length = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] != # && s[i][j] != @ && s[i][j] != . ) { if (s[i][j] == 1 ) { start.x = i; start.y = j; } if (s[i][j] - 0 > length) { backx = i; backy = j; length = s[i][j] - 0 ; } } } } startbody = (1 << ((length - 1) * 2)) - 1; status = 0; while (s[backx][backy] != 1 ) { for (int i = 0; i < 4; i++) { int newbackx = backx + dx[i]; int newbacky = backy + dy[i]; if (in(newbackx, newbacky) && s[newbackx][newbacky] + 1 == s[backx][backy]) { status <<= 2; status |= i; backx = newbackx; backy = newbacky; break; } } } start.body = status; cout << BFS() << endl; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000 * 1000 * 1000 + 7; const int INF = 1000 * 1000 * 1000; const long long LINF = (long long)INF * INF; struct Query { int l, r, ind, k; }; int n, m; int c[100100]; vector<int> adj[100100]; int cnt[100100], bnd[100100]; int ans[100100]; vector<int> st; int sttime[100100]; int fntime[100100]; Query qr[100100]; void dfs(int v, int par) { st.push_back(v); sttime[v] = st.size() - 1; for (int u : adj[v]) { if (u == par) { continue; } dfs(u, v); } fntime[v] = st.size() - 1; } bool mos_cmp(Query &a, Query &b) { if (a.l / 400 == b.l / 400) { return (a.l / 400 % 2 ? a.r > b.r : a.r < b.r); } return a.l / 400 < b.l / 400; } void mos_add(int i) { cnt[c[i]]++; bnd[cnt[c[i]]]++; } void mos_rem(int i) { bnd[cnt[c[i]]]--; cnt[c[i]]--; } int main(void) { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (int i = (1); i < (n + 1); i++) { cin >> c[i]; } for (int i = (0); i < (n - 1); i++) { int ai, bi; cin >> ai >> bi; adj[ai].push_back(bi); adj[bi].push_back(ai); } dfs(1, -1); for (int i = (0); i < (m); i++) { int vi, ki; cin >> vi >> ki; qr[i].l = sttime[vi]; qr[i].r = fntime[vi]; qr[i].k = ki; qr[i].ind = i; } sort(qr, qr + m, mos_cmp); int l = 0, r = -1; for (int i = (0); i < (m); i++) { while (l > qr[i].l) { l--; mos_add(st[l]); } while (r < qr[i].r) { r++; mos_add(st[r]); } while (l < qr[i].l) { mos_rem(st[l]); l++; } while (r > qr[i].r) { mos_rem(st[r]); r--; } ans[qr[i].ind] = bnd[qr[i].k]; } for (int i = (0); i < (m); i++) { cout << ans[i] << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const unsigned long long p = 31; const unsigned long long m = 1e9 + 7; bool compare(string a, string b) { sort(a.begin(), a.end()); sort(b.begin(), b.end()); int n = a.length(); unsigned long long hash_a = 0, hash_b = 0; unsigned long long p_pow = 1; for (int i = 0; i < n; i++) { hash_a = (hash_a + (a[i] - a + 1) * p_pow) % m; hash_b = (hash_b + (b[i] - a + 1) * p_pow) % m; p_pow = (p_pow * p) % m; } if (hash_a == hash_b) return true; return false; } bool check(string a, string b) { int blen = b.length(); int alen = a.length(); for (int i = 0; i + blen - 1 < alen; i++) { string aux = a.substr(i, blen); if (compare(b, aux)) return true; } return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { string a, b; cin >> a >> b; if (a.length() > b.length()) cout << NO << n ; else if (check(b, a)) cout << YES << n ; else cout << NO << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned long long ans = 1e18, n, k; cin >> n >> k; vector<unsigned long long> v; for (unsigned long long i = 1; i <= n; i++) if (n % i == 0) v.push_back(i); for (unsigned long long x : v) if (x < k) ans = min(ans, (n / x) * k + x); cout << ans; }
|
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