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#include <bits/stdc++.h> using namespace std; char a[101][101]; int n, i, j; int main() { cin >> n; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) cin >> a[i][j]; } for (i = 0; i < n - 2; i++) { if (a[i][0] == # ) { cout << NO << endl; return 0; } for (j = 1; j < n; j++) { if (a[i][j] == # ) { if (a[i + 1][j] == # && a[i + 1][j - 1] == # && a[i + 1][j + 1] == # && a[i + 2][j] == # ) { a[i + 1][j] = . ; a[i + 1][j - 1] = . ; a[i + 1][j + 1] = . ; a[i + 2][j] = . ; } else { cout << NO << endl; return 0; } } } } for (; i < n; i++) { for (j = 0; j < n; j++) { if (a[i][j] == # ) { cout << NO << endl; return 0; } } } cout << YES << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 0x7f7f7f7f; void setup() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout.precision(15); } struct seg_tree { struct node { int val; node(int _val = 0x7f7f7f7f) { val = _val; } node operator+(const node &y) { return {min(val, y.val)}; } }; int S; vector<node> arr; seg_tree(int _S) { S = _S; arr = vector<node>(2 * S); } void upd(int i, node v) { i += S + 1; arr[i] = v; while (i > 1) { i /= 2; arr[i] = arr[2 * i] + arr[2 * i + 1]; } } node query(int i, int j) { node res; for (i += S + 1, j += S + 1; i <= j; i /= 2, j /= 2) { if ((i & 1) == 1) res = res + arr[i++]; if ((j & 1) == 0) res = res + arr[j--]; } return res; } }; int find(seg_tree &seg, int i, int k) { int lo = 0, hi = i; int ans = 0; while (lo <= hi) { int mi = (lo + hi) / 2; int lv = seg.query(mi, i).val; if (lv <= k) { ans = mi; lo = mi + 1; } else hi = mi - 1; } return ans; } int look(vector<int> &all, int v) { return lower_bound(all.begin(), all.end(), v) - all.begin(); } const int MAXQ = 200005; int N, Q; seg_tree rows(1 << 19), cols(1 << 19); int L[MAXQ], LC[MAXQ]; int R[MAXQ], RC[MAXQ]; char T[MAXQ]; vector<bool> ater, atec; int main() { setup(); cin >> N >> Q; rows.upd(0, 0); cols.upd(0, 0); vector<int> all; all.push_back(0); for (int i = 0; i < Q; i++) { cin >> L[i] >> R[i] >> T[i]; all.push_back(L[i]); all.push_back(R[i]); } sort(all.begin(), all.end()); all.resize(unique(all.begin(), all.end()) - all.begin()); ater.resize(all.size()); atec.resize(all.size()); for (int i = 0; i < Q; i++) { int LC = look(all, L[i]); int RC = look(all, R[i]); if (T[i] == U ) { if (atec[LC] || ater[RC]) { cout << 0 << n ; continue; } int b = find(rows, RC, LC); cols.upd(LC, b); cout << all[RC] - all[b] << n ; atec[LC] = true; } else { if (ater[RC] || atec[LC]) { cout << 0 << n ; continue; } int b = find(cols, LC, RC); rows.upd(RC, b); cout << all[LC] - all[b] << n ; ater[RC] = true; } } }
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/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_srl_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
$dumpvars(0, test_axis_srl_fifo);
end
axis_srl_fifo #(
.DEPTH(4),
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.count(count)
);
endmodule
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#include <bits/stdc++.h> using namespace std; int GLL(long long& x) { return scanf( %lld , &x); } int GI(int& x) { return scanf( %d , &x); } int m, n; long long add(long long x, long long y) { x += y; if (x >= m) x -= m; return x; } long long sub(long long x, long long y) { x -= y; if (x < 0) x += m; return x; } long long mul(long long x, long long y) { return (x * y) % m; } long long powmod(long long a, long long b) { long long res = 1; a %= m; for (; b; b >>= 1) { if (b & 1) res = res * a % m; a = a * a % m; } return res; } bool euler_criterion(long long a, long long p) { return powmod(a, (p - 1) / 2) == 1; } long long tonelli_shanks(long long a, long long p) { long long q = p - 1; long long s = 0; while (q % 2 == 0) { s++; q /= 2; } long long z = rand() % p; while (euler_criterion(z, p)) { z = rand() % p; } long long c = powmod(z, q); long long r = powmod(a, (q + 1) / 2); long long t = powmod(a, q); long long m = s; while (t != 1) { long long lo = 1, hi = m - 1; long long i = -1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (powmod(t, 1LL << mid) == 1) { i = mid; hi = mid - 1; } else { lo = mid + 1; } } long long b = powmod(c, 1LL << (m - i - 1)); r = mul(b, r); t = mul(t, mul(b, b)); c = mul(b, b); m = i; } return r; } const int MAXN = 100005; long long a[MAXN], d[MAXN], sqrd[MAXN], sumd[MAXN], sumsqrd[MAXN]; long long sumsqr[MAXN]; unordered_set<long long> sa, stest; int main() { GI(m); GI(n); for (int i = 1; i <= (int)(n); i++) { GLL(a[i]); sa.insert(a[i]); } if (n == 0) { printf( %lld 0 n , a[0]); return 0; } memset(d, 0, sizeof d); memset(sqrd, 0, sizeof sqrd); memset(sumd, 0, sizeof sumd); memset(sumsqrd, 0, sizeof sumsqrd); sort(a + 1, a + n + 1); long long inv2 = powmod(2, m - 2); for (int i = 2; i <= n; i++) { d[i] = add(d[i - 1], mul(a[i] - a[i - 1], i - 1)); sqrd[i] = add(add(sqrd[i - 1], mul(2, mul(a[i] - a[i - 1], d[i - 1]))), mul(mul(a[i] - a[i - 1], a[i] - a[i - 1]), i - 1)); sumd[i] = add(sumd[i - 1], d[i]); sumsqrd[i] = add(sumsqrd[i - 1], sqrd[i]); } memset(sumsqr, 0, sizeof sumsqr); for (int i = 1; i < MAXN; i++) sumsqr[i] = add(sumsqr[i - 1], mul(i, i)); long long c = 0; for (int i = 1; i <= (int)(n - 1); i++) c = add(c, sumsqr[i]); long long test2 = mul(sumsqrd[n], powmod(c, m - 2)); if (test2 == 0 || euler_criterion(test2, m)) { long long test = test2 == 0 ? 1 : tonelli_shanks(test2, m); int fwd = 0; long long curr = add(a[1], test); while (curr != a[1] && sa.find(curr) != sa.end()) { fwd++; curr = add(curr, test); } int bwd = 0; curr = sub(a[1], test); while (curr != a[1] && sa.find(curr) != sa.end()) { bwd++; curr = sub(curr, test); } if (fwd + bwd + 1 >= n) { curr = add(curr, test); printf( %lld %lld n , curr, test); } else { printf( -1 n ); } } else { printf( -1 n ); return 0; } return 0; }
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//#############################################################################
//# Purpose: Stretches a pulse by DW+1 clock cycles #
//# Adds one cycle latency #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_stretcher #(parameter CYCLES = 5) // "wakeup" cycles
( input clk, // clock
input in, // input pulse
input nreset, // async active low reset
output out // stretched output pulse
);
reg [CYCLES-1:0] valid;
always @ (posedge clk or negedge nreset)
if(!nreset)
valid[CYCLES-1:0] <='b0;
else if(in)
valid[CYCLES-1:0] <={(CYCLES){1'b1}};
else
valid[CYCLES-1:0] <={valid[CYCLES-2:0],1'b0};
assign out = valid[CYCLES-1];
endmodule // oh_stretcher
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#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n; string s; cin >> n >> s; int steps0 = 0; int steps1 = 0; for (int i = 0; i < n; ++i) { steps0 += ((s[i] - 0 ) != (i % 2)); steps1 += ((s[i] - 0 ) == (i % 2)); } cout << min(steps0, steps1) << n ; return 0; }
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
typedef enum { EN_ZERO,
EN_ONE
} En_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
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#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int sum1 = (n * (n + 1)) / 2; if (sum1 % 2 == 0) { cout << 0 << endl; } else { cout << 1 << endl; } }
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#include <bits/stdc++.h> using namespace std; template <class T> __inline__ __attribute__((always_inline)) T read() { T x = 0, w = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) w = -w; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * w; } template <class T> __inline__ __attribute__((always_inline)) T read(T& x) { return x = read<T>(); } const int N = 1e5 + 10; struct edge { int v; long long w; }; vector<edge> to[N]; long long dis[N]; void dfs(int u) { for (const edge& e : to[u]) dis[e.v] = dis[u] + e.w, dfs(e.v); } int ch[N][2], fa[N]; long long tim[N], tag[N]; __inline__ __attribute__((always_inline)) bool nroot(int x) { return ch[fa[x]][0] == x or ch[fa[x]][1] == x; } void push_down(int x) { if (tag[x] != -1) { if (ch[x][0]) tim[ch[x][0]] = tag[ch[x][0]] = tag[x]; if (ch[x][1]) tim[ch[x][1]] = tag[ch[x][1]] = tag[x]; tag[x] = -1; } } void rotate(int x) { int y = fa[x], z = fa[y], l = x == ch[y][1], r = l ^ 1; if (nroot(y)) ch[z][y == ch[z][1]] = x; fa[x] = z; ch[y][l] = ch[x][r]; fa[ch[x][r]] = y; ch[x][r] = y; fa[y] = x; } void splay(int x) { vector<int> stk = {x}; for (int i = x; nroot(i);) stk.push_back(i = fa[i]); for (; stk.size(); stk.pop_back()) push_down(stk.back()); for (; nroot(x); rotate(x)) { int y = fa[x], z = fa[y]; if (nroot(y)) rotate((x == ch[y][1]) != (y == ch[z][1]) ? x : y); } } struct node { long long l, r; }; vector<node> buc; priority_queue<long long, vector<long long>, greater<long long>> heap; int main() { int n = read<int>(), m = read<int>(); for (int i = 1; i < n; ++i) { int u = read<int>(), v = read<int>(); to[u].push_back({v, read<long long>()}); ch[u][1] = v, fa[v] = u; } dfs(1); for (int i = 1; i <= n; ++i) { tim[i] = -dis[i]; tag[i] = -1; } while (m--) { int s = read<int>(); long long t = read<long long>(); splay(s); for (int x = fa[s], y = s; x; y = x, x = fa[x]) { splay(x), ch[x][1] = y; buc.push_back({tim[x] + dis[x] + 1, t + dis[x]}); } splay(s); if (ch[s][0]) tim[ch[s][0]] = tag[ch[s][0]] = t; } sort(buc.begin(), buc.end(), [&](const node& a, const node& b) -> bool { return a.l < b.l; }); long long now = 1; int cnt = 0; for (int i = 0; i < (int)buc.size(); ++i) { for (; buc[i].l > now and heap.size(); heap.pop()) { long long r = heap.top(); if (now > r) { for (int j = 0; j < i; ++j) cnt -= buc[j].r >= r; for (; heap.size(); heap.pop()) cnt += heap.top() >= r; printf( %lld %d n , r, cnt); return 0; } now = now + 1; ++cnt; } if (buc[i].l > now) now = buc[i].l; heap.push(buc[i].r); } for (; heap.size(); heap.pop()) { long long r = heap.top(); if (now > r) { for (int i = 0; i < (int)buc.size(); ++i) cnt -= buc[i].r >= r; for (; heap.size(); heap.pop()) cnt += heap.top() >= r; printf( %lld %d n , r, cnt); return 0; } now = now + 1, ++cnt; } printf( -1 %d n , cnt); return 0; }
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#include <bits/stdc++.h> using namespace std; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } dbg; char ibuf[4096]; int ipt = 4096; int readUInt() { while (ipt < 4096 && ibuf[ipt] < 0 ) ipt++; if (ipt == 4096) { fread(ibuf, 1, 4096, stdin); ipt = 0; while (ipt < 4096 && ibuf[ipt] < 0 ) ipt++; } int n = 0; char neg = 0; if (ipt != 0 && ibuf[ipt - 1] == - ) neg = 1; while (ipt < 4096 && ibuf[ipt] >= 0 ) n = (n * 10) + (ibuf[ipt++] - 0 ); if (ipt == 4096) { fread(ibuf, 1, 4096, stdin); ipt = 0; while (ipt < 4096 && ibuf[ipt] >= 0 ) n = (n * 10) + (ibuf[ipt++] - 0 ); } return neg ? -n : n; } int testcase; void solve() { int n; scanf( %d , &n); ; int d; scanf( %d , &d); ; int l; scanf( %d , &l); ; int v[n]; int d1 = d; if (d > 0) { for (int i = 0; i < n; ++i) { if (i % 2 == 0) { if (d1 > 0) { v[i] = min(l, d1); d1 -= v[i]; } else { v[i] = 1; d1 -= 1; } } else { v[i] = 1; d1 += 1; } } } else { for (int i = 0; i < n; ++i) { if (i % 2 == 0) { v[i] = 1; d1 -= 1; } else { if (d1 < 0) { v[i] = min(l, -d1); d1 += v[i]; } else { d1 += 1; } } } } if (d1 == 1 && l > 1) { for (int i = 0; i < n; i++) { if (i % 2 == 0 && v[i] < l) { v[i]++; d1 = 0; break; } else if (i % 2 == 1 && v[i] > 1) { v[i]--; d1 = 0; break; } } } if (d1 == -1 && l > 1) { for (int i = 0; i < n; i++) { if (i % 2 == 0 && v[i] > 1) { v[i]--; d1 = 0; break; } else if (i % 2 == 1 && v[i] < l) { v[i]++; d1 = 0; break; } } } if (d1 != 0) { printf( -1 n ); } else { for (int i = 0; i < n; ++i) { if (i) printf( ); printf( %d , v[i]); } printf( n ); } } int main() { solve(); return 0; }
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#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const int N = 2005; int z, n, k, c, i, ind, tab[N]; char t[N]; string s; vector<pair<int, int> > v; void sett(int val, int ind) { if (tab[ind] == val) return; int i = ind + 1; while (tab[i] != val) i++; v.push_back(pair<int, int>(ind, i)); while (ind < i) { swap(tab[ind], tab[i]); ind++; i--; } } int main() { scanf( %d , &z); while (z--) { scanf( %d %d , &n, &k); scanf( %s , t); s = t; for (i = 0; i < n; i++) if (s[i] == ( ) tab[i] = 0; else tab[i] = 1; v.clear(); ind = 0; for (i = 0; i < k - 1; i++) { sett(0, ind++); sett(1, ind++); } c = n / 2 - k + 1; for (i = 0; i < c; i++) sett(0, ind++); for (i = 0; i < c; i++) sett(1, ind++); printf( %d n , v.size()); for (auto& w : v) printf( %d %d n , w.first + 1, w.second + 1); } return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> g[100002]; int find(int v, int* parent) { if (parent[v] == v) { return v; } return find(parent[v], parent); } int vis[100002]; int dp[100002]; void dfs(int u) { vis[u] = 1; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (!vis[v]) dfs(v); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, s; cin >> n >> s; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } int cnt = 0; for (int i = 1; i <= n; i++) { if (g[i].size() == 1) cnt++; } double ans = (2. * s) / (1. * cnt); cout << setprecision(12) << ans << endl; return 0; }
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/*
* This demonstrates a basic dynamic array
*/
module main;
string foo[];
int idx;
string tmp;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
tmp = "fooa";
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
tmp[3] = 'h41 + idx;
foo[idx] = tmp;
end
$display("foo[7] = %0s", foo[7]);
if (foo[7] != "fooH") begin
$display("FAILED -- foo[7] = %0s (s.b. fooH)", foo[7]);
$finish;
end
$display("foo[9] = %0s", foo[9]);
if (foo[9] != "fooJ") begin
$display("FAILED -- foo[9] = %0d (s.b. fooJ)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
tmp[3] = 'h41 + (idx%10);
if (foo[idx%10] != tmp) begin
$display("FAILED -- foo[%0d%%10] = %0s", idx, foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int num[10010]; int dp[1 << 18]; int bad[1 << 18]; int g[100][100]; int tmp[1 << 18]; string s; int get(int l, int r) { int t = 0; for (int i = l; i <= r; ++i) { t |= 1 << (s[i] - a ); } return t; } int main() { int n, p; scanf( %d%d , &n, &p); cin >> s; memset(num, 0, sizeof(num)); memset(g, 0, sizeof(g)); memset(bad, 0, sizeof(bad)); for (int i = 0; i < s.size(); ++i) { num[s[i] - a ]++; } for (int i = 0; i < p; ++i) { for (int j = 0; j < p; ++j) { scanf( %d , &g[i][j]); } } for (int i = 0; i < p; ++i) { for (int j = 0; j < p; ++j) { if (g[i][j]) continue; memset(tmp, 0, sizeof(tmp)); int l = -1; for (int k = 0; k < s.size(); ++k) { if (s[k] - a == i || s[k] - a == j) { if (l == -1) { l = k; } else { int a = s[l] - a , b = s[k] - a ; if ((a == i || a == j) && (b == i || b == j)) { if ((a == i && b == j) || (b == j && a == i)) { int m = get(l + 1, k - 1); tmp[m] = 1; } l = k; } } } } for (int ii = 0; ii < (1 << p); ++ii) { if ((ii & (1 << i)) || (ii & (1 << j))) continue; for (int k = 0; k < p; ++k) { if (k == i || k == j) continue; tmp[ii | (1 << k)] |= tmp[ii]; } if (tmp[ii]) bad[ii] = tmp[ii]; } } } memset(dp, 0, sizeof(dp)); dp[0] = 1; int ans = 0; for (int i = 0; i < (1 << p); ++i) { if (bad[i]) continue; for (int j = 0; j < p; ++j) { if ((1 << j) & i) { if (dp[i ^ (1 << j)]) dp[i] = 1; } } if (dp[i]) { int s = 0; for (int j = 0; j < p; ++j) { if ((1 << j) & i) s += num[j]; } ans = max(ans, s); } } printf( %d n , n - ans); }
|
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : (-x); } template <class T> T sqr(T x) { return x * x; } const int maxn = 57; char ty[maxn][maxn]; bool allow[300]; int d[maxn][maxn]; int f[maxn][maxn]; int n, m, k; int sx, sy, fx, fy; int Q[maxn * maxn * 2]; int qs, qt; const int dx[] = {-1, 0, 0, 1}; const int dy[] = {0, -1, 1, 0}; void bfs() { d[sx][sy] = 0; qs = 0, qt = 0; Q[qs++] = sx * maxn + sy; while (qs > qt) { int x = Q[qt] / maxn; int y = Q[qt] % maxn; if (x == fx && y == fy) break; ++qt; for (int dir = 0; dir < 4; ++dir) { int X = x + dx[dir], Y = y + dy[dir]; if (X < 0 || Y < 0 || X >= n || Y >= m) continue; if (d[X][Y] != -1) continue; if (!allow[ty[X][Y]]) continue; d[X][Y] = d[x][y] + 1; f[X][Y] = x * maxn + y; Q[qs++] = X * maxn + Y; } } } string cur; string rf[maxn][maxn]; bool uf[maxn][maxn]; void rest() { memset(uf, 0, sizeof(uf)); rf[sx][sy] = S ; qs = 0, qt = 0; uf[sx][sy] = true; Q[qs++] = sx * maxn + sy; while (qs > qt) { int x = Q[qt] / maxn; int y = Q[qt] % maxn; if (x == fx && y == fy) break; ++qt; string& s = rf[x][y]; for (int dir = 0; dir < 4; ++dir) { int X = x + dx[dir], Y = y + dy[dir]; if (X < 0 || Y < 0 || X >= n || Y >= m) continue; if (d[X][Y] != d[x][y] + 1) continue; if (!uf[X][Y]) { uf[X][Y] = true; rf[X][Y] = rf[x][y] + ty[X][Y]; Q[qs++] = X * maxn + Y; } else { rf[X][Y] = min(rf[X][Y], rf[x][y] + ty[X][Y]); } } } cur = rf[fx][fy]; } int main() { cin >> n >> m >> k; for (int i = 0; i < n; ++i) { string s; cin >> s; for (int j = 0; j < m; ++j) { ty[i][j] = s[j]; if (islower(s[j])) { continue; } if (s[j] == S ) sx = i, sy = j; else fx = i, fy = j; } } int res = 100500100; string rs; bool rsf = false; set<long long> S; for (int i = a ; i <= z ; ++i) for (int j = a ; j <= i; ++j) for (int p = a ; p <= j; ++p) for (int q = a ; q <= p; ++q) { long long h = 123; if (k >= 1) h = h * 2184057 + i; if (k >= 2) h = h * 2184057 + j; if (k >= 3) h = h * 2184057 + p; if (k >= 4) h = h * 2184057 + q; if (S.count(h)) continue; S.insert(h); memset(allow, 0, sizeof(allow)); if (k >= 1) allow[i] = true; if (k >= 2) allow[j] = true; if (k >= 3) allow[p] = true; if (k >= 4) allow[q] = true; allow[ S ] = allow[ T ] = true; memset(d, -1, sizeof(d)); bfs(); if (d[fx][fy] == -1) continue; if (d[fx][fy] > res) continue; if (res > d[fx][fy]) res = d[fx][fy]; } S.clear(); int bad = 1000000; for (int i = a ; i <= z ; ++i) for (int j = a ; j <= i; ++j) for (int p = a ; p <= j; ++p) for (int q = a ; q <= p; ++q) { if (i >= bad && j >= bad && p >= bad && q >= bad) continue; long long h = 123; if (k >= 1) h = h * 2184057 + i; if (k >= 2) h = h * 2184057 + j; if (k >= 3) h = h * 2184057 + p; if (k >= 4) h = h * 2184057 + q; if (S.count(h)) continue; S.insert(h); memset(allow, 0, sizeof(allow)); if (k >= 1) allow[i] = true; if (k >= 2) allow[j] = true; if (k >= 3) allow[p] = true; if (k >= 4) allow[q] = true; allow[ S ] = allow[ T ] = true; memset(d, -1, sizeof(d)); bfs(); if (d[fx][fy] == -1) continue; if (d[fx][fy] > res) continue; rest(); if (!rsf || cur < rs) { rsf = true, rs = cur; bad = -1; for (int t = 0; t < ((int)(cur).size()); ++t) bad = max(bad, (int)cur[t]); } } if (res == 100500100) res = -1; if (res == -1) cout << res << n ; else cout << rs.substr(1, ((int)(rs).size()) - 2) << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long minOf(long long x, long long y) { return (x < y ? x : y); } inline long long maxOf(long long x, long long y) { return (x > y ? x : y); } char arr[50000000], *ptr; long long ret; string str; inline long long get_int() { bool isNeg = false; ret = 0; while (!((*ptr >= 0 && *ptr <= 9 ) || *ptr == - )) ptr++; while ((*ptr >= 0 && *ptr <= 9 ) || *ptr == - ) { if (*ptr == - ) isNeg = true; else ret = ret * 10 + (*ptr - 0 ); ptr++; } if (isNeg) ret = -ret; return ret; } long long a[100005]; int bits[33]; int main() { fread(arr, sizeof(char), 50000000, stdin); ptr = arr; int n = get_int(); for (int i = 0; i < 33; i++) bits[i] = -1; for (int i = 0; i < n; i++) { a[i] = get_int(); for (int j = 0; j < 32; j++) { if (a[i] & (1 << j)) { if (bits[j] == -1) bits[j] = a[i]; else bits[j] = a[i] & bits[j]; } } } int k = 0; vector<int> list; int lk = 0; for (int i = 32; i >= 0; i--) { if (bits[i] != -1) { for (int j = 0; j < 32; j++) { if (bits[i] & (1 << j)) { if (j > lk) lk = j; break; } } } } for (int j = 0; j < n; j++) { if (a[j] & (1 << lk)) { k++; list.push_back(a[j]); } } cout << k << endl; for (int i = 0; i < k; i++) { cout << list[i] << ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
/**
* top_refgen_new: The REFGEN block (sky130_fd_io__top_refgen) is used
* to provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen_new (
//# {{data|Data Signals}}
input DFT_REFGEN ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ENABLE_H ,
input ENABLE_VDDA_H,
input HLD_H_N ,
input IBUF_SEL ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input VREG_EN ,
input VTRIP_SEL ,
inout VSWITCH ,
inout REFLEAK_BIAS ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
output VINREF ,
inout VINREF_DFT ,
input VOHREF ,
output VOUTREF ,
inout VOUTREF_DFT ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v4_0_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
#include<bits/stdc++.h> using namespace std; #define endl n int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin>>t; while(t--) { long long int n,i,j,k,l; cin>>n>>k; if(k==1) { cout<< 1 <<endl; continue; } if(n&1) { if(k*2>n-2) { j=(n-2)/2+1; l=(k-1)/j; k=k+l; } } if(k%n==0) cout<<n<<endl; else cout<<(k%n)<<endl; } return 0; }
|
#include <bits/stdc++.h> const long long inf = 1000000000; const long long inf64 = inf * inf; const double pi = acos(-1.0); long long Abs(long long x) { return (x >= 0 ? x : -x); } using namespace std; bool solve() { int n; cin >> n; vector<vector<long long> > mat(n, vector<long long>(n)); vector<long long> ans(n, 0); for (int i(0); i < n; i++) for (int j(0); j < n; j++) cin >> mat[i][j]; for (int i(0); i < n; i++) { for (int j(0); j < n; j++) { if (i == j) continue; ans[j] |= mat[i][j]; } } for (int i(0); i < n; i++) cout << ans[i] << ; return true; } int main() { solve(); return 0; }
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
(* X_CORE_INFO = "xlconcat,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_xlconcat_0_0,xlconcat,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN2\
4_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// iverilog -y .. -o tb-DataBuffer.vvp tb-DataBuffer.v
// vvp tb-DataBuffer.vvp
`timescale 1ns/1ns
module tb;
localparam W = 8;
localparam CYC = 10;
reg clk, rst;
reg idata_vld;
wire idata_rdy;
reg [W-1:0] idata;
wire odata_vld;
reg odata_rdy;
wire [W-1:0] odata;
DataBuffer#(W) dut(clk, rst, idata_vld, idata_rdy, idata, odata_vld, odata_rdy, odata);
initial begin
#0;
rst = 1'b1;
#(10*CYC+CYC/3);
rst = 1'b0;
end
initial begin
#0;
clk = 1'b0;
#(CYC);
forever begin
clk = 1'b1;
#(CYC/2);
clk = 1'b0;
#(CYC-CYC/2);
end
end
task wait_reset_release;
begin
@(posedge clk);
while (rst) @(posedge clk);
end
endtask
event idata_update_event;
reg idata_update_ctrl;
initial begin :ivld
reg [31:0] rngseed, rnum;
integer n;
#0;
idata_vld = 1'b0;
wait_reset_release;
rngseed = 32'h01234567;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
idata_vld <= 1'b0;
idata_update_ctrl = 1'b0;
-> idata_update_event;
repeat (n) @(posedge clk);
end
idata_vld <= 1'b1;
idata_update_ctrl = 1'b1;
-> idata_update_event;
@(posedge clk);
while (~idata_rdy) @(posedge clk);
end
end
initial begin :idat
reg [31:0] rngseed, rnum;
#0;
idata = {W{1'b0}};
rngseed = 32'h23456789;
forever begin
@(idata_update_event);
if (idata_update_ctrl) begin
rnum = $random(rngseed);
idata <= rnum[W-1:0];
end else begin
idata <= {W{1'bx}};
end
end
end
initial begin :ordy
reg [31:0] rngseed, rnum;
integer n;
#0;
odata_rdy = 1'b0;
wait_reset_release;
rngseed = 32'h12345678;
forever begin
rnum = $random(rngseed);
n = rnum[7:0];
// 192 32 16 8 4 2 1 1
// 0 1 2 3 4 5 6 X
if (n >= 64) begin
n = 0;
end else if (n >= 32) begin
n = 1;
end else if (n >= 16) begin
n = 2;
end else if (n >= 8) begin
n = 3;
end else if (n >= 4) begin
n = 4;
end else if (n >= 2) begin
n = 5;
end else if (n >= 1) begin
n = 6;
end else begin
n = rnum[15:8];
end
if (n > 0) begin
odata_rdy <= 1'b0;
repeat (n) @(posedge clk);
end
odata_rdy <= 1'b1;
@(posedge clk);
end
end
initial begin
$dumpfile("tb-DataBuffer.vcd");
$dumpvars(0, dut);
#(1000*CYC);
$display("Simulated 1000 cycles.");
$finish;
end
initial begin :verify_idata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (idata_vld & idata_rdy) begin
rnum = $random(rngseed);
if (idata !== rnum[W-1:0]) begin
$display("%0t: Error: idata %h != %h", $time, idata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, idata);
end
@(posedge clk);
end
end
initial begin :verify_odata
reg [31:0] rngseed, rnum;
wait_reset_release;
rngseed = 32'h23456789;
forever begin
if (odata_vld & odata_rdy) begin
rnum = $random(rngseed);
if (odata !== rnum[W-1:0]) begin
$display("%0t: Error: odata %h != %h", $time, odata, rnum[W-1:0]);
#(CYC);
$finish;
end
$display("%0t: %h", $time, odata);
end
@(posedge clk);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long q, x; cin >> q >> x; long long n = q; long long a[n]; map<long long, long long> m; long long min = 0; map<long long, long long> f; for (long long i = 0; i < n; i++) { cin >> a[i]; long long mod = a[i] % x; f[mod]++; m[mod + ((f[mod] - 1) * x)]++; while (m[min] == 1) min++; cout << min << endl; } map<long long, long long>::iterator it; }
|
//
// Copyright (c) 1999 Thomas Coonan ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
`define DEBUG_SHOWREADS
`define DEBUG_SHOWWRITES
// Memory Map:
//
// PIC Data Memory addressing is complicated. See the Data Book for full explanation..
//
// Basically, each BANK contains 32 locations. The lowest 16 locations in ALL Banks
// are really all mapped to the same bank (bank #0). The first 8 locations are the Special
// registers like the STATUS and PC registers. The upper 16 words in each bank, really are
// unique to each bank. The smallest PIC (16C54) only has the one bank #0.
//
// So, as a programmer, what you get is this. No matter what bank you are in (FSR[6:5])
// you always have access to your special registers and also to registers 8-15. You can
// change to a 1 of 4 banks by setting FSR[6:5] and get 4 different sets of registers
// 16-31.
//
//
// bank location
// XX 00rrr - The special registers are not implemented in this register file.
// XX 01rrr - The 8 common words, just above the Special Regs, same for all Banks
// 00 1rrrr - The 16 words unique to Bank #0
// 01 1rrrr - The 16 words unique to Bank #1
// 10 1rrrr - The 16 words unique to Bank #2
// 11 1rrrr - The 16 words unique to Bank #3
//
// So,
// Special Regs are location[4:3] == 00
// Common Regs are location[4:3] == 01
// Words in banks location[4] == 1
//
// Remap to a new single memory space. Remap in chunks of 8 words. The PIC words
// will get remapped to the RAM in a contiguous manner. The Common registers are
// mapped to the first 8 words of our RAM. Next, each bank's words in the upper
// half of the bank are mapped to the RAM in a contiguous manner:
//
// PIC View Our RAM
// bank location Address
// 00 01rrr => 0 - 7 (common words)
// 00 10rrr => 8 - 15
// 00 11rrr => 16 - 23
// 01 01rrr => 0 - 7 (common words)
// 01 10rrr => 24 - 31
// 01 11rrr => 32 - 39
// 10 01rrr => 0 - 7 (common words)
// 10 10rrr => 40 - 47
// 10 11rrr => 48 - 55
// 11 01rrr => 0 - 7 (common words)
// 11 10rrr => 56 - 63
// 11 11rrr => 64 - 71 <-- last four locations are not implemented
//
//
//
module regs (clk, reset, we, re, bank, location, din, dout);
input clk;
input reset;
input we;
input re;
input [1:0] bank; // Bank 0,1,2,3
input [4:0] location; // Location
input [7:0] din; // Input
output [7:0] dout; // Output
// The top-level modulke, piccpu, is supposed to garuntee that re and we
// are asserted for only valid locations. So, we don't need to worry about
// safely mapping invalid addresses.
//
reg [6:0] final_address;
// Instatiate the final memory model.
//
dram dram (
.clk (clk),
.address (final_address),
.we (we),
.re (re),
.din (din),
.dout (dout)
);
// The final_address is our remapped address. This combinational logic
// is performed immediate on the input address signals, before any latching.
// This is because a WRITE doesn't use the latched values whereas the READ does.
//
always @(bank or location) begin
casex ({bank, location})
// First, let's handle the locations that all get mirrored back
// into the bank #0 words from 8-15.
//
7'b00_01XXX: final_address = {4'b0000, location[2:0]};
7'b01_01XXX: final_address = {4'b0000, location[2:0]};
7'b10_01XXX: final_address = {4'b0000, location[2:0]};
7'b11_01XXX: final_address = {4'b0000, location[2:0]};
// Now, handle words in the upper halves of each bank.
//
// Bank #0
7'b00_10XXX: final_address = {4'b0001, location[2:0]};
7'b00_11XXX: final_address = {4'b0010, location[2:0]};
// Bank #1
7'b01_10XXX: final_address = {4'b0011, location[2:0]};
7'b01_11XXX: final_address = {4'b0100, location[2:0]};
// Bank #2
7'b10_10XXX: final_address = {4'b0101, location[2:0]};
7'b10_11XXX: final_address = {4'b0110, location[2:0]};
// Bank #3
7'b11_10XXX: final_address = {4'b0111, location[2:0]};
7'b11_11XXX: final_address = {4'b1000, location[2:0]};
default: final_address = {4'b0000, location[2:0]};
endcase
end
endmodule
|
module PLLE2_ADV #(
parameter BANDWIDTH = "OPTIMIZED",
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
output [15:0] DO,
output DRDY,
output LOCKED,
output CLKFBOUT,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PWRDWN,
input RST
);
//#LOCAL DERIVED PARAMETERS
localparam real VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
localparam real CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
localparam real CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
localparam real CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
localparam real CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
localparam real CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
localparam real CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
localparam phases = CLKFBOUT_MULT / DIVCLK_DIVIDE;
//########################################################################
//# POR
//########################################################################
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
reg reset;
always @ (posedge CLKIN1)
reset <= POR | RST;
//########################################################################
//# CLOCK MULTIPLIER
//########################################################################
//TODO: implement DIVCLK_DIVIDE
//
integer j;
reg [2*phases-1:0] delay;
always @ (CLKIN1)
begin
for(j=0; j<(2*phases); j=j+1)
delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
end
reg [(phases)-1:0] clk_comb;
always @ (delay)
begin
for(j=0; j<(phases); j=j+1)
clk_comb[j] <= ~reset & delay[2*j] & ~delay[2*j+1];
end
reg vco_clk;
integer k;
always @*
begin
vco_clk = 1'b0;
for(k=0; k<(phases); k=k+1)
vco_clk = vco_clk | clk_comb[k];
end
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[5:0];
wire [5:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
genvar i;
generate for(i=0; i<6; i=i+1)
begin : gen_clkdiv
clock_divider clkdiv (/*AUTOINST*/
// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (reset));
end
endgenerate
reg [5:0] CLKOUT_DIV_LOCK;
always @ (posedge (CLKIN1&vco_clk) or negedge (CLKIN1&~vco_clk))
begin
CLKOUT_DIV_LOCK[5:0] <= CLKOUT_DIV[5:0];
end
//##############
//#SUB PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
always @ (CLKOUT_DIV_LOCK)
begin
CLKOUT0 <= #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
CLKOUT1 <= #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
CLKOUT2 <= #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
CLKOUT3 <= #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
CLKOUT4 <= #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
CLKOUT5 <= #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
//###########################
//#SANITY CHECK LOCK COUNTER
//############################
localparam LCW=4;
reg [LCW-1:0] lock_counter;
always @ (posedge CLKIN1 or posedge reset)
if(reset)
lock_counter[LCW-1:0] <= {(LCW){1'b1}};
else if(~LOCKED)
lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
assign LOCKED = ~(|lock_counter[LCW-1:0]);
endmodule // PLLE2_ADV
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module video_sys_Clock_Signals (
// Inputs
CLOCK_50,
reset,
// Bidirectional
// Outputs
SDRAM_CLK,
VGA_CLK,
sys_clk,
sys_reset_n
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
// Bidirectionals
// Outputs
output SDRAM_CLK;
output VGA_CLK;
output sys_clk;
output sys_reset_n;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
// Inputs
.inclk ({1'b0, CLOCK_50}),
// Outputs
.clk (sys_mem_clks),
.locked (clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_P_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_P_TB_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_P_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_request_generator (
input req_aclk,
input req_aresetn,
output [C_ID_WIDTH-1:0] request_id,
input [C_ID_WIDTH-1:0] response_id,
input req_valid,
output reg req_ready,
input [BURST_COUNT_WIDTH:0] req_burst_count,
input enable,
input pause,
output eot
);
parameter C_ID_WIDTH = 3;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BURST_ALIGN_BITS = 7;
parameter C_DMA_LENGTH_WIDTH = 24;
localparam BURST_COUNT_WIDTH = C_DMA_LENGTH_WIDTH - C_BURST_ALIGN_BITS;
`include "inc_id.v"
/*
* Here we only need to count the number of bursts, which means we can ignore
* the lower bits of the byte count. The last last burst may not contain the
* maximum number of bytes, but the address_generator and data_mover will take
* care that only the requested ammount of bytes is transfered.
*/
reg [BURST_COUNT_WIDTH-1:0] burst_count = 'h00;
reg [C_ID_WIDTH-1:0] id;
wire [C_ID_WIDTH-1:0] id_next = inc_id(id);
assign eot = burst_count == 'h00;
assign request_id = id;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
burst_count <= 'h00;
id <= 'h0;
req_ready <= 1'b1;
end else begin
if (req_ready) begin
if (req_valid && enable) begin
burst_count <= req_burst_count;
req_ready <= 1'b0;
end
end else if (response_id != id_next && ~pause) begin
if (eot)
req_ready <= 1'b1;
burst_count <= burst_count - 1'b1;
id <= id_next;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 6e5 + 8; const int T = 2e5 + 2; int n, b[N], t[N]; template <typename _Tp> inline void IN(_Tp& x) { char ch; bool flag = 0; x = 0; while (ch = getchar(), !isdigit(ch)) if (ch == - ) flag = 1; while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); if (flag) x = -x; } struct Segment_Tree { long long sum[N << 2]; void update(int x, int l, int r, int pos, int val) { if (l == r) { sum[x] += val; return void(); } (pos <= ((l + r) >> 1)) ? update(((x) << 1), l, ((l + r) >> 1), pos, val) : update(((x) << 1 | 1), ((l + r) >> 1) + 1, r, pos, val); sum[x] = max(sum[((x) << 1)], sum[((x) << 1 | 1)]); } } Tree; int main() { IN(n); for (int i = 1; i <= n; ++i) IN(b[i]), t[i] = b[i] - i + T; for (int i = 1; i <= n; ++i) Tree.update(1, 1, N - 1, t[i], b[i]); printf( %lld n , Tree.sum[1]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:17:00 09/05/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: LED_Segment_Mapper
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: LED to Seven-Segment Display Mapper
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module LED_Segment_Mapper
(
// Control Signals
input LED_ENABLE_1,
input LED_ENABLE_2,
// LED Data Signals
input [15:0] LED_DATA_1,
input [15:0] LED_DATA_2,
// Output Signals
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
// System Signals
input CLK
);
//
// LED Output Registers
//
reg [15:0] led_out_reg;
initial
begin
led_out_reg = 16'hFFFF;
end
always @(posedge CLK)
begin
led_out_reg[ 0] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 0]) | (LED_ENABLE_2 & LED_DATA_2[ 0]) );
led_out_reg[ 1] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 1]) | (LED_ENABLE_2 & LED_DATA_2[ 1]) );
led_out_reg[ 2] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 2]) | (LED_ENABLE_2 & LED_DATA_2[ 2]) );
led_out_reg[ 3] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 3]) | (LED_ENABLE_2 & LED_DATA_2[ 3]) );
led_out_reg[ 4] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 4]) | (LED_ENABLE_2 & LED_DATA_2[ 4]) );
led_out_reg[ 5] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 5]) | (LED_ENABLE_2 & LED_DATA_2[ 5]) );
led_out_reg[ 6] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 6]) | (LED_ENABLE_2 & LED_DATA_2[ 6]) );
led_out_reg[ 7] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 7]) | (LED_ENABLE_2 & LED_DATA_2[ 7]) );
led_out_reg[ 8] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 8]) | (LED_ENABLE_2 & LED_DATA_2[ 8]) );
led_out_reg[ 9] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 9]) | (LED_ENABLE_2 & LED_DATA_2[ 9]) );
led_out_reg[10] <= ~( (LED_ENABLE_1 & LED_DATA_1[10]) | (LED_ENABLE_2 & LED_DATA_2[10]) );
led_out_reg[11] <= ~( (LED_ENABLE_1 & LED_DATA_1[11]) | (LED_ENABLE_2 & LED_DATA_2[11]) );
led_out_reg[12] <= ~( (LED_ENABLE_1 & LED_DATA_1[12]) | (LED_ENABLE_2 & LED_DATA_2[12]) );
led_out_reg[13] <= ~( (LED_ENABLE_1 & LED_DATA_1[13]) | (LED_ENABLE_2 & LED_DATA_2[13]) );
led_out_reg[14] <= ~( (LED_ENABLE_1 & LED_DATA_1[14]) | (LED_ENABLE_2 & LED_DATA_2[14]) );
led_out_reg[15] <= ~( (LED_ENABLE_1 & LED_DATA_1[15]) | (LED_ENABLE_2 & LED_DATA_2[15]) );
end
//
// 7-Segment Display Mapping
//
// Map the 16 LED Output Signals to the
// outer LED segments of the 7-Segment Display
//
assign HEX3[0] = led_out_reg[ 0];
assign HEX4[0] = led_out_reg[ 1];
assign HEX5[0] = led_out_reg[ 2];
assign HEX5[5] = led_out_reg[ 3];
assign HEX5[4] = led_out_reg[ 4];
assign HEX5[3] = led_out_reg[ 5];
assign HEX4[3] = led_out_reg[ 6];
assign HEX3[3] = led_out_reg[ 7];
assign HEX2[3] = led_out_reg[ 8];
assign HEX1[3] = led_out_reg[ 9];
assign HEX0[3] = led_out_reg[10];
assign HEX0[2] = led_out_reg[11];
assign HEX0[1] = led_out_reg[12];
assign HEX0[0] = led_out_reg[13];
assign HEX1[0] = led_out_reg[14];
assign HEX2[0] = led_out_reg[15];
//
// Unused Segment Assignments
//
// This segment LEDs will not be used to leave turned off.
// NOTE: The compiler will generate warnings about these signals
// begin tied to GND. Those warnings can be ignored.
//
assign HEX0[6:4] = ~3'h0;
assign HEX1[2:1] = ~2'h0;
assign HEX1[6:4] = ~3'h0;
assign HEX2[2:1] = ~2'h0;
assign HEX2[6:4] = ~3'h0;
assign HEX3[2:1] = ~2'h0;
assign HEX3[6:4] = ~3'h0;
assign HEX4[2:1] = ~2'h0;
assign HEX4[6:4] = ~3'h0;
assign HEX5[2:1] = ~2'h0;
assign HEX5[6] = ~1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, +1, -1}; int dy[] = {+1, -1, 0, 0}; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } int biton(int N, int pos) { return N = N | (1 << pos); } int bitoff(int N, int pos) { return N = N & ~(1 << pos); } bool check(int N, int pos) { return (bool)(N & (1 << pos)); } int n, ar[1234567], k; pair<int, int> p[323456]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &p[i].first); p[i].second = i + 1; ar[i + 1] = p[i].first; } sort(p, p + n, greater<pair<int, int>>()); int start = k + 1; long long int ans = 0; map<int, int> block, ok; for (int i = 0; i < n; i++) { while (block[start] != 0) start++; if (start < p[i].second) { ok[p[i].second] = p[i].second; block[p[i].second] = p[i].second; } else { ok[p[i].second] = start; block[start] = start; start++; } } long long int sum = 0; for (int i = 1; i <= n; i++) { sum += 1LL * (ok[i] - i) * ar[i]; } printf( %lli n , sum); for (int i = 1; i <= n; i++) printf( %i , ok[i]); }
|
#include <bits/stdc++.h> int main(void) { int a[101]; int b, c, d, i, j, count = 0, num, number; scanf( %d %d , &b, &c); for (i = 0; i < b; i++) { scanf( %d , &a[i]); } for (i = 0; i < b - 1; i++) { for (j = i + 1; j < b; j++) { if (a[i] > a[j]) { d = a[i]; a[i] = a[j]; a[j] = d; } } } for (i = 0; i < b; i++) { num = 0; number = 1; for (j = i + 1; j < b; j++) { num += a[j] - a[j - 1]; if (num > c) { break; } else { number++; } } if (number > count) { count = number; } } printf( %d n , b - count); return 0; }
|
// daq_dma32_debug.v
`timescale 1 ns / 1 ps
/*
register set:
offset | bits | name |access| description
-------+------+-----------+------+--------------------------------
0 | 30:0 | mem_base | R/W |memory base byte address
4 | 25:0 | mem_size | R/W |memory size in words (16 bit)
8 | 25:0 | mem_read | R/W |memory read offset in words
12 | 25:0 | mem_write | R |memory write offset in words
16 | 0 | control | W | bit 0: enable
16 | 2:0 | status | R | {fifo_ovfl, ram_ovfl, running}
*/
module daq_dma32
(
input clk,
input reset,
// avalon mm data master
input avm_data_waitrq,
output avm_data_write,
output [31:0]avm_data_writedata,
output [31:0]avm_data_address,
output [3:0]avm_data_byteenable,
// avalon mm ctrl slave
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
input avs_ctrl_read,
output reg [31:0]avs_ctrl_readdata,
input [2:0]avs_ctrl_address,
// conduit interface
input clk_daq,
input write,
input [15:0]din,
output reg running
);
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire dreg_clear;
wire dreg_write;
wire [15:0]data;
wire [1:0]be;
wire next;
// register
reg [15:0]dreg;
reg dreg_empty;
reg [30:1]mem_base;
reg [26:1]mem_size;
reg [26:1]mem_read;
reg [26:1]mem_write;
reg next2;
reg start;
reg fifo_ovfl;
reg ram_ovfl;
reg running_int;
// --- register write -----------------------------------------------------
wire write_ctrl = avs_ctrl_write && (avs_ctrl_address == 3'd4);
wire set_start = write_ctrl && avs_ctrl_writedata[0];
wire set_stop = write_ctrl && !avs_ctrl_writedata[0];
wire [26:1]inc_addr = mem_write + 26'd1;
wire carry = inc_addr == mem_size;
wire [26:1]next_addr = carry ? 26'd0 : inc_addr;
wire overflow = next_addr == mem_read;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
dreg <= 0;
dreg_empty <= 1;
next2 <= 0;
mem_base <= 0;
mem_size <= 0;
mem_write <= 0;
mem_read <= 0;
start <= 0;
running_int <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
end
else
begin
start <= set_start;
if (running_int)
begin
if (dreg_write) {dreg, dreg_empty} = {data, 1'b0};
else if (dreg_clear) dreg_empty = 1'b1;
if (overflow) ram_ovfl <= 1;
if (fifo_full) fifo_ovfl <= 1;
if (overflow || fifo_full || set_stop) running_int <= 0;
if (next || next2) mem_write <= next_addr;
if ((be == 3) && avm_data_write && !avm_data_waitrq) next2 <= 1;
else if (!next) next2 <= 0;
if (avs_ctrl_write && (avs_ctrl_address == 2))
mem_read <= avs_ctrl_writedata[25:0];
end
else if (start)
begin
dreg_empty <= 1;
next2 <= 0;
mem_write <= 0;
mem_read <= 0;
fifo_ovfl <= 0;
ram_ovfl <= 0;
running_int <= 1;
end
else
begin
if (avs_ctrl_write)
case (avs_ctrl_address)
0: mem_base <= avs_ctrl_writedata[30:1];
1: mem_size <= avs_ctrl_writedata[25:0];
2: mem_read <= avs_ctrl_writedata[25:0];
endcase
end
end
end
// --- register read ------------------------------------------------------
always @(*)
begin
case (avs_ctrl_address)
0: avs_ctrl_readdata <= {1'b0, mem_base, 1'b0};
1: avs_ctrl_readdata <= {6'b000000, mem_size };
2: avs_ctrl_readdata <= {6'b000000, mem_read };
3: avs_ctrl_readdata <= {6'b000000, mem_write };
default: avs_ctrl_readdata <= {29'b0, fifo_ovfl, ram_ovfl, running_int};
endcase
end
// --- DMA write controller -----------------------------------------------
wire [30:1]address = mem_base + {4'b0000, mem_write};
reg [6:0]sm_out;
always @(*)
begin
if (running_int)
case ({fifo_empty, dreg_empty, address[1], avm_data_waitrq})
4'b0000: sm_out <= 7'b1011111;
4'b0001: sm_out <= 7'b0001110;
4'b0010: sm_out <= 7'b1101101;
4'b0011: sm_out <= 7'b0001100;
4'b0100: sm_out <= 7'b1100110;
4'b0101: sm_out <= 7'b1100110;
4'b0110: sm_out <= 7'b1100100;
4'b0111: sm_out <= 7'b1100100;
4'b1000: sm_out <= 7'b0011011;
4'b1001: sm_out <= 7'b0001010;
4'b1010: sm_out <= 7'b0011101;
4'b1011: sm_out <= 7'b0001100;
4'b1100: sm_out <= 7'b0000010;
4'b1101: sm_out <= 7'b0000010;
4'b1110: sm_out <= 7'b0000100;
4'b1111: sm_out <= 7'b0000100;
endcase
else sm_out <= 7'b0000000;
end
assign {fifo_read, dreg_write, dreg_clear, avm_data_write, be, next} = sm_out;
assign avm_data_byteenable = { be[1], be[1], be[0], be[0] };
assign avm_data_address = {1'b0, address[30:2], 2'b00};
assign avm_data_writedata = be[0] ? {data, dreg} : {dreg, dreg};
daq_dma_fifo buffer
(
.aclr(reset || start),
.data(din),
.rdclk(clk),
.rdreq(fifo_read),
.wrclk(clk_daq),
.wrreq(write),
.q(data),
.rdempty(fifo_empty),
.rdfull(fifo_full)
);
// clock crossing: runnning_int -> running
reg running1;
always @(posedge clk_daq or posedge reset)
begin
if (reset)
begin
running1 <= 0;
running <= 0;
end
else
begin
running1 <= running_int;
running <= running1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_PP_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__muxb8to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input [7:0] D ;
input [7:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_d0 ;
wire pwrgood_pp1_out_s0 ;
wire pwrgood_pp2_out_d1 ;
wire pwrgood_pp3_out_s1 ;
wire pwrgood_pp4_out_d2 ;
wire pwrgood_pp5_out_s2 ;
wire pwrgood_pp6_out_d3 ;
wire pwrgood_pp7_out_s3 ;
wire pwrgood_pp8_out_d4 ;
wire pwrgood_pp9_out_s4 ;
wire pwrgood_pp10_out_d5;
wire pwrgood_pp11_out_s5;
wire pwrgood_pp12_out_d6;
wire pwrgood_pp13_out_s6;
wire pwrgood_pp14_out_d7;
wire pwrgood_pp15_out_s7;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_d0 , D[0], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_s0 , S[0], VPWR, VGND );
bufif1 bufif10 (Z , !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (pwrgood_pp2_out_d1 , D[1], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (pwrgood_pp3_out_s1 , S[1], VPWR, VGND );
bufif1 bufif11 (Z , !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (pwrgood_pp4_out_d2 , D[2], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (pwrgood_pp5_out_s2 , S[2], VPWR, VGND );
bufif1 bufif12 (Z , !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (pwrgood_pp6_out_d3 , D[3], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (pwrgood_pp7_out_s3 , S[3], VPWR, VGND );
bufif1 bufif13 (Z , !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (pwrgood_pp8_out_d4 , D[4], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (pwrgood_pp9_out_s4 , S[4], VPWR, VGND );
bufif1 bufif14 (Z , !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (pwrgood_pp10_out_d5, D[5], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (pwrgood_pp11_out_s5, S[5], VPWR, VGND );
bufif1 bufif15 (Z , !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (pwrgood_pp12_out_d6, D[6], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (pwrgood_pp13_out_s6, S[6], VPWR, VGND );
bufif1 bufif16 (Z , !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (pwrgood_pp14_out_d7, D[7], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (pwrgood_pp15_out_s7, S[7], VPWR, VGND );
bufif1 bufif17 (Z , !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:16777216 ) const int fin = 111110; struct T { int cnt, val, l, r, mx, y, ans; T() : cnt(0), val(-1), l(fin), r(fin), mx(-1000000000), y(-1), ans(-1) {} }; T a[111111]; void upd(int v) { a[v].cnt = 1 + a[a[v].r].cnt + a[a[v].l].cnt; a[v].mx = max(a[v].val, max(a[a[v].r].mx, a[a[v].l].mx)); } void split(int v, int &l, int &r, int key) { l = r = fin; if (v == fin) return; if (key && (a[v].l == -1 || a[a[v].l].cnt < key)) { l = v; split(a[v].r, a[v].r, r, key - a[a[v].l].cnt - 1); upd(l); } else { r = v; split(a[v].l, l, a[v].l, key); upd(r); } } int merge(int l, int r) { if (l == fin) return r; if (r == fin) return l; if (a[l].y < a[r].y) { a[l].r = merge(a[l].r, r); upd(l); return l; } else { a[r].l = merge(l, a[r].l); upd(r); return r; } } int root, m; void push(int val) { a[m].y = (rand() << 16) + rand(); a[m].val = val; a[m].cnt = 1; a[m].mx = val; a[m].ans = m + 1; root = merge(root, m++); } int tot = 0; void print(int v) { if (v == fin) return; if (a[v].l != fin) print(a[v].l); { if (tot) printf( ); else tot = 1; printf( %d , a[v].ans); } if (a[v].r != fin) print(a[v].r); } int fmin(int st, int fn) { int r1, r2, r3, r4; split(root, r1, r2, st); split(r2, r3, r4, fn - st); int rez = (r3 != -1) ? (a[r3].mx) : (-1000000000); root = merge(r1, r3); root = merge(root, r4); return rez; } int n, A, C; int find(int v, int maxim, int value, int lft) { if (a[a[v].r].cnt + 1 > maxim) return find(a[v].r, maxim, value, lft + 1 + a[a[v].l].cnt); else if (a[a[v].r].mx > value) return find(a[v].r, maxim, value, lft + 1 + a[a[v].l].cnt); else if (a[v].val > value) return lft + a[a[v].l].cnt; else return find(a[v].l, maxim - 1 - a[a[v].r].cnt, value, lft); } int main() { a[fin].cnt = 0; a[fin].mx = -1000000000; scanf( %d , &n); for (int(i) = 0; (i) < (n); ++(i)) { scanf( %d%d , &A, &C); if (i) { int high = max(i - C, 0); if (fmin(high, i) > A) high = find(root, C, A, 0) + 1; int r1, r2; split(root, r1, r2, high); root = r1; push(A); root = merge(root, r2); } else { a[0].val = A; a[0].ans = 1; a[0].cnt = 1; a[0].mx = A; root = 0; m = 1; } } print(root); cout << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hvl__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A2BB2OI_PP_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; double tick() { static clock_t oldt, newt = clock(); double diff = 1.0 * (newt - oldt) / CLOCKS_PER_SEC; oldt = newt; return diff; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long a[4][4] = {0}; long long k; cin >> k; char c; std::map<long long, long long> mp; for (long long i = 0LL; i < (4); i++) for (long long j = 0LL; j < (4); j++) { cin >> c; if (c != . ) mp[c - 0 ]++; } bool flag = true; for (auto a : mp) if (a.second > (2 * k)) { flag = false; break; } if (flag) cout << YES ; else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int iinf = 1e9 + 7; const long long linf = 1ll << 60; const double dinf = 1e10; template <typename T> inline void scf(T &x) { bool f = 0; x = 0; char c = getchar(); while ((c < 0 || c > 9 ) && c != - ) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } if (f) x = -x; return; } template <typename T1, typename T2> void scf(T1 &x, T2 &y) { scf(x); return scf(y); } template <typename T1, typename T2, typename T3> void scf(T1 &x, T2 &y, T3 &z) { scf(x); scf(y); return scf(z); } const int N = 233; int n, l, k; int p[N], a[N]; double dp[N][N][N * 2]; int main() { scf(n, l, k); for (int i = (1); i <= (n); i++) scf(p[i]); for (int i = (1); i <= (n); i++) scf(a[i]); dp[0][0][k + 200] = 1.0; for (int i = 0; i < (n); i++) for (int j = (0); j <= (i); j++) for (int k = (0); k <= (400); k++) if (dp[i][j][k] > 1e-20) { dp[i + 1][j][k] += dp[i][j][k] * (1.0 * (100 - p[i + 1]) / 100.0); int nxtk = k; if (a[i + 1] < 0) nxtk--; else nxtk += a[i + 1]; if (nxtk > 400) nxtk = 400; if (k >= 0) dp[i + 1][j + 1][nxtk] += dp[i][j][k] * (1.0 * p[i + 1] / 100.0); } double ans = 0.0; for (int j = (l); j <= (n); j++) for (int k = (200); k <= (400); k++) ans += dp[n][j][k]; printf( %.12f n , ans); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// debounce # (
// .pCLKS(32'd 1_000_000) // number of clocks to count before signal is "stable"
// ) debounce_inst (
// .iCLK(), .iRESET(), .oSIG(), .iSIG()
// );
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module debounce # (
parameter pCLKS = 32'd 1_000_000) // around 20-50ms works OK for a button; 2-10us could work for an asynchronous machine source
(
input iCLK,
input iRESET, // active high reset
input iSIG,
output reg oSIG
);
integer debounceCtr = 0;
always @(posedge iCLK or posedge iRESET) begin
if (iRESET)
begin
debounceCtr <= 0;
oSIG <= 0;
end
else if (iSIG)
begin // iSIG trying to go high
if (!oSIG)
begin // output low, increment counter
if (debounceCtr < pCLKS)
begin
debounceCtr <= debounceCtr + 1;
oSIG <= 0;
end
else
begin
debounceCtr <= 0;
oSIG <= 1;
end
end
else
begin // output already high, do nothing
debounceCtr <= 0;
end
end
else
begin // iSIG trying to go low
if (oSIG)
begin
if (debounceCtr < pCLKS)
begin // output high, increment counter
debounceCtr <= debounceCtr + 1;
oSIG <= 1;
end
else
begin
debounceCtr <= 0;
oSIG <= 0;
end
end
else
begin // output already low, do nothing
debounceCtr <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void in(T &x) { x = 0; bool f = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while ( 0 <= c && c <= 9 ) { x = (x << 3) + (x << 1) + (c ^ 48); c = getchar(); } if (f) x = -x; } char s[1005]; int n, p; char can(int x) { for (register int i = s[x] + 1; i <= a + p - 1; ++i) if (i != s[x - 1] && i != s[x - 2]) return i; return 0; } signed main() { in(n), in(p); scanf( %s , s + 1); int pos = 0; for (register int i = n; i >= 1; --i) { if (can(i)) { s[i] = can(i); pos = i; break; } } if (!pos) { puts( NO ); return 0; } for (register int i = pos + 1; i <= n; ++i) { for (register int j = a ; j <= a + p - 1; ++j) if (j != s[i - 1] && j != s[i - 2]) { s[i] = j; break; } } for (register int i = 1; i <= n; ++i) putchar(s[i]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e15; long long arr[100003]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &arr[i]); if (n == 1 || n == 2) printf( 0 n ); else { long long res = INF; for (int i = -1; i <= 1; i++) { for (int j = -1; j <= 1; j++) { long long a = arr[0] + i; long long b = (arr[1] + j) - (arr[0] + i); long long cnt = abs(i) + abs(j); for (int k = 2; k < n; k++) { if (abs(a + (k * b) - arr[k]) > 1) cnt = INF; else cnt += abs(a + (k * b) - arr[k]); } res = min(res, cnt); } } if (res <= 1e9) printf( %lld n , res); else printf( -1 n ); } }
|
//==============================================================================
// Copyright (C) John-Philip Taylor
//
//
// This file is part of a library
//
// This file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>
//==============================================================================
module UART #(
parameter N = 5,
parameter Full = 5'd29 // Clk / BAUD - 1
)(
input Reset,
input Clk,
output [7:0]Rx_Data,
output Rx_Ready,
input Rx_Ack,
input [7:0]Tx_Data,
input Tx_Send,
output Tx_Busy,
input Rx,
output Tx
);
//------------------------------------------------------------------------------
UART_Rx #(N, Full) UART_Rx1(
Reset,
Clk,
Rx_Data,
Rx_Ready,
Rx_Ack,
Rx
);
//------------------------------------------------------------------------------
UART_Tx #(N, Full) UART_Tx1(
Reset,
Clk,
Tx_Data,
Tx_Send,
Tx_Busy,
Tx
);
//------------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 2000; vector<array<int, 2>> que; int degree[N][N], n, m; string grid[N]; bool valid(int i, int j) { return i >= 0 && i < n && j >= 0 && j < m && grid[i][j] == . ; } void update(int i, int j) { if (i >= 0 && i < n && j >= 0 && j < m) { degree[i][j] = 0; } if (valid(i - 1, j) && ++degree[i - 1][j] == 3) { que.push_back({i - 1, j}); } if (valid(i + 1, j) && ++degree[i + 1][j] == 3) { que.push_back({i + 1, j}); } if (valid(i, j - 1) && ++degree[i][j - 1] == 3) { que.push_back({i, j - 1}); } if (valid(i, j + 1) && ++degree[i][j + 1] == 3) { que.push_back({i, j + 1}); } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m; for (int i = 0; i < n; ++i) { cin >> grid[i]; } for (int i = 0; i < n; ++i) { update(i, -1), update(i, m); } for (int i = 0; i < m; ++i) { update(-1, i), update(n, i); } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (grid[i][j] == * ) { update(i, j); } } } while (!que.empty()) { auto [i, j] = que.back(); que.pop_back(); if (degree[i][j] == 0) { continue; } else if (degree[i][j] == 4) { cout << Not unique n ; exit(0); } if (valid(i - 1, j)) { grid[i - 1][j] = ^ , grid[i][j] = v ; update(i - 1, j); } else if (valid(i + 1, j)) { grid[i][j] = ^ , grid[i + 1][j] = v ; update(i + 1, j); } else if (valid(i, j - 1)) { grid[i][j - 1] = < , grid[i][j] = > ; update(i, j - 1); } else { grid[i][j] = < , grid[i][j + 1] = > ; update(i, j + 1); } update(i, j); } for (int i = 0; i < n; ++i) { if (count(grid[i].begin(), grid[i].end(), . ) > 0) { cout << Not unique n ; exit(0); } } for (int i = 0; i < n; ++i) { cout << grid[i] << n ; } }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const long double PI = 3.141592653589793238462643383279502884197; priority_queue<int, vector<int>, greater<int> > pq; vector<int> v; int cnt[512]; pair<int, int> vec[512]; pair<int, int> sec[512]; int main() { memset(vec, 0x3f, sizeof(vec)); memset(vec, 0x3f, sizeof(vec)); int n, m; scanf( %d %d , &n, &m); int t; for (int i = 0; i < n; i++) { scanf( %d , &t); vector<int> kk; int k, bit = 0; while (t--) { scanf( %d , &k); k--; bit |= 1 << k; } for (int j = 0; j < 512; j++) if ((bit & j) == bit) cnt[j]++; } for (int i = 0; i < m; i++) { int p, t, bit = 0; scanf( %d %d , &p, &t); while (t--) { int k; scanf( %d , &k); k--; bit |= (1 << k); } if (vec[bit].first > p) { sec[bit] = vec[bit]; vec[bit] = {p, i + 1}; } else if (sec[bit].first > p) { sec[bit] = {p, i + 1}; } } int mav = -1, mivp = 1e9, u, v; for (int i = 0; i < 512; i++) { if (vec[i].first > 1e9) continue; for (int j = i + 1; j < 512; j++) { if (i == j || vec[j].first > 1e9) continue; int k = i | j; if (mav < cnt[k]) { mav = cnt[k]; mivp = vec[i].first + vec[j].first; u = vec[i].second; v = vec[j].second; } else if (mav == cnt[k] && mivp > vec[i].first + vec[j].first) { mivp = vec[i].first + vec[j].first; u = vec[i].second; v = vec[j].second; } } if (sec[i].first > 1e9) continue; if (mav < cnt[i]) { mav = cnt[i]; mivp = vec[i].first + sec[i].first; u = vec[i].second, v = sec[i].second; } else if (mav == cnt[i] && mivp > vec[i].first + sec[i].first) { mivp = vec[i].first + sec[i].first; u = vec[i].second, v = sec[i].second; } } printf( %d %d , u, v); }
|
#include <bits/stdc++.h> using namespace std; const int N = 305, Q = (int)2e6 + 50; struct Qry { int x, y, c; void read() { cin >> x >> y >> c; x--, y--; } } qry[Q]; int n, m, q; int mp[N][N]; int f[N * N]; int dx[] = {0, 0, -1, 1}, dy[] = {1, -1, 0, 0}; int ch[Q], off[Q]; int ans[Q]; int gid(int i, int j) { return i * m + j; } int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } bool unite(int x, int y) { x = find(x); y = find(y); if (x == y) return false; f[x] = y; return true; } int build(int val, int ig) { for (int k = 0; k < n * m; k++) { f[k] = k; } for (int ki = 0; ki < n; ki++) { for (int kj = 0; kj < m; kj++) { if (ig != -1 && (!((mp[ki][kj] == val) ^ ig))) continue; if (ki + 1 < n && mp[ki + 1][kj] == mp[ki][kj]) unite(gid(ki + 1, kj), gid(ki, kj)); if (kj + 1 < m && mp[ki][kj + 1] == mp[ki][kj]) unite(gid(ki, kj + 1), gid(ki, kj)); } } int ccnt = 0; for (int k = 0; k < n * m; k++) ccnt += (f[k] == k); return ccnt; } bool in_bound(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> q; for (int i = 0; i < q; i++) qry[i].read(); int r = 0; for (int i = 0; i < q; i = r) { while (r < q && qry[r].c == qry[i].c) r++; build(qry[i].c, 0); int cur = 0; for (int j = i; j < r; j++) { int x = qry[j].x, y = qry[j].y; ch[j] = mp[x][y]; if (mp[x][y] != qry[j].c) cur++; mp[x][y] = qry[j].c; for (int d = 0; d < 4; d++) { int nx = x + dx[d], ny = y + dy[d]; if (in_bound(nx, ny) && mp[x][y] == mp[nx][ny]) { if (unite(gid(x, y), gid(nx, ny))) cur--; } } off[j] += cur; } cur = 0; build(qry[i].c, 1); for (int j = r - 1; j >= i; j--) { off[j] += cur; int x = qry[j].x, y = qry[j].y; if (mp[x][y] != ch[j]) { cur++; mp[x][y] = ch[j]; for (int d = 0; d < 4; d++) { int nx = x + dx[d], ny = y + dy[d]; if (in_bound(nx, ny) && mp[x][y] == mp[nx][ny]) { if (unite(gid(x, y), gid(nx, ny))) cur--; } } } } int ccnt = build(qry[i].c, -1); for (int j = i; j < r; j++) { ans[j] = ccnt - cur + off[j]; } for (int j = i; j < r; j++) { int x = qry[j].x, y = qry[j].y; mp[x][y] = qry[j].c; } } for (int i = 0; i < q; i++) cout << ans[i] << n ; }
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module neo_f0(
input nRESET,
input nDIPRD0,
input nDIPRD1, // "IN3"
input nBITWD0,
input [7:0] DIPSW,
input [7:4] M68K_ADDR,
inout [7:0] M68K_DATA,
input SYSTEMB,
output [5:0] nSLOT,
output SLOTA, SLOTB, SLOTC,
output reg [2:0] LED_LATCH,
output reg [7:0] LED_DATA,
input RTC_DOUT, RTC_TP,
output RTC_DIN, RTC_CLK, RTC_STROBE
//output [3:0] EL_OUT,
//output [8:0] LED_OUT1,
//output [8:0] LED_OUT2
);
reg [2:0] REG_RTCCTRL;
reg [2:0] SLOTS;
assign RTC_DIN = REG_RTCCTRL[0];
assign RTC_CLK = REG_RTCCTRL[1];
assign RTC_STROBE = REG_RTCCTRL[2];
//PCB only:
//These might have to be positive logic to match clock polarity of used chips
//assign nLED_LATCH = (M68K_ADDR[6:4] == 3'b011) ? nBITWD0 : 1'b1;
//assign nLED_DATA = (M68K_ADDR[6:4] == 3'b100) ? nBITWD0 : 1'b1;
// REG_DIPSW $300001~?, odd bytes
// REG_SYSTYPE $300081~?, odd bytes TODO (Test switch and stuff... Neutral for now)
assign M68K_DATA = (nDIPRD0) ? 8'bzzzzzzzz :
(M68K_ADDR[7]) ? 8'b11000000 :
DIPSW;
// REG_STATUS_A $320001~?, odd bytes TODO
// nDIPRD1: Output IN300~IN304 to D0~D4, D5 ?, and CALTP/CALDOUT to D6/D7 TODO (Neutral switches + RTC ok for now)
assign M68K_DATA = (nDIPRD1) ? 8'bzzzzzzzz :
{RTC_DOUT, RTC_TP, 1'b1, 5'b11111};
always @(nRESET, nBITWD0)
begin
if (!nRESET)
begin
SLOTS <= 3'b000;
REG_RTCCTRL <= 3'b000;
end
else if (!nBITWD0)
begin
// DEBUG
if (M68K_ADDR[6:4] == 3'b010)
$display("SELECT SLOT %d", M68K_DATA[2:0]);
else if (M68K_ADDR[6:4] == 3'b011)
$display("SET LED LATCHES to %b", M68K_DATA[5:3]);
else if (M68K_ADDR[6:4] == 3'b100)
$display("SET LED DATA to %b", M68K_DATA[7:0]);
else if (M68K_ADDR[6:4] == 3'b101)
$display("SET RTCCTRL to %b", M68K_DATA[2:0]);
case (M68K_ADDR[6:4])
3'b010:
SLOTS <= M68K_DATA[2:0]; // REG_SLOT $380021
3'b011:
LED_LATCH <= M68K_DATA[5:3]; // REG_LEDLATCHES $380031
3'b100:
LED_DATA <= M68K_DATA[7:0]; // REG_LEDDATA $380041
3'b101:
REG_RTCCTRL <= M68K_DATA[2:0]; // REG_RTCCTRL $380051
endcase
end
end
assign {SLOTC, SLOTB, SLOTA} = SYSTEMB ? SLOTS : 3'b000; // Maybe not
// TODO: check this
assign nSLOT = SYSTEMB ?
(SLOTS == 3'b000) ? 6'b111110 :
(SLOTS == 3'b001) ? 6'b111101 :
(SLOTS == 3'b010) ? 6'b111011 :
(SLOTS == 3'b011) ? 6'b110111 :
(SLOTS == 3'b100) ? 6'b101111 :
(SLOTS == 3'b101) ? 6'b011111 :
6'b111111 : // Invalid
6'b111111 ; // All slots disabled
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_2_V
`define SKY130_FD_SC_MS__O31A_2_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31a_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by ____YOUR_NAME_HERE____.
// SPDX-License-Identifier: CC0-1.0
module t #
(
parameter PIPE = 4
)(/*AUTOARG*/
// Inputs
clk
);
input clk;
// These are ok
sub #(
.P_STOP (1)
) u_sub1 ();
sub #(
.P_STOP (0)
) u_sub0 ();
genvar i;
for (i = -1; i < 1; i++) begin: SUB_PIPE
sub #(
.P_STOP (i)
) u_sub ();
end
always @ (posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub #
(
parameter P_START = 1,
parameter P_STOP = 0
)(
);
initial begin
for (int i = P_START; i >= P_STOP; --i) begin
$display("%m %0d..%0d i=%0d", P_START, P_STOP, i);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = pow(10, 9) + 7; int main() { ios_base::sync_with_stdio(false); int k; cin >> k; string s; cin >> s; int n = s.length(); int l = 0, r = 0; long long ans = 0LL; long long count1 = 0; while (l < n && k != 0) { long long countL = 0, countr = 0; bool found = false; while (r < n) { if (s[r] == 1 ) count1++; r++; if (count1 == k) { found = true; break; } } while (r < n && s[r] != 1 ) { countr++; r++; } while (l < n && s[l] != 1 ) { countL++; l++; } if (found) ans += (countL + 1) * (countr + 1); count1--; l++; } long long z = 0LL; if (k == 0) { for (int i = 0; i < n; i++) { if (s[i] == 0 ) z++; else { ans += (z * (z + 1)) / 2; z = 0; } } } cout << (ans + (z * (z + 1)) / 2); cout << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_BEHAVIORAL_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module read data from the Audio ADC on the Altera DE1 board. *
* *
******************************************************************************/
module Altera_UP_Audio_In_Deserializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
done_channel_sync,
serial_audio_in_data,
read_left_audio_data_en,
read_right_audio_data_en,
// Bidirectionals
// Outputs
left_audio_fifo_read_space,
right_audio_fifo_read_space,
left_channel_data,
right_channel_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 16;
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input done_channel_sync;
input serial_audio_in_data;
input read_left_audio_data_en;
input read_right_audio_data_en;
// Bidirectionals
// Outputs
output reg [7:0] left_audio_fifo_read_space;
output reg [7:0] right_audio_fifo_read_space;
output [AUDIO_DATA_WIDTH:1] left_channel_data;
output [AUDIO_DATA_WIDTH:1] right_channel_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire valid_audio_input;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [6:0] left_channel_fifo_used;
wire [6:0] right_channel_fifo_used;
// Internal Registers
reg [AUDIO_DATA_WIDTH:1] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_audio_fifo_read_space <= 8'h00;
else
begin
left_audio_fifo_read_space[7] <= left_channel_fifo_is_full;
left_audio_fifo_read_space[6:0] <= left_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_audio_fifo_read_space <= 8'h00;
else
begin
right_audio_fifo_read_space[7] <= right_channel_fifo_is_full;
right_audio_fifo_read_space[6:0] <= right_channel_fifo_used;
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_in_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (bit_clk_rising_edge & valid_audio_input)
data_in_shift_reg <=
{data_in_shift_reg[(AUDIO_DATA_WIDTH - 1):1],
serial_audio_in_data};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_Audio_Bit_Counter Audio_Out_Bit_Counter (
// Inputs
.clk (clk),
.reset (reset),
.bit_clk_rising_edge (bit_clk_rising_edge),
.bit_clk_falling_edge (bit_clk_falling_edge),
.left_right_clk_rising_edge (left_right_clk_rising_edge),
.left_right_clk_falling_edge (left_right_clk_falling_edge),
// Bidirectionals
// Outputs
.counting (valid_audio_input)
);
defparam
Audio_Out_Bit_Counter.BIT_COUNTER_INIT = BIT_COUNTER_INIT;
Altera_UP_SYNC_FIFO Audio_In_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_falling_edge & ~left_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_left_audio_data_en & ~left_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_data)
);
defparam
Audio_In_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Left_Channel_FIFO.ADDR_WIDTH = 7;
Altera_UP_SYNC_FIFO Audio_In_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_right_clk_rising_edge & ~right_channel_fifo_is_full & done_channel_sync),
.write_data (data_in_shift_reg),
.read_en (read_right_audio_data_en & ~right_channel_fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_data)
);
defparam
Audio_In_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_In_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_In_Right_Channel_FIFO.ADDR_WIDTH = 7;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; int n; int main() { scanf( %d , &n); if (n <= 8) { int a = 2; int b = (n) / a; int c = (n) % a; for (int i = 1; i <= n;) { if (c > 0) { printf( %d , c); c--; i++; } else if (c == 0) { for (int j = a - 1; j >= 0; j--) { printf( %d , i + j); } i += a; } } } else { int a; for (a = 3; a <= 1000; a++) { if (a * a > n) break; } a--; int b = (n) / a; int c = n % a; for (int i = 1; i <= n;) { if (c > 0) { printf( %d , c); c--; i++; } else if (c == 0) { for (int j = a - 1; j >= 0; j--) { printf( %d , i + j); } i += a; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve(); int main(int argc, const char** argv) { int t = 1; cin >> t; while (bool(t--)) { solve(); cout << n ; } } void solve() { vector<int> v(3); int s = 0; for (int i = 0; i < 3; i++) { cin >> v[i]; s += v[i]; } sort(v.begin(), v.end()); if (v[1] == v[0]) { if (v[2] % 2 != 0) { cout << NO ; return; } else { cout << YES ; return; } } if (v[2] != v[1]) { if (s != 2 * v[2]) { cout << NO ; return; } else { cout << YES ; return; } } else { if (v[0] % 2 != 0) { cout << NO ; return; } else { cout << YES ; return; } } }
|
#include <bits/stdc++.h> using namespace std; const long long M = 998244353; long long f[300005]; vector<long long> m1[300005], m2[300005]; int32_t main() { std::ios::sync_with_stdio(0); std::cin.tie(0); ; long long n; cin >> n; for (long long i = 0; i < n; i++) { long long x, y; cin >> x >> y; m1[x].push_back(y); m2[y].push_back(x); } f[0] = 1; for (long long i = 1; i < 300005; i++) f[i] = f[i - 1] * i % M; long long ans = f[n], d1 = 1, d2 = 1, d3 = 1; for (long long i = 1; i <= n; i++) d1 = d1 * f[m1[i].size()] % M; for (long long i = 1; i <= n; i++) d2 = d2 * f[m2[i].size()] % M; ans = ((ans - d1 - d2) % M + M) % M; vector<long long> a, b; for (long long i = 1; i <= n; i++) { if (m1[i].size() == 0) continue; sort((m1[i]).begin(), (m1[i]).end()); map<long long, long long> m; for (long long e : m1[i]) m[e]++; for (pair<long long, long long> p : m) d3 = d3 * f[p.second] % M; a.push_back(i); b.push_back(m1[i][0]); b.push_back(m1[i].back()); } for (long long i = 0; i < a.size() - 1; i++) if (a[i + 1] < a[i]) d3 = 0; for (long long i = 0; i < b.size() - 1; i++) if (b[i + 1] < b[i]) d3 = 0; ans = (ans + d3) % M; cout << ans << n ; }
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// reset generator
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module resetter(
clk,
rst_in_n,
rst_out_n );
parameter RST_CNT_SIZE = 4;
input clk;
input rst_in_n; // input of external asynchronous reset
output rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
reg rst_out_n;
reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
reg rst1_n,rst2_n;
`ifdef SIMULATE
initial
begin
rst_cnt = 0;
rst1_n = 1'b0;
rst2_n = 1'b0;
rst_out_n = 1'b0;
end
`endif
always @(posedge clk, negedge rst_in_n)
if( !rst_in_n ) // external asynchronous reset
begin
rst_cnt <= 0;
rst1_n <= 1'b0;
rst2_n <= 1'b0;
rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
end
else // clocking
begin
rst1_n <= 1'b1;
rst2_n <= rst1_n;
if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
begin
rst_cnt <= rst_cnt + 1;
end
if( rst_cnt[RST_CNT_SIZE] )
begin
rst_out_n <= 1'b1;
end
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Simple printout of characters from the UART
// Only does 8N1, requires the baud clock
module uart_rx (input baudclk, input rxd);
reg [8:0] sr = 9'b0;
reg [3:0] baud_ctr = 4'b0;
/*
wire byteclk = baud_ctr[3];
reg rxd_d1 = 0;
always @(posedge baudclk)
rxd_d1 <= rxd;
always @(posedge baudclk)
if(rxd_d1 != rxd)
baud_ctr <= 0;
else
baud_ctr <= baud_ctr + 1;
*/
wire byteclk = baudclk;
always @(posedge byteclk)
sr <= { rxd, sr[8:1] };
reg [3:0] state = 0;
always @(posedge byteclk)
case(state)
0 :
if(~sr[8] & sr[7]) // found start bit
state <= 1;
1, 2, 3, 4, 5, 6, 7, 8 :
state <= state + 1;
9 :
begin
state <= 0;
$write("%c",sr[7:0]);
if(~sr[8])
$display("Error, no stop bit\n");
end
default :
state <= 0;
endcase // case(state)
endmodule // uart_rx
|
//////////////////////////////////////////////////////////////////////////////////
// AXI4MasterInterfaceReadChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4 master interface read channel
// Module Name: AXI4MasterInterfaceReadChannel
// File Name: AXI4MasterInterfaceReadChannel.v
//
// Version: v1.0.0
//
// Description: AXI4 compliant read channel control for master interface
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4MasterInterfaceReadChannel
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter MaxDivider = 16
)
(
ACLK ,
ARESETN ,
OUTER_ARADDR ,
OUTER_ARLEN ,
OUTER_ARSIZE ,
OUTER_ARBURST ,
OUTER_ARCACHE ,
OUTER_ARPROT ,
OUTER_ARVALID ,
OUTER_ARREADY ,
OUTER_RDATA ,
OUTER_RRESP ,
OUTER_RLAST ,
OUTER_RVALID ,
OUTER_RREADY ,
INNER_ARADDR ,
INNER_ARLEN ,
INNER_ARVALID ,
INNER_ARREADY ,
INNER_RDATA ,
INNER_RLAST ,
INNER_RVALID ,
INNER_RREADY
);
input ACLK ;
input ARESETN ;
output [AddressWidth - 1:0] OUTER_ARADDR ;
output [7:0] OUTER_ARLEN ;
output [2:0] OUTER_ARSIZE ;
output [1:0] OUTER_ARBURST ;
output [3:0] OUTER_ARCACHE ;
output [2:0] OUTER_ARPROT ;
output OUTER_ARVALID ;
input OUTER_ARREADY ;
input [DataWidth - 1:0] OUTER_RDATA ;
input [1:0] OUTER_RRESP ;
input OUTER_RLAST ;
input OUTER_RVALID ;
output OUTER_RREADY ;
input [AddressWidth - 1:0] INNER_ARADDR ;
input [InnerIFLengthWidth - 1:0] INNER_ARLEN ;
input INNER_ARVALID ;
output INNER_ARREADY ;
output [DataWidth - 1:0] INNER_RDATA ;
output INNER_RLAST ;
output INNER_RVALID ;
input INNER_RREADY ;
wire [AddressWidth - 1:0] wDivAddress ;
wire [7:0] wDivLength ;
wire wDivValid ;
wire wDivReady ;
wire wDivFlush ;
wire wRCmdQPopSignal ;
wire wIsRCmdQFull ;
wire wIsRCmdQEmpty ;
wire [AddressWidth - 1:0] wQdDivAddress ;
wire [7:0] wQdDivLength ;
wire wQdDivValid ;
wire wQdDivReady ;
wire wDivReadyCond ;
wire wIsRLenQFull ;
wire wIsRLenQEmpty ;
AXI4CommandDivider
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.MaxDivider (MaxDivider )
)
Inst_AXI4ReadCommandDivider
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.SRCADDR (INNER_ARADDR ),
.SRCLEN (INNER_ARLEN ),
.SRCVALID (INNER_ARVALID ),
.SRCREADY (INNER_ARREADY ),
.SRCREADYCOND (!wIsRLenQFull ),
.DIVADDR (wDivAddress ),
.DIVLEN (wDivLength ),
.DIVVALID (wDivValid ),
.DIVREADY (wDivReady ),
.DIVFLUSH (wDivFlush )
);
assign wDivReady = !wIsRCmdQFull;
SCFIFO_80x64_withCount
Inst_AXI4ReadCommandQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData ({wDivAddress, wDivLength} ),
.iPushEnable (wDivValid & wDivReady ),
.oIsFull (wIsRCmdQFull ),
.oPopData ({wQdDivAddress, wQdDivLength} ),
.iPopEnable (wRCmdQPopSignal ),
.oIsEmpty (wIsRCmdQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4ReadCommandQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wRCmdQPopSignal),
.iEmpty (wIsRCmdQEmpty ),
.oValid (wQdDivValid ),
.iReady (wQdDivReady )
);
AXI4CommandDriver
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth )
)
Inst_AXI4ReadCommandDriver
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.AXADDR (OUTER_ARADDR ),
.AXLEN (OUTER_ARLEN ),
.AXSIZE (OUTER_ARSIZE ),
.AXBURST (OUTER_ARBURST ),
.AXCACHE (OUTER_ARCACHE ),
.AXPROT (OUTER_ARPROT ),
.AXVALID (OUTER_ARVALID ),
.AXREADY (OUTER_ARREADY ),
.SRCADDR (wQdDivAddress ),
.SRCLEN (wQdDivLength ),
.SRCVALID (wQdDivValid ),
.SRCREADY (wQdDivReady ),
.SRCFLUSH (wDivFlush ),
.SRCREADYCOND (1'b1 )
);
wire [InnerIFLengthWidth - 1:0] wQdRLen ;
wire wRLenQPopSignal ;
wire wQdRLenValid ;
wire wQdRLenReady ;
assign wDivReadyCond = !wIsRLenQFull;
SCFIFO_40x64_withCount
Inst_AXI4ReadLengthQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData (INNER_ARLEN - 1 ),
.iPushEnable (INNER_ARVALID && INNER_ARREADY && (INNER_ARLEN != 0) ),
.oIsFull (wIsRLenQFull ),
.oPopData (wQdRLen ),
.iPopEnable (wRLenQPopSignal ),
.oIsEmpty (wIsRLenQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4ReadLengthQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wRLenQPopSignal),
.iEmpty (wIsRLenQEmpty ),
.oValid (wQdRLenValid ),
.iReady (wQdRLenReady )
);
wire [DataWidth - 1:0] wQdRData ;
wire wIsRDataQFull ;
wire wIsRDataQEmpty ;
wire wRDataQPopSignal;
wire wQdRDataValid ;
wire wQdRDataReady ;
assign OUTER_RREADY = !wIsRDataQFull;
SCFIFO_64x64_withCount
Inst_AXI4ReadDataQ
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.iPushData (OUTER_RDATA ),
.iPushEnable (OUTER_RVALID && OUTER_RREADY ),
.oIsFull (wIsRDataQFull ),
.oPopData (wQdRData ),
.iPopEnable (wRDataQPopSignal ),
.oIsEmpty (wIsRDataQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_AXI4ReadDataQPopControl
(
.iClock (ACLK ),
.iReset (!ARESETN ),
.oPopSignal (wRDataQPopSignal ),
.iEmpty (wIsRDataQEmpty ),
.oValid (wQdRDataValid ),
.iReady (wQdRDataReady )
);
AXI4DataDriver
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.LengthWidth (InnerIFLengthWidth )
)
Inst_AXI4ReadDataDriver
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.SRCLEN (wQdRLen ),
.SRCVALID (wQdRLenValid ),
.SRCREADY (wQdRLenReady ),
.DATA (wQdRData ),
.DVALID (wQdRDataValid ),
.DREADY (wQdRDataReady ),
.XDATA (INNER_RDATA ),
.XDVALID (INNER_RVALID ),
.XDREADY (INNER_RREADY ),
.XDLAST (INNER_RLAST )
);
assign OUTER_WSTRB = {(DataWidth/8){1'b1}};
endmodule
|
`timescale 1ns / 1ps
`define intN 8
`define addrN 8
`include "primitives.v"
`include "io_stream_read_array.v"
`include "array.v"
module io_stream_read_array_tb;
`wire(Array, (`addrN, `intN), arr);
`reg(stream, `intN, sIn);
`wire(stream, `intN, sOut);
assign sOut_ready = out_ready;
`testbench(io_stream_read_array_tb, 100)
array array(.clk(clk),
`out(Array, 0, arr));
`in_ready(inst);
`inst_sync(io_stream_read_array, inst, #())(
`sync(in_valid, out_ready),
`in(Array, 0, arr),
`in(stream, 1, sIn),
`out(stream, 0, sOut));
initial begin
`start;
sIn = 0;
sIn_valid = `true;
end
always @(posedge clk) begin
if(sIn_ready & sIn_valid) begin
sIn <= (sIn + 1) % 16;
end
if(sOut_valid) begin
$display("out0 = %d", sOut);
if(sOut == 15) begin
$display("done");
$finish;
end
end
end
endmodule // io_stream_read_array_tb
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/19 09:26:57
// Design Name: INST_MEM
// Module Name: INST_MEM
// Project Name: MIPS_CPU
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module INST_MEM(
input[31:0] a,
output[31:0] inst_out );
wire[31:0] rom[0:31];
assign rom[5'h0] = 32'h3c010000;
assign rom[5'h1] = 32'h34240050;
assign rom[5'h2] = 32'h20050004;
assign rom[5'h3] = 32'h0c000018;
assign rom[5'h4] = 32'hac820000;
assign rom[5'h5] = 32'h8c890000;
assign rom[5'h6] = 32'h01244022;
assign rom[5'h7] = 32'h20050003;
assign rom[5'h8] = 32'h20a5ffff;
assign rom[5'h9] = 32'h34a8ffff;
assign rom[5'ha] = 32'h39085555;
assign rom[5'hb] = 32'h2009ffff;
assign rom[5'hc] = 32'h3124ffff;
assign rom[5'hd] = 32'h01493025;
assign rom[5'he] = 32'h01494026;
assign rom[5'hf] = 32'h01463824;
assign rom[5'h10] = 32'h10a00001;
assign rom[5'h11] = 32'h08000008;
assign rom[5'h12] = 32'h2005ffff;
assign rom[5'h13] = 32'h000543c0;
assign rom[5'h14] = 32'h00084400;
assign rom[5'h15] = 32'h00084403;
assign rom[5'h16] = 32'h000843c2;
assign rom[5'h17] = 32'h08000017;
assign rom[5'h18] = 32'h00004020;
assign rom[5'h19] = 32'h8c890000;
assign rom[5'h1a] = 32'h20840004;
assign rom[5'h1b] = 32'h01094020;
assign rom[5'h1c] = 32'h20a5ffff;
assign rom[5'h1d] = 32'h14a0fffb;
assign rom[5'h1e] = 32'h00081000;
assign rom[5'h1f] = 32'h03e00008;
assign inst_out = rom[a[6:2]];
endmodule
|
// megafunction wizard: %ALTTEMP_SENSE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTTEMP_SENSE
// ============================================================
// File Name: temp_sense.v
// Megafunction Name(s):
// ALTTEMP_SENSE
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alttemp_sense CBX_AUTO_BLACKBOX="ALL" CLK_FREQUENCY="50.0" CLOCK_DIVIDER_ENABLE="on" CLOCK_DIVIDER_VALUE=80 DEVICE_FAMILY="Stratix V" NUMBER_OF_SAMPLES=128 POI_CAL_TEMPERATURE=85 SIM_TSDCALO=0 USE_WYS="on" USER_OFFSET_ENABLE="off" ce clk clr tsdcaldone tsdcalo ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 12.0SP2 cbx_alttemp_sense 2012:08:02:15:11:11:SJ cbx_cycloneii 2012:08:02:15:11:11:SJ cbx_lpm_add_sub 2012:08:02:15:11:11:SJ cbx_lpm_compare 2012:08:02:15:11:11:SJ cbx_lpm_counter 2012:08:02:15:11:11:SJ cbx_lpm_decode 2012:08:02:15:11:11:SJ cbx_mgl 2012:08:02:15:40:54:SJ cbx_stratix 2012:08:02:15:11:11:SJ cbx_stratixii 2012:08:02:15:11:11:SJ cbx_stratixiii 2012:08:02:15:11:11:SJ cbx_stratixv 2012:08:02:15:11:11:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = stratixv_tsdblock 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module temp_sense_alttemp_sense_v8t
(
ce,
clk,
clr,
tsdcaldone,
tsdcalo) /* synthesis synthesis_clearbox=2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ce;
tri0 clr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_sd1_tsdcaldone;
wire [7:0] wire_sd1_tsdcalo;
stratixv_tsdblock sd1
(
.ce(ce),
.clk(clk),
.clr(clr),
.tsdcaldone(wire_sd1_tsdcaldone),
.tsdcalo(wire_sd1_tsdcalo));
defparam
sd1.clock_divider_enable = "true",
sd1.clock_divider_value = 80,
sd1.sim_tsdcalo = 0,
sd1.lpm_type = "stratixv_tsdblock";
assign
tsdcaldone = wire_sd1_tsdcaldone,
tsdcalo = wire_sd1_tsdcalo;
endmodule //temp_sense_alttemp_sense_v8t
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module temp_sense (
ce,
clk,
clr,
tsdcaldone,
tsdcalo)/* synthesis synthesis_clearbox = 2 */;
input ce;
input clk;
input clr;
output tsdcaldone;
output [7:0] tsdcalo;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [7:0] tsdcalo = sub_wire0[7:0];
wire tsdcaldone = sub_wire1;
temp_sense_alttemp_sense_v8t temp_sense_alttemp_sense_v8t_component (
.ce (ce),
.clk (clk),
.clr (clr),
.tsdcalo (sub_wire0),
.tsdcaldone (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = ALTTEMP_SENSE
clearbox_defparam = "clk_frequency=50.0;clock_divider_enable=ON;clock_divider_value=80;intended_device_family=Stratix V;lpm_hint=UNUSED;lpm_type=alttemp_sense;number_of_samples=128;poi_cal_temperature=85;sim_tsdcalo=0;user_offset_enable=off;use_wys=on;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: CLK_FREQUENCY STRING "50.0"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_ENABLE STRING "ON"
// Retrieval info: CONSTANT: CLOCK_DIVIDER_VALUE NUMERIC "80"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alttemp_sense"
// Retrieval info: CONSTANT: NUMBER_OF_SAMPLES NUMERIC "128"
// Retrieval info: CONSTANT: POI_CAL_TEMPERATURE NUMERIC "85"
// Retrieval info: CONSTANT: SIM_TSDCALO NUMERIC "0"
// Retrieval info: CONSTANT: USER_OFFSET_ENABLE STRING "off"
// Retrieval info: CONSTANT: USE_WYS STRING "on"
// Retrieval info: USED_PORT: ce 0 0 0 0 INPUT NODEFVAL "ce"
// Retrieval info: CONNECT: @ce 0 0 0 0 ce 0 0 0 0
// Retrieval info: USED_PORT: clk 0 0 0 0 INPUT NODEFVAL "clk"
// Retrieval info: CONNECT: @clk 0 0 0 0 clk 0 0 0 0
// Retrieval info: USED_PORT: clr 0 0 0 0 INPUT NODEFVAL "clr"
// Retrieval info: CONNECT: @clr 0 0 0 0 clr 0 0 0 0
// Retrieval info: USED_PORT: tsdcaldone 0 0 0 0 OUTPUT NODEFVAL "tsdcaldone"
// Retrieval info: CONNECT: tsdcaldone 0 0 0 0 @tsdcaldone 0 0 0 0
// Retrieval info: USED_PORT: tsdcalo 0 0 8 0 OUTPUT NODEFVAL "tsdcalo[7..0]"
// Retrieval info: CONNECT: tsdcalo 0 0 8 0 @tsdcalo 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL temp_sense.cmp FALSE TRUE
|
#include <bits/stdc++.h> using namespace std; bool q[2][1001]; short qf[3][1001], an[1001][1001][50][2]; inline short gt(int l, int r, int p) { return qf[p][r] - qf[p][l - 1]; } int main() { int n, p, k; scanf( %d%d%d , &n, &p, &k); for (int i = 0; i < (int)(2); ++i) { int t; scanf( %d , &t); while (t--) { int t; scanf( %d , &t); q[i][t] = true; } } for (int i = 1; i < (int)(n + 1); ++i) { qf[0][i] = qf[0][i - 1] + q[0][i]; qf[1][i] = qf[1][i - 1] + q[1][i]; qf[2][i] = qf[2][i - 1] + (q[0][i] || q[1][i]); } for (int i = 0; i < (int)(p + 1); ++i) for (int j = 0; j < (int)(n + 1); ++j) for (int w = 0; w < (int)(k); ++w) for (int c = 0; c < (int)(2); ++c) an[i][j][w][c] = -2000; for (int l = 0; l < (int)(p + 1); ++l) for (int i = 0; i < (int)(n + 1); ++i) an[l][i][0][0] = an[l][i][0][1] = 0; for (int l = 1; l < (int)(p + 1); ++l) for (int i = 1; i < (int)(n + 1); ++i) for (int j = 0; j < (int)(min(k, i + 1)); ++j) for (int c = 0; c < (int)(2); ++c) { short &a = an[l][i][j][c]; if (j) a = gt(i, i, c) + an[l - (j == 1)][i - 1][j - 1][c]; else { for (int z = 1; z < (int)(k); ++z) a = max(a, (short)(gt(i, i, c) + an[l][i - 1][z][c])); a = max(a, an[l][i - 1][0][c]); } if (j > 1) a = max(a, an[l][i][j - 1][c]); for (int z = 0; z < (int)(2); ++z) a = max(a, (short)(gt(i, i, c) + an[l - 1][i - 1][0][z])); a = max(a, (short)(gt(i - j + 1, i, 2) + an[l - 1][i - j][j ? k - j : 0][c ^ 1])); } short a = 0; for (int i = 0; i < (int)(k); ++i) for (int j = 0; j < (int)(2); ++j) a = max(a, an[p][n][i][j]); printf( %u n , a); }
|
#include <bits/stdc++.h> using ll = long long; const ll maxn = 1234; const ll inf = 1e9 + 7; int main(int argc, char *argv[]) { ll n, m, a[maxn]; std::cin >> n >> m; ll cur = 0, maxx = 0, minn = 0; for (int i = 0; i < n; i++) { std::cin >> a[i]; cur += a[i]; maxx = std::max(maxx, cur); minn = std::min(minn, cur); } ll ans = maxx - minn; if (maxx - minn > m) { std::cout << 0; } else { std::cout << m - (maxx - minn) + 1; } }
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma,sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; long long MOD = 1e9 + 7; long long k; vector<long long> v, w, num; vector<pair<long long, pair<long long, long long> > > zp; vector<vector<long long> > dp; long long st(long long t, long long id, long long mod) { long long res = 1, a = t, n = id; while (n) { if (n & 1) res = (res * a) % mod; a = (a * a) % mod; n >>= 1; } return res % mod; } void add(long long id) { vector<long long> mem(k + 1); dp.push_back(mem); long long lst = dp.size() - 1; for (int i = 0; i < k + 1; i++) { dp[lst][i] = dp[lst - 1][i]; if (i >= w[id]) dp[lst][i] = max(dp[lst - 1][i], dp[lst - 1][i - w[id]] + v[id]); } } void del() { dp.pop_back(); } long long ans() { long long lst = dp.size() - 1; long long anss = 0; for (int i = 1; i < k + 1; i++) { anss = ((10000019 * (long long)anss) + (long long)dp[lst][k - i + 1]) % MOD; if (anss > MOD) anss -= MOD; } return anss; } void get(long long l, long long r) { if (r == l + 1) { if (zp[l].first == 3) { zp[l].second.first = ans(); } return; } long long mid = (l + r) / 2; long long kol = 0; for (int i = mid; i < r; i++) { if (zp[i].first == 2) { if (num[zp[i].second.second] < l) { add(zp[i].second.second); kol++; } } } get(l, mid); while (kol--) del(); kol = 0; for (int i = l; i < mid; i++) { if (zp[i].first == 1) { if (zp[i].second.second >= r) { add(zp[i].second.first); kol++; } } } get(mid, r); while (kol--) del(); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0), cout << fixed << setprecision(20); long long n; cin >> n >> k; v.resize(n), w.resize(n), num.resize(n); vector<long long> mem(k + 1); dp.push_back(mem); for (int i = 0; i < n; i++) { cin >> v[i] >> w[i]; zp.push_back({1, {i, MOD}}); num[i] = i; } long long q; cin >> q; while (q--) { long long sz = zp.size(); zp.push_back({0, {num.size(), MOD}}); cin >> zp[zp.size() - 1].first; if (zp.back().first == 1) { long long vv, ww; cin >> vv >> ww; v.push_back(vv); w.push_back(ww); num.push_back(sz); } if (zp.back().first == 2) { long long x; cin >> x; x--; zp[num[x]].second.second = sz; zp[sz].second.second = x; } } get(0, zp.size()); for (auto i : zp) { if (i.first == 3) { cout << i.second.first << endl; } } }
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#include <bits/stdc++.h> int main() { int n, x = 0; char arra[10]; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , arra); if (arra[0] == + || arra[1] == + ) x = x + 1; else if (arra[0] == - || arra[1] == - ) x = x - 1; } printf( %d n , x); }
|
#include <bits/stdc++.h> using namespace std; char buf[25]; const int maxn = 1000010; int a[maxn * 2], b[maxn * 2]; int n, m, x, y, t, mx; int read() { int x = 0, f = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = 1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return f ? -x : x; } void write(int x) { if (!x) { putchar( 0 ); return; } if (x < 0) { putchar( - ); x = -x; } int cnt = 0; while (x) { buf[++cnt] = 0 + x % 10; x /= 10; } for (int i = cnt; i >= 1; --i) putchar(buf[i]); } int main() { t = read(); for (int i = 1; i <= t; ++i) { int v = read(); mx = max(mx, v); ++a[v]; } int x = 1; for (int i = 1; i <= mx; ++i) if (a[i] != i * 4) { x = i; break; } for (int i = x * 2 - 1; i <= t; ++i) if (t % i == 0) { n = i; m = t / i; y = n + m - x - mx; if (y <= 0 || y * 2 - 1 > m) continue; bool flag = true; int t1 = 0, t2 = 0; for (int j = 1; j <= n; ++j) { bool f = true; for (int k = 1; k <= m; ++k) { t1 = j; t2 = k; int tmp = abs(j - x) + abs(k - y); ++b[tmp]; if (b[tmp] > a[tmp]) { flag = false; f = false; break; } } if (!f) break; } for (int j = 1; j <= n; ++j) { bool f = true; for (int k = 1; k <= m; ++k) { int tmp = abs(j - x) + abs(k - y); --b[tmp]; if (j == t1 && k == t2) { f = false; break; } } if (!f) break; } if (flag) { write(n); putchar( ); write(m); putchar( n ); write(x); putchar( ); write(y); putchar( n ); return 0; } } write(-1); putchar( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; const int mxn = 2e5 + 5; long long a[1001][1001]; int main() { int t; cin >> t; while (t--) { int n, m; cin >> n >> m; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cin >> a[i][j]; if ((i + j) & 1 && !(a[i][j] & 1)) ++a[i][j]; else if (!((i + j) & 1) && a[i][j] & 1) ++a[i][j]; cout << a[i][j] << ; } cout << endl; } } }
|
#include<bits/stdc++.h> // #define int long long #define ld long double #define fi first #define se second #define vll vector<int> #define pii pair<int,int> #define pb push_back #define sz(v) (int)(v).size() #define inf (int)(1e8) #define md (int)(1e9+7) #define all(v) (v).begin(),(v).end() #define rep(i,a,b) for(int i=a;i<b;++i) using namespace std; const int M = 50 + 11; const int K = 251; int n; string s; int dp[2][M][K][K]; /* int f(int i,int car,int pos,int neg) { if(pos<0 or neg<0 or car+30>=M or car+30<0) return inf; if(i>=n) return car?inf:0; if(dp[i][car+30][pos][neg]!=-1) return dp[i][car+30][pos][neg]; int ans=min(f(i,car,pos-1,neg),f(i,car,pos,neg-1)); int now=s[i]- 0 ,tot=pos-neg+car; if((tot%10+10)%10==now) { ans=min(ans,f(i+1,tot/10+(tot>0?0:-1)*(bool)(tot%10),pos,neg)+pos+neg); } return dp[i][car+30][pos][neg]=ans; } */ int32_t main(){ ios_base::sync_with_stdio(false); cin.tie(0); cin>>s; reverse(all(s)); s+= 0 ; n=sz(s); rep(i,0,2)rep(car,0,M)rep(pos,0,K)rep(neg,0,K) dp[i][car][pos][neg]=inf; rep(pos,0,K)rep(neg,0,K) dp[0][0+M/2][pos][neg]=0; for(int i=n-1;i>=0;--i) { rep(car,-M/2,M/2+1)rep(pos,0,K)rep(neg,0,K) { int &ans=dp[1][car+M/2][pos][neg]; if(pos) ans=min(ans,dp[1][car+M/2][pos-1][neg]); if(neg) ans=min(ans,dp[1][car+M/2][pos][neg-1]); int now=s[i]- 0 ,tot=pos-neg+car; if((tot%10+10)%10==now) { int ncar=tot/10+(tot>0?0:-1)*(bool)(tot%10)+M/2; if(ncar<0 or ncar>=M) continue; ans=min(ans,dp[0][ncar][pos][neg]+pos+neg); } } rep(car,-M/2,M/2+1)rep(pos,0,K)rep(neg,0,K) { dp[0][car+M/2][pos][neg]=dp[1][car+M/2][pos][neg]; dp[1][car+M/2][pos][neg]=inf; } } cout<<dp[0][0+M/2][K-1][K-1]; /* memset(dp,-1,sizeof(dp)); cout<<f(0,0,K-1,K-1); */ return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int N = 300100; int arr[N]; #pragma warning(disable : 6031) #pragma warning(disable : 4996) int t, n; bool c1[N], c2[N]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); bool f1 = 1, f2 = 1; bool f3 = 1; for (int i = 1; i <= n; i++) scanf( %d , arr + i); memset(c1, 0, sizeof c1); memset(c2, 0, sizeof c2); c1[1] = 1; for (int i = 2; i <= n; i++) { if (c1[i - 1] && arr[i] >= i - 1) { c1[i] = 1; } else { break; } } c2[n] = 1; for (int i = n - 1; i >= 1; i--) { if (c2[i + 1] && arr[i] >= n - i) { c2[i] = 1; } else break; } f1 = c1[n]; f2 = c2[1]; f3 = 0; for (int i = 1; i <= n; i++) { if (c1[i] && c2[i]) { f3 = 1; } } if (f1 || f2 || f3) puts( Yes ); else puts( No ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_1_V
`define SKY130_FD_SC_LS__NAND4BB_1_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_1 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4bb_1 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_1_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void maxtt(T& t1, T t2) { t1 = max(t1, t2); } template <typename T> void mintt(T& t1, T t2) { t1 = min(t1, t2); } bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = URDL ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int& x, int y, int mod = 998244353) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et(int x = -1) { printf( %d n , x); exit(0); } long long fastPow(long long x, long long y, int mod = 998244353) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { return y ? gcd1(y, x % y) : x; } vector<int> mp[200135]; int d[200135], tar; vector<int> dp[200135]; pair<int, int> tmp; void dfs(int x, int pa) { d[x] = d[pa] + 1; dp[x].clear(); for (int c : mp[x]) if (c != pa) { dfs(c, x); int v = dp[c][0]; if (dp[x].size() <= 1) { dp[x].push_back(v); if (dp[x].size() == 2 && d[dp[x][0]] < d[dp[x][1]]) { swap(dp[x][0], dp[x][1]); } } else if (d[v] > d[dp[x][0]]) { dp[x][1] = dp[x][0]; dp[x][0] = v; } else if (d[v] > d[dp[x][1]]) { dp[x][1] = v; } } if (dp[x].empty()) dp[x].push_back(x); if (dp[x].size() == 2) { pair<int, int> key = {d[x], d[dp[x][0]] + d[dp[x][1]]}; if (key > tmp) { tmp = key; tar = x; } } } void fmain(int tid) { scanf( %d , &n); for (int i = 0, u, v; i < n - 1; i++) { scanf( %d%d , &u, &v); mp[u].push_back(v); mp[v].push_back(u); }; tmp = {-1, -1}; dfs(1, 0); vector<int> ans(4); ans[0] = dp[tar][0]; ans[2] = dp[tar][1]; tmp = {-1, -1}; dfs(tar, 0); ans[1] = dp[tar][0]; ans[3] = dp[tar][1]; for (int(i) = 0; (i) < (int)(4); (i)++) printf( %d , ans[i]); } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_TB_V
`define SKY130_FD_SC_HS__SDFRBP_TB_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfrbp dut (.RESET_B(RESET_B), .D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1001; int dp2[MAX_N][MAX_N], dp5[MAX_N][MAX_N]; int n; string findPath(int (*p)[MAX_N]) { int i = n - 1, j = n - 1; string path = ; while (i != 0 && j != 0) { if (p[i - 1][j] > p[i][j - 1]) { path.insert(0, R ); j--; } else { path.insert(0, D ); i--; } } if (i == 0) { while (j != 0) { path.insert(0, R ); j--; } } else { while (i != 0) { path.insert(0, D ); i--; } } return path; } int main() { std::ios::sync_with_stdio(false); cin >> n; int temp1, temp2, zeroI = -1; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) { cin >> temp1; if (!temp1) { zeroI = i; continue; } temp2 = temp1; while (!(temp1 & 1)) { dp2[i][j]++; temp1 >>= 1; } while (!(temp2 % 5)) { dp5[i][j]++; temp2 /= 5; } } for (int i = 1; i < n; i++) { dp2[i][0] += dp2[i - 1][0]; dp5[i][0] += dp5[i - 1][0]; dp2[0][i] += dp2[0][i - 1]; dp5[0][i] += dp5[0][i - 1]; } for (int i = 1; i < n; i++) { for (int j = 1; j < n; j++) { dp2[i][j] += min(dp2[i - 1][j], dp2[i][j - 1]); dp5[i][j] += min(dp5[i - 1][j], dp5[i][j - 1]); } } int(*p)[MAX_N] = (dp2[n - 1][n - 1] < dp5[n - 1][n - 1]) ? dp2 : dp5; if ((~zeroI) && p[n - 1][n - 1] > 1) { cout << 1 << endl; for (int i = 0; i < zeroI; i++) cout << D << flush; for (int j = 1; j < n; j++) cout << R << flush; for (int i = zeroI + 1; i < n; i++) cout << D << flush; return 0; } else { cout << p[n - 1][n - 1] << endl; cout << findPath(p) << flush; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int mod = 1051131; const int Inv2 = (mod + 1) >> 1; inline void setIO(string a) {} long long Power; int m, s, n, nn; int a[(1 << 25) + 23]; void work(int n, int p, int q) { if (n == 1) { int &An = a[1]; (p += q) %= mod; for (long long c = Power; c; c >>= 1, p = 1ll * p * p % mod) if (c & 1) An = 1ll * An * p % mod; return; } int t = n >> 1, tt = 1ll * t * p % mod; int ttp = (p + q + mod - tt) % mod, tttp = 1; for (long long c = Power; c; c >>= 1, ttp = 1ll * ttp * ttp % mod) if (c & 1) tttp = 1ll * tttp * ttp % mod; int xi = (1ll * t * p % mod - p + q + mod) % mod; for (int i = (1); i <= (t); i++) { int A = a[i], B = a[i + t]; a[i] = (A + B) % mod; a[i + t] = (A + mod - B) % mod; a[i + t] = 1ll * a[i + t] * tttp % mod; } work(n >> 1, (p + p) % mod, xi); for (int i = (1); i <= (t); i++) { int A = a[i], B = a[i + t]; a[i] = (A + B) % mod; a[i + t] = (A + mod - B) % mod; a[i] = 1ll * a[i] * Inv2 % mod; a[i + t] = 1ll * a[i + t] * Inv2 % mod; } } int main() { scanf( %d , &m); cin >> Power; scanf( %d , &s); for (int i = (1); i <= (s); i++) scanf( %d , &a[i]); n = 1 << m; nn = n; for (int i = (s + 1); i <= (n); i++) a[i] = (101ll * a[i - s] + 10007) % 1051131; work(n, 1, 0); int ans = 0; for (int i = (1); i <= (n); i++) ans ^= a[i]; printf( %d n , ans); return 0; }
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtye4_delay_powergood # (
parameter C_USER_GTPOWERGOOD_DELAY_EN = 0,
parameter C_PCIE_ENABLE = "FALSE"
)(
input wire GT_TXOUTCLKPCS,
input wire GT_GTPOWERGOOD,
input wire [2:0] USER_TXRATE,
input wire USER_TXRATEMODE,
input wire USER_GTTXRESET,
input wire USER_TXPMARESET,
input wire USER_TXPISOPD,
output wire USER_GTPOWERGOOD,
output wire [2:0] GT_TXRATE,
output wire GT_TXRATEMODE,
output wire GT_GTTXRESET,
output wire GT_TXPMARESET,
output wire GT_TXPISOPD
);
generate if (C_PCIE_ENABLE || (C_USER_GTPOWERGOOD_DELAY_EN == 0))
begin : gen_powergood_nodelay
assign GT_TXPISOPD = USER_TXPISOPD;
assign GT_GTTXRESET = USER_GTTXRESET;
assign GT_TXPMARESET = USER_TXPMARESET;
assign GT_TXRATE = USER_TXRATE;
assign GT_TXRATEMODE = USER_TXRATEMODE;
assign USER_GTPOWERGOOD = GT_GTPOWERGOOD;
end
else
begin: gen_powergood_delay
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [4:0] intclk_rrst_n_r;
reg [3:0] wait_cnt;
(* KEEP = "TRUE" *) reg pwr_on_fsm = 1'b0;
wire intclk_rrst_n;
wire gt_intclk;
and and1(gt_intclk, GT_TXOUTCLKPCS, !pwr_on_fsm);
//--------------------------------------------------------------------------
// POWER ON FSM Encoding
//--------------------------------------------------------------------------
localparam PWR_ON_WAIT_CNT = 4'd0;
localparam PWR_ON_DONE = 4'd1;
//--------------------------------------------------------------------------------------------------
// Reset Synchronizer
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk or negedge GT_GTPOWERGOOD)
begin
if (!GT_GTPOWERGOOD)
intclk_rrst_n_r <= 5'd0;
else
intclk_rrst_n_r <= {intclk_rrst_n_r[3:0], 1'd1};
end
assign intclk_rrst_n = intclk_rrst_n_r[4];
//--------------------------------------------------------------------------------------------------
// Wait counter
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk)
begin
if (!intclk_rrst_n)
wait_cnt <= 4'd0;
else begin
if (pwr_on_fsm == PWR_ON_WAIT_CNT)
wait_cnt <= wait_cnt + 4'd1;
else
wait_cnt <= 4'd0;
end
end
//--------------------------------------------------------------------------------------------------
// Power On FSM
//--------------------------------------------------------------------------------------------------
always @ (posedge gt_intclk or negedge GT_GTPOWERGOOD)
begin
if (!GT_GTPOWERGOOD)
begin
pwr_on_fsm <= PWR_ON_WAIT_CNT;
end
else begin
case (pwr_on_fsm)
PWR_ON_WAIT_CNT :
begin
pwr_on_fsm <= (wait_cnt[3] == 1'b1) ? PWR_ON_DONE : PWR_ON_WAIT_CNT;
end
PWR_ON_DONE :
begin
pwr_on_fsm <= PWR_ON_DONE;
end
default :
begin
pwr_on_fsm <= PWR_ON_WAIT_CNT;
end
endcase
end
end
assign GT_TXPISOPD = pwr_on_fsm ? USER_TXPISOPD : 1'b1;
assign GT_GTTXRESET = pwr_on_fsm ? USER_GTTXRESET : !GT_GTPOWERGOOD;
assign GT_TXPMARESET = pwr_on_fsm ? USER_TXPMARESET : 1'b0;
assign GT_TXRATE = pwr_on_fsm ? USER_TXRATE : 3'b001;
assign GT_TXRATEMODE = pwr_on_fsm ? USER_TXRATEMODE : 1'b1;
assign USER_GTPOWERGOOD = pwr_on_fsm;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3fffffff; const int SINF = 0x7fffffff; const long long LINF = 0x3fffffffffffffff; const long long SLINF = 0x7fffffffffffffff; const int MAXN = 2007; int n, m; vector<int> es[MAXN]; bitset<MAXN> bs[MAXN]; bool hv[MAXN]; int dp[MAXN]; void init(); void input(); void work(); int main() { init(); int T; scanf( %d , &T); while (T--) { input(); work(); } } void init() { ios::sync_with_stdio(false); } void input() { scanf( %d%d , &n, &m); int u, v; for (int i = 1; i <= n; ++i) es[i].clear(); for (int i = 1; i <= m; ++i) { scanf( %d%d , &u, &v); es[u].push_back(v); es[v].push_back(u); } } void work() { bool flag = true; for (int i = 1; i <= n; ++i) { if (es[i].size() & 1) { flag = false; break; } } if (flag) { printf( 1 n ); for (int i = 1; i <= n; ++i) printf( 1 ); putchar( n ); return; } bitset<MAXN> nb; memset(hv, false, sizeof(hv)); for (int i = 1; i <= n; ++i) bs[i] = 0; for (int i = 1; i <= n; ++i) { nb = 0; for (auto x : es[i]) nb[x] = 1; nb[i] = es[i].size() & 1; nb[n + 1] = es[i].size() & 1; for (int j = 1; j <= n; ++j) { if (nb[j]) { if (hv[j]) nb ^= bs[j]; else { hv[j] = true; bs[j] = nb; break; } } } } memset(dp, 0, sizeof(dp)); for (int i = n; i > 0; --i) { if (hv[i]) { dp[i] = bs[i][n + 1]; for (int j = i + 1; j <= n; ++j) { if (bs[i][j] && hv[j]) dp[i] ^= dp[j]; } } } printf( 2 n ); for (int i = 1; i <= n; ++i) printf( %d , dp[i] + 1); putchar( n ); }
|
////////////////////////////////////////////////////////////////////-
// Design unit: Control Unit (Module)
// :
// File name : cu.v
// :
// Description: Control Unit of Vending Machine
// :
// Limitations: None
// :
// System : Verilog
// :
// Author : 1. Wan Ahmad Zainie bin Wan Mohamad (ME131135)
// :
// : 2. Azfar 'Aizat bin Mohd Isa (ME131032)
// :
//
// Revision : Version 0.1 2014-05-30 Initial
// : Version 1.0 2014-06-09 Ready for submission
// : Version 2.0 2014-06-10 Change to behavioral
////////////////////////////////////////////////////////////////////-
module cu(clk, rst, deposited, selected, cancel, maintenance, purchase,
ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange,
ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect,
clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase,
refundall, depositall, state);
input clk, rst;
input deposited, selected, cancel, maintenance, purchase;
output ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange;
output ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect;
output clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase;
output refundall, depositall;
output [2:0] state;
reg [2:0] pstate, nstate;
reg [15:0] cv;
parameter S_init = 3'b000, S_wait = 3'b001, S_deposit = 3'b010,
S_cancel = 3'b011, S_select = 3'b100, S_purchase = 3'b101,
S_maintenance = 3'b110;
// state register submodule
always @ (negedge clk or negedge rst) begin
if (rst == 0) pstate <= S_init;
else pstate <= nstate;
end
// next state logic
always @ (pstate or cancel or maintenance or deposited or selected or purchase) begin
case (pstate)
S_init:
nstate = S_wait;
S_wait:
if (maintenance) nstate = S_maintenance;
else if (deposited) nstate = S_deposit;
else if (cancel) nstate = S_cancel;
else if (selected) nstate = S_select;
else nstate = S_wait;
S_select:
if (purchase) nstate = S_purchase;
else nstate = S_wait;
S_purchase: nstate = S_init;
S_maintenance:
if (maintenance) nstate = S_maintenance;
else nstate = S_init;
default: nstate = S_wait;
endcase
end
// output logic
always @ (pstate or selected) begin
case (pstate)
S_init: cv = 16'b0011_1111_1000_0000;
S_wait: cv = 16'b0011_1000_0000_0111;
S_deposit: cv = 16'b0011_1011_0000_1001;
S_cancel: cv = 16'b0011_1111_1000_0000;
S_select: cv = 16'b0001_1010_1100_0000;
S_purchase: cv = 16'b1010_0010_1011_0000;
S_maintenance:
if (selected) cv = 16'b0111_1100_1000_0110;
else cv = 16'b0011_1100_1000_0000;
endcase
end
assign state = pstate;
assign ldRdeposit = cv[0];
assign ldRselect = cv[1];
assign ldRprice = cv[2];
assign ldA = cv[3];
assign ldRproduct = cv[4];
assign ldRchange = cv[5];
assign ldRpurchase = cv[6];
assign clrRdeposit = cv[7];
assign clrRselect = cv[8];
assign clrRprice = cv[9];
assign clrA = cv[10];
assign clrRproduct = cv[11];
assign clrRchange = cv[12];
assign clrRpurchase = cv[13];
assign ldMprice = cv[14];
assign ldMquantity = cv[15];
assign refundall = (state == S_cancel || state == S_maintenance) ? 1'b1 : 1'b0;
assign depositall = (state == S_purchase) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int power_mod(long long int a, long long int x) { if (x == 0) return 1; long long int y = power_mod(a, x / 2); long long int ans = (y * y) % 1000000007; if (x % 2) ans = (ans * a) % 1000000007; return ans; } long long int inv(long long int a) { return power_mod(a, 1000000007 - 2); } long long int power(long long int a, long long int x) { if (x == 0) return 1; long long int y = power(a, x / 2); long long int ans = (y * y); if (x % 2) ans *= a; return ans; } const long long int N = 1 + 1ll << 18; int level[20] = {}; long long int a[N] = {}; long long int tree[4 * N] = {}; void build(long long int st, long long int ed, long long int node) { if (st == ed) { tree[node] = a[st]; return; } long long int mid = (st + ed) / 2; long long int left = 2 * node; long long int right = 2 * node + 1; build(st, mid, left); build(mid + 1, ed, right); tree[node] = tree[left] + tree[right]; } inline void update(long long int st, long long int ed, long long int node, long long int dep, long long int i) { if (i < st or i > ed) return; if (st == ed) { if (st == i) { tree[node] = a[st]; } return; } long long int mid = (st + ed) / 2; long long int left = 2 * node; long long int right = 2 * node + 1; if (level[dep]) { swap(left, right); } update(st, mid, left, dep - 1, i); update(mid + 1, ed, right, dep - 1, i); tree[node] = tree[left] + tree[right]; } inline long long int query(long long int st, long long int ed, long long int l, long long int r, long long int node, long long int dep) { if (ed < l or st > r) return 0; if (st >= l and ed <= r) return tree[node]; long long int mid = (st + ed) / 2; long long int left = 2 * node; long long int right = 2 * node + 1; long long int x = st, y = mid; long long int go = left; if (l > mid) { x = mid + 1; y = ed; go = right; } if (level[dep]) { if (go == left) { go = right; } else go = left; } return query(x, y, l, r, go, dep - 1); } inline long long int get(long long int x, long long int n) { if (x == 0) return 0; long long int sum = 0; long long int left = 1; long long int m = 1 << n; for (long long int i = 18; i >= 0; i--) { if (x & (1 << i)) { sum += query(1, m, left, left - 1 + (1 << i), 1, n); left += (1 << i); } } return sum; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, q; cin >> n >> q; long long int m = 1ll << n; for (long long int i = 1; i <= m; i++) { cin >> a[i]; } build(1, m, 1); while (q--) { long long int c; cin >> c; if (c == 1) { long long int x, k; cin >> x >> k; a[x] = k; update(1, m, 1, n, x); } if (c == 2) { long long int x; cin >> x; for (long long int i = 0; i <= x; i++) { level[i] = 1 - level[i]; } } if (c == 3) { long long int x; cin >> x; level[x + 1] = 1 - level[x + 1]; } if (c == 4) { long long int l, r; cin >> l >> r; long long int ans = get(r, n) - get(l - 1, n); cout << ans << endl; } } }
|
`timescale 1ns/1ns
module dm( addr, wd, be, clk, rd ) ;
input [12:2] addr ; // address bus
input [31:0] wd ;
// 32-bit input data
input [3:0] be ;
// memory write enable
input clk ;
// clock
output [31:0] rd ; // 32-bit memory output
reg [31:0] _dm[2047:0] ;
always @(posedge clk) begin
if (be==4'b1111) begin
_dm[addr]<=wd;
end // if(be==4'b1111)
else if (be==4'b0011) begin
_dm[addr]<={_dm[addr][31:16],wd[15:0]};
end // if(be==4'b0011)
else if (be==4'b1100) begin
_dm[addr]<={wd[15:0],_dm[addr][15:0]};
end // if(be==4'b1100)
else if (be==4'b0001) begin
_dm[addr]<={_dm[addr][31:8],wd[7:0]};
end // if(be==4'b0001)
else if (be==4'b0010) begin
_dm[addr]<={_dm[addr][31:16],wd[7:0],_dm[addr][7:0]};
end // if(be==4'b0001)
else if (be==4'b0100) begin
_dm[addr]<={_dm[addr][31:24],wd[7:0],_dm[addr][15:0]};
end // if(be==4'b0001)
else if (be==4'b1000) begin
_dm[addr]<={wd[7:0],_dm[addr][23:0]};
end
end
assign rd = _dm[addr];
initial begin
$readmemh("data.txt",_dm);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input play,
input reset,
output sdout,
output lrck,
output mclk,
output sclk,
output DAC_STATUS
);
reg[8:0] dac_address_r;
wire[8:0] dac_address = dac_address_r;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[7:0] vol_reg;
reg[7:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
reg [25:0] interpol_count;
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [8:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
assign mclk = cnt[2]; // mclk = clk/8
assign lrck = cnt[8]; // lrck = mclk/128
assign sclk = cnt[3]; // sclk = lrck*32
reg [2:0] lrck_sreg;
reg [2:0] sclk_sreg;
wire lrck_rising = (lrck_sreg[1:0] == 2'b01);
wire lrck_falling = (lrck_sreg[1:0] == 2'b10);
wire sclk_rising = (sclk_sreg[1:0] == 2'b01);
wire sclk_falling = (sclk_sreg[1:0] == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg [1:0] reset_sreg;
wire reset_rising = (reset_sreg[1:0] == 2'b01);
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b11;
sclk_sreg = 1'b0;
dac_address_r = 10'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 8'h0;
vol_target_reg = 8'h00;
samples <= 2'b00;
end
always @(posedge clkin) begin
if(reset_rising) begin
dac_address_r <= 0;
interpol_count <= 0;
end else if(sysclk_rising) begin
if(interpol_count > 59378938) begin
interpol_count <= interpol_count + 122500 - 59501439;
dac_address_r <= dac_address_r + play_r;
end else begin
interpol_count <= interpol_count + 122500;
end
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[1:0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
reset_sreg <= {reset_sreg[0], reset};
end
always @(posedge clkin) begin
if (vol_latch_rising) begin
vol_valid <= 1'b1;
end
else if(vol_valid) begin
vol_target_reg <= volume;
vol_valid <= 1'b0;
end
end
// ramp volume only every 4 samples
always @(posedge clkin) begin
if (lrck_rising && &samples[1:0]) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising) begin // right channel
smpshift <= (({16'h0, dac_data[31:16]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
samples <= samples + 1;
end else if (lrck_falling) begin // left channel
smpshift <= (({16'h0, dac_data[15:0]^16'h8000} * vol_reg) >> 8) ^ 16'h8000;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 10; struct Node { int is, id, x; bool operator<(const Node &a) const { if (x != a.x) return x < a.x; else return is < a.is; } }; int a[maxn * 4], s[maxn], p[maxn], inc[maxn], b[maxn], treea[maxn * 4], treeb[maxn * 4], pb[maxn]; int ans[maxn]; map<int, int> ma; int cnt = 0, tt = 0; Node que[maxn * 3]; int getid(int x) { x = -x; return ma[x]; } void add1(int x, int y) { for (int i = x; i < 4 * maxn; i += (i & -i)) treea[i] += y; } void add2(int x, int y) { for (int i = x; i < 4 * maxn; i += (i & -i)) treeb[i] += -y; } int quer1(int x) { int res = 0; for (int i = x; i >= 1; i -= (i & -i)) res += treea[i]; return res; } int quer2(int x) { int res = 0; for (int i = x; i >= 1; i -= (i & -i)) res += treeb[i]; return res; } int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &p[i]); for (int i = 1; i <= n; i++) scanf( %d , &s[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); for (int i = 1; i <= m; i++) scanf( %d , &inc[i]); for (int i = 1; i <= m; i++) scanf( %d , &pb[i]); for (int i = 1; i <= n; i++) { a[++cnt] = -(p[i] + b[i] - 1), a[++cnt] = -(b[i] - p[i]); que[++tt] = Node{0, i, p[i]}; que[++tt] = Node{2, i, s[i]}; } for (int i = 1; i <= m; i++) { a[++cnt] = -(inc[i] + pb[i]), a[++cnt] = -(pb[i] - inc[i]); que[++tt] = Node{1, i, inc[i]}; } sort(que + 1, que + 1 + tt); sort(a + 1, a + cnt + 1); int pz = 1; for (int i = 1; i <= cnt; i++) if (ma[a[i]] == 0) ma[a[i]] = pz++; for (int i = 1; i <= tt; i++) { Node now = que[i]; if (now.is == 0) { add1(getid(b[now.id] - p[now.id]), 1); add2(getid(p[now.id] + b[now.id] - 1), 1); } else if (now.is == 1) { ans[now.id] = quer1(getid(pb[now.id] - inc[now.id])) + quer2(getid(inc[now.id] + pb[now.id])); } else if (now.is == 2) { add1(getid(b[now.id] - p[now.id]), -1); add2(getid(p[now.id] + b[now.id] - 1), -1); } } for (int i = 1; i <= m; i++) { printf( %d , ans[i]); } return 0; }
|
extern "C" int ScheduleWavefront();
extern "C" void DescheduleWavefront(int cuid, int wfTag);
extern "C" int getTotalWavefronts();
extern "C" int getCuId();
//extern "C" int getWgId();
//extern "C" int getWfId();
extern "C" int getWfTag();
extern "C" int getWfCnt();
extern "C" int getWfNumThrds();
extern "C" int getVregBase();
extern "C" int getVregSize();
extern "C" int getSregBase();
extern "C" int getSregSize();
extern "C" int getLdsBase();
extern "C" int getLdsSize();
extern "C" int getSetVregs();
extern "C" int getVregKey(int index, int thrd);
extern "C" int getVregValue(int index, int thrd);
extern "C" int getSetSregs();
extern "C" int getSregKey(int index);
extern "C" int getSregValue(int index);
extern "C" void setVregValue(int cuid, int thrd, int vreg, int bitnum, int value);
extern "C" void setSregValue(int cuid, int sreg, int bitnum, int value);
extern "C" int getPC();
module dispatcher_soft (/*AUTOARG*/
// Outputs
dispatch2cu_wf_dispatch, dispatch2cu_wg_wf_count,
dispatch2cu_wf_size_dispatch, dispatch2cu_sgpr_base_dispatch,
dispatch2cu_vgpr_base_dispatch, dispatch2cu_wf_tag_dispatch,
dispatch2cu_lds_base_dispatch, dispatch2cu_start_pc_dispatch,
ldssize_out, vregsize_out, sregsize_out,
// Inputs
cu2dispatch_wf_done, cu2dispatch_wf_tag_done, rst, clk
) ;
parameter NUMOFCU = 1;
output reg [(NUMOFCU-1):0] dispatch2cu_wf_dispatch;
output reg [3:0] dispatch2cu_wg_wf_count;
output reg [5:0] dispatch2cu_wf_size_dispatch;
output reg [8:0] dispatch2cu_sgpr_base_dispatch;
output reg [9:0] dispatch2cu_vgpr_base_dispatch;
output reg [14:0] dispatch2cu_wf_tag_dispatch;
output reg [15:0] dispatch2cu_lds_base_dispatch;
output reg [31:0] dispatch2cu_start_pc_dispatch;
output [15:0] ldssize_out;
output [9:0] vregsize_out;
output [8:0] sregsize_out;
input [NUMOFCU-1:0] cu2dispatch_wf_done;
input [NUMOFCU*15 - 1:0] cu2dispatch_wf_tag_done;
input rst,clk;
reg [15:0] ldssize;
reg [9:0] vregsize;
reg [8:0] sregsize;
reg [31:0] sregVal, vregVal;
integer x, y, z;
integer m, n;
integer thrds, setVregs, setSregs;
integer sregKey, vregKey;
integer cuid;
integer a;
always @ (posedge clk) begin
if (rst) begin
// check <= 1'b0;
dispatch2cu_wf_dispatch <= 'b0;
end
end
always @ (posedge clk) begin
if (!rst) begin
if (ScheduleWavefront()==1'b1) begin
#1;
thrds = getWfNumThrds();
setVregs = getSetVregs();
setSregs = getSetSregs();
cuid = getCuId();
// set vregs
for (x = 0; x < setVregs; x++) begin
vregKey = getVregKey(x, 0);
for (y = 0; y < thrds; y++) begin
vregVal = getVregValue(x, y);
// set the vregister
for(a = 0; a < 32; a++) begin
setVregValue(cuid, y, vregKey, a, vregVal[a]);
//DUT[cuid].vgpr0.reg_file.bank[y].word[vregKey].bits[a].dff_0.state = vregVal[a];
end
end
end
// set sregs
for (z = 0; z < setSregs; z++) begin
sregKey = getSregKey(z);
sregVal = getSregValue(z);
// set the sregister
for(a = 0; a < 32; a++) begin
setSregValue(cuid, sregKey, a, sregVal[a]);
//DUT[cuid].sgpr0.sgpr_reg_file.word[sregKey].bits[a].dff_0.state = sregVal[a];
end
end
dispatch2cu_vgpr_base_dispatch <= getVregBase();
dispatch2cu_sgpr_base_dispatch <= getSregBase();
dispatch2cu_lds_base_dispatch <= getLdsBase();
vregsize <= getVregSize();
sregsize <= getSregSize();
ldssize <= getLdsSize();
dispatch2cu_start_pc_dispatch <= getPC();
dispatch2cu_wf_size_dispatch <= getWfNumThrds() - 1;
dispatch2cu_wf_tag_dispatch <= getWfTag();
dispatch2cu_wg_wf_count <= getWfCnt();
for (m = 0; m < NUMOFCU; m++) begin
// $display("CUID: %d",getCuId());
if(m==getCuId()) dispatch2cu_wf_dispatch[m] <= 1'b1;
else dispatch2cu_wf_dispatch[m] <= 1'b0;
// $display("m: %d dispatch2cu_wf_dispatch: %d",m,dispatch2cu_wf_dispatch[m]);
end
end
else begin
for ( m = 0; m < NUMOFCU; m++) begin
dispatch2cu_vgpr_base_dispatch <= 10'bx;
dispatch2cu_sgpr_base_dispatch <= 9'bx;
dispatch2cu_lds_base_dispatch <= 16'bx;
vregsize <= 10'bx;
sregsize <= 9'bx;
ldssize <= 16'bx;
dispatch2cu_start_pc_dispatch <= 32'bx;
dispatch2cu_wf_size_dispatch <= 6'bx;
dispatch2cu_wf_tag_dispatch <= 11'bx;
dispatch2cu_wf_dispatch[m] <= 1'b0;
end
end
end
end
always @ (posedge clk) begin
for(n=0; n<NUMOFCU; n++) begin
if (cu2dispatch_wf_done[n]) begin
DescheduleWavefront(n, cu2dispatch_wf_tag_done[((n * 15) + 14)-:15]); // cuid
end
end
end
assign ldssize_out = ldssize;
assign vregsize_out = vregsize;
assign sregsize_out = sregsize;
endmodule // dispatcher_wrapper
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/31/2014 07:10:33 PM
// Design Name:
// Module Name: led_controller_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module led_controller_sim();
integer i;
reg clk = 0;
always begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end
reg [7 : 0] data [511 : 0];
reg [7 : 0] data_out = 0;
wire [10 : 0] data_addr;
wire data_write;
wire [7 : 0] data_in;
wire led_clk;
wire led_data;
wire data_sending_test;
initial begin
for (i = 32'h0; i < 32'h10; i = i + 1) begin
data[i] = 8'hff;
end
data[1] = 8'b0;
for (i = 32'h10; i < 32'h200; i = i + 1) begin
data[i] = 8'b11100111;
end
end
always @ (posedge clk) begin
data_out = data[data_addr];
if (data_write) data[data_addr] = data_in;
if (data[1] == 1) data[0] = 0;
end
led_controller controller(
.clk(clk),
.mem_dout(data_out),
.mem_addr(data_addr),
.mem_din(data_in),
.mem_write(data_write),
.led_clk(led_clk),
.led_data(led_data),
.data_sending_test(data_sending_test)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int cheak(int x) { int sum = x; while (x) { sum += x / k; x /= k; } if (sum >= n) return 1; return 0; } int main() { scanf( %d%d , &n, &k); int head = 1, tail = n; while (head <= tail) { int mid = (head + tail) / 2; if (cheak(mid)) tail = mid - 1; else head = mid + 1; } printf( %d n , head); return 0; }
|
/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: Verify addition in a param declaration
*/
module test;
parameter A0 = 4'b0011 + 4'b0001 ;
initial
begin
if(A0 !== 4'b0100)
$display("FAILED - Addition in a param declaration.");
else
$display("PASSED");
end
endmodule
|
// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_7_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_0_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
`default_nettype wire
|
`include "elink_constants.v"
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
// Inputs
reset, etx90_reset, tx_lclk, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, tx_burst
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//###########
//# reset, clocks
//##########
input reset; //reset for io
input tx_lclk; // fast clock for io
input tx_lclk90; // fast 90deg shifted lclk
input etx90_reset;
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [PW-1:0] tx_packet;
input tx_access;
input tx_burst;
output tx_io_wait;
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [7:0] tx_pointer;
reg [15:0] tx_data16;
reg tx_access_reg;
reg tx_frame;
reg tx_io_wait_reg;
reg io_reset;
reg io_reset_in;
reg [PW-1:0] tx_packet_reg;
reg [63:0] tx_double;
reg [2:0] tx_state_reg;
reg [2:0] tx_state;
//############
//# WIRES
//############
wire new_tran;
wire access;
wire write;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [7:0] txo_data;
wire txo_frame;
wire txo_lclk90;
reg tx_io_wait;
//#############################
//# Transmit state machine
//#############################
`define IDLE 3'b000
`define CYCLE1 3'b001
`define CYCLE2 3'b010
`define CYCLE3 3'b011
`define CYCLE4 3'b100
`define CYCLE5 3'b101
`define CYCLE6 3'b110
`define CYCLE7 3'b111
always @ (posedge tx_lclk)
if(reset)
tx_state[2:0] <= `IDLE;
else
case (tx_state[2:0])
`IDLE : tx_state[2:0] <= tx_access ? `CYCLE1 : `IDLE;
`CYCLE1 : tx_state[2:0] <= `CYCLE2;
`CYCLE2 : tx_state[2:0] <= `CYCLE3;
`CYCLE3 : tx_state[2:0] <= `CYCLE4;
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst ? `CYCLE4 : `IDLE;
endcase // case (tx_state)
assign tx_new_frame = (tx_state[2:0]==`CYCLE1);
//Creating wait pulse for slow clock domain
always @ (posedge tx_lclk)
if(reset | ~tx_access)
tx_io_wait <= 1'b0;
else if ((tx_state[2:0] ==`CYCLE4) & ~tx_burst)
tx_io_wait <= 1'b1;
else if (tx_state[2:0]==`CYCLE7)
tx_io_wait <= 1'b0;
//Create frame signal for output
always @ (posedge tx_lclk)
begin
tx_state_reg[2:0] <= tx_state[2:0];
tx_frame <= |(tx_state_reg[2:0]);
end
//#############################
//# 2 CYCLE PACKET PIPELINE
//#############################
always @ (posedge tx_lclk)
if (tx_access)
tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
packet2emesh p2e (.access_out (access),
.write_out (write),
.datamode_out (datamode[1:0]),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (tx_packet_reg[PW-1:0]));
always @ (posedge tx_lclk)
if (tx_new_frame)
tx_double[63:0] <= {16'b0,//16
~write,7'b0,ctrlmode[3:0],//12
dstaddr[31:0],datamode[1:0],write,access};//36
else if(tx_state[2:0]==`CYCLE4)
tx_double[63:0] <= {data[31:0],srcaddr[31:0]};
//#############################
//# SELECTING DATA FOR TRANSMIT
//#############################
always @ (posedge tx_lclk)
case(tx_state_reg[2:0])
//Cycle1
3'b001: tx_data16[15:0] <= tx_double[47:32];
//Cycle2
3'b010: tx_data16[15:0] <= tx_double[31:16];
//Cycle3
3'b011: tx_data16[15:0] <= tx_double[15:0];
//Cycle4
3'b100: tx_data16[15:0] <= tx_double[63:48];
//Cycle5
3'b101: tx_data16[15:0] <= tx_double[47:32];
//Cycle6
3'b110: tx_data16[15:0] <= tx_double[31:16];
//Cycle7
3'b111: tx_data16[15:0] <= tx_double[15:0];
default tx_data16[15:0] <= 16'b0;
endcase // case (tx_state[2:0])
//#############################
//# RESET SYNCHRONIZER
//#############################
always @ (posedge tx_lclk)// or posedge reset)
if(reset)
begin
io_reset_in <= 1'b1;
io_reset <= 1'b1;
end
else
begin
io_reset_in <= 1'b0;
io_reset <= io_reset_in;
end
//#############################
//# ODDR DRIVERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data[i]),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_data16[i+8]),
.D2 (tx_data16[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame),
.C (tx_lclk),
.CE (1'b1),
.D1 (tx_frame),
.D2 (tx_frame),
.R (io_reset),
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"),.SRTYPE("SYNC"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1),
.D2 (1'b0),
.R (etx90_reset),
.S (1'b0)
);
//##############################
//# OUTPUT BUFFERS
//##############################
OBUFDS obufds_data[7:0] (
.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data[7:0])
);
OBUFDS obufds_frame ( .O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame)
);
OBUFDS obufds_lclk ( .O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90)
);
//################################
//# Wait Input Buffers
//################################
generate
if(ETYPE==1)
begin
assign tx_wr_wait = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait));
end
endgenerate
//TODO: Come up with cleaner defines for this
//Parallella and other platforms...
`ifdef TODO
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:48:31 MST 2014
//Date : Wed Sep 30 14:31:49 2015
//Host : rcswrka27 running 64-bit Ubuntu 10.04.4 LTS
//Command : generate_target Test_AXI_Master_simple_v1_0_hw_1_wrapper.bd
//Design : Test_AXI_Master_simple_v1_0_hw_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module Test_AXI_Master_simple_v1_0_hw_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
mosi_o,
ppm_signal_in,
sck_o,
ss_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output mosi_o;
input ppm_signal_in;
output sck_o;
output [0:0]ss_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire mosi_o;
wire ppm_signal_in;
wire sck_o;
wire [0:0]ss_o;
Test_AXI_Master_simple_v1_0_hw_1 Test_AXI_Master_simple_v1_0_hw_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.mosi_o(mosi_o),
.ppm_signal_in(ppm_signal_in),
.sck_o(sck_o),
.ss_o(ss_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; int mdc(int a, int b) { return !b ? a : mdc(b, a % b); } int main() { int n, m, x, y, a, b, p, d, x1, y1, x2, y2; cin >> n >> m >> x >> y >> a >> b; d = mdc(a, b); a /= d; b /= d; p = min(n / a, m / b); a *= p; b *= p; if (x + a / 2 > n) { x2 = n; x1 = n - a; } else if (x - a / 2 < 0) { x1 = 0; x2 = a; } else { x2 = x + a / 2; x1 = x2 - a; } if (y + b / 2 > m) { y2 = m; y1 = m - b; } else if (y - b / 2 < 0) { y1 = 0; y2 = b; } else { y2 = y + b / 2; y1 = y2 - b; } cout << x1 << << y1 << << x2 << << y2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 3e5 + 10; const int lim = 1000; int prime[Maxn], M[Maxn], H[Maxn], cnt; bool vis[Maxn]; struct node { int v, c, l; } a[Maxn]; int cmp(node A, node B) { return A.l < B.l; } int n, k; int main() { int cnt = 0; vis[0] = vis[1] = 1; for (int i = 2; i <= 3e5; i++) { if (!vis[i]) prime[++cnt] = i; for (int j = 1; j <= cnt && i * prime[j] <= 3e5; j++) { vis[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } scanf( %d %d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d %d %d , &a[i].v, &a[i].c, &a[i].l); sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n; i++) M[a[i].l] = i; int ans = 0, sum, top; for (int i = 1; i <= n; i++) { if (!M[i]) continue; for (int h = 0; h < lim; h++) { random_shuffle(a + 1, a + M[i] + 1); top = 0, sum = 0; for (int j = 1; j <= M[i]; j++) { bool _ = 1; for (int q = 0; q < top; q++) if (!vis[a[j].c + a[H[q]].c]) { _ = 0; break; } if (_) { H[top++] = j; sum += a[j].v; } } if (sum >= k) return 0 * printf( %d n , i); } } puts( -1 ); }
|
module Computer(
output [COUNTER_WIDTH-1:0] COUNTER_bus,
output [WORD_WIDTH-1:0] ADDR_bus,
output [WORD_WIDTH-1:0] DATA_bus,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
parameter FLAG_WIDTH = 4;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
Computer_ControlUnit_InstructionDecoder ID0 (
.CNTRL_bus_out(CNTRL_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam ID0.WORD_WIDTH = WORD_WIDTH;
defparam ID0.DR_WIDTH = DR_WIDTH;
defparam ID0.SB_WIDTH = DR_WIDTH;
defparam ID0.SA_WIDTH = DR_WIDTH;
defparam ID0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam ID0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam ID0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] INSTR_bus;
Computer_ControlUnit_InstructionMemory IM0 (
.INSTR_out(INSTR_bus),
.COUNTER_in(COUNTER_bus)
);
defparam IM0.WORD_WIDTH = WORD_WIDTH;
defparam IM0.DR_WIDTH = DR_WIDTH;
defparam IM0.SB_WIDTH = DR_WIDTH;
defparam IM0.SA_WIDTH = DR_WIDTH;
defparam IM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam IM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam IM0.COUNTER_WIDTH = COUNTER_WIDTH;
//wire [COUNTER_WIDTH-1:0] COUNTER_bus;
Computer_ControlUnit_ProgramCounter PC0 (
.COUNTER_out(COUNTER_bus),
.JMPADDR_in(ADDR_bus),
.CNTRL_bus_in(CNTRL_bus),
.FLAG_bus_in(FLAG_bus),
.SE_in(SE_bus),
.CLK(CLK),
.RST(RST)
);
defparam PC0.WORD_WIDTH = WORD_WIDTH;
defparam PC0.DR_WIDTH = DR_WIDTH;
defparam PC0.SB_WIDTH = DR_WIDTH;
defparam PC0.SA_WIDTH = DR_WIDTH;
defparam PC0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam PC0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam PC0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] SE_bus;
Computer_ControlUnit_SignalExtensor SE0 (
.SE_out(SE_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam SE0.WORD_WIDTH = WORD_WIDTH;
defparam SE0.DR_WIDTH = DR_WIDTH;
defparam SE0.SB_WIDTH = DR_WIDTH;
defparam SE0.SA_WIDTH = DR_WIDTH;
defparam SE0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam SE0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam SE0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] CONST_bus;
Computer_ControlUnit_ZeroFiller ZF0 (
.CONST_bus_out(CONST_bus),
.INSTR_bus_in(INSTR_bus)
);
defparam ZF0.WORD_WIDTH = WORD_WIDTH;
defparam ZF0.DR_WIDTH = DR_WIDTH;
defparam ZF0.SB_WIDTH = DR_WIDTH;
defparam ZF0.SA_WIDTH = DR_WIDTH;
defparam ZF0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam ZF0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam ZF0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] DMEM_out_bus;
Computer_DataMemory DM0 (
.DMEM_out(DMEM_out_bus),
.ADDR_bus_in(ADDR_bus),
.DATA_bus_in(DATA_bus),
.CNTRL_bus_in(CNTRL_bus),
.RST(RST)
);
defparam DM0.WORD_WIDTH = WORD_WIDTH;
defparam DM0.DR_WIDTH = DR_WIDTH;
defparam DM0.SB_WIDTH = DR_WIDTH;
defparam DM0.SA_WIDTH = DR_WIDTH;
defparam DM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam DM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam DM0.COUNTER_WIDTH = COUNTER_WIDTH;
//wire [WORD_WIDTH-1:0] DATA_bus;
Computer_Datapath_BusMuxer BM0 (
.BUS_out(DATA_bus),
.A_in(B_data_out_bus),
.B_in(CONST_bus),
.S(CNTRL_bus[10])
);
defparam BM0.WORD_WIDTH = WORD_WIDTH;
defparam BM0.DR_WIDTH = DR_WIDTH;
defparam BM0.SB_WIDTH = DR_WIDTH;
defparam BM0.SA_WIDTH = DR_WIDTH;
defparam BM0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam BM0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam BM0.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] D_bus;
Computer_Datapath_BusMuxer BM1 (
.BUS_out(D_bus),
.A_in(FU_out_bus),
.B_in(DMEM_out_bus),
.S(CNTRL_bus[5])
);
defparam BM1.WORD_WIDTH = WORD_WIDTH;
defparam BM1.DR_WIDTH = DR_WIDTH;
defparam BM1.SB_WIDTH = DR_WIDTH;
defparam BM1.SA_WIDTH = DR_WIDTH;
defparam BM1.OPCODE_WIDTH = OPCODE_WIDTH;
defparam BM1.CNTRL_WIDTH = CNTRL_WIDTH;
defparam BM1.COUNTER_WIDTH = COUNTER_WIDTH;
wire [WORD_WIDTH-1:0] FU_out_bus;
wire [FLAG_WIDTH-1:0] FLAG_bus;
Computer_Datapath_FunctionUnit FU0 (
.FU_out(FU_out_bus),
.FLAG_bus_out(FLAG_bus),
.ADDR_bus_in(ADDR_bus),
.DATA_bus_in(DATA_bus),
.CNTRL_bus_in(CNTRL_bus)
);
defparam FU0.WORD_WIDTH = WORD_WIDTH;
defparam FU0.DR_WIDTH = DR_WIDTH;
defparam FU0.SB_WIDTH = DR_WIDTH;
defparam FU0.SA_WIDTH = DR_WIDTH;
defparam FU0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam FU0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam FU0.COUNTER_WIDTH = COUNTER_WIDTH;
//wire [WORD_WIDTH-1:0] ADDR_bus;
wire [WORD_WIDTH-1:0] B_data_out_bus;
Computer_Datapath_RegisterFile RF0 (
.ADDR_bus_out(ADDR_bus),
.B_data_out(B_data_out_bus),
.CNTRL_bus_in(CNTRL_bus),
.D_bus_in(D_bus),
.CLK(CLK),
.RST(RST)
);
defparam RF0.WORD_WIDTH = WORD_WIDTH;
defparam RF0.DR_WIDTH = DR_WIDTH;
defparam RF0.SB_WIDTH = DR_WIDTH;
defparam RF0.SA_WIDTH = DR_WIDTH;
defparam RF0.OPCODE_WIDTH = OPCODE_WIDTH;
defparam RF0.CNTRL_WIDTH = CNTRL_WIDTH;
defparam RF0.COUNTER_WIDTH = COUNTER_WIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { unsigned int n, c, i, ans = 1, arr[100001]; cin >> n >> c; for (i = 0; i < n; i++) { cin >> arr[i]; } for (i = 1; i < n; i++) { if (arr[i] - arr[i - 1] <= c) ans++; else ans = 1; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > q[500005]; int n, m, tot, nms, ans[500005], dep[500005], ms[500005], sz[500005], t[500005][30], a[500005], hd[500005], to[500005], nxt[500005]; char ch[500005]; int read() { int x = 0, fl = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) fl = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * fl; } void add(int x, int y) { tot++; to[tot] = y; nxt[tot] = hd[x]; hd[x] = tot; return; } void dfs(int x, int f) { sz[x] = 1; int mx = 0; for (int i = hd[x]; i; i = nxt[i]) { int y = to[i]; if (y == f) continue; dep[y] = dep[x] + 1, dfs(y, x); sz[x] += sz[y]; if (sz[y] > mx) mx = sz[y], ms[x] = y; } return; } void calc(int x, int f, int o) { t[dep[x]][a[x]] += o; for (int i = hd[x]; i; i = nxt[i]) { int y = to[i]; if (y == f || y == nms) continue; calc(y, x, o); } return; } void dsu(int x, int f, int o) { for (int i = hd[x]; i; i = nxt[i]) { int y = to[i]; if (y == f || y == ms[x]) continue; dsu(y, x, -1); } if (ms[x]) dsu(ms[x], x, 1), nms = ms[x]; calc(x, f, 1), nms = 0; for (int p = 0; p < (int)q[x].size(); p++) { int d = q[x][p].first, id = q[x][p].second, cnt = 0; for (int i = 1; i <= 26; i++) cnt += (t[d][i] & 1); ans[id] = (cnt <= 1); } if (o == -1) calc(x, f, -1); return; } int main() { n = read(), m = read(); for (int i = 2; i <= n; i++) { int x = read(); add(x, i); } scanf( %s , ch + 1); for (int i = 1; i <= n; i++) a[i] = ch[i] - a + 1; for (int i = 1; i <= m; i++) { int x = read(), y = read(); q[x].push_back(make_pair(y, i)); } dep[1] = 1, dfs(1, 0), dsu(1, 0, -1); for (int i = 1; i <= m; i++) printf( %s n , ans[i] ? Yes : No ); return 0; }
|
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module arbiter_2_masters (
//control signals
input clk,
input rst,
//wishbone master ports
input i_m0_we,
input i_m0_cyc,
input i_m0_stb,
input [3:0] i_m0_sel,
output o_m0_ack,
input [31:0] i_m0_dat,
output [31:0] o_m0_dat,
input [31:0] i_m0_adr,
output o_m0_int,
input i_m1_we,
input i_m1_cyc,
input i_m1_stb,
input [3:0] i_m1_sel,
output o_m1_ack,
input [31:0] i_m1_dat,
output [31:0] o_m1_dat,
input [31:0] i_m1_adr,
output o_m1_int,
//wishbone slave signals
output o_s_we,
output o_s_stb,
output o_s_cyc,
output [3:0] o_s_sel,
output [31:0] o_s_adr,
output [31:0] o_s_dat,
input [31:0] i_s_dat,
input i_s_ack,
input i_s_int
);
localparam MASTER_COUNT = 2;
//registers/wires
//this should be parameterized
reg [7:0] master_select;
reg [7:0] priority_select;
wire o_master_we [MASTER_COUNT - 1:0];
wire o_master_stb [MASTER_COUNT - 1:0];
wire o_master_cyc [MASTER_COUNT - 1:0];
wire [3:0] o_master_sel [MASTER_COUNT - 1:0];
wire [31:0] o_master_adr [MASTER_COUNT - 1:0];
wire [31:0] o_master_dat [MASTER_COUNT - 1:0];
//master select block
localparam MASTER_NO_SEL = 8'hFF;
localparam MASTER_0 = 0;
localparam MASTER_1 = 1;
always @ (posedge clk) begin
if (rst) begin
master_select <= MASTER_NO_SEL;
end
else begin
case (master_select)
MASTER_0: begin
if (!i_m0_cyc && !i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
MASTER_1: begin
if (!i_m1_cyc && !i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
default: begin
//nothing selected
if (i_m0_cyc) begin
master_select <= MASTER_0;
end
else if (i_m1_cyc) begin
master_select <= MASTER_1;
end
end
endcase
if ((master_select != MASTER_NO_SEL) && (priority_select < master_select) && (!o_s_stb && !i_s_ack))begin
master_select <= MASTER_NO_SEL;
end
end
end
//priority select
always @ (posedge clk) begin
if (rst) begin
priority_select <= MASTER_NO_SEL;
end
else begin
//find the highest priority
if (i_m0_cyc) begin
priority_select <= MASTER_0;
end
else if (i_m1_cyc) begin
priority_select <= MASTER_1;
end
else begin
priority_select <= MASTER_NO_SEL;
end
end
end
//slave assignments
assign o_s_we = (master_select != MASTER_NO_SEL) ? o_master_we[master_select] : 0;
assign o_s_stb = (master_select != MASTER_NO_SEL) ? o_master_stb[master_select] : 0;
assign o_s_cyc = (master_select != MASTER_NO_SEL) ? o_master_cyc[master_select] : 0;
assign o_s_sel = (master_select != MASTER_NO_SEL) ? o_master_sel[master_select] : 0;
assign o_s_adr = (master_select != MASTER_NO_SEL) ? o_master_adr[master_select] : 0;
assign o_s_dat = (master_select != MASTER_NO_SEL) ? o_master_dat[master_select] : 0;
//write select block
assign o_master_we[MASTER_0] = i_m0_we;
assign o_master_we[MASTER_1] = i_m1_we;
//strobe select block
assign o_master_stb[MASTER_0] = i_m0_stb;
assign o_master_stb[MASTER_1] = i_m1_stb;
//cycle select block
assign o_master_cyc[MASTER_0] = i_m0_cyc;
assign o_master_cyc[MASTER_1] = i_m1_cyc;
//select select block
assign o_master_sel[MASTER_0] = i_m0_sel;
assign o_master_sel[MASTER_1] = i_m1_sel;
//address seelct block
assign o_master_adr[MASTER_0] = i_m0_adr;
assign o_master_adr[MASTER_1] = i_m1_adr;
//data select block
assign o_master_dat[MASTER_0] = i_m0_dat;
assign o_master_dat[MASTER_1] = i_m1_dat;
//assign block
assign o_m0_ack = (master_select == MASTER_0) ? i_s_ack : 0;
assign o_m0_dat = i_s_dat;
assign o_m0_int = (master_select == MASTER_0) ? i_s_int : 0;
assign o_m1_ack = (master_select == MASTER_1) ? i_s_ack : 0;
assign o_m1_dat = i_s_dat;
assign o_m1_int = (master_select == MASTER_1) ? i_s_int : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long i, j, k, n, m, x, y, T, ans, mx, mi, cas, num, len; bool flag; long long a[105]; const int mod = 1000000007; typedef struct matrixnod { long long m[105][105]; } matrix; matrix mat(matrix a, matrix b) { matrix c; for (long long i = 0; i < x; i++) { for (long long j = 0; j < x; j++) { c.m[i][j] = 0; for (long long k = 0; k < x; k++) { c.m[i][j] += a.m[i][k] * b.m[k][j]; c.m[i][j] %= mod; } } } return c; } matrix p, f; matrix doexpmat(matrix f, long long num) { matrix b; long long i, j; for (i = 0; i < x; i++) { for (j = 0; j < x; j++) { if (i == j) b.m[i][j] = 1; else b.m[i][j] = 0; } } while (num) { if (num & 1) b = mat(b, f); num = num >> 1; f = mat(f, f); } return b; } long long b, t; int main() { scanf( %I64d%I64d%I64d%I64d , &n, &b, &k, &x); for (i = 1; i <= n; i++) { scanf( %I64d , &t); a[t]++; } for (i = 0; i < x; i++) { for (j = 0; j < 10; j++) { f.m[i][(i * 10 + j) % x] += a[j]; f.m[i][(i * 10 + j) % x] %= mod; } } matrix pp = doexpmat(f, b); printf( %I64d n , pp.m[0][k]); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
/**
* lsbufhv2hv_lh: Level shifting buffer, High Voltage to High Voltage,
* Lower Voltage to Higher Voltage.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbufhv2hv_lh (
X ,
A ,
VPWR ,
VGND ,
LOWHVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LOWHVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LOWHVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_LH_BEHAVIORAL_PP_V
|
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