text
stringlengths 59
71.4k
|
|---|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_BEHAVIORAL_V
|
/*
*
* Copyright (c) 2011-2012
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
module virtual_wire # (
parameter INPUT_WIDTH = 0,
parameter OUTPUT_WIDTH = 0,
parameter INITIAL_VALUE = " 0",
parameter INSTANCE_ID = "NONE"
) (
input clk,
input [INPUT_WIDTH-1:0] rx_data,
output [OUTPUT_WIDTH-1:0] tx_data
);
altsource_probe altsource_probe_component (
.probe (rx_data),
.source_clk (clk),
.source (tx_data)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = INSTANCE_ID,
altsource_probe_component.probe_width = INPUT_WIDTH,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = INITIAL_VALUE,
altsource_probe_component.source_width = OUTPUT_WIDTH;
endmodule
|
#include <bits/stdc++.h> int n; int a[1001000]; int b[1001000]; int c[1001000]; int ans; int main() { int i, j; scanf( %d , &n); n++; for (i = 2; i <= n; i++) { scanf( %d , &a[i]); b[i] = 1; c[i] = 0; j = i; if (ans < b[j]) ans = b[j]; while (a[j] != 1) { if (ans < b[j]) ans = b[j]; if (ans < b[a[j]]) ans = b[a[j]]; if (b[a[j]] < b[j]) { b[a[j]] = b[j]; c[a[j]] = 1; } else if (c[a[j]] == 1 && b[a[j]] == b[j]) { b[a[j]] = b[j] + 1; c[a[j]] = 0; } else if (c[a[j]] == 0 && b[a[j]] == b[j]) { c[a[j]] = 1; break; } else break; if (ans < b[a[j]]) ans = b[a[j]]; j = a[j]; } printf( %d , ans); } }
|
// ALU implementation
`include "verilog/mips_alu_defines.v"
module alu
(
input wire[31:0] opr_a_alu_i,
input wire[31:0] opr_b_alu_i,
input wire[5:0] op_alu_i,
output wire[31:0] res_alu_o,
output wire z_alu_o,
output wire n_alu_o
);
wire[31:0] res_alu;
wire z_alu;
wire n_alu;
wire v_alu;
wire[31:0] opr_b_negated_alu;
wire cin_alu;
wire[31:0] adder_out_alu;
wire carry_out_alu;
wire[31:0] logical_out_alu;
wire[31:0] shifter_out_alu;
wire comparator_out_alu;
assign res_alu_o = res_alu;
assign z_alu_o = z_alu;
assign n_alu_o = n_alu;
assign opr_b_negated_alu = op_alu_i[0] ? ~opr_b_alu_i : opr_b_alu_i;
assign cin_alu = op_alu_i[0];
assign z_alu = ~|res_alu;
assign n_alu = (v_alu) ? opr_a_alu_i[31] : adder_out_alu[31];
assign res_alu = ((op_alu_i == `ADD_OP) || (op_alu_i == `SUB_OP)) ? adder_out_alu :
((op_alu_i == `SHL_OP) || (op_alu_i == `LSR_OP) || (op_alu_i == `ASR_OP)) ? shifter_out_alu :
((op_alu_i == `OR_OP) || (op_alu_i == `AND_OP) || (op_alu_i == `NOR_OP) || (op_alu_i == `XOR_OP)) ? logical_out_alu :
((op_alu_i == `SLTU_OP)) ? comparator_out_alu :
((op_alu_i == `SLT_OP)) ? {{31{1'b0}}, n_alu}:
31'hxxxx_xxxx;
adder A1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_negated_alu),
.cin (cin_alu),
.sum (adder_out_alu),
.carry (carry_out_alu),
.v_flag (v_alu)
);
shifter S1 (
.op1 (opr_a_alu_i),
.shamt (opr_b_alu_i[5:0]),
.operation (op_alu_i[2:1]),
.res (shifter_out_alu)
);
logical L1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (logical_out_alu)
);
comparator C1 (
.op1 (opr_a_alu_i),
.op2 (opr_b_alu_i),
.operation (op_alu_i[5:3]),
.res (comparator_out_alu)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:28 07/05/2015
// Design Name:
// Module Name: Level1_Cache
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Level_1_Cache(
input Clock_in,
input Reset_in,
input [29:0] CPU_Address_in,
input [3:0] CPU_Write_Data_in,
input [31:0] CPU_Data_in,
output [31:0] CPU_Data_out,
input CPU_Read_in,
output CPU_Ready_out,
input CPU_Flush_in,
output CPU_Flush_Complete_out,
output [29:0] MEM_Address_out,
output MEM_Write_Data_out,
input [4095:0] MEM_Data_in,
output [4095:0] MEM_Data_out,
output MEM_Read_out,
input MEM_Ready_in,
output Init_Mem_out
);
wire [3:0] Index, Write_Data;
wire [7:0] Flush_Counter, Counter;
wire [6:0] Offset;
wire [18:0] Tag;
Cache_Control CONTROL (
.CPU_Address_in(CPU_Address_in),
.CPU_Write_Data_in(CPU_Write_Data_in),
.CPU_Read_in(CPU_Read_in),
.CPU_Ready_out(CPU_Ready_out),
.CPU_Flush_in(CPU_Flush_in),
.CPU_Flush_out(CPU_Flush_Complete_out),
.MEM_Address_out(MEM_Address_out),
.MEM_Write_Data_out(MEM_Write_Data_out),
.MEM_Read_out(MEM_Read_out),
.MEM_Ready_in(MEM_Ready_in),
.Index_out(Index),
.Offset_out(Offset),
.Write_Data_out(Write_Data),
.Dirty_in(Dirty_o),
.Dirty_out(Dirty_i),
.Write_Dirty_out(Write_Dirty),
.Init_Dirty_in(Init_Dirty),
.Tag_in(Tag),
.Write_Valid_Tag_out(Write_Valid_Tag),
.Valid_out(Valid_i),
.Init_Valid_in(Init_Mem_out),
.Hit_in(Hit),
.Counter_in(Counter),
.Reset_Counter_out(Reset_Counter),
.Counter_Enable_out(Counter_Enable),
.Flush_Count_in(Flush_Counter),
.Flush_Reset_Counter_out(Flush_Reset_Counter),
.Flush_Counter_Enable_out(Flush_Counter_Enable),
.Clock_in(Clock_in),
.Reset_in(Reset_in),
.Reset_Valid_Dirty_out(Reset_Valid_Dirty),
.Fill_out(Fill)
);
Data_Ram DATA_RAM (
.Offset_in(Offset),
.Index_in(Index),
.CPU_Data_in(CPU_Data_in),
.MEM_Data_in(MEM_Data_in),
.Clock_in(Clock_in),
.Write_Data_in(Write_Data),
.CPU_Data_out(CPU_Data_out),
.MEM_Data_out(MEM_Data_out),
.Fill_in(Fill)
);
Dirty_Ram DIRTY_RAM (
.Clock_in(Clock_in),
.Reset_in(Reset_Valid_Dirty || Reset_in),
.Index_in(Index),
.Dirty_in(Dirty_i),
.Write_Dirty_in(Write_Dirty),
.Dirty_out(Dirty_o),
.Counter_in(Counter),
.Init_Dirty_out(Init_Dirty)
);
Tag_Ram TAG_RAM (
.Index_in(Index),
.Tag_in(CPU_Address_in[29:11]),
.Clock_in(Clock_in),
.Write_Tag_in(Write_Valid_Tag),
.Tag_out(Tag)
);
Valid_Ram VALID_RAM (
.Clock_in(Clock_in),
.Reset_in(Reset_Valid_Dirty || Reset_in),
.Index_in(Index),
.Valid_in(Valid_i),
.Write_Valid_in(Write_Valid_Tag),
.Valid_out(Valid_o),
.Counter_in(Counter),
.Init_Valid_out(Init_Mem_out)
);
Hit_Detection HIT (
.CPU_Tag_in(CPU_Address_in[29:11]),
.Cache_Tag_in(Tag),
.Valid_Bit_in(Valid_o),
.HIT_out(Hit)
);
Counter Cache_Count (
.Clock_in(Clock_in),
.Enable_in(Counter_Enable),
.Reset_in(Reset_Counter),
.Count_out(Counter)
);
Counter Flush_Count (
.Clock_in(Clock_in),
.Enable_in(Flush_Counter_Enable),
.Reset_in(Flush_Reset_Counter),
.Count_out(Flush_Counter)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; struct node { double x; double y; double t; double p; bool operator<(const node& W) const { return t < W.t; } } q[N]; double dp[N]; bool check(node a, node b) { double dx = a.x - b.x; double dy = a.y - b.y; return sqrt(dx * dx + dy * dy) <= b.t - a.t; } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> q[i].x >> q[i].y >> q[i].t >> q[i].p; } sort(q + 1, q + n + 1); dp[1] = q[1].p; for (int i = 2; i <= n; i++) { dp[i] = q[i].p; for (int j = 1; j <= i - 1; j++) if (check(q[j], q[i])) dp[i] = max(dp[i], dp[j] + q[i].p); } double res = 0; for (int i = 1; i <= n; i++) res = max(res, dp[i]); printf( %.6lf n , res); return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_wb_sel_ctrl.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Module resposible for controlling wb_sel signal of the ////
//// master wishbone if. Handles unaligned access to wishbone ////
//// bus. ////
//// ////
//// Author(s): ////
//// - Marek Czerski, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_wb_sel_ctrl(
input wb_clk,
input rst,
input ena,
input [31:0] base_adr_i,
input [31:0] wbm_adr_i,
input [`BLKSIZE_W+`BLKCNT_W-1:0] xfersize,
output [3:0] wbm_sel_o
);
function [3:0] get_first_sel;
input [1:0] byte_addr;
begin
case (byte_addr)
2'b00: get_first_sel = 4'b1111;
2'b01: get_first_sel = 4'b0111;
2'b10: get_first_sel = 4'b0011;
2'b11: get_first_sel = 4'b0001;
endcase
end
endfunction
function [3:0] get_last_sel;
input [1:0] byte_addr;
begin
case (byte_addr)
2'b00: get_last_sel = 4'b1111;
2'b01: get_last_sel = 4'b1000;
2'b10: get_last_sel = 4'b1100;
2'b11: get_last_sel = 4'b1110;
endcase
end
endfunction
reg [31:0] base_adr_reg;
reg [`BLKSIZE_W+`BLKCNT_W-1:0] xfersize_reg;
wire [31:0] base_adr_plus_xfersize;
wire [3:0] first_mask;
wire [3:0] second_mask;
assign base_adr_plus_xfersize = base_adr_reg + xfersize_reg;
assign first_mask = base_adr_reg[31:2] == wbm_adr_i[31:2] ?
get_first_sel(base_adr_reg[1:0]) :
4'b1111;
assign second_mask = base_adr_plus_xfersize[31:2] == wbm_adr_i[31:2] ?
get_last_sel(base_adr_plus_xfersize[1:0]) :
4'b1111;
assign wbm_sel_o = first_mask & second_mask;
always @(posedge wb_clk or posedge rst)
if (rst) begin
base_adr_reg <= 0;
xfersize_reg <= 0;
end
else begin
if (!ena) begin
base_adr_reg <= base_adr_i;
xfersize_reg <= xfersize;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; string s[105]; set<char> ms; cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; long long ans = 1; for (int i = 0; i < m; i++) { ms.clear(); for (int j = 0; j < n; j++) ms.insert(s[j][i]); ans = ans * ms.size() % 1000000007; } cout << ans % 1000000007; }
|
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg avl_burstbegin_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_burstbegin_reg <= 1'b0;
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_burstbegin_reg <= avl_burstbegin;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_burstbegin_reg = avl_burstbegin;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = {4{itf_rd_data_error}};
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int k[3], t[3]; int n; long long a[100000]; long long was[100000]; int main() { scanf( %d %d %d , &k[0], &k[1], &k[2]); scanf( %d %d %d , &t[0], &t[1], &t[2]); scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %I64d , &a[i]); was[i] = a[i]; } for (int i = 0; i < 3; i++) { for (int j = 0; j < k[i]; j++) { int pos = j; long long finished = -1000000; if (pos >= n) break; while (pos < n) { a[pos] = finished = max(finished + t[i], a[pos] + t[i]); pos += k[i]; } } } long long res = a[0] - was[0]; for (int i = 1; i < n; i++) if (res < a[i] - was[i]) res = a[i] - was[i]; printf( %I64d n , res); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`include "../u_mux_4/sky130_fd_sc_hs__u_mux_4.v"
`celldefine
module sky130_fd_sc_hs__mux4 (
VPWR,
VGND,
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
// Local signals
wire u_mux_40_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_4_2 u_mux_40 (u_mux_40_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, u_mux_40_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; struct node { int x, y, id; bool operator<(const node &A) const { return x < A.x; } }; vector<node> line[2][100005 << 2]; bool mark[2][100005 << 2]; int n, m, k; long long t[100005]; void add(int x, int y, int i) { node a; a.x = x, a.y = y, a.id = i; line[1][y - x + 200000].push_back(a); line[0][x + y + 200000].push_back(a); } void solve() { bool flag = 0, first = 0; long long res = 0; int k = 1; int x = 0, y = 0; while (!flag) { if (x == 0 || y == 0 || x == n || y == m) { if (first) { if ((x == 0 || x == n) && (y == 0 || y == m)) { flag = 1; break; } k = -k; } else first = 1; } int cur = (k == 1); if (line[cur][y - k * x + 200000].size()) { if (mark[cur][y - k * x + 200000]) flag = 1; else { mark[cur][y - k * x + 200000] = 1; if (k == 1 && (!x || !y) || k == -1 && ((!x && y) || (y == m && x))) { for (int i = 0; i < line[cur][y - k * x + 200000].size(); i++) { int j = line[cur][y - k * x + 200000][i].id; node tmp = line[cur][y - k * x + 200000][i]; if (t[j]) { } else t[j] = res + abs(line[cur][y - k * x + 200000][i].x - x); } } else { for (int i = line[cur][y - k * x + 200000].size() - 1; i >= 0; i--) { int j = line[cur][y - k * x + 200000][i].id; node tmp = line[cur][y - k * x + 200000][i]; if (t[j]) { } else t[j] = res + abs(line[cur][y - k * x + 200000][i].x - x); } } } } int nx1, ny1, nx2, ny2, t1 = x, t2 = y; if (k == 1) { if (0 <= n + y - x && n + y - x <= m) nx1 = n, ny1 = n + y - x; else ny1 = m, nx1 = m + x - y; if (0 <= y - x && y - x <= m) nx2 = 0, ny2 = y - x; else ny2 = 0, nx2 = x - y; if (nx1 == x) { x = nx2, y = ny2; } else x = nx1, y = ny1; } else { if (0 <= x + y && x + y <= m) nx1 = 0, ny1 = x + y; else ny1 = m, nx1 = x + y - m; if (0 <= x + y - n && x + y - n <= m) nx2 = n, ny2 = x + y - n; else ny2 = 0, nx2 = x + y; if (nx1 == x) { x = nx2, y = ny2; } else x = nx1, y = ny1; } res += abs(x - t1); } } inline void print(long long x) { if (!x) return; print(x / 10); putchar(x % 10 ^ 48); } inline void pf(long long x) { print(x); if (!x) puts( 0 ); else puts( ); } inline void rd(int &res) { res = 0; char c; while (c = getchar(), c < 0 || c > 9 ) ; do { res = (res << 3) + (res << 1) + (c ^ 48); } while (c = getchar(), 0 <= c && c <= 9 ); } int main() { rd(n); rd(m); rd(k); for (int i = 1; i <= k; i++) { int a, b; rd(a); rd(b); add(a, b, i); } for (int i = 0; i < 2; i++) for (int j = 0; j < 2 * 100005; j++) { if (line[i][j].size()) { sort(line[i][j].begin(), line[i][j].end()); } } solve(); for (int i = 1; i <= k; i++) { if (t[i]) pf(t[i]); else puts( -1 ); } return 0; }
|
module top (
input wire [7:0] inp,
input wire [1:0] hiz,
output wire [3:0] out,
output wire [3:0] out_p,
output wire [3:0] out_n
);
// OBUF
OBUF #(
.IOSTANDARD("LVCMOS33"),
.DRIVE(8),
.SLEW("FAST")
) obuf_0 (
.I (inp[0]),
.O (out[0])
);
// OBUFT, T=0
OBUFT #(
.IOSTANDARD("LVCMOS33"),
.DRIVE(8),
.SLEW("FAST")
) obuf_1 (
.I (inp[1]),
.T (1'b0),
.O (out[1])
);
// OBUFT, T=1 (this case is useless as it is always 1'bz on output)
OBUFT #(
.IOSTANDARD("LVCMOS33"),
.DRIVE(8),
.SLEW("FAST")
) obuf_2 (
.I (inp[2]),
.T (1'b1),
.O (out[2])
);
// OBUFT, T=<net>
OBUFT #(
.IOSTANDARD("LVCMOS33"),
.DRIVE(8),
.SLEW("FAST")
) obuf_3 (
.I (inp[3]),
.T (hiz[0]),
.O (out[3])
);
// OBUFDS
OBUFDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_0 (
.I (inp[4]),
.O (out_p[0]),
.OB(out_n[0])
);
// OBUFTDS, T=0
OBUFTDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_1 (
.I (inp[5]),
.T (1'b0),
.O (out_p[1]),
.OB(out_n[1])
);
// OBUFTDS, T=1 (this case is useless as it is always 1'bz on output)
OBUFTDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_2 (
.I (inp[6]),
.T (1'b1),
.O (out_p[2]),
.OB(out_n[2])
);
// OBUFTDS, T=<net>
OBUFTDS # (
.IOSTANDARD("DIFF_SSTL135"),
.SLEW("FAST")
) obuftds_3 (
.I (inp[7]),
.T (hiz[1]),
.O (out_p[3]),
.OB(out_n[3])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; const long long INF = 1e9; const long long MOD = 1000000007; int prevs[20]; int main() { ios ::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; int ar[n][20]; for (int i = 0; i < n; i++) for (int j = 0; j < 20; j++) ar[i][j] = n + 3; for (int i = n - 1; i >= 0; i--) { int x = 1; for (int j = 0; j < 20; j++) { if ((x << j) & arr[i]) { ar[i][j] = i; if (prevs[j] != 0) for (int k = 0; k < 20; k++) ar[i][k] = min(ar[i][k], ar[prevs[j]][k]); prevs[j] = i; } } } while (q--) { int x, y; cin >> x >> y; x--, y--; if (!arr[x] || !arr[y]) { cout << Fou << endl; continue; } int p = 1; int l = 0; for (int j = 0; j < 20; j++) if (p << j & arr[y]) if (ar[x][j] <= y) { l = 1; continue; } if (l == 1) cout << Shi << endl; else cout << Fou << endl; } }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:image_capture_manager:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_image_capture_manager_0_0 (
image_capture_enabled,
clear_memory,
reset,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
output wire image_capture_enabled;
output wire clear_memory;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST" *)
output wire reset;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
image_capture_manager #(
.START_IMAGE_CAPTURE_COMMAND(1),
.STOP_IMAGE_CAPTURE_COMMAND(2),
.RESET_IMAGE_CAPTURE_COMMAND(3),
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.image_capture_enabled(image_capture_enabled),
.clear_memory(clear_memory),
.reset(reset),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
#include <bits/stdc++.h> int main() { long long n, d, m, l, i, le, ri, step; while (~scanf( %I64d%I64d%I64d%I64d , &n, &d, &m, &l)) { for (i = 0; i < n; i++) { le = i * m + l; ri = (i + 1) * m; step = (le + d) / d; if (step * d < ri) break; } printf( %I64d n , step * d); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND ,
SLEEP
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
input SLEEP ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_BLACKBOX_V
|
#include <bits/stdc++.h> int minDig(uint64_t n) { int k = n % 10, min = k; n /= 10; while (n != 0) { k = n % 10; if (k <= min) min = k; n /= 10; } return min; } int maxDig(uint64_t n) { int k = n % 10, max = k; n /= 10; while (n != 0) { k = n % 10; if (k >= max) max = k; n /= 10; } return max; } int searchzero(uint64_t n) { while (n != 0) { if (n % 10 == 0) return 1; n /= 10; } return 0; } int main(void) { int t; uint64_t a, k; scanf( %d , &t); while (t--) { scanf( %llu %llu , &a, &k); for (uint64_t i = 1; i < k; i++) { a += (minDig(a) * maxDig(a)); if (searchzero(a) == 1) break; } printf( %llu n , a); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 5; const int mod = 51123987; char s[maxn]; struct Pam { vector<pair<int, int> > next[maxn]; int fail[maxn]; int len[maxn]; int num[maxn]; int S[maxn]; long long a[maxn], b[maxn]; int last, n, p; int newNode(int l) { next[p].clear(); len[p] = l; return p++; } void init() { n = last = p = 0; newNode(0); newNode(-1); S[n] = -1; fail[0] = 1; } int getFail(int x) { while (S[n - len[x] - 1] != S[n]) { x = fail[x]; } return x; } int find(int u, int c) { vector<pair<int, int> >& x = next[u]; int sz = x.size(); for (int i = 0; i < sz; ++i) { if (x[i].first == c) return x[i].second; } return 0; } int add(int c) { S[++n] = c; int cur = getFail(last); int x = find(cur, c); if (!x) { int now = newNode(len[cur] + 2); x = now; fail[now] = find(getFail(fail[cur]), c); next[cur].push_back(make_pair(c, now)); num[now] = num[fail[now]] + 1; } last = x; return num[last]; } void solve(int len) { memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); init(); for (int i = 0; i < len; i++) { a[i] = add(s[i] - a ); } init(); for (int i = len - 1; i >= 0; i--) { b[i] = (b[i + 1] + add(s[i] - a )) % mod; } long long ans = (b[0] * (b[0] - 1) / 2) % mod; for (int i = 0; i < len; i++) { ans = ((ans - (a[i] * b[i + 1]) + mod) % mod) % mod; } printf( %lld n , ans); } } pam; int main() { int n; while (~scanf( %d , &n)) { scanf( %s , s); pam.solve(n); } return 0; }
|
#include <bits/stdc++.h> using namespace std; struct data { int to, head; } e[750000 * 2]; stack<int> s; vector<int> cir[750000]; int n, m, len, head[750000], dfn[750000], low[750000], cnt, num, p[750000], binv[750000], d[750000]; int ans, tot; long long mm; int mul(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = 1ll * ans * a % 1000000007; a = 1ll * a * a % 1000000007; b >>= 1; } return ans; } void dfs(int lab, int fa) { dfn[lab] = low[lab] = ++num; s.push(lab); for (int i = head[lab]; i; i = e[i].head) { if (!dfn[e[i].to]) { dfs(e[i].to, lab); low[lab] = min(low[lab], low[e[i].to]); if (low[e[i].to] == dfn[lab]) { cnt++; int m1; do { m1 = s.top(); s.pop(); if (dfn[lab] == low[m1]) cir[cnt].push_back(m1); } while (m1 != e[i].to); cir[cnt].push_back(lab); m1 = cir[cnt].size(); for (auto j : cir[cnt]) p[j] = (1ll * p[j] + binv[m1]) % 1000000007; tot = (1ll * tot + binv[m1]) % 1000000007; } } if (e[i].to != fa) low[lab] = min(low[lab], dfn[e[i].to]); } } void add(int u, int v) { e[++len].to = v; e[len].head = head[u]; head[u] = len; } int main() { binv[0] = 1; binv[1] = mul(2, 1000000007 - 2); int u, v, m1, m2, m3; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); add(u, v); add(v, u); d[u]++; d[v]++; } m1 = max(n, 10); for (int i = 2; i <= m1; i++) binv[i] = 1ll * binv[1] * binv[i - 1] % 1000000007; ans = 1ll * n * (n + 1) % 1000000007 * binv[2] % 1000000007; ans = (ans + 1ll * m * binv[2]) % 1000000007; dfs(1, 0); for (int i = 1; i <= n; i++) { ans = (ans - 2ll * d[i] * binv[2]) % 1000000007; ans = (ans - 2ll * (m - d[i]) * binv[3]) % 1000000007; ans = (ans + 2ll * p[i]) % 1000000007; ans = (ans + 2ll * (tot - p[i]) * binv[1]) % 1000000007; for (int j = head[i]; j; j = e[j].head) { if (e[j].to < i) continue; ans = (ans + (1ll * d[i] + d[e[j].to] - 3 + m) * binv[4]) % 1000000007; } } ans = (1ll * ans + tot) % 1000000007; for (int i = 1; i <= cnt; i++) { m1 = 0; m2 = cir[i].size(), m3 = 0; for (auto j : cir[i]) { m1 = (1ll * m1 + p[j] - binv[m2]) % 1000000007; ans = (ans + 1ll * (p[j] - binv[m2]) * binv[m2] % 1000000007 * 2) % 1000000007; m3 = (1ll * m3 + d[j] - 2) % 1000000007; ans = (ans - 2ll * binv[m2 + 1] * (d[j] - 2)) % 1000000007; } m1 = (1ll * m1 + binv[m2]) % 1000000007; ans = (ans + 1ll * (tot - m1) * binv[m2]) % 1000000007; ans = (ans - 2ll * m2 * binv[m2]) % 1000000007; ans = (ans - 2ll * (m - m3 - m2) * binv[m2 + 2]) % 1000000007; } m1 = (1ll * n * binv[1] - 1ll * m * binv[2] + 1ll * tot) % 1000000007; ans = ((ans - 1ll * m1 * m1) % 1000000007 + 1000000007) % 1000000007; printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; unsigned long long mod = 1e9 + 7; unsigned long long ncr(long long int n, long long int k) { unsigned long long res = 1; if (k > n - k) k = n - k; for (int i = 0; i < k; ++i) { res *= (n - i); res /= (i + 1); res = res % mod; } return res % mod; } bool prime(unsigned long long num) { bool flag = true; for (unsigned long long i = 2; i * i <= num; i++) { if (num % i == 0) { flag = false; break; } } return flag; } long long ipow(long long base, long long exp) { long long result = 1; for (;;) { if (exp & 1) { result *= base; result = result % mod; } exp >>= 1; if (!exp) break; base *= base; base = base % mod; } return result % mod; } long long abs(long long a, long long b) { if ((a - b) > 0) return (a - b); else return (b - a); } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; int mx[n + 1], mn[n + 1]; memset(mn, -1, sizeof mn); memset(mx, -1, sizeof mx); for (int i = 0; i < k; i++) { int k; cin >> k; if (mn[k] == -1) mn[k] = i; mx[k] = i; } int ans = 0; for (int i = 1; i <= n; i++) { if (mn[i] == -1 && i != 1 && i != n) ans += 3; else if (mn[i] == -1 && (i == 1 || i == n)) ans += 2; else { if (i != 1) { if (mn[i - 1] == -1) ans++; else { if (mx[i - 1] < mn[i]) ans++; } } if (i != n) { if (mn[i + 1] == -1) ans++; else { if (mx[i + 1] < mn[i]) { ans++; } } } } } cout << ans; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const int INF = 1 << 30; const long long LINF = 1ll << 60; const int BUFFER_SZ = 1 << 15; const int MOD = 1000 * 1000 * 1000 + 7; char BUFFER[BUFFER_SZ]; int gi() { int x; scanf( %d , &x); return x; } double gd() { double x; scanf( %lf , &x); return x; } long long gll() { long long x; cin >> x; return x; } vector<int> gvi(int n) { vector<int> a; while (n-- > 0) a.push_back(gi()); return a; } string gs() { scanf( %s , BUFFER); return string(BUFFER); } template <class T> void print(vector<T> &x, string format) { format += %c ; for (int i = 0; i < x.size(); ++i) printf(format.c_str(), x[i], i + 1 == x.size() ? n : ); } int c_ins, c_del, c_rep, c_swp; int dp[4444][4444]; int main() { int c_ins = gi(); int c_del = gi(); int c_rep = gi(); int c_swp = gi(); string a = gs(); string b = gs(); int prev[256]; memset((prev), (0), sizeof(prev)); for (int i = 0; i <= a.size(); ++i) { int last = 0; for (int j = 0; j <= b.size(); ++j) { if (!i) dp[i][j] = j * c_ins; else if (!j) dp[i][j] = i * c_del; else { dp[i][j] = 1 << 30; int ii = j > 0 ? prev[b[j - 1]] : 0; int jj = last; if (a[i - 1] == b[j - 1]) { dp[i][j] = dp[i - 1][j - 1]; last = j; } int v = min(min(dp[i - 1][j] + c_del, dp[i][j - 1] + c_ins), dp[i - 1][j - 1] + c_rep); if (i && j && ii && jj) { v = min(v, dp[ii - 1][jj - 1] + c_swp + c_del * (i - ii - 1) + c_ins * (j - jj - 1)); } dp[i][j] = min(dp[i][j], v); } } if (i > 0) { prev[a[i - 1]] = i; } } printf( %d n , dp[a.size()][b.size()]); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
// that should not work.
//
// The given generate loops should attempt to access invalid bits of mask and
// trigger errors.
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
`define MAX_SIZE 3
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, so we can immediately finish
always @(posedge clk) begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that all have errors in applying short-circuting to
// generate "if" conditionals.
// Attempt to access invalid bits of MASK in different ways
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE + 1)) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g + 1]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise AND
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < (SIZE)) & MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
// Attempt to short-circuit bitwise OR
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) | ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Bitwise OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n + 1]; for (int i = 1; i < n + 1; i++) { cin >> a[i]; } int s = 0; int arr[n + 1], max; max = INT_MIN; memset(arr, 0, sizeof(arr)); for (int i = 1; i < n + 1; i++) { if (a[i] == 1) { arr[i] = arr[i - 1] + 1; } else { arr[i] = 0; } if (arr[i] > max) { max = arr[i]; } } if (arr[n] != 0) { int j = 1; while (arr[j] != 0) { arr[n]++; j++; } if (arr[n] > max) { max = arr[n]; } } cout << max; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLYGATE4SD2_PP_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd2 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD2_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module tx_sm_tb ();
`include "dut.v"
integer i;
initial
begin
//$dumpfile("test.vcd");
//$dumpvars(0,tx_sm_tb,U_tx_sm);
end
initial
begin
#15 reset = 0;
mode = 0;
// Will initially wait IFG before making any transmissions
// Set fifo_count to 1 and check IFG delay before tx_enable is asserted
// Clock flips every 5ns -> 10ns period
// tx_enable_monitor will take care of these checks
fifo_count = 1;
#110
expected_tx_enable = 1;
// MAC should then start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG and send the same packet again
#120
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Followed by the frame data we supply
// 10 Bytes
fork
// Data Start
data.sync_write(8'h00);
data_start.sync_write(1);
join
data.assert(tx_data == 0, "DATA START");
for (i = 1; i < 9; i = i + 1)
begin
data.sync_write(i);
data.assert(tx_data == i, "DATA");
end
fork
// Data End
data.sync_write(8'h09);
data_end.sync_write(1);
join
data.assert(tx_data == 8'h09, "DATA END");
// Followed by padding
// 50 bytes
for (i = 0; i < 50; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 0, "PADDING");
end
// Followed by CRC
// 4 bytes
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'hAA, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
data.sync_read(tempdata);
data.assert(tempdata == 8'h91, "CRC");
expected_tx_enable = 0;
// Wait IFG
#110
// Assert Carrier Sense - Should defer
carrier_sense = 1;
// Delay to simulate reception of a packet
#1000
// Deassert Carrier Sense
carrier_sense = 0;
// Wait IFG
#110
expected_tx_enable = 1;
// MAC should start transmitting the preamble
// 7 bytes
for (i = 0; i < 7; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h55, "Preamble");
expected_tx_enable = 1;
end
// Followed by the SFD
// 1 byte
// Insert a collision
collision = 1;
data.sync_read(tempdata);
data.assert(tempdata == 8'hD5, "SFD");
// Should transmit a 16 byte jamming signal
for (i = 0; i < 16; i = i + 1)
begin
data.sync_read(tempdata);
data.assert(tempdata == 8'h01, "COLLISION DETECTED- JAMMING");
end
// Then stop transmitting
expected_tx_enable = 0;
// And deassert collision detect signal
collision = 0;
// Should go to a back off state and wait a random amount of time before reattempting transmission
// TODO: Test BACKOFF
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned long long dsum(unsigned long long n) { unsigned long long res = 0; while (n) { res += n % 10; n /= 10; } return res; } int main() { unsigned long long n, s; cin >> n >> s; unsigned long long dif = n - dsum(n); if (dif < s) cout << 0 << endl; else { unsigned long long l = 1, h = n; while (h - l > 0) { unsigned long long mid = l + (h - l) / 2; unsigned long long x = dsum(mid); dif = mid - x; if (dif < s) { l = mid + 1; } else h = mid; } if (n - dsum(l) >= s) l--; cout << n - l << endl; } }
|
#include <bits/stdc++.h> namespace my_std { using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); template <typename T> inline T rnd(T first, T second) { return uniform_int_distribution<T>(first, second)(rng); } template <typename T> inline bool chkmax(T &x, T y) { return x < y ? x = y, 1 : 0; } template <typename T> inline bool chkmin(T &x, T y) { return x > y ? x = y, 1 : 0; } template <typename T> inline void read(T &t) { t = 0; char f = 0, ch = getchar(); double d = 0.1; while (ch > 9 || ch < 0 ) f |= (ch == - ), ch = getchar(); while (ch <= 9 && ch >= 0 ) t = t * 10 + ch - 48, ch = getchar(); if (ch == . ) { ch = getchar(); while (ch <= 9 && ch >= 0 ) t += d * (ch ^ 48), d *= 0.1, ch = getchar(); } t = (f ? -t : t); } template <typename T, typename... Args> inline void read(T &t, Args &...args) { read(t); read(args...); } char __sr[1 << 21], __z[20]; int __C = -1, __zz = 0; inline void Ot() { fwrite(__sr, 1, __C + 1, stdout), __C = -1; } inline void print(int x) { if (__C > 1 << 20) Ot(); if (x < 0) __sr[++__C] = - , x = -x; while (__z[++__zz] = x % 10 + 48, x /= 10) ; while (__sr[++__C] = __z[__zz], --__zz) ; __sr[++__C] = n ; } void file() {} inline void chktime() {} long long ksm(long long x, int y) { long long ret = 1; for (; y; y >>= 1, x = x * x) if (y & 1) ret = ret * x; return ret; } } // namespace my_std using namespace my_std; int n, T, _cnt; pair<int, int> D[403030 >> 1]; int _w[403030 >> 1]; void init() { static int first[403030], second[403030], p[403030], _l[403030], _r[403030]; for (int i = (1); i <= (n); i++) read(first[i], second[i]), chkmax(first[i], 0); int m = 0, K = 0; for (int i = (1); i <= (n); i++) if (second[i] >= first[i] && second[i] - first[i] < 2 * T - 2) p[++m] = first[i], p[++m] = second[i], ++K, _l[K] = first[i], _r[K] = second[i]; else if (second[i] >= first[i]) ++_cnt; sort(p + 1, p + m + 1); m = unique(p + 1, p + m + 1) - p - 1; n = K; for (int i = (1); i <= (n); i++) first[i] = _l[i], second[i] = _r[i]; for (int i = (1); i <= (n); i++) first[i] = lower_bound(p + 1, p + m + 1, first[i]) - p, second[i] = lower_bound(p + 1, p + m + 1, second[i]) - p; long long dt = p[1]; p[1] = 0; for (int i = (2); i <= (m); i++) if ((p[i] -= dt) > p[i - 1] + 2ll * T) dt += p[i] - (p[i - 1] + 2 * T), p[i] = p[i - 1] + 2 * T; for (int i = (1); i <= (n); i++) D[i] = make_pair(p[first[i]], p[second[i]] + 1); sort(D + 1, D + n + 1); for (int i = (1); i <= (n); i++) { int second = D[i].second; int x = lower_bound(D + 1, D + n + 1, make_pair(second, -1)) - D; ++_w[i], --_w[x]; } for (int i = (1); i <= (n); i++) _w[i] += _w[i - 1]; } vector<pair<int, int> > Dec[403030 << 1]; struct hh { int tp, ti, first, second; hh(int a, int b, int c, int d) { tp = a, ti = b, first = c, second = d; } const bool operator<(const hh &a) const { return ti == a.ti ? tp < a.tp : ti < a.ti; } }; vector<hh> op[403030 << 1]; vector<pair<int, int> > inc[403030 << 1]; const int Tree = 403030 * 35; int ch[Tree][2], mx[Tree], cc; int root[403030 << 1]; void add(int &k, int first, int second, int x, int y, int w) { if (!k) return; int kk = k; k = ++cc; ch[k][0] = ch[kk][0], ch[k][1] = ch[kk][1], mx[k] = mx[kk]; if (x <= first && second <= y) return mx[k] += w, void(); int tg = mx[k] - max(mx[ch[k][0]], mx[ch[k][1]]), mid = (first + second) >> 1; if (x <= mid) add(ch[k][0], first, mid, x, y, w); if (y > mid) add(ch[k][1], mid + 1, second, x, y, w); mx[k] = tg + max(mx[ch[k][0]], mx[ch[k][1]]); } int query(int k, int first, int second, int x, int y) { if (!k) return -1e7; if (x <= first && second <= y) return mx[k]; int tg = mx[k] - max(mx[ch[k][0]], mx[ch[k][1]]), mid = (first + second) >> 1, res = -1e7; if (x <= mid) chkmax(res, query(ch[k][0], first, mid, x, y)); if (y > mid) chkmax(res, query(ch[k][1], mid + 1, second, x, y)); return res + tg; } void modify(int &k, int first, int second, int x, int w) { int kk = k; k = ++cc; mx[k] = mx[kk], ch[k][0] = ch[kk][0], ch[k][1] = ch[kk][1]; if (first == second) return chkmax(mx[k], w), void(); int mid = (first + second) >> 1; int tg = (ch[k][0] || ch[k][1]) ? mx[k] - max(mx[ch[k][0]], mx[ch[k][1]]) : 0; w -= tg; if (x <= mid) modify(ch[k][0], first, mid, x, w); else modify(ch[k][1], mid + 1, second, x, w); mx[k] = max(mx[ch[k][0]], mx[ch[k][1]]) + tg; } vector<pair<int, int> > V[3]; void rebuild(int k, int first, int second, int tg, int tp) { if (!k) return; if (first == second) return V[tp].push_back(make_pair(first, tg + mx[k])); int mid = (first + second) >> 1; tg += mx[k] - max(mx[ch[k][0]], mx[ch[k][1]]); rebuild(ch[k][0], first, mid, tg, tp), rebuild(ch[k][1], mid + 1, second, tg, tp); } void Rebuild(int second) { int first = max(0, second - 2); for (int i = (0); i <= (2); i++) V[i].clear(); for (int i = (first); i <= (second); i++) rebuild(root[i], 0, T - 1, 0, i - first); cc = 0; for (int i = (first); i <= (second); i++) { root[i] = 0; for (auto t : V[i - first]) modify(root[i], 0, T - 1, t.first, t.second); } } int main() { file(); read(n, T); init(); for (int i = (1); i <= (n); i++) { op[D[i].first / T].push_back(hh(i, D[i].first % T, 0, 0)); if (D[i].second - D[i].first > T) { auto add = [&](int first, int second, int re) { Dec[first / T].push_back( make_pair(first % T, (second % T == 0 ? T : second % T))), op[re / T].push_back(hh(-1, re % T, first, second)); }; int first = D[i].first, second = D[i].second - T; if (first % T < second % T || second % T == 0) add(first, second, D[i].second); else add(first, first - first % T + T, D[i].second), add(second - second % T, second, D[i].second); } int first = D[i].first, second = D[i].second; while (first - first % T + T <= second) inc[first / T].push_back(make_pair(first % T, T)), first = first - first % T + T; if (first < second) inc[first / T].push_back(make_pair(first % T, second % T)); } mx[0] = -1e7; const int RE = n / 10; int ti = 0; for (int i = (0); i <= (4 * n); i++) { if (i) root[i] = root[i - 1]; for (auto p : inc[i]) { add(root[i], 0, T - 1, p.first, p.second - 1, 1); if ((++ti) > RE) ti = 0, Rebuild(i); } sort(op[i].begin(), op[i].end()); for (auto p : op[i]) { ++ti; if (p.tp == -1) add(root[p.first / T], 0, T - 1, p.first % T, (p.second % T == 0 ? T - 1 : p.second % T - 1), 1); else { int x = p.ti, w = 0; if (i > 0) chkmax(w, query(root[i - 1], 0, T - 1, 0, x)); if (i > 1) chkmax(w, mx[root[i - 2]]); modify(root[i], 0, T - 1, x, w + _w[p.tp]); } if (ti > RE) ti = 0, Rebuild(i); } for (auto p : Dec[i]) { add(root[i], 0, T - 1, p.first, p.second - 1, -1); if ((++ti) > RE) ti = 0, Rebuild(i); } } cout << max(0, mx[root[n * 4]]) + _cnt; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long num[505]; int n; long long minval = 0x3f3f3f3f3f3f3f3fll; long long check(int x) { long long ans = 0; for (int i = 1; i <= n; i++) { if (num[i] % x == 0) { ans += num[i] / x; } else { if (num[i] % x + num[i] / x >= x - 1) { ans += num[i] / x + 1; } else { return 0; } } } return ans; } void solve(int x) { long long t = check(x); if (t) { printf( %I64d n , t); exit(0); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %I64d , &num[i]); minval = min(minval, num[i]); } long long t = (long long)sqrt(minval); for (long long i = 1; i <= t; i++) { solve(minval / i + 1); solve(minval / i); solve(minval / i - 1); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_BLACKBOX_V
|
#include <bits/stdc++.h> const int MAX_VAL = 1000000; struct AInt { int sum; int minSum; }; AInt aInt[1 << 21]; void update(int index, int left, int right, int addIndex, int addValue) { if (left == right) { aInt[index].sum += addValue; aInt[index].minSum += addValue; } else { int avg = (left + right) / 2; if (addIndex <= avg) { update(2 * index + 0, left, avg, addIndex, addValue); } else { update(2 * index + 1, avg + 1, right, addIndex, addValue); } aInt[index].sum = aInt[2 * index].sum + aInt[2 * index + 1].sum; aInt[index].minSum = std::min(aInt[2 * index].minSum + aInt[2 * index + 1].sum, aInt[2 * index + 1].minSum); } } int query(int index, int suffSum, int left, int right) { if (aInt[index].minSum + suffSum >= 0) { return -1; } else if (left == right) { return left; } else { int avg = (left + right) / 2; int q2 = query(2 * index + 1, suffSum, avg + 1, right); if (q2 == -1) { int q1 = query(2 * index + 0, aInt[2 * index + 1].sum + suffSum, left, avg); return q1; } else { return q2; } } } void update(int value, int sign) { update(1, 1, MAX_VAL, value, sign); } int query() { return query(1, 0, 1, MAX_VAL); } int main() { int n, m; scanf( %d%d , &n, &m); int a[n]; int b[m]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); update(a[i], -1); } for (int i = 0; i < m; i++) { scanf( %d , &b[i]); update(b[i], +1); } int q; scanf( %d , &q); for (int z = 0; z < q; z++) { int t, i, x; scanf( %d%d%d , &t, &i, &x); i--; if (t == 1) { update(a[i], +1); a[i] = x; update(a[i], -1); } else { update(b[i], -1); b[i] = x; update(b[i], +1); } printf( %d n , query()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6; int n, t[1000001]; struct data { int num, loc, vis; } b[1000001]; int a[1000001]; int lowbit(int x) { return x & (-x); } int Query(int x) { int sum = 0; while (x > 0) { sum = max(sum, t[x]); x -= lowbit(x); } return sum; } void Add(int x, int va) { while (x <= N) { t[x] = max(t[x], va); x += lowbit(x); } } bool cmp(data p, data q) { return p.num < q.num; } bool cmp2(data p, data q) { return p.vis < q.vis; } int work() { memset(t, 0, sizeof(t)); for (int i = 1; i <= n; i++) { b[i].num = a[i]; b[i].vis = i; } sort(b + 1, b + n + 1, cmp); for (int i = 1; i <= n; i++) b[i].loc = n + 1 - i; sort(b + 1, b + n + 1, cmp2); int ans = 0; for (int i = 1; i <= n; i++) { int nowans = Query(b[i].loc); Add(b[i].loc, i); if (nowans == 0) continue; ans = max(ans, b[i].num ^ b[nowans].num); } return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int ans = work(); for (int i = 1; i <= n / 2; i++) swap(a[i], a[n + 1 - i]); ans = max(ans, work()); printf( %d n , ans); return 0; }
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
// Copyright 2013 David Turnbull AE9RB
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 03/11/2013 at 13:09
// Component: FracN
module FracN (
input clk
);
//`#start body` -- edit after this line, do not edit this line
// Special thanks to Michael Hightower KF6SJ for showing me how
// to create a Fractional-N Sigma Delta Modulator in the PSoC.
// This version is simpified to reduce PLA usage.
// A more complete implementation is available from:
// http://www.simplecircuits.com/SimpleSDR.html
wire [7:0] fHigh;
wire [7:0] fLow;
wire [13:0] frac = {fHigh [5:0], fLow [7:0]};
reg [13:0] acc1;
reg [13:0] acc2;
wire [14:0] adder1 = acc1 + frac;
wire [14:0] adder2 = acc2 + acc1;
reg minus1;
reg [6:0] pOut;
cy_psoc3_control #(.cy_init_value (8'h3D), .cy_force_order(`TRUE))
FRAC_HI ( .control(fHigh));
cy_psoc3_control #(.cy_init_value (8'hF4), .cy_force_order(`TRUE))
FRAC_LO ( .control(fLow));
cy_psoc3_status #(.cy_md_select(8'h00), .cy_force_order(`TRUE))
PLL_P ( .status( {1'b0, pOut} ));
always @(posedge clk)
begin
acc1 <= adder1 [13:0];
acc2 <= adder2 [13:0];
minus1 <= adder2 [14];
pOut <= 8'h13 + {6'b0, adder1 [14]} + {6'b0, adder2 [14]} + {7{minus1}};
end
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// mv_sie_read O 64
// mav_sie_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// mav_sie_write_misa I 28
// mav_sie_write_wordxl I 64
// EN_reset I 1
// EN_mav_write I 1
// EN_mav_sie_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
// (mav_sie_write_misa, mav_sie_write_wordxl) -> mav_sie_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIE(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
mv_sie_read,
mav_sie_write_misa,
mav_sie_write_wordxl,
EN_mav_sie_write,
mav_sie_write);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// value method mv_sie_read
output [63 : 0] mv_sie_read;
// actionvalue method mav_sie_write
input [27 : 0] mav_sie_write_misa;
input [63 : 0] mav_sie_write_wordxl;
input EN_mav_sie_write;
output [63 : 0] mav_sie_write;
// signals for module outputs
wire [63 : 0] mav_sie_write, mav_write, mv_read, mv_sie_read;
// register rg_mie
reg [11 : 0] rg_mie;
reg [11 : 0] rg_mie$D_IN;
wire rg_mie$EN;
// rule scheduling signals
wire CAN_FIRE_mav_sie_write,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
WILL_FIRE_mav_sie_write,
WILL_FIRE_mav_write,
WILL_FIRE_reset;
// inputs to muxes for submodule ports
wire [11 : 0] MUX_rg_mie$write_1__VAL_3;
// remaining internal signals
wire [11 : 0] mie__h92, x__h458, x__h883;
wire seie__h123,
seie__h544,
ssie__h117,
ssie__h538,
stie__h120,
stie__h541,
ueie__h122,
ueie__h543,
usie__h116,
usie__h537,
utie__h119,
utie__h540;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, rg_mie } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, mie__h92 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// value method mv_sie_read
assign mv_sie_read = { 52'd0, x__h458 } ;
// actionvalue method mav_sie_write
assign mav_sie_write = { 52'd0, x__h883 } ;
assign CAN_FIRE_mav_sie_write = 1'd1 ;
assign WILL_FIRE_mav_sie_write = EN_mav_sie_write ;
// inputs to muxes for submodule ports
assign MUX_rg_mie$write_1__VAL_3 =
{ rg_mie[11],
1'b0,
seie__h544,
ueie__h543,
rg_mie[7],
1'b0,
stie__h541,
utie__h540,
rg_mie[3],
1'b0,
ssie__h538,
usie__h537 } ;
// register rg_mie
always@(EN_mav_write or
mie__h92 or
EN_reset or EN_mav_sie_write or MUX_rg_mie$write_1__VAL_3)
case (1'b1)
EN_mav_write: rg_mie$D_IN = mie__h92;
EN_reset: rg_mie$D_IN = 12'd0;
EN_mav_sie_write: rg_mie$D_IN = MUX_rg_mie$write_1__VAL_3;
default: rg_mie$D_IN = 12'b101010101010 /* unspecified value */ ;
endcase
assign rg_mie$EN = EN_mav_write || EN_mav_sie_write || EN_reset ;
// remaining internal signals
assign mie__h92 =
{ mav_write_wordxl[11],
1'b0,
seie__h123,
ueie__h122,
mav_write_wordxl[7],
1'b0,
stie__h120,
utie__h119,
mav_write_wordxl[3],
1'b0,
ssie__h117,
usie__h116 } ;
assign seie__h123 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign seie__h544 = mav_sie_write_misa[18] && mav_sie_write_wordxl[9] ;
assign ssie__h117 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign ssie__h538 = mav_sie_write_misa[18] && mav_sie_write_wordxl[1] ;
assign stie__h120 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign stie__h541 = mav_sie_write_misa[18] && mav_sie_write_wordxl[5] ;
assign ueie__h122 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign ueie__h543 = mav_sie_write_misa[13] && mav_sie_write_wordxl[8] ;
assign usie__h116 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign usie__h537 = mav_sie_write_misa[13] && mav_sie_write_wordxl[0] ;
assign utie__h119 = mav_write_misa[13] && mav_write_wordxl[4] ;
assign utie__h540 = mav_sie_write_misa[13] && mav_sie_write_wordxl[4] ;
assign x__h458 =
{ 2'd0, rg_mie[9:8], 2'd0, rg_mie[5:4], 2'd0, rg_mie[1:0] } ;
assign x__h883 =
{ 2'd0,
seie__h544,
ueie__h543,
2'd0,
stie__h541,
utie__h540,
2'd0,
ssie__h538,
usie__h537 } ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_mie <= `BSV_ASSIGNMENT_DELAY 12'd0;
end
else
begin
if (rg_mie$EN) rg_mie <= `BSV_ASSIGNMENT_DELAY rg_mie$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_mie = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIE
|
module stimulus;
parameter data_width = 32;
parameter address_width = 32;
parameter address_depth = 2048;
parameter opcode_width = 7;
parameter reg_addr_width = 5;
parameter immediate_width = 15;
parameter period = 20;
parameter delay = 1;
// Define the input and output file names
/*
parameter program_code = "01_gcd_plain-bin.dat";
parameter program_data = "01_gcd_plain-data.dat";
parameter program_code = "02_mult-bin.dat";
parameter program_data = "02_mult-data.dat";
parameter program_code = "04_lcm-bin.dat";
parameter program_data = "04_lcm-data.dat";
parameter program_code = "09_fabonacci-bin.dat";
parameter program_data = "09_fabonacci-data.dat";
parameter program_code = "12_factional_2-bin.dat";
parameter program_data = "12_factional_2-data.dat";
*/
parameter program_code = "03_division-bin.dat";
parameter program_data = "03_division-data.dat";
parameter sdf_file = "Processor.sdf";
parameter fsdb_syn_file = "risc_syn.fsdb";
parameter fsdb_file = "risc.fsdb";
parameter vcd_syn_file = "risc_syn.vcd";
parameter vcd_file = "risc.vcd";
parameter instr_count = 20;
parameter HALT = 32'b11111111111111111111111111111111;
reg clk;
reg rst_n;
wire [31:0] pPC, pdatain, paddr;
wire pwen, poen;
// signals for instruction memory IM
reg im_cen;
reg im_wen;
reg [10:0] im_addr;
reg [31:0] im_datain;
reg im_oen;
wire [31:0] im_dataout;
// signals for data memory DM
reg dm_cen;
reg dm_wen;
reg [10:0] dm_addr;
reg [31:0] dm_datain;
reg dm_oen;
wire [31:0] dm_dataout;
reg [data_width - 1:0] pc;
reg [data_width - 1:0] pc_pre;
reg [data_width - 1:0] ir;
reg [opcode_width - 1:0] opcode;
reg [reg_addr_width - 1:0] dr, sa, sb, sh;
reg signed [immediate_width - 1:0] imm;
RAM2Kx32 #(
.preload_file(program_code)
) IMEM (
.Q(im_dataout),
.CLK(clk),
.CEN(im_cen),
.WEN(im_wen),
.A(im_addr),
.D(im_datain),
.OEN(im_oen)
);
RAM2Kx32 #(
.preload_file(program_data)
) DMEM (
.Q(dm_dataout),
.CLK(clk),
.CEN(dm_cen),
.WEN(dm_wen),
.A(dm_addr),
.D(dm_datain),
.OEN(dm_oen)
);
SingleCycleProcessor processor (
.PC(pPC),
.datain(pdatain),
.address(paddr),
.MW(pwen),
.MR(poen),
.instruction(im_dataout),
.dataout(dm_dataout),
.clk(clk),
.reset_n(rst_n)
);
always #(period/2) clk = ~clk;
initial begin
`ifdef NETLIST
$sdf_annotate(sdf_file, processor);
`ifdef FSDB
$fsdbDumpfile(fsdb_syn_file);
$fsdbDumpvars;
`else
$dumpfile(vcd_syn_file);
$dumpvars(0, stimulus);
`endif
`else
`ifdef FSDB
$fsdbDumpfile(fsdb_file);
$fsdbDumpvars;
`else
$dumpfile(vcd_file);
$dumpvars(0, stimulus);
`endif
`endif
end
initial begin
// initialization
clk = 1;
rst_n = 1'b1;
im_cen = 0;
im_wen = 1'b1;
im_oen = 1'b1;
dm_cen = 0;
dm_wen = 1'b1;
dm_oen = 1'b1;
pc = 0;
pc_pre = 0;
#(period) rst_n = 0;
im_oen = 1'b0;
im_addr = 0;
dm_datain = pdatain;
dm_addr = paddr;
dm_wen = pwen;
dm_oen = poen;
#(period*10) rst_n = 1;
while (im_dataout != HALT) begin
im_addr = pPC;
dm_datain = pdatain;
dm_addr = paddr;
dm_wen = pwen;
dm_oen = poen;
#(period);
end
#(period) idle;
#(period) idle;
#(period) idle;
#(period*4);
$finish;
end
// tasks
task idle;
begin
im_wen = 1;
im_oen = 1;
im_datain = 32'bz;
end
endtask
task dm_nop;
begin
dm_wen = 1;
dm_oen = 1;
dm_datain = 32'bz;
end
endtask
always @(posedge clk) begin
pc_pre = #(delay) pc;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_2_V
`define SKY130_FD_SC_HS__DLXBN_2_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_2 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_2_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_0_0 (
Din,
Dout
);
input wire [39 : 0] Din;
output wire [39 : 0] Dout;
xlslice #(
.DIN_WIDTH(40),
.DIN_FROM(39),
.DIN_TO(0)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sram_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 10: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 10: 0] data_out;
wire [ 10: 0] out_port;
wire [ 10: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {11 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[10 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
`include "hexOnHex.v"
`include "Implementation/mux2_1.sv"
`include "Implementation/mux4_1.sv"
`include "Implementation/mux8_1.sv"
`include "Implementation/mux32_1.sv"
`include "Implementation/DFlipFlop.sv"
`include "Implementation/registerSingle.sv"
`include "Implementation/register.sv"
`include "Implementation/decoder5_32.sv"
//`include "DE1_SoCPhase1.v"
`include "adder_subtractor.v"
`include "flag.v"
`include "adder16b.v"
`include "adder4b.v"
`include "fullAdder1b.v"
`include "lookAhead4b.v"
`include "addition.v"
`include "subtract.v"
`include "andGate.v"
`include "orGate.v"
`include "xorGate.v"
`include "setLT.v"
`include "shiftll.v"
`include "ALUnit.sv"
`include "SRAM2Kby16.v"
`include "registerFile.sv"
module DE1_SoCPhase1 (CLOCK_50, LEDR, HEX0, HEX1, HEX2, HEX3, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
input [9:0] SW;
input [3:0] KEY;
reg [31:0] AL, BL, A, B, data;
reg [1:0] count;
reg enter, eHold;
wire clk, run, res, Z, V, C, N;
wire [31:0] dataOut;
wire [3:0]digits;
reg [2:0] oper;
reg [1:0] sel;
initial begin
oper = 0;
sel = 0;
enter = 0;
eHold = 0;
count = 0;
AL = 0;
BL = 0;
A = 0;
B = 0;
data = 0;
end
assign LEDR[3] = Z;
assign LEDR[2] = V;
assign LEDR[1] = C;
assign LEDR[0] = N;
assign clk = CLOCK_50;
//Interpreted by the system as an Enter. When Enter is pressed
// the ALU will read the state of the input switches and respond accordingly
//assign enter = ~KEY[0];
//Directs the ALU to perform the specified operation and display the results.
assign run = ~KEY[1];
// sets the hex digits
assign digits = SW[3:0];
// Specify whether operand A or B is to be entered or the result is to be displayed
// controls the hex
hexOnHex hex0(data[3:0], HEX0);
hexOnHex hex1(data[7:4], HEX1);
hexOnHex hex2(data[11:8], HEX2);
hexOnHex hex3(data[15:12], HEX3);
ALUnit alzheimers (clk,oper, A, B, dataOut,Z,V,C,N);
//ALuBe alzheimers (clk,oper, A, B, dataOut,Z,V,C,N);
always @(posedge clk) begin
// hex display done
case(sel)
0: data <= AL;
1: data <= BL;
default: data <= dataOut;
endcase
if(~KEY[0]) begin
if(eHold) begin
enter <= 0;
//eHold <=0;
end else begin
enter <= 1;
//eHold <= 1;
end
eHold <= 1;
end
else begin
eHold <= 0;
enter <= 0;
end
if(enter) begin
if(sel != SW[9:8]) begin
sel <= SW[9:8];
count <= 0;
end else begin
if(sel == 0)
case(count)
0: AL[3:0] = digits;
1: AL[7:4] = digits;
2: AL[11:8] = digits;
3: AL[15:12] = digits;
endcase
else if(sel == 1)
case(count)
0: BL[3:0] = digits;
1: BL[7:4] = digits;
2: BL[11:8] = digits;
3: BL[15:12] = digits;
endcase
count = count + 1;
end
end
if(run) begin
oper <= SW[6:4];
A <= AL;
B <= BL;
end
end
endmodule
module interfaceTest();
wire clk; // connect to system 50 MHz clock
wire [9:0] LEDR;
wire [9:0] SW;
wire [3:0] KEY;
wire [6:0] HEX0;
wire [6:0] HEX1;
wire [6:0] HEX2;
wire [6:0] HEX3;
DE1_SoCPhase1 dut (clk, LEDR, HEX0, HEX1, HEX2, HEX3, SW, KEY);
phase1Tester test (clk, SW, KEY);
initial begin
$dumpfile("Phase1Test.vcd");
$dumpvars(1, dut);
end
endmodule
module phase1Tester(clk, SW, KEY);
output reg clk;
output reg [9:0] SW;
output reg [3:0] KEY;
reg [2:0] control;
initial begin
control = 0;
SW = 0;
KEY = 15;
end
//controls = SW[6:4];
//inVal = SW[3:0];
//sel = SW[9:8];
//enter = ~KEY[0];
//run = ~KEY[1];
parameter [2:0] NOP = 3'b000, ADD= 3'b001, SUB = 3'b010, AND = 3'b011, OR = 3'b100, XOR = 3'b101, SLT = 3'b110, SLL = 3'b111;
parameter d = 20;
// Set up the clocking
always #(d/2) clk= ~clk;
initial begin
$display("clk \t SW \t KEY ");
#d
clk =0;
end
// Set up the inputs to the design
initial begin
$monitor("%b \t %b \t %b \t %b", clk,SW, KEY, $time);
/*//#(d*3); //SW[9:8] = 0; //KEY[0] =0;
//#d; //KEY[0]= 1;
//#d;
#d; SW[9:8] = 1; SW[3:0] =2;#d; #d; #d; KEY[0] = 0;//set value of B
#d;#d; KEY[0] = 1;
#d;
#d; SW[9:8] = 0; SW[3:0] = 1;#d;#d; KEY[0]= 0; //set value of A
#d#d; KEY[0] = 1;
#d;
// #d; SW[3:0] = 2; KEY[0] = 0;
// #d; KEY[0] = 1;
// #d;
#d; SW[9:8] = 3; KEY[0] = 0;
#d#d; KEY[0] = 1; // display result
#d;*/
#d SW[3:0] = 1; KEY[0] = 0; #d KEY[0] = 1;
#d SW[8] = 1; KEY[0] = 0; #d KEY[0] = 1;
#d SW[3:0] = 2; KEY[0] = 0; #d KEY[0] = 1;
#d SW[9] = 1; KEY[0] = 0; #d KEY[0] = 1;
// operation tests
#d; SW[6:4] = NOP; KEY[1] = 0;
#d; SW[6:4] = ADD;
#d; SW[6:4] = SUB;
#d; SW[6:4] = AND;
#d; SW[6:4] = OR;
#d; SW[6:4] = XOR;
#d; SW[6:4] = SLT;
#d; SW[6:4] = SLL;
#(d*3);
$stop;
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N, K; bool good[1050]; int main() { scanf( %d , &N); for (int i = 2; i <= N; i++) { bool isp = true; for (int j = 2; j < i; j++) if (i % j == 0) { isp = false; int x = i; while (x % j == 0) x /= j; if (x == 1) good[i] = true; break; } if (isp) good[i] = true; if (good[i]) ++K; } printf( %d n , K); for (int i = 2; i <= N; i++) if (good[i]) printf( %d , i); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_TB_V
`define SKY130_FD_SC_HVL__O21AI_TB_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o21ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hvl__o21ai dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_ms__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_ms__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_SYMBOL_V
`define SKY130_FD_SC_HS__OR4BB_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_SYMBOL_V
|
/*
eTeak synthesiser for the Balsa language
Copyright (C) 2012-2016 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Mahdi Jelodari <>
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
`define HAS_GO 1
`define HAS_DONE 0
`define HAS_INOUT 1
`define DUT teak_top
`include "eteak_inclusions.v"
`include "encode.v"
module my_top;
initial begin
tkr_monitor_ctrl.report_filename = "encode.report";
tkr_monitor_ctrl.report_spacer_links = 1;
tkr_monitor_ctrl.trace = 1;
tkr_monitor_ctrl.open_report_file;
tkr_monitor_ctrl.finish_after_report = 1;
$dumpfile ("encode.vcd");
$dumpvars (2, top);
#5000;
tkr_monitor_ctrl.report;
end
endmodule
|
// Actel Corporation Proprietary and Confidential
// Copyright 2007 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 6419 $
// SVN $Date: 2009-02-04 04:34:22 -0800 (Wed, 04 Feb 2009) $
`timescale 1ns/100ps
module
BFM_AHBL
(
SYSCLK
,
SYSRSTN
,
HADDR
,
HCLK
,
HRESETN
,
HBURST
,
HMASTLOCK
,
HPROT
,
HSIZE
,
HTRANS
,
HWRITE
,
HWDATA
,
HRDATA
,
HREADY
,
HRESP
,
HSEL
,
INTERRUPT
,
GP_OUT
,
GP_IN
,
EXT_WR
,
EXT_RD
,
EXT_ADDR
,
EXT_DATA
,
EXT_WAIT
,
FINISHED
,
FAILED
)
;
parameter
VECTFILE
=
"test.vec"
;
parameter
MAX_INSTRUCTIONS
=
16384
;
parameter
MAX_STACK
=
1024
;
parameter
MAX_MEMTEST
=
65536
;
parameter
TPD
=
1
;
parameter
DEBUGLEVEL
=
-
1
;
parameter
ARGVALUE0
=
0
;
parameter
ARGVALUE1
=
0
;
parameter
ARGVALUE2
=
0
;
parameter
ARGVALUE3
=
0
;
parameter
ARGVALUE4
=
0
;
parameter
ARGVALUE5
=
0
;
parameter
ARGVALUE6
=
0
;
parameter
ARGVALUE7
=
0
;
parameter
ARGVALUE8
=
0
;
parameter
ARGVALUE9
=
0
;
parameter
ARGVALUE10
=
0
;
parameter
ARGVALUE11
=
0
;
parameter
ARGVALUE12
=
0
;
parameter
ARGVALUE13
=
0
;
parameter
ARGVALUE14
=
0
;
parameter
ARGVALUE15
=
0
;
parameter
ARGVALUE16
=
0
;
parameter
ARGVALUE17
=
0
;
parameter
ARGVALUE18
=
0
;
parameter
ARGVALUE19
=
0
;
parameter
ARGVALUE20
=
0
;
parameter
ARGVALUE21
=
0
;
parameter
ARGVALUE22
=
0
;
parameter
ARGVALUE23
=
0
;
parameter
ARGVALUE24
=
0
;
parameter
ARGVALUE25
=
0
;
parameter
ARGVALUE26
=
0
;
parameter
ARGVALUE27
=
0
;
parameter
ARGVALUE28
=
0
;
parameter
ARGVALUE29
=
0
;
parameter
ARGVALUE30
=
0
;
parameter
ARGVALUE31
=
0
;
parameter
ARGVALUE32
=
0
;
parameter
ARGVALUE33
=
0
;
parameter
ARGVALUE34
=
0
;
parameter
ARGVALUE35
=
0
;
parameter
ARGVALUE36
=
0
;
parameter
ARGVALUE37
=
0
;
parameter
ARGVALUE38
=
0
;
parameter
ARGVALUE39
=
0
;
parameter
ARGVALUE40
=
0
;
parameter
ARGVALUE41
=
0
;
parameter
ARGVALUE42
=
0
;
parameter
ARGVALUE43
=
0
;
parameter
ARGVALUE44
=
0
;
parameter
ARGVALUE45
=
0
;
parameter
ARGVALUE46
=
0
;
parameter
ARGVALUE47
=
0
;
parameter
ARGVALUE48
=
0
;
parameter
ARGVALUE49
=
0
;
parameter
ARGVALUE50
=
0
;
parameter
ARGVALUE51
=
0
;
parameter
ARGVALUE52
=
0
;
parameter
ARGVALUE53
=
0
;
parameter
ARGVALUE54
=
0
;
parameter
ARGVALUE55
=
0
;
parameter
ARGVALUE56
=
0
;
parameter
ARGVALUE57
=
0
;
parameter
ARGVALUE58
=
0
;
parameter
ARGVALUE59
=
0
;
parameter
ARGVALUE60
=
0
;
parameter
ARGVALUE61
=
0
;
parameter
ARGVALUE62
=
0
;
parameter
ARGVALUE63
=
0
;
parameter
ARGVALUE64
=
0
;
parameter
ARGVALUE65
=
0
;
parameter
ARGVALUE66
=
0
;
parameter
ARGVALUE67
=
0
;
parameter
ARGVALUE68
=
0
;
parameter
ARGVALUE69
=
0
;
parameter
ARGVALUE70
=
0
;
parameter
ARGVALUE71
=
0
;
parameter
ARGVALUE72
=
0
;
parameter
ARGVALUE73
=
0
;
parameter
ARGVALUE74
=
0
;
parameter
ARGVALUE75
=
0
;
parameter
ARGVALUE76
=
0
;
parameter
ARGVALUE77
=
0
;
parameter
ARGVALUE78
=
0
;
parameter
ARGVALUE79
=
0
;
parameter
ARGVALUE80
=
0
;
parameter
ARGVALUE81
=
0
;
parameter
ARGVALUE82
=
0
;
parameter
ARGVALUE83
=
0
;
parameter
ARGVALUE84
=
0
;
parameter
ARGVALUE85
=
0
;
parameter
ARGVALUE86
=
0
;
parameter
ARGVALUE87
=
0
;
parameter
ARGVALUE88
=
0
;
parameter
ARGVALUE89
=
0
;
parameter
ARGVALUE90
=
0
;
parameter
ARGVALUE91
=
0
;
parameter
ARGVALUE92
=
0
;
parameter
ARGVALUE93
=
0
;
parameter
ARGVALUE94
=
0
;
parameter
ARGVALUE95
=
0
;
parameter
ARGVALUE96
=
0
;
parameter
ARGVALUE97
=
0
;
parameter
ARGVALUE98
=
0
;
parameter
ARGVALUE99
=
0
;
localparam
OPMODE
=
0
;
localparam
CON_SPULSE
=
0
;
input
SYSCLK
;
input
SYSRSTN
;
output
[
31
:
0
]
HADDR
;
wire
[
31
:
0
]
HADDR
;
output
HCLK
;
wire
HCLK
;
output
HRESETN
;
wire
HRESETN
;
output
[
2
:
0
]
HBURST
;
wire
[
2
:
0
]
HBURST
;
output
HMASTLOCK
;
wire
HMASTLOCK
;
output
[
3
:
0
]
HPROT
;
wire
[
3
:
0
]
HPROT
;
output
[
2
:
0
]
HSIZE
;
wire
[
2
:
0
]
HSIZE
;
output
[
1
:
0
]
HTRANS
;
wire
[
1
:
0
]
HTRANS
;
output
HWRITE
;
wire
HWRITE
;
output
[
31
:
0
]
HWDATA
;
wire
[
31
:
0
]
HWDATA
;
input
[
31
:
0
]
HRDATA
;
input
HREADY
;
input
HRESP
;
output
[
15
:
0
]
HSEL
;
wire
[
15
:
0
]
HSEL
;
input
[
255
:
0
]
INTERRUPT
;
output
[
31
:
0
]
GP_OUT
;
wire
[
31
:
0
]
GP_OUT
;
input
[
31
:
0
]
GP_IN
;
output
EXT_WR
;
wire
EXT_WR
;
output
EXT_RD
;
wire
EXT_RD
;
output
[
31
:
0
]
EXT_ADDR
;
wire
[
31
:
0
]
EXT_ADDR
;
inout
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
EXT_DATA
;
wire
[
31
:
0
]
BFMA1O1OII
;
input
EXT_WAIT
;
output
FINISHED
;
wire
FINISHED
;
output
FAILED
;
wire
FAILED
;
wire
[
31
:
0
]
INSTR_IN
=
{
32
{
1
'b
0
}
}
;
assign
EXT_DATA
=
BFMA1O1OII
;
BFM_MAIN
#
(
OPMODE
,
VECTFILE
,
MAX_INSTRUCTIONS
,
MAX_STACK
,
MAX_MEMTEST
,
TPD
,
DEBUGLEVEL
,
CON_SPULSE
,
ARGVALUE0
,
ARGVALUE1
,
ARGVALUE2
,
ARGVALUE3
,
ARGVALUE4
,
ARGVALUE5
,
ARGVALUE6
,
ARGVALUE7
,
ARGVALUE8
,
ARGVALUE9
,
ARGVALUE10
,
ARGVALUE11
,
ARGVALUE12
,
ARGVALUE13
,
ARGVALUE14
,
ARGVALUE15
,
ARGVALUE16
,
ARGVALUE17
,
ARGVALUE18
,
ARGVALUE19
,
ARGVALUE20
,
ARGVALUE21
,
ARGVALUE22
,
ARGVALUE23
,
ARGVALUE24
,
ARGVALUE25
,
ARGVALUE26
,
ARGVALUE27
,
ARGVALUE28
,
ARGVALUE29
,
ARGVALUE30
,
ARGVALUE31
,
ARGVALUE32
,
ARGVALUE33
,
ARGVALUE34
,
ARGVALUE35
,
ARGVALUE36
,
ARGVALUE37
,
ARGVALUE38
,
ARGVALUE39
,
ARGVALUE40
,
ARGVALUE41
,
ARGVALUE42
,
ARGVALUE43
,
ARGVALUE44
,
ARGVALUE45
,
ARGVALUE46
,
ARGVALUE47
,
ARGVALUE48
,
ARGVALUE49
,
ARGVALUE50
,
ARGVALUE51
,
ARGVALUE52
,
ARGVALUE53
,
ARGVALUE54
,
ARGVALUE55
,
ARGVALUE56
,
ARGVALUE57
,
ARGVALUE58
,
ARGVALUE59
,
ARGVALUE60
,
ARGVALUE61
,
ARGVALUE62
,
ARGVALUE63
,
ARGVALUE64
,
ARGVALUE65
,
ARGVALUE66
,
ARGVALUE67
,
ARGVALUE68
,
ARGVALUE69
,
ARGVALUE70
,
ARGVALUE71
,
ARGVALUE72
,
ARGVALUE73
,
ARGVALUE74
,
ARGVALUE75
,
ARGVALUE76
,
ARGVALUE77
,
ARGVALUE78
,
ARGVALUE79
,
ARGVALUE80
,
ARGVALUE81
,
ARGVALUE82
,
ARGVALUE83
,
ARGVALUE84
,
ARGVALUE85
,
ARGVALUE86
,
ARGVALUE87
,
ARGVALUE88
,
ARGVALUE89
,
ARGVALUE90
,
ARGVALUE91
,
ARGVALUE92
,
ARGVALUE93
,
ARGVALUE94
,
ARGVALUE95
,
ARGVALUE96
,
ARGVALUE97
,
ARGVALUE98
,
ARGVALUE99
)
BFMA1I1OII
(
.SYSCLK
(
SYSCLK
)
,
.SYSRSTN
(
SYSRSTN
)
,
.HADDR
(
HADDR
)
,
.HCLK
(
HCLK
)
,
.PCLK
(
)
,
.HRESETN
(
HRESETN
)
,
.HBURST
(
HBURST
)
,
.HMASTLOCK
(
HMASTLOCK
)
,
.HPROT
(
HPROT
)
,
.HSIZE
(
HSIZE
)
,
.HTRANS
(
HTRANS
)
,
.HWRITE
(
HWRITE
)
,
.HWDATA
(
HWDATA
)
,
.HRDATA
(
HRDATA
)
,
.HREADY
(
HREADY
)
,
.HRESP
(
HRESP
)
,
.HSEL
(
HSEL
)
,
.INTERRUPT
(
INTERRUPT
)
,
.GP_OUT
(
GP_OUT
)
,
.GP_IN
(
GP_IN
)
,
.EXT_WR
(
EXT_WR
)
,
.EXT_RD
(
EXT_RD
)
,
.EXT_ADDR
(
EXT_ADDR
)
,
.EXT_DATA
(
EXT_DATA
)
,
.EXT_WAIT
(
EXT_WAIT
)
,
.CON_ADDR
(
16
'b
0
)
,
.CON_DATA
(
)
,
.CON_RD
(
1
'b
0
)
,
.CON_WR
(
1
'b
0
)
,
.CON_BUSY
(
)
,
.INSTR_OUT
(
)
,
.INSTR_IN
(
INSTR_IN
)
,
.FINISHED
(
FINISHED
)
,
.FAILED
(
FAILED
)
)
;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, sum, num, ans; long long a[200005]; int main() { cin >> n >> m >> k; for (int i = 1; i <= m; i++) cin >> a[i]; sort(a + 1, a + m + 1); sum = 0, num = 1, ans = 1; for (int i = 2; i <= m; i++) { if ((a[i] - 1 - sum) / k != (a[i - 1] - 1 - sum) / k) { ans++; sum += num; num = 1; } else num++; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; string s; int n, ans = 0; vector<pair<int, int>> b; vector<int> a(26); int main() { cin >> s >> n; for (int i = 0; i < s.length(); ++i) { a[s[i] - a ]++; } for (int i = 0; i < 26; ++i) { b.push_back(make_pair(a[i], i)); } sort(b.begin(), b.end()); for (int i = 0; i < 26; ++i) { if (n >= b[i].first) { n -= b[i].first; b[i].first = 0; } } for (int i = 0; i < 26; ++i) { if (b[i].first != 0) ans++; } cout << ans << endl; for (int i = 0; i < s.length(); ++i) { for (int j = 0; j < 26; ++j) { if (s[i] - a == b[j].second && b[j].first > 0) { cout << s[i]; } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long dp[210][210]; struct point { long long x, y; void read() { scanf( %I64d%I64d , &x, &y); } } P[210]; long long cross(point a, point b, point c) { return (b.x - a.x) * (c.y - a.y) - (b.y - a.y) * (c.x - a.x); } int main() { long long s = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) P[i].read(); P[n + 1] = P[1]; for (int i = 2; i <= n; i++) s += cross(P[1], P[i], P[i + 1]); if (s > 0) for (int i = 1; i <= n / 2; i++) swap(P[i], P[n - i + 1]); for (int i = 1; i < n; i++) dp[i][i + 1] = 1; for (int i = 2; i < n; i++) for (int j = 1; j <= n - i; j++) for (int k = j + 1; k < i + j; k++) if (cross(P[j], P[i + j], P[k]) > 0) dp[j][i + j] = (dp[j][i + j] + dp[j][k] * dp[k][i + j]) % 1000000007; printf( %I64d , dp[1][n]); }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_4_V
`define SKY130_FD_SC_LP__DFRTP_4_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtp_4 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtp_4 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_1_V
`define SKY130_FD_SC_LP__O32AI_1_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_1_V
|
/*
* PS2 Interface
* Copyright (C) 2009 Takeshi Matsuya
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ps2 #(
parameter csr_addr = 4'h0,
parameter clk_freq = 100000000
) (
input sys_rst,
input sys_clk,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
inout ps2_clk,
inout ps2_data,
output reg irq
);
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
reg tx_busy;
//-----------------------------------------------------------------
// divisor
//-----------------------------------------------------------------
reg [9:0] enable_counter;
wire enable;
assign enable = (enable_counter == 10'd0);
parameter divisor = clk_freq/12800/16;
always @(posedge sys_clk) begin
if(sys_rst)
enable_counter <= divisor - 10'd1;
else begin
enable_counter <= enable_counter - 10'd1;
if(enable)
enable_counter <= divisor - 10'd1;
end
end
//-----------------------------------------------------------------
// Synchronize ps2 clock and data
//-----------------------------------------------------------------
reg ps2_clk_1;
reg ps2_data_1;
reg ps2_clk_2;
reg ps2_data_2;
reg ps2_clk_out;
reg ps2_data_out1, ps2_data_out2;
always @(posedge sys_clk) begin
ps2_clk_1 <= ps2_clk;
ps2_data_1 <= ps2_data;
ps2_clk_2 <= ps2_clk_1;
ps2_data_2 <= ps2_data_1;
end
/* PS2 */
reg [7:0] kcode;
reg rx_clk_data;
reg [5:0] rx_clk_count;
reg [4:0] rx_bitcount;
reg [10:0] rx_data;
reg [10:0] tx_data;
reg we_reg;
/* FSM */
reg [2:0] state;
reg [2:0] next_state;
parameter RECEIVE = 3'd0;
parameter WAIT_READY = 3'd1;
parameter CLOCK_LOW = 3'd2;
parameter CLOCK_HIGH = 3'd3;
parameter CLOCK_HIGH1 = 3'd4;
parameter CLOCK_HIGH2 = 3'd5;
parameter WAIT_CLOCK_LOW = 3'd6;
parameter TRANSMIT = 3'd7;
assign state_receive = state == RECEIVE;
assign state_transmit = state == TRANSMIT;
always @(posedge sys_clk) begin
if(sys_rst)
state = RECEIVE;
else begin
state = next_state;
end
end
/* ps2 clock falling edge 100us counter */
//parameter divisor_100us = clk_freq/10000;
parameter divisor_100us = 1;
reg [16:0] watchdog_timer;
wire watchdog_timer_done;
assign watchdog_timer_done = (watchdog_timer == 17'd0);
always @(posedge sys_clk) begin
if(sys_rst||ps2_clk_out)
watchdog_timer <= divisor_100us - 1;
else if(~watchdog_timer_done)
watchdog_timer <= watchdog_timer - 1;
end
always @(*) begin
ps2_clk_out = 1'b1;
ps2_data_out1 = 1'b1;
tx_busy = 1'b1;
next_state = state;
case(state)
RECEIVE: begin
tx_busy = 1'b0;
if(we_reg) begin
next_state = WAIT_READY;
end
end
WAIT_READY: begin
if(rx_bitcount == 5'd0) begin
ps2_clk_out = 1'b0;
next_state = CLOCK_LOW;
end
end
CLOCK_LOW: begin
ps2_clk_out = 1'b0;
if(watchdog_timer_done) begin
next_state = CLOCK_HIGH;
end
end
CLOCK_HIGH: begin
next_state = CLOCK_HIGH1;
end
CLOCK_HIGH1: begin
next_state = CLOCK_HIGH2;
end
CLOCK_HIGH2: begin
ps2_data_out1 = 1'b0;
next_state = WAIT_CLOCK_LOW;
end
WAIT_CLOCK_LOW: begin
ps2_data_out1 = 1'b0;
if(ps2_clk_2 == 1'b0) begin
next_state = TRANSMIT;
end
end
TRANSMIT: begin
if(rx_bitcount == 5'd10) begin
next_state = RECEIVE;
end
end
endcase
end
//-----------------------------------------------------------------
// PS2 RX/TX Logic
//-----------------------------------------------------------------
always @(posedge sys_clk) begin
if(sys_rst) begin
rx_clk_data <= 1'd1;
rx_clk_count <= 5'd0;
rx_bitcount <= 5'd0;
rx_data <= 11'b11111111111;
irq <= 1'd0;
csr_do <= 32'd0;
we_reg <= 1'b0;
ps2_data_out2 <= 1'b1;
end else begin
irq <= 1'b0;
we_reg <= 1'b0;
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[0])
1'b0: csr_do <= kcode;
1'b1: csr_do <= tx_busy;
endcase
if(csr_we && csr_a[0] == 1'b0) begin
tx_data <= {2'b11, ~(^csr_di[7:0]), csr_di[7:0]}; // STOP+PARITY+DATA
we_reg <= 1'b1;
end
end
if(enable) begin
if(rx_clk_data == ps2_clk_2) begin
rx_clk_count <= rx_clk_count + 5'd1;
end else begin
rx_clk_count <= 5'd0;
rx_clk_data <= ps2_clk_2;
end
if(state_receive && rx_clk_data == 1'b0 && rx_clk_count == 5'd4) begin
rx_data <= {ps2_data_2, rx_data[10:1]};
rx_bitcount <= rx_bitcount + 5'd1;
if(rx_bitcount == 5'd10) begin
irq <= 1'b1;
kcode <= rx_data[9:2];
end
end
if(state_transmit && rx_clk_data == 1'b0 && rx_clk_count == 5'd0) begin
ps2_data_out2 <= tx_data[rx_bitcount];
rx_bitcount <= rx_bitcount + 5'd1;
if(rx_bitcount == 5'd10) begin
ps2_data_out2 <= 1'b1;
end
end
if(rx_clk_count == 5'd16) begin
rx_bitcount <= 5'd0;
rx_data <= 11'b11111111111;
end
end
end
end
assign ps2_clk = ps2_clk_out ? 1'hz : 1'b0;
assign ps2_data = ps2_data_out1 & ps2_data_out2 ? 1'hz : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; int f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; } inline void judge() { freopen( in.txt , r , stdin); freopen( out.txt , w , stdout); } const int maxn = 100005; int fac[maxn], facinv[maxn]; const int mod = 1e9 + 7; inline int powmod(int a, int b) { int res = 1; for (; b; b >>= 1) { if (b & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; } return res; } inline void prprpr() { fac[0] = 1; for (int i = (1); i <= (100000); i++) fac[i] = 1ll * fac[i - 1] * i % mod; for (int i = (0); i <= (100000); i++) facinv[i] = powmod(fac[i], mod - 2); } inline int C(int n, int m) { return 1ll * fac[n] * facinv[m] % mod * facinv[n - m] % mod; } inline int Gans(int x, int n, int *a) { if (n < x) return 0; return a[n - x + 1] * 1ll * powmod(26, n) % mod; } inline void calc(int x, int *&a) { a = (int *)malloc(140005 * sizeof(int)); int inv = powmod(26, mod - 2); int v1 = powmod(inv, x), v2 = 1; for (int i = (x); i <= (100000); i++) { a[i - x + 1] = 1ll * C(i - 1, x - 1) * v2 % mod * v1 % mod; v1 = 1ll * v1 * inv % mod; v2 = 1ll * v2 * (26 - 1) % mod; a[i - x + 1] = (a[i - x + 1] + a[i - x]) % mod; } } char s[maxn]; int nowlen; map<int, int *> zball; int main() { prprpr(); int m; read(m); scanf( %s , s + 1); nowlen = strlen(s + 1); calc(nowlen, zball[nowlen]); for (int i = (1); i <= (m); i++) { int x; read(x); if (x == 2) { int v; read(v); printf( %d n , Gans(nowlen, v, zball[nowlen])); } else { scanf( %s , s + 1); nowlen = strlen(s + 1); if (!zball.count(nowlen)) calc(nowlen, zball[nowlen]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; const int N = 1000 + 20; int n, m, q, part[N][N]; string s[N]; inline int get(int x) { return (__builtin_popcount(x) & 1 ? -1 : +1); } inline int get(int x, int y) { return get(x) * get(y); } inline pii calc(int x) { int a = x / 2, b = x / 2; if (x & 1) { if (get(x - 1) == 1) a++; else b++; } return pii(a, b); } inline pii calc(int x, int y) { pii p1 = calc(x), p2 = calc(y); return pii(p1.first * p2.first + p1.second * p2.second, p1.first * p2.second + p1.second * p2.first); } inline int f(int x, int y) { int res = 0; int X = x / n, Y = y / m; x %= n, y %= m; pii p = calc(X, Y); res += part[n][m] * p.first + (n * m - part[n][m]) * p.second; p = calc(X); if (get(Y) == -1) swap(p.first, p.second); res += part[n][y] * p.first + (n * y - part[n][y]) * p.second; p = calc(Y); if (get(X) == -1) swap(p.first, p.second); res += part[x][m] * p.first + (x * m - part[x][m]) * p.second; if (get(X, Y) == 1) res += part[x][y]; else res += (x * y - part[x][y]); return res; } int32_t main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> q; for (int i = 0; i < n; i++) { cin >> s[i]; for (int j = 0; j < m; j++) { part[i + 1][j + 1] = (s[i][j] == 1 ) + part[i][j + 1] + part[i + 1][j] - part[i][j]; } } while (q--) { int x1, hlkhjl, x2, y2; cin >> x1 >> hlkhjl >> x2 >> y2; x1--, hlkhjl--; cout << f(x2, y2) - f(x1, y2) - f(x2, hlkhjl) + f(x1, hlkhjl) << n ; } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:46:45 10/11/2015
// Design Name:
// Module Name: rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_rx(
input rx, // entrada serie de datos
input s_tick, // clock baud rate (9600 bps)
input reset,
input clock, // clock de la placa (50MHz)
output reg rx_done, // flag de finalización de recepción
output reg [7:0] d_out // salida paralela de datos
);
localparam [1:0] IDLE = 0,
START = 1,
DATA = 2,
STOP = 3;
localparam D_BIT = 8,
B_start= 0,
B_stop= 1;
reg [1:0] current_state, next_state;
reg [3:0] s;
reg [3:0] n;
// algoritmo de cambio de estado
always @(posedge clock, posedge reset) begin
if(reset)
current_state <= IDLE ;
else
current_state <= s_tick ? next_state : current_state;
end
//lógica interna de estados
always @(posedge clock) begin
if(s_tick) begin
case(current_state)
IDLE: begin
rx_done=0;
s = 0;
next_state = (rx == B_start) ? START : IDLE;
end
START: begin
rx_done=0;
if(s >= 7) begin
s = 0;
n = 0;
next_state = DATA;
end
else begin
s = s + 1;
end
end
DATA: begin
if(s >= 15) begin
s = 0;
if(n >= D_BIT) begin
next_state = STOP;
end
else begin
d_out = {rx,d_out[7:1]};
n = n + 1;
end
end
else begin
s = s + 1;
end
end
STOP: begin
if(rx==0)begin
rx_done = 1;
next_state = START;
s = 0;
n = 0;
end
else if(s >= 15) begin
rx_done = 1;
next_state = IDLE;
end
else begin
s = s + 1;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; const int C = 26; void add(int &x, int y) { x += y; while (x >= MOD) x -= MOD; while (x < 0) x += MOD; } int fix(int x) { while (x >= MOD) x -= MOD; while (x < 0) x += MOD; return x; } int pw(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % MOD; b >>= 1; a = 1ll * a * a % MOD; } return ret; } int inv(int a) { return pw(a, MOD - 2); } int mul(int a, int b) { return (long long)a * b % MOD; } const int MAXN = 2e5 + 10; const int LOG = 20; int n, q, p[MAXN]; int tab[MAXN][LOG]; int get(int l, int r) { int ans = 1; for (int i = LOG - 1; ~i; --i) if (l + (1 << i) <= r) ans = mul(ans, tab[l][i]), l += 1 << i; return ans; } int st[MAXN << 2], lz[MAXN << 2]; int pr[MAXN]; void plant(int v, int b, int e) { if (e - b == 1) { st[v] = pr[b]; return; } int m = (b + e) >> 1; plant(v << 1, b, m); plant(v << 1 ^ 1, m, e); st[v] = fix(st[v << 1] + st[v << 1 ^ 1]); } void weed(int v) { for (int u : {v << 1, v << 1 ^ 1}) { st[u] = mul(st[u], lz[v]); lz[u] = mul(lz[u], lz[v]); } lz[v] = 1; } void water(int v, int b, int e, int l, int r, int x) { if (l >= r) return; if (b == l && e == r) { st[v] = mul(st[v], x); lz[v] = mul(lz[v], x); return; } weed(v); int m = (b + e) >> 1; water(v << 1, b, m, l, min(r, m), x); water(v << 1 ^ 1, m, e, max(l, m), r, x); st[v] = fix(st[v << 1] + st[v << 1 ^ 1]); } int smoke(int v, int b, int e, int l, int r) { if (l >= r) return 0; if (b == l && e == r) return st[v]; weed(v); int m = (b + e) >> 1; return fix(smoke(v << 1, b, m, l, min(r, m)) + smoke(v << 1 ^ 1, m, e, max(l, m), r)); } void solve() { cin >> n >> q; for (int i = 0; i < n; i++) cin >> p[i]; for (int i = 0; i < n; i++) p[i] = mul(p[i], inv(100)); for (int i = 0; i < n; i++) tab[i][0] = p[i]; for (int j = 1; j < LOG; j++) for (int i = 0; i < n; i++) if (i + (1 << j) <= n) tab[i][j] = mul(tab[i][j - 1], tab[i + (1 << (j - 1))][j - 1]); else tab[i][j] = tab[i][j - 1]; fill(lz, lz + (MAXN << 2), 1); pr[n - 1] = inv(p[n - 1]); for (int i = n - 2; ~i; --i) pr[i] = mul(pr[i + 1], inv(p[i])); plant(1, 0, n); set<int> pts; pts.insert(0); pts.insert(n); while (q--) { int u; cin >> u; --u; if (pts.count(u)) { auto prv = --pts.lower_bound(u); water(1, 0, n, *prv, u, smoke(1, 0, n, u, u + 1)); pts.erase(u); } else { auto prv = --pts.lower_bound(u); water(1, 0, n, *prv, u, inv(smoke(1, 0, n, u, u + 1))); pts.insert(u); } cout << st[1] << n ; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int te = 1; for (int w = 1; w <= te; w++) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int l, r, d; scanf( %d %d %d , &l, &r, &d); if ((double)l / d > 1) printf( %d n , d); else { int f = ((double)r / d) + 1; printf( %d n , f * d); } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; long long A[100005]; map<long long, long long> mp; int main() { long long n, a, i; cin >> n; for (i = 1; i <= n; i++) { cin >> a; mp[a] += a; } A[1] = mp[1]; A[0] = 0; for (i = 2; i <= 100000; i++) { A[i] = max(A[i - 1], A[i - 2] + mp[i]); } cout << A[100000] << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_2_V
`define SKY130_FD_SC_HS__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_r90_224x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_r90_224x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_r90_224x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105]; bool judge(int x) { for(int i=1;i<=100;i++) { if(i*i==x) return true; } return false; } int main() { int t; cin>>t; while(t--) { int n; cin>>n; for(int i=1; i<=n; i++) { cin>>a[i]; } int loop=0; for(int i=1; i<=n; i++) { if(judge(a[i])) { continue; } else { cout<< YES <<endl; loop=1; break; } } if(loop==0) cout<< NO <<endl; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_1_V
`define SKY130_FD_SC_HD__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_1_V
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
input clk_i;
input rst_i;
input ena_i;
input tx_empty_i;
input [11:0] tx_delay_i;
input [11:0] rx_delay_i;
output atr_tx_o;
reg [3:0] state;
reg [11:0] count;
`define ST_RX_DELAY 4'b0001
`define ST_RX 4'b0010
`define ST_TX_DELAY 4'b0100
`define ST_TX 4'b1000
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
state <= `ST_RX;
count <= 12'b0;
end
else
case (state)
`ST_RX:
if (!tx_empty_i)
begin
state <= `ST_TX_DELAY;
count <= tx_delay_i;
end
`ST_TX_DELAY:
if (count == 0)
state <= `ST_TX;
else
count <= count - 1;
`ST_TX:
if (tx_empty_i)
begin
state <= `ST_RX_DELAY;
count <= rx_delay_i;
end
`ST_RX_DELAY:
if (count == 0)
state <= `ST_RX;
else
count <= count - 1;
default: // Error
begin
state <= `ST_RX;
count <= 0;
end
endcase
assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
endmodule // atr_delay
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int mod = 998244353; int T; int a[N], b[N], p[N]; bool vis[N]; int main() { scanf( %d , &T); while (T--) { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); p[a[i]] = i; vis[i] = 0; } for (int i = 1; i <= k; ++i) { scanf( %d , &b[i]); } int ans = 1; for (int i = k; i >= 1; --i) { int t = p[b[i]]; int kk = 0; if (t > 1 && !vis[t - 1]) kk++; if (t < n && !vis[t + 1]) kk++; vis[t] = 1; ans = (ans * kk) % mod; } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n, m, k, s; cin >> n >> m >> k >> s; vector<vector<long long>> a(2, vector<long long>(n)); for (long long i = 0; i < 2; ++i) { for (long long j = 0; j < n; ++j) { cin >> a[i][j]; } } vector<vector<pair<long long, long long>>> g(2); for (long long i = 0; i < m; ++i) { long long x, y; cin >> x >> y; g[x - 1].push_back({y, i}); } for (long long i = 0; i < 2; ++i) { sort(g[i].begin(), g[i].end()); } auto ok = [&](long long q) { vector<long long> p(2, numeric_limits<long long>::max()); vector<long long> day(2, -1); for (long long i = 0; i <= q; ++i) { for (long long j = 0; j < 2; ++j) { if (p[j] > a[j][i]) { p[j] = a[j][i]; day[j] = i; } } } assert(day[0] != -1 && day[1] != -1); long long i = 0, j = 0; vector<pair<long long, long long>> ans; long long ss = s; auto buyi = [&]() { ss -= p[0] * g[0][i].first; ans.push_back({g[0][i].second, day[0]}); ++i; }; auto buyj = [&]() { ss -= p[1] * g[1][j].first; ans.push_back({g[1][j].second, day[1]}); ++j; }; while ((i < g[0].size() || j < g[1].size()) && ans.size() < k) { if (i >= g[0].size()) { buyj(); } else if (j >= g[1].size()) { buyi(); } else { if (p[0] * g[0][i].first < p[1] * g[1][j].first) buyi(); else buyj(); } } if (ss < 0 || ans.size() < k) ans.clear(); return ans; }; if (ok(n - 1).size() == 0) { cout << -1 n ; return 0; } long long l = 0, r = n - 1; while (r - l > 1) { long long mid = (l + r) >> 1; if (ok(mid).size()) { r = mid; } else { l = mid + 1; } } if (!ok(l).size()) { l = r; } cout << l + 1 << n ; for (auto [x, y] : ok(l)) { cout << x + 1 << << y + 1 << n ; } }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ns
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
always @ (posedge clk) begin
if ($time >= 10) begin
// Display formatting
$write; // Check missing arguments work
$write("default: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n",
$time, $time, $time, $time);
$timeformat(-9, 0, "", 0);
$write("-9,0,,0: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n",
$time, $time, $time, $time);
$timeformat(-9, 0, "", 10);
$write("-9,0,,10: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n",
$time, $time, $time, $time);
$timeformat(-9, 0, "ns", 5);
$write("-9,0,ns,5: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n",
$time, $time, $time, $time);
$timeformat(-9, 3, "ns", 8);
$write("-9,3,ns,8: [%0t] 0t time [%t] No0 time p=%p 0p=%0p\n",
$time, $time, $time, $time);
$write("\n");
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_0_V
`define SKY130_FD_SC_LP__A221O_0_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_0 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_0 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_0_V
|
`timescale 1ns / 1ps
module test_amba;
// Inputs
reg clk;
reg miso;
//reg[7:0] data_in;
//reg ready_send;
reg rst;
reg hwrite;
reg[31:0] hwdata;
reg[31:0] haddr;
reg hsel;
// Outputs
wire mosi;
wire sclk;
wire ss;
//wire busy;
//wire[7:0] data_out;
wire[31:0] hrdata;
// amba_connector - - spi
wire [7:0] spi_data_out;
wire spi_busy;
wire [7:0] spi_data_in;
wire spi_ready_send;
// Instantiate the Unit Under Test (UUT)
spi uut (
.clk (clk ),
.miso (miso ),
.data_in (spi_data_in ),
.ready_send (spi_ready_send),
.rst (rst ),
.mosi (mosi ),
.sclk (sclk ),
.ss (ss ),
.busy (spi_busy ),
.data_out (spi_data_out )
);
spi_amba_connector amba_uut (
.clk (clk ),
.rst (rst ),
.hwrite (hwrite ),
.hwdata (hwdata ),
.haddr (haddr ),
.hsel (hsel ),
.hrdata (hrdata ),
.spi_data_out (spi_data_out ),
.spi_busy (spi_busy ),
.spi_data_in (spi_data_in ),
.spi_ready_send (spi_ready_send)
);
initial begin
// Initialize Inputs
clk = 0;
miso = 0;
rst = 1;
// Wait for two clocks for the global reset to finish
@(posedge clk);
@(posedge clk);
rst = 0;
// AHB-Lite Write
// Address phase
hwrite = 1;
haddr = 'h00000000;
hsel = 1;
// Data phase
@(posedge clk);
hwdata = 'h00000013;
hwrite = 0;
// SPI reads at the same time
@(spi_busy == 1);
miso = 0;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 1;
@(spi_busy == 0);
hsel=0;
// AHB-Lite Read
// Address phase
@(posedge clk);
haddr = 'h00000004;
hsel = 1;
hwrite = 0;
// Data phase
@(posedge clk);
@(posedge clk);
@(posedge clk);
/*#50;
hsel = 0;
@(spi_busy == 0);
miso = 0;
hwrite = 1;
hwdata = 'h00000014;
haddr = 'h00000000;
hsel = 1;
@(spi_busy == 1);
miso = 1;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 1;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 0;
@(negedge sclk); miso = 0;
#50;
hwrite = 0;
hsel=0;
@(spi_busy == 0);
#10;
haddr = 'h00000004;
hsel = 1;
#50;
hsel = 0;
@(posedge clk);
@(posedge clk);*/
@(posedge clk);
$finish;
end
always #5 clk = ! clk;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:20000000 ) using namespace std; int ri() { int x; scanf( %d , &x); return x; } long long rll() { long long x; scanf( %lld , &x); return x; } void solve() { long long x; cin >> x; set<pair<long long, long long> > result; result.insert(make_pair(1, x)); result.insert(make_pair(x, 1)); long long tmp = 0; for (long long k = 2;; k++) { tmp += (k - 1) * (k - 1); long long ost = x - tmp; long long wtf = k * k * k - (k - 1) * k / 2 * k * 2; if (ost < wtf) { cerr << k << endl; break; } ost *= 2LL; if (ost % k == 0) { ost /= k; long long n = k; long long t = ost + (k - 1) * n; long long m = t / (2 * n - k + 1); if (m * (2 * n - k + 1) == t) { result.insert(make_pair(n, m)), result.insert(make_pair(m, n)); } } } cout << result.size() << endl; for (set<pair<long long, long long> >::iterator it = result.begin(); it != result.end(); it++) cout << it->first << << it->second << endl; } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; template <typename T> void read(T &x) { x = 0; char op = getchar(); int F = 1; while (!isdigit(op)) { if (op == - ) F *= -1; op = getchar(); } while (isdigit(op)) { x = (x << 1) + (x << 3) + op - 0 ; op = getchar(); } x *= F; } template <typename T, typename... Args> void read(T &x, Args &...args) { read(x); read(args...); } template <typename T1, typename T2> void ckmax(T1 &x, T2 y) { if (x < y) x = y; } template <typename T1, typename T2> void ckmin(T1 &x, T2 y) { if (x > y) x = y; } int a[1005]; int n, m, c; void work() { int rec; cin >> rec; if (2 * rec <= c) { for (int i = 1; i <= n; i++) { if (a[i] > rec || !a[i]) { a[i] = rec; cout << i << n ; break; } } } else { for (int i = n; i >= 1; i--) { if (a[i] < rec || !a[i]) { a[i] = rec; cout << i << n ; break; } } } fflush(stdout); } int main() { cin >> n >> m >> c; while (m--) work(); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4B_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_PP_V
/**
* buflp: Buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__buflp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_PP_V
|
// (c) NedoPC 2013
//
// SD data sender to test SD and MP3 dmas
`timescale 1ns/100ps
module sd
(
input wire clk,
input wire sdi,
output wire sdo
);
reg [7:0] byteout;
reg [7:0] bytein;
int bitcntout;
int bitcntin;
int state;
int count;
reg [7:0] tmp;
localparam _FF = 'd0;
localparam _FE = 'd1;
localparam _DATA = 'd2;
localparam _CRC = 'd3;
initial byteout = 8'hFF;
initial bitcntout = 8;
initial bitcntin = 7;
initial state = _FF;
initial count = 5;
assign sdo = byteout[7];
always @(negedge clk)
begin
byteout <= {byteout[6:0],1'b1};
bitcntout = bitcntout - 1;
if( bitcntout<0 )
begin
bitcntout = 7;
case( state )
_FF:begin
count = count - 1;
if( count <= 0 )
state <= _FE;
byteout <= 8'hFF;
end
_FE:begin
state <= _DATA;
byteout <= 8'hFE;
count = 512;
end
_DATA:begin
count = count - 1;
if( count <= 0 )
begin
state <= _CRC;
count <= 2;
end
tmp = $random>>24;
byteout <= tmp;
tb.sdmp3_chk.push_back(tmp);
end
_CRC:begin
count = count - 1;
if( count <= 0 )
begin
state <= _FF;
count <= 1+($random&63);
end
byteout <= $random>>24;
end
endcase
end
end
always @(posedge clk)
begin
bytein = {bytein[6:0], sdi};
bitcntin = bitcntin - 1;
if( bitcntin<0 )
begin
bitcntin = 7;
if( bytein!==8'hFF )
begin
$display("sd: received not FF!");
$stop;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p_arr[200005]; int main() { int n, in, cnt, x, arr[200005]; std::cin >> n; queue<int> q; for (int i = 1; i <= n; i++) { std::cin >> in; q.push(in); } for (int i = 1; i <= n; i++) { std::cin >> arr[i]; } cnt = 0; for (int i = 1; i <= n; i++) { x = q.front(); while (p_arr[x] == -1) { q.pop(); x = q.front(); } x = q.front(); if (x == arr[i]) { q.pop(); } else { cnt++; p_arr[arr[i]] = -1; } } std::cout << cnt << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; long long s, x; int main() { srand(time(NULL)); cin >> n; n--; s = 1; x = 12; while (n) { s += x; x += 12; n--; } cout << s << endl; return 0; }
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_unit.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_unit (
dataa,
datab,
result);
input [35:0] dataa;
input [35:0] datab;
output [71:0] result;
wire [71:0] sub_wire0;
wire [71:0] result = sub_wire0[71:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 36,
lpm_mult_component.lpm_widthb = 36,
lpm_mult_component.lpm_widthp = 72;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
// Retrieval info: PRIVATE: WidthA NUMERIC "36"
// Retrieval info: PRIVATE: WidthB NUMERIC "36"
// Retrieval info: PRIVATE: WidthP NUMERIC "72"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: optimize NUMERIC "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=9"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "36"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "72"
// Retrieval info: USED_PORT: dataa 0 0 36 0 INPUT NODEFVAL "dataa[35..0]"
// Retrieval info: USED_PORT: datab 0 0 36 0 INPUT NODEFVAL "datab[35..0]"
// Retrieval info: USED_PORT: result 0 0 72 0 OUTPUT NODEFVAL "result[71..0]"
// Retrieval info: CONNECT: @dataa 0 0 36 0 dataa 0 0 36 0
// Retrieval info: CONNECT: @datab 0 0 36 0 datab 0 0 36 0
// Retrieval info: CONNECT: result 0 0 72 0 @result 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mult_unit_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`include "defines.v"
module alu (input [31:0] a, b, output [15:0] o1, o2, input size, input [4:0] func, output [15:0] flag_o, input en);
reg [15:0] flag;
wire [15:0] alu8_flag, alu16_flag;
wire alu8_en, alu16_en;
always @(alu8_flag) begin
flag <= alu8_flag;
end
always @(alu16_flag) begin
flag <= alu16_flag;
end
alu_impl #(.SIZE(8), .LOG2(3)) alu8(a[15:0], b[15:0], o1[7:0], o2[7:0], func, flag, alu8_flag, alu8_en);
alu_impl #(.SIZE(16), .LOG2(4)) alu16(a, b, o1, o2, func, flag, alu16_flag, alu16_en);
assign alu8_en = (en && !size);
assign alu16_en = (en && size);
assign flag_o = flag;
endmodule
module alu_impl #(parameter SIZE = 16, parameter LOG2 = 4) (input [SIZE*2-1:0] a, b, output [SIZE-1:0] o1, o2, input [4:0] func, input [15:0] flag_i, output [15:0] flag_o, input en);
reg [SIZE-1:0] r1, r2;
reg [15:0] flag;
always @(posedge en) begin
case (func)
`ALU_ADD : begin
{flag[`ALUF_CF], r1} = a[SIZE-1:0] + b[SIZE-1:0];
flag[`ALUF_OF] = (a[SIZE-1] & b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & ~b[SIZE-1] & r1[SIZE-1]);
end
`ALU_SUB : begin
{flag[`ALUF_CF], r1} = a[SIZE-1:0] - b[SIZE-1:0];
flag[`ALUF_OF] = (a[SIZE-1] & ~b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & b[SIZE-1] & r1[SIZE-1]);
end
`ALU_AND : begin
r1 = a[SIZE-1:0] & b[SIZE-1:0];
flag[`ALUF_CF] = 0;
flag[`ALUF_OF] = 0;
end
`ALU_OR : begin
r1 = a[SIZE-1:0] & b[SIZE-1:0];
flag[`ALUF_CF] = 0;
flag[`ALUF_OF] = 0;
end
`ALU_OR : begin
r1 = a[SIZE-1:0] | b[SIZE-1:0];
flag[`ALUF_CF] = 0;
flag[`ALUF_OF] = 0;
end
`ALU_XOR : begin
r1 = a[SIZE-1:0] ^ b[SIZE-1:0];
flag[`ALUF_CF] = 0;
flag[`ALUF_OF] = 0;
end
`ALU_MUL : begin
{r2, r1} = a[SIZE-1:0] * b[SIZE-1:0];
flag[`ALUF_CF] = (r2 != 0);
flag[`ALUF_OF] = (r2 != 0);
end
`ALU_DIV : begin
r2 = b[SIZE*2-1:0] % a[SIZE-1:0];
r1 = b[SIZE*2-1:0] / a[SIZE-1:0];
// flag[`ALUF_CF] = (r2 != 0);
// flag[`ALUF_OF] = (r2 != 0);
end
`ALU_IMUL : begin
{r2, r1} = $signed(a[SIZE-1:0]) * $signed(b[SIZE-1:0]);
flag[`ALUF_CF] = (r2 != 0);
flag[`ALUF_OF] = (r2 != 0);
end
`ALU_IDIV : begin
// todo a == 0
r2 = $signed(b[SIZE*2-1:0]) % $signed(a[SIZE*2-1:0]);
r1 = $signed(b[SIZE*2-1:0]) / $signed(a[SIZE*2-1:0]);
// flag[`ALUF_CF] = (r2 != 0);
// flag[`ALUF_OF] = (r2 != 0);
end
`ALU_NOT : begin
r1 = ~a[SIZE-1:0];
end
`ALU_NEG : begin
r1 = - a[SIZE-1:0];
flag[`ALUF_CF] = (r1 == 0);
end
`ALU_INC : begin
r1 = a[SIZE-1:0] + 16'd1;
end
`ALU_DEC : begin
r1 = a[SIZE-1:0] - 16'd1;
end
`ALU_SAL : begin
if (b[LOG2-1:0] != 0) begin
{flag[`ALUF_CF], r1} = a[SIZE-1:0] << b[LOG2-1:0];
end
end
`ALU_SAR : begin
if (b[LOG2-1:0] != 0) begin
r1 = $signed(a[SIZE-1:0]) >>> b[LOG2-1:0];
flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
end
end
`ALU_SHR : begin
if (b[LOG2-1:0] != 0) begin
r1 = a[SIZE-1:0] >> b[LOG2-1:0];
flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
end
end
`ALU_RCL : begin
if (b[LOG2-1:0] != 0) begin
{flag[`ALUF_CF], r1, r2} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} << (b[LOG2-1:0] - 1);
end
end
`ALU_RCR : begin
if (b[LOG2-1:0] != 0) begin
{flag[`ALUF_CF], r1} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} >> b[LOG2-1:0];
end
end
`ALU_ROL : begin
if (b[LOG2-1:0] != 0) begin
{r1, r2} = {a[SIZE-1:0], a[SIZE-1:0]} << b[LOG2-1:0];
flag[`ALUF_CF] = r1[0];
end
end
`ALU_ROR : begin
if (b[LOG2-1:0] != 0) begin
{r2, r1} = {a[SIZE-1:0], a[SIZE-1:0]} >> b[LOG2-1:0];
flag[`ALUF_CF] = r1[SIZE-1];
end
end
endcase
flag[`ALUF_ZF] = (r1 == 0);
flag[`ALUF_SF] = r1[SIZE-1];
end
assign o1 = (en) ? r1 : {SIZE{1'bz}};
assign o2 = (en) ? r2 : {SIZE{1'bz}};
assign flag_o = flag;
endmodule
module alu_test;
reg [31:0] a, b;
wire [15:0] r1, r2;
reg [4:0] func;
reg en;
wire [15:0] flag;
wire size;
alu alu(a, b, r1, r2, size, func, flag, en);
initial begin
$monitor("%t: a = %x, b = %x, result = %x %x, flag = %b", $time, a, b, r2, r1, flag[3:0]);
en = 1;
a <= 32'h7FFF;
b <= 32'h7FFF;
func <= `ALU_ADD;
#10
func <= `ALU_SUB;
#10
a <= 32'hFFFF;
b <= 32'hFFFF;
func <= `ALU_ADD;
#10
func <= `ALU_SUB;
#10
a <= 32'hFFFF;
b <= 32'hFFFF;
func <= `ALU_MUL;
#10 $finish();
end
always #5 begin
en <= ~en;
end
assign size = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, d, ans = 0; vector<long long> a; int main() { ios::sync_with_stdio(false); cin >> n >> d; while (n--) { long long temp; cin >> temp; a.push_back(temp); } for (long long i = 0; i < a.size(); i++) { long long idx = upper_bound(a.begin(), a.end(), a[i] + d) - a.begin(); idx--; if (idx > i + 1) ans += ((idx - i) * (idx - i - 1)) / 2; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; set<int> s; for (int i = 0; i < n; i++) { int a; cin >> a; s.insert(a); } cout << s.size() << n ; } return 0; }
|
/**************************************
* Module: router
* Date:2016-01-29
* Author: saber
*
* Description:
***************************************/
`include "constants.v"
`include "util.v"
module router(flit_out, credit, flit_in, data, next_router_credit, load, write,
init, clock, reset);
parameter CREDIT_DELAY = 16;
parameter VC_NUM = 4;
output [1:`IN_OUTPORT_CNT*`FLIT_SIZE] flit_out;
output [0:VC_NUM*`IN_OUTPORT_CNT-1] credit;
input [1:`IN_OUTPORT_CNT*`FLIT_SIZE] flit_in;
input [1:`IN_OUTPORT_CNT_BIN] data;
input [0:VC_NUM*`IN_OUTPORT_CNT-1] next_router_credit;
input [1:`ROUTERS_CNT_BIN] load;
input write;
input init;
input clock;
input reset;
/************************
INITIAL phase:initial values for router's table
************************/
reg [0:`IN_OUTPORT_CNT_BIN-1] TABLE_ARRAY [0:`TABLE_ROWS-1];
wire[0:`IN_OUTPORT_CNT_BIN-1] NEXT_TABLE_ARRAY [0:`TABLE_ROWS-1];
reg [0:`OCCUPIEDS_SIZE*`IN_OUTPORT_CNT*VC_NUM-1] occupieds;
wire [0:`OCCUPIEDS_SIZE*`IN_OUTPORT_CNT*VC_NUM-1] nxt_occupieds;
genvar tmp;
generate
for(tmp=0; tmp<`TABLE_ROWS; tmp=tmp+1)
begin
always @(posedge clock or posedge reset)
begin
if ( reset )
TABLE_ARRAY[tmp] <= {`IN_OUTPORT_CNT_BIN{1'b0}};
else
TABLE_ARRAY[tmp] <= NEXT_TABLE_ARRAY[tmp];
end
end
endgenerate
always @(posedge clock or posedge reset)
begin
if(reset)
occupieds <= {`OCCUPIEDS_SIZE*`IN_OUTPORT_CNT*VC_NUM{1'b0}};
else
occupieds <= nxt_occupieds;
end
genvar i;
generate
for(i = 0; i <`TABLE_ROWS; i = i + 1)begin : GEN_NEXT_TABLE_ARRAY
assign NEXT_TABLE_ARRAY[i] = ((init == 1'b0) ? TABLE_ARRAY[i] : (write == 1'b1 && load == i) ? data : TABLE_ARRAY[i]);
end
endgenerate
genvar util_genvar;
`MAKE_ARRAY(credit_array, credit, `IN_OUTPORT_CNT, VC_NUM, GEN_CREDIT)
`MAKE_VECTOR(TABLE_VECTOR, TABLE_ARRAY, `TABLE_ROWS, `IN_OUTPORT_CNT_BIN, GEN_TABLE_VECTOR)
`MAKE_ARRAY_1BASED(flit_in_array, flit_in, `IN_OUTPORT_CNT, `FLIT_SIZE, GEN_FLIT_IN1)
wire [1:`FLIT_SIZE*VC_NUM] flit_out_each_in_port [0:`IN_OUTPORT_CNT-1];
wire [0:VC_NUM-1] isnew_each_in_port [0:`IN_OUTPORT_CNT-1];
`MAKE_VECTOR(isnew_vector, isnew_each_in_port, `IN_OUTPORT_CNT, VC_NUM, GEN_ISNEW_VECTOR)
wire [0:`IN_OUTPORT_CNT * VC_NUM -1] credit_for_inputs;
wire [0:`IN_OUTPORT_CNT * VC_NUM -1] nxt_routers_credits;
wire [0:VC_NUM-1] credit_next_router [0:`IN_OUTPORT_CNT];
generate
for(i = 0; i < `IN_OUTPORT_CNT; i = i + 1)begin:GEN_IN_PORT
in_port #(.CREDIT_DELAY(CREDIT_DELAY),.VC_NUM(VC_NUM)) m(
.credit(credit_array[i]),
.flit_out(flit_out_each_in_port[i]),
.is_new(isnew_each_in_port[i]),
.flit_in(flit_in_array[i]),
.credit_next_router(credit_next_router[i]),
.clock(clock),
.reset(reset)
);
end
endgenerate
genvar j;
generate
for(i=0;i<VC_NUM;i=i+1) begin : GEN_VC_CREDIT
for(j=0;j<`IN_OUTPORT_CNT;j=j+1) begin : GEN_IN_OUTPORT_CREDIT
assign credit_next_router[j][i] = credit_for_inputs[i*`IN_OUTPORT_CNT + j];
assign nxt_routers_credits[i*`IN_OUTPORT_CNT + j] = next_router_credit[j*VC_NUM + i];
end
end
endgenerate
priority_all_vc P(.outputs_out(flit_out),
.occupieds_out(nxt_occupieds),
.credit_for_inputs(credit_for_inputs),
.nxt_routers_credits(nxt_routers_credits),
.flit_in(flit_in),
.occupieds_in(occupieds),
.is_new_flit(isnew_vector),
.TABLE(TABLE_VECTOR)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct osoba { string ime, prezime; }; int main() { int n; cin >> n; vector<osoba> osobe(n); vector<int> redoslijed(n); vector<string> minori(n); bool trigger = true; for (int i = 0; i < n; i++) cin >> osobe[i].ime >> osobe[i].prezime; for (int i = 0; i < n; i++) cin >> redoslijed[i]; if (strcmp(osobe[redoslijed[0] - 1].ime.c_str(), osobe[redoslijed[0] - 1].prezime.c_str()) < 0) minori[0] = osobe[redoslijed[0] - 1].ime; else minori[0] = osobe[redoslijed[0] - 1].prezime; for (int i = 1; i < n; i++) { if (strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].ime.c_str()) > 0 && strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].prezime.c_str()) <= 0) minori[i] = osobe[redoslijed[i] - 1].prezime; else if (strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].ime.c_str()) <= 0 && strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].prezime.c_str()) > 0) minori[i] = osobe[redoslijed[i] - 1].ime; else if (strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].ime.c_str()) <= 0 && strcmp(minori[i - 1].c_str(), osobe[redoslijed[i] - 1].prezime.c_str()) <= 0) { if (strcmp(osobe[redoslijed[i] - 1].ime.c_str(), osobe[redoslijed[i] - 1].prezime.c_str()) < 0) minori[i] = osobe[redoslijed[i] - 1].ime; else minori[i] = osobe[redoslijed[i] - 1].prezime; } else { cout << NO << endl; trigger = false; break; } } if (trigger) cout << YES << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int N, i; cin >> N; char ch; int o = 0, n = 0, e = 0, z = 0, r = 0; for (i = 0; i < N; i++) { cin >> ch; if (ch == o ) o++; else if (ch == n ) n++; else if (ch == e ) e++; else if (ch == z ) z++; else r++; } int m1, m2; m1 = min(o, min(n, e)); o -= m1; e -= m1; while (m1--) cout << 1 ; m2 = min(z, min(e, min(r, o))); while (m2--) cout << 0 ; return 0; }
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Ramdon_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:19 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module Ramdon_gen(
Reset ,
Clk ,
Init ,
RetryCnt ,
Random_time_meet
);
input Reset ;
input Clk ;
input Init ;
input [3:0] RetryCnt ;
output Random_time_meet;
//******************************************************************************
//internal signals
//******************************************************************************
reg [9:0] Random_sequence ;
reg [9:0] Ramdom ;
reg [9:0] Ramdom_counter ;
reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time
reg Random_time_meet;
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_sequence <=0;
else
Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};
always @ (RetryCnt or Random_sequence)
case (RetryCnt)
4'h0 : Ramdom={9'b0,Random_sequence[0]};
4'h1 : Ramdom={8'b0,Random_sequence[1:0]};
4'h2 : Ramdom={7'b0,Random_sequence[2:0]};
4'h3 : Ramdom={6'b0,Random_sequence[3:0]};
4'h4 : Ramdom={5'b0,Random_sequence[4:0]};
4'h5 : Ramdom={4'b0,Random_sequence[5:0]};
4'h6 : Ramdom={3'b0,Random_sequence[6:0]};
4'h7 : Ramdom={2'b0,Random_sequence[7:0]};
4'h8 : Ramdom={1'b0,Random_sequence[8:0]};
4'h9 : Ramdom={ Random_sequence[9:0]};
default : Ramdom={ Random_sequence[9:0]};
endcase
always @ (posedge Clk or posedge Reset)
if (Reset)
Slot_time_counter <=0;
else if(Init)
Slot_time_counter <=0;
else if(!Random_time_meet)
Slot_time_counter <=Slot_time_counter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
Ramdom_counter <=0;
else if (Init)
Ramdom_counter <=Ramdom;
else if (Ramdom_counter!=0&&Slot_time_counter==255)
Ramdom_counter <=Ramdom_counter -1 ;
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_time_meet <=1;
else if (Init)
Random_time_meet <=0;
else if (Ramdom_counter==0)
Random_time_meet <=1;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: TU Darmstadt
// Engineer: Mahdi Enan
//
// Create Date: 10:44:35 01/18/2017
// Design Name: Pi
// Module Name: spongent/tb_Pi.v
// Project Name: spongent
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Pi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Pi;
// Inputs
reg [31:0] in;
reg clk;
reg rst;
// Outputs
wire [8:0] out;
// Instantiate the Unit Under Test (UUT)
Pi_mod uut (
.in(in),
.out(out),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
in = 0;
clk = 0;
#5;
rst = 1;
#5;
rst = 0;
#5;
while ( in < 10) begin
#5;
$display ("i = %d, Pi=%h", in, out);
in = in + 1;
#5;
end
in = 31'h000000FE;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h000000FD;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
in = 31'h00000100;
#5;
$display("pi_in: %X, pi_out: %X", in, out);
end
always begin
#5 clk = !clk;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void read(T &a) { register int b = 1, c = getchar(); a = 0; for (; !isdigit(c); c = getchar()) if (c == 45) b *= -1; for (; isdigit(c); c = getchar()) a = (a << 3) + (a << 1) + c - 48; a *= b; } const int maxn = 105; const int maxm = 1 << 18; long long dp[maxm][maxn]; string str; int len; int m; int main() { cin >> str; len = int((str).size()); read(m); dp[0][0] = 1; for (int msk = 0; msk < int(1 << len); msk++) { for (int rem = 0; rem < int(m); rem++) { for (int j = 0; j < int(len); j++) if (!(msk & (1 << j))) { int nwrem = (rem * 10 + str[j] - 0 ) % m; int nwmsk = msk | (1 << j); if (!msk && str[j] == 0 ) continue; dp[nwmsk][nwrem] += dp[msk][rem]; } } } long long ans = dp[(1 << len) - 1][0]; for (int i = 0; i < int(10); i++) { int cnt = 0; for (int j = 0; j < int(len); j++) { if (str[j] == i + 48) cnt++; } long long fac = 1; for (int j = 1; j <= cnt; j++) fac *= j; ans /= fac; } printf( %I64d n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR2_4_V
`define SKY130_FD_SC_MS__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR2_4_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module defines the LDEXP function, which multiplies a floating point number by 2^(shift_in).
// The result is a valid floating point number within single-precision range, +/- INF or 0.
// If a denormalized number is supplied as input, the result will be zero (until we add denormalized
// number support).
//
module acl_fp_ldexp(clock, resetn, dataa, datab, enable, result);
input clock, resetn;
input [31:0] dataa;
input [31:0] datab;
input enable;
output [31:0] result;
// Cycle 1: Test inputs and compute resulting exponents.
wire [7:0] exponent_in = dataa[30:23];
wire [22:0] mantissa_in = dataa[22:0];
wire sign_in = dataa[31];
wire [31:0] shift_in = datab;
wire [31:0] intermediate_exp = shift_in + exponent_in;
reg [7:0] exp_stage_1;
reg [22:0] man_stage_1;
reg sign_stage_1;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exp_stage_1 <= 8'dx;
man_stage_1 <= 23'dx;
sign_stage_1 <= 1'bx;
end
else if (enable)
begin
sign_stage_1 <= sign_in;
if (exponent_in == 8'hff)
begin
// NaN / Inf input, so produce an NaN / Inf output.
man_stage_1 <= mantissa_in;
exp_stage_1 <= exponent_in;
end
else
if (intermediate_exp[31] | (exponent_in == 8'd0))
begin
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'd0;
end
else if ({1'b0, intermediate_exp[30:0]} >= 255)
begin
// infinity
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'hff;
end
else if (intermediate_exp[7:0] == 8'd0)
begin
// zero
man_stage_1 <= 23'd0;
exp_stage_1 <= 8'h00;
end
else
begin
man_stage_1 <= mantissa_in;
exp_stage_1 <= intermediate_exp[7:0];
end
end
end
assign result = {sign_stage_1, exp_stage_1, man_stage_1};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Peter Monsson.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
wire [31:0] in = cyc;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
package lpcm_pkg;
class lpcm_tr;
int latency;
int sample;
function new();
latency = 0;
sample = 0;
endfunction
function string convert2string();
return $sformatf("sample=0x%0h latency=%0d", sample, latency);
endfunction
endclass
endpackage
//internal error happens when lpcm_pkg is not imported
//import lpcm_pkg::*;
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [31:0] in;
initial begin
string s;
lpcm_pkg::lpcm_tr tr; // internal error happens when lpcm_pkg is not imported
tr = new();
tr.sample = 1;
tr.latency = 2;
s = tr.convert2string();
$display("hello %s", tr.convert2string());
if (s != "sample=0x1 latency=2") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [7:0] x, y;
initial begin
x = -4;
if (x !== 8'hfc) begin
$display("FAILED -- x = -4 --> %b", x);
$finish;
end
x = 4;
if (x !== 8'h04) begin
$display("FAILED");
$finish;
end
y = -x;
if (y !== 8'hfc) begin
$display("FAILED -- y = -%b --> %b", x, y);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Protocol Engine Receiver
// Checks each line (16 bits) against values in setting regs
// 3 options for each line --
// Error if mismatch, Slowpath if mismatch, or ignore line
// The engine increases the length of each packet by 32 or 48 bits,
// bringing the total length to a multiple of 32 bits. The last line
// is entirely new, and contains the results of the matching operation:
// 16 bits of flags, 16 bits of data. Flags indicate error or slowpath
// Data indicates line that caused mismatch if any.
// Flags[2:0] is {occ, eop, sop}
// Protocol word format is:
// 22 Last Header Line
// 21 SLOWPATH if mismatch
// 20 ERROR if mismatch
// 19 This is the IP checksum
// 18 This is the UDP checksum
// 17 Compute IP checksum on this word
// 16 Compute UDP checksum on this word
// 15:0 data word to be matched
module prot_eng_rx
#(parameter BASE=0)
(input clk, input reset, input clear,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [18:0] datain, input src_rdy_i, output dst_rdy_o,
output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
localparam HDR_WIDTH = 16 + 7; // 16 bits plus flags
localparam HDR_LEN = 32; // Up to 64 bytes of protocol
// Store header values in a small dual-port (distributed) ram
reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
wire [HDR_WIDTH-1:0] header_word;
always @(posedge clk)
if(set_stb & ((set_addr & 8'hE0) == BASE))
header_ram[set_addr[4:0]] <= set_data;
assign header_word = header_ram[state];
wire consume_input = src_rdy_i & dst_rdy_o;
wire produce_output = src_rdy_o & dst_rdy_i;
// Main State Machine
reg [15:0] pkt_length, fail_word, dataout_int;
reg slowpath, error, sof_o, eof_o, occ_o, odd;
assign dataout = {occ_o, eof_o, sof_o, dataout_int};
wire [15:0] calc_ip_checksum, calc_udp_checksum;
reg [15:0] rx_ip_checksum, rx_udp_checksum;
always @(posedge clk)
if(header_word[19])
rx_ip_checksum <= datain[15:0];
always @(posedge clk)
if(header_word[18])
rx_udp_checksum <= datain[15:0];
always @(posedge clk)
if(reset | clear)
begin
slowpath <= 0;
error <= 0;
state <= 0;
fail_word <= 0;
eof_o <= 0;
occ_o <= 0;
end
else if(src_rdy_i & dst_rdy_i)
case (state)
0 :
begin
slowpath <= 0;
error <= 0;
eof_o <= 0;
occ_o <= 0;
state <= 1;
end
ST_SLOWPATH :
;
ST_ERROR :
;
ST_PAYLOAD :
;
ST_FILLER :
;
ST_END1 :
;
ST_END2 :
;
default :
if(header_word[21] && mismatch)
state <= ST_SLOWPATH;
else if(header_word[20] && mismatch)
state <= ST_ERROR;
else if(header_word[22])
state <= ST_PAYLOAD;
else
state <= state + 1;
endcase // case (state)
// IP + UDP checksum state machines
checksum_sm ip_chk
(.clk(clk), .reset(reset), .in(datain),
.calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
checksum_sm udp_chk
(.clk(clk), .reset(reset), .in(datain),
.calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
endmodule // prot_eng_rx
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int q; cin >> q; while (q--) { int n; cin >> n; int a = 100000, b = 100000, c = -100000, d = -100000; vector<bool> ok(4, false); for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; int f[4]; for (int j = 0; j < 4; j++) cin >> f[j]; if (f[0] == 0) d = max(d, x), ok[0] = true; if (f[1] == 0) a = min(a, y), ok[1] = true; if (f[2] == 0) b = min(b, x), ok[2] = true; if (f[3] == 0) c = max(c, y), ok[3] = true; } if (a < c || d > b) cout << 0; else cout << 1 << << (d + b) / 2 << << (a + c) / 2; cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[100005], b[100005]; vector<int> g[100005]; int next_id, from[100005], to[100005]; bitset<1000> tree[4 * 100005], primes; int lazy[4 * 100005]; void dfs(int u) { from[u] = next_id++; b[from[u]] = a[u] % m; for (int i = 0; i < g[u].size(); i++) if (from[g[u][i]] == -1) dfs(g[u][i]); to[u] = next_id; } void rot(bitset<1000> &b, int k) { b = (b << k) | (b >> (m - k)); b ^= (b >> m) << m; } void init(int no, int l, int r) { if (r - l == 1) { tree[no].set(b[l]); return; } int m = (l + r) / 2; init(2 * no, l, m); init(2 * no + 1, m, r); tree[no] = tree[2 * no] | tree[2 * no + 1]; } void prop(int no, int l, int r) { lazy[no] %= m; if (lazy[no] > 0) { rot(tree[no], lazy[no]); if (r - l > 1) { lazy[2 * no] += lazy[no]; lazy[2 * no + 1] += lazy[no]; } lazy[no] = 0; } } void update(int no, int l, int r, int a, int b, int x) { if (a <= l && r <= b) { lazy[no] += x; return; } prop(no, l, r); int m = (l + r) / 2; if (a < m) update(2 * no, l, m, a, b, x); if (m < b) update(2 * no + 1, m, r, a, b, x); prop(2 * no, l, m); prop(2 * no + 1, m, r); tree[no] = tree[2 * no] | tree[2 * no + 1]; } bitset<1000> query(int no, int l, int r, int a, int b) { prop(no, l, r); if (a <= l && r <= b) return tree[no]; int m = (l + r) / 2; bitset<1000> ret; if (a < m) ret = query(2 * no, l, m, a, b); if (m < b) ret |= query(2 * no + 1, m, r, a, b); return ret; } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 1; i < n; i++) { int u, v; scanf( %d %d , &u, &v); u--, v--; g[u].push_back(v); g[v].push_back(u); } memset(from, -1, sizeof(from)); next_id = 0; dfs(0); memset(lazy, 0, sizeof(lazy)); init(1, 0, n); primes[2].flip(); for (int i = 3; i < m; i += 2) primes.set(i); for (int i = 3; i * i < m; i += 2) if (primes[i]) for (int j = i * i; j < m; j += i) primes.reset(j); int q, op, v, x; scanf( %d , &q); while (q--) { scanf( %d %d , &op, &v); v--; if (op == 1) { scanf( %d , &x); update(1, 0, n, from[v], to[v], x % m); } else { bitset<1000> bs = query(1, 0, n, from[v], to[v]) & primes; printf( %d n , (int)bs.count()); } } }
|
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_dag3_lpm_log_mod(clock,
reset_n,
first,
sceond,
third,
fourth,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, first, sceond, temp_a);
b top_b(clock, first, sceond, temp_b);
c top_c(clock, third, fourth, temp_c);
d top_d(clock, third, fourth, temp_d);
assign out0 = temp_a & temp_b;
assign out1 = temp_c + temp_d;
endmodule
/*---------------------------------------------------------*/
module a(clock,
fifth,
sixth,
out2);
input clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out2;
wire [`BITS-1:0] temp1;
d mya_d(clock, fifth[0], sixth[0], temp1[0]);
d mya_d2(clock, fifth[0], sixth[1], temp1[1]);
always @(posedge clock)
begin
out2 <= fifth & sixth & temp1;
end
endmodule
/*---------------------------------------------------------*/
module b(clock,
seventh,
eight,
out3);
input clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0] out3;
reg [`BITS-1:0] out3;
c myb_c(clock, seventh[0], eight[0], temp3);
always @(posedge clock)
begin
temp2 <= seventh | eight ^ temp3;
out3 <= seventh ^ temp2;
end
endmodule
/*---------------------------------------------------------*/
module c(clock,
ninth,
tenth,
out4);
// SIGNAL DECLARATIONS
input clock;
input ninth;
input tenth;
output out4;
wire out4;
wire temp4;
wire temp5;
d myc_d(clock, ninth, tenth, temp5);
assign out4 = temp4 ^ tenth;
assign temp4 = ninth - temp5;
endmodule
/*---------------------------------------------------------*/
module d(clock,
eleventh,
twelfth,
out5);
// SIGNAL DECLARATIONS
input clock;
input eleventh;
input twelfth;
output out5;
reg out5;
reg temp6;
always @(posedge clock)
begin
temp6 <= eleventh ^ twelfth;
out5 <= temp6 | twelfth;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> const int N = 1123; const double eps = 1e-6; const int inf = (int)1e9 + 123; using namespace std; int n, m; char a[N][N]; int mini = inf; int d[N][N]; int sum(int x, int y, int x2, int y2) { return d[x2][y2] - d[x - 1][y2] - d[x2][y - 1] + d[x - 1][y - 1]; } bool check(int x, int y, int sx, int sy) { if (sum(sx, sy, sx + x - 1, sy + y - 1) != x * y) return 0; int sz = sum(sx, sy, sx + x - 1, sy + y - 1); while (1) { if (sx + x <= n && sum(sx + x, sy, sx + x, sy + y - 1) == y) { sx++; sz += y; continue; } if (sy + y <= m && sum(sx, sy + y, sx + x - 1, sy + y) == x) { if (sum(sx, sy + y, sx + x - 1, sy + y) != x) return 0; sy++; sz += x; continue; } break; } if (d[n][m] != sz) return 0; return 1; } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> a[i][j]; d[i][j] = d[i - 1][j] + d[i][j - 1] - d[i - 1][j - 1] + (a[i][j] == X ? 1 : 0); } int x = -1, y = -1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (a[i][j] == X ) { x = i; y = j; break; } if (x != -1) break; } if (x == -1) { cout << -1; return 0; } int cnt = 0; for (int i = x; i <= n; i++) { if (a[i][y] == X ) cnt++; else break; } for (int i = 1; i <= m; i++) if (y + i - 1 <= m && check(cnt, i, x, y) && mini > cnt * i) mini = cnt * i; cnt = 0; for (int i = y; i <= m; i++) { if (a[x][i] == X ) cnt++; else break; } for (int i = 1; i <= n; i++) if (x + i - 1 <= m && check(i, cnt, x, y) && mini > i * cnt) mini = i * cnt; if (mini == inf) mini = -1; cout << mini; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod1(long long x) { if (x >= 0) { return x; } return -x; } vector<long long> countDigit(long long n) { vector<long long> ret; while (n != 0) { ret.push_back(n % 10); n = n / 10; } return ret; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm1(long long a, long long b) { return (a / gcd(a, b)) * b; } bool prime[1000000]; void SieveOfEratosthenes(long long n) { memset(prime, true, sizeof(prime)); prime[1] = false; for (long long p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long i = p * p; i <= n; i += p) prime[i] = false; } } } bool isPowerOfTwo(long long n) { if (n == 0) return false; return (ceil(log2(n)) == floor(log2(n))); } bool PowerOfFour(long long num) { if (num <= 0) return false; while (num != 1) { if (num % 4 != 0) return false; num = num / 4; } return true; } bool compare(pair<long long, long long> p1, pair<long long, long long> p2) { if (p1.first != p2.first) { return p1.first > p2.first; } else { p1.second > p2.second; } } bool compare1(pair<long long, long long> p1, pair<long long, long long> p2) { if (p1.second != p2.second) { return p1.second < p2.second; } else { p1.first < p2.first; } } bool isPalindrome(string str) { long long l = 0; long long h = str.size() - 1; while (h > l) { if (str[l++] != str[h--]) { return false; } } return true; } vector<long long> primef(long long n) { vector<long long> v; if (n == 1) { return v; } while (n % 2 == 0) { v.push_back(2); n = n / 2; } for (long long i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { v.push_back(i); n = n / i; } } if (n > 2) v.push_back(n); return v; } long long mod = 1000000007; long long fact1(long long x) { if (x < 2) { return 1; } return (x * fact1(x - 1)) % mod; } long long power1(long long x, long long y) { long long r = 1; while (y > 0) { r = (r % mod * x % mod) % mod; y--; } return r; } bool isp(long long x) { if (x >= 0) { long long sr = sqrt(x); return (sr * sr == x); } return false; } bool isPri(long long n) { if (n <= 1) return false; for (long long i = 2; i < n; i++) if (n % i == 0) return false; return true; } long long power2(long long x, long long y, long long p) { long long res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } long long gcdExtended(long long a, long long b, long long *x, long long *y) { if (a == 0) { *x = 0, *y = 1; return b; } long long x1, y1; long long gcd = gcdExtended(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } long long modInverse(long long b, long long m) { long long x, y; long long g = gcdExtended(b, m, &x, &y); if (g != 1) return -1; return (x % m + m) % m; } long long ask(long long val) { cout << val << endl; fflush(stdout); long long x; cin >> x; return x; } void solve() { long long n; cin >> n; string s; cin >> s; long long ret = INT_MAX; for (long long i = 0; i < 26; i++) { long long l = 0; long long r = n - 1; long long c = 0; while (l <= r) { if (s[l] == s[r]) { l++; r--; continue; } if (s[l] == i + a ) { l++; c++; continue; } if (s[r] == i + a ) { r--; c++; continue; } c = INT_MAX; break; } ret = min(ret, c); } if (ret == INT_MAX) { cout << -1 << endl; } else { cout << ret << endl; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 0x7fffffff / 2; int n, m; int fa[maxn]; int vis[maxn]; struct edge { int u; int v; int w; } e[maxn]; struct ex { int mi; int mx; int sum; } ex[maxn]; int father(int x) { if (x != fa[x]) fa[x] = father(fa[x]); return fa[x]; } void join(int x, int y) { ex[father(y)].mi = min(ex[father(y)].mi, ex[father(x)].mi); ex[father(y)].mx = max(ex[father(y)].mx, ex[father(x)].mx); ex[father(y)].sum += ex[father(x)].sum; fa[father(x)] = father(y); } int judge_node(int x) { x = father(x); int mi = ex[x].mi; int mx = ex[x].mx; int sum = ex[x].sum; if (mi == -inf) return 1; mi = ((mi - 1) * mi) / 2; mx = ((mx + 1) * mx) / 2; if ((mx - mi) != sum) return 1; else return 0; } void init(int u, int v) { ex[u].sum = u; ex[v].sum = v; ex[u].mx = u; ex[u].mi = u; ex[v].mx = v; ex[v].mi = v; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; i++) { fa[i] = i; ex[i].mi = inf; ex[i].mx = -inf; ex[i].sum = 0; } for (int i = 1; i <= m; i++) { cin >> e[i].u >> e[i].v; init(e[i].u, e[i].v); } for (int i = 1; i <= m; i++) { if (father(e[i].u) != father(e[i].v)) { join(e[i].u, e[i].v); } } int ans = 0; int mxx = -inf, last; for (int i = 1; i <= n; i++) { if (judge_node(i) && vis[father(i)] == 0) { int l = ex[father(i)].mi; int r = ex[father(i)].mx; for (int j = l; j < r; j++) { if (father(j) != father(i)) { join(i, j); ans++; last = j; } l = ex[father(i)].mi; r = ex[father(i)].mx; } vis[father(last)] = 1; } } cout << ans << endl; return 0; }
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.