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//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.1 (lin64) Build Mon Apr 27 19:07:21 MDT 2015
//Date : Sat Aug 8 15:14:35 2015
//Host : edinburgh running 64-bit Ubuntu 15.04
//Command : generate_target opl3_cpu_wrapper.bd
//Design : opl3_cpu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module opl3_cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
ac_mclk,
ac_mute_n,
clk125,
i2s_sclk,
i2s_sd,
i2s_ws,
iic_0_scl_io,
iic_0_sda_io,
led);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output ac_mclk;
output ac_mute_n;
input clk125;
output i2s_sclk;
output i2s_sd;
output i2s_ws;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]led;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire ac_mclk;
wire ac_mute_n;
wire clk125;
wire i2s_sclk;
wire i2s_sd;
wire i2s_ws;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]led;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
opl3_cpu opl3_cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.ac_mclk(ac_mclk),
.ac_mute_n(ac_mute_n),
.clk125(clk125),
.i2s_sclk(i2s_sclk),
.i2s_sd(i2s_sd),
.i2s_ws(i2s_ws),
.led(led));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, len; char str[55][25]; long long f[(1 << 20) + 10], bin[55]; double ans[(1 << 20) + 10]; double res; int main() { int i, j, k, c; bin[0] = 1; for (i = 1; i < 55; i++) bin[i] = (bin[i - 1] << 1); scanf( %d , &n); for (i = 0; i < n; i++) scanf( %s , str[i]); len = strlen(str[1]); for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (i != j) { int same = 0; for (k = 0; k < len; k++) { if (str[i][k] == str[j][k]) same |= bin[k]; } f[same] |= bin[j]; } } } for (i = bin[len] - 1; i >= 0; i--) { for (j = 0; j < len; j++) { if (i & bin[j]) { f[i ^ bin[j]] |= f[i]; } } } ans[0] = 1; for (i = 0; i < bin[len]; i++) { for (c = j = 0; j < len; j++) { if (i & bin[j]) c++; } for (j = 0; j < len; j++) { if (!(i & bin[j])) ans[i | bin[j]] += ans[i] / (len - c); } for (j = 0; j < n; j++) { if (f[i] & bin[j]) res += ans[i]; } } printf( %.10f n , res / n); return 0; }
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#include <bits/stdc++.h> #define all(v) (v).begin(), (v).end() #define sortv(v) sort(all(v)) #define uniqv(v) (v).erase(unique(all(v)), (v).end()) #define pb push_back #define FI first #define SE second #define lb lower_bound #define ub upper_bound #define mp make_pair #define test 1 #define TEST if(test) using namespace std; typedef long long ll; typedef pair<int, int> pii; typedef pair<ll, ll> pll; typedef vector<int> vi; const int MOD = 1000000007; // 998244353 const int INF = 2e9; const ll INFLL = 1e18; const int MAX_N = 100; int T; int N, K; int h[MAX_N+1]; int main(){ scanf( %d , &T); while(T--){ scanf( %d%d , &N, &K); for(int i=1; i<=N; i++){ scanf( %d , &h[i]); } bool tf = true; int ans = 0; for(int i=1; i<=K; i++){ int pos = 1; while(pos!=N){ if(h[pos]>=h[pos+1]) pos++; else break; } if(pos==N){ tf = false; printf( -1 n ); break; }else{ ans = pos; h[pos]++; } } if(tf){ printf( %d n , ans); } } return 0; }
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#include <bits/stdc++.h> using namespace std; struct node { int a, ord; } p[10005]; int b[10005]; bool cmp(node a, node b) { return a.a < b.a; } int main() { int n; while (~scanf( %d , &n)) { memset(b, 0, sizeof(b)); for (int i = 0; i < n; i++) { scanf( %d , &p[i].a); b[p[i].a]++; p[i].ord = i + 1; } sort(p, p + n, cmp); int sum = 1; int ss[2], A = 0; int sss = -1; int flag = 1; int i; for (i = 1; i < n; i++) { if (p[i].a == p[i - 1].a) flag++; else { if (flag >= 3) { sss = p[i - 1].a; flag = -1; break; } else if (flag == 2) ss[A++] = p[i - 1].a; flag = 1; if (A == 2) { flag = -2; break; } } } if (flag >= 3) { sss = p[i - 1].a; flag = -1; } else if (flag == 2) ss[A++] = p[i - 1].a; flag = 1; if (A == 2) { flag = -2; } if (sss != -1) flag = -1; if (flag > 0) cout << NO << endl; else { cout << YES << endl; if (flag == -1) { for (int i = 0; i < 3; i++) { flag = 1; for (int j = 0; j < n; j++) { if (j != 0) printf( ); if (flag && p[j].a == sss) { if (i == 0) printf( %d %d %d , p[j].ord, p[j + 1].ord, p[j + 2].ord); else if (i == 1) printf( %d %d %d , p[j + 1].ord, p[j + 2].ord, p[j].ord); else printf( %d %d %d , p[j + 2].ord, p[j].ord, p[j + 1].ord); j += 2; flag = 0; } else printf( %d , p[j].ord); } printf( n ); } } else { for (int i = 0; i < 3; i++) { for (int j = 0; j < n; j++) { if (j != 0) printf( ); if (i == 0 && p[j].a == ss[0]) { printf( %d %d , p[j].ord, p[j + 1].ord); j++; } else if (i == 1 && p[j].a == ss[0]) { printf( %d %d , p[j + 1].ord, p[j].ord); j++; } else if (i == 2 && p[j].a == ss[1]) { printf( %d %d , p[j + 1].ord, p[j].ord); j++; } else printf( %d , p[j].ord); } printf( n ); } } } } return 0; }
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#include <bits/stdc++.h> using namespace std; void enter(vector<long long int> &ar) { long long int n = ar.size(); for (long long int i = 0; i < n; i++) { cin >> ar[i]; } } void show(vector<long long int> &a) { long long int n = a.size(); for (long long int i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; } void SieveOfEratosthenes(int n, vector<long long int> &pri) { vector<bool> prime(n + 1, true); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { pri.push_back(p); for (int i = p * p; i <= n; i += p) prime[i] = false; } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; string s; cin >> ws; cin >> s; cin >> ws; vector<long long int> a(n); for (long long int i = 0; i < n; i++) { a[i] = s[i] - 0 ; } vector<long long int> sum(n, 0); sum[0] = a[0]; for (long long int i = 1; i < n; i++) { sum[i] = sum[i - 1] + a[i]; } vector<long long int> dp(n); for (long long int i = n - 1; i >= 0; i--) { long long int add_one = a[i]; if (i + k <= n - 1) { dp[i] = min(dp[i + k] + ((a[i] == 1) ? 0 : 1) + sum[i + k - 1] - sum[i], ((a[i] == 1) ? 1 : 0) + sum[n - 1] - sum[i]); } else { dp[i] = min(((a[i] == 1) ? 0 : 1) + sum[n - 1] - sum[i], ((a[i] == 1) ? 1 : 0) + sum[n - 1] - sum[i]); } } long long int ans; for (long long int i = 0; i < n; i++) { if (i) { dp[i] += sum[i - 1]; ans = min(ans, dp[i]); } else { ans = dp[i]; } } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); for (auto &x : v) cin >> x; int mine = *min_element(v.begin(), v.end()); vector<int> temp; for (int i = 0; i < n; i++) { if (v[i] == mine) temp.push_back(i); } for (int i = 0; i < temp.size() - 1; i++) temp[i] = temp[i + 1] - temp[i]; cout << *min_element(temp.begin(), temp.end() - 1) << endl; }
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#include <bits/stdc++.h> using namespace std; int binarySearch(int a[], int l, int r, int x); int main() { int n, m, i, temp; vector<int> v1; vector<int> v2; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { scanf( %d , &temp); v1.push_back(temp); } for (i = 0; i < m; i++) { scanf( %d , &temp); v2.push_back(temp); } for (i = 0; i < n; i++) { if (find(v2.begin(), v2.end(), v1[i]) != v2.end()) { printf( %d , v1[i]); } } printf( n ); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { { long long i, j, n, a, b, c, d, mx, mn; cin >> n >> a >> b >> c >> d; mx = max(a + b, a + c); mx = max(mx, b + d); mx = max(mx, c + d); mn = min(a + b, a + c); mn = min(mn, b + d); mn = min(mn, c + d); if (mx + 1 <= mn + n) { i = min(a + b + n, mn + n); j = max(mx + 1, a + b + 1); cout << n * (i - j + 1); } else cout << 0 ; } return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { long long d, k, tc, tf, tr, res = 100 * 100 * 100 * 100LL; scanf( %lld , &d); ; scanf( %lld , &k); ; scanf( %lld , &tc); ; scanf( %lld , &tf); ; scanf( %lld , &tr); ; if (k >= d) return 0 * printf( %lld , d * tc); if (k * tc + tr >= k * tf) return 0 * printf( %lld , k * tc + (d - k) * tf); long long chk = d / k; long long bach_gya = d % k; printf( %lld , tr * (chk - 1) + tc * chk * k + min(bach_gya * tc + tr, bach_gya * tf)); }
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#include <bits/stdc++.h> using namespace std; struct NODE { char w[4]; }; NODE tmp; vector<NODE> st, stt; bool use[10]; int bull, cow; char ss[6]; void back(int index) { if (index == 4) { int i, j, b, c; for (i = 0, b = 0, c = 0; i < 4; ++i) for (j = 0; j < 4; ++j) if (tmp.w[i] == ss[j]) { if (i == j) b++; else c++; } if (b == bull && c == cow) { st.push_back(tmp); } } else { int i; for (i = 0; i < 10; ++i) { if (use[i]) continue; tmp.w[index] = 0 + i; use[i] = true; back(index + 1); use[i] = false; } } } int main() { int i, k, j, num, m, n, b, c; while (scanf( %d , &num) == 1) { st.clear(); scanf( %s %d %d , ss, &bull, &cow); memset(use, 0, sizeof(use)); back(0); for (i = 2; i <= num; ++i) { scanf( %s %d %d , ss, &bull, &cow); stt.clear(); for (j = 0, k = st.size(); j < k; ++j) { for (m = 0, b = 0, c = 0; m < 4; ++m) { for (n = 0; n < 4; ++n) { if (st[j].w[m] == ss[n]) { if (m == n) ++b; else ++c; } } } if (b == bull && c == cow) stt.push_back(st[j]); } st.clear(); for (j = 0, k = stt.size(); j < k; ++j) st.push_back(stt[j]); } if (st.size() > 1) puts( Need more data ); else if (st.size() < 1) puts( Incorrect data ); else { for (i = 0; i < 4; ++i) printf( %c , st[0].w[i]); putchar( n ); } } return 0; }
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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_BEHAVIORAL_V
|
`timescale 1 ns / 1 ps
`ifdef DEBUG
`ifndef DEBUGM
`define DEBUGM
`include "debug_module.v"
`endif
`endif
module BUF(A, Y);
input A;
output Y;
assign Y = A;
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,A);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
module NOTcm(A, Y);
`ifdef REALT
parameter tpdm=0.8,tpdM=3.4,tpdt=1.6;
`else
parameter tpdm=0,tpdM=0,tpdt=0;
`endif
input A;
output Y;
assign #(tpdm:tpdt:tpdm) Y = ~A;
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,A);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
module NANDcm(A, B, Y);
`ifdef REALT
parameter tpdm=0.8,tpdM=3.4,tpdt=1.6;
`else
parameter tpdm=0,tpdM=0,tpdt=0;
`endif
input A, B;
output Y;
assign #(tpdm:tpdt:tpdm) Y = ~(A & B);
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,A|B);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
module NORcm(A, B, Y);
`ifdef REALT
parameter tpdm=0.8,tpdM=3.4,tpdt=1.6;
`else
parameter tpdm=0,tpdM=0,tpdt=0;
`endif
input A, B;
output Y;
assign #(tpdm:tpdt:tpdm) Y = ~(A | B);
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,A|B);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
module DFF(C, D, Q);
`ifdef REALT
parameter tsetup = 1.2,thold = 1.5, tpdm=0.8, tpdt=2.3, tpdM=3.8;
`else
parameter tsetup = 1.2,thold = 1.5, tpdm=0,tpdM=0,tpdt=0;
`endif
input C, D;
output reg Q;
`ifdef DEBUG
wire err,err_setup, err_hold;
setup_time_violation tsu(err_setup,D,C,tsetup);
hold_time_violation tho(err_hold,D,C,thold);
xor xo1(err,err_setup,err_hold);
`endif
always @(posedge C)
#(tpdm:tpdt:tpdM) Q <= D;
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,Q);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else
Q <= D;
`ifdef DEBUGM
parameter power_rev_time=`PRTIME;
wire [31:0] contador;
reg enb;
potencia p(contador,enb,Q);
integer cur_time;
initial
begin
enb=1;
#(`PRTIME) $display("%d", contador);
end
`endif
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 15:55:33 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_clk_wiz_1_0 -prefix
// system_clk_wiz_1_0_ system_clk_wiz_1_0_sim_netlist.v
// Design : system_clk_wiz_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module system_clk_wiz_1_0
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1));
endmodule
module system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz
(clk_out1,
clk_in1);
output clk_out1;
input clk_in1;
wire clk_in1;
wire clk_in1_system_clk_wiz_1_0;
wire clk_out1;
wire clk_out1_system_clk_wiz_1_0;
wire clkfbout_buf_system_clk_wiz_1_0;
wire clkfbout_system_clk_wiz_1_0;
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_system_clk_wiz_1_0),
.O(clkfbout_buf_system_clk_wiz_1_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_system_clk_wiz_1_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_system_clk_wiz_1_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(10),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(5),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_system_clk_wiz_1_0),
.CLKFBOUT(clkfbout_system_clk_wiz_1_0),
.CLKIN1(clk_in1_system_clk_wiz_1_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(clk_out1_system_clk_wiz_1_0),
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { string s, a; a = hello ; cin >> s; int i, j, k = 0; for (i = 0, j = 0; j < a.size(); i++) { if (i >= s.size()) break; if (s[i] == a[j]) { j++; } } if (j == a.size()) cout << YES << endl; else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int N, edge; pair<int, int> E[2][200002]; vector<int> V[2][200002]; int in[2][200002], out[2][200002]; bool S[2][200002], isdel[2][200002]; vector<pair<pair<int, int>, int> > ARBf[2][4 * 200002], ARBs[2][4 * 200002]; int Ap1, Ap2, Apv, Ax1, Ax2; vector<int> auxst; void updatef(int w, int nod, int i1, int i2) { ARBf[w][nod].push_back(make_pair(make_pair(Ap1, Ap2), Apv)); if (i1 == i2) return; int mid = (i1 + i2) / 2; if (Ap1 <= mid) updatef(w, nod * 2, i1, mid); else updatef(w, nod * 2 + 1, mid + 1, i2); } void erasef(int w, int nod, int i1, int i2) { if (Ax1 <= i1 && i2 <= Ax2) { while (!ARBf[w][nod].empty() && (ARBf[w][nod].back().first.second > Ax2 || isdel[w][ARBf[w][nod].back().second])) { if (!isdel[w][ARBf[w][nod].back().second]) { auxst.push_back(ARBf[w][nod].back().second); isdel[w][ARBf[w][nod].back().second] = true; } ARBf[w][nod].pop_back(); } return; } int mid = (i1 + i2) / 2; if (Ax1 <= mid) erasef(w, nod * 2, i1, mid); if (Ax2 > mid) erasef(w, nod * 2 + 1, mid + 1, i2); } void updates(int w, int nod, int i1, int i2) { ARBs[w][nod].push_back(make_pair(make_pair(Ap1, Ap2), Apv)); if (i1 == i2) return; int mid = (i1 + i2) / 2; if (Ap2 <= mid) updates(w, nod * 2, i1, mid); else updates(w, nod * 2 + 1, mid + 1, i2); } void erases(int w, int nod, int i1, int i2) { if (Ax1 <= i1 && i2 <= Ax2) { while (!ARBs[w][nod].empty() && (ARBs[w][nod].back().first.first < Ax1 || isdel[w][ARBs[w][nod].back().second])) { if (!isdel[w][ARBs[w][nod].back().second]) { auxst.push_back(ARBs[w][nod].back().second); isdel[w][ARBs[w][nod].back().second] = true; } ARBs[w][nod].pop_back(); } return; } int mid = (i1 + i2) / 2; if (Ax1 <= mid) erases(w, nod * 2, i1, mid); if (Ax2 > mid) erases(w, nod * 2 + 1, mid + 1, i2); } void Dfs(int w, int x) { S[w][x] = true; in[w][x] = ++in[w][0]; for (auto it = V[w][x].begin(); it != V[w][x].end(); ++it) if (!S[w][*it]) Dfs(w, *it); out[w][x] = in[w][0]; } int main() { cin.sync_with_stdio(false); cin >> N; for (int w = 0; w < 2; ++w) for (int i = 2, nod; i <= N; ++i) { cin >> nod; V[w][i].push_back(nod); V[w][nod].push_back(i); E[w][i - 1] = make_pair(min(i, nod), max(i, nod)); } cin >> edge; for (int w = 0; w < 2; ++w) Dfs(w, 1); for (int w = 0; w < 2; ++w) { vector<pair<pair<int, int>, int> > aux; for (int i = 1; i <= N - 1; ++i) { if (w == 0 && i == edge) continue; Ap1 = in[!w][E[w][i].first], Ap2 = in[!w][E[w][i].second], Apv = i; if (Ap1 > Ap2) swap(Ap1, Ap2); aux.push_back(make_pair(make_pair(Ap1, Ap2), Apv)); } sort(aux.begin(), aux.end()); for (int i = int(aux.size()) - 1; i >= 0; --i) { Ap1 = aux[i].first.first, Ap2 = aux[i].first.second, Apv = aux[i].second; updates(w, 1, 1, N); swap(aux[i].first.first, aux[i].first.second); } sort(aux.begin(), aux.end()); for (int i = 0; i < int(aux.size()); ++i) { swap(aux[i].first.first, aux[i].first.second); Ap1 = aux[i].first.first, Ap2 = aux[i].first.second, Apv = aux[i].second; updatef(w, 1, 1, N); } } vector<int> st; st.push_back(edge); for (int i = 0; !st.empty(); ++i) { if (i & 1) printf( Red n ); else printf( Blue n ); int w = i % 2; auxst.clear(); sort(st.begin(), st.end()); for (int j = 0; j < int(st.size()); ++j) { int e = st[j]; printf( %d , e); if (in[w][E[w][e].first] < in[w][E[w][e].second]) { Ax1 = in[w][E[w][e].second]; Ax2 = out[w][E[w][e].second]; } else { Ax1 = in[w][E[w][e].first]; Ax2 = out[w][E[w][e].first]; } erasef(!w, 1, 1, N); erases(!w, 1, 1, N); } st = auxst; printf( n ); } }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benavides
//
// Create Date: 21:40:24 02/29/2016
// Design Name: MDF
// Module Name: D:/ISE/Proyecto1/TB_MDF.v
// Project Name: Proyecto1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
// Inputs
reg clk;
reg rst;
reg [3:0] entrada;
// Outputs
wire salida;
wire [15:0]q;
// Instantiate the Unit Under Test (UUT)
MDF uut (
.clk(clk),
.rst(rst),
.entrada(entrada),
.salida(salida),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
entrada = 0;
// Wait 100 ns for global reset to finish
#10;
entrada = 4'b1111;
#10000;
entrada = 4'b1010;
end
always #1000 clk = ~clk;
/* initial
begin
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,rst,div,clkd);
end
initial
#500 $finish;
*/
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long n, a[100007], x, ans, t, res, tmp; vector<long long> v, cur; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long int i = 0; i < n; i++) { cin >> x; if (x) v.push_back(i); } if (v.size() < 2) { cout << -1; return 0; } if (v.size() < 4) { if (v.size() == 2) cout << v[1] - v[0]; else cout << v[2] - v[0]; return 0; } ans = 1e12; for (long int i = 2; i * i <= v.size(); i++) { if (v.size() % i != 0) continue; tmp = i; for (long int k = 0; k < 2; k++, i = v.size() / i) { t = 0; res = 0; for (auto j : v) { cur.push_back(j); t++; if (t % i == 0) { t = 0; for (auto h : cur) res += abs(cur[i / 2] - h); cur.clear(); } } ans = min(ans, res); } i = tmp; } res = 0; for (auto i : v) { res += abs(i - v[v.size() / 2]); } cout << min(res, ans); }
|
#include <bits/stdc++.h> using namespace std; void init() {} const int N = 1e6 + 34; const int INF = 1e9 + 34; vector<int> ans[2]; vector<int> es[N]; int n, m, v1, v2; int c[N]; void dfs(int v, int q) { if (c[v] && c[v] != q + 1) { cout << -1 ; exit(0); } if (c[v]) return; c[v] = q + 1; ans[q].push_back(v + 1); for (int w : es[v]) { dfs(w, 1 - q); } } int main() { init(); cin >> n >> m; for (int i = 0; i < m; i++) { cin >> v1 >> v2; v1--; v2--; es[v1].push_back(v2); es[v2].push_back(v1); } for (int i = 0; i < n; i++) if (!c[i]) dfs(i, 0); for (int i = 0; i < 2; i++) { cout << ans[i].size() << n ; for (int w : ans[i]) cout << w << ; cout << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 5; const int inf = 1e9 + 5e5 + 19; int n, k; int a[maxn]; bool in_b[maxn]; struct fenwick { int n; vector<int> val; void init(int _n) { n = _n; val.assign(n + 5, -1); } void update(int x, int k) { for (; x <= n; x += x & -x) val[x] = max(val[x], k); } int get(int x) { int res = -1; for (; x > 0; x -= x & -x) res = max(res, val[x]); return res; } } tree; void read_input() { cin >> n >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; for (; k > 0; --k) { int x; cin >> x; in_b[x] = true; } in_b[0] = in_b[n + 1] = true; a[0] = -inf; a[n + 1] = inf; } int calc(const vector<int>& arr, int L, int R) { if ((int)arr.size() == 0) return 0; vector<int> vals; for (int i = 0; i < (int)arr.size(); ++i) vals.push_back(arr[i] - i); sort(vals.begin(), vals.end()); vals.erase(unique(vals.begin(), vals.end()), vals.end()); tree.init((int)vals.size()); int max_val = 0; for (int i = 0; i < (int)arr.size(); ++i) { if (arr[i] <= L || arr[i] >= R) continue; if (arr[i] - L - 1 >= i && R - arr[i] - 1 >= (int)arr.size() - i - 1) { int val = 1; int p = lower_bound(vals.begin(), vals.end(), arr[i] - i) - vals.begin() + 1; val = max(val, tree.get(p) + 1); tree.update(p, val); max_val = max(max_val, val); } } return (int)arr.size() - max_val; } void solve() { int ans = 0; for (int i = 0; i <= n;) { int j = i + 1; while (j <= n && !in_b[j]) ++j; int L = a[i], R = a[j]; if (R - L < j - i) { cout << -1 n ; return; } vector<int> arr; ++i; for (; i < j; ++i) arr.push_back(a[i]); ans += calc(arr, L, R); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); read_input(); solve(); }
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR32_RD_0 3'b000
`define S_SGR32_RD_1 3'b001
`define S_SGR32_RD_2 3'b010
`define S_SGR32_RD_3 3'b011
`define S_SGR32_RD_WAIT 3'b100
`define S_SGR32_CAP_0 3'b000
`define S_SGR32_CAP_1 3'b001
`define S_SGR32_CAP_2 3'b010
`define S_SGR32_CAP_3 3'b011
`define S_SGR32_CAP_RDY 3'b100
`timescale 1ns/1ns
module sg_list_reader_32 #(
parameter C_DATA_WIDTH = 9'd32
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [2:0] rRdState=`S_SGR32_RD_0, _rRdState=`S_SGR32_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [2:0] rCapState=`S_SGR32_CAP_0, _rCapState=`S_SGR32_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = !rRdState[2]; // Not S_SGR32_RD_0
assign VALID = rCapState[2]; // S_SGR32_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & !rRdState[2]); // Not S_SGR32_RD_0
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR32_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR32_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR32_CAP_0: begin
if (rDataValid) begin
_rAddr[31:0] = rData;
_rCapState = `S_SGR32_CAP_1;
end
end
`S_SGR32_CAP_1: begin
if (rDataValid) begin
_rAddr[63:32] = rData;
_rCapState = `S_SGR32_CAP_2;
end
end
`S_SGR32_CAP_2: begin
if (rDataValid) begin
_rLen = rData;
_rCapState = `S_SGR32_CAP_3;
end
end
`S_SGR32_CAP_3: begin
if (rDataValid)
_rCapState = `S_SGR32_CAP_RDY;
end
`S_SGR32_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR32_CAP_0;
end
default: begin
_rCapState = `S_SGR32_CAP_0;
end
endcase
case (rRdState)
`S_SGR32_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_1;
end
`S_SGR32_RD_1: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_2;
end
`S_SGR32_RD_2: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_3;
end
`S_SGR32_RD_3: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR32_RD_WAIT;
end
`S_SGR32_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR32_RD_0;
end
default: begin
_rRdState = `S_SGR32_RD_0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> int ff[] = {1, 1, 2, 6, 24, 120, 720, 5040, 40320, 362880}; long long dp[16][9 + 1]; void solve(int *bb, int l) { int k, d, i, e, j; memset(dp, 0, sizeof dp); k = ((l) < (bb[0]) ? (l) : (bb[0])); for (i = 0; i <= k; i++) dp[0][i] = 1; for (d = 0; d < 16 - 1; d++) for (i = 0; i < l; i++) if (dp[d][i] > 0) for (e = d + 1; e < 16; e++) { k = ((l) < (i + bb[e]) ? (l) : (i + bb[e])); for (j = i + 1; j <= k; j++) dp[e][j] += dp[d][i] * (ff[j] / ff[i] / ff[j - i]); } } int main() { static int bb[16]; static char cc[9 + 1]; int k, t, l, i, d, d_; long long cnt; scanf( %d%d , &k, &t); for (i = 0; i < 16; i++) bb[i] = t; l = 9; solve(bb, l); for (i = 1; i <= l; i++) { cnt = 0; for (d = 0; d < 16; d++) cnt += dp[d][i]; cnt = cnt / 16 * 15; if (k > cnt) k -= cnt; else { l = i; break; } } for (i = 1; i <= l; i++) for (d_ = i == 1 ? 1 : 0; d_ < 16; d_++) if (bb[d_] > 0) { bb[d_]--; solve(bb, l - i); cnt = 0; for (d = 0; d < 16; d++) cnt += dp[d][l - i]; if (k > cnt) k -= cnt; else { cc[i - 1] = d_ < 10 ? 0 + d_ : a + d_ - 10; break; } bb[d_]++; } printf( %s n , cc); return 0; }
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Oct 31 12:11:23 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top dbg_ila -prefix
// dbg_ila_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module dbg_ila(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, B, c; cin >> n >> k >> B >> c; long long a[n]; for (int i = 0; i < n; i++) cin >> a[i]; long long x = *min_element(a, a + n); for (int i = 0; i < n; i++) a[i] = a[i] - x; B = min(B, 5 * c); long long ans = 1e18; for (int t = 0; t < 5; t++) { pair<long long, long long> b[n]; for (int i = 0; i < n; i++) { b[i] = {a[i], 0}; while (b[i].first % 5 != t) { b[i].first++; b[i].second += c; } b[i].first /= 5; } sort(b, b + n); priority_queue<long long> G; long long suma = 0; for (int i = 0; i < n; i++) { if (G.size() >= k - 1) { ans = min(ans, b[i].second + b[i].first * B * (k - 1) + suma); } G.push(b[i].second - b[i].first * B); suma += b[i].second - b[i].first * B; while (G.size() >= k) { suma -= G.top(); G.pop(); } } } cout << ans << n ; }
|
#include <bits/stdc++.h> using namespace std; char s[2005]; const int mod = 1e9 + 7; int n, k, t[2005]; int a[2005][2005], b[2005][2005]; int mp(const int &a, const int &b) { return (int)(1ll * a * b % mod); } int add(const int &a, const int &b) { return (a + b) % mod; } int main() { scanf( %d %d %s , &n, &k, s); int i, j, u, v, d, e; for (i = 0; i < n; i++) t[i + 1] = s[i] - a ; for (i = 0; i <= n + 1; i++) a[i][0] = 1; for (i = n; i > 0; i--) { v = n - i; for (j = 0; j <= k; j++) { b[i][j] = add(b[i + 1][j], mp(t[i], a[i + 1][j])); a[i][j] = add(a[i][j], b[i][j]); for (u = 0; u <= v / 2; u++) { e = j - (v - u + 1) * (u + 1); if (e < 0) break; if (2 * u == v) a[i][j] = add(mp(25 - t[i + u], a[i + u + 1][e]), a[i][j]); else { a[i][j] = add(mp(25 - t[i + u], a[i + u + 1][e]), a[i][j]); a[i][j] = add(mp(25 - t[i + v - u], a[i + v - u + 1][e]), a[i][j]); } } } } printf( %d n , a[1][k]); }
|
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; void solve() { long long int a, s; cin >> a >> s; vector<long long int> b; while (s) { long long int x = a % 10; long long int y = s % 10; if (y >= x) { b.push_back(y - x); } else { s /= 10; y += 10 * (s % 10); if (y > x && y <= 18 && y >= 10) { b.push_back(y - x); } else { cout << -1 << n ; return; } } s /= 10; a /= 10; } if (a) { cout << -1 << n ; return; } while (b.back() == 0) b.pop_back(); reverse((b).begin(), (b).end()); for (long long int x : b) cout << x; cout << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int T = 1; cin >> T; for (long long int i = 1; i <= T; i++) { solve(); } return 0; }
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_mutex (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 2;
parameter invert_mode = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] test_expr;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_MUTEX";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_mutex_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_mutex
|
//-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
module apl2c_connect(autoinoutmodport_type_intf ctl_i,
/*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
// Beginning of automatic in/out/inouts (from modport)
input [4:0] inst,
input isel_t isel,
input replay
// End of automatics
);
/*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
// Beginning of automatic assignments from modport
assign ctl_i.inst = inst;
assign ctl_i.isel = isel;
assign ctl_i.replay = replay;
// End of automatics
endmodule
interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
import uvm_pkg::*;
import ap_defines::*;
logic [4:0] inst;
isel_t isel;
logic replay;
clocking ctl_cb @(posedge clk);
input inst;
input isel;
input replay;
endclocking: ctl_cb
modport ctl_mp(clocking ctl_cb);
endinterface
// Local Variables:
// verilog-typedef-regexp:"_t"
// End:
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100005, MAX_K = 105; int N, M, K, S; int good_type[MAX_N]; int distances[MAX_N][MAX_K]; vector<int> adj[MAX_N]; int dist[MAX_N]; void RunBFS(int type) { queue<int> q; for (int i = 0; i < N; ++i) { if (good_type[i] == type) { distances[i][type] = 0; q.push(i); } } while (!q.empty()) { int u = q.front(); q.pop(); for (const int& v : adj[u]) { if (distances[v][type] == -1) { distances[v][type] = distances[u][type] + 1; q.push(v); } } } } int main() { scanf( %d %d %d %d , &N, &M, &K, &S); for (int i = 0; i < N; ++i) { scanf( %d , &good_type[i]); --good_type[i]; } for (int i = 0; i < M; ++i) { int u, v; scanf( %d %d , &u, &v); --u; --v; adj[u].push_back(v); adj[v].push_back(u); } memset(distances, -1, sizeof distances); for (int i = 0; i < K; ++i) { RunBFS(i); } for (int i = 0; i < N; ++i) { sort(distances[i], distances[i] + K); long long sum = 0; for (int j = 0; j < S; ++j) sum += distances[i][j]; printf( %lld , sum); } return 0; }
|
#include <bits/stdc++.h> using ll = long long; using namespace std; const int INF = 1e8; const int N = 2e5 + 2; int n, m, k; vector<int> G[N]; int a[N]; bool sp[N]; int distN[N], dist1[N]; int suf[N]; bool cmp(int& v, int& u) { return dist1[v] < dist1[u]; } void bfsN() { for (int i = 0; i < n; i++) distN[i] = INF; distN[n - 1] = 0; queue<pair<int, int>> q; q.push({0, n - 1}); while (!q.empty()) { int v = q.front().second; int d = q.front().first; q.pop(); for (auto u : G[v]) { if (distN[u] > d + 1) { distN[u] = d + 1; q.push({distN[u], u}); } } } } void bfs1() { for (int i = 0; i < n; i++) dist1[i] = INF; dist1[0] = 0; queue<pair<int, int>> q; q.push({0, 0}); while (!q.empty()) { int v = q.front().second; ; int d = q.front().first; q.pop(); for (auto u : G[v]) { if (dist1[u] > d + 1) { dist1[u] = d + 1; q.push({dist1[u], u}); } } } } int getAns() { int ans = 0; for (int i = k - 2; i >= 0; i--) ans = max(ans, dist1[a[i]] + 1 + suf[i + 1]); return min(ans, distN[0]); } signed main() { cin >> n >> m >> k; for (int i = 0; i < k; i++) { cin >> a[i], a[i]--; sp[a[i]] = true; } for (int i = 0; i < m; i++) { int v, u; cin >> v >> u, v--, u--; G[v].push_back(u); G[u].push_back(v); } bfsN(); bfs1(); sort(a, a + k, cmp); suf[k - 1] = distN[a[k - 1]]; for (int i = k - 2; i >= 0; i--) suf[i] = max(suf[i + 1], distN[a[i]]); cout << getAns() << n ; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_prqq_buf.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Dqta Queue Buffer
// Top level Module: jbi_ncio_prqq_buf
// Where Instantiated: jbi_ncio
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ncio_prqq_buf(/*AUTOARG*/
// Outputs
prqq_rdata,
// Inputs
clk, hold, testmux_sel, scan_en, csr_16x81array_margin, prqq_csn_wr,
prqq_csn_rd, prqq_waddr, prqq_raddr, prqq_wdata
);
input clk;
input hold;
input testmux_sel;
input scan_en;
input [4:0] csr_16x81array_margin;
input prqq_csn_wr;
input prqq_csn_rd;
input [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_waddr;
input [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_raddr;
input [`JBI_PRQQ_WIDTH-1:0] prqq_wdata;
output [`JBI_PRQQ_WIDTH-1:0] prqq_rdata;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_PRQQ_WIDTH-1:0] prqq_rdata;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [81-`JBI_PRQQ_WIDTH-1:0] dangle;
//
// Code start here
//
bw_rf_16x81 #(1, 1, 1, 0) u_prqq_buf
(.rd_clk(clk), // read clock
.wr_clk(clk), // read clock
.csn_rd(prqq_csn_rd), // read enable -- active low
.csn_wr(prqq_csn_wr), // write enable -- active low
.hold(hold), // Bypass signal -- unflopped -- bypass input data when 0
.scan_en(scan_en), // Scan enable unflopped
.margin(csr_16x81array_margin), // Delay for the circuits--- set to 10101
.rd_a(prqq_raddr), // read address
.wr_a(prqq_waddr), // Write address
.di({ {81-`JBI_PRQQ_WIDTH{1'b0}},
prqq_wdata[`JBI_PRQQ_WIDTH-1:0] }), // Data input
.testmux_sel(testmux_sel), // bypass signal -- unflopped -- testmux_sel = 1 bypasses di to do
.si(), // scan in -- NOT CONNECTED
.so(), // scan out -- TIED TO ZERO
.listen_out(), // Listening flop--
.do( {dangle,
prqq_rdata[`JBI_PRQQ_WIDTH-1:0]} ) // Data out
);
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; bitset<6> a, b; int main() { int n; cin >> n; a = bitset<6>(n); b.set(5, a[5]); b.set(4, a[0]); b.set(3, a[2]); b.set(2, a[3]); b.set(1, a[1]); b.set(0, a[4]); cout << b.to_ulong(); }
|
#include <bits/stdc++.h> using namespace std; const bool testcase = 0; const long long int mod1 = 1000000007; const long long int mod2 = 998244353; const long long int N = 1e5 + 5; std::vector<long long int> adj[N]; std::vector<long long int> vis(N, false); bool hasLoop(long long int i, long long int p) { vis[i] = true; bool ans = false; for (auto it : adj[i]) { if (!vis[it]) { ans |= hasLoop(it, i); } else if (it != p) { ans |= true; } } return ans; } void dfs(long long int i) { vis[i] = true; for (auto it : adj[i]) { if (!vis[it]) { dfs(it); } } } void solve() { long long int n, m; cin >> n >> m; for (int i = 0; i < m; ++i) { long long int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } bool ok = true; dfs(1); for (int i = 1; i <= n; ++i) { ok &= (vis[i] == 1); } if (ok && n == m) { cout << FHTAGN! n ; } else { cout << NO n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); int T_T = 1; if (testcase) { cin >> T_T; } while (T_T--) { solve(); } return 0; }
|
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module j4a(input wire clk,
input wire resetq,
output wire uart0_wr,
output wire uart0_rd,
output wire [7:0] uart_w,
input wire uart0_valid,
input wire [7:0] uart0_data
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
/* verilator lint_off UNUSED */
wire [12:0] code_addr;
wire [15:0] return_top;
/* verilator lint_on UNUSED */
wire [1:0] io_thread;
wire [3:0] kill_slot_rq;
wire [15:0] insn;
assign kill_slot_rq = 4'b0;
reg [15:0] ram_prog[0:4095] /* verilator public_flat */;
always @(posedge clk) begin
//$display("pc=%x", code_addr * 2);
insn <= ram_prog[code_addr[11:0]];
if (mem_wr)
ram_prog[mem_addr[12:1]] <= dout;
end
j4 _j4(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn),
.io_slot(io_thread),
.return_top(return_top),
.kill_slot_rq(kill_slot_rq));
// ###### IO SIGNALS ####################################
// note that io_din has to be delayed one instruction, but it depends upon io_addr_, which is, so it does.
// it doesn't hurt to run dout_ delayed too.
reg io_wr_, io_rd_;
reg [15:0] dout_;
/* verilator lint_off UNUSED */
reg [15:0] io_addr_;
/* verilator lint_on UNUSED */
reg [1:0] io_thread_;
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
io_thread_ <= io_thread;
if (io_rd | io_wr)
io_addr_ <= mem_addr;
else
io_addr_ <= 0; // because we don't want to actuate things unless there really is a read or write.
end
// ###### UART ##########################################
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];
// always @(posedge clk) begin
// if (uart0_wr)
// $display("--- out %x %c", uart_w, uart_w);
// if (uart0_rd)
// $display("--- in %x %c", uart0_data, uart0_data);
// end
// ###### IO PORTS ######################################
/* bit READ WRITE
1000 12 UART RX UART TX
2000 13 misc.in
*/
reg [15:0] taskexec;
reg [47:0] taskexecn;
always @* begin
case (io_thread_)
2'b00: taskexec = 16'b0;// all tasks start with taskexec zeroed, and all tasks will try to run all code from zero.
2'b01: taskexec = taskexecn[15:0];
2'b10: taskexec = taskexecn[31:16];
2'b11: taskexec = taskexecn[47:32];
endcase
end
assign io_din =
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {12'd0, 1'b0, 1'b0, uart0_valid, 1'b1} : 16'd0) |
(io_addr_[14] ? {taskexec}: 16'd0)|
(io_addr_[15] ? {14'd0, io_thread_}: 16'd0);
always@( posedge clk) begin
if (io_wr_ ) begin // any slot can change any other's schedule, except none can mess with slot 0
if (io_addr_[8]) taskexecn[15:0] <= dout_;
if (io_addr_[9]) taskexecn[31:16] <= dout_;
if (io_addr_[10]) taskexecn[47:32] <= dout_;
end // it is even possible to assign the same task to multiple threads, although this isn't recommended.
if (io_addr_[15]==1'b1) $display("io_thread_ = %d, io_din = %d", io_thread_, io_din);
case ({io_wr_ , io_addr_[14], io_thread_})
4'b1100: kill_slot_rq <= dout_[3:0];
4'b1101: kill_slot_rq <= 4'b0010;
4'b1111: kill_slot_rq <= 4'b1000;
4'b1110: kill_slot_rq <= 4'b0100;
default: kill_slot_rq <= 4'b0000;
endcase
end
endmodule
|
//-----------------------------------------------------
// Design Name : ram_dp_ar_aw
// File Name : ram_dp_ar_aw.v
// Function : Asynchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module ram_dp_ar_aw (
address_0 , // address_0 Input
data_0 , // data_0 bi-directional
cs_0 , // Chip Select
we_0 , // Write Enable/Read Enable
oe_0 , // Output Enable
address_1 , // address_1 Input
data_1 , // data_1 bi-directional
cs_1 , // Chip Select
we_1 , // Write Enable/Read Enable
oe_1 // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input [ADDR_WIDTH-1:0] address_0 ;
input cs_0 ;
input we_0 ;
input oe_0 ;
input [ADDR_WIDTH-1:0] address_1 ;
input cs_1 ;
input we_1 ;
input oe_1 ;
//--------------Inout Ports-----------------------
inout [DATA_WIDTH-1:0] data_0 ;
inout [DATA_WIDTH-1:0] data_1 ;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] data_0_out ;
reg [DATA_WIDTH-1:0] data_1_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
//--------------Code Starts Here------------------
// Memory Write Block
// Write Operation : When we_0 = 1, cs_0 = 1
always @ (address_0 or cs_0 or we_0 or data_0
or address_1 or cs_1 or we_1 or data_1)
begin : MEM_WRITE
if ( cs_0 && we_0 ) begin
mem[address_0] <= data_0;
end else if (cs_1 && we_1) begin
mem[address_1] <= data_1;
end
end
// Tri-State Buffer control
// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
assign data_0 = (cs_0 && oe_0 && !we_0) ? data_0_out : 8'bz;
// Memory Read Block
// Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
always @ (address_0 or cs_0 or we_1 or oe_0)
begin : MEM_READ_0
if (cs_0 && !we_0 && oe_0) begin
data_0_out <= mem[address_0];
end else begin
data_0_out <= 0;
end
end
//Second Port of RAM
// Tri-State Buffer control
// output : When we_0 = 0, oe_0 = 1, cs_0 = 1
assign data_1 = (cs_1 && oe_1 && !we_1) ? data_1_out : 8'bz;
// Memory Read Block 1
// Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
always @ (address_1 or cs_1 or we_1 or oe_1)
begin : MEM_READ_1
if (cs_1 && !we_1 && oe_1) begin
data_1_out <= mem[address_1];
end else begin
data_1_out <= 0;
end
end
endmodule // End of Module ram_dp_ar_aw
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const long long mod = 1e9 + 7; void rd(int &x) { int f = 1; x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } void pr(int x) { printf( %d n , x); } int n, a[55][55]; int go[4][2] = {-1, -1, 1, -1, -1, 1, 1, 1}; pair<int, int> g[4]; int main() { int odd = 1, even = 2; cin >> n; if (n == 1) { puts( 1 ); return 0; } if (n == 3) { printf( 2 1 4 n3 5 7 n6 9 8 n ); return 0; } int k = (n + 1) / 2; int l = k, r = k; for (int i = (1); i <= k; i++) { for (int j = (l); j <= r; j++) a[i][j] = odd, odd += 2; l--, r++; } l = k, r = k; for (int i = n; i >= k + 1; i--) { for (int j = (l); j <= r; j++) a[i][j] = odd, odd += 2; l--, r++; } for (int i = (1); i <= n; i++) { for (int j = (1); j <= n; j++) { if (a[i][j] == 0) a[i][j] = even, even += 2; } } for (int i = (1); i <= n; i++) { for (int j = (1); j <= n; j++) printf( %d , a[i][j]); puts( ); } }
|
`define bsg_buf_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_40_BUFFD8BWP_b``bits buf_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_40_BUFFD8BWP_horiz_b``bits buf_gate (.i0(i),.o);\
end
module bsg_buf #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_buf_macro(89) else
`bsg_buf_macro(88) else
`bsg_buf_macro(87) else
`bsg_buf_macro(86) else
`bsg_buf_macro(85) else
`bsg_buf_macro(84) else
`bsg_buf_macro(83) else
`bsg_buf_macro(82) else
`bsg_buf_macro(81) else
`bsg_buf_macro(80) else
`bsg_buf_macro(79) else
`bsg_buf_macro(78) else
`bsg_buf_macro(77) else
`bsg_buf_macro(76) else
`bsg_buf_macro(75) else
`bsg_buf_macro(74) else
`bsg_buf_macro(73) else
`bsg_buf_macro(72) else
`bsg_buf_macro(71) else
`bsg_buf_macro(70) else
`bsg_buf_macro(69) else
`bsg_buf_macro(68) else
`bsg_buf_macro(67) else
`bsg_buf_macro(66) else
`bsg_buf_macro(65) else
`bsg_buf_macro(64) else
`bsg_buf_macro(63) else
`bsg_buf_macro(62) else
`bsg_buf_macro(61) else
`bsg_buf_macro(60) else
`bsg_buf_macro(59) else
`bsg_buf_macro(58) else
`bsg_buf_macro(57) else
`bsg_buf_macro(56) else
`bsg_buf_macro(55) else
`bsg_buf_macro(54) else
`bsg_buf_macro(53) else
`bsg_buf_macro(52) else
`bsg_buf_macro(51) else
`bsg_buf_macro(50) else
`bsg_buf_macro(49) else
`bsg_buf_macro(48) else
`bsg_buf_macro(47) else
`bsg_buf_macro(46) else
`bsg_buf_macro(45) else
`bsg_buf_macro(44) else
`bsg_buf_macro(43) else
`bsg_buf_macro(42) else
`bsg_buf_macro(41) else
`bsg_buf_macro(40) else
`bsg_buf_macro(39) else
`bsg_buf_macro(38) else
`bsg_buf_macro(37) else
`bsg_buf_macro(36) else
`bsg_buf_macro(35) else
`bsg_buf_macro(34) else
`bsg_buf_macro(33) else
`bsg_buf_macro(32) else
`bsg_buf_macro(31) else
`bsg_buf_macro(30) else
`bsg_buf_macro(29) else
`bsg_buf_macro(28) else
`bsg_buf_macro(27) else
`bsg_buf_macro(26) else
`bsg_buf_macro(25) else
`bsg_buf_macro(24) else
`bsg_buf_macro(23) else
`bsg_buf_macro(22) else
`bsg_buf_macro(21) else
`bsg_buf_macro(20) else
`bsg_buf_macro(19) else
`bsg_buf_macro(18) else
`bsg_buf_macro(17) else
`bsg_buf_macro(16) else
`bsg_buf_macro(15) else
`bsg_buf_macro(14) else
`bsg_buf_macro(13) else
`bsg_buf_macro(12) else
`bsg_buf_macro(11) else
`bsg_buf_macro(10) else
`bsg_buf_macro(9) else
`bsg_buf_macro(8) else
`bsg_buf_macro(7) else
`bsg_buf_macro(6) else
`bsg_buf_macro(5) else
`bsg_buf_macro(4) else
`bsg_buf_macro(3) else
`bsg_buf_macro(2) else
`bsg_buf_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_buf)
|
#include <bits/stdc++.h> using namespace std; int n, F[500007], wartosc[500007], Fat[500007]; bool valid_number[500007], valid_edges[300007], query_node[500007]; int Find(int a) { return (a == Fat[a] ? a : Fat[a] = Find(Fat[a])); } inline void Union(int a, int b) { a = Find(a); b = Find(b); F[a] = F[b] = ++n; Fat[a] = Fat[b] = F[n] = Fat[n] = n; } vector<int> G[500007]; int pre[500007], pos[500007], order[500007], nr; bool visited[500007]; void DFS(int v) { visited[v] = 1; pre[v] = ++nr; order[nr] = v; for (auto i : G[v]) if (!visited[i]) DFS(i); pos[v] = nr; } int tree[1 << 20], M = 1; inline void zrob_drzewa() { for (int i = 1; i <= n; i++) if (F[i] != i) { G[i].push_back(F[i]); G[F[i]].push_back(i); } for (int i = 1; i <= n; i++) if (F[i] == i) DFS(i); while (M < n) M *= 2; for (int i = 1; i <= n; i++) tree[i + M - 1] = wartosc[order[i]]; for (int i = M - 1; i > 0; i--) tree[i] = max(tree[i * 2], tree[i * 2 + 1]); } void remove_invalid(int v) { if (valid_number[tree[v]]) return; tree[v] = 0; if (v >= M) return; remove_invalid(v * 2); remove_invalid(v * 2 + 1); tree[v] = max(tree[v * 2], tree[v * 2 + 1]); } int maks(int a, int b, int v = 1, int p = 1, int k = M) { if (p > b || k < a) return 0; if (p >= a && k <= b) { remove_invalid(v); return tree[v]; } return max(maks(a, b, v * 2, p, (p + k) / 2), maks(a, b, v * 2 + 1, (p + k) / 2 + 1, k)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int m, q; cin >> n >> m >> q; n = n; for (int i = 1, a; i <= n; i++) { cin >> wartosc[i]; valid_number[wartosc[i]] = true; F[i] = i; Fat[i] = i; } vector<pair<int, int>> edges(m + 1); for (int i = 1; i <= m; i++) { cin >> edges[i].first >> edges[i].second; valid_edges[i] = true; } vector<pair<int, int>> queries(q); for (int i = 0; i < q; i++) { cin >> queries[i].first >> queries[i].second; if (queries[i].first == 2) valid_edges[queries[i].second] = false; } for (int i = 1; i <= m; i++) if (valid_edges[i]) Union(edges[i].first, edges[i].second); int Res[q]; for (int i = q - 1; i >= 0; i--) { if (queries[i].first == 1) { int v = queries[i].second; v = Find(v); Res[i] = v; } else { int j = queries[i].second; int a = edges[j].first, b = edges[j].second; Union(a, b); } } zrob_drzewa(); for (int i = 0; i < q; i++) { if (queries[i].first == 2) continue; int v = Res[i]; int res = maks(pre[v], pos[v]); cout << res << n ; valid_number[res] = false; valid_number[0] = true; } }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[111], maxx; int main() { cin >> n >> m; for (int i = 0; i < n; ++i) cin >> a[i]; maxx = a[0]; for (int i = 1; i < n; ++i) maxx = max(maxx, a[i]); int tot = 0; for (int i = 0; i < n; ++i) tot += maxx - a[i]; int res2 = maxx + m; m -= tot; if (m < 0) m = 0; int res1 = maxx + m / n; if (m % n) ++res1; cout << res1 << << res2; return 0; }
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module green_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 7: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 7: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 7: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = read_mux_out;
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_2_V
`define SKY130_FD_SC_HDLL__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_2_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_pll_diff_rx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example differential input receiver for clock and data using PLL
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_pll_diff_rx (
input reset, // reset (active high)
input [5:0] datain_p, datain_n, // lvds data inputs
input clkin_p, clkin_n, // lvds clock input
output [41:0] dummy_out) ; // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 7 ; // Set the serdes factor to 8
parameter integer D = 6 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
wire [6:0] clk_iserdes_data ;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_pll_s8_diff #(
.S (S),
.CLKIN_PERIOD (6.700),
.PLLD (1),
.PLLX (S),
.BS ("TRUE")) // Parameter to enable bitslip TRUE or FALSE (has to be true for video applications)
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclk (rx_bufpll_clk_xn),
.pattern1 (7'b1100001), // default values for 7:1 video applications
.pattern2 (7'b1100011),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_pll_x1 (rx_bufg_x1),
.bitslip (bitslip),
.reset (rst),
.datain (clk_iserdes_data),
.rx_pll_lckd (), // PLL locked - only used if a 2nd BUFPLL is required
.rx_pllout_xs (), // Multiplied PLL clock - only used if a 2nd BUFPLL is required
.rx_bufpll_lckd (rx_bufpll_lckd)) ;
// Data Inputs
assign not_bufpll_lckd = ~rx_bufpll_lckd ;
serdes_1_to_n_data_s8_diff #(
.S (S),
.D (D))
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclk (rx_bufpll_clk_xn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bitslip),
.reset (not_bufpll_lckd),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int r1, c1, r2, c2, a[505][505], N, M, dx[4] = {-1, 0, 1, 0}, dy[4] = {0, 1, 0, -1}; bool viz[505][505]; char c; queue<pair<int, int> > Q; bool bfs(int x, int y, int xx, int yy) { Q.push(make_pair(x, y)); while (Q.size()) { pair<int, int> nod = Q.front(); Q.pop(); for (int i = 0; i < 4; ++i) { int nx = nod.first + dx[i], ny = nod.second + dy[i]; if (a[nx][ny] == 1 && nx == xx && ny == yy) { return 1; } else if (a[nx][ny] == 2) { --a[nx][ny]; Q.push(make_pair(nx, ny)); } } } return 0; } int main() { cin.sync_with_stdio(false); cin >> N >> M; for (int i = 1; i <= N; ++i) for (int j = 1; j <= M; ++j) { cin >> c; if (c == . ) a[i][j] = 2; else a[i][j] = 1; } cin >> r1 >> c1 >> r2 >> c2; if (bfs(r1, c1, r2, c2)) cout << YES ; else cout << NO ; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_1_V
`define SKY130_FD_SC_HS__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_1 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, f, k; scanf( %lld %lld %lld %lld , &a, &b, &f, &k); long long ans = 0; long long cfuel = b; for (int i = 0; i < k - 1; i++) { if (i % 2 == 0) { if (cfuel >= 2 * a - f) { cfuel -= a; } else if (cfuel >= f && b >= a - f) { ans++; cfuel = b - (a - f); } else { printf( -1 n ); return 0; } } else { if (cfuel >= a + f) { cfuel -= a; } else if (cfuel >= a - f && b >= f) { ans++; cfuel = b - f; } else { printf( -1 n ); return 0; } } } if (k % 2) { if (cfuel >= a) { } else if (cfuel >= f && b >= a - f) { ans++; } else { printf( -1 n ); return 0; } } else { if (cfuel >= a) { } else if (cfuel >= a - f && b >= f) { ans++; } else { printf( -1 n ); return 0; } } printf( %lld n , ans); }
|
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style
module cog_ram
(
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [31:0] r [511:0];
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long double gimmearea(long double x1, long double y1, long double r1, long double x2, long double y2, long double r2, long double c) { long double t1, t2, p1, p2; t1 = acos((r1 * r1 + c - r2 * r2) / (2 * r1 * sqrt(c))); t2 = acos((r2 * r2 + c - r1 * r1) / (2 * r2 * sqrt(c))); p1 = sin(2 * t1); p2 = sin(2 * t2); return (r1 * r1 * t1 + r2 * r2 * t2) - 0.5 * (r1 * r1 * p1 + r2 * r2 * p2); } int main() { long double x1, y1, r1, x2, y2, r2, c, ans; cin >> x1 >> y1 >> r1 >> x2 >> y2 >> r2; c = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); if (c >= (r1 + r2) * (r1 + r2)) { ans = 0; } else if (sqrt(c) <= fabs(r1 - r2)) { if (r2 < r1) r1 = r2; ans = 3.14159265358979323846264338 * r1 * r1; } else { ans = gimmearea(x1, y1, r1, x2, y2, r2, c); } cout << fixed << setprecision(15); cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b, long long m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } int binomial(int n, int k) { if (k == 0 || k == n) return 1; return binomial(n - 1, k - 1) + binomial(n - 1, k); } bool prime[10000]; void Sieve(long long int n) { memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (int i = p * p; i <= n; i += p) prime[i] = false; } } } vector<int> f; int print(int n) { for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { if (n / i == i) f.push_back(i); else { f.push_back(i); f.push_back(n / i); } } } return f.size(); } pair<int, int> fib(int n) { if (n == 0) return {0, 1}; auto p = fib(n >> 1); int c = p.first * (2 * p.second - p.first); int d = p.first * p.first + p.second * p.second; if (n & 1) return {d, c + d}; else return {c, d}; } int main() { int n; cin >> n; int k = 0; vector<int> v; Sieve(n); for (int i = 2; i <= n; i++) { if (prime[i]) { int q = 1; while (q <= (n / i)) { q *= i; v.push_back(q); } } } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// File : wb_sum_buffer.v
// Creation date : 20.04.2017
// Creation time : 10:25:17
// Description : Maintains calculated sum of input values. The output value is the latest result. When new input value is set, the oldest is discarded and deducted from the result.
// Created by : TermosPullo
// Tool : Kactus2 3.4.88 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:peripheral:sum_buffer:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral/sum_buffer/1.0/sum_buffer.1.0.xml
//-----------------------------------------------------------------------------
module wb_sum_buffer #(
parameter BUFFER_SIZE = 16, // How much buffer is allocated for both directions.
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of the both transferred and inputted data.
parameter BASE_ADDRESS = 'h0F00, // The first referred address of the master.
parameter BUFFER_INDEX_WIDTH = $clog2(BUFFER_SIZE), // How many bits are needed to index the buffer.
parameter COLUMN_WIDTH = 1 // Width of each column in sum.
) (
// Interface: wb_slave
input [ADDR_WIDTH-1:0] adr_i, // The address of the data.
input cyc_i, // Asserted by master for transfer.
input [DATA_WIDTH-1:0] dat_i, // Data from master to slave.
input stb_i, // Asserted, when this specific slave is selected.
input we_i, // Write = 1, Read = 0.
output reg ack_o, // Slave asserts acknowledge.
output reg [DATA_WIDTH-1:0] dat_o, // Data from slave to master.
output reg err_o, // Indicates abnormal cycle termination.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// The contained buffer.
reg [DATA_WIDTH-1:0] memory [BUFFER_SIZE-1:0];
// The result of the operation.
reg [DATA_WIDTH-1:0] result;
// The position of the next input data.
reg [BUFFER_INDEX_WIDTH-1:0] index;
// Addressable unit bits.
localparam AUB = 8;
// How many AUBs come in each input and output.
localparam AU_IN_DATA = DATA_WIDTH/AUB;
// The state.
reg [0:0] state;
// The value that was previously in the current index.
integer lastValue;
// The value that will be in the current index.
integer newValue;
// Used to iterate the buffer.
integer iterator;
// The available states.
parameter [0:0]
S_WAIT = 1'd0, // Waiting for cyc_i & stb_i
S_DEASSERT = 1'd1; // Deassert acknowledgement.
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
ack_o <= 0; // Obviously, there is nothing to acknowledge by default.
dat_o <= 0; // No output by default.
err_o <= 0; // No error by default.
state <= S_WAIT; // Wait signals from the masters at reset.
result <= 0;
index <= 0;
// The buffer is zeroed in reset.
for (iterator = 0; iterator < BUFFER_SIZE; iterator = iterator +1) begin
memory[iterator] <= 0;
end
end
else begin
if (state == S_WAIT) begin
// Wait signal from the master.
if ( cyc_i == 1 && stb_i == 1 ) begin
// Master ok, check the address.
if (adr_i == BUFFER_SIZE+BASE_ADDRESS && we_i == 1) begin
// Address of the new value.
ack_o <= 1;
// Memorize for while what the new value will replace.
lastValue = memory[index];
// The new value. Values may be scaled if so desired.
newValue = dat_i * COLUMN_WIDTH;
// Place the value in the correct index.
memory[index] <= newValue;
// The result of the sum: Remove the replaced value, add the new value.
result <= result - lastValue + newValue;
// Step to the next index, which will be zero if the current index is the last.
if (index < BUFFER_SIZE-1) begin
index <= index + 1;
end
else begin
index <= 0;
end
end
else if (adr_i == BUFFER_SIZE+BASE_ADDRESS+AU_IN_DATA && we_i == 0) begin
// Address of the result was read, so output it.
ack_o <= 1;
dat_o = result;
end
else begin
// The specified address out-of-scope -> error!
err_o <= 1;
end
// Next thing is to deassert.
state <= S_DEASSERT;
end
end
else if (state == S_DEASSERT) begin
// Deassert acknowlegement, get ready to receive next one.
ack_o <= 0;
err_o <= 0;
state <= S_WAIT;
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Jie Xu.
//
// change these two parameters to see the speed differences
`define DATA_WIDTH 8
`define REP_COUNT4 `DATA_WIDTH/4
`define REP_COUNT2 `DATA_WIDTH/2
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [3:0] count4 = 0;
reg [1:0] count2 = 0;
reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}};
reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}};
reg [`DATA_WIDTH-1:0] res1;
reg [`DATA_WIDTH-1:0] res2;
reg [`DATA_WIDTH-1:0] res3;
reg [`DATA_WIDTH-1:0] res4;
drv1 t_drv1 [`DATA_WIDTH-1:0] (.colSelA(a), .datao(res1));
drv2 t_drv2 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .datao(res2));
drv3 t_drv3 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .datao(res3));
drv4 t_drv4 [`DATA_WIDTH-1:0] (.colSelA(a), .colSelB(b), .colSelC(c), .colSelD(d), .datao(res4));
always@(posedge clk)
begin
count2 <= count2 + 1;
count4 <= count4 + 1;
a <= {`REP_COUNT4{count4}};
b <= {`REP_COUNT4{count4}};
c <= {`REP_COUNT2{count2}};
d <= {`REP_COUNT2{count2}};
if (res1 != (a)) begin
$stop;
end
if (res2 != (a&b)) begin
$stop;
end
if (res3 != (a&b&c)) begin
$stop;
end
if (res4 != (a&b&c&d)) begin
$stop;
end
if (count4 > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module drv1
(input colSelA,
output datao
);
assign datao = colSelA;
endmodule
module drv2
(input colSelA,
input colSelB,
output datao
);
assign datao = colSelB & colSelA;
endmodule
module drv3
(input colSelA,
input colSelB,
input colSelC,
output datao
);
assign datao = colSelB & colSelA & colSelC;
endmodule
module drv4
(input colSelA,
input colSelB,
input colSelC,
input colSelD,
output datao
);
assign datao = colSelB & colSelA & colSelC & colSelD;
endmodule
|
#include <bits/stdc++.h> using namespace std; int ABS(int a) { if (a < 0) return (-a); return a; } void input() {} int a[100005]; int seg[100005]; int nxt[100005]; int hop[100005]; void readInt(int &n) { n = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) { n = n * 10 + ch - 48; ch = getchar(); } } int main() { input(); int n, q; readInt(n); readInt(q); int sq = sqrt(n); int c = 0, cnt = 0; for (int i = (0); i < (n); ++i) { readInt(a[i]); seg[i] = cnt; c++; if (c == sq) c = 0, cnt++; } for (int i = (n - 1); i >= (0); --i) { int to = i + a[i]; hop[i] = 1; if (to >= n) nxt[i] = -1; else if (seg[to] != seg[i]) nxt[i] = to; else { nxt[i] = nxt[to]; hop[i] += hop[to]; } } while (q--) { int type; readInt(type); if (type == 0) { int x, y; readInt(x); readInt(y); x--; int i = x; a[x] = y; while (i >= 0) { if (seg[i] != seg[x]) break; int to = i + a[i]; hop[i] = 1; if (to >= n) nxt[i] = -1; else if (seg[to] != seg[i]) nxt[i] = to; else { nxt[i] = nxt[to]; hop[i] += hop[to]; } i--; } } else { int x; readInt(x); x--; int ans = 0; int last = x; while (x != -1) { ans += hop[x]; last = x; x = nxt[x]; } while (last + a[last] < n) last = last + a[last]; printf( %d %d n , last + 1, ans); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[300010]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } long long ans = 0; vector<int> v; for (int i = 1; i <= n; ++i) { ans += a[i] / 2; if (a[i] % 2 != 0) { v.push_back(i); } } stack<int> q; if (v.size() == 0) { cout << ans << endl; return 0; } q.push(v[0]); for (int i = 1; i < v.size(); ++i) { if (q.size() && (v[i] - q.top()) % 2 != 0) { q.pop(); ans++; continue; } q.push(v[i]); } cout << ans << endl; return 0; }
|
// megafunction wizard: %In-System Sources and Probes%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 20; long long sum; int k, p, n, a[N + 1], i, b[N + 1], left_tree[N + 1], right_tree[N + 1]; vector<long long> leftv, rightv; void update(int index, int value, int tree[]) { while (index < N + 1) { tree[index] += value; index += (index & -index); } } int read(int index, int tree[]) { int sum = 0; while (index > 0) { sum += tree[index]; index -= (index & -index); } return sum; } int main() { cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b, b + n); for (i = 0; i < n; i++) { a[i] = upper_bound(b, b + n, a[i]) - b; } for (i = 0; i < n; i++) { update(a[i], 1, left_tree); leftv.push_back(read(N, left_tree) - read(a[i], left_tree)); } for (i = n - 1; i >= 0; i--) { rightv.push_back(read(a[i], right_tree)); update(a[i], 1, right_tree); } reverse(rightv.begin(), rightv.end()); for (i = 0; i < n; i++) { sum += rightv[i] * leftv[i]; } cout << sum; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; int n; struct ma { int x, vt; } a[105]; bool cmp(ma p, ma y) { return p.x < y.x; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].x; a[i].vt = i; } sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n / 2; i++) cout << a[i].vt << << a[n - i + 1].vt << endl; return 0; }
|
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int X = 0, w = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) w = -1; c = getchar(); } while (c >= 0 && c <= 9 ) X = X * 10 + c - 0 , c = getchar(); return X * w; } const int N = 200000 + 10; const int inf = 0x3f3f3f3f; int n, Q; char s[N]; int sum[N][26]; struct SuffixArray { int sa[N], rnk[N], height[N], x[N], y[N], z[N]; void SuffixSort() { int m = 256; for (int i = 1; i <= n; ++i) ++z[x[i] = s[i]]; for (int i = 2; i <= m; ++i) z[i] += z[i - 1]; for (int i = n; i; --i) sa[z[x[i]]--] = i; for (int k = 1; k < n; k <<= 1) { int p = 0; for (int i = n - k + 1; i <= n; ++i) y[++p] = i; for (int i = 1; i <= n; ++i) if (sa[i] > k) y[++p] = sa[i] - k; for (int i = 1; i <= m; ++i) z[i] = 0; for (int i = 1; i <= n; ++i) ++z[x[i]]; for (int i = 2; i <= m; ++i) z[i] += z[i - 1]; for (int i = n; i; --i) sa[z[x[y[i]]]--] = y[i], y[i] = 0; swap(x, y), x[sa[1]] = p = 1; for (int i = 2; i <= n; ++i) x[sa[i]] = (y[sa[i - 1]] == y[sa[i]] && y[sa[i - 1] + k] == y[sa[i] + k]) ? p : ++p; if (p == m) break; m = p; } } void GetHeight() { for (int i = 1; i <= n; ++i) rnk[sa[i]] = i; for (int i = 1, j = 0; i <= n; ++i) { if (j) --j; int p = sa[rnk[i] - 1]; while (s[i + j] == s[p + j]) ++j; height[rnk[i]] = j; } } int lg[N], st[18][N]; void buildST() { for (int i = 2; i <= n; ++i) lg[i] = lg[i >> 1] + 1; for (int i = 1; i <= n; ++i) st[0][i] = height[i]; for (int i = 1; i < 18; ++i) for (int j = 1; j <= n; ++j) st[i][j] = min(st[i - 1][j], st[i - 1][j + (1 << (i - 1))]); } int qmin(int l, int r) { int t = lg[r - l + 1]; return min(st[t][l], st[t][r - (1 << t) + 1]); } int LCP(int x, int y) { if (rnk[x] > rnk[y]) swap(x, y); return qmin(rnk[x] + 1, rnk[y]); } } A, B; struct SegmentTree { int minv[N << 2], tag[N << 2]; SegmentTree() { memset(minv, 0x3f, sizeof(minv)), memset(tag, 0x3f, sizeof(tag)); } void update(int o, int l, int w) { tag[o] = min(tag[o], w), minv[o] = min(minv[o], l + w); } void pushup(int o) { minv[o] = min(minv[(o << 1)], minv[(o << 1 | 1)]); } void pushdown(int o, int l, int r) { int mid = (l + r) >> 1; if (tag[o] != inf) update((o << 1), l, tag[o]), update((o << 1 | 1), mid + 1, tag[o]), tag[o] = inf; } void modify(int o, int l, int r, int ql, int qr, int w) { if (ql <= l && r <= qr) { update(o, l, w); return; } int mid = (l + r) >> 1; pushdown(o, l, r); if (ql <= mid) modify((o << 1), l, mid, ql, qr, w); if (qr > mid) modify((o << 1 | 1), mid + 1, r, ql, qr, w); pushup(o); } int query(int o, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) return minv[o]; int mid = (l + r) >> 1, res = inf; pushdown(o, l, r); if (ql <= mid) res = min(res, query((o << 1), l, mid, ql, qr)); if (qr > mid) res = min(res, query((o << 1 | 1), mid + 1, r, ql, qr)); return res; } } L, R; void InitAA(SuffixArray &lcp_sa, SuffixArray &lcs_sa, SegmentTree &T) { for (int l = 1; l <= n / 2; ++l) for (int i = l, j = l << 1; j <= n; i += l, j += l) { int lcp = lcp_sa.LCP(i, j), lcs = lcs_sa.LCP(n - i + 1, n - j + 1); if (lcp + lcs - 1 >= l) T.modify(1, 1, n, i - lcs + 1, i + lcp - l, 2 * l - 1); } } bool CheckBorder(int l, int r) { int len = r - l + 1, S = sqrt(n) + 1; for (int i = 1; i < len && i <= S; ++i) if (A.LCP(l, r - i + 1) >= i) return 1; for (int i = A.rnk[l] - 1, h = A.height[i + 1], c = 0; i && c <= S && h > S; ++c, h = min(h, A.height[i--])) if (A.sa[i] >= l && A.sa[i] <= r && A.sa[i] + h > r) return 1; for (int i = A.rnk[l] + 1, h = A.height[i], c = 0; i <= n && c <= S && h > S; ++c, h = min(h, A.height[++i])) if (A.sa[i] >= l && A.sa[i] <= r && A.sa[i] + h > r) return 1; return 0; } bool CheckNS(int l, int r) { int flag = 1; for (int i = 0; i < 26; ++i) if (sum[r][i] - sum[l - 1][i] >= 2) { flag = 0; break; } return flag; } bool Check1(int l, int r) { int len = r - l + 1; for (int i = 1; i * i <= len; ++i) { if (len % i) continue; if (A.LCP(l, l + i) >= len - i) return 1; if (i != 1 && A.LCP(l, l + len / i) >= len - len / i) return 1; } return 0; } bool Check2(int l, int r) { if (CheckBorder(l, r)) return 1; if (L.query(1, 1, n, l, l) <= r) return 1; if (R.query(1, 1, n, n - r + 1, n - r + 1) <= n - l + 1) return 1; return 0; } bool Check3(int l, int r) { if (sum[r][s[l] - a ] - sum[l][s[l] - a ]) return 1; if (sum[r - 1][s[r] - a ] - sum[l - 1][s[r] - a ]) return 1; if (L.query(1, 1, n, l, r) <= r) return 1; return 0; } int main() { n = read(); scanf( %s , s + 1); for (int i = 1; i <= n; ++i) for (int j = 0; j < 26; ++j) sum[i][j] = sum[i - 1][j] + (j == s[i] - a ); A.SuffixSort(), A.GetHeight(), A.buildST(); reverse(s + 1, s + n + 1); B.SuffixSort(), B.GetHeight(), B.buildST(); reverse(s + 1, s + n + 1); InitAA(A, B, L), InitAA(B, A, R); Q = read(); while (Q--) { int l = read(), r = read(); if (CheckNS(l, r)) { puts( -1 ); continue; } if (Check1(l, r)) { puts( 1 ); continue; } if (Check2(l, r)) { puts( 2 ); continue; } if (Check3(l, r)) { puts( 3 ); continue; } puts( 4 ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const long long INF = (long long)5e18; const int MOD = 998244353; int add(int x, int y) { x += y; return x >= MOD ? x - MOD : x; } int sub(int x, int y) { x -= y; return x < 0 ? x + MOD : x; } int qpow(int x, int y) { int ret = 1; while (y) { if (y & 1) ret = (long long)(ret) * (x) % MOD; x = (long long)(x) * (x) % MOD; y >>= 1; } return ret; } void checkmin(int &x, int y) { if (x > y) x = y; } void checkmax(int &x, int y) { if (x < y) x = y; } void checkmin(long long &x, long long y) { if (x > y) x = y; } void checkmax(long long &x, long long y) { if (x < y) x = y; } inline int read() { int x = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } const int N = 5005; int n, a[N], dp[N]; int fac[N], ifac[N], lim[N]; void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (long long)(fac[i - 1]) * (i) % MOD; ifac[n] = qpow(fac[n], MOD - 2); for (int i = n - 1; i >= 0; i--) ifac[i] = (long long)(ifac[i + 1]) * (i + 1) % MOD; for (int i = 1; i <= n; i++) { for (int j = i - 1; j >= 1; j--) { if (a[j] * 2 <= a[i]) { lim[i] = j; break; } } } } void solve() { dp[0] = 1; if (a[n] < a[n - 1] * 2) { puts( 0 ); return; } for (int i = 1; i <= n; i++) { for (int j = lim[i]; j >= 0; j--) { int delta = lim[i] - lim[j] - 1, rest = n - lim[j] - 2; if (j == 0) delta++, rest++; dp[i] = add(dp[i], (long long)(dp[j]) * ((long long)(fac[rest]) * (ifac[rest - delta]) % MOD) % MOD); } } cout << dp[n] << endl; } int main() { init(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int ans = -1; map<pair<int, int>, bool> visited, mp; void bfs(int x1, int y1, int x2, int y2) { queue<pair<pair<int, int>, int>> q; q.push({{x1, y1}, 0}); while (!q.empty()) { auto z = q.front(); q.pop(); visited[z.first] = 1; if (z.first.first == x2 && z.first.second == y2) { ans = z.second; break; } int x = z.first.first, y = z.first.second; if (x - 1 >= 1 && !visited[{x - 1, y}] && mp[{x - 1, y}]) { visited[{x - 1, y}] = true; q.push({{x - 1, y}, z.second + 1}); } if (x + 1 <= 1e9 && !visited[{x + 1, y}] && mp[{x + 1, y}]) { visited[{x + 1, y}] = true; q.push({{x + 1, y}, z.second + 1}); } if (y - 1 >= 1 && !visited[{x, y - 1}] && mp[{x, y - 1}]) { visited[{x, y - 1}] = true; q.push({{x, y - 1}, z.second + 1}); } if (y + 1 <= 1e9 && !visited[{x, y + 1}] && mp[{x, y + 1}]) { visited[{x, y + 1}] = true; q.push({{x, y + 1}, z.second + 1}); } if (x + 1 <= 1e9 && y + 1 <= 1e9 && !visited[{x + 1, y + 1}] && mp[{x + 1, y + 1}]) { visited[{x + 1, y + 1}] = true; q.push({{x + 1, y + 1}, z.second + 1}); } if (x + 1 <= 1e9 && y - 1 >= 1 && !visited[{x + 1, y - 1}] && mp[{x + 1, y - 1}]) { visited[{x + 1, y - 1}] = true; q.push({{x + 1, y - 1}, z.second + 1}); } if (x - 1 >= 1 && y + 1 <= 1e9 && !visited[{x - 1, y + 1}] && mp[{x - 1, y + 1}]) { visited[{x - 1, y + 1}] = true; q.push({{x - 1, y + 1}, z.second + 1}); } if (x - 1 >= 1 && y - 1 >= 1 && !visited[{x - 1, y - 1}] && mp[{x - 1, y - 1}]) { visited[{x - 1, y - 1}] = true; q.push({{x - 1, y - 1}, z.second + 1}); } } } int main() { ; ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; int n; cin >> n; set<pair<int, pair<int, int>>> s; for (int i = 0; i < n; i++) { int r, a, b; cin >> r >> a >> b; s.insert({r, {a, b}}); } for (auto it : s) { for (int i = it.second.first; i <= it.second.second; i++) { mp[{it.first, i}] = true; } } mp[{x1, y1}] = true; mp[{x2, y2}] = true; bfs(x1, y1, x2, y2); cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int a[410], s[410], dp[60][410][2]; void su(int &a, int b) { if (b > a) a = b; } void lemon() { int n, m; scanf( %d%d , &n, &m); for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); for (int i = (1); i <= (n); i++) s[i] = s[i - 1] + a[i]; for (int k = (1); k <= (m); k++) for (int i = (1); i <= (n); i++) for (int flag = (0); flag <= (1); flag++) dp[k][i][flag] = -1000000000; for (int i = (1); i <= (n); i++) for (int j = (i); j <= (n); j++) { su(dp[1][j][0], -(s[j] - s[i - 1])); su(dp[1][j][1], s[j] - s[i - 1]); } for (int k = (1); k <= (m - 1); k++) for (int i = (1); i <= (n); i++) for (int flag = (0); flag <= (1); flag++) if (dp[k][i][flag] != -1000000000) { for (int j = (i + 1); j <= (n); j++) { if (k != m - 1) su(dp[k + 1][j][flag], dp[k][i][flag]); if (flag == 0) { if (k == m - 1) su(dp[k + 1][j][1 - flag], dp[k][i][flag] + (s[j] - s[i])); else su(dp[k + 1][j][1 - flag], dp[k][i][flag] + (s[j] - s[i]) * 2); } else { if (k == m - 1) su(dp[k + 1][j][1 - flag], dp[k][i][flag] - (s[j] - s[i])); else su(dp[k + 1][j][1 - flag], dp[k][i][flag] - (s[j] - s[i]) * 2); } } } int ans = -1000000000; for (int i = (1); i <= (n); i++) for (int flag = (0); flag <= (1); flag++) su(ans, dp[m][i][flag]); cout << ans << endl; } int main() { ios::sync_with_stdio(true); lemon(); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long h, n; int main() { cin >> h >> n; long long ans = 0; long long l = 1, r = (1LL << h); int dir = 0; for (int i = h - 1; i >= 0; i--) { ans++; long long mid = (l + r) / 2; if (dir == 0) { if (mid < n) { ans += (1LL << (i + 1)) - 1; dir = 0; l = mid + 1; } else { r = mid; dir = 1; } } else { if (n <= mid) { ans += (1LL << (i + 1)) - 1; dir = 1; r = mid; } else { l = mid + 1; dir = 0; } } } cout << ans << endl; }
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr16 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [15:0] Q,
input C0,
input C1,
input CE,
input [15:0] D0,
input [15:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr2 (
.Q(Q[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[2]),
.D1(D1[2]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr3 (
.Q(Q[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[3]),
.D1(D1[3]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr4 (
.Q(Q[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[4]),
.D1(D1[4]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr5 (
.Q(Q[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[5]),
.D1(D1[5]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr6 (
.Q(Q[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[6]),
.D1(D1[6]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr7 (
.Q(Q[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[7]),
.D1(D1[7]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr8 (
.Q(Q[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[8]),
.D1(D1[8]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr9 (
.Q(Q[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[9]),
.D1(D1[9]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr10 (
.Q(Q[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[10]),
.D1(D1[10]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr11 (
.Q(Q[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[11]),
.D1(D1[11]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr12 (
.Q(Q[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[12]),
.D1(D1[12]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr13 (
.Q(Q[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[13]),
.D1(D1[13]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr14 (
.Q(Q[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[14]),
.D1(D1[14]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr15 (
.Q(Q[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[15]),
.D1(D1[15]),
.R(R),
.S(S)
);
endmodule
|
module io1_sub(
/*AUTOARG*/
// Outputs
sec_out, lower_out,
// Inouts
sec_io, lower_io,
// Inputs
sec_ina, lower_ina
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input lower_ina; // To instio of instio.v
input sec_ina; // To instio of instio.v
// End of automatics
/*AUTOINOUT*/
// Beginning of automatic inouts (from unused autoinst inouts)
inout lower_io; // To/From instio of instio.v
inout sec_io; // To/From instio of instio.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output lower_out; // From instio of instio.v
output sec_out; // From instio of instio.v
// End of automatics
/* inst AUTO_TEMPLATE (
.lower_inb (1'b1),
)*/
instio instio (/*AUTOINST*/
// Outputs
.lower_out (lower_out),
.sec_out (sec_out),
// Inouts
.lower_io (lower_io),
.sec_io (sec_io),
// Inputs
.lower_ina (lower_ina),
.sec_ina (sec_ina));
endmodule
module instio (/*AUTOARG*/
// Outputs
lower_out, sec_out,
// Inouts
lower_io, sec_io,
// Inputs
lower_ina, sec_ina
);
input lower_ina;
inout lower_io;
output lower_out;
input sec_ina;
inout sec_io;
output sec_out;
wire lower_out = lower_ina | lower_io;
wire sec_out = sec_ina | sec_io;
endmodule
|
`include "../network_params.h"
module feature_map_buffer_ctrl(
input clock,
input reset,
input data_rdy,
input [`X_COORD_BITWIDTH:0] xcoord,
input [`Y_COORD_BITWIDTH:0] ycoord,
output reg [`FM_ADDR_BITWIDTH:0] addr,
output reg buffer_full
);
//assign addr = xcoord + (ycoord * `FM_ADDR_WIDTH'd`FM_WIDTH);
always@(posedge clock or negedge reset) begin
if(reset == 1'b0)
addr <= `FM_ADDR_WIDTH'd0;
else if (data_rdy)
if(xcoord[0]&ycoord[0])
addr <= addr + `FM_ADDR_WIDTH'd1;
else
addr <= addr;
else
addr <= `FM_ADDR_WIDTH'd0;
end // always
//// incriment address
//always@(*/*posedge clock or negedge reset*/) begin
// if(reset == 1'b0) begin
// addr <= `FM_ADDR_WIDTH'd0;
// end else begin
// if(data_rdy) begin
// // addr <= addr + `FM_ADDR_WIDTH'd0;
// addr <= xcoord + (ycoord * `FM_ADDR_WIDTH'd`FM_WIDTH);
// end else begin
// // reset addres
// addr <= `FM_ADDR_WIDTH'd0;
// end // rdy
// end // reset
//end // always
// set buffer full signal
always@(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
buffer_full <= 1'b0;
end else begin
// - 1 to adjust for 0 index
if (addr == `ADDR_MAX - 1) begin
buffer_full <= 1'b1;
end else begin
buffer_full <= 1'b0;
end // addr == max
end // reset
end // always
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module simpleuart (
input clk,
input resetn,
output ser_tx,
input ser_rx,
input [3:0] reg_div_we,
input [31:0] reg_div_di,
output [31:0] reg_div_do,
input reg_dat_we,
input reg_dat_re,
input [31:0] reg_dat_di,
output [31:0] reg_dat_do,
output reg_dat_wait
);
reg [31:0] cfg_divider;
reg [3:0] recv_state;
reg [31:0] recv_divcnt;
reg [7:0] recv_pattern;
reg [7:0] recv_buf_data;
reg recv_buf_valid;
reg [9:0] send_pattern;
reg [3:0] send_bitcnt;
reg [31:0] send_divcnt;
reg send_dummy;
assign reg_div_do = cfg_divider;
assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy);
assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0;
always @(posedge clk) begin
if (!resetn) begin
cfg_divider <= 1;
end else begin
if (reg_div_we[0]) cfg_divider[ 7: 0] <= reg_div_di[ 7: 0];
if (reg_div_we[1]) cfg_divider[15: 8] <= reg_div_di[15: 8];
if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16];
if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24];
end
end
always @(posedge clk) begin
if (!resetn) begin
recv_state <= 0;
recv_divcnt <= 0;
recv_pattern <= 0;
recv_buf_data <= 0;
recv_buf_valid <= 0;
end else begin
recv_divcnt <= recv_divcnt + 1;
if (reg_dat_re)
recv_buf_valid <= 0;
case (recv_state)
0: begin
if (!ser_rx)
recv_state <= 1;
recv_divcnt <= 0;
end
1: begin
if (2*recv_divcnt > cfg_divider) begin
recv_state <= 2;
recv_divcnt <= 0;
end
end
10: begin
if (recv_divcnt > cfg_divider) begin
recv_buf_data <= recv_pattern;
recv_buf_valid <= 1;
recv_state <= 0;
end
end
default: begin
if (recv_divcnt > cfg_divider) begin
recv_pattern <= {ser_rx, recv_pattern[7:1]};
recv_state <= recv_state + 1;
recv_divcnt <= 0;
end
end
endcase
end
end
assign ser_tx = send_pattern[0];
always @(posedge clk) begin
if (reg_div_we)
send_dummy <= 1;
send_divcnt <= send_divcnt + 1;
if (!resetn) begin
send_pattern <= ~0;
send_bitcnt <= 0;
send_divcnt <= 0;
send_dummy <= 1;
end else begin
if (send_dummy && !send_bitcnt) begin
send_pattern <= ~0;
send_bitcnt <= 15;
send_divcnt <= 0;
send_dummy <= 0;
end else
if (reg_dat_we && !send_bitcnt) begin
send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0};
send_bitcnt <= 10;
send_divcnt <= 0;
end else
if (send_divcnt > cfg_divider && send_bitcnt) begin
send_pattern <= {1'b1, send_pattern[9:1]};
send_bitcnt <= send_bitcnt - 1;
send_divcnt <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int B = 12; const int D = 64; const int MASK = 1030; int q, b; long long f[B][D][MASK]; long long sum[B][D]; long long call(int base, int rem, int mask) { if (rem <= 0) return mask == 0; long long &ret = f[base][rem][mask]; if (ret != -1) return ret; ret = 0; for (int i = 0; i < base; ++i) { ret += call(base, rem - 1, mask ^ 1 << i); } return ret; } long long solve(long long x) { if (x == 0) return 0; vector<int> v; while (x) { v.push_back(x % b); x /= b; } reverse(v.begin(), v.end()); int mask = 0, sz = v.size(); long long ans = 0; for (int i = 0; i < sz; ++i) { mask ^= 1 << v[i]; if (i + 1 < sz) { for (int j = 0; j < v[i + 1]; ++j) { ans += call(b, sz - 2 - i, mask ^ 1 << j); } } else { ans += (mask == 0); } } for (int i = 1; i < v[0]; ++i) { ans += call(b, sz - 1, 1 << i); } for (int i = 1; i < sz; ++i) { for (int j = 1; j < b; ++j) { ans += call(b, sz - 1 - i, 1 << j); } } return ans; } int main() { memset(f, -1, sizeof f); memset(sum, -1, sizeof sum); scanf( %d , &q); while (q--) { long long l, r; scanf( %d %lld %lld , &b, &l, &r); printf( %lld n , solve(r) - solve(l - 1)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n, x, res = 0; cin >> n; int t[n + 1]; fill(t, t + (n + 1), 0); for (int i = 1; i <= n; i++) { cin >> x; t[x] = t[x - 1] + 1; res = max(res, t[x]); } cout << n - res; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:51:06 09/06/2013
// Design Name:
// Module Name: time_parameters
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module time_parameters(clk, rst, reprogram, time_param_sel, new_time_value, interval, tiempo_espera);
input clk;
input rst;
input reprogram;
input [1:0] time_param_sel;
input [3:0] new_time_value;
input [1:0] interval;
output [3:0] tiempo_espera;
reg [3:0] t_base, t_ext, t_yel;
initial
begin
t_base <= 4'b0110;
t_ext <= 4'b0011;
t_yel <= 4'b0010;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
t_base <= 4'b0110;
t_ext <= 4'b0011;
t_yel <= 4'b0010;
end
else
if(reprogram)
begin
case(time_param_sel)
2'b00 : t_base <= new_time_value;
2'b01 : t_ext <= new_time_value;
2'b10 : t_yel <= new_time_value;
default : t_base <= 4'bxxxx;
endcase
end
end
//Se hace un muy con el interval
mux_tiempos selector_tiempo(t_base, t_ext, t_yel, interval, tiempo_espera);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__INV_BLACKBOX_V
`define SKY130_FD_SC_HD__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__INV_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int Max(int a, int b) { return a > b ? a : b; } int Min(int a, int b) { return a < b ? a : b; } char s[10][10]; int n, k; int a[10], mi, ma, ans; int flag[10]; void dfs(int t) { int i, j; if (t == k) { mi = ma = a[0]; for (i = 1; i < n; ++i) { mi = Min(mi, a[i]); ma = Max(ma, a[i]); } ans = Min(ans, ma - mi); return; } for (i = 0; i < k; ++i) { if (flag[i]) { flag[i] = 0; for (j = 0; j < n; ++j) { a[j] *= 10; a[j] += s[j][i] - 0 ; } dfs(t + 1); for (j = 0; j < n; ++j) { a[j] /= 10; } flag[i] = 1; } } } int main() { int i; scanf( %d%d , &n, &k); for (i = 0; i < n; ++i) scanf( %s , s[i]); ans = 1000000000; memset(flag, 1, sizeof(flag)); dfs(0); printf( %d n , ans); }
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; char c = getchar(); bool f = 0; for (; !isdigit(c); c = getchar()) f ^= c == - ; for (; isdigit(c); c = getchar()) x = x * 10 + (c ^ 48); x = f ? -x : x; } inline void readChar(char &c) { for (c = getchar(); c < A || c > E ; c = getchar()) ; } template <class T> inline void write(T x) { if (x < 0) { putchar( - ); x = -x; } T y = 1; int len = 1; for (; y <= x / 10; y *= 10) ++len; for (; len; --len, x %= y, y /= 10) putchar(x / y + 48); } const int MAXN = 1e3; int n, m, ans, a[MAXN + 5]; char s[MAXN + 5][MAXN + 5]; int main() { read(n), read(m); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) readChar(s[i][j]); for (int i = 1; i <= m; ++i) read(a[i]); for (int i = 1; i <= m; ++i) { int maxn = 0, tot[5] = {0}; for (int j = 1; j <= n; ++j) { ++tot[(int)s[j][i] - A ]; maxn = max(maxn, tot[(int)s[j][i] - A ]); } ans += maxn * a[i]; } write(ans); putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int A[200005]; vector<int> L[105]; int dp[400005]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &A[i]); L[A[i]].push_back(i); } int opt = 0; int D = 0; int N = min(n, 100); for (int i = 1; i <= N; i++) { if (L[i].size() > L[D].size()) D = i; } memset(dp, -1, sizeof(dp)); for (int V = 1; V <= N; V++) { if (V == D) continue; if (L[V].empty()) continue; int bal = 0; vector<int> T; T.push_back(bal); dp[bal + n] = 0; for (int i = 1; i <= n; i++) { if (A[i] == D) bal++; else if (A[i] == V) bal--; if (dp[bal + n] != -1) { if (i - dp[bal + n] > opt) opt = i - dp[bal + n]; } if (dp[bal + n] == -1) { dp[bal + n] = i; T.push_back(bal); } } for (int v : T) { dp[v + n] = -1; } } printf( %d n , opt); return 0; }
|
// Generated by FIR Compiler 9.0 [Altera, IP Toolbench 1.3.0 Build 132]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module lf (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [30:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; while (cin >> n) { vector<long long> vec; for (long long i = 2; i * i <= n; i++) { while (n % i == 0) { vec.push_back(i); n /= i; } } if (n > 1) { vec.push_back(n); } if (vec.size() < 2) { printf( 1 n0 n ); } else if (vec.size() == 2) { printf( 2 n ); } else { printf( 1 n%lld n , vec[0] * vec[1]); } } return 0; }
|
/**
* Reads the input and passes it to the game engine.
*
*/
module player(
CLOCK,
RESET,
A,
B,
POSITION
);
input CLOCK, RESET, A, B;
output [7:0] POSITION;
wire [3:0] speed;
wire direction;
wire count_enable;
// Read the rotary encoder.
quadrature_decoder quad_1(
CLOCK,
RESET,
A,
B,
count_enable,
direction,
speed
);
reg [15:0] total;
always @(posedge CLOCK or posedge RESET) begin
if (RESET) begin
total <= 0;
end
// Change the total only if a valid change has happened on the rotary encoder.
else if (count_enable) begin
// Max 200 (x4 for the clicks)
if (direction && total < 16'd800) begin
total <= total + 16'd1;
end
else if (total > 0) begin
total <= total - 16'd1;
end
end
end
wire [15:0] clicks;
assign clicks = (total >> 2) << 3; // divide by 4 as the encoder has 4 edges per "click", then multiply by 8 to move faster
reg [7:0] position;
always @(posedge CLOCK) begin
if (clicks > 8'd200) begin
position <= 8'd200;
end else begin
position <= clicks[7:0];
end
end
assign POSITION = position;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
input read,
input write,
input pawr,
input pard,
input refresh,
input cpuclk,
input romsel,
output reg [31:0] snes_sysclk_freq,
output reg [31:0] snes_read_freq,
output reg [31:0] snes_write_freq,
output reg [31:0] snes_pawr_freq,
output reg [31:0] snes_pard_freq,
output reg [31:0] snes_refresh_freq,
output reg [31:0] snes_cpuclk_freq,
output reg [31:0] snes_romsel_freq
);
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
reg [31:0] read_value;
reg [31:0] write_value;
reg [31:0] pard_value;
reg [31:0] pawr_value;
reg [31:0] refresh_value;
reg [31:0] cpuclk_value;
reg [31:0] romsel_value;
initial snes_sysclk_freq = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
initial read_value = 0;
initial write_value = 0;
initial pard_value = 0;
initial pawr_value = 0;
initial refresh_value = 0;
initial cpuclk_value = 0;
initial romsel_value = 0;
reg [1:0] sysclk_sreg;
reg [1:0] read_sreg;
reg [1:0] write_sreg;
reg [1:0] pard_sreg;
reg [1:0] pawr_sreg;
reg [1:0] refresh_sreg;
reg [1:0] cpuclk_sreg;
reg [1:0] romsel_sreg;
always @(posedge clk) romsel_sreg <= {romsel_sreg[0], romsel};
wire romsel_rising = (romsel_sreg == 2'b01);
always @(posedge clk) cpuclk_sreg <= {cpuclk_sreg[0], cpuclk};
wire cpuclk_rising = (cpuclk_sreg == 2'b01);
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) read_sreg <= {read_sreg[0], read};
wire read_rising = (read_sreg == 2'b01);
always @(posedge clk) write_sreg <= {write_sreg[0], write};
wire write_rising = (write_sreg == 2'b01);
always @(posedge clk) pard_sreg <= {pard_sreg[0], pard};
wire pard_rising = (pard_sreg == 2'b01);
always @(posedge clk) pawr_sreg <= {pawr_sreg[0], pawr};
wire pawr_rising = (pawr_sreg == 2'b01);
always @(posedge clk) refresh_sreg <= {refresh_sreg[0], refresh};
wire refresh_rising = (refresh_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 88000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
if(read_rising) read_value <= read_value + 1;
if(write_rising) write_value <= write_value + 1;
if(pard_rising) pard_value <= pard_value + 1;
if(pawr_rising) pawr_value <= pawr_value + 1;
if(refresh_rising) refresh_value <= refresh_value + 1;
if(cpuclk_rising) cpuclk_value <= cpuclk_value + 1;
if(romsel_rising) romsel_value <= romsel_value + 1;
end else begin
snes_sysclk_freq <= sysclk_value;
snes_read_freq <= read_value;
snes_write_freq <= write_value;
snes_pard_freq <= pard_value;
snes_pawr_freq <= pawr_value;
snes_refresh_freq <= refresh_value;
snes_cpuclk_freq <= cpuclk_value;
snes_romsel_freq <= romsel_value;
sysclk_counter <= 0;
sysclk_value <= 0;
read_value <= 0;
write_value <= 0;
pard_value <= 0;
pawr_value <= 0;
refresh_value <= 0;
cpuclk_value <= 0;
romsel_value <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long n, ar[500000], ps[500000], q, tp, a, b, bd[500000], sb[500000]; long res, fb; long gs(long v) { fb = v / 200; res = 0; for (int i = 0; i < fb; i++) res += sb[i]; for (int i = fb * 200; i <= v; i++) res += bd[i]; return res; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i]; ps[ar[i]] = i; } for (int i = 2; i <= n; i++) if (ps[i] < ps[i - 1]) { bd[i] = 1; sb[i / 200]++; } cin >> q; for (; q; --q) { cin >> tp; if (tp == 1) { cin >> a >> b; cout << gs(b) - gs(a) + 1 << endl; } else { cin >> a >> b; swap(ar[a], ar[b]); ps[ar[a]] = a; ps[ar[b]] = b; a = ar[a]; b = ar[b]; sb[a / 200] -= bd[a]; sb[b / 200] -= bd[b]; bd[a] = 0; bd[b] = 0; sb[(a + 1) / 200] -= bd[a + 1]; sb[(b + 1) / 200] -= bd[b + 1]; bd[a] = bd[b] = bd[a + 1] = bd[b + 1] = 0; if (a > 1 && ps[a] < ps[a - 1]) { bd[a] = 1; sb[a / 200]++; } if (a < n && ps[a] > ps[a + 1]) { bd[a + 1] = 1; sb[(a + 1) / 200]++; } if (b > 1 && ps[b] < ps[b - 1]) { sb[b / 200] += 1 - bd[b]; bd[b] = 1; } if (b < n && ps[b] > ps[b + 1]) { sb[(b + 1) / 200] += 1 - bd[b + 1]; bd[b + 1] = 1; } } } cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n; n += 1; int h[n]; for (int i = 1; i < n; i++) cin >> h[i]; h[0] = 0; int energy = 0; int max_energy = 0; for (int i = 0; i < (n); ++i) { if (i == 0) continue; energy += h[i - 1] - h[i]; max_energy = min(max_energy, energy); } cout << -max_energy << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int *arr = new int[2 * n + 1]; cin >> arr[0]; for (int i = 1; i < 2 * n + 1; i += 2) { cin >> arr[i] >> arr[i + 1]; if (k > 0 && arr[i] > arr[i - 1] + 1 && arr[i] > arr[i + 1] + 1) { k -= 1; arr[i] -= 1; } } for (int i = 0; i < 2 * n + 1; i++) cout << arr[i] << ; cout << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_TB_V
`define SKY130_FD_SC_LS__A21OI_TB_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ls__a21oi dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_TB_V
|
`include "./Definition.v"
//float Lmin = 0, L1x = 5, L2x = 10, L3x = 50;
//float Lmax = 100, L1y = 10, L2y = 17.5, L3y = 55;
//float a1 = ( L1y - Lmin ) / ( L1x - Lmin ), a2 = ( L2y - L1y ) / ( L2x - L1x ), a3 = ( L3y - L2y ) / ( L3x - L2x ), a4 = ( Lmax - L3y ) / ( Lmax - L3x);
//float b1 = ( L1y - ( L1x * a1)), b2 = ( L1y - ( L1x * a2 )), b3 = ( L3y - ( L3x * a3 )), b4 = ( L3y - ( L3x * a4 ));
`define Lmin 0
`define L1x 8127
`define L2x 16255
`define L3x 81275
`define Lmax 162550
`define L1y 16255
`define L2y 28446
`define L3y 89402
`define a1 512
`define a2 384
`define a3 240
`define a4 230
`define b1 0
`define b2 640
`define b3 2080
`define b4 2560
module ToneReproduction
(
input[ `size_int - 1 : 0 ]L,
input[ `size_int - 1 : 0 ]IN_R,
input[ `size_int - 1 : 0 ]IN_G,
input[ `size_int - 1 : 0 ]IN_B,
output reg[ `size_int - 1 : 0 ]OUT_R,
output reg[ `size_int - 1 : 0 ]OUT_G,
output reg[ `size_int - 1 : 0 ]OUT_B
);
always@( L )
begin
if( L <= `L1x )
begin
OUT_R = ( ( IN_R * `a1 ) + `b1 );
OUT_G = ( ( IN_G * `a1 ) + `b1 );
OUT_B = ( ( IN_B * `a1 ) + `b1 );
end
else if( `L1x < L && L <= `L2x)
begin
OUT_R = ( ( IN_R * `a2 ) + `b2 );
OUT_G = ( ( IN_G * `a2 ) + `b2 );
OUT_B = ( ( IN_B * `a2 ) + `b2 );
end
else if( `L2x < L && L <= `L3x)
begin
OUT_R = ( ( IN_R * `a3 ) + `b3 );
OUT_G = ( ( IN_G * `a3 ) + `b3 );
OUT_B = ( ( IN_B * `a3 ) + `b3 );
end
else
begin
OUT_R = ( ( IN_R * `a4 ) + `b4 );
OUT_G = ( ( IN_G * `a4 ) + `b4 );
OUT_B = ( ( IN_B * `a4 ) + `b4 );
end
end
endmodule
module ToneReproduction_testbench;
reg[ `size_int - 1 : 0 ]L;
reg[ `size_int - 1 : 0 ]IN_R;
reg[ `size_int - 1 : 0 ]IN_G;
reg[ `size_int - 1 : 0 ]IN_B;
wire[ `size_int - 1 : 0 ]OUT_R;
wire[ `size_int - 1 : 0 ]OUT_G;
wire[ `size_int - 1 : 0 ]OUT_B;
ToneReproduction ToneReproduction_test( L, IN_R, IN_G, IN_B, OUT_R, OUT_G, OUT_B );
initial
begin
//L = 58 * 256 * 6.3496042078727978990068225570775 = 94279
//IN_R = 128 * 256 = 32768
//IN_G = 90 * 256 = 23040
//IN_B = 78 * 256 = 19968
#10
begin
L = 65019;
IN_R = 32768;
IN_G = 23040;
IN_B = 19968;
end
#10 $display( "L = %d\tIN_R = %d\tIN_G = %d\tIN_B = %d", L, IN_R, IN_G, IN_B );
#10 $display( "OUT_R = %d\tOUT_G = %d\tOUT_B = %d",OUT_R, OUT_G, OUT_B );
#10 $stop;
#10 $finish;
end
endmodule
|
/********************************************/
/* generic_output.v */
/* A generic implementation of outputs */
/* (LEDs, ...) */
/* */
/* 2012, */
/********************************************/
module generic_output #(
parameter OW = 1, // output width
parameter DS = 1'b0, // default (off) state
parameter DBG = 0 // debug output
)(
output wire [ OW-1:0] i
);
////////////////////////////////////////
// logic //
////////////////////////////////////////
reg [ OW-1:0] state_old = {OW{DS}};
always @ (i) begin
if (i != state_old) begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, state_old, i);
state_old = #1 i;
end
end
////////////////////////////////////////
// tasks //
////////////////////////////////////////
//// read ////
task read;
output [ OW-1:0] data;
begin
data = state_old;
end
endtask
endmodule
|
#include <bits/stdc++.h> #define MP make_pair using namespace std; #define rep(i, n) for (int i = 0; i < (int)(n); ++ i) #define rep1(i, n) for (int i = 1; i <= (int)(n); ++ i) #define foreach(itr, c) for (__typeof((c).begin()) itr = (c).begin(); itr != (c).end(); ++ itr) typedef long long LL; typedef pair<int, int> pii; const int MAXN = 2e5 + 5; int N; string str[MAXN]; map<string, vector<string> > grps; LL ans; int solve_pair(const string& s1, const string& s2) { int prefix = 0, suffix = 0, n = s1.size(); while (s1[prefix] == s2[prefix]) prefix ++; while (s1[n - suffix - 1] == s2[n - suffix - 1]) suffix ++; return is_sorted(s1.begin() + prefix, s1.end() - suffix) || is_sorted(s2.begin() + prefix, s2.end() - suffix) ? 1ll : 2ll; } void solve(vector<string>& grp) { int n = grp.size(), len = grp[0].size(); ans -= 1ll * (n - 1) * n / 2 * 1337; if (n <= 200 * len) { rep(i, n) for (int j = i + 1; j < n; ++ j) { ans += solve_pair(grp[i], grp[j]); } } else { sort(grp.begin(), grp.end()); ans += 1ll * (n - 1) * n / 2 * 2; for (auto& s : grp) { rep(i, len) for (int j = i + 2; j <= len; ++ j) { string sorted = s; sort(sorted.begin() + i, sorted.begin() + j); ans -= (sorted[i] != s[i] && sorted[j - 1] != s[j - 1] && binary_search(grp.begin(), grp.end(), sorted)); } } } }; int main() { scanf( %d , &N); rep(i, N) { cin >> str[i]; string sorted = str[i]; sort(sorted.begin(), sorted.end()); grps[sorted].push_back(str[i]); } ans = 1ll * (N - 1) * N / 2 * 1337; for (auto& grp : grps) solve(grp.second); printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:128777216 ) using namespace std; const long long LINF = 1000000000000000000LL; const int INF = 1000000000; const long double eps = 1e-9; const long double PI = 3.1415926535897932384626433832795l; void prepare(string s) { if (s.length() != 0) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } } const int NMAX = 1000100; const int MOD = INF + 7; char s[NMAX]; int n; int c[4]; char sym[] = { A , C , G , T }; int get(char c) { for (int i = 0; i < (int)(4); i++) if (sym[i] == c) return i; assert(false); return -1; } void read() { scanf( %d n , &n); scanf( %s , s); } int bpow(int a, int n) { int r = 1; for (; n > 0; n >>= 1) { if (n & 1) r = ((long long)r * (long long)a) % MOD; a = ((long long)a * (long long)a) % MOD; } return r; } void solve() { memset(c, 0, sizeof(c)); for (int i = 0; i < (int)(n); i++) c[get(s[i])]++; int mx = *max_element(c, c + 4); int cnt = 0; for (int i = 0; i < (int)(4); i++) if (c[i] == mx) cnt++; printf( %d n , bpow(cnt, n)); } int main() { prepare( ); read(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; const int sz = 3; const double eps = 1e-9; const int maxn = 1e3 + 500, base = 1e9 + 7, maxm = 10; string second[maxn]; int main() { ios_base::sync_with_stdio(0); ; cin.tie(0); int n; cin >> n; if (n == 1) { cout << 6 << endl; return 0; } int k = inf; for (int i = 0; i < n; i++) cin >> second[i]; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { int eq = 0; for (int b = 0; b < 6; b++) if (second[i][b] == second[j][b]) eq++; if (eq == 0 || eq == 1) k = min(k, 2); if (eq == 3 || eq == 2) k = min(k, 1); if (eq >= 4) k = min(k, 0); } cout << k; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cin.get(); string s; deque<pair<string, bool>> storage; while (n--) { getline(cin, s); storage.push_back(pair<string, bool>(s, true)); } deque<pair<string, bool>>::iterator it1, it2; bool flag; for (it1 = storage.begin(); it1 < storage.end(); it1++) { if (it1->second == true) { cout << NO << endl; } else { cout << YES << endl; } for (it2 = it1 + 1; it2 < storage.end(); it2++) { if (it1->first == it2->first) { it2->second = false; } } } }
|
/*
* Titor - Barrel Processor - Task-dedicated register bank
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Register_Bank
`else
`define INC_Register_Bank
`timescale 1 ns / 100 ps
// Register module
module Register_Bank (
// memory interface
din,
dout,
address,
size,
enable,
read_write,
// register inputs
PC0_next,
PC1_next,
PC2_next,
MSR0_next,
MSR1_next,
MSR2_next,
HMULT_next,
result,
result_reg,
result_valid,
// register outputs
reg0,
reg1,
reg2,
reg3,
PC0,
PC1,
PC2,
MSR0,
MSR1,
MSR2,
HMULT,
// control
sel0,
sel1,
sel2,
sel3,
state,
clk,
reset
);
`include "definition/Definition.v"
parameter REGWSTATE_HMULT = 0; // state to write HMULT
parameter REGWSTATE_GEN = 0; // state to write any general registers
parameter REGWSTATE_SFR = 0; // state to write all SFRs
// memory interface
input [WORD-1:0] din;
input [WORD-1:0] address;
output reg [WORD-1:0] dout;
input enable;
input read_write;
input [LOGWORDBYTE-1:0] size;
// register inputs
input [WORD-1:0] PC0_next;
input [WORD-1:0] PC1_next;
input [WORD-1:0] PC2_next;
input [WORD-1:0] MSR0_next;
input [WORD-1:0] MSR1_next;
input [WORD-1:0] MSR2_next;
input [WORD-1:0] HMULT_next;
input [WORD-1:0] result;
input [WORD-1:0] result_reg;
input result_valid;
// register outputs
output reg [WORD-1:0] reg0;
output reg [WORD-1:0] reg1;
output reg [WORD-1:0] reg2;
output reg [WORD-1:0] reg3;
output reg [WORD-1:0] PC0;
output reg [WORD-1:0] PC1;
output reg [WORD-1:0] PC2;
output reg [WORD-1:0] MSR0;
output reg [WORD-1:0] MSR1;
output reg [WORD-1:0] MSR2;
output reg [WORD-1:0] HMULT;
// control
input [WIDTH_FIELD0-1:0] sel0;
input [WIDTH_FIELD1-1:0] sel1;
input [WIDTH_FIELD2-1:0] sel2;
input [WIDTH_SHAMT_R-1:0] sel3;
input [WORD-1:0] state;
input clk;
input reset;
wire [WORD-1:0] value [TOTAL_SPACE-1:0]; // register value outputs
reg active;
reg unpacked_sel_memory [REG_SPACE-1:0];
always @(*) begin
dout <= value[address];
reg0 <= value[sel0];
reg1 <= value[sel1];
reg2 <= value[sel2];
reg3 <= value[sel3];
PC0 <= value[SFR_PC0];
PC1 <= value[SFR_PC1];
PC2 <= value[SFR_PC2];
MSR0 <= value[SFR_MSR0];
MSR1 <= value[SFR_MSR1];
MSR2 <= value[SFR_MSR2];
HMULT <= value[REG_HMULT];
end
genvar i;
generate
for(i=0; i<REG_SPACE; i=i+1) begin : REGSEL
always @(*) begin
unpacked_sel_memory[i] <= ((address/WORDBYTE) == i) && (read_write == WRITE) && enable;
end
end
endgenerate
// register set ****************************************************************
// Zero register
Register X0(
.value (value[REG_Z] ),
.memory (0 ),
.datapath (0 ),
.sel_memory (0 ),
.sel_datapath (0 ),
.clk (clk ),
.reset (reset )
);
// Higher Multiplication register
Register X1(
.value (value[REG_HMULT] ),
.memory (din ),
.datapath (HMULT_next ),
.sel_memory (unpacked_sel_memory[REG_HMULT] ),
.sel_datapath ((state == REGWSTATE_HMULT) ),
.clk (clk ),
.reset (reset )
);
// "Real" general purpose registers
generate
for(i=GENERAL_OFFSET; i<GENERAL_SPACE; i=i+1) begin : REGGENERAL
Register X(
.value (value[i] ),
.memory (din ),
.datapath (result ),
.sel_memory (unpacked_sel_memory[i] ),
.sel_datapath ((state == REGWSTATE_GEN) && (result_reg == i) && result_valid ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
end
endgenerate
// PC*
Register X16(
.value (value[SFR_PC0] ),
.memory (din ),
.datapath (PC0_next ),
.sel_memory (unpacked_sel_memory[SFR_PC0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X17(
.value (value[SFR_PC1] ),
.memory (din ),
.datapath (PC1_next ),
.sel_memory (unpacked_sel_memory[SFR_PC1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X18(
.value (value[SFR_PC2] ),
.memory (din ),
.datapath (PC2_next ),
.sel_memory (unpacked_sel_memory[SFR_PC2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
// MSR*
Register X19(
.value (value[SFR_MSR0] ),
.memory (din ),
.datapath (MSR0_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR0] ),
.sel_datapath ((state == REGWSTATE_SFR) ), // REGWRITE_BROADSIDE
.clk (clk ),
.reset (reset )
);
Register X20(
.value (value[SFR_MSR1] ),
.memory (din ),
.datapath (MSR1_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR1] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
Register X21(
.value (value[SFR_MSR2] ),
.memory (din ),
.datapath (MSR2_next ),
.sel_memory (unpacked_sel_memory[SFR_MSR2] ),
.sel_datapath ((state == REGWSTATE_SFR) ),
.clk (clk ),
.reset (reset )
);
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_DC_NMLodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_DC_NMLodr
// File Name: d_KES_PE_DC_NMLodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Discrepancy Computation module, normal order
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_DC_NMLodr // discrepancy computation module: normal order
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_DC,
input wire [`D_KES_GF_ORDER-1:0] i_S_in,
input wire [`D_KES_GF_ORDER-1:0] i_v_2i_X,
output wire [`D_KES_GF_ORDER-1:0] o_S_out,
output wire [`D_KES_GF_ORDER-1:0] o_coef_2ip1
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_DC_RST = 2'b01; // reset
parameter PE_DC_INP = 2'b10; // input capture
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
reg [`D_KES_GF_ORDER-1:0] r_S_in_b;
reg [`D_KES_GF_ORDER-1:0] r_v_2i_X_b;
wire [`D_KES_GF_ORDER-1:0] w_coef_term;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_DC_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_DC_RST: begin
r_nxt_state <= (i_EXECUTE_PE_DC)? (PE_DC_INP):(PE_DC_RST);
end
PE_DC_INP: begin
r_nxt_state <= PE_DC_RST;
end
default: begin
r_nxt_state <= PE_DC_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
r_S_in_b <= 0;
r_v_2i_X_b <= 0;
end
else begin
case (r_nxt_state)
PE_DC_RST: begin // hold original data
r_S_in_b <= r_S_in_b;
r_v_2i_X_b <= r_v_2i_X_b;
end
PE_DC_INP: begin // input capture only
r_S_in_b <= i_S_in;
r_v_2i_X_b <= i_v_2i_X;
end
default: begin
r_S_in_b <= r_S_in_b;
r_v_2i_X_b <= r_v_2i_X_b;
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_S_in_FFM_v_2i_X (
.i_poly_form_A (r_S_in_b[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (r_v_2i_X_b[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_coef_term[`D_KES_GF_ORDER-1:0]));
assign o_S_out[`D_KES_GF_ORDER-1:0] = r_S_in_b[`D_KES_GF_ORDER-1:0];
assign o_coef_2ip1 = w_coef_term;
endmodule
|
#include <bits/stdc++.h> const int MAX_MEM = 1e8; int mpos = 0; char mem[MAX_MEM]; inline void *operator new(size_t n) { assert((mpos += n) <= MAX_MEM); return (void *)(mem + mpos - n); } inline void operator delete(void *) noexcept {} using namespace std; struct Ex { int s, d, c, i; }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<Ex> data(m + 1); unordered_map<int, int> table(m + 1); for (int i = 1; i <= m; i++) { int s, d, c; cin >> s >> d >> c; data[i] = {s, d, c, i}; table[d] = i; } vector<int> answer(n + 1); vector<int> cnt(m + 1); for (int i = 1; i <= n; i++) { if (table[i]) { if (cnt[table[i]] == data[table[i]].c) { answer[i] = m + 1; } else { cout << -1; return 0; } } else { int best_ex = -1; int day = 1000; for (int j = 1; j <= m; j++) { if (data[j].d < day and cnt[data[j].i] < data[j].c and data[j].s <= i) { best_ex = data[j].i; day = data[j].d; } } if (best_ex == -1) { answer[i] = 0; } else { answer[i] = best_ex; cnt[best_ex]++; } } } for (int i = 1; i <= n; i++) { cout << answer[i] << ; } }
|
#include <bits/stdc++.h> using namespace std; int dp[500005][28]; int ar[500005]; int p[500005][28]; int ans[500005]; string st; int main() { int a, b, c, d, e, x, y, z, k, n; cin >> n >> k; cin >> st; for (a = 0; a < n; a++) ar[a + 1] = st[a] - A ; for (a = 1; a <= n; a++) { for (b = 0; b < k; b++) { dp[a][b] = 500005; } } for (a = 1; a <= n; a++) { for (b = 0; b < k; b++) { if (ar[a] == b) c = 0; else c = 1; for (d = 0; d < k; d++) { if (b == d) continue; if (dp[a][b] > dp[a - 1][d] + c) { dp[a][b] = min(dp[a][b], dp[a - 1][d] + c); p[a][b] = d; } } } } x = 500005; for (a = 0; a < k; a++) if (x > dp[n][a]) { x = dp[n][a]; b = a; } cout << x << endl; a = n; while (a >= 1) { ans[a] = b; b = p[a][b]; a--; } for (a = 1; a <= n; a++) printf( %c , ans[a] + A ); printf( n ); return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file decryption_mem.v when simulating
// the core, decryption_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module decryption_mem(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [14 : 0] addra;
input [7 : 0] dina;
input clkb;
input rstb;
input [14 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(15),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(1),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("decryption_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(32768),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("SR"),
.C_RST_TYPE("ASYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(32768),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 14:40:47 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_stub.v
// Design : zqynq_lab_1_design_auto_pc_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// ledtest_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3 // .hps_io_emac1_inst_RXD3
);
ledtest_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3) // .hps_io_emac1_inst_RXD3
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int main() { int n, m, t; cin >> n >> m >> t; int total = (n - 2) * (n - 1) / 2 + 1; if (total >= m && m >= n - 1) { m = m - n + 1; int cant = 0; if (t != 1) cant = 1; else cant = n; printf( %d %d n , t, cant); for (int i = 1; i < n; i++) { if (i != cant && i + 1 != cant) printf( %d %d n , i, i + 1); } for (int i = 1; i <= n && m; i++) { if (t - i == 1 || i - t == 1 || t == i || i == cant) continue; printf( %d %d n , i, t); m--; } for (int i = 1; i <= n && m; i++) { if (i == t || i == cant) continue; for (int j = i + 2; j <= n && m; j++) { if (j == t || j == cant) continue; printf( %d %d n , i, j); m--; } } } else puts( -1 ); return 0; }
|
#include <bits/stdc++.h> using namespace std; struct Grass { int sizee; char dir; } a[100005]; int n; bool flag[100005]; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i].dir; } for (int i = 1; i <= n; i++) { cin >> a[i].sizee; } int nowx = 1; flag[nowx] = 1; while (true) { if (a[nowx].dir == > ) { nowx += a[nowx].sizee; } else { nowx -= a[nowx].sizee; } if (nowx > n || nowx < 1) { cout << FINITE ; break; } if (flag[nowx] == 1) { cout << INFINITE ; break; } flag[nowx] = 1; } return 0; }
|
module reg_64page_1024x32b_3r_1w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_en_xoutof4,
wr0_data, clk, clk_double
);
output [8191:0] rd0_data;
output [2047:0] rd1_data;
output [2047:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1_addr;
input [9:0] rd2_addr;
input [9:0] wr0_addr;
input [63:0] wr0_en;
input [3:0] wr0_en_xoutof4;
input [8191:0] wr0_data;
input clk;
input clk_double;
//wire [255:0] effective_wr0_en;
reg [63:0] block_we;
reg [31:0] block_addr_a;
reg [31:0] block_addr_b;
wire [31:0] block_addr_c;
assign block_addr_c = {rd2_addr, 2'd0};
always @ (*) begin
if(clk) begin
block_we <= 64'd0;
block_addr_a <= {rd0_addr, 2'd0};
block_addr_b <= {rd1_addr, 2'd0};
end
else begin
block_we <= wr0_en;
block_addr_a <= {wr0_addr, 2'd0};
end
end
genvar index;
generate
for(index = 0; index < 64; index = index + 1) begin : block_ram_banks
block_ram bank0
(
.clka(clk_double), // input clka
//.rsta(rst), // input rsta
.wea({4{block_we[index]}}), // input [3 : 0] wea
.addra(block_addr_a), // input [31 : 0] addra
.dina(wr0_data[(31 + (index * 128)):(index * 128)]), // input [31 : 0] dina
.douta(rd0_data[31 + (index * 128):index * 128]), // output [31 : 0] douta
.clkb(clk_double), // input clkb
//.rstb(rst), // input rstb
.web(4'd0), // input [3 : 0] web
.addrb(block_addr_b), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(rd1_data[31 + (index * 32):index * 32]) // output [31 : 0] doutb
);
block_ram bank1
(
.clka(clk_double), // input clka
//.rsta(rst), // input rsta
.wea(4'd0), // input [3 : 0] wea
.addra(block_addr_c), // input [31 : 0] addra
.dina(32'd0), // input [31 : 0] dina
.douta(rd2_data[31 + (index * 32):index * 32]), // output [31 : 0] douta
.clkb(clk_double), // input clkb
//.rstb(rst), // input rstb
.web({4{block_we[index]}}), // input [3 : 0] web
.addrb(block_addr_a), // input [31 : 0] addrb
.dinb(wr0_data[(31 + (index * 128)):(index * 128)]), // input [31 : 0] dinb
.doutb() // output [31 : 0] doutb
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_2_V
`define SKY130_FD_SC_HDLL__XOR3_2_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_2_V
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