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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A222O_FUNCTIONAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire B2 and2_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X , and1_out, and0_out, and2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; long long mas[200004]; long long mas2[200004]; struct ver { long long abs; int number; long long maxabs; int masnumber; ver *l; ver *r; }; void build(ver *v, int l, int r, long long *m) { if (l == r) { v->abs = m[l]; v->number = l; v->masnumber = l; v->maxabs = m[l]; } else { ver *a = new ver; ver *b = new ver; v->l = a; v->r = b; build(a, l, (l + r) / 2, m); build(b, (l + r) / 2 + 1, r, m); if (a->maxabs < b->maxabs) { v->maxabs = b->maxabs; v->masnumber = b->masnumber; } else { v->maxabs = a->maxabs; v->masnumber = a->masnumber; } } } pair<long long, long long> maxver(ver *v, int l, int r, int zl, int zr) { pair<long long, long long> answer; answer.first = -100000; answer.second = 0; if (l > zr || r < zl) return answer; else { if (zl <= l && r <= zr) { answer.first = v->maxabs; answer.second = v->masnumber; return answer; } else { pair<long long, long long> left; pair<long long, long long> right; left = maxver(v->l, l, (l + r) / 2, zl, zr); right = maxver(v->r, (l + r) / 2 + 1, r, zl, zr); if (left.first < right.first) return right; else return left; } } } int main() { ver *root = new ver; int n, k; pair<long long, long long> answer; long long maxans = 0; answer.first = 0; answer.second = 0; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> mas[i]; for (int i = 0; i < 200004; i++) mas2[i] = 0; for (int i = n - k + 1; i <= n; i++) mas2[n - k + 1] += mas[i]; for (int i = n - k; i >= 1; i--) mas2[i] = mas2[i + 1] + mas[i] - mas[i + k]; build(root, 1, n, mas2); for (int i = 1; i <= n - 2 * k + 1; i++) { pair<long long, long long> an = maxver(root, 1, n, i + k, n); if (an.first + mas2[i] > maxans) { maxans = an.first + mas2[i]; answer.first = i; answer.second = an.second; } } cout << answer.first << << answer.second; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s18 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s18.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s18_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s18 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S18_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, T, low, mid, high, a[200005], t[200005]; vector<int> ans; scanf( %d%d , &n, &T); for (int i = 1; i <= n; i++) { scanf( %d%d , &a[i], &t[i]); } low = 0; high = n; while (low <= high) { mid = (low + high) / 2; vector<pair<int, int> > v; int cnt = 0, tot_t = 0, idx = -1; for (int i = 1; i <= n; i++) { if (a[i] >= mid) v.push_back(make_pair(t[i], i)); } sort(v.begin(), v.end()); for (int i = 0; i < v.size(); i++) { if (tot_t + v[i].first > T) break; cnt++; tot_t += v[i].first; if (cnt == mid) { idx = i; break; } } if (cnt >= mid) { ans.clear(); for (int i = 0; i <= idx; i++) ans.push_back(v[i].second); low = mid + 1; } else { high = mid - 1; } } printf( %d n%d n , ans.size(), ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d , ans[i]); printf( n ); return 0; }
|
#include <bits/stdc++.h> const int dx[] = {1, -1, 0, 0}; const int dy[] = {0, 0, -1, 1}; using namespace std; long long tests; long long n, m, b, MOD, dp[5256][5256], a[5256], ans; void solve() { scanf( %I64d%I64d%I64d%I64d , &n, &m, &b, &MOD); for (int i = 1; i <= n; i += 1) { scanf( %I64d , &a[i]); } dp[0][0] = 1; for (int i = 1; i <= n; i += 1) for (int j = 0; j <= m; j += 1) for (int k = 0; k <= b; k += 1) if (k + a[i] <= b) { dp[j + 1][k + a[i]] += dp[j][k]; dp[j + 1][k + a[i]] %= MOD; } for (int i = 0; i <= b; i += 1) { ans += dp[m][i]; ans %= MOD; } printf( %I64d , ans); } int main() { solve(); }
|
// DESCRIPTION: Verilator: Test of gated clock detection
//
// The code as shown generates a result by a delayed assignment from PC. The
// creation of the result is from a clock gated from the clock that sets
// PC. Howevever since they are essentially the same clock, the result should
// be delayed by one cycle.
//
// Standard Verilator treats them as different clocks, so the result stays in
// step with the PC. An event drive simulator always allows the clock to win.
//
// The problem is caused by the extra loop added by Verilator to the
// evaluation of all internally generated clocks (effectively removed by
// marking the clock enable).
//
// This test is added to facilitate experiments with solutions.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett <>.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg gated_clk_en = 1'b0 ;
reg [1:0] pc = 2'b0;
reg [1:0] res = 2'b0;
wire gated_clk = gated_clk_en & clk;
always @(posedge clk) begin
pc <= pc + 1;
gated_clk_en <= 1'b1;
end
always @(posedge gated_clk) begin
res <= pc;
end
always @(posedge clk) begin
if (pc == 2'b11) begin
// Correct behaviour is that res should be lagging pc in the count
// by one cycle
if (res == 2'b10) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; char c[109][109]; bool ja = 1; bool useless = 1; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> c[i][j]; if (c[i][j] == . ) { if (i % 2 == 0 && j % 2 == 0 || i % 2 == 1 && j % 2 == 1) { c[i][j] = B ; } else { c[i][j] = W ; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << c[i][j]; } cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2; cin >> s1; s2 = hello ; int i = 0, j = 0, count = 0; int l = s1.length(); while (l) { if (s1[i] != s2[j]) i++; if (s1[i] == s2[j]) { i++; j++; count++; } l--; } if (count > 4) cout << YES ; else cout << NO ; }
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v1_9_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1000 * 1000 + 5; bool mark[4][maxN]; int n, m, comp; inline void dfs(int x, int y) { if (mark[x][y]) return; mark[x][y] = true; if (x == 0 && y == 1) mark[3][1] = true; if (x == 0 && y == m) mark[1][1] = true; if (x == 1 && y == 1) mark[0][m] = true; if (x == 1 && y == n) mark[2][m] = true; if (x == 2 && y == 1) mark[3][n] = true; if (x == 2 && y == m) mark[1][n] = true; if (x == 3 && y == m) mark[2][1] = true; if (x == 3 && y == 1) mark[0][1] = true; if (x == 0) { int dr = m - y; int dl = y - 1; int dd = n - 1; int xr = 1 + min(dr, dd), yr = y + min(dr, dd); int xl = 1 + min(dl, dd), yl = y - min(dl, dd); (xr == n) ? dfs(2, yr) : dfs(1, xr); (xl == n) ? dfs(2, yl) : dfs(3, xl); } if (x == 2) { int dr = m - y; int dl = y - 1; int du = n - 1; int xr = n - min(dr, du), yr = y + min(dr, du); int xl = n - min(dl, du), yl = y - min(dl, du); (xr == 1) ? dfs(0, yr) : dfs(1, xr); (xl == 1) ? dfs(0, yl) : dfs(3, xl); } if (x == 1) { int dd = n - y; int du = y - 1; int dl = m - 1; int xu = y - min(du, dl), yu = m - min(du, dl); int xd = y + min(dd, dl), yd = m - min(dd, dl); (yu == 1) ? dfs(3, xu) : dfs(0, yu); (yd == 1) ? dfs(3, xd) : dfs(2, yd); } if (x == 3) { int dd = n - y; int du = y - 1; int dr = m - 1; int xu = y - min(du, dr), yu = 1 + min(du, dr); int xd = y + min(dd, dr), yd = 1 + min(dd, dr); (yu == m) ? dfs(1, xu) : dfs(0, yu); (yd == m) ? dfs(1, xd) : dfs(2, yd); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { if (!mark[0][i]) { comp++; dfs(0, i); } if (!mark[2][i]) { comp++; dfs(2, i); } } for (int i = 1; i <= n; i++) { if (!mark[1][i]) { comp++; dfs(1, i); } if (!mark[3][i]) { comp++; dfs(3, i); } } printf( %d n , comp); return 0; }
|
`include "defines.v"
`include "HRnode.v"
`timescale 1ns/1ps
/*module HRnode
#(parameter addr = 4'b0010)
(
input `control_w port0_i,
input `control_w port1_i,
input `control_w port0_local_i,
input `control_w port1_local_i,
output portl0_ack,
output portl1_ack,
input clk,
input rst,
output `control_w port0_o,
output `control_w port1_o,
output `control_w port0_local_o,
output `control_w port1_local_o
);*/
module tb(
);
wire ack0, ack1;
reg clk, rst;
reg `control_w flit0c, flit1c, flitl0, flitl1;
wire `control_w port0_co, port1_co, portl0_co, portl1_co;
HRnode r(
.clk(clk),
.rst(rst),
.port0_i(flit0c), .port0_o(port0_co),
.port1_i(flit1c), .port1_o(port1_co),
.port0_local_i(flitl0), .port0_local_o(portl0_co),
.port1_local_i(flitl1), .port1_local_o(portl1_co),
.portl0_ack(ack0), .portl1_ack(ack1)
);
initial begin
//$set_toggle_region(tb.r);
//$toggle_start();
clk = 0;
rst = 0;
flit0c = 144'h0123456789abcdef0123456789abcdef1852;
flit1c = 144'h0;
flitl0 = 144'h0123456789abcdef0123456789abcdef1855;
flitl1 = 144'h0;
#1;
clk = 1;
#1;
clk = 0;
$display("clk = %d\n, port0 %04x\n, port1 %04x\n, portl0_co %04x\n, portl1_co %04x\n, portl0_ack %04x\n, portl1_ack %04x\n",
clk, port0_co, port1_co, portl0_co, portl1_co, ack0, ack1);
//$toggle_stop();
//$toggle_report("./calf_backward_1.saif", 1.0e-9, "tb.r");
//$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, A, B; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; while (n--) { cin >> A >> B; cout << A * (long long)log10(B + 1) << endl; } }
|
#include <bits/stdc++.h> using namespace std; int dp[5000][5000]; int main() { char a[5000], b[5000]; int ti, td, tr, te; scanf( %d %d %d %d , &ti, &td, &tr, &te); scanf( %s %s , a, b); int n = strlen(a); int m = strlen(b); dp[0][0] = 0; for (int i = 1; i <= n; i++) dp[i][0] = dp[i - 1][0] + td; for (int i = 1; i <= m; i++) dp[0][i] = dp[0][i - 1] + ti; int da[26]; int db; memset(da, 0, sizeof(da)); int ii, jj, d; for (int i = 1; i <= n; i++) { db = 0; for (int j = 1; j <= m; j++) { d = (a[i - 1] == b[j - 1]) ? 0 : tr; ii = da[b[j - 1] - a ]; jj = db; db = (a[i - 1] == b[j - 1]) ? j : db; dp[i][j] = min(dp[i][j - 1] + ti, min(dp[i - 1][j] + td, dp[i - 1][j - 1] + d)); if (ii > 0 && jj > 0) dp[i][j] = min(dp[i][j], dp[ii - 1][jj - 1] + (i - ii - 1) * td + (j - jj - 1) * ti + te); } da[a[i - 1] - a ] = i; } printf( %d n , dp[n][m]); }
|
// part of NeoGS flash programmer project (c) 2014 lvd^NedoPC
//
// reset controller
module reset
(
input wire clk_fpga,
input wire clk_24mhz,
input wire init,
output reg init_in_progress,
output wire zxbus_rst_n,
output reg rom_rst_n,
output reg z80_rst_n,
output reg z80_busrq_n,
input wire z80_busak_n
);
parameter RST_CNT_SIZE = 8;
reg [RST_CNT_SIZE:0] poweron_rst_cnt;
reg [RST_CNT_SIZE:0] rz_rst_cnt;
wire poweron_rst_n = poweron_rst_cnt[RST_CNT_SIZE];
wire rz_rst_n = rz_rst_cnt[RST_CNT_SIZE];
reg z80_rst2;
reg [1:0] z80_halted;
// make overall reset from poweron
//
initial
poweron_rst_cnt <= 'd0;
//
always @(posedge clk_24mhz)
if( !poweron_rst_n )
poweron_rst_cnt <= poweron_rst_cnt + 'd1;
// make zxbus reset
assign zxbus_rst_n = poweron_rst_n;
// make rom/z80 reset
//
always @(posedge clk_24mhz, negedge poweron_rst_n)
if( !poweron_rst_n )
rz_rst_cnt <= 'd0;
else if( init )
rz_rst_cnt <= 'd0;
else if( !rz_rst_n )
rz_rst_cnt <= rz_rst_cnt + 'd1;
// z80 reset
always @(posedge clk_fpga, negedge rz_rst_n)
if( !rz_rst_n )
begin
z80_rst_n <= 1'b0;
z80_rst2 <= 1'b0;
end
else
begin
z80_rst_n <= z80_rst2;
z80_rst2 <= 1'b1;
end
// z80 busrq/busak
always @(posedge clk_fpga, negedge z80_rst_n)
if( !z80_rst_n )
z80_busrq_n <= 1'b1;
else
z80_busrq_n <= 1'b0;
//
always @(posedge clk_24mhz, negedge rz_rst_n)
if( !rz_rst_n )
z80_halted <= 2'b00;
else
z80_halted[1:0] <= {z80_halted[0], ~z80_busak_n};
// rom reset, init_in_progress
always @(posedge clk_24mhz, negedge rz_rst_n)
if( !rz_rst_n )
begin
rom_rst_n <= 1'b0;
init_in_progress <= 1'b1;
end
else if( z80_halted[1] )
begin
rom_rst_n <= 1'b1;
init_in_progress <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int M = 1e9 + 7; int sum_digit(int x) { int sum = 0; while (x > 0) { sum += x % 10; x /= 10; } return sum; } int reverse_num(int n) { int tmp = n, ans = 0, r; while (tmp > 0) { r = tmp % 10; ans = ans * 10 + r; tmp /= 10; } return ans; } long long int factorial(long long int n) { long long int i, ans = 1; for (i = n; i > 1; i--) { ans *= i; } return ans; } long long int gcd(long long int num1, long long int num2) { long long int a, b, r; a = num1; b = num2; r = a % b; while (r > 0) { a = b; b = r; r = a % b; } return b; } long long int lcm(long long int num1, long long int num2) { return (num1 * num2) / gcd(num1, num2); } bool prime(long long int n) { if (n < 2) return false; for (long long int i = 2; i <= sqrt(n); i++) { if (n % i == 0) return false; } return true; } bool vowel(char ch) { ch = tolower(ch); if (ch == a || ch == e || ch == i || ch == o || ch == u ) return true; return false; } void solve() { double d, h, v, e; cin >> d >> h >> v >> e; double r = d / 2; double v_in = 2 * acos(0) * r * r * h; double L = 0, R = 1e4 + 10; double ans = 0; while (L < R) { double t = L + (R - L) / 2; double dif = (v_in + 2 * acos(0) * r * r * e * t) - v * t; if (abs(dif) < 1e-4) { ans = t; break; } if (dif < 0) R = t; else L = t; } if (ans != 0) { cout << YES n ; cout << setprecision(12) << fixed << ans << endl; } else cout << NO n ; } int main() { solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[2][1 << 16]; char art[7][1008]; int n; int c[5]; vector<int> modi[1008]; void upd(int &x, int y) { x = min(x, y); } int main() { scanf( %d , &n); for (int i = 1; i <= 4; i++) scanf( %d , &c[i]); for (int i = 1; i <= 4; i++) scanf( %s , art[i] + 1); int now = 0; memset(dp[now], 0x3f, sizeof dp[now]); dp[now][0] = 0; for (int i = 1; i <= 4; i++) { for (int j = 1; j <= 4 - i + 1; j++) { int mas = (1 << 16) - 1; for (int x = 0; x < i; x++) for (int y = j - 1; y < j - 1 + i; y++) { mas ^= (1 << (x * 4 + y)); } modi[i].push_back(mas); } } for (int i = 1; i <= n + 4; i++) { now ^= 1; memset(dp[now], 0x3f, sizeof dp[now]); int nm = 0; for (int j = 1; j <= 4; j++) if (art[j][i] == * ) nm |= (1 << 11 + j); for (int j = (1 << 16) - 1; j >= 0; j--) if (dp[now ^ 1][j] < 1e9) { for (int k = 1; k <= 4; k++) for (int l = 0; l < modi[k].size(); l++) upd(dp[now ^ 1][j & modi[k][l]], dp[now ^ 1][j] + c[k]); if (j & 15) continue; upd(dp[now][(j >> 4) | nm], dp[now ^ 1][j]); } } printf( %d n , dp[now][0]); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:51:39 11/23/2009
// Design Name:
// Module Name: tetris_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module grid_tb;
reg clk;
reg[4:0] row;
reg[3:0] col;
reg[2:0] type;
reg[1:0] rot;
reg en, start;
wire ready;
reg[2:0] count;
wire[2:0] n_lines;
grid mem(clk, row, col, type, rot, en, n_lines, start, ready);
initial begin
start <= 1;
type <= 5;
rot <= 0;
clk <= 1;
row <= 18;
end
always @(posedge clk) begin
if(count == 4)
count <= 0;
else
count <= count +1;
if(start == 1) begin
start <= 0;
count <= 4;
col <= 0;
end
end
always @(posedge clk) begin
if(count == 3)
col <= col + 2;
if(count == 4)
en <= 1;
else
en <= 0;
end
always begin
#5 clk = !clk;
end
endmodule
module jizlots_tb;
reg clk;
reg[2:0] type;
reg[1:0] rot;
wire[0:15] block_out;
JIZLOTS_sel write(type, rot, block_out);
initial begin
clk <= 0;
type <= 0;
rot <= 0;
end
always begin
#5 clk = !clk;
end
endmodule
module check_move_tb;
reg clk;
wire[4:0] row;
wire[3:0] col;
reg[2:0] type;
wire[1:0] rot_out;
reg start, left, right, down, rot, rst;
wire done, ok, hit;
reg[0:13] d;
wire[4:0] addr_row;
wire[0:15] fake[0:19];
assign fake[0] = 14'b00000000000000;
assign fake[1] = 14'b00000000000000;
assign fake[2] = 14'b00000000000000;
assign fake[3] = 14'b00000000000000;
assign fake[4] = 14'b00000000000000;
assign fake[5] = 14'b00000000000000;
assign fake[6] = 14'b00000000000000;
assign fake[7] = 14'b00000000000000;
assign fake[8] = 14'b00000000000000;
assign fake[9] = 14'b00000000000000;
assign fake[10] = 14'b00000000000000;
assign fake[11] = 14'b00000000000000;
assign fake[12] = 14'b00000000000000;
assign fake[13] = 14'b00000000000000;
assign fake[14] = 14'b00000000000000;
assign fake[15] = 14'b00000000000000;
assign fake[16] = 14'b00000000000000;
assign fake[17] = 14'b00000000000000;
assign fake[18] = 14'b00000000000000;
assign fake[19] = 14'b11111111111111;
check_move chk1(clk, d, addr_row, rst, left, right, down, rot, type, row, col, rot_out, ok, hit, done);
initial begin
rst = 1;
left <= 0;
right <= 0;
down <= 1;
rot <= 1;
type <= 5;
clk = 1;
#10 rst <= 0;
end
always @(posedge clk)
begin
d <= fake[addr_row];
end
always begin
#5 clk = !clk;
end
endmodule
module sync_gen_tb;
reg clk;
reg rst;
wire h_sync, v_sync, gfx_clk;
wire[9:0] x,y;
wire[3:0] r,g,b;
wire[4:0] addr_row;
reg[0:13] d;
wire[0:13] fake[0:3];
assign fake[0] = 14'b00001100010001;
assign fake[1] = 14'b00011100010011;
assign fake[2] = 14'b11110000010001;
assign fake[3] = 14'b11000000011001;
sync_gen sg(clk, h_sync, v_sync, gfx_clk, x, y, rst);
colour_gen cg(gfx_clk, x, y, d, addr_row, r, g, b, rst);
initial begin
rst = 1;
clk <= 1;
#10 rst <= 0;
end
always @(posedge clk)
begin
d <= fake[addr_row];
end
always begin
#5 clk = !clk;
end
endmodule
module tetris_tb;
reg clk = 1;
reg start = 1;
reg left, right, rot;
wire h_sync, v_sync;
wire[9:0] r,g,b;
reg drop;
tetris tet(clk, start, left, right, rot, drop, h_sync, v_sync, r, g, b);
initial begin
#10 start <= 0;
left <= 0;
right <= 0;
rot <= 0;
#120 rot <= 1;
drop <= 1;
end
always begin
#5 clk = !clk;
end
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ll8_to_fifo36
(input clk, input reset, input clear,
input [7:0] ll_data,
input ll_sof_n,
input ll_eof_n,
input ll_src_rdy_n,
output ll_dst_rdy_n,
output [35:0] f36_data,
output f36_src_rdy_o,
input f36_dst_rdy_i );
wire f36_write = f36_src_rdy_o & f36_dst_rdy_i;
// Why anybody would use active low in an FPGA is beyond me...
wire ll_sof = ~ll_sof_n;
wire ll_eof = ~ll_eof_n;
wire ll_src_rdy = ~ll_src_rdy_n;
wire ll_dst_rdy;
assign ll_dst_rdy_n = ~ll_dst_rdy;
reg f36_sof, f36_eof;
reg [1:0] f36_occ;
reg [2:0] state;
reg [7:0] dat0, dat1, dat2, dat3;
always @(posedge clk)
if(ll_src_rdy & ((state==0)|f36_write))
f36_sof <= ll_sof;
always @(posedge clk)
if(ll_src_rdy & ((state !=4)|f36_write))
f36_eof <= ll_eof;
always @(posedge clk)
if(ll_eof)
f36_occ <= state[1:0] + 1;
else
f36_occ <= 0;
always @(posedge clk)
if(reset)
state <= 0;
else
if(ll_src_rdy)
case(state)
0 :
if(ll_eof)
state <= 4;
else
state <= 1;
1 :
if(ll_eof)
state <= 4;
else
state <= 2;
2 :
if(ll_eof)
state <= 4;
else
state <= 3;
3 : state <= 4;
4 :
if(f36_dst_rdy_i)
if(ll_eof)
state <= 4;
else
state <= 1;
endcase // case(state)
else
if(f36_write)
state <= 0;
always @(posedge clk)
if(ll_src_rdy & (state==3))
dat3 <= ll_data;
always @(posedge clk)
if(ll_src_rdy & (state==2))
dat2 <= ll_data;
always @(posedge clk)
if(ll_src_rdy & (state==1))
dat1 <= ll_data;
always @(posedge clk)
if(ll_src_rdy & ((state==0) | f36_write))
dat0 <= ll_data;
assign ll_dst_rdy = f36_dst_rdy_i | (state != 4);
assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3}; // FIXME endianess
assign f36_src_rdy_o = (state == 4);
endmodule // ll8_to_fifo36
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const long long MAXN = 100005; long long n, m, o, a[MAXN], b[MAXN], f[2][205][5005]; int main() { n = read(); m = read(); memset(a, 0, sizeof(a)); memset(b, 0, sizeof(b)); for (long long i = (1); i <= (n); ++i) { long long x = read(); while (x % 2 == 0) a[i]++, x /= 2; while (x % 5 == 0) b[i]++, x /= 5; } memset(f, 0, sizeof(f)); f[0][0][0] = 1; o = 0; for (long long i = (1); i <= (n); ++i) { o = 1 - o; memset(f[o], 0, sizeof(f[o])); for (long long j = (0); j <= (i); ++j) for (long long k = (0); k <= (j * 25); ++k) { f[o][j][k] = max(f[o][j][k], f[1 - o][j][k]); if (k >= b[i] && j > 0 && f[1 - o][j - 1][k - b[i]] > 0) f[o][j][k] = max(f[o][j][k], f[1 - o][j - 1][k - b[i]] + a[i]); } } long long ans = 0; for (long long i = (0); i <= (m * 25); ++i) ans = max(ans, min(f[o][m][i] - 1, i)); cout << ans << endl; return 0; }
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_sync_cell.v
//
// *Module Description:
// Generic synchronizer for the openMSP430
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_sync_cell (
// OUTPUTs
data_out, // Synchronized data output
// INPUTs
clk, // Receiving clock
data_in, // Asynchronous data input
rst // Receiving reset (active high)
);
// OUTPUTs
//=========
output data_out; // Synchronized data output
// INPUTs
//=========
input clk; // Receiving clock
input data_in; // Asynchronous data input
input rst; // Receiving reset (active high)
//=============================================================================
// 1) SYNCHRONIZER
//=============================================================================
reg [1:0] data_sync;
always @(posedge clk or posedge rst)
if (rst) data_sync <= 2'b00;
else data_sync <= {data_sync[0], data_in};
assign data_out = data_sync[1];
endmodule // omsp_sync_cell
|
/*****************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A21OI_BEHAVIORAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long a[4]; vector<int> order, to; bool cmp(int x, int y) { return a[x] < a[y]; } int main() { cin >> a[1] >> a[2] >> a[3]; order = {1, 2, 3}; sort(order.begin(), order.end(), cmp); to = order; cout << First << endl; for (;;) { long long w = 2 * a[to[2]] - a[to[1]] - a[to[0]]; cout << w << endl; int ps; cin >> ps; if (ps == 0) return 0; a[ps] += w; if (ps == to[0]) { w = a[to[2]] - a[to[1]]; cout << w << endl; cin >> ps; if (ps == 0) return 0; a[ps] += w; } else if (ps == to[1]) { w = a[to[2]] - a[to[0]]; cout << w << endl; cin >> ps; if (ps == 0) return 0; a[ps] += w; } } return 0; }
|
module KeyboardDecoder(
output reg [511:0] key_down,
output wire [8:0] last_change,
output reg key_valid,
inout wire PS2_DATA,
inout wire PS2_CLK,
input wire rst,
input wire clk
);
parameter [1:0] INIT = 2'b00;
parameter [1:0] WAIT_FOR_SIGNAL = 2'b01;
parameter [1:0] GET_SIGNAL_DOWN = 2'b10;
parameter [1:0] WAIT_RELEASE = 2'b11;
parameter [7:0] IS_INIT = 8'hAA;
parameter [7:0] IS_EXTEND = 8'hE0;
parameter [7:0] IS_BREAK = 8'hF0;
reg [9:0] key; // key = {been_extend, been_break, key_in}
reg [1:0] state;
reg been_ready, been_extend, been_break;
wire [7:0] key_in;
wire is_extend;
wire is_break;
wire valid;
wire err;
wire [511:0] key_decode = 1 << last_change;
assign last_change = {key[9], key[7:0]};
KeyboardCtrl_0 inst (
.key_in(key_in),
.is_extend(is_extend),
.is_break(is_break),
.valid(valid),
.err(err),
.PS2_DATA(PS2_DATA),
.PS2_CLK(PS2_CLK),
.rst(rst),
.clk(clk)
);
/*OnePulse op (
.signal_single_pulse(pulse_been_ready),
.signal(been_ready),
.clock(clk)
);*/
always @ (posedge clk, posedge rst) begin
if (rst) begin
state <= INIT;
been_ready <= 1'b0;
been_extend <= 1'b0;
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end else begin
state <= state;
been_ready <= been_ready;
been_extend <= (is_extend) ? 1'b1 : been_extend;
been_break <= (is_break ) ? 1'b1 : been_break;
key <= key;
case (state)
INIT : begin
if (key_in == IS_INIT) begin
state <= WAIT_FOR_SIGNAL;
been_ready <= 1'b0;
been_extend <= 1'b0;
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end else begin
state <= INIT;
end
end
WAIT_FOR_SIGNAL : begin
if (valid == 0) begin
state <= WAIT_FOR_SIGNAL;
been_ready <= 1'b0;
end else begin
state <= GET_SIGNAL_DOWN;
end
end
GET_SIGNAL_DOWN : begin
state <= WAIT_RELEASE;
key <= {been_extend, been_break, key_in};
been_ready <= 1'b1;
end
WAIT_RELEASE : begin
if (valid == 1) begin
state <= WAIT_RELEASE;
end else begin
state <= WAIT_FOR_SIGNAL;
been_extend <= 1'b0;
been_break <= 1'b0;
end
end
default : begin
state <= INIT;
been_ready <= 1'b0;
been_extend <= 1'b0;
been_break <= 1'b0;
key <= 10'b0_0_0000_0000;
end
endcase
end
end
always @ (posedge clk, posedge rst) begin
if (rst) begin
key_valid <= 1'b0;
key_down <= 511'b0;
end else if (key_decode[last_change] && been_ready) begin
key_valid <= 1'b1;
if (key[8] == 0) begin
key_down <= key_down | key_decode;
end else begin
key_down <= key_down & (~key_decode);
end
end else begin
key_valid <= 1'b0;
key_down <= key_down;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) { if (ch == - ) f = -1; } for (; isdigit(ch); ch = getchar()) { x = x * 10 + ch - 48; } return x * f; } const int mxN = 1e5; const int P = 998244353; struct Element { long long x, v, p; } a[mxN + 3]; struct Event { int u, x, y; long long t1, t2; bool operator<(const Event &arg) const { return t1 * arg.t2 < t2 * arg.t1; } } ev[mxN * 2 + 3]; int f[mxN + 3][2][2]; int n, m; long long quickpow(long long x, long long y) { long long cur = x, ret = 1ll; for (int i = 0; y; i++) { if (y & (1ll << i)) { y -= (1ll << i); ret = ret * cur % P; } cur = cur * cur % P; } return ret; } long long mulinv(long long x) { return quickpow(x, P - 2); } struct SgTNode { long long x[2][2]; } sgt[mxN * 4 + 3]; void pushup(int u, int mid) { for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) sgt[u].x[i][j] = 0ll; for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) if (!f[mid][i][j]) { for (int ii = 0; ii < 2; ii++) for (int jj = 0; jj < 2; jj++) { sgt[u].x[ii][jj] += sgt[u << 1].x[ii][i] * sgt[u << 1 | 1].x[j][jj]; } } for (int i = 0; i < 2; i++) for (int j = 0; j < 2; j++) { sgt[u].x[i][j] %= P; } } void build(int u, int le, int ri) { if (le == ri) { sgt[u].x[0][0] = P + 1 - a[le].p, sgt[u].x[1][1] = a[le].p; return; } int mid = (le + ri) >> 1; build(u << 1, le, mid); build(u << 1 | 1, mid + 1, ri); pushup(u, mid); } void update(int u, int le, int ri, int pos) { if (le == ri) { return; } int mid = (le + ri) >> 1; if (pos <= mid) { update(u << 1, le, mid, pos); } else { update(u << 1 | 1, mid + 1, ri, pos); } pushup(u, mid); } long long query() { return (sgt[1].x[0][0] + sgt[1].x[0][1] + sgt[1].x[1][0] + sgt[1].x[1][1]) % P; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %I64d%I64d%I64d , &a[i].x, &a[i].v, &a[i].p); a[i].p = a[i].p * mulinv(100) % P; } for (int i = 1; i < n; i++) { ev[++m].u = i, ev[m].x = 1, ev[m].y = 0, ev[m].t1 = a[i + 1].x - a[i].x, ev[m].t2 = a[i].v + a[i + 1].v; if (a[i].v < a[i + 1].v) { ev[++m].u = i, ev[m].x = 0, ev[m].y = 0, ev[m].t1 = a[i + 1].x - a[i].x, ev[m].t2 = a[i + 1].v - a[i].v; } else if (a[i].v > a[i + 1].v) { ev[++m].u = i, ev[m].x = 1, ev[m].y = 1, ev[m].t1 = a[i + 1].x - a[i].x, ev[m].t2 = a[i].v - a[i + 1].v; } } sort(ev + 1, ev + m + 1); long long ans = 0ll, prob = 1ll; build(1, 1, n); for (int i = 1; i <= m; i++) { f[ev[i].u][ev[i].x][ev[i].y] = 1; update(1, 1, n, ev[i].u); long long tmp = query(), tim = ev[i].t1 * mulinv(ev[i].t2) % P; ans = (ans + (prob - tmp + P) * tim) % P; prob = tmp; } printf( %I64d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; char s[100100]; char s1[111]; char s2[110]; int main() { scanf( %s%s%s , s, s1, s2); int flag1, flag2; int n = strlen(s); int n1 = strlen(s1); int n2 = strlen(s2); flag1 = flag2 = 0; int i, j; for (i = 0; i < n; i++) { for (j = 0; j < n1; j++) { if (s[i + j] != s1[j]) break; } if (j == n1) { break; } } i += n1; for (; i < n; i++) { for (j = 0; j < n2; j++) { if (s[i + j] != s2[j]) break; } if (j == n2) { flag1 = 1; break; } } for (i = 0; i < n; i++) { for (j = 0; j < n2; j++) { if (s[i + n2 - j - 1] != s2[j]) break; } if (j == n2) { break; } } i += n2; for (; i < n; i++) { for (j = 0; j < n1; j++) { if (s[i + n1 - j - 1] != s1[j]) break; } if (j == n1) { flag2 = 1; break; } } if (flag1 == 0 && flag2 == 0) { printf( fantasy n ); } if (flag1 == 0 && flag2 == 1) { printf( backward n ); } if (flag1 == 1 && flag2 == 0) { printf( forward n ); } if (flag1 == 1 && flag2 == 1) { printf( both n ); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_LP_V
`define SKY130_FD_SC_LP__O22AI_LP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_lp (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_lp (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_LP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; char a[n + 1][n + 1]; int ans[n + 1][n + 1]; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { cin >> a[i][j]; ans[i][j] = 0; } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n - k + 1; j++) { bool x = true; for (int t = j; t < j + k; t++) { if (a[i][t] == # ) { x = false; break; } } if (x) { for (int t = j; t < j + k; t++) ans[i][t]++; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n - k + 1; j++) { bool x = true; for (int t = j; t < j + k; t++) { if (a[t][i] == # ) { x = false; break; } } if (x) { for (int t = j; t < j + k; t++) ans[t][i]++; } } } int mx = ans[1][1]; int p = 1, q = 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { if (ans[i][j] > mx) { mx = ans[i][j]; p = i; q = j; } } cout << p << << q; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_1_V
`define SKY130_FD_SC_HDLL__A21BO_1_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_1_V
|
#include <bits/stdc++.h> using namespace std; struct data { int x, y; } t[800001]; int n, m, k, x, y, sum, cnt, tot, h[400001], st[400001], f[400001], fa[400001], p[400001], idfn[400001], dfn[400001], low[400001], son[400001], dep[400001], sz[400001], tr[1600001]; char ch[11]; vector<int> v[400001]; multiset<int> q[400001]; void add(int a, int b) { cnt++; t[cnt].x = b; t[cnt].y = h[a]; h[a] = cnt; } void tarjan(int a) { cnt++; dfn[a] = cnt; low[a] = cnt; tot++; st[tot] = a; for (int i = h[a]; i; i = t[i].y) { if (!dfn[t[i].x]) { tarjan(t[i].x); low[a] = min(low[a], low[t[i].x]); if (low[t[i].x] >= dfn[a]) { sum++; v[sum].push_back(a); v[a].push_back(sum); int c; do { c = st[tot]; tot--; v[sum].push_back(c); v[c].push_back(sum); } while (c != t[i].x); } } else { low[a] = min(low[a], dfn[t[i].x]); } } } void dfs1(int a) { sz[a] = 1; for (int i = h[a]; i; i = t[i].y) { if (t[i].x == fa[a]) continue; fa[t[i].x] = a; dep[t[i].x] = dep[a] + 1; dfs1(t[i].x); if (sz[son[a]] < sz[t[i].x]) son[a] = t[i].x; sz[a] = sz[a] + sz[t[i].x]; } } void dfs2(int a, int c) { cnt++; dfn[a] = cnt; idfn[cnt] = a; p[a] = c; if (son[a]) dfs2(son[a], c); for (int i = h[a]; i; i = t[i].y) { if (t[i].x == fa[a]) continue; if (t[i].x == son[a]) continue; dfs2(t[i].x, t[i].x); } } void build(int a, int l, int r) { if (l == r) { tr[a] = f[idfn[l]]; return; } int mid = (l + r) / 2; build(a * 2, l, mid); build(a * 2 + 1, mid + 1, r); tr[a] = min(tr[a * 2], tr[a * 2 + 1]); } void turn(int a, int l, int r, int u, int v) { if (l > u || r < u) return; if (l == r) { tr[a] = v; return; } int mid = (l + r) / 2; turn(a * 2, l, mid, u, v); turn(a * 2 + 1, mid + 1, r, u, v); tr[a] = min(tr[a * 2], tr[a * 2 + 1]); } int find(int a, int l, int r, int ql, int qr) { if (l > qr || r < ql) return 1000000000; if (ql <= l && r <= qr) return tr[a]; int mid = (l + r) / 2; int p1 = find(a * 2, l, mid, ql, qr); int p2 = find(a * 2 + 1, mid + 1, r, ql, qr); return min(p1, p2); } int solve(int a, int b) { int s = 1000000000; while (p[a] != p[b]) { if (dep[p[a]] > dep[p[b]]) swap(a, b); s = min(s, find(1, 1, sum, dfn[p[b]], dfn[b])); b = fa[p[b]]; } if (dep[a] > dep[b]) swap(a, b); s = min(s, find(1, 1, sum, dfn[a], dfn[b])); if (a > n) s = min(s, f[fa[a]]); return s; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %d , &f[i]); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); add(x, y); add(y, x); } cnt = 0; sum = n; tarjan(1); cnt = 0; for (int i = 1; i <= n; i++) h[i] = 0; for (int i = 1; i <= sum; i++) { for (int j = 0; j < v[i].size(); j++) { add(i, v[i][j]); } } cnt = 0; dfs1(1); dfs2(1, 1); for (int i = n + 1; i <= sum; i++) { for (int j = h[i]; j; j = t[j].y) { if (t[j].x == fa[i]) continue; q[i].insert(f[t[j].x]); } f[i] = *q[i].begin(); } build(1, 1, sum); for (int i = 1; i <= k; i++) { scanf( %s%d%d , ch + 1, &x, &y); if (ch[1] == C ) { if (fa[x] > n) { q[fa[x]].erase(q[fa[x]].find(f[x])); q[fa[x]].insert(y); turn(1, 1, sum, dfn[fa[x]], *q[fa[x]].begin()); } f[x] = y; turn(1, 1, sum, dfn[x], y); } else { printf( %d n , solve(x, y)); } } }
|
#include <bits/stdc++.h> using namespace std; long long call(long long n) { if (n == 1) return 1; else return n + call(n / 2); } void fun() { long long n; cin >> n; cout << call(n); } int main() { long long t; cin >> t; while (t--) { fun(); cout << endl; } return 0; }
|
#include <iostream> #include <iomanip> #include<iterator> // for iterators #include<vector> // for vectors #include <utility> #include <algorithm> #include <set> #include <map> #include <stack> #include <unordered_map> using namespace std; int main() { int t, n, temp; scanf( %d , &t); vector<int> v; while (t --) { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , &temp); v.emplace_back(temp); } sort(v.begin() , v.end()); int counter = 0; for (int i = 1; i < v.size(); ++i) { if (v[i] > v[0]) counter ++; } printf( %d n , counter); v.clear(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; using LL = long long; constexpr int N = 1e5 + 5; void solve() { int a, b; cin >> a >> b; if (a * 2 <= b) cout << a << << a * 2 << n ; else cout << -1 -1 n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const int N = 3000 * 100 + 5; vector<pair<int, int> > adj[N]; pair<int, int> edge[N]; short d[N]; bool mark[N], edg[N], c[N]; int bad[N], par[N], m, n; void findd(int a, int e, int b) { while (a != b) { edg[e] = 1; if (a == edge[e].first) a = edge[e].second; else a = edge[e].first; e = par[a]; } return; } void DFS2(int v, int parr) { mark[v] = 1; par[v] = parr; int s = adj[v].size(); int temp = -1, temp2 = 0; if (c[v]) temp = v; for (int i = 0; i < s; i++) { int u = adj[v][i].first; int w = adj[v][i].second; if (!mark[u]) { DFS2(u, w); if (bad[u] != -1) { if (temp == -1) { temp = bad[u]; temp2 = par[bad[u]]; } else { findd(temp, temp2, v); findd(bad[u], par[bad[u]], v); temp = -1; } } } } bad[v] = temp; return; } void DFS(int v) { mark[v] = 1; int s = adj[v].size(); for (int i = 0; i < s; i++) { int u = adj[v][i].first; int w = adj[v][i].second; if (!mark[u]) { DFS(u); if (c[u]) { c[v] = 1 - c[v]; edg[w] = 1; } } } return; } void pp() { int t = 0; for (int i = 0; i < m; i++) { if (!edg[i]) t++; } printf( %d n , t); for (int i = 0; i < m; i++) { if (!edg[i]) printf( %d n , i + 1); } return; } int main() { int t = -1, x, y, k = 0; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &d[i]); if (d[i] == -1) t = i; } for (int i = 0; i < m; i++) { scanf( %d %d , &x, &y); adj[--x].push_back(make_pair(--y, i)); adj[y].push_back(make_pair(x, i)); edge[i] = make_pair(x, y); } for (int i = 0; i < n; i++) { int s = adj[i].size(); if (d[i] == 0 && s % 2) { k++; c[i] = 1; } if (d[i] == 1 && s % 2 == 0) { k++; c[i] = 1; } } if (t != -1) { DFS(t); pp(); } else { t = 0; if (k % 2 == 1) { cout << -1 ; return 0; } DFS2(0, m); pp(); } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_M_V
`define SKY130_FD_SC_LP__AND4BB_M_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_m (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4bb_m (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_M_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; const long long INF = 1e10; const int MOD = 1e9 + 7; const double EPS = 1e-7; const double PI = acos(-1.0); pair<long long, long long> p[N]; long long n, k, a[N]; int main() { ios::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; p[i] = {a[i], i}; } sort(p, p + n); long long ans = LLONG_MIN; for (int l = 0; l < n; l++) { for (int r = l; r < n; r++) { long long sum = 0; vector<long long> subarr(r - l + 1); for (int i = l, j = 0; i <= r; i++, j++) { subarr[j] = a[i]; sum += a[i]; } sort(subarr.begin(), subarr.end()); for (int i = 0, j = n - 1; i < min(k, r - l + 1ll); i++) { while (j >= 0 && p[j].second <= r && p[j].second >= l) { j--; } if (j >= 0) { sum = max(sum, sum - subarr[i] + p[j].first); j--; } } ans = max(ans, sum); } } cout << ans << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLRBP_PP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_PP_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND2B_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2b (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_BLACKBOX_V
|
//---------------------------------------------------------------------------------------
// Generated by WISHBONE Builder. Do not edit this file.
//
// For defines see wb_devices.defines
//
// Generated Tue May 30 10:23:57 2017
//
// Wishbone masters:
// cpu
//
// Wishbone slaves:
// rs2
// baseadr 0x00000000 - size 0x40
// ad
// baseadr 0x00000040 - size 0x40
// tmr
// baseadr 0x00000080 - size 0x40
// t16
// baseadr 0x000000C0 - size 0x40
//---------------------------------------------------------------------------------------
module WBDevIntercon
(
// WISHBONE master port(s)
// cpu
output [7:0] cpu_dat_o,
output cpu_ack_o,
input [7:0] cpu_dat_i,
input cpu_we_i,
input [7:0] cpu_adr_i,
input cpu_cyc_i,
input cpu_stb_i,
// WISHBONE slave port(s)
// rs2
input [7:0] rs2_dat_i,
input rs2_ack_i,
output [7:0] rs2_dat_o,
output rs2_we_o,
output [0:0] rs2_adr_o,
output rs2_stb_o,
// ad
input [7:0] ad_dat_i,
input ad_ack_i,
output [7:0] ad_dat_o,
output ad_we_o,
output [0:0] ad_adr_o,
output ad_stb_o,
// tmr
input [7:0] tmr_dat_i,
input tmr_ack_i,
output [7:0] tmr_dat_o,
output tmr_we_o,
output [2:0] tmr_adr_o,
output tmr_stb_o,
// t16
input [7:0] t16_dat_i,
input t16_ack_i,
output [7:0] t16_dat_o,
output t16_we_o,
output [0:0] t16_adr_o,
output t16_stb_o,
// Clock and reset
input wb_clk_i,
input wb_rst_i);
// Slave select
wire rs2_ss;
wire ad_ss;
wire tmr_ss;
wire t16_ss;
wire [7:0] adr;
assign adr=cpu_adr_i;
assign rs2_ss=adr[7:6]==2'b00;
assign ad_ss=adr[7:6]==2'b01;
assign tmr_ss=adr[7:6]==2'b10;
assign t16_ss=adr[7:6]==2'b11;
assign rs2_adr_o=adr[0:0];
assign ad_adr_o=adr[0:0];
assign tmr_adr_o=adr[2:0];
assign t16_adr_o=adr[0:0];
wire stb_m2s;
wire we_m2s;
wire ack_s2m;
wire [7:0] dat_m2s;
wire [7:0] dat_s2m;
// stb Master -> Slave [Selection]
assign stb_m2s=cpu_stb_i;
assign rs2_stb_o=rs2_ss & stb_m2s;
assign ad_stb_o=ad_ss & stb_m2s;
assign tmr_stb_o=tmr_ss & stb_m2s;
assign t16_stb_o=t16_ss & stb_m2s;
// we Master -> Slave
assign we_m2s=cpu_we_i;
assign rs2_we_o=we_m2s;
assign ad_we_o=we_m2s;
assign tmr_we_o=we_m2s;
assign t16_we_o=we_m2s;
// ack Slave -> Master
assign ack_s2m=rs2_ack_i | ad_ack_i | tmr_ack_i | t16_ack_i;
assign cpu_ack_o=ack_s2m;
// dat Master -> Slave
assign dat_m2s=cpu_dat_i;
assign rs2_dat_o=dat_m2s;
assign ad_dat_o=dat_m2s;
assign tmr_dat_o=dat_m2s;
assign t16_dat_o=dat_m2s;
// dat Slave -> Master [and/or]
assign dat_s2m=(rs2_dat_i & {8{rs2_ss}}) | (ad_dat_i & {8{ad_ss}}) | (tmr_dat_i & {8{tmr_ss}}) | (t16_dat_i & {8{t16_ss}});
assign cpu_dat_o=dat_s2m;
endmodule // WBDevIntercon
|
/* SRAM Test Bench
*
* Case I:
* Tests the FIFO by writing the FF byte and reading them back.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-01-2014
*/
`include "sram_fifo.v"
module sram_fifo_tb (
readMode, // Specifies if we want to read to the FIFO
writeMode, // Specifies if we want to write to the FIFO
inputPacket // The input packet
);
parameter bits = 8;
output readMode, writeMode;
reg readMode, writeMode;
reg readModeQ;
output [bits-1:0] inputPacket;
reg [bits-1:0] inputPacket;
reg clk, rst;
wire [bits-1:0] outputPacket;
SRAM_fifo SRAM (readMode, writeMode, inputPacket, outputPacket, clk, rst);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
forever begin
@(posedge clk); begin // Only output on positive edge
$display("time=%04d RW=%b%b I=%h O=%h clk=%b", $time,
readModeQ, writeMode, inputPacket, outputPacket, clk);
readModeQ = readMode;
end
end
end
initial
begin
// Test Case I: Write to capacity and empty
rst = 1;
readMode = 0;
readModeQ = 0;
writeMode = 0;
#5 rst = 0;
#5 inputPacket = {bits{1'b1}}; writeMode = 1;
#80 writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
#90 readMode = 0;
if (outputPacket === {bits{1'b1}}) begin
$display("Pass");
end else begin
$display("Fail");
end
$finish;
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.2
// \ \ Application : xaw2verilog
// / / Filename : DCM_FRL.v
// /___/ /\ Timestamp : 10/19/2012 11:30:08
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL.xaw D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL
//Design Name: DCM_FRL
//Device: xc5vlx50t-1ff1136
//
// Module DCM_FRL
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module DCM_FRL(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLK0_BUF;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(4.464),
.CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"),
.DCM_PERFORMANCE_MODE("MAX_SPEED"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
.DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
wire [width-1:0] dec_test_expr = test_expr - {{width-1{1'b0}},1'b1};
wire zoh_test_expr = ((test_expr & dec_test_expr) == {width{1'b0}});
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression contains more or less than 1 asserted bits");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = !zoh_test_expr || (test_expr == {width{1'b0}});
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
// Auxiliary logic
reg [width-1:0] one_hots_checked;
reg [width-1:0] prev_one_hots_checked;
reg [width-1:0] prev_test_expr;
always @ (posedge clk) begin
prev_test_expr <= test_expr; // deliberately not reset
if (`OVL_RESET_SIGNAL == 1'b0) begin
one_hots_checked <= {width{1'b0}};
prev_one_hots_checked <= {width{1'b0}};
end
else begin
if (valid_test_expr && zoh_test_expr) begin
one_hots_checked <= one_hots_checked | test_expr;
end
prev_one_hots_checked <= one_hots_checked;
end
end
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("test_expr_change covered"); // sanity
end
if (fire_cover_2) begin
ovl_cover_t("all_one_hots_checked covered"); // corner
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_SANITY_ON > 0) && (test_expr != prev_test_expr));
assign fire_cover_2 = ((OVL_COVER_CORNER_ON > 0) && (one_hots_checked == {width{1'b1}}) && (one_hots_checked != prev_one_hots_checked));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_axis_tx
*/
module test_eth_axis_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser,
busy
);
// dump file
$dumpfile("test_eth_axis_tx.lxt");
$dumpvars(0, test_eth_axis_tx);
end
eth_axis_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int query(vector<int>& v) { cout << ? ; for (auto& x : v) { cout << x << ; } cout << endl; int a; cin >> a; return a; } void solve(int n) { int x = 1; vector<int> v(n, 1); for (int i = n; i >= 2; i--) { for (int j = 0; j < n - 1; j++) { v[j] = i; } int a = query(v); if (a == 0) continue; x = i; break; } vector<int> ans(n, -1); ans[n - 1] = x; for (int i = 0; i < n; i++) { v[i] = x; } for (int i = 1; i <= n; i++) { if (i == x) continue; v[n - 1] = i; int index = query(v); ans[index - 1] = i; } cout << ! ; for (auto& y : ans) { cout << y << ; } cout << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; while (t--) { int n; cin >> n; solve(n); } }
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 2e5; const long long inf = 1e15; inline int read() { char ch = getchar(); int f = 1, x = 0; while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } struct Point { long long x, y; Point() : x(0), y(0) {} Point(long long X, long long Y) : x(X), y(Y) {} inline long long Len() { return x * x + y * y; } }; bool operator<(Point a, Point b) { return a.x == b.x ? a.y < b.y : a.x < b.x; } inline long long Dis(Point a, Point b) { return Point(a.x - b.x, a.y - b.y).Len(); } int n; long long ans = 1e15, sum[Maxn + 5]; Point P[Maxn + 5], st[Maxn + 5]; inline long long Divide(int l, int r) { int mid = (l + r) >> 1, i, j, tot = 0; if (l == r) return inf; long long d; Point pnt = P[mid]; d = min(Divide(l, mid), Divide(mid + 1, r)); i = l, j = mid + 1; while (i <= mid && j <= r) { if (P[i].y < P[j].y) st[++tot] = P[i++]; else st[++tot] = P[j++]; } while (i <= mid) st[++tot] = P[i++]; while (j <= r) st[++tot] = P[j++]; for (int i = l; i <= r; ++i) P[i] = st[i - l + 1]; tot = 0; for (int i = l; i <= r; ++i) if ((pnt.x - P[i].x) * (pnt.x - P[i].x) < d) st[++tot] = P[i]; for (int i = 1; i <= tot; ++i) for (int j = i + 1; (st[j].y - st[i].y) * (st[j].y - st[i].y) < d && j <= tot; ++j) d = min(d, Dis(st[i], st[j])); return d; } int main() { n = read(); for (int i = 1; i <= n; ++i) sum[i] = sum[i - 1] + read(); for (int i = 1; i <= n; ++i) P[i] = Point(i, sum[i]); sort(P + 1, P + n + 1); ans = Divide(1, n); printf( %lld n , ans); return 0; }
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_mem_server_request_put O 1 reg
// mem_server_response_get O 256 reg
// RDY_mem_server_response_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// mem_server_request_put I 353
// EN_mem_server_request_put I 1
// EN_mem_server_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMem_Model(CLK,
RST_N,
mem_server_request_put,
EN_mem_server_request_put,
RDY_mem_server_request_put,
EN_mem_server_response_get,
mem_server_response_get,
RDY_mem_server_response_get);
input CLK;
input RST_N;
// action method mem_server_request_put
input [352 : 0] mem_server_request_put;
input EN_mem_server_request_put;
output RDY_mem_server_request_put;
// actionvalue method mem_server_response_get
input EN_mem_server_response_get;
output [255 : 0] mem_server_response_get;
output RDY_mem_server_response_get;
// signals for module outputs
wire [255 : 0] mem_server_response_get;
wire RDY_mem_server_request_put, RDY_mem_server_response_get;
// ports of submodule f_raw_mem_rsps
wire [255 : 0] f_raw_mem_rsps$D_IN, f_raw_mem_rsps$D_OUT;
wire f_raw_mem_rsps$CLR,
f_raw_mem_rsps$DEQ,
f_raw_mem_rsps$EMPTY_N,
f_raw_mem_rsps$ENQ,
f_raw_mem_rsps$FULL_N;
// ports of submodule rf
wire [255 : 0] rf$D_IN, rf$D_OUT_1;
wire [63 : 0] rf$ADDR_1,
rf$ADDR_2,
rf$ADDR_3,
rf$ADDR_4,
rf$ADDR_5,
rf$ADDR_IN;
wire rf$WE;
// rule scheduling signals
wire CAN_FIRE_mem_server_request_put,
CAN_FIRE_mem_server_response_get,
WILL_FIRE_mem_server_request_put,
WILL_FIRE_mem_server_response_get;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h371;
reg [31 : 0] v__h365;
// synopsys translate_on
// remaining internal signals
wire mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2;
// action method mem_server_request_put
assign RDY_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign CAN_FIRE_mem_server_request_put = f_raw_mem_rsps$FULL_N ;
assign WILL_FIRE_mem_server_request_put = EN_mem_server_request_put ;
// actionvalue method mem_server_response_get
assign mem_server_response_get = f_raw_mem_rsps$D_OUT ;
assign RDY_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign CAN_FIRE_mem_server_response_get = f_raw_mem_rsps$EMPTY_N ;
assign WILL_FIRE_mem_server_response_get = EN_mem_server_response_get ;
// submodule f_raw_mem_rsps
FIFO2 #(.width(32'd256), .guarded(32'd1)) f_raw_mem_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_raw_mem_rsps$D_IN),
.ENQ(f_raw_mem_rsps$ENQ),
.DEQ(f_raw_mem_rsps$DEQ),
.CLR(f_raw_mem_rsps$CLR),
.D_OUT(f_raw_mem_rsps$D_OUT),
.FULL_N(f_raw_mem_rsps$FULL_N),
.EMPTY_N(f_raw_mem_rsps$EMPTY_N));
// submodule rf
RegFileLoad #(.file("Mem.hex"),
.addr_width(32'd64),
.data_width(32'd256),
.lo(64'd0),
.hi(64'd8388607),
.binary(1'd0)) rf(.CLK(CLK),
.ADDR_1(rf$ADDR_1),
.ADDR_2(rf$ADDR_2),
.ADDR_3(rf$ADDR_3),
.ADDR_4(rf$ADDR_4),
.ADDR_5(rf$ADDR_5),
.ADDR_IN(rf$ADDR_IN),
.D_IN(rf$D_IN),
.WE(rf$WE),
.D_OUT_1(rf$D_OUT_1),
.D_OUT_2(),
.D_OUT_3(),
.D_OUT_4(),
.D_OUT_5());
// submodule f_raw_mem_rsps
assign f_raw_mem_rsps$D_IN = rf$D_OUT_1 ;
assign f_raw_mem_rsps$ENQ =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
!mem_server_request_put[352] ;
assign f_raw_mem_rsps$DEQ = EN_mem_server_response_get ;
assign f_raw_mem_rsps$CLR = 1'b0 ;
// submodule rf
assign rf$ADDR_1 = mem_server_request_put[319:256] ;
assign rf$ADDR_2 = 64'h0 ;
assign rf$ADDR_3 = 64'h0 ;
assign rf$ADDR_4 = 64'h0 ;
assign rf$ADDR_5 = 64'h0 ;
assign rf$ADDR_IN = mem_server_request_put[319:256] ;
assign rf$D_IN = mem_server_request_put[255:0] ;
assign rf$WE =
EN_mem_server_request_put &&
mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 &&
mem_server_request_put[352] ;
// remaining internal signals
assign mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2 =
mem_server_request_put[319:256] < 64'h0000000000800000 ;
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
begin
v__h371 = $stime;
#0;
end
v__h365 = v__h371 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$display("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)",
v__h365,
mem_server_request_put[319:256],
64'h0000000000800000);
if (RST_N != `BSV_RESET_VALUE)
if (EN_mem_server_request_put &&
!mem_server_request_put_BITS_319_TO_256_ULT_0x8_ETC___d2)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkMem_Model
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module slave #(
parameter id = 0,
parameter p = 3
) (
input sys_clk,
input sys_rst,
input [31:0] dat_w,
output reg [31:0] dat_r,
input [31:0] adr,
input [2:0] cti,
input we,
input [3:0] sel,
input cyc,
input stb,
output reg ack
);
always @(posedge sys_clk) begin
if(sys_rst) begin
dat_r = 0;
ack = 0;
end else begin
if(cyc & stb & ~ack) begin
if(($random % p) == 0) begin
ack = 1;
if(~we)
dat_r = ($random << 16) + id;
if(we)
$display("[S%d] Ack W: %x:%x [%x]", id, adr, dat_w, sel);
else
$display("[S%d] Ack R: %x:%x [%x]", id, adr, dat_r, sel);
end
end else
ack = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; bool b[4][n][n]; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { char c[n + 1]; scanf( %s , &c); for (int k = 0; k < n; k++) b[i][j][k] = c[k] == 1 ? 1 : 0; } } int s[] = {0, 1, 2, 3}, mi = 1e9, co = 0; bool o = 0; do { for (int k = 0; k < 4; k += 2) { for (int j = 0; j < n; j++) { for (int i = 0; i < n; i++) { if (b[s[k]][j][i] != o) co++; o ^= 1; } for (int i = 0; i < n; i++) { if (b[s[k + 1]][j][i] != o) co++; o ^= 1; } o ^= 1; } } mi = min(mi, co); co = 0; } while (next_permutation(s, s + 4)); cout << mi << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int firstt(int* a, int n) { long long l, r, s; for (int i = 0; i <= n - 1; ++i) { l = 0; r = 10000000000; while (l < r - 1) { s = (-l + r) / 2 + l; if (s * n >= a[i] - i) { r = s; } else { l = s; } } if (l * n >= a[i] - i) { a[i] = l; } else { a[i] = l + 1; } } l = 0; int minn = a[0]; for (int i = 1; i <= n - 1; ++i) { if (a[i] < minn) { minn = a[i]; l = i; } } return (l + 1); } int main() { int n, i; cin >> n; int* a = new int[n]; for (i = 0; i <= n - 1; ++i) { cin >> a[i]; } long long res = firstt(a, n); cout << res; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; char s[maxn]; struct Node { int sum, pmx, lmx, mi, ma, d; Node() {} Node(int a, int b, int c, int d, int e, int f) { sum = a; pmx = b; lmx = c; mi = d; ma = e; d = f; } }; Node segT[maxn << 2]; void maintain(int curPos) { segT[curPos].sum = segT[curPos << 1].sum + segT[curPos << 1 | 1].sum; segT[curPos].pmx = max(segT[curPos << 1].pmx, max(segT[curPos << 1 | 1].ma - 2 * segT[curPos << 1].mi + segT[curPos << 1].sum, segT[curPos << 1 | 1].pmx - segT[curPos << 1].sum)); segT[curPos].lmx = max(segT[curPos << 1].lmx, max(segT[curPos << 1 | 1].lmx - segT[curPos << 1].sum, segT[curPos << 1].ma - 2 * segT[curPos << 1 | 1].mi - 2 * segT[curPos << 1].sum)); segT[curPos].mi = min(segT[curPos << 1].mi, segT[curPos << 1 | 1].mi + segT[curPos << 1].sum); segT[curPos].ma = max(segT[curPos << 1].ma, segT[curPos << 1 | 1].ma + segT[curPos << 1].sum); segT[curPos].d = max(max(segT[curPos << 1].d, segT[curPos << 1 | 1].d), max(segT[curPos << 1].ma + segT[curPos << 1 | 1].pmx - segT[curPos << 1].sum, segT[curPos << 1].lmx + segT[curPos << 1].sum + segT[curPos << 1 | 1].ma)); } void build(int curPos, int curL, int curR) { if (curL == curR) { curR = s[curL] == ( ? 1 : -1; segT[curPos] = Node(curR, -curR, -curR, curR, curR, 0); return; } int mid = curL + curR >> 1; build(curPos << 1, curL, mid); build(curPos << 1 | 1, mid + 1, curR); maintain(curPos); } void update(int pos, int curPos, int curL, int curR) { if (curL == curR) return build(curPos, curL, curR); int mid = curL + curR >> 1; if (pos <= mid) update(pos, curPos << 1, curL, mid); else update(pos, curPos << 1 | 1, mid + 1, curR); maintain(curPos); } int main() { int n, m; scanf( %d%d , &n, &m); scanf( %s , s + 1); n = n * 2 - 2; build(1, 1, n); printf( %d n , segT[1].d); while (m--) { int x, y; scanf( %d%d , &x, &y); swap(s[x], s[y]); update(x, 1, 1, n); update(y, 1, 1, n); printf( %d n , segT[1].d); } return 0; }
|
module axi2spi_bridge(
//CLK
input FCLK_CLK0,
//RST
input RST_N,
//AXI INTERFACE
input [31:0] AXI_araddr, // read address address (data)
input [2:0] AXI_arprot, // ???
output [0:0] AXI_arready, // read address ready
input [0:0] AXI_arvalid, // read address valid
input [31:0] AXI_awaddr, // write address address (channel data)
input [2:0] AXI_awprot, // write address ??
output [0:0] AXI_awready, // write address ready
input [0:0] AXI_awvalid, // write address valid
input [0:0] AXI_bready, // (write) response ready
output [1:0] AXI_bresp, // write response
output [0:0] AXI_bvalid, // write response valid
output [31:0] AXI_rdata, // read data
input [0:0] AXI_rready, // read ready
output [1:0] AXI_rresp, // read response
output [0:0] AXI_rvalid, // read valid
input [31:0] AXI_wdata, // write data
output [0:0] AXI_wready, // write ready
input [3:0] AXI_wstrb, // ??
input [0:0] AXI_wvalid, // write valid
//IRQ to AXI master
output IRQ,
//SPI interface
input i_miso,
output o_mosi,
output o_sclk
);
// Signal declarations to connect AXI to spi controller:
wire [31:0] w_data_to_registers;
wire w_wr_controll_reg, w_wr_data_reg;
wire [31:0] w_controll_reg;
wire [31:0] w_status_reg;
wire [31:0] w_data_reg;
wire w_irq;
assign IRQ = w_irq;
// Implementation of the AXI interface:
axi_interface axi_interface_inst(
//CLK
.FCLK_CLK0(FCLK_CLK0),
//RST
.RST_N(RST_N),
//Signals towards register interface:
.o_data_to_registers(w_data_to_registers),
.o_wr_controll_reg(w_wr_controll_reg), // Offset: 0x00
.o_wr_data_reg(w_wr_data_reg), // Offset: 0x08
.i_controll_reg(w_controll_reg),
.i_status_reg(w_status_reg),
.i_data_reg(w_data_reg),
//AXI INTERFACE
.AXI_araddr(AXI_araddr), // read address address (data)
.AXI_arprot(AXI_arprot), // ???
.AXI_arready(AXI_arready), // read address ready
.AXI_arvalid(AXI_arvalid), // read address valid
.AXI_awaddr(AXI_awaddr), // write address address (channel data)
.AXI_awprot(AXI_awprot), // write address ??
.AXI_awready(AXI_awready), // write address ready
.AXI_awvalid(AXI_awvalid), // write address valid
.AXI_bready(AXI_bready), // (write) response ready
.AXI_bresp(AXI_bresp), // write response
.AXI_bvalid(AXI_bvalid), // write response valid
.AXI_rdata(AXI_rdata), // read data
.AXI_rready(AXI_rready), // read ready
.AXI_rresp(AXI_rresp), // read response
.AXI_rvalid(AXI_rvalid), // read valid
.AXI_wdata(AXI_wdata), // write data
.AXI_wready(AXI_wready), // write ready
.AXI_wstrb(AXI_wstrb), // ??
.AXI_wvalid(AXI_wvalid) // write valid
);
// Implementation of spi_controller:
spi_controller spi_controller_inst(
//CLK
.clk(FCLK_CLK0),
//RST
.RST_N(RST_N),
//IRQ to AXI master
.o_IRQ(w_irq),
//Signals towards AXI interface:
.i_data_to_registers(w_data_to_registers),
.i_wr_controll_reg(w_wr_controll_reg), // Offset: 0x00
.i_wr_data_reg(w_wr_data_reg), // Offset: 0x08
.i_read_status_reg(w_read_status_reg),
.o_controll_reg(w_controll_reg),
.o_status_reg(w_status_reg),
.o_data_reg(w_data_reg),
//SPI interface
.i_miso(i_miso),
.o_mosi(o_mosi),
.o_sclk(o_sclk)
);
endmodule
|
/*
* NAME
* ----
*
* led_ctl - bussed LED control
*
*
* DESCRIPTION
* -----------
*
* 8-bit bar led module suitable for use with a "bus"
* consisting of address, data and control lines.
*
* To write, data must be assigned to the data bus ('data'),
* write must be enabled (write_n=0), read must not be
* enabled (read_n=1), and the chip must be enabled (ce_n=0).
*
* AUTHOR
* ------
*
* Jeremiah Mahler <>
*
*/
module led_ctl(
input read_n,
write_n,
reset_n,
ce_n,
inout [7:0] data,
output reg [7:0] leds);
// ~(leds) and ~(data) are used to invert the inputs/outputs
// to compensate for actual pull up circuit which inverts the
// value.
// READ
// If we are enabled (ce_n lo) and read is enabled (read_n lo)
// and write is not enabled (write_n hi)
// drive the leds values on to the data bus.
assign data = (~(ce_n | read_n | ~write_n)) ? ~(leds) : 8'bz;
// This is a psuedo wire that goes low when BOTH write_n
// and ce_n are low.
// ~A & ~B = ~(A | B) (De Morgans Law)
wire write_ce_n;
assign write_ce_n = write_n | ce_n;
// WRITE
// If anything here changes and reset_n is low, reset leds
// If write_n or ce_n change such that write is enabled
// (write_n lo) and the chip is enabled (ce_n lo)
// write the data to the leds.
always @(negedge reset_n, posedge write_ce_n) begin
if (~reset_n)
leds <= ~(8'h00);
else
leds <= ~(data);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int ma = -1, mi = 1000000000000000; inline long long int gcd(long long int a, long long int b) { return b ? gcd(b, a % b) : a; } inline long long int lcm(long long int a, long long int b, long long int MOD) { return a / gcd(a, b) * b % MOD; } long long int power(long long int x, unsigned int y) { if (y == 0) return 1; else if (y % 2 == 0) return power(x, y / 2) * power(x, y / 2); else return x * power(x, y / 2) * power(x, y / 2); } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int i, j, k, a[100009] = {0}, b[100009] = {0}, c = 0, d = 0; string n, m; cin >> n >> m; if (n == monday ) { if (m == monday || m == wednesday || m == thursday ) { cout << YES << endl; return 0; } } if (n == tuesday ) { if (m == tuesday || m == friday || m == thursday ) { cout << YES << endl; return 0; } } if (n == wednesday ) { if (m == friday || m == wednesday || m == saturday ) { cout << YES << endl; return 0; } } if (n == thursday ) { if (m == saturday || m == sunday || m == thursday ) { cout << YES << endl; return 0; } } if (n == friday ) { if (m == friday || m == sunday || m == monday ) { cout << YES << endl; return 0; } } if (n == saturday ) { if (m == saturday || m == monday || m == tuesday ) { cout << YES << endl; return 0; } } if (n == sunday ) { if (m == sunday || m == wednesday || m == tuesday ) { cout << YES << endl; return 0; } } cout << NO << endl; }
|
module top;
reg pass;
real rvar;
wire [3:0] var;
assign var = rvar;
initial begin
pass = 1'b1;
rvar <= 1'b0;
#1 rvar = 1'b1;
#1 rvar = 2'b10;
#1 rvar = 2'b11;
#1 if (pass) $display("PASSED");
end
real_to_bit u1(rvar);
real_to_real u2(rvar);
real_to_real u3[1:0](rvar);
real_to_vec u4(rvar);
real_to_vec u5[1:0](rvar);
bit_to_real u6(var[0]);
vec_to_real u7(var);
vec_to_real u8[1:0](var);
endmodule
// Check a real value going to a single bit.
module real_to_bit (input wire in);
always @(in) if (in !== $stime%2) begin
$display("Failed real_to_bit %m at %1d, got %b, expected %2b",
$stime, in, $stime%2);
top.pass = 1'b0;
end
endmodule
// Check a real value going to a real wire.
module real_to_real (input wire real in);
always @(in) if (in != $stime) begin
$display("Failed real_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1'b0;
end
endmodule
// Check a real value going to multiple bit.
module real_to_vec (input wire [3:0] in);
always @(in) if (in !== $stime) begin
$display("Failed real_to_vec %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1'b0;
end
endmodule
// Check a single bit going to a real wire.
module bit_to_real (input wire real in);
always @(in) if (in != $stime%2) begin
$display("Failed bit_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime%2);
top.pass = 1'b0;
end
endmodule
// Check a vector going to a real wire.
module vec_to_real (input wire real in);
always @(in) if (in != $stime) begin
$display("Failed vec_to_real %m at %1d, got %0d, expected %0d",
$stime, in, $stime);
top.pass = 1'b0;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module small_fifo_test (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
output [4:0] usedw;
wire [4:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] sub_wire3;
wire [4:0] usedw = sub_wire0[4:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [31:0] q = sub_wire3[31:0];
scfifo scfifo_component (
.clock (clock),
.sclr (sclr),
.wrreq (wrreq),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix II",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long k; cin >> n >> k; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); int prev = arr[0], best = -1, num, left = 0; for (int i = 0; i < n; i++) { k -= (0LL + i - left) * (arr[i] - prev); while (k < 0) { k += arr[i] - arr[left++]; } if (best < i - left + 1) { best = i - left + 1; num = arr[i]; } prev = arr[i]; } cout << best << << num << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
/**
* udp_dff$P_pp$PKG$s: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$P_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 100005, LOG = 25; long long n, f[N][LOG + 5], cnt = 0, head[N], dep[N]; long long size[N]; struct CLANNAD { long long to, nxt; } a[N << 1]; inline void add(long long u, long long v) { a[++cnt].to = v; a[cnt].nxt = head[u]; head[u] = cnt; } inline long long getnode(long long x, long long deep) { for (long long i = LOG; i >= 0; i--) if (dep[f[x][i]] >= deep) x = f[x][i]; return x; } inline long long LCA(long long x, long long y) { if (dep[x] < dep[y]) swap(x, y); long long ox = x, oy = y; for (long long i = LOG; i >= 0; i--) if (dep[f[x][i]] >= dep[y]) x = f[x][i]; long long lca; if (x == y) lca = x; else { for (long long i = LOG; i >= 0; i--) if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; lca = f[x][0]; } long long dis = dep[ox] + dep[oy] - dep[lca] * 2; if (dis & 1) return 0; else if (oy == lca) { long long mid = (dep[ox] + dep[oy]) >> 1; return size[getnode(ox, mid)] - size[getnode(ox, mid + 1)]; } else if (dep[ox] != dep[oy]) { long long mid = dep[ox] - dis / 2; return size[getnode(ox, mid)] - size[getnode(ox, mid + 1)]; } else return n - size[getnode(ox, dep[lca] + 1)] - size[getnode(oy, dep[lca] + 1)]; } void dfs(long long x, long long fx) { size[x] = 1; dep[x] = dep[fx] + 1; f[x][0] = fx; for (long long i = 1; i <= LOG; i++) f[x][i] = f[f[x][i - 1]][i - 1]; for (long long i = head[x]; i; i = a[i].nxt) if (a[i].to != fx) dfs(a[i].to, x), size[x] += size[a[i].to]; } signed main() { cin >> n; long long u, v; for (long long i = 1; i <= n - 1; i++) scanf( %lld%lld , &u, &v), add(u, v), add(v, u); dfs(1, 0); long long T, x, y; cin >> T; while (T--) { scanf( %lld%lld , &x, &y); if (x == y) printf( %lld n , n); else printf( %lld n , LCA(x, y)); } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; const int MOD = 1000000007; const int INF = 0x3fffffff; typedef struct Node { long long v; int p; Node(long long v_, int p_) { v = v_; p = p_; } bool operator<(const Node& other) const { return v < other.v || (v == other.v && p > other.p); } } Node; long long a[N]; int main() { ios::sync_with_stdio(false); int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %I64d , &a[i]); a[i] += a[i - 1]; } priority_queue<Node> Q; Q.push(Node(a[n] - a[n - k], n + 1 - k)); long long ans = 0; int ansa, ansb; int q = n + 1 - k; for (int i = n + 1 - k - k; i > 0; --i) { if (ans <= Q.top().v + a[i + k - 1] - a[i - 1]) { ans = Q.top().v + a[i + k - 1] - a[i - 1]; ansa = i; ansb = Q.top().p; } --q; Q.push(Node(a[q + k - 1] - a[q - 1], q)); } printf( %d %d n , ansa, ansb); return 0; }
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// (c) Analog Devices Inc.
// ***************************************************************************
// ***************************************************************************
// Input must be RGB or CrYCb in that order, output is CrY/CbY
module cf_ss_444to422 (
clk,
s444_vs,
s444_hs,
s444_de,
s444_data,
s422_vs,
s422_hs,
s422_de,
s422_data);
input clk;
input s444_vs;
input s444_hs;
input s444_de;
input [23:0] s444_data;
output s422_vs;
output s422_hs;
output s422_de;
output [15:0] s422_data;
reg s444_vs_d = 'd0;
reg s444_hs_d = 'd0;
reg s444_de_d = 'd0;
reg [23:0] s444_data_d = 'd0;
reg s444_vs_2d = 'd0;
reg s444_hs_2d = 'd0;
reg s444_de_2d = 'd0;
reg [23:0] s444_data_2d = 'd0;
reg s444_vs_3d = 'd0;
reg s444_hs_3d = 'd0;
reg s444_de_3d = 'd0;
reg [23:0] s444_data_3d = 'd0;
reg [ 7:0] Cr = 'd0;
reg [ 7:0] Cb = 'd0;
reg Cr_Cb_sel = 'd0;
reg s422_vs = 'd0;
reg s422_hs = 'd0;
reg s422_de = 'd0;
reg [15:0] s422_data = 'd0;
wire [23:0] s444_data_s;
wire [ 9:0] Cr_s;
wire [ 9:0] Cb_s;
assign s444_data_s = (s444_de == 1'b1) ? s444_data : 24'd0;
always @(posedge clk) begin
s444_vs_d <= s444_vs;
s444_hs_d <= s444_hs;
s444_de_d <= s444_de;
s444_data_d <= s444_data_s;
s444_vs_2d <= s444_vs_d;
s444_hs_2d <= s444_hs_d;
s444_de_2d <= s444_de_d;
s444_data_2d <= s444_data_d;
s444_vs_3d <= s444_vs_2d;
s444_hs_3d <= s444_hs_2d;
s444_de_3d <= s444_de_2d;
s444_data_3d <= s444_data_2d;
end
assign Cr_s = {2'd0, s444_data_d[23:16]} + {2'd0, s444_data_3d[23:16]} +
{1'd0, s444_data_2d[23:16], 1'd0};
assign Cb_s = {2'd0, s444_data_d[7:0]} + {2'd0, s444_data_3d[7:0]} +
{1'd0, s444_data_2d[7:0], 1'd0};
always @(posedge clk) begin
Cr <= Cr_s[9:2];
Cb <= Cb_s[9:2];
if (s444_de_3d == 1'b1) begin
Cr_Cb_sel <= ~Cr_Cb_sel;
end else begin
Cr_Cb_sel <= 'd0;
end
end
always @(posedge clk) begin
s422_vs <= s444_vs_3d;
s422_hs <= s444_hs_3d;
s422_de <= s444_de_3d;
if (s444_de_3d == 1'b0) begin
s422_data <= 'd0;
end else if (Cr_Cb_sel == 1'b1) begin
s422_data <= {Cr, s444_data_3d[15:8]};
end else begin
s422_data <= {Cb, s444_data_3d[15:8]};
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR4B_PP_BLACKBOX_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[111111], b[111111]; vector<int> v; long long t[555][555]; int main() { int n; cin >> n; int r, c; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> t[i][j]; if (t[i][j] == 0) { r = i; c = j; } } } if (n == 1) { cout << 1 << endl; return 0; } long long sum = 0; if (r == 0) { for (int i = 0; i < n; i++) sum += t[1][i]; } else { for (int i = 0; i < n; i++) sum += t[0][i]; } long long lel = 0; for (int i = 0; i < n; i++) { lel += t[r][i]; } if (lel >= sum) { cout << -1 ; return 0; } t[r][c] = sum - lel; for (int i = 0; i < n; i++) { long long cur = 0; for (int j = 0; j < n; j++) { cur += t[i][j]; } if (cur != sum) { cout << -1 ; return 0; } } for (int i = 0; i < n; i++) { long long cur = 0; for (int j = 0; j < n; j++) { cur += t[j][i]; } if (cur != sum) { cout << -1 ; return 0; } } long long cur = 0; for (int i = 0; i < n; i++) { cur += t[i][i]; } if (cur != sum) { cout << -1 ; return 0; } cur = 0; for (int i = 0; i < n; i++) { cur += t[i][n - 1 - i]; } if (cur != sum) { cout << -1 ; return 0; } cout << t[r][c]; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); if (a == 0 && b == 0 && c == 0 && d == 0) { printf( 1 n ); } else if (a == 0 && d == 0 && c != 0) { printf( 0 n ); } else if (a != d) { printf( 0 n ); } else { printf( 1 n ); } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream &operator<<(ostream &os, const vector<T> &v) { for (T i : v) os << i << , ; return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &v) { for (T i : v) os << i << ; return os; } template <class T> ostream &operator<<(ostream &os, const multiset<T> &v) { for (T i : v) os << i << ; return os; } template <class T, class second> ostream &operator<<(ostream &os, const pair<T, second> &v) { os << v.first << << v.second; return os; } template <class T, class second> ostream &operator<<(ostream &os, const map<T, second> &v) { for (auto i : v) os << ( << i.first << => << i.second << ) << ; return os; } void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } void f1(string &s) { int n = s.length() + 1; vector<int> ans(n); int pos = 0, c = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == > ) pos = i + 1; } ans[pos] = ++c; if (pos > 1) { for (int i = pos - 2; i >= 0; i--) { if (s[i] == > ) { ans[i + 1] = ++c; if (i == 0) ans[i] = ++c; } } } set<int> to_do; while (c < n) to_do.insert(++c); for (int i = 1; i < n; i++) { if (s[i - 1] == > || ans[i] != 0) continue; int c = i; while (c < n && s[c - 1] == < ) c++; c--; while (c >= i) { ans[c] = *to_do.rbegin(); to_do.erase(--to_do.end()); c--; } } for (int i = 0; i < n; i++) if (ans[i] == 0) { ans[i] = *to_do.rbegin(); to_do.erase(--to_do.end()); } for (int i : ans) cout << i << ; cout << n ; } void f2(string &s) { int n = s.length() + 1; vector<int> ans(n); reverse(s.begin(), s.end()); int pos = 0, c = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == < ) pos = i + 1; } ans[pos] = ++c; if (pos > 1) { for (int i = pos - 2; i >= 0; i--) { if (s[i] == < ) { ans[i + 1] = ++c; } } } c = n; for (int i = n - 1; i >= 0; i--) if (ans[i] == 0) ans[i] = c--; reverse(ans.begin(), ans.end()); for (int i : ans) cout << i << ; cout << n ; } void solve() { int n; cin >> n; string s; cin >> s; f1(s); f2(s); } int main() { fast(); int t; cin >> t; while (t--) solve(); }
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long fpow(long long b, long long x) { long long res = 1; while (x) { if (x & 1) res = (res * b) % MOD; b = (b * b) % MOD; x >>= 1; } return res; } long long c(long long k, long long r) { if (r < 0) return 0; if (r == 0) return 1; return c(k, r - 1) * (k - r + 1) % MOD * fpow(r, MOD - 2) % MOD; } int main() { long long n, m, g; cin >> n >> m >> g; if (m == 1) { if (n & 1) { if (g) cout << (n - 1) / 2 << endl; else cout << (n - 1) / 2 + 2 << endl; } else { if (g) cout << n / 2 + 1 << endl; else cout << n / 2 << endl; } return 0; } if (m == 0) { if (g == !(n & 1)) printf( 1 n ); else printf( 0 n ); return 0; } if (n == 0) { if (g) printf( 0 n ); else printf( 1 n ); return 0; } long long k = 1 + g; long long C = c(n + m - k, m - 1); long long ans = C; for (k = k + 2; k <= n + 1; k += 2) { C = C * (n - k + 2) % MOD * (n - k + 3) % MOD * fpow(n + m - k + 2, MOD - 2) % MOD * fpow(n + m - k + 1, MOD - 2) % MOD; ans = (ans + C) % MOD; } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { return (b ? __gcd(a, b) : a); } template <typename T> T lcm(T a, T b) { return (a * (b / gcd(a, b))); } template <class T> ostream &operator<<(ostream &os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; return os << ] ; } template <class T> ostream &operator<<(ostream &os, set<T> S) { os << { ; for (auto s : S) os << s << ; return os << } ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream &operator<<(ostream &os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } const int N = 5e5 + 5; long long ar[N]; long long l[N], r[N], ans[N]; int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> ar[i]; vector<long long> lft(1, 0), rt(1, n + 1); for (int i = 1; i <= n; ++i) { while (ar[lft.back()] > ar[i]) { lft.pop_back(); } l[i] = l[lft.back()] + ar[i] * (i - lft.back()); lft.push_back(i); } for (int i = n; i; --i) { while (ar[rt.back()] > ar[i]) rt.pop_back(); r[i] = r[rt.back()] + ar[i] * (rt.back() - i); rt.push_back(i); } for (int i = 1; i <= n; ++i) { ans[i] = l[i] + r[i] - ar[i]; } long long maxa = max_element(ans + 1, ans + n + 1) - ans; for (int i = maxa - 1; i; --i) { if (ar[i] > ar[i + 1]) ar[i] = ar[i + 1]; } for (int i = maxa + 1; i <= n; ++i) if (ar[i - 1] < ar[i]) ar[i] = ar[i - 1]; for (int i = 1; i <= n; ++i) cout << ar[i] << ; cout << n ; return 0; }
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module CART_ROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("CART_ROM.mif"),
.C_INIT_FILE("CART_ROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 500043; const int K = 750; int a[N]; int sum[K][K]; int main() { int q; scanf( %d , &q); for (int i = 0; i < q; i++) { int t, x, y; scanf( %d %d %d , &t, &x, &y); if (t == 1) { a[x] += y; for (int i = 1; i < K; i++) sum[i][x % i] += y; } else { if (x >= K) { int ans = 0; for (int i = y; i <= 500000; i += x) ans += a[i]; printf( %d n , ans); } else printf( %d n , sum[x][y]); } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; string second; cin >> second; int mi = 0, gr = 0, le = 0, ans = 0; for (int i = 0; i < second.length(); i++) { if (second[i] == - ) mi++; else if (second[i] == > ) gr++; else le++; } if (mi == n || gr == n || le == n) { cout << n << endl; continue; } if (mi == 0 && gr && le) { cout << 0 << endl; continue; } if ((mi && gr && !le) || (mi && le && !gr)) { cout << n << endl; continue; } for (int i = 0; i < second.length(); i++) { if (second[i] == - || second[(i - 1 + n) % n] == - ) ans++; } cout << ans << endl; } return 0; }
|
// --------------------------------------------------------------------
// ng_INP Input Buffer Port
// --------------------------------------------------------------------
module ng_INP(
input CLK2, // AGC Main Clock
input NSA, // Stanby, negative logic
input [ 4:0] Keypad, // Keypad input port
input Keyready, // Signals a key value is ready
output [15:0] INP_BUS, // Input Port output
output KeyStrobe // Short key strobe output
);
assign INP_BUS = {2'b00, !NSA, 8'h00, Keypad};
//assign KeyStrobe = Keyready;
//-----------------------------------------------------------------------------
// Find Rising edge of Key ready line using a 3-bits shift register
// and syncronize it to the AGC main clock.
//-----------------------------------------------------------------------------
reg [2:0] DRedge;
always @(posedge CLK2) DRedge <= {DRedge[1:0], Keyready};
wire DR_risingedge = (DRedge[2:1] == 2'b01); // now we can detect DR rising edge
assign KeyStrobe = DR_risingedge;
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKBUFLP_BLACKBOX_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuflp (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int MAXL = 2000005; string pat[100005]; int beg[2000005]; int bel[2000005]; int id[4200000]; int L = 0; inline void modify(int a, int b, int val, int v = 1, int l = 1, int r = MAXL) { if (b < l || a > r) return; if (a <= l && r <= b) { id[v] = val; return; } int m = l + r >> 1; if (id[v]) id[v << 1] = id[v << 1 | 1] = id[v]; id[v] = 0; modify(a, b, val, v << 1, l, m); modify(a, b, val, v << 1 | 1, m + 1, r); return; } inline int query(int p, int v = 1, int l = 1, int r = MAXL) { if (p < l || p > r) return 0; if (id[v]) return id[v]; if (l == r) return 0; int m = l + r >> 1; return max(query(p, v << 1, l, m), query(p, v << 1 | 1, m + 1, r)); } int cnt = 0; int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> pat[i]; int len = pat[i].size(); int m; cin >> m; while (m--) { cin >> beg[++cnt]; bel[cnt] = i; modify(beg[cnt], beg[cnt] + len - 1, cnt); L = max(L, beg[cnt] + len - 1); } } for (int i = 1; i <= L; ++i) { int q = query(i); if (!q) cout << a ; else { cout << pat[bel[q]][i - beg[q]]; } } cout << endl; return 0; }
|
/*
Anthony De Caria - June 15, 2014
This module is the structure that interfaces NIOS-II with two AD7264 A-D-Cs.
This is done using SPI protocol.
It takes key signals from NIOS (CPOL, CPHA, ss), and transforms them into SCLK and SS signals.
In addition, it also creates the structures needed to collect and transmit data to and from the AD7264s
A 16-bit serializer for transmitting.
And two 14-bit deserializers for recieveing (the AD7264 is dual channel).
*/
module ADCConnector (SPIClock, resetn,
CPOL, CPHA, ss,
SCLK, SS, MOSI1, MISO1A, MISO1B, MOSI2, MISO2A, MISO2B,
DOM1, DIM1A, DIM1B, DOM2, DIM2A, DIM2B,
DOL1, DOL2, ready, loaded1, loaded2);
/*
I/Os
*/
// General I/Os //
input SPIClock;
input resetn;
// CPU I/Os //
input CPOL;
input CPHA;
input ss;
input DOL1;
input DOL2;
output ready;
output loaded1;
output loaded2;
// Data I/Os //
// Note: DOM lines are the lines that have data to be sent out. //
// While DIM lines are the lines that have data for NIOS. //
input [15:0]DOM1;
output [13:0]DIM1A;
output [13:0]DIM1B;
input [15:0]DOM2;
output [13:0]DIM2A;
output [13:0]DIM2B;
// SPI I/Os //
output SCLK;
output SS;
output MOSI1;
input MISO1A;
input MISO1B;
output MOSI2;
input MISO2A;
input MISO2B;
// Intra-Connector wires //
wire [5:0] master_counter_bit;
wire Des_en, Ser_en;
wire A1, B1, A2, B2, O1, O2;
wire [15:0] o1, o2;
wire RS;
// Early assignments //
assign SS = ss;
assign Ser_en = ~master_counter_bit[5] & ~master_counter_bit[4];
assign Des_en = (~master_counter_bit[5] & master_counter_bit[4] & (master_counter_bit[3] | master_counter_bit[2] | master_counter_bit[1] & master_counter_bit[0]) ) | (master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & ~master_counter_bit[0]);
assign ready = master_counter_bit[5];
assign loaded1 = (o1 == DOM1)? 1'b1: 1'b0;
// assign loaded2 = (o2 == DOM2)? 1'b1: 1'b0;
assign loaded2 = 1'b1;
assign O1 = o1[15];
assign O2 = o2[15];
/*
Counter
This is the counter that will be used to pace out the sending out and receiving parts of the
*/
SixBitCounterAsync PocketWatch(
.clk(SPIClock),
.resetn(resetn & ~SS),
.enable(~SS & ~(master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & master_counter_bit[0]) ),
.q(master_counter_bit)
);
/*
Signal Makers
*/
SCLKMaker TimeLord(
.Clk(SPIClock),
.S(ss),
.CPOL(CPOL),
.SCLK(SCLK)
);
SPIRSMaker Level(
.CPHA(CPHA),
.CPOL(CPOL),
.RS(RS)
);
/*
Serializers
*/
ShiftRegisterWEnableSixteenAsyncMuxedInput OutBox1(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Ser_en),
.select(DOL1),
.d(DOM1),
.q(o1)
);
/*
Deserializers
*/
ShiftRegisterWEnableFourteen InBox1A(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Des_en),
.d(A1),
.q(DIM1A)
);
ShiftRegisterWEnableFourteen InBox1B(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Des_en),
.d(B1),
.q(DIM1B)
);
/*
Tri-state buffers
*/
TriStateBuffer BorderGuardOut1(
.In(O1),
.Select(Ser_en),
.Out(MOSI1)
);
TriStateBuffer BorderGuardIn1A(
.In(MISO1A),
.Select(Des_en),
.Out(A1)
);
TriStateBuffer BorderGuardIn1B(
.In(MISO1B),
.Select(Des_en),
.Out(B1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:36777216 ) #pragma GCC optimize( O2 ) template <class T> inline void RD(T &); template <class T> inline void OT(const T &); inline int RD() { int x; RD(x); return x; } template <class T> inline T &_RD(T &x) { RD(x); return x; } inline void RC(char &c) { scanf( %c , &c); } inline void RS(char *s) { scanf( %s , s); } template <class T0, class T1> inline void RD(T0 &x0, T1 &x1) { RD(x0), RD(x1); } template <class T0, class T1, class T2> inline void RD(T0 &x0, T1 &x1, T2 &x2) { RD(x0), RD(x1), RD(x2); } template <class T0, class T1, class T2, class T3> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3) { RD(x0), RD(x1), RD(x2), RD(x3); } template <class T0, class T1, class T2, class T3, class T4> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void RD(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5, T6 &x6) { RD(x0), RD(x1), RD(x2), RD(x3), RD(x4), RD(x5), RD(x6); } template <class T0, class T1> inline void OT(T0 &x0, T1 &x1) { OT(x0), OT(x1); } template <class T0, class T1, class T2> inline void OT(T0 &x0, T1 &x1, T2 &x2) { OT(x0), OT(x1), OT(x2); } template <class T0, class T1, class T2, class T3> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3) { OT(x0), OT(x1), OT(x2), OT(x3); } template <class T0, class T1, class T2, class T3, class T4> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void OT(T0 &x0, T1 &x1, T2 &x2, T3 &x3, T4 &x4, T5 &x5, T6 &x6) { OT(x0), OT(x1), OT(x2), OT(x3), OT(x4), OT(x5), OT(x6); } template <class T> inline void RST(T &A) { memset(A, 0, sizeof(A)); } template <class T0, class T1> inline void RST(T0 &A0, T1 &A1) { RST(A0), RST(A1); } template <class T0, class T1, class T2> inline void RST(T0 &A0, T1 &A1, T2 &A2) { RST(A0), RST(A1), RST(A2); } template <class T0, class T1, class T2, class T3> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { RST(A0), RST(A1), RST(A2), RST(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void RST(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { RST(A0), RST(A1), RST(A2), RST(A3), RST(A4), RST(A5), RST(A6); } template <class T> inline void CLR(T &A) { A.clear(); } template <class T0, class T1> inline void CLR(T0 &A0, T1 &A1) { CLR(A0), CLR(A1); } template <class T0, class T1, class T2> inline void CLR(T0 &A0, T1 &A1, T2 &A2) { CLR(A0), CLR(A1), CLR(A2); } template <class T0, class T1, class T2, class T3> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { CLR(A0), CLR(A1), CLR(A2), CLR(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void CLR(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { CLR(A0), CLR(A1), CLR(A2), CLR(A3), CLR(A4), CLR(A5), CLR(A6); } template <class T> inline void CLR(T &A, int n) { for (int i = 0; i < int(n); ++i) CLR(A[i]); } template <class T> inline void FLC(T &A, int x) { memset(A, x, sizeof(A)); } template <class T0, class T1> inline void FLC(T0 &A0, T1 &A1, int x) { FLC(A0, x), FLC(A1, x); } template <class T0, class T1, class T2> inline void FLC(T0 &A0, T1 &A1, T2 &A2) { FLC(A0), FLC(A1), FLC(A2); } template <class T0, class T1, class T2, class T3> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3) { FLC(A0), FLC(A1), FLC(A2), FLC(A3); } template <class T0, class T1, class T2, class T3, class T4> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4); } template <class T0, class T1, class T2, class T3, class T4, class T5> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4), FLC(A5); } template <class T0, class T1, class T2, class T3, class T4, class T5, class T6> inline void FLC(T0 &A0, T1 &A1, T2 &A2, T3 &A3, T4 &A4, T5 &A5, T6 &A6) { FLC(A0), FLC(A1), FLC(A2), FLC(A3), FLC(A4), FLC(A5), FLC(A6); } template <class T> inline void SRT(T &A) { sort(A.begin(), A.end()); } template <class T, class C> inline void SRT(T &A, C B) { sort(A.begin(), A.end(), B); } const int MOD = 1000000007; const int INF = 0x7fffffff; const double EPS = 1e-6; const double OO = 1e15; const double PI = acos(-1.0); template <class T> inline void checkMin(T &a, const T b) { if (b < a) a = b; } template <class T> inline void checkMax(T &a, const T b) { if (b > a) a = b; } template <class T, class C> inline void checkMin(T &a, const T b, C c) { if (c(b, a)) a = b; } template <class T, class C> inline void checkMax(T &a, const T b, C c) { if (c(a, b)) a = b; } template <class T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <class T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <class T> inline T sqr(T a) { return a * a; } template <class T> inline T cub(T a) { return a * a * a; } int Ceil(int x, int y) { return (x - 1) / y + 1; } inline bool _1(int x, int i) { return x & 1 << i; } inline int _1(int i) { return 1 << i; } inline int _U(int i) { return _1(i) - 1; }; inline int count_bits(int x) { x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); x = (x & 0x0f0f0f0f) + ((x & 0xf0f0f0f0) >> 4); x = (x & 0x00ff00ff) + ((x & 0xff00ff00) >> 8); x = (x & 0x0000ffff) + ((x & 0xffff0000) >> 16); return x; } template <class T> inline T low_bit(T x) { return x & -x; } template <class T> inline T high_bit(T x) { T p = low_bit(x); while (p != x) x -= p, p = low_bit(x); return p; } inline void INC(int &a, int b) { a += b; if (a >= MOD) a -= MOD; } inline int sum(int a, int b) { a += b; if (a >= MOD) a -= MOD; return a; } inline void DEC(int &a, int b) { a -= b; if (a < 0) a += MOD; } inline int dff(int a, int b) { a -= b; if (a < 0) a += MOD; return a; } inline void MUL(int &a, int b) { a = int((long long)a * b % MOD); } inline int pdt(int a, int b) { return int((long long)a * b % MOD); } template <class T> inline void RD(T &x) { char c; for (c = getchar(); c < 0 ; c = getchar()) ; x = c - 0 ; for (c = getchar(); c >= 0 ; c = getchar()) x = x * 10 + c - 0 ; } int ____Case; template <class T> inline void OT(const T &x) { printf( %d n , x); } const int dx[] = {-1, -1, -1, 0, 0, 1, 1, 1}, dy[] = {-1, 0, 1, -1, 1, -1, 0, 1}; char reverse_bits(char x) { x = ((x >> 1) & 0x55) | ((x << 1) & 0xaa); x = ((x >> 2) & 0x33) | ((x << 2) & 0xcc); x = ((x >> 4) & 0x0f) | ((x << 4) & 0xf0); return x; } const int N = 8; string s; int main() { unsigned char cur, last = 0; getline(cin, s); for (int i = 0; i < int(int(s.size())); ++i) { last = reverse_bits(last); cur = s[i], cur = reverse_bits(cur); cur = (last - cur + 256) % 256, last = s[i]; cout << (unsigned int)(cur) << endl; } }
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#include <bits/stdc++.h> using namespace std; const int maxn = 300050; int a[maxn << 2]; int ll[maxn], rr[maxn], x[maxn], N, M; void getdown(int cur) { a[cur << 1] = a[cur]; a[(cur << 1) | 1] = a[cur]; a[cur] = 0; } void Insert(int cur, int L, int R, int l, int r, int u) { int mid = (L + R) >> 1; if (l <= L && R <= r) { a[cur] = u; return; } if (a[cur]) getdown(cur); if (l <= mid) Insert(((cur) << 1), L, mid, l, r, u); if (r > mid) Insert((((cur) << 1) | 1), (mid + 1), R, l, r, u); } int Query(int cur, int L, int R, int p) { int mid = (L + R) >> 1; if (a[cur]) return a[cur]; if (L == R) return a[cur]; if (p <= mid) return Query(((cur) << 1), L, mid, p); else return Query((((cur) << 1) | 1), (mid + 1), R, p); } int main() { scanf( %d%d , &N, &M); for (int i = 1; i <= M; i++) { scanf( %d%d%d , &ll[i], &rr[i], &x[i]); } for (int i = M; i >= 1; i--) { if (ll[i] < x[i]) Insert(1, 1, N, ll[i], x[i] - 1, x[i]); if (x[i] < rr[i]) Insert(1, 1, N, x[i] + 1, rr[i], x[i]); } printf( %d , Query(1, 1, N, 1)); for (int i = 2; i <= N; i++) printf( %d , Query(1, 1, N, i)); printf( n ); return 0; }
|
`timescale 1 ps / 1 ps
module system_wrapper
(AC_BCLK,
AC_MCLK,
AC_MUTE_N,
AC_PBLRC,
AC_RECLRC,
AC_SDATA_I,
AC_SDATA_O,
BLUE_O,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GREEN_O,
HDMI_CLK_N,
HDMI_CLK_P,
HDMI_D0_N,
HDMI_D0_P,
HDMI_D1_N,
HDMI_D1_P,
HDMI_D2_N,
HDMI_D2_P,
HDMI_OEN,
HSYNC_O,
RED_O,
VSYNC_O,
btns_4bits_tri_i,
iic_0_scl_io,
iic_0_sda_io,
leds_4bits_tri_o,
sws_4bits_tri_i);
output [0:0]AC_BCLK;
output AC_MCLK;
output [0:0]AC_MUTE_N;
output [0:0]AC_PBLRC;
output [0:0]AC_RECLRC;
input AC_SDATA_I;
output [0:0]AC_SDATA_O;
output [4:0]BLUE_O;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output [5:0]GREEN_O;
output HDMI_CLK_N;
output HDMI_CLK_P;
output HDMI_D0_N;
output HDMI_D0_P;
output HDMI_D1_N;
output HDMI_D1_P;
output HDMI_D2_N;
output HDMI_D2_P;
output [0:0]HDMI_OEN;
output HSYNC_O;
output [4:0]RED_O;
output VSYNC_O;
input [3:0]btns_4bits_tri_i;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]leds_4bits_tri_o;
input [3:0]sws_4bits_tri_i;
wire [0:0]AC_BCLK;
wire AC_MCLK;
wire [0:0]AC_MUTE_N;
wire [0:0]AC_PBLRC;
wire [0:0]AC_RECLRC;
wire AC_SDATA_I;
wire [0:0]AC_SDATA_O;
wire [4:0]BLUE_O;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [5:0]GREEN_O;
wire HDMI_CLK_N;
wire HDMI_CLK_P;
wire HDMI_D0_N;
wire HDMI_D0_P;
wire HDMI_D1_N;
wire HDMI_D1_P;
wire HDMI_D2_N;
wire HDMI_D2_P;
wire [0:0]HDMI_OEN;
wire HSYNC_O;
wire [4:0]RED_O;
wire VSYNC_O;
wire [3:0]btns_4bits_tri_i;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]leds_4bits_tri_o;
wire [3:0]sws_4bits_tri_i;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
system system_i
(.AC_BCLK(AC_BCLK),
.AC_MCLK(AC_MCLK),
.AC_MUTE_N(AC_MUTE_N),
.AC_PBLRC(AC_PBLRC),
.AC_RECLRC(AC_RECLRC),
.AC_SDATA_I(AC_SDATA_I),
.AC_SDATA_O(AC_SDATA_O),
.BLUE_O(BLUE_O),
.BTNs_4Bits_tri_i(btns_4bits_tri_i),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GREEN_O(GREEN_O),
.HDMI_CLK_N(HDMI_CLK_N),
.HDMI_CLK_P(HDMI_CLK_P),
.HDMI_D0_N(HDMI_D0_N),
.HDMI_D0_P(HDMI_D0_P),
.HDMI_D1_N(HDMI_D1_N),
.HDMI_D1_P(HDMI_D1_P),
.HDMI_D2_N(HDMI_D2_N),
.HDMI_D2_P(HDMI_D2_P),
.HDMI_OEN(HDMI_OEN),
.HSYNC_O(HSYNC_O),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.LEDs_4Bits_tri_o(leds_4bits_tri_o),
.RED_O(RED_O),
.SWs_4Bits_tri_i(sws_4bits_tri_i),
.VSYNC_O(VSYNC_O));
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Simple FML interface for HPDMC */
module hpdmc_busif #(
parameter sdram_depth = 26
) (
input sys_clk,
input sdram_rst,
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
output mgmt_stb,
output mgmt_we,
output [sdram_depth-3-1:0] mgmt_address, /* in 64-bit words */
input mgmt_ack,
input data_ack
);
reg mgmt_stb_en;
assign mgmt_stb = fml_stb & mgmt_stb_en;
assign mgmt_we = fml_we;
assign mgmt_address = fml_adr[sdram_depth-1:3];
assign fml_ack = data_ack;
always @(posedge sys_clk) begin
if(sdram_rst)
mgmt_stb_en = 1'b1;
else begin
if(mgmt_ack)
mgmt_stb_en = 1'b0;
if(data_ack)
mgmt_stb_en = 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Point { int x, y; Point(int x0, int y0) : x(x0), y(y0) {} Point() : x(0), y(0) {} }; int t; int dx[] = {-1, 0, 1, 0, -1, -1, 1, 1}; int dy[] = {0, -1, 0, 1, -1, 1, -1, 1}; int n, m; long long maxx; int d[100005][4]; int a[100005], h[100005]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> a[i] >> h[i]; } memset(d, 0, sizeof(d)); d[0][0] = 1; d[0][1] = 0; if (a[1] - a[0] > h[1]) d[0][2] = 1; else d[0][2] = 0; int res = 1; for (int i = 1; i < n; i++) { int dis = a[i] - a[i - 1]; if (h[i] < dis) d[i][0] = max(d[i - 1][0] + 1, d[i - 1][1] + 1); if (h[i] + h[i - 1] < dis) d[i][0] = max(d[i][0], d[i - 1][2] + 1); d[i][1] = max(d[i - 1][0], d[i - 1][1]); if (h[i - 1] < dis) d[i][1] = max(d[i][1], d[i - 1][2]); if (h[i] < a[i + 1] - a[i] || i == n - 1) d[i][2] = max(d[i - 1][0] + 1, d[i - 1][1] + 1); if (h[i - 1] < dis) d[i][2] = max(d[i][2], d[i - 1][2] + 1); res = max(res, max(d[i][0], max(d[i][1], d[i][2]))); } cout << res; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_center_3inv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gclk_center_3inv(jbus_out ,ddr_out ,cmp_out ,jbus_in ,
ddr_in ,cmp_in );
output jbus_out ;
output ddr_out ;
output cmp_out ;
input jbus_in ;
input ddr_in ;
input cmp_in ;
bw_clk_gclk_inv_224x xddr (
.clkout (ddr_out ),
.clkin (ddr_in ) );
bw_clk_gclk_inv_224x xjbus (
.clkout (jbus_out ),
.clkin (jbus_in ) );
bw_clk_gclk_inv_224x xcmp (
.clkout (cmp_out ),
.clkin (cmp_in ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); template <typename T, typename U> inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> inline void amax(T &x, U y) { if (x < y) x = y; } using namespace std; int main() { int n, m; cin >> n >> m; string grid[n]; for (int i = 0; i < n; ++i) { cin >> grid[i]; } int left[n][m], right[n][m], top[n][m], bottom[n][m]; memset(left, (0), sizeof(left)); memset(right, (0), sizeof(right)); memset(top, (0), sizeof(top)); memset(bottom, (0), sizeof(bottom)); for (int i = 1; i < n; ++i) { for (int j = 1; j < m; ++j) { if (grid[i][j] != * ) continue; left[i][j] = left[i][j - 1]; top[i][j] = top[i - 1][j]; if (grid[i][j - 1] == * ) left[i][j] = left[i][j - 1] + 1; if (grid[i - 1][j] == * ) top[i][j] = top[i - 1][j] + 1; } } for (int i = n - 2; i >= 0; --i) { for (int j = m - 2; j >= 0; --j) { if (grid[i][j] != * ) continue; if (grid[i][j + 1] == * ) right[i][j] = right[i][j + 1] + 1; if (grid[i + 1][j] == * ) bottom[i][j] = bottom[i + 1][j] + 1; } } bool marked[n][m]; memset(marked, (false), sizeof(marked)); vector<int> row, col, sz; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (grid[i][j] != * ) continue; int cnt1 = min(left[i][j], right[i][j]); int cnt2 = min(top[i][j], bottom[i][j]); int cnt = min(cnt1, cnt2); if (cnt != 0) { row.push_back(i + 1); col.push_back(j + 1); sz.push_back(cnt); marked[i][j] = true; for (int k = 1; k <= cnt; ++k) { marked[i][j - k] = true; marked[i][j + k] = true; marked[i - k][j] = true; marked[i + k][j] = true; } } } } bool pos = true; for (int l = 0; l < n; ++l) { for (int j = 0; j < m; ++j) { if (grid[l][j] == * && !marked[l][j]) { pos = false; break; } } } if (pos) { cout << row.size() << n ; for (int i = 0; i < row.size(); ++i) { cout << row[i] << << col[i] << << sz[i] << n ; } } else { cout << -1 n ; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_TB_V
`define SKY130_FD_SC_LP__FAHCON_TB_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fahcon.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT_N;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CI = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CI = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CI = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CI = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__fahcon dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT_N(COUT_N), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_TB_V
|
#include <bits/stdc++.h> using namespace std; using Vi = vector<int>; using i64 = long long; using ll = long long; using Pi = pair<int, int>; mt19937 mrand(time(0)); int rnd(int x) { return mrand() % x; } const int N = 500005; const int M = 40005; int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) { int n; cin >> n; Vi a(n); for (int i = 0; i < n; ++i) cin >> a[i]; int TOP = 30; Vi bit(TOP); for (int i = 0; i < n; ++i) for (int j = 0; j < TOP; ++j) if (a[i] >> j & 1) ++bit[j]; Vi ans(n + 1); for (int i = 0; i < TOP; ++i) for (int j = 1; j < n + 1; ++j) if (bit[i] % j == 0) ++ans[j]; for (int i = 1; i < n + 1; ++i) if (ans[i] == TOP) cout << i << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename X> void MA(X& a, X b) { a = max(a, b); } template <typename X> void MI(X& a, X b) { a = min(a, b); } template <typename X> void clr(X& x, int a) { memset(x, a, sizeof(x)); }; int cond = 0, multi = 0, gcj = 0; int N; const int MAXN = 111; vector<array<int, 2> > ED[MAXN]; long double wsp[MAXN]; array<int, 3> res[MAXN]; int numkr = 0; void go(int u, int p, long double val) { int kr = 0; kr += ED[u].size(); { if (cond) cerr << 38 << << u << << kr << << val << << u << << kr << << val << endl; }; val += 2.0 / kr; while (val >= 2.0) val -= 2.0; for (array<int, 2> ed : ED[u]) if (ed[0] != p) { int v = ed[0]; int idx = ed[1]; { if (cond) cerr << 45 << << u << << v << << val << << u << << v << << val << endl; }; go(v, u, 1 + val); if (val <= 1.0) { res[numkr] = array<int, 3>({v, u, idx}); wsp[numkr] = 1.0 - val; } else { res[numkr] = array<int, 3>({u, v, idx}); wsp[numkr] = 2.0 - val; } numkr++; val += 2.0 / kr; while (val >= 2.0) val -= 2.0; } } void solve() { cin >> N; for (auto i = (1); i <= (N - 1); ++i) { int u, v; cin >> u >> v; ED[u].push_back(array<int, 2>({v, i})); ED[v].push_back(array<int, 2>({u, i})); } go(1, -1, 0); cout << N - 1 << n ; for (auto i = 0; i < (N - 1); ++i) { cout << 1 << << res[i][2] << << res[i][0] << << res[i][1] << << wsp[i] << n ; } } int main(int argc, char** argv) { ios::sync_with_stdio(false), cin.tie(0), cond = argc >= 2 && argv[1][0] == q ? 1 << 30 : 0; cout.setf(ios::fixed), cout.precision(10); int t; if (multi || gcj) cin >> t; else t = 1; for (auto i = (1); i <= (t); ++i) { if (cond) cerr << 84 << << i << endl; if (gcj) cout << Case # << i << : ; solve(); } return 0; }
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
// Note: the definitions here are without shifts
// Commands:
`define FPGA_CMD_SET_CONFREG 1
`define FPGA_CMD_TRACE_ENABLE 2
// Major modes:
`define FPGA_MAJOR_MODE_LF_ADC 0
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
`define FPGA_MAJOR_MODE_HF_READER 0
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
`define FPGA_MAJOR_MODE_HF_SNOOP 3
`define FPGA_MAJOR_MODE_HF_GET_TRACE 4
`define FPGA_MAJOR_MODE_OFF 7
// Options for the generic HF reader
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
`define FPGA_HF_READER_MODE_SEND_JAM 8
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
// Options for the HF simulated tag, how to modulate
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
// Options for ISO14443A
`define FPGA_HF_ISO14443A_SNIFFER 0
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
`define FPGA_HF_ISO14443A_READER_LISTEN 3
`define FPGA_HF_ISO14443A_READER_MOD 4
`include "hi_reader.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "hi_get_trace.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [8:0] conf_word;
reg trace_enable;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
// select module (outputs) based on major mode
wire [2:0] major_mode = conf_word[8:6];
// configuring the HF reader
wire [1:0] subcarrier_frequency = conf_word[5:4];
wire [3:0] minor_mode = conf_word[3:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_reader hr(
ck_1356megb,
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
adc_d, hr_adc_clk,
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
hr_dbg,
subcarrier_frequency, minor_mode
);
hi_simulate hs(
ck_1356meg,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
hs_dbg,
minor_mode
);
hi_iso14443a hisn(
ck_1356meg,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
hisn_dbg,
minor_mode
);
hi_sniffer he(
ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, he_ssp_clk
);
hi_get_trace gt(
ck_1356megb,
adc_d, trace_enable, major_mode,
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
);
// Major modes:
// 000 -- HF reader; subcarrier frequency and modulation depth selectable
// 001 -- HF simulated tag
// 010 -- HF ISO14443-A
// 011 -- HF Snoop
// 100 -- HF get trace
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, gt_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, gt_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
// not used
assign miso = 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int a[25][25], n, m, dp[1 << 22]; char s[25][222]; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %s , s[i]); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) scanf( %d , &a[i][j]); memset(dp, 63, sizeof(dp)), dp[0] = 0; for (int l, msk = 0; msk < (1 << n); ++msk) { for (int b = 0; b < n; ++b) if (!(msk & (1 << b))) { l = b; break; } for (int c = 0; c < m; ++c) { dp[msk + (1 << l)] = min(dp[msk + (1 << l)], dp[msk] + a[l][c]); int t = 0, h = 0, tmsk = msk; for (int i = 0; i < n; ++i) if (s[i][c] == s[l][c]) tmsk |= (1 << i), t += a[i][c], h = max(h, a[i][c]); dp[tmsk] = min(dp[tmsk], dp[msk] + t - h); } } printf( %d n , dp[(1 << n) - 1]); }
|
module test_round_robin();
reg[39:0] queue_vfull;
reg icache_ack;
reg[39:0] vacant;
reg clk, rst;
wire fetch_valid;
wire[5:0] pc_select;
round_robin rr(fetch_valid, pc_select, queue_vfull, icache_ack, vacant, clk, rst);
initial begin
clk = 0;
while (1) begin
#2;
clk = ~clk;
end
end
initial begin
rst <= 1;
icache_ack <= 0;
queue_vfull <= 40'hffffffffff;
vacant <= 40'hffffffffff;
#20;
rst = 0;
#10;
queue_vfull <= 40'hffffffff43;
vacant <= 40'hffffffff51;
#150;
icache_ack = 1;
end
initial begin
#200
$finish;
end
always @ (posedge clk) begin
if (!rst) begin
$display ("Time= %g : Fetch_valid= %b : PC_select= %b", $time, fetch_valid, pc_select);
$display ("QF: %b", queue_vfull);
$display ("VC: %b", vacant);
$display ("NF: %b", rr.valid_queues_not_full);
$display ("SQ: %b", rr.shifted_queue);
$display ("HP_in= %d : HP_out = %d : PR_enc_out= %b", rr.highest_pr_in, rr.highest_pr_out, rr.prenc_out);
$display ("IC_in= %d : IC_out = %d", rr.icache_req_in, rr.icache_req_out);
$display ("IC_p1= %d : IC_m1 = %d", rr.icache_req_plus1, rr.icache_req_minus1);
$display ("-----------------------------------------------------------");
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 5;
localparam DW = DATA_WIDTH - 1;
localparam AW = ADDR_WIDTH - 1;
input clka;
input wea;
input [AW:0] addra;
input [DW:0] dina;
input clkb;
input [AW:0] addrb;
output [DW:0] doutb;
reg [DW:0] m_ram[0:((2**ADDR_WIDTH)-1)];
reg [DW:0] doutb;
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
doutb <= m_ram[addrb];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Clock and Reset
//
// File : alt_ddrx_clock_and_reset.v
//
// Abstract : Clock and reset
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_clock_and_reset #
( parameter
CTL_RESET_SYNC_STAGES = 4,
CTL_NUM_RESET_OUTPUT = 1,
CTL_HALF_RESET_SYNC_STAGES = 4,
CTL_HALF_NUM_RESET_OUTPUT = 1
)
(
// Inputs
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
// Outputs
resynced_ctl_reset_n,
resynced_ctl_half_clk_reset_n
);
// Inputs
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
// Outputs
output [CTL_NUM_RESET_OUTPUT - 1 : 0] resynced_ctl_reset_n;
output [CTL_HALF_NUM_RESET_OUTPUT - 1 : 0] resynced_ctl_half_clk_reset_n;
alt_ddrx_reset_sync #(
.RESET_SYNC_STAGES (CTL_RESET_SYNC_STAGES),
.NUM_RESET_OUTPUT (CTL_NUM_RESET_OUTPUT)
) reset_sync_inst (
.reset_n (ctl_reset_n),
.clk (ctl_clk),
.reset_n_sync (resynced_ctl_reset_n)
);
alt_ddrx_reset_sync #(
.RESET_SYNC_STAGES (CTL_HALF_RESET_SYNC_STAGES),
.NUM_RESET_OUTPUT (CTL_HALF_NUM_RESET_OUTPUT)
) half_reset_sync_inst (
.reset_n (ctl_half_clk_reset_n),
.clk (ctl_half_clk),
.reset_n_sync (resynced_ctl_half_clk_reset_n)
);
endmodule
//--------------------------------------------------------------------------------------------------------------------//
//
// Important Note: The following code was copied from //acds/main/quartus/iptcl/memphy/rtl/phy/reset_sync.v
// Code is added to remove recovery failures on reset net for HCx. In HCx global network,
// there is significant insertion delay (not a problem in FPGA global network)
//
//--------------------------------------------------------------------------------------------------------------------//
module alt_ddrx_reset_sync #
( parameter
RESET_SYNC_STAGES = 4,
NUM_RESET_OUTPUT = 1
)
(
reset_n,
clk,
reset_n_sync
);
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
//USER identify the synchronizer chain so that Quartus can analyze metastability.
//USER Since these resets are localized to the PHY alone, make them routed locally
//USER to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
//--------------------------------------------------------------------------------------------------------------------//
//
// End
//
//--------------------------------------------------------------------------------------------------------------------//
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 110000; int n, m, h; int head[maxn], num; struct road { int to, next; } edge[maxn * 2]; void add(int u, int v) { edge[num].to = v; edge[num].next = head[u]; head[u] = num++; } int dfn[maxn], low[maxn], block[maxn]; int id, cnt, vis[maxn], numxx[maxn]; int out[maxn]; stack<int> q; void dfs(int u, int fa) { dfn[u] = low[u] = ++id; q.push(u); vis[u] = 1; for (int i = head[u]; i != -1; i = edge[i].next) { int v = edge[i].to; if (!dfn[v]) { dfs(v, u); low[u] = min(low[v], low[u]); } else if (vis[v]) low[u] = min(low[u], dfn[v]); } if (dfn[u] == low[u]) { cnt++; int v; do { v = q.top(); vis[v] = 0; q.pop(); block[v] = cnt; numxx[cnt]++; } while (v != u); } } int tim[maxn]; void init() { id = num = cnt = 0; memset(dfn, 0, sizeof(dfn)); memset(low, 0, sizeof(low)); memset(edge, 0, sizeof(edge)); memset(numxx, 0, sizeof(numxx)); memset(block, 0, sizeof(block)); memset(vis, 0, sizeof(vis)); while (!q.empty()) q.pop(); memset(head, -1, sizeof(head)); memset(out, 0, sizeof(out)); } int main() { while (scanf( %d%d%d , &n, &m, &h) != EOF) { init(); for (int i = 1; i <= n; i++) { scanf( %d , &tim[i]); } for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); if ((tim[a] + 1) % h == tim[b]) add(a, b); if ((tim[b] + 1) % h == tim[a]) add(b, a); } for (int i = 1; i <= n; i++) { if (!dfn[i]) dfs(i, -1); } for (int i = 1; i <= n; i++) { for (int j = head[i]; j != -1; j = edge[j].next) { int v = edge[j].to; if (block[v] != block[i]) { out[block[i]]++; } } } int ans = INF; int flag = 0; for (int i = 1; i <= cnt; i++) { if (out[i] == 0) { if (ans > numxx[i]) { ans = numxx[i]; flag = i; } } } cout << ans << endl; for (int i = 1; i <= n; i++) { int putt = 0; if (block[i] == flag) { ans--; putt = 1; } if (ans != 0 && putt == 1) cout << i << ; else if (ans == 0 && putt == 1) cout << i << endl; } } }
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt10_adpcm_cnt(
input rst_n,
input clk, // CPU clock
input cen, // 666 kHz
// pipeline channel
input [ 5:0] cur_ch,
input [ 5:0] en_ch,
// Address writes from CPU
input [15:0] addr_in,
input [ 2:0] addr_ch,
input up_start,
input up_end,
// Counter control
input aon,
input aoff,
// ROM driver
output [19:0] addr_out,
output [ 3:0] bank,
output sel,
output roe_n,
output decon,
output clr, // inform the decoder that a new section begins
// Flags
output reg [ 5:0] flags,
input [ 5:0] clr_flags,
//
output [15:0] start_top,
output [15:0] end_top
);
reg [20:0] addr1, addr2, addr3, addr4, addr5, addr6;
reg [3:0] bank1, bank2, bank3, bank4, bank5, bank6;
reg [11:0] start1, start2, start3, start4, start5, start6,
end1, end2, end3, end4, end5, end6;
reg on1, on2, on3, on4, on5, on6;
reg done5, done6, done1;
reg [5:0] done_sr, zero;
reg roe_n1, decon1;
reg clr1, clr2, clr3, clr4, clr5, clr6;
reg skip1, skip2, skip3, skip4, skip5, skip6;
// All outputs from stage 1
assign addr_out = addr1[20:1];
assign sel = addr1[0];
assign bank = bank1;
assign roe_n = roe_n1;
assign clr = clr1;
assign decon = decon1;
// Two cycles early: 0 0 1 1 2 2 3 3 4 4 5 5
wire active5 = (en_ch[1] && cur_ch[4]) || (en_ch[2] && cur_ch[5]) || (en_ch[2] && cur_ch[0]) || (en_ch[3] && cur_ch[1]) || (en_ch[4] && cur_ch[2]) || (en_ch[5] && cur_ch[3]);//{ cur_ch[3:0], cur_ch[5:4] } == en_ch;
wire sumup5 = on5 && !done5 && active5;
reg sumup6;
reg [5:0] last_done, set_flags;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
zero <= 6'd1;
done_sr <= ~6'd0;
last_done <= ~6'd0;
end else if(cen) begin
zero <= { zero[0], zero[5:1] };
done_sr <= { done1, done_sr[5:1]};
if( zero[0] ) begin
last_done <= done_sr;
set_flags <= ~last_done & done_sr;
end
end
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
flags <= 6'd0;
end else begin
flags <= ~clr_flags & (set_flags | flags);
end
`ifdef SIMULATION
wire [11:0] addr1_cmp = addr1[20:9];
`endif
assign start_top = {bank1, start1};
assign end_top = {bank1, end1};
reg [5:0] addr_ch_dec;
always @(*)
case(addr_ch)
3'd0: addr_ch_dec = 6'b000_001;
3'd1: addr_ch_dec = 6'b000_010;
3'd2: addr_ch_dec = 6'b000_100;
3'd3: addr_ch_dec = 6'b001_000;
3'd4: addr_ch_dec = 6'b010_000;
3'd5: addr_ch_dec = 6'b100_000;
default: addr_ch_dec = 6'd0;
endcase // up_addr
wire up1 = cur_ch == addr_ch_dec;
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
addr1 <= 'd0; addr2 <= 'd0; addr3 <= 'd0;
addr4 <= 'd0; addr5 <= 'd0; addr6 <= 'd0;
done1 <= 'd1; done5 <= 'd1; done6 <= 'd1;
start1 <= 'd0; start2 <= 'd0; start3 <= 'd0;
start4 <= 'd0; start5 <= 'd0; start6 <= 'd0;
end1 <= 'd0; end2 <= 'd0; end3 <= 'd0;
end4 <= 'd0; end5 <= 'd0; end6 <= 'd0;
skip1 <= 'd0; skip2 <= 'd0; skip3 <= 'd0;
skip4 <= 'd0; skip5 <= 'd0; skip6 <= 'd0;
end else if( cen ) begin
addr2 <= addr1;
on2 <= aoff ? 1'b0 : (aon | (on1 && ~done1));
clr2 <= aoff || aon || done1; // Each time a A-ON is sent the address counter restarts
start2 <= (up_start && up1) ? addr_in[11:0] : start1;
end2 <= (up_end && up1) ? addr_in[11:0] : end1;
bank2 <= (up_start && up1) ? addr_in[15:12] : bank1;
skip2 <= skip1;
addr3 <= addr2; // clr2 ? {start2,9'd0} : addr2;
on3 <= on2;
clr3 <= clr2;
start3 <= start2;
end3 <= end2;
bank3 <= bank2;
skip3 <= skip2;
addr4 <= addr3;
on4 <= on3;
clr4 <= clr3;
start4 <= start3;
end4 <= end3;
bank4 <= bank3;
skip4 <= skip3;
addr5 <= addr4;
on5 <= on4;
clr5 <= clr4;
done5 <= addr4[20:9] == end4 && addr4[8:0]==~9'b0 && ~(clr4 && on4);
start5 <= start4;
end5 <= end4;
bank5 <= bank4;
skip5 <= skip4;
// V
addr6 <= addr5;
on6 <= on5;
clr6 <= clr5;
done6 <= done5;
start6 <= start5;
end6 <= end5;
bank6 <= bank5;
sumup6 <= sumup5;
skip6 <= skip5;
addr1 <= (clr6 && on6) ? {start6,9'd0} : (sumup6 && ~skip6 ? addr6+21'd1 :addr6);
on1 <= on6;
done1 <= done6;
start1 <= start6;
end1 <= end6;
roe_n1 <= ~sumup6;
decon1 <= sumup6;
bank1 <= bank6;
clr1 <= clr6;
skip1 <= (clr6 && on6) ? 1'b1 : sumup6 ? 1'b0 : skip6;
end
endmodule // jt10_adpcm_cnt
|
module testcache();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache,readmissdata;
wire hit, miss, dirty;
// test
memory_system DUT(clk, re, we, we2, we3, address, writedata, readdatacache, hit, miss, dirty);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
/*
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
*/
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#5;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008011;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008010;
writedata <= 32'h01010101;
#10;
we <= 1'b0;
#200;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[300010][2]; int dp[300010][2]; int Flag[300010]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &f[i][0]); for (int i = 1; i <= n; i++) scanf( %d , &f[i][1]); if (k == 1) { for (int ii = 0; ii < 2; ii++) { int r = ii, s = ii ^ 1; for (int i = 1; i <= n; i++) { int nr = f[i][r], ns = f[i][s]; int ss = nr + ns; if (nr != ((ss + 1) / 2) || ns != (ss / 2)) { Flag[ii] = 1; break; } if (ss & 1) swap(r, s); } } if (Flag[1] && Flag[0]) puts( NO ); else puts( YES ); return 0; } dp[0][0] = dp[0][1] = 0; for (int i = 1; i <= n; i++) { dp[i][0] = dp[i][1] = 0x3f3f3f3f; for (int v = 0; v < 2; v++) { int u = v ^ 1; int r = dp[i - 1][v]; if (r != 0x3f3f3f3f) { int x = f[i][v], y = f[i][u]; if (x >= y) { if (x <= (k - r + (long long)k * y)) dp[i][v] = min((long long)dp[i][v], max(1LL, x - (k - r) - (long long)k * (y - 1))); if (x <= ((long long)k * (y - 1) + k - r)) dp[i][u] = min(dp[i][u], 1); } else { if (y <= ((long long)k * (x + 1))) dp[i][u] = min((long long)dp[i][u], max(1LL, y - (long long)k * x)); if (y <= ((long long)k * x)) dp[i][v] = min(dp[i][v], 1); } } } } if (dp[n][0] == 0x3f3f3f3f && dp[n][1] == 0x3f3f3f3f) puts( NO ); else puts( YES ); return 0; }
|
#include <bits/stdc++.h> using namespace std; long long powmod(long long a, long long b) { long long res = 1; a %= 1000000007; for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } template <typename T> inline bool chkmin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <typename T> inline bool chkmax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int P = 10000007; unsigned int p[500100], l[500100], r[500100]; int m; char ans[500100], s[500100]; int n; bool ok(int i, int x) { if (++i < x) return 0; return ((r[i] - r[i - x] * p[x]) * p[i - x]) == (l[i] - l[i - x]); } bool dfs(int i, int x) { if (i == n) { puts(ans); return 1; } ans[i] = x ? s[i] : a ; for (; ans[i] <= z ; ans[i]++) { l[i + 1] = l[i] + ans[i] * p[i]; r[i + 1] = r[i] * P + ans[i]; if (!ok(i, m) && !ok(i, m + 1) && dfs(i + 1, x && (ans[i] == s[i]))) return 1; } return 0; } int main() { m = read(); scanf( %s , s); n = strlen(s); int i; for (i = n - 1; i >= 0 && s[i] == z ; i--) s[i] = a ; if (i == -1) { puts( Impossible ); return 0; } s[i]++; p[0] = 1; for (int i = 1; i < 500100; i++) p[i] = p[i - 1] * P; if (!dfs(0, 1)) puts( Impossible ); return 0; }
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mmio_if_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
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#include <bits/stdc++.h> using namespace std; long long a, b, n; short ans = 0; int main() { cin >> a >> b; while (b > 0) { if (b == 1) { ans = 0; break; } if (b % a != 0) { ans = 1; break; } ++n; b = b / a; } if (ans == 0) { cout << YES << endl; cout << n - 1; } else cout << NO << endl; }
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int n) { if (n <= 1) return false; for (int i = 2; i < n; i++) if (n % i == 0) return false; return true; } int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> v; for (long long int i = 0; i < n; i++) { long long int x; cin >> x; v.push_back(x); } if (v[0] + v[1] <= v[n - 1]) { cout << 1 << << 2 << << n << n ; } else { cout << -1 << n ; } } return 0; }
|
`default_nettype none
module romtest1 (
input wire sysclk,
input wire clk,
input wire rst,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
wire [7:0] dout;
reg [3:0] addr;
//-- Instanciar la memoria rom
rom16x8
ROM (
.clk(sysclk),
.addr(addr),
.data(dout)
);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
debounce deb1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(clk_in)
);
//-- Counter for incrementing the address
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
addr <= 4'b0;
else
addr <= addr + 1;
end
assign {d7,d6,d5,d4,d3,d2,d1,d0} = dout;
endmodule
module rom16x8 (input clk,
input wire [3:0] addr,
output reg [7:0] data);
//-- Memoria
reg [7:0] rom [0:15];
always @(negedge clk) begin
data <= rom[addr];
end
//-- ROM2: Secuencia
initial begin
rom[0] = 8'hAA;
rom[1] = 8'h55;
rom[2] = 8'hAA;
rom[3] = 8'h55;
rom[4] = 8'h11;
rom[5] = 8'h22;
rom[6] = 8'h44;
rom[7] = 8'h88;
rom[8] = 8'h99;
rom[9] = 8'hCC;
rom[10] = 8'hFF;
rom[11] = 8'h08;
rom[12] = 8'h04;
rom[13] = 8'h02;
rom[14] = 8'h01;
rom[15] = 8'h00;
end
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
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