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//*******************************************************************/
// $File: full_adder.v
// $Date: 2016-03-22
// $Revision: 1.0 $
// $Author: ENCLab
// $State: 1.0 - Initial Release
//*******************************************************************/
// $Change History:
//
// Revision 1.0 ENCLab
// Initial Release
//*******************************************************************/
// $Description
//
// one-bit full adder
//
//*******************************************************************/
`timescale 1 ns / 1 ps
module full_adder
(
//----------------------------------------------------------------
// Input Ports
//----------------------------------------------------------------
input x_in, // one bit input data
input y_in, // one bit input data
input c_in, // one bit carry data
//----------------------------------------------------------------
// Output Ports
//----------------------------------------------------------------
output wire s_out, // sum of two input
output wire c_out // carry of two input
);
//----------------------------------------------------------------
// internal variables declaration
//----------------------------------------------------------------
wire wire_sum0;
wire wire_carry0;
wire wire_carry1;
//----------------------------------------------------------------
// submodule instantiation
//----------------------------------------------------------------
half_adder U0_half_adder (
.x_in ( x_in ),
.y_in ( y_in ),
.s_out ( wire_sum0 ),
.c_out ( wire_carry0 )
);
half_adder U1_half_adder (
.x_in ( wire_sum0 ),
.y_in ( c_in ),
.s_out ( s_out ),
.c_out ( wire_carry1 )
);
//----------------------------------------------------------------
// code for operation start
//----------------------------------------------------------------
// output port
assign c_out = ( wire_carry0 | wire_carry1 );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__decap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_TB_V
`define SKY130_FD_SC_MS__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 1 << 17; const long long MN = N; long long s[MN]; long long m[MN]; long long rr[MN]; bool st[2 * N]; long long tme[2 * N]; long long lz[2 * N]; long long nn; vector<pair<long long, pair<long long, long long> > > manaFull[2 * N]; struct second { long long s, m, r; }; void f1(long long k, long long l, long long r) { for (long long i = l; i <= r; ++i) { if (rr[i]) { manaFull[k].push_back({m[i] / rr[i] + !!(m[i] % rr[i]), {m[i], rr[i]}}); } else { manaFull[k].push_back({1e18, {m[i], rr[i]}}); } } sort(manaFull[k].begin(), manaFull[k].end()); for (long long i = 1; i < manaFull[k].size(); ++i) { manaFull[k][i].second.first += manaFull[k][i - 1].second.first; } for (long long i = (long long)manaFull[k].size() - 1; i > 0; --i) { manaFull[k][i - 1].second.second += manaFull[k][i].second.second; } if (l == r) return; long long mid = (l + r) / 2; f1(k * 2, l, mid); f1(k * 2 + 1, mid + 1, r); } long long getFirstNotFull(long long k, long long t) { long long lo = 0; long long hi = (long long)manaFull[k].size() - 1; long long res = hi + 1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (manaFull[k][mid].first > t) { hi = mid - 1; res = mid; } else { lo = mid + 1; } } return res; } void lol(long long k, long long l, long long r, long long t) { if (l < r && lz[k]) { lz[k] = 0; lz[k * 2] = 1; lz[k * 2 + 1] = 1; tme[k * 2] = tme[k]; tme[k * 2 + 1] = tme[k]; } } bool eka[2 * N]; long long absorbMana(long long k, long long l, long long r, long long x, long long y, long long t) { long long res = 0; if (l > y || r < x) return 0; if (l >= x && r <= y && lz[k]) { long long firstNotFull = getFirstNotFull(k, t - tme[k]); if (firstNotFull != 0) { res += manaFull[k][firstNotFull - 1].second.first; } long long sz = r - l + 1; if (firstNotFull != sz) res += (manaFull[k][firstNotFull].second.second) * (t - tme[k]); if (eka[k]) { eka[k] = 0; res = min(m[k - N], s[k - N] + (t - tme[k]) * rr[k - N]); } lz[k] = 1; tme[k] = t; return res; } lol(k, l, r, t); long long mid = (l + r) / 2; long long q = absorbMana(k * 2, l, mid, x, y, t); long long w = absorbMana(k * 2 + 1, mid + 1, r, x, y, t); if (l >= x && r <= y) { lz[k] = 1; tme[k] = t; } return q + w; } int main() { long long n; ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; nn = n; for (long long i = 0; i < n; ++i) { cin >> s[i] >> m[i] >> rr[i]; lz[i + N] = 1; eka[i + N] = 1; } f1(1, 0, N - 1); long long m; cin >> m; for (long long i = 0; i < m; ++i) { long long t, l, r; cin >> t >> l >> r; cout << absorbMana(1, 0, N - 1, l - 1, r - 1, t) << n ; } }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_BLACKBOX_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_bleeder (
SHORT
);
input SHORT;
// Voltage supply signals
wire VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int NN = 1010; double first[NN], second[NN]; int main() { int n, a, b, c, d; cin >> n; for (int i = 0; i < n; i++) { scanf( %d%d%d%d , &a, &b, &c, &d); double s = a * a * d * d + c * c * b * b; first[i] = a * b * d * d / s; second[i] = c * b * b * d / s; } const double eps = 1e-9; vector<pair<pair<double, double>, double> > line(n * (n - 1) / 2); for (int i = 0, id = 0; i < n; i++) for (int j = i + 1; j < n; j++, id++) { line[id] = make_pair(make_pair(first[i] + first[j], second[i] + second[j]), fabs(first[i] - first[j]) < eps ? 1e9 : (second[i] - second[j]) / (first[i] - first[j])); } sort(line.begin(), line.end(), [&](const pair<pair<double, double>, double> &a, const pair<pair<double, double>, double> &b) { if (fabs(a.first.first - b.first.first) > eps) return a.first.first < b.first.first; if (fabs(a.first.second - b.first.second) > eps) return a.first.second < b.first.second; return a.second < b.second - eps; }); auto cmp1 = [&](double first, double second) { return fabs(first - second) < eps; }; auto cmp = [&](pair<double, double> first, pair<double, double> second) { return cmp1(first.first, second.first) && cmp1(first.second, second.second); }; int ans = 0; const int mod = 1000000007; for (int i = 0, j, k; i < line.size(); i = j) { int mid = 1; for (j = i; j < line.size() && cmp(line[i].first, line[j].first); j = k) { for (k = j; k < line.size() && cmp(line[k].first, line[j].first) && cmp1(line[j].second, line[k].second); k++) ; mid = (long long)mid * (k - j + 1) % mod; } mid = (mid + mod - 1 - j + i) % mod; ans += mid; if (ans >= mod) ans -= mod; } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Tomasz Kryjak
//
// Create Date: 11:29:28 10/28/2013
// Design Name:
// Module Name: tb_filter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_hdmi(
);
wire rx_pclk;
wire rx_de;
wire rx_hsync;
wire rx_vsync;
wire [7:0] rx_red;
wire [7:0] rx_green;
wire [7:0] rx_blue;
wire tx_de;
wire tx_hsync;
wire tx_vsync;
wire [7:0] tx_red;
wire [7:0] tx_green;
wire [7:0] tx_blue;
// --------------------------------------
// HDMI input
// --------------------------------------
hdmi_in file_input (
.hdmi_clk(rx_pclk),
.hdmi_de(rx_de),
.hdmi_hs(rx_hsync),
.hdmi_vs(rx_vsync),
.hdmi_r(rx_red),
.hdmi_g(rx_green),
.hdmi_b(rx_blue)
);
wire [7:0] H;
wire [7:0] S;
wire [7:0] V;
wire conv_vsync;
wire conv_hsync;
wire conv_de;
// image processing
rgb2hsv uut (
.clk(rx_pclk),
.ce(1'b1),
.R(rx_red),
.G(rx_green),
.B(rx_blue),
.in_hsync(rx_hsync),
.in_vsync(rx_vsync),
.in_de(rx_de),
.H(H),
.S(S),
.V(V),
.out_hsync(conv_hsync),
.out_vsync(conv_vsync),
.out_de(conv_de)
);
// --------------------------------------
// Output assigment
// --------------------------------------
assign tx_de = conv_de;
assign tx_hsync = conv_hsync;
assign tx_vsync = conv_vsync;
assign tx_red = H;
assign tx_green = S;
assign tx_blue = V;
// --------------------------------------
// HDMI output
// --------------------------------------
hdmi_out file_output (
.hdmi_clk(rx_pclk),
.hdmi_vs(tx_vsync),
.hdmi_de(tx_de),
.hdmi_data({8'b0,tx_red,tx_green,tx_blue})
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:29:52 05/02/2013
// Design Name:
// Module Name: cond_sum
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cond_sum(input [3:0] X,Y,input Cin,output [3:0] Sum,output C_out
);
reg [1:0] c00sum00,c01sum01,c10sum10,c11sum11,c20sum20,c21sum21,c30sum30,c31sum31;
wire [1:0]mux_out01,mux_out02,mux_out03,mux_out04;
wire [2:0]mux_out11,mux_out12;
assign Sum = Cin? {mux_out12[1:0],mux_out02[0],c01sum01[0]}:{mux_out11[1:0],mux_out01[0],c00sum00[0]};
assign C_out = Cin?mux_out12[2]:mux_out11[2];
assign mux_out01=c00sum00[1]?c11sum11:c10sum10,
mux_out02=c01sum01[1]?c11sum11:c10sum10,
mux_out03=c20sum20[1]?c31sum31:c30sum30,
mux_out04=c21sum21[1]?c31sum31:c30sum30;
assign mux_out11=mux_out01[1]?{mux_out04,c21sum21[0]}:{mux_out03,c20sum20[0]},
mux_out12=mux_out02[1]?{mux_out04,c21sum21[0]}:{mux_out03,c20sum20[0]};
always @* begin
cond_cell(X[0],Y[0],c00sum00,c01sum01);
cond_cell(X[1],Y[1],c10sum10,c11sum11);
cond_cell(X[2],Y[2],c20sum20,c21sum21);
cond_cell(X[3],Y[3],c30sum30,c31sum31);
end
task cond_cell(input x,y, output [1:0] c0sum0,c1sum1);
reg xr;
begin
xr = x^y;
c0sum0 ={x&y,xr};
c1sum1 ={x|y,~xr};
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.v"
module top();
// Inputs are registered
reg A;
reg LOWLVPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LOWLVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LOWLVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LOWLVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LOWLVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LOWLVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LOWLVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell dut (.A(A), .LOWLVPWR(LOWLVPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// (c) Analog Devices Inc.
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, RGB to CrYCb conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
module cf_csc_RGB2CrYCb (
clk,
RGB_vs,
RGB_hs,
RGB_de,
RGB_data,
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data);
input clk;
input RGB_vs;
input RGB_hs;
input RGB_de;
input [23:0] RGB_data;
output CrYCb_vs;
output CrYCb_hs;
output CrYCb_de;
output [23:0] CrYCb_data;
reg CrYCb_vs = 'd0;
reg CrYCb_hs = 'd0;
reg CrYCb_de = 'd0;
reg [23:0] CrYCb_data = 'd0;
wire Cr_vs_s;
wire Cr_hs_s;
wire Cr_de_s;
wire [ 7:0] Cr_data_s;
wire Y_vs_s;
wire Y_hs_s;
wire Y_de_s;
wire [ 7:0] Y_data_s;
wire Cb_vs_s;
wire Cb_hs_s;
wire Cb_de_s;
wire [ 7:0] Cb_data_s;
always @(posedge clk) begin
CrYCb_vs <= Cr_vs_s & Y_vs_s & Cb_vs_s;
CrYCb_hs <= Cr_hs_s & Y_hs_s & Cb_hs_s;
CrYCb_de <= Cr_de_s & Y_de_s & Cb_de_s;
CrYCb_data <= {Cr_data_s, Y_data_s, Cb_data_s};
end
cf_csc_1 i_csc_Cr (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h00707),
.C2 (17'h105e2),
.C3 (17'h10124),
.C4 (25'h0080000),
.csc_vs (Cr_vs_s),
.csc_hs (Cr_hs_s),
.csc_de (Cr_de_s),
.csc_data_1 (Cr_data_s));
cf_csc_1 i_csc_Y (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h0041b),
.C2 (17'h00810),
.C3 (17'h00191),
.C4 (25'h0010000),
.csc_vs (Y_vs_s),
.csc_hs (Y_hs_s),
.csc_de (Y_de_s),
.csc_data_1 (Y_data_s));
cf_csc_1 i_csc_Cb (
.clk (clk),
.vs (RGB_vs),
.hs (RGB_hs),
.de (RGB_de),
.data (RGB_data),
.C1 (17'h1025f),
.C2 (17'h104a7),
.C3 (17'h00707),
.C4 (25'h0080000),
.csc_vs (Cb_vs_s),
.csc_hs (Cb_hs_s),
.csc_de (Cb_de_s),
.csc_data_1 (Cb_data_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; typedef struct _Box { int pos, weight; } Box; Box arr[200010]; long long int bit1[200010], bit2[200010]; const int mod = 1e9 + 7; int num; int getLowbit(int n) { return n & (-n); } void add(long long int* bitArr, int pos, long long int val, bool shouldMod) { if (shouldMod) val = (val + mod) % mod; for (int i = pos; i <= num; i += getLowbit(i)) { bitArr[i] += val; if (shouldMod) bitArr[i] = (bitArr[i] + mod) % mod; } } long long int getPrefixSum(long long int* bitArr, int pos, bool shouldMod) { long long int ans = 0; for (int i = pos; i > 0; i -= getLowbit(i)) { ans += bitArr[i]; if (shouldMod) ans = (ans + mod) % mod; } return ans; } long long int getRangeSum(long long int* bitArr, int qLeftPt, int qRightPt, bool shouldMod) { if (qRightPt < qLeftPt) return 0; long long int ans = getPrefixSum(bitArr, qRightPt, shouldMod) - getPrefixSum(bitArr, qLeftPt - 1, shouldMod); if (shouldMod) ans = (ans + mod) % mod; return ans; } int getMidPos(int qLeftPt, int qRightPt) { int leftPt = qLeftPt, rightPt = qRightPt; int ans = rightPt; while (leftPt <= rightPt) { int midPt = (leftPt + rightPt) >> 1; if (getRangeSum(bit1, qLeftPt, midPt, false) >= getRangeSum(bit1, midPt + 1, qRightPt, false)) { ans = midPt; rightPt = midPt - 1; } else { leftPt = midPt + 1; } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); memset(bit1, 0, sizeof(bit1)); memset(bit2, 0, sizeof(bit2)); int qNum; cin >> num >> qNum; for (int i = 1; i <= num; i++) { cin >> arr[i].pos; } for (int i = 1; i <= num; i++) { cin >> arr[i].weight; add(bit1, i, arr[i].weight, false); add(bit2, i, (long long int)arr[i].weight * (arr[i].pos - i), true); } while (qNum--) { int x, y; cin >> x >> y; if (x < 0) { x = -x; add(bit1, x, y - arr[x].weight, false); add(bit2, x, ((long long int)y - arr[x].weight) * (arr[x].pos - x), true); arr[x].weight = y; } else { if (x == y) { cout << 0 << endl; continue; } int midPos = getMidPos(x, y); long long int leftAns = (getRangeSum(bit1, x, midPos, true) * abs(arr[midPos].pos - midPos) % mod - getRangeSum(bit2, x, midPos, true) + mod) % mod; long long int rightAns = (getRangeSum(bit1, midPos, y, true) * abs(arr[midPos].pos - midPos) % mod - getRangeSum(bit2, midPos, y, true) + mod) % mod; long long int ans = (leftAns - rightAns + mod) % mod; cout << ans << endl; } } return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21A_FUNCTIONAL_PP_V
|
module autoinst_signed
(/*AUTOARG*/
// Outputs
another_output2, another_output, an_outputpre, an_output2
);
/*AUTOOUTPUTEVERY*/
// Beginning of automatic outputs (every signal)
output [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
output signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
output signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
output [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] an_output2; // From u_fubar2 of autoinst_signed_fubar2.v
wire signed [1:0] an_outputpre; // From u_fubar of autoinst_signed_fubar.v
wire signed [1:0] another_output; // From u_fubar of autoinst_signed_fubar.v
wire [1:0] another_output2; // From u_fubar2 of autoinst_signed_fubar2.v
// End of automatics
autoinst_signed_fubar u_fubar
(
// Outputs
.an_output (an_outputpre[1:0]),
.plover (plump),
/*AUTOINST*/
// Outputs
.another_output (another_output[1:0]),
// Inputs
.an_input (an_input[1:0]));
autoinst_signed_fubar2 u_fubar2
(
/*AUTOINST*/
// Outputs
.an_output2 (an_output2[1:0]),
.another_output2 (another_output2[1:0]),
// Inputs
.an_input2 (an_input2[1:0]));
endmodule
|
#include<bits/stdc++.h> using namespace std; int main(){ int t; cin >> t; while(t--){ int n; cin >> n; vector <int> a(n); int k = INT_MAX,z = -1; for(int i=0;i<n;i++){ cin >> a[i]; k = min(k,a[i]); if(k==a[i]){ z = i; } } cout << n-1 << endl; for(int i=0;i<n;i++){ if(i!=z){ cout << i+1 << << z+1 << << max(1,k+abs(z-i)) << << k << endl; } } //cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = (1e5) + 15; const int mod = (1e9) + 7; const int inf = (1e9) + 3; long long int n, k, ans; string s; long long int a[maxn]; int main() { ios::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); ; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < n; i++) { if (a[i] + a[i - 1] < k) ans += (k - a[i] - a[i - 1]), a[i] += (k - a[i] - a[i - 1]); } cout << ans << endl; for (int i = 0; i < n; i++) cout << a[i] << ; cout << endl; return 0; }
|
// megafunction wizard: %CRC Compiler v9.1%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// crc_check_altcrc
// ============================================================
// Generated by CRC Compiler 9.1 [Altera, IP Toolbench 1.3.0 Build 222]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2010 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module crc_check (
clk,
data,
datavalid,
empty,
endofpacket,
reset_n,
startofpacket,
crcbad,
crcvalid);
input clk;
input [127:0] data;
input datavalid;
input [3:0] empty;
input endofpacket;
input reset_n;
input startofpacket;
output crcbad;
output crcvalid;
crc_check_altcrc crc_check_altcrc_inst(
.clk(clk),
.data(data),
.datavalid(datavalid),
.empty(empty),
.endofpacket(endofpacket),
.reset_n(reset_n),
.startofpacket(startofpacket),
.crcbad(crcbad),
.crcvalid(crcvalid));
endmodule
// =========================================================
// CRC Compiler Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, CRC Compiler Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="CRC Compiler" version="9.1" build="222" iptb_version="1.3.0 Build 222" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="crc_check_altcrc" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "p_wordsize" value="128" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_crccheck" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_inbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_outbuff" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lanes" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_fwdpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_initvalue" value="0xFFFFFFFF" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_bckpipe" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_generator" value="1_0000_0100_1100_0001_0001_1101_1011_0111" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_lsb" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_symbol_lsb" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_true_output" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_reverse" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_start_offset" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_channels" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_optimize" value="speed" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_use_all_ones" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_datapath" value="128 bits" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_genname" value="CRC-32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "g_negate_checksum" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "p_cbx_hdl_language" value="verilog" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="VERILOG" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "gb_enabled" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="crc_check_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "filename" value="crc_check.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
// RELATED_FILES: crc_check.v, crc_check_altcrc.v;
// IPFS_FILES: crc_check.vo;
// =========================================================
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, count; long long l, u; scanf( %d , &n); long long int a[n]; long long int h[n]; for (i = 0; i < n; ++i) { cin >> a[i] >> h[i]; } l = a[0]; h[n - 1] = 0; h[0] = 0; u = a[n - 1]; if (n > 1) { count = 2; for (i = 1; i < n - 1; ++i) { if (a[i] - h[i] > l) { count++; l = a[i]; } else { if (a[i] + h[i] < a[i + 1]) { l = a[i] + h[i]; count++; } else l = a[i]; } } } else count = 1; printf( %d n , count); return 0; }
|
/* Author: ChinmayKarnik Time: 21:14:26 Date: 16-04-2021 */ #include<bits/stdc++.h> using namespace std; //mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); //mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); typedef enum {BLACK,WHITE,GRAY} color; #define int long long #define TESTCASES true #define FASTIO true const int maxN = 200009; const int inf = (int)1e18 + 1; int N,K; int a[maxN]; int p[64]; void solve() { int i,j,k; vector<int> ans; cin >> N >> K; int one = 1; if(N<64) { if((one<<(N-1))<K) { cout << -1 n ; return; } } while(N>=64) { ans.push_back(1); N--; } while(N) { int curr = 1; int sub = 0; while((curr<=N) && p[N-curr]<K) { K-=p[N-curr]; curr++; } // curr--; N-=curr; ans.push_back(curr); //K-=(curr-1)*(p[]) } int p = 1; vector<int> fin; for(int x:ans) { for(i=p+x-1;i>=p;i--) { fin.push_back(i); } p=p+x; } for(int x:fin) { cout << x << ; } cout << n ; } signed main() { if(FASTIO) { ios_base::sync_with_stdio(false); cin.tie(NULL); } int T = 1; if(TESTCASES) { cin >> T; } int i,j,k; p[0]=1; p[1]=1; for(i=2;i<64;i++) { p[i]=0; for(j=0;j<i;j++) { p[i]+=p[j]; } // cout << p[i] << ; } while(T--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; vector<long long> V[100005]; long long n; map<long long, long long> DP[100005]; long long concatHash(long long x, long long y) { return (x * 100005 + y) % 1000000007; } void answer(long long x) { cout << x; exit(0); } void fail() { cout << -1; exit(0); } void prec(long long x, long long f) { if (V[x].size() == 1 && f) { DP[x][f] = 1; return; } unordered_set<long long> S; for (auto i : V[x]) { if (i != f) { prec(i, x); if (DP[i][x] == -1) DP[x][f] = -1; S.insert(DP[i][x]); } } if (DP[x][f] == -1) return; if (S.size() == 1) { long long chash = *(S.begin()); DP[x][f] = concatHash(chash, V[x].size()); } else DP[x][f] = -1; } void DFS(long long x, long long f, long long phash) { if (V[x].size() == 1 && f) { if (phash != -1) { answer(x); } return; } unordered_map<long long, long long> S; for (auto i : V[x]) if (i != f) S[DP[i][x]]++; if (f) S[phash]++; if (S.size() == 0) { assert(false); return; } if (S.size() == 1 && S.begin()->first != -1) { answer(x); } if (S.size() == 1 && S.begin()->first == -1) { if (S.begin()->second != 1) return; for (auto i : V[x]) { if (DP[i][x] == -1) { if (f) DFS(i, x, concatHash(phash, V[x].size())); else DFS(i, x, V[x].size()); return; } } } if (S.size() >= 3) { return; } auto it = S.begin(); auto a = make_pair(it->first, it->second); it++; auto b = make_pair(it->first, it->second); for (auto i : V[x]) { if (i != f && (DP[i][x] == a.first && a.second == 1 && b.first != -1)) { DFS(i, x, concatHash(b.first, V[x].size())); } if (i != f && (DP[i][x] == b.first && b.second == 1 && a.first != -1)) { DFS(i, x, concatHash(a.first, V[x].size())); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; if (n == 1) { answer(1); } for (long long i = 1; i < n; i++) { long long x, y; cin >> x >> y; V[x].push_back(y); V[y].push_back(x); } prec(1, 0); DFS(1, 0, -1); cout << -1; return 0; }
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module spw_light_ctrl_in (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 1: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] data_out;
wire [ 1: 0] out_port;
wire [ 1: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[1 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_TB_V
`define SKY130_FD_SC_HS__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_TB_V
|
module memory(input clk, input [31:0] idata, output [47:0] odata, input [15:0] addr, input [1:0] rw);
reg [7:0] data [0:2**16-1];
initial $readmemb("mem_init.txt", data);
always @(clk) begin
case (rw)
2'b01 : begin
data[addr] <= idata;
end
2'b10 : begin
{data[addr], data[addr + 1] } <= idata;
end
2'b11 : begin
{data[addr], data[addr + 1], data[addr + 2], data[addr + 3] } <= idata;
end
endcase
end
assign odata = {data[addr], data[addr + 1], data[addr + 2], data[addr + 3], data[addr + 4], data[addr + 5] };
endmodule
module memory_test;
reg clk;
reg [1:0] rw;
reg [15:0] addr;
wire line;
reg [31:0] wline;
wire [47:0] rline;
memory memory(clk, wline, rline, addr, rw);
initial begin
$monitor("%t: rw = %b, addr = %x, wline = %x, rline = %x", $time, rw, addr, wline, rline);
clk <= 0;
#10
rw <= 2'b11;
addr <= 0;
wline <= 48'h123456789ABC;
#10
rw <= 2'b00;
addr <= 0;
#10
rw <= 2'b10;
addr <= 1;
wline <= 48'hDEF012345678;
#10
rw <= 2'b00;
addr <= 0;
#10
rw <= 2'b11;
addr <= 3;
wline <= 48'h9ABCDEF12345;
#10
rw <= 2'b00;
addr <= 0;
#10
rw <= 2'b00;
addr <= 2;
#10 $finish;
end
always #10 begin
clk <= ~clk;
end
endmodule
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_carry_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b1),
.S (S_n)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> void chkmax(T &x, T y) { x = x > y ? x : y; } template <typename T> void chkmin(T &x, T y) { x = x > y ? y : x; } const int INF = (1ll << 30) - 1; template <typename T> void read(T &x) { x = 0; bool f = 1; char ch; do { ch = getchar(); if (ch == - ) f = 0; } while (ch > 9 || ch < 0 ); do { x = x * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); x = f ? x : -x; } template <typename T> void write(T x) { if (x < 0) x = ~x + 1, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int N = 3e4 + 5; const int K = 200 + 5; int n, m, a[N], f[N][K][4]; int main() { read(n); read(m); memset(f, -0x3f, sizeof(f)); for (int i = 1; i <= n; i++) read(a[i]); for (int i = 0; i <= n; i++) for (int j = 0; j < 4; j++) f[i][0][j] = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { int x = 1 + (j != 1 && j != m); f[i][j][0] = max(f[i - 1][j][0], f[i - 1][j - 1][3]) + x * a[i]; f[i][j][1] = max(f[i][j][0], f[i - 1][j][1]); f[i][j][2] = max(f[i - 1][j][2], f[i - 1][j - 1][1]) - x * a[i]; f[i][j][3] = max(f[i][j][2], f[i - 1][j][3]); if (x == 2) f[i][j][1] = max(f[i][j][1], f[i - 1][j - 1][1]); if (x == 2) f[i][j][3] = max(f[i][j][3], f[i - 1][j - 1][3]); } } int ans = 0; for (int i = 0; i < 4; i++) chkmax(ans, f[n][m][i]); printf( %d n , ans); return 0; }
|
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
// Also check that SystemC is ordering properly
// verilator lint_on IMPERFECTSCH
module t (/*AUTOARG*/
// Outputs
o1, o8, o16, o32, o64, o65, o128, o513, o1a2, o94a3, obv1, obv16,
// Inputs
clk, i1, i8, i16, i32, i64, i65, i128, i513, i1a2, i94a3, ibv1, ibv16
);
input clk;
input i1;
input [7:0] i8;
input [15:0] i16;
input [31:0] i32;
input [63:0] i64;
input [64:0] i65;
input [127:0] i128;
input [512:0] i513;
input i1a2 [1:0];
input [93:0] i94a3 [2:0];
output o1;
output [7:0] o8;
output [15:0] o16;
output [31:0] o32;
output [63:0] o64;
output [64:0] o65;
output [127:0] o128;
output [512:0] o513;
output o1a2 [1:0];
output [93:0] o94a3 [2:0];
input [0:0] ibv1 /*verilator sc_bv*/;
input [15:0] ibv16 /*verilator sc_bv*/;
output [0:0] obv1 /*verilator sc_bv*/;
output [15:0] obv16 /*verilator sc_bv*/;
always @ (posedge clk) begin
o1 <= i1;
o8 <= i8;
o16 <= i16;
o32 <= i32;
o64 <= i64;
o65 <= i65;
o128 <= i128;
o513 <= i513;
obv1 <= ibv1;
obv16 <= ibv16;
o1a2 <= i1a2;
o94a3 <= i94a3;
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module can create clock signals that have a frequency lower *
* than those a PLL can generate. *
* *
* Revision: 1.1 *
* *
* Used in IP Cores: *
* Altera UP Avalon Audio and Video Config *
* *
******************************************************************************/
module Altera_UP_Slow_Clock_Generator (
// Inputs
clk,
reset,
enable_clk,
// Bidirectionals
// Outputs
new_clk,
rising_edge,
falling_edge,
middle_of_high_level,
middle_of_low_level
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter COUNTER_BITS = 10;
parameter COUNTER_INC = 10'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input enable_clk;
// Bidirectionals
// Outputs
output reg new_clk;
output reg rising_edge;
output reg falling_edge;
output reg middle_of_high_level;
output reg middle_of_low_level;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [COUNTER_BITS:1] clk_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
clk_counter <= {COUNTER_BITS{1'b0}};
else if (enable_clk == 1'b1)
clk_counter <= clk_counter + COUNTER_INC;
end
always @(posedge clk)
begin
if (reset == 1'b1)
new_clk <= 1'b0;
else
new_clk <= clk_counter[COUNTER_BITS];
end
always @(posedge clk)
begin
if (reset == 1'b1)
rising_edge <= 1'b0;
else
rising_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & ~new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
falling_edge <= 1'b0;
else
falling_edge <= (clk_counter[COUNTER_BITS] ^ new_clk) & new_clk;
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_high_level <= 1'b0;
else
middle_of_high_level <=
clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
always @(posedge clk)
begin
if (reset == 1'b1)
middle_of_low_level <= 1'b0;
else
middle_of_low_level <=
~clk_counter[COUNTER_BITS] &
~clk_counter[(COUNTER_BITS - 1)] &
(&(clk_counter[(COUNTER_BITS - 2):1]));
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* top = 1 *)
(* src = "var7_multi.v:2" *)
module var7_multi(A, B, C, D, E, F, G, valid);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
(* src = "var7_multi.v:3" *)
input A;
(* src = "var7_multi.v:3" *)
input B;
(* src = "var7_multi.v:3" *)
input C;
(* src = "var7_multi.v:3" *)
input D;
(* src = "var7_multi.v:3" *)
input E;
(* src = "var7_multi.v:3" *)
input F;
(* src = "var7_multi.v:3" *)
input G;
(* src = "var7_multi.v:4" *)
output valid;
assign _064_ = A & D;
assign _000_ = _064_ ^ B;
assign _001_ = _000_ ^ E;
assign _002_ = ~F;
assign _003_ = A ^ D;
assign _004_ = ~(_003_ | _002_);
assign _005_ = _004_ ^ _001_;
assign _006_ = ~(_005_ & G);
assign _007_ = _000_ & E;
assign _008_ = ~(A & B);
assign _009_ = ~(_008_ & D);
assign _010_ = _009_ ^ _007_;
assign _011_ = ~((_003_ | _001_) & F);
assign _012_ = ~(_011_ ^ _010_);
assign _013_ = _003_ ^ F;
assign _014_ = _013_ | E;
assign _015_ = ~((_014_ & _005_) | G);
assign _016_ = ~((_015_ | _012_) & _006_);
assign _017_ = ~E;
assign _018_ = C & D;
assign _019_ = _018_ ^ A;
assign _020_ = C | D;
assign _021_ = _020_ & E;
assign _022_ = ~(_021_ & _019_);
assign _023_ = ~(A ^ B);
assign _024_ = ~C;
assign _025_ = ~(_064_ | _024_);
assign _026_ = _025_ ^ _023_;
assign _027_ = ~((_026_ | _017_) & _022_);
assign _028_ = ~A;
assign _029_ = _028_ & B;
assign _030_ = _028_ | B;
assign _031_ = ~((_030_ & _024_) | _029_);
assign _032_ = ~(_064_ | _018_);
assign _033_ = ~((_032_ | B) & (_031_ | D));
assign _034_ = _033_ ^ _017_;
assign _035_ = ~(_034_ ^ _027_);
assign _036_ = _021_ | _019_;
assign _037_ = _022_ & E;
assign _038_ = ~(_037_ ^ _026_);
assign _039_ = ~((_036_ & _022_) | _038_);
assign _040_ = ~(_039_ & _035_);
assign _041_ = _018_ & A;
assign _042_ = ~(A | B);
assign _043_ = ~((_042_ | _024_) & _008_);
assign _044_ = ~((_031_ & D) | _043_);
assign _045_ = ~((_044_ | _041_) & (_033_ | _017_));
assign _046_ = ~((_034_ & _027_) | _045_);
assign _047_ = ~(_046_ | _002_);
assign _048_ = A & B;
assign _049_ = ~((_007_ | _048_) & D);
assign _050_ = ~((_011_ | _010_) & _049_);
assign _051_ = _048_ & _020_;
assign _052_ = ~(C & D);
assign _053_ = ~(_020_ & _052_);
assign _054_ = ~G;
assign _055_ = ~(_023_ & _054_);
assign _056_ = ~((_055_ | _053_) & _051_);
assign _057_ = ~((_042_ | _002_) & _056_);
assign _058_ = ~(_023_ | G);
assign _059_ = ~((_058_ & _053_) | (_008_ & _052_));
assign _060_ = ~((_059_ & _057_) | _041_);
assign _061_ = _060_ & _050_;
assign _062_ = ~(_061_ & _022_);
assign _063_ = ~((_047_ & _040_) | _062_);
assign valid = _063_ & _016_;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long power(long long b, long long e, long long m) { if (e == 0) return 1; if (e & 1) return b * power(b * b % m, e / 2, m) % m; return power(b * b % m, e / 2, m); } long long power(long long b, long long e) { if (e == 0) return 1; if (e & 1) return b * power(b * b, e / 2); return power(b * b, e / 2); } int _runtimeTerror_() { long long n; cin >> n; long long i, a[n], b[n]; for (i = 0; i < n; ++i) cin >> a[i]; for (i = 0; i < n; ++i) cin >> b[i]; long long ans = 0; long long arr[n]; for (i = 0; i < n; ++i) { arr[i] = a[i] * (i + 1) * (n - i); } sort(arr, arr + n, greater<long long>()); sort(b, b + n); for (i = 0; i < n; ++i) { ans += (b[i] * (arr[i] % 998244353)) % 998244353; ans %= 998244353; } cout << ans << n ; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) _runtimeTerror_(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100000 + 10; const int INF = 1000000000; const int MOD = (int)(1e9) + 7; int main() { int n; cin >> n; int m = (1 << (n + 1)) - 1; vector<int> a(m + 10, 0); for (int i = 2; i <= m; i++) cin >> a[i]; vector<int> s(m + 10, 0), c(m + 10, 0), add(m + 10, 0); int l = 0; for (int i = 2; i <= m; i++) { s[i] = s[i / 2] + a[i]; l = max(l, s[i]); } for (int i = m; i >= 1; i--) { if (i + i + 1 > m) c[i] = s[i]; else c[i] = max(c[i + i], c[i + i + 1]); } int res = 0; for (int i = 2; i <= m; i++) { int cur = c[i] + add[i / 2]; int inc = l - cur; add[i] = add[i / 2] + inc; res += inc; } cout << res << endl; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FA_SYMBOL_V
`define SKY130_FD_SC_LS__FA_SYMBOL_V
/**
* fa: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fa (
//# {{data|Data Signals}}
input A ,
input B ,
input CIN ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FA_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[26]; int A[26]; string s, t; int x1, x2; char c; int main() { cin >> s >> t; for (int i = 0; i < t.size(); i++) { c = t[i]; if (c > 96) a[c - 97]++; else A[c - 65]++; } for (int i = 0; i < s.size(); i++) { c = s[i]; if (c > 96) { if (a[c - 97]) { a[c - 97]--; x1++; s[i] = 0 ; } } else if (A[c - 65]) { A[c - 65]--; x1++; s[i] = 0 ; } } for (int i = 0; i < s.size(); i++) { c = s[i]; if (c == 0 ) continue; if (c >= 97) { c = c - 32; if (A[c - 65]) { x2++; A[c - 65]--; } } else { c = c + 32; if (a[c - 97]) { x2++; a[c - 97]--; } } } cout << x1 << << x2 << endl; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XNOR3_BEHAVIORAL_V
`define SKY130_FD_SC_MS__XNOR3_BEHAVIORAL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__xnor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xnor0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__XNOR3_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A222OI_PP_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void rs(int &x) { scanf( %d , &x); } void rsl(long long &x) { scanf( %I64d , &x); } void rsd(double &x) { scanf( %lf , &x); } void rss(char *str) { scanf( %s , str); } void ws(int &x) { printf( %d , x); } void wsl(long long &x) { printf( %I64d , x); } void wsd(double &x) { printf( %lf , x); } void wss(char *str) { printf( %s , str); } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } int const N = (2e5) + 5; int const mod = (1e9) + 7; int a[N], t[N], suma[N], sumt[N]; priority_queue<int> que; set<pair<int, int>> ms, mns; map<int, int> mm; int ins[N], inns[N]; int main() { int n, w, k; cin >> n >> w >> k; for (int i = 1; i <= n; ++i) { cin >> a[i]; suma[i] = suma[i - 1] + a[i]; } for (int i = 1; i <= n; ++i) { cin >> t[i]; mm[t[i]] = i; sumt[i] = sumt[i - 1] + t[i]; } int ans = 0; int r = 1; int ct = 0; int cp = 0; for (int i = 1; i <= n; ++i) { r = max(r, i); while (r <= n) { int dt = 0; if (ms.size() < w) { dt = t[r] / 2 + t[r] % 2; if (ct + dt <= k) { ms.insert(make_pair(t[r], r)); ins[r] = 1; ct += dt; } else { break; } } else { int var = ms.begin()->first; if (t[r] > var) { int dt = t[r] / 2 + t[r] % 2; int ddt = (var / 2); if (ct + dt + ddt <= k) { ins[ms.begin()->second] = 0; ins[r] = 1; mns.insert(*ms.begin()); ms.erase(ms.begin()); ms.insert(make_pair(t[r], r)); ct += dt + ddt; } else { break; } } else { int dt = t[r]; if (ct + dt <= k) { ct += dt; mns.insert(make_pair(t[r], r)); } else { break; } } } r++; } ans = max(suma[r - 1] - suma[i - 1], ans); if (ins[i] == 0) { ct -= t[i]; } else { ct -= (t[i] / 2 + t[i] % 2); ins[i] = 0; set<pair<int, int>>::iterator it = ms.find(make_pair(t[i], i)); if (it != ms.end()) { ms.erase(it); } while (mns.size() > 0 && ((--mns.end())->second <= i)) { mns.erase(--mns.end()); } if (mns.size() > 0) { it = --mns.end(); ct -= ((it->first) / 2); ins[it->second] = 1; ms.insert(*(--mns.end())); mns.erase((--mns.end())); } } } cout << ans; return 0; }
|
#include <bits/stdc++.h> const int mod = 1e9 + 7; const int MAXN = 1e6 + 5; template <typename _T> void read(_T &x) { x = 0; char s = getchar(); int f = 1; while (s < 0 || 9 < s) { f = 1; if (s == - ) f = -1; s = getchar(); } while ( 0 <= s && s <= 9 ) { x = (x << 3) + (x << 1) + s - 0 , s = getchar(); } x *= f; } template <typename _T> void write(_T x) { if (x < 0) { putchar( - ), x = -x; } if (9 < x) { write(x / 10); } putchar(x % 10 + 0 ); } int g[MAXN], f[MAXN], slink[MAXN], dif[MAXN]; int ch[MAXN][26], fa[MAXN], len[MAXN]; char Snat[MAXN], S[MAXN]; int N, lst, siz; int main() { scanf( %s , Snat + 1); N = strlen(Snat + 1); for (int i = 1; i <= N >> 1; i++) S[(i << 1) - 1] = Snat[i]; for (int i = (N >> 1) + 1; i <= N; i++) S[(N - i + 1) << 1] = Snat[i]; int x, p, cur; f[0] = 1; fa[0] = ++siz, len[1] = -1; for (int i = 1; i <= N; i++) { x = S[i] - a ; while (S[i] ^ S[i - len[lst] - 1]) lst = fa[lst]; if (!ch[lst][x]) { cur = ++siz, p = fa[lst]; len[cur] = len[lst] + 2; while (S[i] ^ S[i - len[p] - 1]) p = fa[p]; fa[cur] = ch[p][x], ch[lst][x] = cur; dif[cur] = len[cur] - len[fa[cur]], slink[cur] = (dif[cur] == dif[fa[cur]]) ? slink[fa[cur]] : fa[cur]; } lst = ch[lst][x]; for (p = lst; p; p = slink[p]) { g[p] = f[i - len[slink[p]] - dif[p]]; if (slink[p] ^ fa[p]) g[p] = (g[p] + g[fa[p]]) % mod; if (!(i & 1)) f[i] = (f[i] + g[p]) % mod; } } write(f[N]), putchar( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; auto random_address = [] { char *p = new char; delete p; return (uint64_t)p; }; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count() * (random_address() | 1)); const int INF = 1e9 + 5; struct edge { int a, b, color, index; }; int N, M, K; vector<edge> edges; vector<vector<int>> color_count; void set_color(edge &e, int color) { color_count[e.a][e.color]--; color_count[e.b][e.color]--; e.color = color; color_count[e.a][e.color]++; color_count[e.b][e.color]++; } bool fix() { vector<int> minimum(N, INF), maximum(N, 0); for (int i = 0; i < N; i++) for (int k = 0; k < K; k++) { minimum[i] = min(minimum[i], color_count[i][k]); maximum[i] = max(maximum[i], color_count[i][k]); } bool change = false; for (edge &e : edges) if ((maximum[e.a] - minimum[e.a] > 2 && color_count[e.a][e.color] == maximum[e.a]) || (maximum[e.b] - minimum[e.b] > 2 && color_count[e.b][e.color] == maximum[e.b])) { set_color(e, rng() % K); change = true; } return change; } int main() { cin >> N >> M >> K; color_count.assign(N, vector<int>(K, 0)); for (int i = 0; i < N; i++) { int _; cin >> _; } edges.resize(M); for (int i = 0; i < M; i++) { edge &e = edges[i]; cin >> e.a >> e.b; e.a--; e.b--; e.index = i; e.color = rng() % K; color_count[e.a][e.color]++; color_count[e.b][e.color]++; } bool bad; do { shuffle(edges.begin(), edges.end(), rng); bad = false; while (fix()) bad = true; } while (bad); vector<int> answers(M); for (edge &e : edges) answers[e.index] = e.color + 1; for (int i = 0; i < M; i++) cout << answers[i] << n ; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1 << 22; int h, g; long long a[N]; vector<int> ans; int path[25]; long long pull(int u) { long long tp = a[u]; int cnt = 0; path[cnt++] = u; a[u] = 0; while ((u << 1) < (1 << h) && max(a[u << 1], a[(u << 1) | 1]) > 0) { if (a[u << 1] > a[(u << 1) | 1]) { swap(a[u << 1], a[u]); u <<= 1; } else { swap(a[(u << 1) | 1], a[u]); u = (u << 1) | 1; } path[cnt++] = u; } if (u < (1 << g)) { for (int i = cnt - 1; i >= 0; i--) { a[path[i]] = a[path[i - 1]]; } a[path[0]] = tp; return 0; } return tp; } void solve() { ans.clear(); cin >> h >> g; long long sum = 0; for (int i = 1; i <= (1 << h) - 1; i++) { cin >> a[i]; sum += a[i]; } for (int i = 1; i <= (1 << g) - 1; i++) { while (true) { long long v = pull(i); if (v) { sum -= v; ans.push_back(i); } else break; } } cout << sum << endl; for (auto v : ans) cout << v << ; cout << endl; } int main() { int t; ios::sync_with_stdio(0); cin >> t; while (t--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; int sum = n; for (int i = n / 2; i >= 1; i--) { if (n % i == 0) { sum += i; n = i; } } cout << sum; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; inline long long fexp(long long b, long long e) { long long x = 1; for (; e; e >>= 1, b = (b * b) % (1000000007)) if (e & 1) x = (x * b) % (1000000007); return x; } long long n, k, ok, i, j, x; set<long long> S; signed main() { ios_base::sync_with_stdio(0); cin >> n >> k; ok = 1; for (x = 1; x <= k && ok; x++) { S.clear(); for (i = 1; i <= x; i++) { if (S.count(n % i)) ok = 0; else S.insert(n % i); } } cout << (ok ? Yes : No ) << endl; return 0; return 0; }
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_rx.v
//----------------------------------------------------------------------------//
// File: axi_basic_rx.v //
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // tkeep width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [STRB_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd (trn_rd ),
.trn_rsof (trn_rsof ),
.trn_reof (trn_reof ),
.trn_rsrc_rdy (trn_rsrc_rdy ),
.trn_rdst_rdy (trn_rdst_rdy ),
.trn_rsrc_dsc (trn_rsrc_dsc ),
.trn_rrem (trn_rrem ),
.trn_rerrfwd (trn_rerrfwd ),
.trn_rbar_hit (trn_rbar_hit ),
.trn_recrc_err (trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid (null_rx_tvalid ),
.null_rx_tlast (null_rx_tlast ),
.null_rx_tkeep (null_rx_tkeep ),
.null_rdst_rdy (null_rdst_rdy ),
.null_is_eof (null_is_eof ),
// System
//-----------
.np_counter (np_counter ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
axi_basic_rx_null_gen #(
.C_DATA_WIDTH (C_DATA_WIDTH ),
.TCQ (TCQ ),
.STRB_WIDTH (STRB_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid (null_rx_tvalid ),
.null_rx_tlast (null_rx_tlast ),
.null_rx_tkeep (null_rx_tkeep ),
.null_rdst_rdy (null_rdst_rdy ),
.null_is_eof (null_is_eof ),
// System
//-----------
.user_clk (user_clk ),
.user_rst (user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, d, h; cin >> n >> d >> h; if (h * 2 < d) { cout << -1; return 0; } if (d == 1) { if (n >= 3) { cout << -1; return 0; } if (n == 2) { cout << 1 << << 2; return 0; } } for (int i = 2; i <= h + 1; i++) { cout << i << << i - 1 << endl; } int b = d - h; if (b > 0) { cout << 1 << << h + 2 << endl; for (int i = h + 3; i <= d + 1; i++) { cout << i << << i - 1 << endl; } } int hd = 1; if (b == 0) { hd = 2; } for (int i = d + 2; i <= n; i++) { cout << hd << << i << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, a[111169], sum = 0; int main() { int x, y; cin >> n >> m; for (int i = (0); i < n; i += 1) cin >> a[i]; for (int i = (0); i < m; i += 1) { cin >> x >> y; sum += min(a[x - 1], a[y - 1]); } cout << sum; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DLATCH_P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a[n], b[n]; for (long long i = 0; i < n; i++) { cin >> a[i] >> b[i]; } long long sum = 0; long long price = 99999; for (long long i = 0; i < n; i++) { price = min(price, b[i]); sum += price * a[i]; } cout << sum << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 3; struct tree { long long sum; int tag; int lc; int rc; } a[N << 1]; long long s[N]; int n, m, t = 1; long long ans; long long win; vector<pair<long long, long long> > other, change; inline int read() { int v = 0, c = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) c = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { v = v * 10 + ch - 48; ch = getchar(); } return v * c; } inline void pushup(int u) { a[u].sum = a[a[u].lc].sum + a[a[u].rc].sum; } inline void pushdown(int u, int l, int r) { if (a[u].tag) { int mid = (l + r) >> 1; a[a[u].lc].sum = mid - l + 1 - a[a[u].lc].sum; a[a[u].lc].tag ^= 1; a[a[u].rc].sum = r - mid - a[a[u].rc].sum; a[a[u].rc].tag ^= 1; } a[u].tag = 0; } void build(int u, int l, int r) { if (l == r) return; int mid = (l + r) >> 1; a[u].lc = ++t; build(a[u].lc, l, mid); a[u].rc = ++t; build(a[u].rc, mid + 1, r); pushup(u); } long long query(int u, int l, int r, int ll, int rr, int w) { if (l == ll && r == rr) { if (w == 1) return a[u].sum; return r - l + 1 - a[u].sum; } pushdown(u, l, r); int mid = (l + r) >> 1; if (rr <= mid) return query(a[u].lc, l, mid, ll, rr, w); else if (ll > mid) return query(a[u].rc, mid + 1, r, ll, rr, w); else return query(a[u].lc, l, mid, ll, mid, w) + query(a[u].rc, mid + 1, r, mid + 1, rr, w); } void updata(int u, int l, int r, int ll, int rr) { if (l == ll && r == rr) { a[u].sum = r - l + 1 - a[u].sum; a[u].tag ^= 1; return; } pushdown(u, l, r); int mid = (l + r) >> 1; if (rr <= mid) updata(a[u].lc, l, mid, ll, rr); else if (ll > mid) updata(a[u].rc, mid + 1, r, ll, rr); else { updata(a[u].lc, l, mid, ll, mid); updata(a[u].rc, mid + 1, r, mid + 1, rr); } pushup(u); } int main() { n = read(), m = read(); for (int i = 1; i <= n; ++i) s[i] = (long long)read(); sort(s + 1, s + n + 1); for (int i = 1; i <= m; ++i) { int l = read(), r = read(); l = lower_bound(s + 1, s + n + 1, l) - s; r = upper_bound(s + 1, s + n + 1, r) - s - 1; if (l > r) continue; change.push_back(make_pair(l, r)); other.push_back(make_pair(r, l)); } build(1, 1, n); sort(change.begin(), change.end()); sort(other.begin(), other.end()); ans = (long long)(n - 2) * (n - 1) * n / 6; for (int i = 1, r = 0, l = 0; i <= n; ++i) { while (l < change.size() && change[l].first == i) { updata(1, 1, n, change[l].first, change[l].second); l++; } win = 0; if (i != 1) win += query(1, 1, n, 1, i - 1, 0); if (i != n) win += query(1, 1, n, i + 1, n, 1); ans -= win * (win - 1) / 2; while (r < other.size() && other[r].first == i) { updata(1, 1, n, other[r].second, other[r].first); r++; } } cout << ans << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:14:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: EECS301_Lab4_TopLevel
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: EECS301 Lab 4 Top Level File
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module EECS301_Lab4_TopLevel
#(
// These parameters are listed here so they can be overridden in simulation.
parameter KEY_LOCK_DELAY = 500000000, // 500 ms
parameter SW_DEBOUNCE_TIME = 10000000 // 10 mS
)
(
// Clock Signals
input CLOCK_50,
// LED Signals
output [9:0] LEDR,
// 7-Segment Display Signals (Active-Low)
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
// Button Signals (Active-Low)
input [3:0] KEY,
// Switch Signals
input [9:0] SW
);
localparam CLOCK_50_RATE = 50000000; // 50 MHz
//
// Show the Switch position value on the Status LEDs (0 = off, 1 = on)
//
assign LEDR = SW;
////////////////////////////////////////////////////////
//
// System Reset Controller
//
wire sys_reset;
System_Reset_Module
#(
.REF_CLK_RATE_HZ( CLOCK_50_RATE ),
.POWER_ON_DELAY( 500 ) // 500 ns
)
sys_reset_ctrl
(
// Input Signals
.PLL_LOCKED( 1'b1 ), // No PLL so force true
.REF_CLK( CLOCK_50 ),
// Output Signals
.RESET( sys_reset )
);
////////////////////////////////////////////////////////
//
// Key Input Synchronizers
//
wire key_add;
wire key_sub;
wire key_clr;
Key_Synchronizer_Bank
#(
.KEY_SYNC_CHANNELS( 3 ),
.CLK_RATE_HZ( CLOCK_50_RATE ),
.KEY_LOCK_DELAY( KEY_LOCK_DELAY ) // nS
)
key_sync_bank
(
// Input Signals
.KEY( { ~KEY[3], ~KEY[1:0] } ),
// Output Signals
.KEY_EVENT( { key_clr, key_sub, key_add } ),
// System Signals
.CLK( CLOCK_50 )
);
////////////////////////////////////////////////////////
//
// Switch Input Debounce Synchronizers
//
wire [9:0] calc_operand;
Switch_Synchronizer_Bank
#(
.SWITCH_SYNC_CHANNELS( 10 ),
.CLK_RATE_HZ( CLOCK_50_RATE ),
.DEBOUNCE_TIME( SW_DEBOUNCE_TIME ),
.SIG_OUT_INIT( 1'b0 )
)
switch_sync_bank
(
// Input Signals (asynchronous)
.SIG_IN( SW ),
// Output Signals (synchronized to CLK domain)
.SIG_OUT( calc_operand ),
// System Signals
.CLK( CLOCK_50 )
);
////////////////////////////////////////////////////////
//
// Key Controller
//
wire cmd_clear;
wire cmd_compute;
wire cmd_operation;
wire cmd_done;
Key_Command_Controller key_commander
(
// Key Input Signals
.KEY_CLEAR( key_clr ),
.KEY_ADD( key_add ),
.KEY_SUB( key_sub ),
// Command Signals
.CMD_DONE( cmd_done ),
.CMD_CLEAR( cmd_clear ),
.CMD_COMPUTE( cmd_compute ),
.CMD_OPERATION( cmd_operation ),
// System Signals
.CLK( CLOCK_50 ),
.RESET( sys_reset )
);
////////////////////////////////////////////////////////
//
// Calculator
//
localparam CALC_DATA_WIDTH = 10;
localparam CALC_RESULT_WIDTH = 18;
wire calc_result_ready;
wire [CALC_RESULT_WIDTH-1:0] calc_result_data;
Calculator_Module
#(
.DATA_WIDTH( CALC_DATA_WIDTH ),
.RESULT_WIDTH( CALC_RESULT_WIDTH )
)
calculator
(
// Control Signals
.DONE( cmd_done ),
.CLEAR( cmd_clear ),
.COMPUTE( cmd_compute ),
.OPERATION( cmd_operation ), // 0=Add, 1=Sub
.CALC_DATA( calc_operand ),
// Result Signals
.RESULT_READY( calc_result_ready ),
.RESULT_DATA( calc_result_data ),
// System Signals
.CLK( CLOCK_50 ),
.RESET( sys_reset )
);
////////////////////////////////////////////////////////
//
// Compute Absolute Value of Calc Result
//
wire [CALC_RESULT_WIDTH-1:0] abs_result_data;
FxP_ABS_Function
#(
.DATA_WIDTH( CALC_RESULT_WIDTH )
)
calc_result_abs
(
// Data Signals
.DATA_IN( calc_result_data ),
.DATA_ABS( abs_result_data )
);
////////////////////////////////////////////////////////
//
// Result Register to BCD Digits
//
localparam BCD_DIGITS = 5;
wire [BCD_DIGITS*4-1:0] bcd_result;
wire bcd_overflow;
BCD_Binary_Encoder
#(
.BIN_WIDTH( CALC_RESULT_WIDTH ),
.BDC_DIGITS( BCD_DIGITS )
)
result_to_bcd_converter
(
// Control Signals
.CONVERT( calc_result_ready ),
.DONE( ),
.BIN_IN( abs_result_data ),
// BCD Data Output Signals
.BCD_OUT( bcd_result ),
.BCD_OVERFLOW( bcd_overflow ),
// System Signals
.CLK( CLOCK_50 ),
.RESET( sys_reset )
);
////////////////////////////////////////////////////////
//
// Convert BCD Digits to drive Seven Segment Outputs
//
wire [BCD_DIGITS*7-1:0] seg_out;
BCD_Segment_Decoder
#(
.BCD_DIGITS( BCD_DIGITS )
)
bcd_to_7seg_decoders
(
// BCD Input (Packed Array)
.BCD_IN( bcd_result ),
// Seven-Segment Output (Packed Array)
.SEG_OUT( seg_out ),
// System Signals
.CLK( CLOCK_50 )
);
////////////////////////////////////////////////////////
//
// Map the Segment Output values from the packed arry
// to the FPGA output pins.
//
// Note: The hardware signals are active-low so the
// values of seg_out need to be inverted.
//
assign HEX0 = ~seg_out[0*7+:7];
assign HEX1 = ~seg_out[1*7+:7];
assign HEX2 = ~seg_out[2*7+:7];
assign HEX3 = ~seg_out[3*7+:7];
assign HEX4 = ~seg_out[4*7+:7];
assign HEX5[0] = 1'b1; // Unused
assign HEX5[2:1] = bcd_overflow ? 2'h0 : 2'h3; // If overflowed, show "1" else blank
assign HEX5[5:3] = 3'h7; // Unused
assign HEX5[6] = ~calc_result_data[17]; // Show "-" when value is negative
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long long mod = 1e9 + 7; const long long N = 1e5 + 10; struct node { int ind, type, row, color; node(int a, int b, int c, int d) { ind = a; type = b; row = c; color = d; } }; bool comp(node x, node y) { return x.ind < y.ind; } int main() { ios::sync_with_stdio(false); int n, m, k; cin >> n >> m >> k; vector<vector<int> > ans(n, vector<int>(m, 0)); vector<vector<pair<int, int> > > v(2, vector<pair<int, int> >(max(n, m))); for (int i = 0; i < k; i++) { int a, b, c; cin >> a >> b >> c; v[a - 1][b - 1] = make_pair(i, c); } vector<node> vec; for (int i = 0; i < 2; i++) for (int j = 0; j < max(n, m); j++) if (v[i][j].second != 0) vec.push_back(node(v[i][j].first, i, j, v[i][j].second)); sort(vec.begin(), vec.end(), comp); for (int i = 0; i < vec.size(); i++) { if (vec[i].type == 0) { for (int j = 0; j < m; j++) ans[vec[i].row][j] = vec[i].color; } else { for (int j = 0; j < n; j++) ans[j][vec[i].row] = vec[i].color; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cout << ans[i][j] << ; cout << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a[100010]; int s[100010]; int solve() { int ret = 0, top = 0; for (int i = 0; i < n; i++) { while (top && a[s[top]] < a[i]) --top; if (top) ret = max(ret, a[s[top]] ^ a[i]); s[++top] = i; } return ret; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; reverse(a, a + n); int ans = solve(); reverse(a, a + n); ans = max(ans, solve()); cout << ans << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTN_TB_V
`define SKY130_FD_SC_LP__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfrtn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__sdfrtn dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTN_TB_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x7fffffff; int main() { int n; cin >> n; int sum = 0; int zero = 0; for (int i = 0; i < 2 * n; i++) { int x; scanf( %*d.%d , &x); sum += x; if (x == 0) zero++; } int ans = INF; for (int k = 0; k <= n; k++) { if (k + zero < n) continue; ans = min(ans, abs(k * 1000 - sum)); } printf( %d.%03d n , ans / 1000, ans % 1000); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, k; vector<int> cur; unordered_set<long long> bad; unordered_set<int> was; void err() { cout << impossible << endl; exit(0); } void go(int x) { cur.push_back(x); vector<int> g; for (auto it = was.begin(); it != was.end(); it++) if (bad.count(x * 1000000ll + (*it)) == 0) g.push_back(*it); for (int i = 0; i < g.size(); i++) was.erase(g[i]); for (int i = 0; i < g.size(); i++) go(g[i]); } int main() { ios::sync_with_stdio(false); cin >> n >> m >> k; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; x--; y--; bad.insert(x * 1000000ll + y); bad.insert(y * 1000000ll + x); } for (int i = 1; i < n; i++) was.insert(i); vector<vector<int> > comps; for (int i = 1; i < n; i++) if (was.count(i)) { cur.clear(); was.erase(i); go(i); comps.push_back(cur); } int sum = 0; for (int i = 0; i < comps.size(); i++) { int cnt = 0; for (int j = 0; j < comps[i].size(); j++) if (bad.count(comps[i][j]) == 0) cnt++; if (cnt == 0) err(); sum += cnt; } if (k < comps.size() || k > sum) err(); cout << possible << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a41o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21AI_4_V
`define SKY130_FD_SC_HDLL__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21AI_4_V
|
//
// File: zbt_6111.v
// Date: 27-Nov-05
// Author: I. Chuang <>
//
// Simple ZBT driver for the MIT 6.111 labkit, which does not hide the
// pipeline delays of the ZBT from the user. The ZBT memories have
// two cycle latencies on read and write, and also need extra-long data hold
// times around the clock positive edge to work reliably.
//
/////////////////////////////////////////////////////////////////////////////
// Ike's simple ZBT RAM driver for the MIT 6.111 labkit
//
// Data for writes can be presented and clocked in immediately; the actual
// writing to RAM will happen two cycles later.
//
// Read requests are processed immediately, but the read data is not available
// until two cycles after the intial request.
//
// A clock enable signal is provided; it enables the RAM clock when high.
module zbt_6111(clk, cen, we, addr, write_data, read_data,
ram_clk, ram_we_b, ram_address, ram_data, ram_cen_b);
input clk; // system clock
input cen; // clock enable for gating ZBT cycles
input we; // write enable (active HIGH)
input [18:0] addr; // memory address
input [35:0] write_data; // data to write
output [35:0] read_data; // data read from memory
output ram_clk; // physical line to ram clock
output ram_we_b; // physical line to ram we_b
output [18:0] ram_address; // physical line to ram address
inout [35:0] ram_data; // physical line to ram data
output ram_cen_b; // physical line to ram clock enable
// clock enable (should be synchronous and one cycle high at a time)
wire ram_cen_b = ~cen;
// create delayed ram_we signal: note the delay is by two cycles!
// ie we present the data to be written two cycles after we is raised
// this means the bus is tri-stated two cycles after we is raised.
reg [1:0] we_delay;
always @(posedge clk)
we_delay <= cen ? {we_delay[0],we} : we_delay;
// create two-stage pipeline for write data
reg [35:0] write_data_old1;
reg [35:0] write_data_old2;
always @(posedge clk)
if (cen)
{write_data_old2, write_data_old1} <= {write_data_old1, write_data};
// wire to ZBT RAM signals
assign ram_we_b = ~we;
assign ram_clk = 1'b0; // gph 2011-Nov-10
// set to zero as place holder
// assign ram_clk = ~clk; // RAM is not happy with our data hold
// times if its clk edges equal FPGA's
// so we clock it on the falling edges
// and thus let data stabilize longer
assign ram_address = addr;
assign ram_data = we_delay[1] ? write_data_old2 : {36{1'bZ}};
assign read_data = ram_data;
endmodule // zbt_6111
|
module AsymmetricBRAM_Xilinx(
CLK,
RADDR,
RDATA,
REN,
WADDR,
WDATA,
WEN
);
parameter PIPELINED = 'd 0;
parameter FORWARDING = 'd 0;
parameter WADDR_WIDTH = 'd 0;
parameter WDATA_WIDTH = 'd 0;
parameter RADDR_WIDTH = 'd 0;
parameter RDATA_WIDTH = 'd 0;
parameter MEMSIZE = 'd 1;
parameter REGISTERED = (PIPELINED == 0) ? "UNREGISTERED":"CLOCK0";
input CLK;
input [RADDR_WIDTH-1:0] RADDR;
output [RDATA_WIDTH-1:0] RDATA;
input REN;
input [WADDR_WIDTH-1:0] WADDR;
input [WDATA_WIDTH-1:0] WDATA;
input WEN;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxWIDTH = `max(WDATA_WIDTH, RDATA_WIDTH);
localparam minWIDTH = `min(WDATA_WIDTH, RDATA_WIDTH);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:MEMSIZE-1];
reg [RDATA_WIDTH-1:0] readB;
always @(posedge CLK)
begin
if (WEN) begin
RAM[WADDR] <= WDATA;
end
end
always @(posedge CLK)
begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (REN) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{RADDR, lsbaddr}];
end
end
end
assign RDATA = readB;
endmodule
|
/****************************************
Branch
for MIST32 Processor
Takahiro Ito @cpu_labs
****************************************/
`include "core.h"
`default_nettype none
module execute_branch(
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
input wire [31:0] iPC,
input wire [4:0] iFLAG,
input wire [3:0] iCC,
input wire [4:0] iCMD,
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oNOT_JUMP_VALID,
output wire oIB_VALID,
output wire oIDTS_VALID,
output wire oHALT_VALID
);
assign oBRANCH_ADDR = func_branch_addr(
iCMD,
iPC,
iDATA_1
);
function [31:0] func_branch_addr;
input [4:0] func_cmd;
input [31:0] func_pc;
input [31:0] func_source1;
begin
case(func_cmd)
`EXE_BRANCH_BUR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_BR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_B:
begin
func_branch_addr = func_source1;
end
`EXE_BRANCH_INTB:
begin
func_branch_addr = 32'h0;
end
`EXE_BRANCH_IDTS:
begin
func_branch_addr = func_pc + 32'h0000004;
end
default:
begin
func_branch_addr = 32'h0;
end
endcase
end
endfunction
assign oJUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oNOT_JUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? !func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oIB_VALID = (iCMD == `EXE_BRANCH_INTB)? 1'b1 : 1'b0;
assign oIDTS_VALID = (iCMD == `EXE_BRANCH_IDTS)? 1'b1 : 1'b0;
assign oHALT_VALID = (iCMD == `EXE_BRANCH_HALT)? 1'b1 : 1'b0;
function func_ex_branch_check;
input [3:0] func_ex_branch_check_cc;
input [4:0] func_ex_branch_check_flag;
begin
case(func_ex_branch_check_cc)
`CC_AL : func_ex_branch_check = 1'b1;
`CC_EQ :
begin
if(func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_NEQ :
begin
if(!func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_MI :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_PL :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_EN :
begin
if(!func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_ON :
begin
if(func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_OVF :
begin
if(func_ex_branch_check_flag[`FLAGS_OF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_UEO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF] && !func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_UEU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF] || func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_SEO :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SO :
begin
func_ex_branch_check = !((func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF]);
end
`CC_SEU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF];
end
default : func_ex_branch_check = 1'b1;
endcase
end
endfunction
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int main() { int x, x1, y, y1; char a, b; cin >> a >> y >> b >> y1; x1 = a - 96; x = b - 96; int counter = 0; string s[100000]; while (true) { if (x == x1 && y == y1) { break; } if (x > x1) { x1++; s[counter] += R ; } if (x < x1) { x1--; s[counter] += L ; } if (y > y1) { y1++; s[counter] += D ; } if (y < y1) { y1--; s[counter] += U ; } counter++; } cout << counter << endl; for (int i = 0; i < counter; i++) { cout << s[i] << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } void O_o() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0), cout.tie(0); } bool prime(int n, int i) { if (i == n) return true; if (n % i == 0) return false; prime(n, i + 1); } int arr[1000005], arr1[1000005]; unsigned long long sum = 0; int main() { O_o(); int n, s, m; cin >> n; for (int i = 1;; i *= 2) { if (i < 1000005) arr1[i] = 1; else break; } for (int i = 1;; i *= 2) { if (i == n) { s = ((i * 2) - 1); break; } else if (i > n) { s = i - 1; break; } } m = n++; for (int i = 0; i < int(n); i++) { if (arr[s - m] == 0 && arr[m] == 0) arr[s - m] = m, arr[m] = s - m; if (arr1[m] == 1) s = m - 1; if (m == 0) break; m--; } for (int i = 0; i < int(n); i++) sum += (arr[i] ^ i); cout << sum << n ; for (int i = 0; i < int(n); i++) cout << arr[i] << ; cout << n ; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : ddr_axi.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ddr_axi (
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
input app_sr_req,
input app_ref_req,
input app_zq_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [3:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [3:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [3:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [3:0] s_axi_rid,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
input sys_rst
);
// Start of IP top instance
ddr_axi_mig u_ddr_axi_mig (
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.device_temp_i (device_temp_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_TB_V
`define SKY130_FD_SC_LS__NAND4BB_TB_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ls__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_TB_V
|
// `define READ read_good
module top;
reg clk;
reg dout;
reg [7:0] data;
integer lp;
always #10 clk = ~clk; // Build a clock generator.
always @(negedge clk) dout = ~dout; // Build a bit stream.
initial begin
clk = 0;
dout = 0;
@(negedge clk);
for (lp=0; lp<4; lp=lp+1) begin
#0 read_bad(data);
$display("Read(%0d) %b from the bit stream.", lp, data);
#20; // For the fun of it skip a clock.
end
#1 $finish(0);
end
// This one locks up on the third call.
task read_bad;
output [7:0] edata;
integer i;
reg [7:0] rddata;
begin
for(i=7; i>=0; i=i-1) begin
@(posedge clk);
$display(" Reading bit %0d", i);
rddata[i] = dout; // <<--- This appears to be the problem line!
end
assign edata = rddata;
end
endtask
// This one works fine.
task read_good;
output [7:0] edata;
integer i;
reg [7:0] edata;
begin
for(i=7; i>=0; i=i-1) begin
@(posedge clk);
$display(" Reading bit %0d", i);
edata[i] = dout;
end
end
endtask
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12.07.2017 22:01:56
// Design Name:
// Module Name: t_ex
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Just like with t_id, full testing of alu.v is not needed
// as that was done in t_alu. This testbench tests the multiplexers in this block
// to make sure they work as intended, as well as the wires are connected
// correctly. The branch adder is also given a simple test too.
//
//////////////////////////////////////////////////////////////////////////////////
module t_ex;
// Inputs
reg [31:0] pcplus4, srca, regread2, signimm;
reg [4:0] rt, rd;
reg [2:0] alucontrol;
reg alusrc, regdst, regwrite1, memtoreg1, memwrite1, branch1;
// Outputs
wire [31:0] aluresult, pcbranch, writedata;
wire [4:0] writereg;
wire regwrite2, memtoreg2, memwrite2, branch2, zerowire;
execute uut(
.ALUResult( aluresult ),
.PCBranchE( pcbranch ),
.WriteDataE( writedata ),
.WriteRegE( writereg ),
.RegWriteE2( regwrite2 ),
.MemToRegE2( memtoreg2 ),
.MemWriteE2( memwrite2 ),
.BranchE2( branch2 ),
.ZerowireE( zerowire ),
.PCPlus4E( pcplus4 ),
.srcA( srca ),
.RegRead2( regread2 ),
.SignImmE( signimm ),
.rt( rt ),
.rd( rd ),
.ALUControlE( alucontrol ),
.ALUSrcE( alusrc ),
.RegDstE( regdst ),
.RegWriteE1( regwrite1 ),
.MemToRegE1( memtoreg1 ),
.MemWriteE1( memwrite1 ),
.BranchE1( branch1 )
);
initial begin
// Initialise the inputs
pcplus4 = 0; srca = 0; regread2 = 0; signimm = 0;
rt = 0; rd = 0;
alucontrol = 0;
alusrc = 0; regdst = 0; regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
// display test signals
$display(srca);
$display(regread2);
// Wait 100ns for global resets
#100;
// Test RegDst
rt = 5'b01000; rd = 5'b01001; regdst = 1;
#20 regdst = 0; // writereg should switch from 0x09 to 0x08
#20 rt = 0; rd = 0; // reset
#100;
// Test ALUSrc with ALUControl (i.e. simulate a I-type and R-type instruction)
#20 srca = 32'h00001111; regread2 = 32'hFFFF0000; signimm = 32'hFFFFFFFF; alusrc = 0; alucontrol = 3'b001; // r-type or instruction
// expected output should be 00001111 OR FFFF0000 = FFFF1111; writedata = 32'hFFFF0000; zerowire = 0;
#20 alusrc = 1; // i-type or instruction, expected output should be 00001111 OR FFFFFFFF = FFFFFFFF; writedata = 32'hFFFF0000; zerowire = 0;
#20 srca = 0; regread2 = 0; signimm = 0; alusrc = 0; alucontrol = 3'b000; // reset
#100;
// Test Branch Circuit
pcplus4 = 32'h00000004; signimm = 32'h00000001; // expected output: pcbranch = 4 + (1<<2) = 32'h00000008;
// Test Follow-through signals
#20 regwrite1 = 1; memtoreg1 = 1; memwrite1 = 1; branch1 = 1;
// expected output regwrite2 = 1; memtoreg2 = 1; memwrite2 = 1; branch2 = 1;
#20 regwrite1 = 0; memtoreg1 = 0; memwrite1 = 0; branch1 = 0;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; int n, first, second, a, b, m, d[(1 << 17) + 5], p[(1 << 17) + 5]; vector<int> g[(1 << 17) + 5]; bool check(int nod, int par, int del, int hg) { int kids = g[nod].size(); if (par) kids--; if (nod == del) { if (hg == 1) return 0; else if (hg == 2) { if (kids != 1) return 0; for (int i : g[nod]) { if (i != par) return check(i, nod, del, hg - 1); } } else { if (kids != 3) return 0; for (int i : g[nod]) { if (i != par) kids -= check(i, nod, del, hg - 1); } if (kids != 2) return 0; for (int i : g[nod]) { if (i != par) kids -= check(i, nod, del, hg - 2); } if (kids != 0) return 0; return 1; } } else { if (hg == 1) return (kids == 0); else { if (kids != 2) return 0; for (int i : g[nod]) { if (i != par) kids -= check(i, nod, del, hg - 1); } return (kids == 0); } } } bool good(int del, int root) { return check(root, 0, del, n); } int32_t main() { ios_base ::sync_with_stdio(0); cin.tie(); cout.tie(); cin >> n; m = (1 << n) - 2; for (int i = 1; i < m; i++) { cin >> first >> second; g[first].push_back(second); g[second].push_back(first); } for (int i = 1; i <= m; i++) { if (g[i].size() == 2) { int gd = 1; for (int j : g[i]) { if (g[j].size() == 1) gd = 0; } if (gd) b = i; else a = i; } else if (g[i].size() == 4) a = i; } if (a && b && good(a, b)) { cout << 1 << n << a; return 0; } int st = 0; for (int i = 1; i <= m; i++) { if (g[i].size() == 1) st = i; } queue<int> q; d[st] = 1; p[st] = 0; q.push(st); while (q.size()) { int nod = q.front(); q.pop(); for (int i : g[nod]) { if (!d[i]) d[i] = d[nod] + 1, p[i] = nod, q.push(i); } } st = 0; for (int i = 1; i <= m; i++) { if (d[i] == 2 * n - 2) st = i; } for (int i = 1; i <= n - 2; i++) st = p[st]; a = st; b = p[st]; if (a && b && good(a, a)) { cout << 2 << n << min(a, b) << << max(a, b); return 0; } cout << 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, d, h, i, p, q, s; cin >> n >> d >> h; if (d > (2 * h)) { cout << -1 ; } else if ((d == 1) && (h == 1)) { if (n == 2) { cout << 1 2 ; } else { cout << -1 ; } } else if ((d == h)) { for (i = 1; i <= h - 1; i++) { cout << i << << i + 1 << endl; } p = h + 2; for (i = h + 1; i <= n; i++) { cout << h << << i << endl; } } else { if (d > h) { for (i = 1; i <= h; i++) { cout << i << << i + 1 << endl; } cout << 1 << h + 2 << endl; for (i = (h + 2); i <= d; i++) { cout << i << << i + 1 << endl; } for (i = (d + 2); i <= n; i++) { cout << 1 << i << endl; } } } }
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> ostream& operator<<(ostream& out, const pair<A, B>& p) { out << ( << p.first << , << p.second << ) ; return out; } template <typename A, typename B> void printP(const pair<A, B>& p, const char* str = NULL) { if (!(1 && !1)) return; if (str != NULL) cout << str << : ; cout << ( << p.first << , << p.second << ) ; } template <typename T> void printV(const vector<T>& v, const char* str = NULL) { if (!(1 && !1)) return; if (str != NULL) cout << str << : ; for (int i = 0; i < (v.size()); ++i) cout << v[i] << ; cout << endl; } template <typename T> void printC(T& container, const char* str = NULL) { if (!(1 && !1)) return; if (str != NULL) cout << str << : ; for (__typeof((container).begin()) it = ((container).begin()); it != (container).end(); ++it) { cout << (*it) << ; } cout << endl; } const int INF = 1000010111; const int S_N = 152; const int MOD = 1000000007; int main() { int n; cin >> n; vector<int> t1, t2; for (int i = 0; i < n; i++) { int thick, width; cin >> thick >> width; ((thick == 1) ? t1 : t2).push_back(width); } sort(t1.begin(), t1.end(), greater<int>()); sort(t2.begin(), t2.end(), greater<int>()); int mini = INF; for (int c1 = 0; c1 <= t1.size(); c1++) { for (int c2 = 0; c2 <= t2.size(); c2++) { int tSum = 1 * c1 + 2 * c2; int wSum = 0; for (int i = c1; i < t1.size(); i++) wSum += t1[i]; for (int i = c2; i < t2.size(); i++) wSum += t2[i]; if (tSum >= wSum) mini = min(mini, tSum); } } cout << mini << endl; return 0; }
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// lvt_1ht.v: Onehot-coded LVT (Live-Value-Table) //
// //
// Author: Ameer M.S. Abdelhadi (, ) //
// Switched SRAM-based Multi-ported RAM; University of British Columbia, 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module lvt_1ht
#( parameter MEMD = 16, // memory depth
parameter nRP = 1 , // number of reading ports
parameter nWP = 3 , // number of writing ports
parameter WAWB = 1 , // allow Write-After-Write (need to bypass feedback ram)
parameter RAWB = 1 , // new data for Read-after-Write (need to bypass output ram)
parameter RDWB = 0 , // new data for Read-During-Write
parameter ZERO = 0 , // binary / Initial RAM with zeros (has priority over FILE)
parameter FILE = "" // initialization file, optional
)( input clk , // clock
input [ nWP-1:0] WEnb , // write enable for each writing port
input [`log2(MEMD)*nWP-1:0] WAddr, // write addresses - packed from nWP write ports
input [`log2(MEMD)*nRP-1:0] RAddr, // read addresses - packed from nRP read ports
output reg [nWP *nRP-1:0] RBank); // read bank selector - packed from nRP read ports
localparam ADRW = `log2(MEMD); // address width
localparam LVTW = nWP - 1 ; // required memory width
// Register write addresses, data and enables
reg [ADRW*nWP-1:0] WAddr_r; // registered write addresses - packed from nWP write ports
reg [ nWP-1:0] WEnb_r ; // registered write enable for each writing port
always @(posedge clk) begin
WAddr_r <= WAddr;
WEnb_r <= WEnb ;
end
// unpacked/pack addresses and data
reg [ADRW -1:0] WAddr2D [nWP-1:0] ; // write addresses / 2D
reg [ADRW -1:0] WAddr2D_r [nWP-1:0] ; // registered write addresses / 2D
wire [LVTW*nRP -1:0] RDataOut2D [nWP-1:0] ; // read data out / 2D
reg [LVTW -1:0] RDataOut3D [nWP-1:0][nRP -1:0]; // read data out / 3D
reg [ADRW*LVTW-1:0] RAddrFB2D [nWP-1:0] ; // read address fb / 2D
reg [ADRW -1:0] RAddrFB3D [nWP-1:0][LVTW-1:0]; // read address fb / 3D
wire [LVTW*LVTW-1:0] RDataFB2D [nWP-1:0] ; // read data fb / 2D
reg [LVTW -1:0] RDataFB3D [nWP-1:0][LVTW-1:0]; // read data fb / 3D
reg [LVTW -1:0] WDataFB2D [nWP-1:0] ; // write data / 2D
reg [LVTW -1:0] InvData2D [nWP-1:0] ; // write data / 2D
reg [nWP -1:0] RBank2D [nRP-1:0] ; // read bank selector / 2D
`ARRINIT;
always @* begin
// packing/unpacking arrays into 1D/2D/3D structures; see utils.vh for definitions
`ARR1D2D(nWP, ADRW, WAddr , WAddr2D );
`ARR1D2D(nWP, ADRW, WAddr_r , WAddr2D_r );
`ARR2D1D(nRP, nWP , RBank2D , RBank );
`ARR2D3D(nWP, nRP , LVTW, RDataOut2D, RDataOut3D);
`ARR3D2D(nWP, LVTW, ADRW, RAddrFB3D , RAddrFB2D );
`ARR2D3D(nWP, LVTW, LVTW, RDataFB2D , RDataFB3D );
end
// generate and instantiate mulriread BRAMs
genvar wpi;
generate
for (wpi=0 ; wpi<nWP ; wpi=wpi+1) begin: RPORTwpi
// feedback multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nWP-1 ), // number of reading ports
.BYPS (WAWB||RDWB||RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_fdb ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [LVTW -1:0]
.RAddr (RAddrFB2D[wpi] ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataFB2D[wpi] )); // read data - packed from nRP read ports - out: [LVTW *nRP-1:0]
// output multiread ram instantiation
mrram #( .MEMD (MEMD ), // memory depth
.DATW (LVTW ), // data width
.nRP (nRP ), // number of reading ports
.BYPS (RDWB ? 2 : RAWB), // bypass? 0:none; 1:single-stage; 2:two-stages
.ZERO (ZERO ), // binary / Initial RAM with zeros (has priority over FILE)
.FILE (FILE )) // initialization file, optional
mrram_out ( .clk (clk ), // clock - in
.WEnb (WEnb_r[wpi] ), // write enable (1 port) - in
.WAddr (WAddr2D_r[wpi] ), // write address (1 port) - in : [`log2(MEMD) -1:0]
.WData (WDataFB2D[wpi] ), // write data (1 port) - in : [LVTW -1:0]
.RAddr (RAddr ), // read addresses - packed from nRP read ports - in : [`log2(MEMD)*nRP-1:0]
.RData (RDataOut2D[wpi])); // read data - packed from nRP read ports - out: [LVTW *nRP-1:0]
end
endgenerate
// combinatorial logic for output and feedback functions
integer wp; // write port counter
integer wf; // write feedback counter
integer rf; // read feedback counter
integer rp; // read port counter
integer lv; // lvt bit counter
integer fi; // feedback bit index
always @* begin
// generate inversion vector
for(wp=0;wp<nWP;wp=wp+1) InvData2D[wp] = (1<<wp)-1; // 2^wp-1
// initialize output read bank
for(rp=0;rp<nRP;rp=rp+1)
for(wp=0;wp<nWP;wp=wp+1)
RBank2D[rp][wp] = 1;
// generate feedback functions
for(wp=0;wp<nWP;wp=wp+1) begin
wf = 0;
for(lv=0;lv<LVTW;lv=lv+1) begin
wf=wf+(lv==wp);
rf=wp-(wf<wp);
fi=wp-(InvData2D[wp][lv]);
RAddrFB3D[wp][lv] = WAddr2D[wf];
WDataFB2D[wp][lv] = RDataFB3D[wf][rf][fi] ^ InvData2D[wp][lv];
for(rp=0;rp<nRP;rp=rp+1) RBank2D[rp][wp] = RBank2D[rp][wp] && (( RDataOut3D[wf][rp][fi] ^ InvData2D[wp][lv]) == RDataOut3D[wp][rp][lv]);
wf=wf+1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool bSearch(int* toys, int item, int from, int to) { if (from > to) return false; else { int midPoint = (from + to) / 2; if (item < toys[midPoint]) return bSearch(toys, item, from, midPoint - 1); else if (item == toys[midPoint]) return true; else return bSearch(toys, item, midPoint + 1, to); } } int main() { int n, m; scanf( %d %d , &n, &m); int toys[n]; for (int i = 0; i < n; i++) { scanf( %d , &toys[i]); } sort(toys, toys + n); long long int counter = 0; vector<int> v; for (int i = 1; i <= 1000000000 && i <= m && counter < m; i++) { if (!bSearch(toys, i, 0, n - 1)) { counter += i; if (counter <= m) v.push_back(i); } } printf( %d n , v.size()); for (int i = 0; i < v.size(); i++) { printf( %d , v[i]); } printf( n ); }
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 10; int a[N]; int vis[N]; int sum[4 * N]; void up(int id, int l, int r, int pos, int val) { if (l == r) { sum[id] = val; return; } int mid = l + r >> 1; if (pos <= mid) up(id << 1, l, mid, pos, val); else up(id << 1 | 1, mid + 1, r, pos, val); sum[id] = max(sum[id << 1], sum[id << 1 | 1]); } int qu(int id, int l, int r, int ql, int qr) { if (ql <= l && r <= qr) return sum[id]; int mx = 0; int mid = l + r >> 1; if (ql <= mid) mx = max(mx, qu(id << 1, l, mid, ql, qr)); if (qr > mid) mx = max(mx, qu(id << 1 | 1, mid + 1, r, ql, qr)); return mx; } int main() { int n; cin >> n; for (int i = 1; i <= (n); ++i) cin >> a[i]; int q; cin >> q; int h; int le = 0; int pre = 0; for (int i = 1; i <= q; ++i) { int ty; cin >> ty; if (ty == 1) { int pos, val; cin >> pos >> val; vis[pos] = i; a[pos] = val; } else { cin >> h; up(1, 1, q, i, h); } } for (int i = 1; i <= (n); ++i) { int le = qu(1, 1, q, vis[i], q); if (le > a[i]) printf( %d , le); else printf( %d , a[i]); } }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { register long long x = 0, f = 1; register char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = x * 10 + c - 48, c = getchar(); return x * f; } long long t, l, r, tot, cnt; long long f[50 + 5][2520 + 5][50 + 5], in[2520 + 5], a[2520 + 5], bas[2520 + 5]; long long gcd(long long a, long long b) { return !b ? a : gcd(b, a % b); } long long dfs(long long p, long long sum, long long lcm, bool limit) { if (!p) return sum % lcm == 0 ? 1 : 0; if (!limit && f[p][sum][in[lcm]] != -1) return f[p][sum][in[lcm]]; long long up = limit ? a[p] : 9, ans = 0; for (register long long i = 0; i <= up; ++i) { if (i == 0) ans += dfs(p - 1, sum * 10 % 2520, lcm, limit && (i == up)); else ans += dfs(p - 1, (sum * 10 + i) % 2520, lcm * i / gcd(lcm, i), limit && (i == up)); } if (!limit) f[p][sum][in[lcm]] = ans; return ans; } long long calc(long long x) { cnt = 0; while (x) a[++cnt] = x % 10, x /= 10; return dfs(cnt, 0, 1, 1); } signed main() { t = read(); memset(f, -1, sizeof(f)); ; for (register long long i = 1; i <= 2520; ++i) if (2520 % i == 0) in[i] = (++(tot)); while (t--) l = read(), r = read(), printf( %lld n , calc(r) - calc(l - 1)); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
// Test for trace file interface aliasing
typedef struct packed {
integer val100;
integer val200;
} struct_t;
interface ifc (input logic clk,
input integer cyc);
integer value;
struct_t the_struct;
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
ifc intf_1(.*);
ifc intf_2(.*);
always @(*) begin
intf_1.value = cyc + 1;
intf_2.value = cyc + 2;
end
sub_struct s1 (.intf_for_struct(intf_1));
sub_struct s2 (.intf_for_struct(intf_2));
sub_check c1 (.intf_for_check(intf_1));
sub_check c2 (.intf_for_check(intf_2));
sub_all a (.intf_one(intf_1),
.intf_two(intf_2));
// Intentionally longer scope name
sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2),
.intf_two(intf_1));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (intf_1.value != 21) $stop;
if (intf_2.value != 22) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_struct
(
ifc intf_for_struct
);
always @(*) begin
intf_for_struct.the_struct.val100 = intf_for_struct.value + 100;
intf_for_struct.the_struct.val200 = intf_for_struct.value + 200;
end
endmodule
module sub_check
(
ifc intf_for_check
);
`ifdef NO_INLINE_A
//verilator no_inline_module
`endif
always @(posedge intf_for_check.clk) begin
if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop;
if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop;
end
endmodule
module sub_all
(
ifc intf_one,
ifc intf_two
);
`ifdef NO_INLINE_B
//verilator no_inline_module
`endif
ifc intf_in_sub_all (
.clk(intf_one.clk),
.cyc(intf_one.cyc)
);
assign intf_in_sub_all.value = intf_one.value + 1000;
sub_check ac1 (.intf_for_check(intf_one));
sub_check ac2 (.intf_for_check(intf_two));
sub_struct as3 (.intf_for_struct(intf_in_sub_all));
sub_check ac3 (.intf_for_check(intf_in_sub_all));
endmodule
|
`timescale 1ns/1ps
module video_to_block_fifo #(
parameter BUFFER_SIZE = 9
)(
input clk,
input rst,
input i_enable,
input i_video_hsync,
input i_video_sof_stb,
input [7:0] i_red,
input [7:0] i_green,
input [7:0] i_blue,
//Memory FIFO Interface
input i_rfifo_clk,
input i_rfifo_rst,
output o_rfifo_ready,
input i_rfifo_activate,
input i_rfifo_strobe,
output [24:0] o_rfifo_data,
output [23:0] o_rfifo_size
);
//Local Parameters
//Registers/Wires
wire w_write_ready;
reg r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_stb;
reg [24:0] r_write_data;
reg r_used;
reg [23:0] r_count; //XXX: Don't need this in the final design but it's good for debugging
//Submodules
block_fifo #(
.DATA_WIDTH (25 ),
.ADDRESS_WIDTH (BUFFER_SIZE )
) bf (
.reset (rst | i_rfifo_rst ),
//write side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (r_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_stb ),
.write_data (r_write_data ),
//read size
.read_clock (i_rfifo_clk ),
.read_strobe (i_rfifo_strobe ),
.read_ready (o_rfifo_ready ),
.read_activate (i_rfifo_activate ),
.read_count (o_rfifo_size ),
.read_data (o_rfifo_data )
);
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
r_write_stb <= 0;
if (rst) begin
r_write_activate <= 0;
r_write_stb <= 0;
r_write_data <= 0;
r_used <= 0;
r_count <= 0;
end
else begin
if (i_enable && !r_write_activate && w_write_ready) begin
r_write_activate <= 1;
r_used <= 0;
r_count <= 0;
end
if (r_write_activate) begin
if (i_video_hsync) begin
r_write_data <= {i_video_sof_stb, i_red, i_green, i_blue};
r_write_stb <= 1;
r_used <= 1;
r_count <= r_count + 1;
end
else if (r_used) begin
r_write_activate <= 0;
end
end
end
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: R_SEQ.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module R_SEQ (
address,
clock,
q);
input [7:0] address;
input clock;
output [127:0] q;
wire [127:0] sub_wire0;
wire [127:0] q = sub_wire0[127:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({128{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "R_SEQ.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=Rseq",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 128,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "Rseq"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "R_SEQ.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "R_SEQ.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=Rseq"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL R_SEQ_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long n, k; cin >> n >> k; if (k >= n / 2) cout << n * (n - 1) / 2; else cout << n * (n - 1) / 2 - (n - 2 * k) * (n - 2 * k - 1) / 2; return 0; }
|
module opc5lscpu( input[15:0] din, input clk, input reset_b, input int_b, input clken, output vpa, output vda, output[15:0] dout, output[15:0] address, output rnw);
parameter MOV=4'h0,AND=4'h1,OR=4'h2,XOR=4'h3,ADD=4'h4,ADC=4'h5,STO=4'h6,LD=4'h7,ROR=4'h8,NOT=4'h9,SUB=4'hA,SBC=4'hB,CMP=4'hC,CMPC=4'hD,BSWP=4'hE,PSR=4'hF;
parameter FETCH0=3'h0,FETCH1=3'h1,EA_ED=3'h2,RDMEM=3'h3,EXEC=3'h4,WRMEM=3'h5,INT=3'h6 ;
parameter EI=3,S=2,C=1,Z=0,P0=15,P1=14,P2=13,IRLEN=12,IRLD=16,IRSTO=17,IRGETPSR=18,IRPUTPSR=19,IRRTI=20,IRCMP=21,INT_VECTOR=16'h0002;
reg [15:0] OR_q, PC_q, PCI_q, result;
reg [21:0] IR_q; (* RAM_STYLE="DISTRIBUTED" *)
reg [15:0] dprf_q[15:0];
reg [2:0] FSM_q;
reg [3:0] swiid,PSRI_q;
reg [7:0] PSR_q ;
reg zero,carry,sign,enable_int,reset_s0_b,reset_s1_b;
wire predicate = IR_q[P2] ^ (IR_q[P1]?(IR_q[P0]?PSR_q[S]:PSR_q[Z]):(IR_q[P0]?PSR_q[C]:1));
wire predicate_din = din[P2] ^ (din[P1]?(din[P0]?PSR_q[S]:PSR_q[Z]):(din[P0]?PSR_q[C]:1));
wire [15:0] dprf_dout_p2 = (IR_q[7:4]==4'hF) ? PC_q: {16{(IR_q[7:4]!=4'h0)}} & dprf_q[IR_q[7:4]]; // Port 2 always reads source reg
wire [15:0] dprf_dout = (IR_q[3:0]==4'hF) ? PC_q: {16{(IR_q[3:0]!=4'h0)}} & dprf_q[IR_q[3:0]]; // Port 1 always reads dest reg
wire [15:0] operand = (IR_q[IRLEN]||IR_q[IRLD]) ? OR_q : dprf_dout_p2; // For one word instructions operand comes from dprf
assign {rnw, dout, address} = { !(FSM_q==WRMEM), dprf_dout, ( FSM_q==WRMEM || FSM_q == RDMEM)? OR_q : PC_q };
assign {vpa,vda} = {((FSM_q==FETCH0)||(FSM_q==FETCH1)||(FSM_q==EXEC)),((FSM_q==RDMEM)||(FSM_q==WRMEM)) };
always @( * )
begin
case (IR_q[11:8]) // no real need for STO entry but include it so all instructions are covered, no need for default
LD,MOV,PSR,STO :{carry,result} = {PSR_q[C],(IR_q[IRGETPSR])?{8'b0,PSR_q}:operand} ;
AND,OR :{carry,result} = {PSR_q[C],(IR_q[8])?(dprf_dout & operand):(dprf_dout | operand)};
ADD,ADC :{carry,result} = dprf_dout + operand + (IR_q[8] & PSR_q[C]);
SUB,SBC,CMP,CMPC :{carry,result} = dprf_dout + (operand ^ 16'hFFFF) + ((IR_q[8])?PSR_q[C]:1);
XOR,BSWP :{carry,result} = {PSR_q[C],(!IR_q[11])?(dprf_dout ^ operand):{operand[7:0],operand[15:8] }};
NOT,ROR :{result,carry} = (IR_q[8])?{~operand,PSR_q[C]}:{PSR_q[C],operand} ;
endcase // case ( IR_q )
{swiid,enable_int,sign,carry,zero} = (IR_q[IRPUTPSR])?operand[7:0]:(IR_q[3:0]!=4'hF)?{PSR_q[7:3],result[15],carry,!(|result)}:PSR_q;
end // always @ ( * )
always @(posedge clk)
if (clken) begin
{reset_s0_b,reset_s1_b} <= {reset_b,reset_s0_b};
if (!reset_s1_b)
{PC_q,PCI_q,PSRI_q,PSR_q,FSM_q} <= 0;
else begin
case (FSM_q)
FETCH0 : FSM_q <= (din[IRLEN]) ? FETCH1 : (!predicate_din) ? FETCH0 : ((din[11:8]==LD) || (din[11:8]==STO)) ? EA_ED : EXEC;
FETCH1 : FSM_q <= (!predicate )? FETCH0: ((IR_q[3:0]!=0) || (IR_q[IRLD]) || IR_q[IRSTO]) ? EA_ED : EXEC;
EA_ED : FSM_q <= (!predicate )? FETCH0: (IR_q[IRLD]) ? RDMEM : (IR_q[IRSTO]) ? WRMEM : EXEC;
RDMEM : FSM_q <= EXEC;
EXEC : FSM_q <= ((!int_b & PSR_q[EI])||(IR_q[IRPUTPSR] && (|swiid)))?INT:(IR_q[3:0]==4'hF)?FETCH0: (din[IRLEN]) ? FETCH1 : // go to fetch0 if PC or PSR affected by exec
((din[11:8]==LD) || (din[11:8]==STO) ) ? EA_ED : // load/store have to go via EA_ED
(din[P2] ^ (din[P1] ? (din[P0] ? sign : zero): (din[P0] ? carry : 1))) ? EXEC : FETCH0; // short cut to exec on all predicates
//(din[15:13]==3'b000)? EXEC : EA_ED; // or short cut on always only
WRMEM : FSM_q <= (!int_b & PSR_q[EI])?INT:FETCH0;
default: FSM_q <= FETCH0;
endcase // case (FSM_q)
OR_q <= (FSM_q == FETCH0 || FSM_q==EXEC)? 16'b0 : (FSM_q==EA_ED) ? dprf_dout_p2 + OR_q : din;
if ( FSM_q == INT )
{PC_q,PCI_q,PSRI_q,PSR_q[EI]} <= {INT_VECTOR,PC_q,PSR_q[3:0],1'b0} ; // Always clear EI on taking interrupt
else if ( FSM_q == FETCH0 || FSM_q == FETCH1 )
PC_q <= PC_q + 1;
else if ( FSM_q == EXEC ) begin
PC_q <= (IR_q[IRRTI])?PCI_q:(IR_q[3:0]==4'hF)?result:((!int_b && PSR_q[EI]) || (IR_q[IRPUTPSR] && (|swiid)))?PC_q:PC_q + 1;
PSR_q <= (IR_q[IRRTI])?{4'b0,PSRI_q}:{swiid,enable_int,sign,carry,zero}; // Clear SWI bits on return
if (!IR_q[IRCMP])
dprf_q[IR_q[3:0]] <= result ;
end
if ( FSM_q == FETCH0 || FSM_q == EXEC)
IR_q <= {((din[11:8]==CMP)||(din[11:8]==CMPC)),{3{(din[11:8]==PSR)}}&{(din[3:0]==4'hF),(din[3:0]==4'h0),(din[7:4]==4'b0)},(din[11:8]==STO),(din[11:8]==LD),din};
end // else: !if(!reset_s1_b)
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_FUNCTIONAL_PP_V
|
module wallace(x,y,p);
input [7:0] x,y;
output [15:0] p;
wire [6:0] ip1;
wire [7:0] ip2,ip3,ip4,ip5,ip6,ip7,ip8,si,iip;
wire [6:0] s1,s2,s3,s4,s5,s6;
wire [7:0] c1,c2,c3,c4,c5,c6,c7;
wire c;
// first AND array
and fi1(p[0],y[0],x[0]);
and fi2(ip1[0],y[0],x[1]);
and fi3(ip1[1],y[0],x[2]);
and fi4(ip1[2],y[0],x[3]);
and fi5(ip1[3],y[0],x[4]);
and fi6(ip1[4],y[0],x[5]);
and fi7(ip1[5],y[0],x[6]);
and fi8(ip1[6],y[0],x[7]);
not n1(si[0],ip1[6]);
// second AND array and NOT GATES
and se1(ip2[0],y[1],x[0]);
and se2(ip2[1],y[1],x[1]);
and se3(ip2[2],y[1],x[2]);
and se4(ip2[3],y[1],x[3]);
and se5(ip2[4],y[1],x[4]);
and se6(ip2[5],y[1],x[5]);
and se7(ip2[6],y[1],x[6]);
and se8(ip2[7],y[1],x[7]);
not n2(si[1],ip2[7]);
//third
and th1(ip3[0],y[2],x[0]);
and th2(ip3[1],y[2],x[1]);
and th3(ip3[2],y[2],x[2]);
and th4(ip3[3],y[2],x[3]);
and th5(ip3[4],y[2],x[4]);
and th6(ip3[5],y[2],x[5]);
and th7(ip3[6],y[2],x[6]);
and th8(ip3[7],y[2],x[7]);
not n3(si[2],ip3[7]);
//fourth
and fo1(ip4[0],y[3],x[0]);
and fo2(ip4[1],y[3],x[1]);
and fo3(ip4[2],y[3],x[2]);
and fo4(ip4[3],y[3],x[3]);
and fo5(ip4[4],y[3],x[4]);
and fo6(ip4[5],y[3],x[5]);
and fo7(ip4[6],y[3],x[6]);
and fo8(ip4[7],y[3],x[7]);
not n4(si[3],ip4[7]);
//fifth
and fif1(ip5[0],y[4],x[0]);
and fif2(ip5[1],y[4],x[1]);
and fif3(ip5[2],y[4],x[2]);
and fif4(ip5[3],y[4],x[3]);
and fif5(ip5[4],y[4],x[4]);
and fif6(ip5[5],y[4],x[5]);
and fif7(ip5[6],y[4],x[6]);
and fif8(ip5[7],y[4],x[7]);
not n5(si[4],ip5[7]);
//sixth
and si1(ip6[0],y[5],x[0]);
and si2(ip6[1],y[5],x[1]);
and si3(ip6[2],y[5],x[2]);
and si4(ip6[3],y[5],x[3]);
and si5(ip6[4],y[5],x[4]);
and si6(ip6[5],y[5],x[5]);
and si7(ip6[6],y[5],x[6]);
and si8(ip6[7],y[5],x[7]);
not n6(si[5],ip6[7]);
//seventh
and sev1(ip7[0],y[6],x[0]);
and sev2(ip7[1],y[6],x[1]);
and sev3(ip7[2],y[6],x[2]);
and sev4(ip7[3],y[6],x[3]);
and sev5(ip7[4],y[6],x[4]);
and sev6(ip7[5],y[6],x[5]);
and sev7(ip7[6],y[6],x[6]);
and sev8(ip7[7],y[6],x[7]);
not n7(si[6],ip7[7]);
//eight
and eii1(iip[0],y[7],x[0]);
and eii2(iip[1],y[7],x[1]);
and eii3(iip[2],y[7],x[2]);
and eii4(iip[3],y[7],x[3]);
and eii5(iip[4],y[7],x[4]);
and eii6(iip[5],y[7],x[5]);
and eii7(iip[6],y[7],x[6]);
and eii8(iip[7],y[7],x[7]);
xor ei1(ip8[0],y[7],iip[0]);
xor ei2(ip8[1],y[7],iip[1]);
xor ei3(ip8[2],y[7],iip[2]);
xor ei4(ip8[3],y[7],iip[3]);
xor ei5(ip8[4],y[7],iip[4]);
xor ei6(ip8[5],y[7],iip[5]);
xor ei7(ip8[6],y[7],iip[6]);
xor ei8(ip8[7],y[7],iip[7]);
not n8(si[7],ip8[7]);
//first adder array
HA ha1(ip1[0],ip2[0],c1[0],p[1]);
FA fa1(ip1[1],ip2[1],ip3[0],c1[1],s1[0]);
FA fa2(ip1[2],ip2[2],ip3[1],c1[2],s1[1]);
FA fa3(ip1[3],ip2[3],ip3[2],c1[3],s1[2]);
FA fa4(ip1[4],ip2[4],ip3[3],c1[4],s1[3]);
FA fa5(ip1[5],ip2[5],ip3[4],c1[5],s1[4]);
FA fa6(ip1[6],ip2[6],ip3[5],c1[6],s1[5]);
FA fa7(si[0],si[1],ip3[6],c1[7],s1[6]);
//second adder array
HA ha2(s1[0],c1[0],c2[0],p[2]);
FA sa1(s1[1],c1[1],ip4[0],c2[1],s2[0]);
FA sa2(s1[2],c1[2],ip4[1],c2[2],s2[1]);
FA sa3(s1[3],c1[3],ip4[2],c2[3],s2[2]);
FA sa4(s1[4],c1[4],ip4[3],c2[4],s2[3]);
FA sa5(s1[5],c1[5],ip4[4],c2[5],s2[4]);
FA sa6(s1[6],c1[6],ip4[5],c2[6],s2[5]);
FA sa7(si[2],c1[7],ip4[6],c2[7],s2[6]);
//third adder
HA ha3(s2[0],c2[0],c3[0],p[3]);
FA ta1(s2[1],ip5[0],c2[1],c3[1],s3[0]);
FA ta2(s2[2],ip5[1],c2[2],c3[2],s3[1]);
FA ta3(s2[3],ip5[2],c2[3],c3[3],s3[2]);
FA ta4(s2[4],ip5[3],c2[4],c3[4],s3[3]);
FA ta5(s2[5],ip5[4],c2[5],c3[5],s3[4]);
FA ta6(s2[6],ip5[5],c2[6],c3[6],s3[5]);
FA ta7(si[3],ip5[6],c2[7],c3[7],s3[6]);
//fourth adder
HA ha4(s3[0],c3[0],c4[0],p[4]);
FA foa1(s3[1],ip6[0],c3[1],c4[1],s4[0]);
FA foa2(s3[2],ip6[1],c3[2],c4[2],s4[1]);
FA foa3(s3[3],ip6[2],c3[3],c4[3],s4[2]);
FA foa4(s3[4],ip6[3],c3[4],c4[4],s4[3]);
FA foa5(s3[5],ip6[4],c3[5],c4[5],s4[4]);
FA foa6(s3[6],ip6[5],c3[6],c4[6],s4[5]);
FA foa7(si[4],ip6[6],c3[7],c4[7],s4[6]);
//fifth adder
HA ha5(s4[0],c4[0],c5[0],p[5]);
FA fia1(s4[1],ip7[0],c4[1],c5[1],s5[0]);
FA fia2(s4[2],ip7[1],c4[2],c5[2],s5[1]);
FA fia3(s4[3],ip7[2],c4[3],c5[3],s5[2]);
FA fia4(s4[4],ip7[3],c4[4],c5[4],s5[3]);
FA fia5(s4[5],ip7[4],c4[5],c5[5],s5[4]);
FA fia6(s4[6],ip7[5],c4[6],c5[6],s5[5]);
FA fia7(si[5],ip7[6],c4[7],c5[7],s5[6]);
//sixth adder
HA ha6(s5[0],c5[0],c6[0],p[6]);
FA sia1(s5[1],ip8[0],c5[1],c6[1],s6[0]);
FA sia2(s5[2],ip8[1],c5[2],c6[2],s6[1]);
FA sia3(s5[3],ip8[2],c5[3],c6[3],s6[2]);
FA sia4(s5[4],ip8[3],c5[4],c6[4],s6[3]);
FA sia5(s5[5],ip8[4],c5[5],c6[5],s6[4]);
FA sia6(s5[6],ip8[5],c5[6],c6[6],s6[5]);
FA sia7(si[6],ip8[6],c5[7],c6[7],s6[6]);
//seventh adder
FAd sea0(s6[0],c6[0],y[7],c7[0],p[7]);
FAd sea1(s6[1],c6[1],c7[0],c7[1],p[8]);
FAd sea2(s6[2],c6[2],c7[1],c7[2],p[9]);
FAd sea3(s6[3],c6[3],c7[2],c7[3],p[10]);
FAd sea4(s6[4],c6[4],c7[3],c7[4],p[11]);
FAd sea5(s6[5],c6[5],c7[4],c7[5],p[12]);
FAd sea6(s6[6],c6[6],c7[5],c7[6],p[13]);
FAd sea7(si[7],c6[7],c7[6],c7[7],p[14]);
HA ha8(c7[7],1'b1,c,p[15]);
endmodule
module HA(a,b,c,s);
input a,b;
output c,s;
xor x1(s,a,b);
and a1(c,a,b);
endmodule
module FA(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y;
xor x1(x,a,b);
xnor x2(y,a,b);
MUX m1(x,y,c,sm);
MUX m2(a,c,x,cy);
endmodule
module MUX(i0,i1,s,o);
input i0,i1,s;
output o;
wire t,p,q;
and a1(t,s,i1);
not n0(p,s);
and a2(q,p,i0);
or a3(o,t,q);
endmodule
module FAd(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y,z;
xor x1(x,a,b);
xor x2(sm,x,c);
and a1(y,a,b);
and a2(z,x,c);
or o1(cy,y,z);
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream fin( lol.in ); ofstream fout( lol.out ); char c; int m[10][10], ok; int main() { ios::sync_with_stdio(false); for (int i = 1; i <= 6; ++i) { m[1][i] = m[6][i] = 100; m[i][1] = m[i][6] = 100; } for (int i = 2; i <= 5; ++i) { for (int j = 2; j <= 5; ++j) { cin >> c; if (c == x ) m[i][j] = 1; if (c == o ) m[i][j] = 100; } } for (int i = 2; i <= 5; ++i) { for (int j = 2; j <= 5; ++j) { if (m[i][j] + m[i + 1][j] + m[i + 2][j] == 2) ok = 1; if (m[i][j] + m[i + 1][j + 1] + m[i + 2][j + 2] == 2) ok = 1; if (m[i][j] + m[i + 1][j - 1] + m[i + 2][j - 2] == 2) ok = 1; if (m[i][j] + m[i][j + 1] + m[i][j + 2] == 2) ok = 1; if (ok == 1) { cout << YES ; return 0; } } } if (ok == 1) { cout << YES ; return 0; } else cout << NO ; return 0; }
|
#include <bits/stdc++.h> using namespace std; typedef struct graph { list<int> edges[1001]; } graph; void dfs(graph *g, int i, int group[], int gn) { for (list<int>::iterator it = g->edges[i].begin(); it != g->edges[i].end(); it++) { if (group[*it] == -1) { group[*it] = gn; dfs(g, *it, group, gn); } } } void printArray(int arr[], int n) { for (int i = 1; i <= n; i++) cout << arr[i] << ; cout << endl; } int main() { int n; graph *g = new graph; cin >> n; bool flag = false; int fin[1001], pref[1001], group[1001]; for (int i = 1; i <= n; i++) cin >> fin[i]; for (int i = 1; i <= n; i++) { cin >> pref[i]; if (i + pref[i] <= n) { g->edges[i].push_back(i + pref[i]); g->edges[i + pref[i]].push_back(i); } if (i - pref[i] >= 1) { g->edges[i].push_back(i - pref[i]); g->edges[i - pref[i]].push_back(i); } } fill_n(group, n + 1, -1); int gn = 0; for (int i = 1; i <= n; i++) { if (group[i] == -1) { group[i] = gn; dfs(g, i, group, gn); gn++; } } for (int i = 1; i <= n; i++) { if (group[i] == group[fin[i]]) { } else { flag = true; cout << NO << endl; break; } } if (!flag) { cout << YES << endl; } }
|
#include <bits/stdc++.h> using namespace std; int n, sz[1005], lab[1005], cur = 1, cur2, f = 1; vector<int> v[1005]; int getsz(int node, int p) { sz[node] = 1; for (int u : v[node]) { if (u != p) sz[node] += getsz(u, node); } return sz[node]; } int find(int node, int p) { for (int u : v[node]) { if (u != p && sz[u] > n / 2) return find(u, node); } return node; } void assign(int node, int p) { if (f) lab[node] = cur++; else lab[node] = (++cur2) * cur; printf( %d %d %d n , node, p, lab[node] - lab[p]); for (int u : v[node]) { if (u != p) assign(u, node); } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); v[a].push_back(b); v[b].push_back(a); } getsz(1, 0); int c = find(1, 0); getsz(c, 0); vector<pair<int, int> > ch; for (int u : v[c]) ch.push_back({sz[u], u}); sort(ch.begin(), ch.end()); reverse(ch.begin(), ch.end()); for (auto p : ch) { assign(p.second, c); if (f && n <= 3 * cur && 3 * cur <= 2 * n) f = 0; } }
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#include <bits/stdc++.h> const int N = 1000005; std::vector<int> e[N]; int a[N], n, m, x, y, r[N], c[N], id[N], cnt, cnt2, s[N], vis[N]; void dfs(int x) { if (vis[x]) return; vis[x] = 1; for (auto u : e[x]) { dfs(u); a[x] |= a[u]; } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); e[x].push_back(y); r[y]++; c[x]++; } for (int i = 1; i <= n; i++) if (!c[i]) a[i] = 1 << cnt, id[i] = cnt++; for (int i = 1; i <= n; i++) if (!r[i]) { dfs(i); s[cnt2++] = a[i]; } for (int i = 1; i < (1 << cnt) - 1; i++) { int t = 0, S = 0, t2 = 0; for (int j = 0; j < cnt; j++) if (i & (1 << j)) t++, S |= s[j]; for (int j = 0; j < cnt; j++) if (S & (1 << j)) t2++; if (t2 <= t) { puts( NO ); return 0; } } puts( YES ); return 0; }
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg a;
integer i;
initial begin
vec = 4'b0000;
a = 0;
if (vec !== 4'b0000) begin
$display("FAILED -- initialized vec to %b", vec);
$finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
#1 { a, vec[i] } <= 2'b11;
end
#1 if (vec !== 4'b1111) begin
$display("FAILED == vec (%b) is not 1111", vec);
$finish;
end
if (a !== 1'b1) begin
$display("FAILED -- a (%b) is not 1", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; bool flag = false; int n, m, K; int up[2005][2005], down[2005][2005]; int Find(int p[], int x) { return p[x] != x ? p[x] = Find(p, p[x]) : x; } void check(int x, int y, int i, int &g, int &h, int &L) { if (i < 1 || i > n) return; int j; j = Find(up[i], y); if (j != 0) { int d = abs(x - i) + abs(y - j); if (d < L || d == L && (!flag && (i < g || i == g && j < h) || flag && (j < h || j == h && i < g))) L = d, g = i, h = j; } j = Find(down[i], y); if (j != m + 1) { int d = abs(x - i) + abs(y - j); if (d < L || d == L && (!flag && (i < g || i == g && j < h) || flag && (j < h || j == h && i < g))) L = d, g = i, h = j; } } int main() { scanf( %d%d%d , &n, &m, &K); if (n > m) { swap(n, m); flag = true; } for (int i = 1; i <= n; i++) for (int j = 0; j <= m + 1; j++) up[i][j] = down[i][j] = j; while (K--) { int x, y; scanf( %d%d , &x, &y); if (flag) swap(x, y); int g = -1, h = -1, L = 0x7fffffff; for (int i = 0; i <= L; i++) { check(x, y, x - i, g, h, L); check(x, y, x + i, g, h, L); } up[g][h] = h - 1; down[g][h] = h + 1; if (flag) swap(g, h); printf( %d %d n , g, h); } return 0; }
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#include <bits/stdc++.h> const int N = 100005; using namespace std; int n, a[N], b[N], flag[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), b[i] = 1; int now = a[n]; for (int i = n - 1; i >= 1; i--) { if (now > a[i]) b[i] = -1, flag[i] = 1, now = now - a[i]; else b[i] = 1, flag[i] = -1, now = a[i] - now; } int yh = 1; for (int i = 1; i <= n; i++) { if (b[i] * yh == 1) printf( + ); else printf( - ); yh *= flag[i]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int readInt() { bool minus = false; int result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = result * 10 + (ch - 0 ); } if (minus) return -result; else return result; } template <class T> T mulmod(T a, T b) { if (b == 0) return 0; if (b == 1) return a; T x = mulmod(a, b >> 1); x = (x + x) % 1000000007; if (b & 1) x = (x + a) % 1000000007; return x; } template <class T> T larger(T a, T b) { return (a > b ? a : b); } template <class T> T smaller(T a, T b) { return (a < b ? a : b); } template <class T> T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return (a * b) / gcd(a, b); } template <class T> string converter(T n) { stringstream x; x << n; return x.str(); } template <class T> T pw(T a, T b) { if (b == 0) return 1; T x = pw(a, b >> 1); x = (x * x) % 1000000007; if (b & 1) x = (x * a) % 1000000007; return x; } template <class T1> void deb(T1 e1) { cout << e1 << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } char totalDiff(char a, char b) { for (char c = a ; c <= z ; c++) if (c != a && c != b) return c; } void letsgo() { int n, t; cin >> n >> t; string a, b, c; cin >> a >> b; int i, same = 0; for (i = 0; i < n; i++) { same += (a[i] == b[i]); } c = ; if (same >= n - t) { int j = n - t; for (i = 0; i < n; i++) { if (a[i] == b[i] && j) c.push_back(a[i]), j--; else c.push_back(totalDiff(a[i], b[i])); } cout << c; return; } int j = n - t - same; int l = j; int k = same; if (2 * j > n - same) { cout << -1; return; } for (i = 0; i < n; i++) { if (a[i] == b[i] && k) { c.push_back(a[i]); k--; } else if (j) { c.push_back(a[i]); j--; } else if (l) { c.push_back(b[i]); l--; } else { c.push_back(totalDiff(a[i], b[i])); } } cout << c; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; letsgo(); int t; cin >> t; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 5; const int mod = 1e9 + 7; long long n, k, arr[MAX], ans = 0; int main(int argc, char** argv) { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; if (n == 1) { cout << 0; exit(0); } bool moded = true; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); long long modu = arr[0] % k; for (int i = 0; i < n; i++) if (arr[i] % k != modu) moded = false; if (moded) for (int i = 0; i < n; i++) ans += (arr[i] - arr[0]) / k; else ans = -1; cout << ans; return 0; }
|
#include <bits/stdc++.h> const long double eps = 0.00000001; const long long MOD = 1e9 + 7; const double PI = 3.141592653589793238463; using namespace std; long long ans; int was[1010][1010]; int main() { fflush(stdin); cout << fixed, cout.precision(18); ios_base::sync_with_stdio(false); int i, j, n, m; cin >> n >> m; string second[n]; for (i = 0; i < n; ++i) cin >> second[i]; vector<pair<pair<int, int>, int>> ve; for (i = 1; i < n - 1; ++i) { for (j = 1; j < m - 1; ++j) { if (second[i][j] == . ) continue; int max_len = min(min(i, n - i - 1), min(j, m - j - 1)); if (max_len == 0) continue; int x = i, y = j; for (int len = 1; len <= max_len; ++len) { if (second[i + len][j] == * && second[i - len][j] == * && second[i][j - len] == * && second[i][j + len] == * ) { was[i][j] = 1; was[i + len][j] = was[i - len][j] = was[i][j - len] = was[i][j + len] = 1; if (len == max_len) ve.push_back({{i + 1, j + 1}, len}); continue; } if (len - 1 > 0) ve.push_back({{i + 1, j + 1}, len - 1}); break; } } } bool b = true; for (i = 0; i < n; ++i) for (j = 0; j < m; ++j) if (second[i][j] == * && !was[i][j]) b = false; if (!b) return cout << -1, 0; cout << ve.size() << endl; for (i = 0; i < ve.size(); ++i) { printf( %d %d %d n , ve[i].first.first, ve[i].first.second, ve[i].second); } }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T Abs(T a) { return a > 0 ? a : -a; } void split(string s, string seps, vector<string> &res, bool doEmpty = false) { int start = 0; res.clear(); for (int i = 0; i < s.size(); i++) { if (seps.find(s[i]) != string::npos) { if (doEmpty || i - start > 0) res.push_back(s.substr(start, i - start)); start = i + 1; } } if (doEmpty || s.size() - start > 0) res.push_back(s.substr(start, s.size() - start)); } string Union(vector<string> s, int start = 0) { string res; for (int i = start; i < s.size(); i++) res.append(s[i]); return res; } int main() { string s; int n; cin >> s >> n; vector<string> b(n); vector<int> fn(s.size()); for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) { int k = 0; while (k < s.length()) { int r = s.find(b[i], k); if (r == s.npos) break; fn[r + b[i].size() - 1] = max(fn[r + b[i].size() - 1], r + 1); k = r + 1; } } int best = 0; int bi = 0; int cur = 0; int ci = 0; for (int i = 0; i < s.length(); i++) { if (fn[i]) { int lci = ci; ci = -1; int g = fn[i]; int j = i; while (j >= g) { g = max(g, fn[j]); ci = j; j--; } if (ci == -1) ci = i + 1; cur = i - ci; } cur++; if (cur > best) { best = cur; bi = ci; } } cout << best << << bi; return 0; }
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#include <bits/stdc++.h> using namespace std; vector<int> a[2222]; int dis[2222]; int main() { for (int i = 0; i < 2222; ++i) dis[i] = -1; dis[0] = 0; int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { char c; cin >> c; if (c == # ) a[i].push_back(n + j), a[n + j].push_back(i); } queue<int> q; q.push(0); while (!q.empty()) { int p = q.front(); q.pop(); for (int i = 0; i < a[p].size(); ++i) if (dis[a[p][i]] == -1) { q.push(a[p][i]); dis[a[p][i]] = dis[p] + 1; } } cout << dis[n - 1] << endl; return 0; }
|
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
@modified by Zhiyang Ong on November 1, 2007
The output out signal must be of the data type reg
I had to reallocate this data-type reg.
Correction: It is relabelled to the wire data type since
it is not used again, or explicitly assigned a value in
this module
*/
/*
`include "spdu.v"
`include "demux2to4.v"
`include "selector.v"
*/
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// @modified by Zhiyang Ong on November 1, 2007
// Registers...
// reg out;
/*
reg selectord0, selectord1;
reg spdu0out0, spdu0out1, spdu0out2, spdu0out3;
reg spdu1out0, spdu1out1, spdu1out2, spdu1out3;
reg spdu2out0, spdu2out1, spdu2out2, spdu2out3;
reg spdu3out0, spdu3out1, spdu3out2, spdu3out3;
reg spdu4out0, spdu4out1, spdu4out2, spdu4out3;
reg spdu5out0, spdu5out1, spdu5out2, spdu5out3;
reg spdu6out0, spdu6out1, spdu6out2, spdu6out3;
reg spdu7out0, spdu7out1, spdu7out2, spdu7out3;
reg spdu8out0, spdu8out1, spdu8out2, spdu8out3;
reg spdu9out0, spdu9out1, spdu9out2, spdu9out3;
reg spdu10out0, spdu10out1, spdu10out2, spdu10out3;
reg spdu11out0, spdu11out1, spdu11out2, spdu11out3;
reg spdu12out0, spdu12out1, spdu12out2, spdu12out3;
reg spdu13out0, spdu13out1, spdu13out2, spdu13out3;
reg spdu14out0, spdu14out1, spdu14out2, spdu14out3;
*/
// wires
// @Modified by Zhiyang Ong on November 1, 2007
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; vector<long long> v(n); for (int i = 0; i < n; i++) { string s; cin >> s; long long a = 0; for (int j = 0; j < m; j++) { if (s[j] == 1 ) { a += (1LL << (m - 1 - j)); } } v[i] = a; } sort(v.begin(), v.end()); long long mid = (1LL << (m - 1)) - 1; long long x = (1 << m); for (int i = 0; i < n; i++) { if (v[i] < mid) { if (x % 2 == 0) mid++; x--; } else if (v[i] == mid) { if (x % 2 == 0) { mid++; x--; } else { long long q = mid - 1; int y; while (1) { y = 0; for (int j = 0; j < n; j++) { if (q == v[j]) { q--; y = 1; break; } } if (!y) break; } mid = q; x--; } } else { if (x % 2) { long long q = mid - 1; int y; while (1) { y = 0; for (int j = 0; j < n; j++) { if (q == v[j]) { q--; y = 1; break; } } if (!y) break; } mid = q; } x--; } } for (int j = m - 1; j >= 0; j--) { if (mid & (1LL << j)) { cout << 1; } else cout << 0; } cout << endl; } }
|
// Controller module
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// This is the high level smarts of the RFID tag.
// It decides if and what to send upon a
// packet complete signal from the rx module.
// If we should transmit, it starts up the tx module
// and waits for it to indicate that it is finished.
// We also return a data select signal to the 'top' module
// which mux'es the epc, rn, and adc into the tx module.
// A couple features have been added for EPC compatibility
// 1. Handle persistence
// During a Write command, the reader asks for two successive
// req_rn's. The first is to be our handle. The second is the
// write data cover code. We store the handle as our current handle
// and this condition is kept in a reg tagisopen.
// For reference, see EPC spec - Annex K
//
// 2. Q-slotting for TDMA based on the rng
// Query, QueryAdj and QueryRep commands are used to manage
// the number of time slots. Query and QueryAdj load
// the slotcounter with Q bits of the RN from the rng.
// If slotcounter == 0, tag should TX its RN.
// QueryRep commands cause tag to decrement slotcounter.
// This feature is enabled via the use_q input.
// EPC spec - see Annex J
//
// 3. Unique ID
// Tags should have unique ID's (uid). However, the UID
// should not change in time unless the reader rewrites the ID.
// Ying's ID generator has unstable bits, which violates SPEC
// so we have another option to use a static ID.
// This feature is enabled via the use_uid input.
// use_uid=1 -> Ying's ID, use_uid=0 -> static ID
module controller (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle,
packet_complete, txsetupdone, tx_done,
rx_en, tx_en, docrc, handlematch,
bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn,
use_uid, use_q, comm_enable);
parameter QUERYREP = 9'b000000001;
parameter ACK = 9'b000000010;
parameter QUERY = 9'b000000100;
parameter QUERYADJ = 9'b000001000;
parameter SELECT = 9'b000010000;
parameter NACK = 9'b000100000;
parameter REQRN = 9'b001000000;
parameter READ = 9'b010000000;
parameter WRITE = 9'b100000000;
parameter bitsrcselect_RNG = 2'd0;
parameter bitsrcselect_EPC = 2'd1;
parameter bitsrcselect_ADC = 2'd2;
parameter bitsrcselect_UID = 2'd3;
input reset, clk, rx_overflow, packet_complete, txsetupdone, tx_done;
input [8:0] rx_cmd;
input [15:0] currentrn;
output [15:0] currenthandle;
output rx_en, tx_en, docrc; // current_mode 0: rx mode, 1: tx mode
output [1:0] bitsrcselect;
input [7:0] readwriteptr;
output readfrommsp;
input use_uid, use_q;
input [3:0] rx_q;
input [2:0] rx_updn;
input handlematch, comm_enable;
reg [3:0] rx_q_reg;
reg readfrommsp;
reg [15:0] storedhandle;
reg [1:0] bitsrcselect;
reg docrc;
reg rx_en, tx_en;
reg commstate;
parameter STATE_RX = 1'b0;
parameter STATE_TX = 1'b1;
// See EPC spec Annex K
// First request RN sets our handle
// Second request RN sets the current cover code
// For write data
reg tagisopen;
assign currenthandle = tagisopen ? storedhandle : currentrn;
// Code to handle Q slotting for time-division multiplexing
// We TX our RN when slot counter == 0 for any of the following commands:
// They also have special behaviors:
// Query -> draw new rn, take Q bits of rn as init slot counter
// QueryAdj -> draw new rn, adjust stored Q value as per cmd,
// take Q bits of rn as init slot counter (like a query)
// QueryRep -> decrement existing slot counter value
reg [14:0] slotcounter;
// For query adjust, we will init slot counter based on q_adj
wire [3:0] q_adj, q_up, q_dn;
assign q_up = (rx_q_reg < 4'd15 && rx_updn[2] && rx_updn[1]) ? rx_q_reg + 4'd1 : rx_q_reg;
assign q_dn = (rx_q_reg > 4'd0 && rx_updn[0] && rx_updn[1]) ? rx_q_reg - 4'd1 : rx_q_reg;
assign q_adj = rx_updn[0] ? q_dn : q_up;
// For query, we init slot counter based on rx_q (from the parser module)
// This code takes Q bits of our rn as the new slot counter.
// If we get a query or queryAdj, the state machine will
// set slotcounter = newslotcounter as defined here:
wire [14:0] newslotcounter;
wire [3:0] q_ctl;
assign q_ctl = (rx_cmd == QUERY) ? rx_q : q_adj;
reg [14:0] slotcountermask;
always @ (q_ctl) begin
case(q_ctl)
0: slotcountermask = 15'b000000000000000;
1: slotcountermask = 15'b000000000000001;
2: slotcountermask = 15'b000000000000011;
3: slotcountermask = 15'b000000000000111;
4: slotcountermask = 15'b000000000001111;
5: slotcountermask = 15'b000000000011111;
6: slotcountermask = 15'b000000000111111;
7: slotcountermask = 15'b000000001111111;
8: slotcountermask = 15'b000000011111111;
9: slotcountermask = 15'b000000111111111;
10: slotcountermask = 15'b000001111111111;
11: slotcountermask = 15'b000011111111111;
12: slotcountermask = 15'b000111111111111;
13: slotcountermask = 15'b001111111111111;
14: slotcountermask = 15'b011111111111111;
15: slotcountermask = 15'b111111111111111;
default: slotcountermask = 15'b000000000000000;
endcase
end
assign newslotcounter = currentrn[14:0] & slotcountermask;
always @ (posedge clk or posedge reset) begin
if (reset) begin
commstate <= STATE_RX;
bitsrcselect <= 2'd0;
docrc <= 0;
tx_en <= 0;
rx_en <= 0;
tagisopen <= 0;
rx_q_reg <= 0;
slotcounter <= 0;
storedhandle <= 0;
readfrommsp <= 0;
end else if (commstate == STATE_TX) begin
if(txsetupdone) begin
rx_en <= 0;
end
if(tx_done) begin // tx_done
tx_en <= 0;
commstate <= STATE_RX;
end else begin
tx_en <= 1;
end
end else if (commstate == STATE_RX) begin // rx mode
if(packet_complete) begin
case (rx_cmd)
QUERYREP: begin
tagisopen <= 0;
slotcounter <= slotcounter - 15'd1;
if (comm_enable & ((slotcounter-15'd1)==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
ACK: begin
tagisopen <= 0;
if (comm_enable && handlematch) begin
commstate <= STATE_TX; // send ack.
bitsrcselect <= use_uid ? bitsrcselect_UID : bitsrcselect_EPC;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
QUERY: begin
tagisopen <= 0;
rx_q_reg <= rx_q;
// load slot counter
slotcounter <= newslotcounter;
if (comm_enable & (newslotcounter==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
QUERYADJ: begin
tagisopen <= 0;
rx_q_reg <= q_adj;
// load slot counter
slotcounter <= newslotcounter;
if (comm_enable & (newslotcounter==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
SELECT: begin
tagisopen <= 0;
rx_en <= 0; // reset rx
end
NACK: begin
tagisopen <= 0;
rx_en <= 0; // reset rx
end
REQRN: begin
if (comm_enable && handlematch) begin
// First request RN opens tag, sets handle
if (!tagisopen) begin
storedhandle <= currentrn;
tagisopen <= 1;
end
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
READ: begin
if (comm_enable && handlematch) begin
if (readwriteptr == 0) readfrommsp <= 0;
else readfrommsp <= 1;
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_ADC;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
WRITE: begin
rx_en <= 0; // reset rx
end
default begin
rx_en <= 0; // reset rx
end
endcase
end else if(rx_overflow) begin
rx_en <= 0;
end else begin
rx_en <= 1;
tx_en <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n; getline(cin, s); while (n--) { getline(cin, s); bool L = false, M = false; if (s.length() < 5) { cout << OMG>.< I don t know! << endl; continue; } if (s.substr(0, 5) == miao. ) { M = true; } if (s.substr(s.length() - 5) == lala. ) { L = true; } if (M && L) { cout << OMG>.< I don t know! << endl; } else if (M) { cout << Rainbow s << endl; } else if (L) { cout << Freda s << endl; } else { cout << OMG>.< I don t know! << endl; } } return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Device DNA Data Access Port
// /___/ /\ Filename : DNA_PORT.v
// \ \ / \ Timestamp : Mon Oct 10 14:55:34 PDT 2005
// \___\/\___\
//
// Revision:
// 10/10/05 - Initial version.
// 05/29/07 - Added wire declaration for internal signals
// 04/07/08 - CR 469973 -- Header Description fix
// 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE[56:55]
// 09/18/08 - CR 488646 -- added period check for simprim
// 10/28/08 - IR 494079 -- Shifting of dna_value is corrected to MSB first out
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/27/12 - Removed DRC warning for SIM_DNA_VALUE (CR 669726).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT);
parameter [56:0] SIM_DNA_VALUE = 57'h0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output DOUT;
input CLK, DIN, READ, SHIFT;
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 57;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
reg notifier;
wire clk_in, din_in, gsr_in, read_in, shift_in;
buf b_dout (DOUT, dout_out);
buf b_clk (clk_in, CLK);
buf b_din (din_in, DIN);
buf buf_gsr (gsr_in, GSR);
buf b_read (read_in, READ);
buf b_shift (shift_in, SHIFT);
// GSR has no effect
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE;
dout_out = 1'b1;
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
// IR 494079
// dna_val = {din_in, dna_val[MSB_DNA_BITS :1]};
dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in};
dout_out = dna_val[MSB_DNA_BITS];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (posedge CLK, 0:0:0, notifier);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // DNA_PORT
`endcelldefine
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gsu_cache.v when simulating
// the core, gsu_cache. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsu_cache(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
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