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#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 3e3 + 555; struct node { long long x, y, v; bool operator<(const node& n) const { if (x != n.x) return x < n.x; else return y < n.y; } }; long long pre[maxn][maxn]; node ori[maxn]; inline long long cal(long long hang1, long long lie1, long long hang2, long long lie2) { hang1 = min(hang1, 1000ll); lie1 = min(lie1, 1000ll); hang2 = max(hang2, 1ll); lie2 = max(lie2, 1ll); return pre[hang1][lie1] - pre[hang1][lie2 - 1] - pre[hang2 - 1][lie1] + pre[hang2 - 1][lie2 - 1]; } long long buxuan[maxn]; long long f[maxn]; void init() { f[0] = 1; for (long long i = 1; i < maxn; i++) f[i] = f[i - 1] * i % mod; } inline long long qpow(long long a, long long n) { long long base = a; long long res = 1; while (n) { if (n & 1) res = res * base % mod; base = base * base % mod; n >>= 1; } return res; } long long C(long long n, long long m) { if (n < m) return 0; return f[n] * qpow(f[m], mod - 2) % mod * qpow(f[n - m], mod - 2) % mod; } void solve() { long long n, m, r; scanf( %lld %lld %lld , &n, &m, &r); for (long long i = 1; i <= n; i++) { scanf( %lld %lld %lld , &ori[i].x, &ori[i].y, &ori[i].v); pre[ori[i].x][ori[i].y] = 1; } sort(ori + 1, ori + n + 1); long long ans = 0; for (long long i = 1; i <= 1000; i++) for (long long j = 1; j <= 1000; j++) pre[i][j] += pre[i][j - 1]; for (long long j = 1; j <= 1000; j++) for (long long i = 1; i <= 1000; i++) pre[i][j] += pre[i - 1][j]; long long base = C(n, m); for (long long i = 1; i <= n; i++) { long long wai = n - cal(ori[i].x + r, ori[i].y + r, ori[i].x - r, ori[i].y - r); long long cnt = C(wai, m); buxuan[i] = cnt; ans += ori[i].v * ori[i].v % mod * (base - cnt) % mod; ans %= mod; } for (long long i = 1; i <= n; i++) { for (long long j = 1; j < i; j++) { long long wai = n - cal(ori[i].x + r, ori[i].y + r, ori[i].x - r, ori[i].y - r); wai -= cal(ori[j].x + r, ori[j].y + r, ori[j].x - r, ori[j].y - r); if (ori[i].x - ori[j].x <= r * 2) { if (abs(ori[j].y - ori[i].y) <= r * 2) { if (ori[j].y < ori[i].y) wai = wai + cal(ori[j].x + r, ori[j].y + r, ori[i].x - r, ori[i].y - r) % mod; else wai = wai + cal(ori[j].x + r, ori[i].y + r, ori[i].x - r, ori[j].y - r) % mod; } } long long cnt = (base - buxuan[i] - buxuan[j] + C(wai, m)) % mod; cnt += mod; cnt %= mod; ans += ori[i].v * ori[j].v % mod * 2 % mod * cnt % mod; ans %= mod; } } printf( %lld n , ans); } signed main() { init(); solve(); }
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#include <bits/stdc++.h> using namespace std; int main() { char s1[50], s2[50]; cin >> s1 >> s2; long long left = 0, right = 0, mid = 0, l; l = strlen(s1); for (long long i = 0; i < l; i++) if (s1[i] == | ) { mid = i; break; } left = mid; right = l - (mid + 1); if ((strlen(s1) + strlen(s2) - 1) % 2 == 1) { printf( Impossible ); return 0; } if (left == right) { if (strlen(s2) % 2 == 0) { for (int j = 0; j < left; j++) printf( %c , s1[j]); for (int j = 0; j < strlen(s2) / 2; j++) printf( %c , s2[j]); printf( | ); for (int j = left + 1; j < l; j++) printf( %c , s1[j]); for (int j = strlen(s2) / 2; j < strlen(s2); j++) printf( %c , s2[j]); return 0; } else { printf( Impossible ); return 0; } } if (left < right) { if (right - left > strlen(s2)) { printf( Impossible ); return 0; } else { long long dif = right - left; dif += (strlen(s2) - dif) / 2; for (int j = 0; j < left; j++) printf( %c , s1[j]); for (int j = 0; j < dif; j++) printf( %c , s2[j]); printf( | ); for (int j = left + 1; j < strlen(s1); j++) printf( %c , s1[j]); for (int j = dif; j < strlen(s2); j++) printf( %c , s2[j]); return 0; } } if (right < left) { if (left - right > strlen(s2)) { printf( Impossible ); return 0; } else { long long dif = left - right; dif = (strlen(s2) - dif) / 2; for (int j = 0; j < left; j++) printf( %c , s1[j]); for (int j = 0; j < dif; j++) printf( %c , s2[j]); printf( | ); for (int j = left + 1; j < strlen(s1); j++) printf( %c , s1[j]); for (int j = dif; j < strlen(s2); j++) printf( %c , s2[j]); return 0; } } return 0; }
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//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_NIOS_mult_cell (
// inputs:
M_mul_src1,
M_mul_src2,
clk,
reset_n,
// outputs:
M_mul_cell_result
)
;
output [ 31: 0] M_mul_cell_result;
input [ 31: 0] M_mul_src1;
input [ 31: 0] M_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_result;
wire [ 31: 0] M_mul_cell_result_part_1;
wire [ 15: 0] M_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[15 : 0]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEIVGX",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[31 : 16]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEIVGX",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign M_mul_cell_result = {M_mul_cell_result_part_1[31 : 16] +
M_mul_cell_result_part_2,
M_mul_cell_result_part_1[15 : 0]};
endmodule
|
//---------------------------------------------------------------------//
// Name: addrgen.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Generates addresses.
//---------------------------------------------------------------------//
module addrdecode(
clk,
addr_in,
bank0_addr,
bank1_addr,
bank2_addr,
bank3_addr,
bank4_addr,
bank5_addr,
bank6_addr,
bank7_addr,
bank8_addr,
bank9_addr,
bank10_addr,
bank11_addr,
bank12_addr,
bank13_addr,
bank14_addr,
bank15_addr,
bank16_addr,
bank17_addr,
bank18_addr,
bank19_addr,
bank20_addr,
bank21_addr,
bank22_addr,
bank23_addr,
bank24_addr,
bank25_addr,
bank26_addr,
bank27_addr,
bank28_addr,
bank29_addr,
bank30_addr,
bank31_addr,
sel,
odd
);
input clk;
input [13:0]addr_in;
output [10:0]bank0_addr;
output [10:0]bank1_addr;
output [10:0]bank2_addr;
output [10:0]bank3_addr;
output [10:0]bank4_addr;
output [10:0]bank5_addr;
output [10:0]bank6_addr;
output [10:0]bank7_addr;
output [10:0]bank8_addr;
output [10:0]bank9_addr;
output [10:0]bank10_addr;
output [10:0]bank11_addr;
output [10:0]bank12_addr;
output [10:0]bank13_addr;
output [10:0]bank14_addr;
output [10:0]bank15_addr;
output [10:0]bank16_addr;
output [10:0]bank17_addr;
output [10:0]bank18_addr;
output [10:0]bank19_addr;
output [10:0]bank20_addr;
output [10:0]bank21_addr;
output [10:0]bank22_addr;
output [10:0]bank23_addr;
output [10:0]bank24_addr;
output [10:0]bank25_addr;
output [10:0]bank26_addr;
output [10:0]bank27_addr;
output [10:0]bank28_addr;
output [10:0]bank29_addr;
output [10:0]bank30_addr;
output [10:0]bank31_addr;
output [1:0]sel;
output odd;
reg [10:0] bank0_addr;
reg [10:0] bank1_addr;
reg [10:0] bank2_addr;
reg [10:0] bank3_addr;
reg [10:0] bank4_addr;
reg [10:0] bank5_addr;
reg [10:0] bank6_addr;
reg [10:0] bank7_addr;
reg [10:0] bank8_addr;
reg [10:0] bank9_addr;
reg [10:0] bank10_addr;
reg [10:0] bank11_addr;
reg [10:0] bank12_addr;
reg [10:0] bank13_addr;
reg [10:0] bank14_addr;
reg [10:0] bank15_addr;
reg [10:0] bank16_addr;
reg [10:0] bank17_addr;
reg [10:0] bank18_addr;
reg [10:0] bank19_addr;
reg [10:0] bank20_addr;
reg [10:0] bank21_addr;
reg [10:0] bank22_addr;
reg [10:0] bank23_addr;
reg [10:0] bank24_addr;
reg [10:0] bank25_addr;
reg [10:0] bank26_addr;
reg [10:0] bank27_addr;
reg [10:0] bank28_addr;
reg [10:0] bank29_addr;
reg [10:0] bank30_addr;
reg [10:0] bank31_addr;
reg [1:0] sel_dlya;
reg [1:0] sel_dlyb;
reg [1:0] sel;
reg odd_dlya;
reg odd_dlyb;
reg odd;
wire [10:0] addr = addr_in[13:3];
wire [10:0] addr_pone = addr_in[13:3] + 1;
// We delay odd and sel by 2 cycle to account for:
// (1) cycle of address decode time.
// (1) cycle of memory access time.
always@(posedge clk) begin
odd_dlya <= addr_in[0];
sel_dlya <= addr_in[2:1];
end
always@(posedge clk) begin
odd_dlyb <= odd_dlya;
sel_dlyb <= sel_dlya;
end
always@(posedge clk) begin
odd <= odd_dlyb;
sel <= sel_dlyb;
end
// Decode the address.
always@(posedge clk) begin
case(addr_in[2:1])
2'b00: begin
bank0_addr <= addr;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
bank4_addr <= addr;
bank5_addr <= addr;
bank6_addr <= addr;
bank7_addr <= addr;
bank8_addr <= addr;
bank9_addr <= addr;
bank10_addr <= addr;
bank11_addr <= addr;
bank12_addr <= addr;
bank13_addr <= addr;
bank14_addr <= addr;
bank15_addr <= addr;
bank16_addr <= addr;
bank17_addr <= addr;
bank18_addr <= addr;
bank19_addr <= addr;
bank20_addr <= addr;
bank21_addr <= addr;
bank22_addr <= addr;
bank23_addr <= addr;
bank24_addr <= addr;
bank25_addr <= addr;
bank26_addr <= addr;
bank27_addr <= addr;
bank28_addr <= addr;
bank29_addr <= addr;
bank30_addr <= addr;
bank31_addr <= addr;
end
2'b01: begin
bank0_addr <= addr_pone;
bank1_addr <= addr;
bank2_addr <= addr;
bank3_addr <= addr;
bank4_addr <= addr;
bank5_addr <= addr;
bank6_addr <= addr;
bank7_addr <= addr;
bank8_addr <= addr;
bank9_addr <= addr;
bank10_addr <= addr;
bank11_addr <= addr;
bank12_addr <= addr;
bank13_addr <= addr;
bank14_addr <= addr;
bank15_addr <= addr;
bank16_addr <= addr;
bank17_addr <= addr;
bank18_addr <= addr;
bank19_addr <= addr;
bank20_addr <= addr;
bank21_addr <= addr;
bank22_addr <= addr;
bank23_addr <= addr;
bank24_addr <= addr;
bank25_addr <= addr;
bank26_addr <= addr;
bank27_addr <= addr;
bank28_addr <= addr;
bank29_addr <= addr;
bank30_addr <= addr;
bank31_addr <= addr;
end
2'b10: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr;
bank3_addr <= addr;
bank4_addr <= addr;
bank5_addr <= addr;
bank6_addr <= addr;
bank7_addr <= addr;
bank8_addr <= addr;
bank9_addr <= addr;
bank10_addr <= addr;
bank11_addr <= addr;
bank12_addr <= addr;
bank13_addr <= addr;
bank14_addr <= addr;
bank15_addr <= addr;
bank16_addr <= addr;
bank17_addr <= addr;
bank18_addr <= addr;
bank19_addr <= addr;
bank20_addr <= addr;
bank21_addr <= addr;
bank22_addr <= addr;
bank23_addr <= addr;
bank24_addr <= addr;
bank25_addr <= addr;
bank26_addr <= addr;
bank27_addr <= addr;
bank28_addr <= addr;
bank29_addr <= addr;
bank30_addr <= addr;
bank31_addr <= addr;
end
2'b11: begin
bank0_addr <= addr_pone;
bank1_addr <= addr_pone;
bank2_addr <= addr_pone;
bank3_addr <= addr;
bank4_addr <= addr;
bank5_addr <= addr;
bank6_addr <= addr;
bank7_addr <= addr;
bank8_addr <= addr;
bank9_addr <= addr;
bank10_addr <= addr;
bank11_addr <= addr;
bank12_addr <= addr;
bank13_addr <= addr;
bank14_addr <= addr;
bank15_addr <= addr;
bank16_addr <= addr;
bank17_addr <= addr;
bank18_addr <= addr;
bank19_addr <= addr;
bank20_addr <= addr;
bank21_addr <= addr;
bank22_addr <= addr;
bank23_addr <= addr;
bank24_addr <= addr;
bank25_addr <= addr;
bank26_addr <= addr;
bank27_addr <= addr;
bank28_addr <= addr;
bank29_addr <= addr;
bank30_addr <= addr;
bank31_addr <= addr;
end
endcase
end
endmodule
|
// Copyright 2017 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Unit-level testbench for the BottleRocket core with RISC-V isa tests
`include "BottleRocketCore.v"
`include "MockAXI4LiteSRAM.v"
`define MAXCYCLES 100000
`define TOHOSTADDR 'h00006000
`define SUCCESSCODE 1
module BottleRocketCoreTB(
);
reg clk;
reg reset;
wire imem_awvalid;
wire imem_awready;
wire [31:0] imem_awaddr;
wire [2:0] imem_awprot;
wire [3:0] imem_awcache;
wire imem_wvalid;
wire imem_wready;
wire [31:0] imem_wdata;
wire [3:0] imem_wstrb;
wire imem_bvalid;
wire imem_bready;
wire [1:0] imem_bresp;
wire imem_arvalid;
wire imem_arready;
wire [31:0] imem_araddr;
wire [2:0] imem_arprot;
wire [3:0] imem_arcache;
wire imem_rvalid;
wire imem_rready;
wire [1:0] imem_rresp;
wire [31:0] imem_rdata;
wire dmem_awvalid;
wire dmem_awready;
wire [31:0] dmem_awaddr;
wire [2:0] dmem_awprot;
wire [3:0] dmem_awcache;
wire dmem_wvalid;
wire dmem_wready;
wire [31:0] dmem_wdata;
wire [3:0] dmem_wstrb;
wire dmem_bvalid;
wire dmem_bready;
wire [1:0] dmem_bresp;
wire dmem_arvalid;
wire dmem_arready;
wire [31:0] dmem_araddr;
wire [2:0] dmem_arprot;
wire [3:0] dmem_arcache;
wire dmem_rvalid;
wire dmem_rready;
wire [1:0] dmem_rresp;
wire [31:0] dmem_rdata;
MockAXI4LiteSRAM imem(
.aclk(clk),
.aresetn(~reset),
.awvalid(imem_awvalid),
.awready(imem_awready),
.awaddr(imem_awaddr),
.awprot(imem_awprot),
.awcache(imem_awcache),
.wvalid(imem_wvalid),
.wready(imem_wready),
.wdata(imem_wdata),
.wstrb(imem_wstrb),
.bvalid(imem_bvalid),
.bready(imem_bready),
.bresp(imem_bresp),
.arvalid(imem_arvalid),
.arready(imem_arready),
.araddr(imem_araddr),
.arprot(imem_arprot),
.arcache(imem_arcache),
.rvalid(imem_rvalid),
.rready(imem_rready),
.rresp(imem_rresp),
.rdata(imem_rdata)
);
MockAXI4LiteSRAM dmem(
.aclk(clk),
.aresetn(~reset),
.awvalid(dmem_awvalid),
.awready(dmem_awready),
.awaddr(dmem_awaddr),
.awprot(dmem_awprot),
.awcache(dmem_awcache),
.wvalid(dmem_wvalid),
.wready(dmem_wready),
.wdata(dmem_wdata),
.wstrb(dmem_wstrb),
.bvalid(dmem_bvalid),
.bready(dmem_bready),
.bresp(dmem_bresp),
.arvalid(dmem_arvalid),
.arready(dmem_arready),
.araddr(dmem_araddr),
.arprot(dmem_arprot),
.arcache(dmem_arcache),
.rvalid(dmem_rvalid),
.rready(dmem_rready),
.rresp(dmem_rresp),
.rdata(dmem_rdata)
);
BottleRocketCore core(
.clock(clk),
.reset(reset),
.io_constclk(clk),
.io_nmi(1'b0),
.io_eip(1'b0),
.io_dmi_req_ready(),
.io_dmi_req_valid(1'b0),
.io_dmi_req_bits_addr(7'b0),
.io_dmi_req_bits_data(32'b0),
.io_dmi_req_bits_op(2'b0),
.io_dmi_resp_ready(1'b0),
.io_dmi_resp_valid(),
.io_dmi_resp_bits_data(),
.io_dmi_resp_bits_resp(),
.io_wfisleep(),
.io_traceInst(),
.io_traceRetire(),
.io_traceInterrupt(),
.io_traceEret(),
.io_iBus_aw_valid(imem_awvalid),
.io_iBus_aw_ready(imem_awready),
.io_iBus_aw_bits_addr(imem_awaddr),
.io_iBus_aw_bits_prot(imem_awprot),
.io_iBus_aw_bits_cache(imem_awcache),
.io_iBus_w_valid(imem_wvalid),
.io_iBus_w_ready(imem_wready),
.io_iBus_w_bits_data(imem_wdata),
.io_iBus_w_bits_strb(imem_wstrb),
.io_iBus_b_valid(imem_bvalid),
.io_iBus_b_ready(imem_bready),
.io_iBus_b_bits_resp(imem_bresp),
.io_iBus_ar_valid(imem_arvalid),
.io_iBus_ar_ready(imem_arready),
.io_iBus_ar_bits_addr(imem_araddr),
.io_iBus_ar_bits_prot(imem_arprot),
.io_iBus_ar_bits_cache(imem_arcache),
.io_iBus_r_valid(imem_rvalid),
.io_iBus_r_ready(imem_rready),
.io_iBus_r_bits_resp(imem_rresp),
.io_iBus_r_bits_data(imem_rdata),
.io_dBus_aw_valid(dmem_awvalid),
.io_dBus_aw_ready(dmem_awready),
.io_dBus_aw_bits_addr(dmem_awaddr),
.io_dBus_aw_bits_prot(dmem_awprot),
.io_dBus_aw_bits_cache(dmem_awcache),
.io_dBus_w_valid(dmem_wvalid),
.io_dBus_w_ready(dmem_wready),
.io_dBus_w_bits_data(dmem_wdata),
.io_dBus_w_bits_strb(dmem_wstrb),
.io_dBus_b_valid(dmem_bvalid),
.io_dBus_b_ready(dmem_bready),
.io_dBus_b_bits_resp(dmem_bresp),
.io_dBus_ar_valid(dmem_arvalid),
.io_dBus_ar_ready(dmem_arready),
.io_dBus_ar_bits_addr(dmem_araddr),
.io_dBus_ar_bits_prot(dmem_arprot),
.io_dBus_ar_bits_cache(dmem_arcache),
.io_dBus_r_valid(dmem_rvalid),
.io_dBus_r_ready(dmem_rready),
.io_dBus_r_bits_resp(dmem_rresp),
.io_dBus_r_bits_data(dmem_rdata)
);
integer ncycles;
reg [1023:0] image;
initial begin
if ($value$plusargs("image=%s", image)) begin
$readmemh({image,".hex"}, imem.mem);
$readmemh({image,".hex"}, dmem.mem);
$shm_open({image,".dump.d"});
end else begin
$fatal;
end
$shm_probe("AMC");
$recordvars(core);
ncycles = 0;
clk = 1'b0;
reset = 1'b1;
repeat(20) #5 clk = ~clk;
reset = 1'b0;
forever #5 clk = ~clk;
end
always @(posedge clk) begin
ncycles = ncycles + 1;
if (ncycles > `MAXCYCLES) begin
$info("Failure: timeout!\n");
$shm_close;
$fatal;
end
end
always @(posedge clk) begin
if (dmem_awvalid && dmem_wvalid && dmem_awaddr == `TOHOSTADDR) begin
if (dmem_wdata == `SUCCESSCODE) begin
$info("Success!\n");
$shm_close;
$finish;
end else begin
$info("Failure!\n");
$shm_close;
$fatal;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.06.2017 23:55:46
// Design Name:
// Module Name: instructionfetch
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Initially, the Jump/Branch/+4 decision was done by cascaded
// 2:1 muxs. This was causing a problem as the Jump address was arriving to PCPrime
// (wire) at the same posedge clk cycle that created it. Thus the jump occured in
// the current clock cycle and not in the next clock cycle. The Branch address was
// working as intended as the branch occured in the next cycle. The reason for this
// was that the Branch address had to go through 2 2:1 muxs, and the added
// propagation delay was enough to prevent the signal from reaching PCPrime at the
// same time as the current rising clk signal. PCJump only had to go through 1 mux
// and therefore the propagation delay wasn't enough.
//
// To fix this, I combined both control signals and created a 3:1 mux, (so all 3
// signals shared the same propagation delay) and stored the result into a new
// register (PCPrimeReg). This was to ensure that the next PC address and the
// current PC address remain separated.
//
// Added signals for the registers so I could monitor them on the simulation.
//
// Added reset switch to PC and PCPrimeReg register in order to initialise a 0
// value in them during normal operation.
//////////////////////////////////////////////////////////////////////////////////
module instructionfetch(
output [31:0] PCPlus4F,
output [31:0] instruction,
input [31:0] PCBranchF,
input [27:0] WAinstrF,
input clk, reset, JumpF, PCSrcF
);
wire [31:0] PCJump;
wire [1:0] controlSignals;
reg [31:0] PC, PCPrime;
instrmem instrmem_if(
.A( PC ),
.RD( instruction )
);
assign controlSignals = {JumpF, PCSrcF};
always @ (controlSignals or posedge reset or posedge clk) begin
if(reset) begin
PCPrime <= 0;
end else begin
case (controlSignals)
2'b00: PCPrime <= PCPlus4F;
2'b01: PCPrime <= PCBranchF;
2'b10: PCPrime <= PCJump;
default: PCPrime <= 0;
endcase
end
end
always @ (posedge clk or posedge reset) begin // I have no idea why, but PC required it's own always block, separate to PCPrime. The problem was that the Jump instruction address
if(reset) begin // was skipping PCPrime and being saved straight to PC. When I separated the 2 always blocks, 1 for each register, it appeared to fix
PC <= 0; // the problem. Using 'or' or ',' in the sensitivity list made no difference, perhaps the conflict was the level sensitivity of
end else begin // controlSignals that was causing the signal to go from PCJump -> PCPrime -> PC in 1 clock cycle. In the simulation, the PC register
PC <= PCPrime; // was going from 0 -> 4 -> 0, and skipping the 3rd instruction (in the testjump.dat file) which was the jump file. But it was still
end // functionally jumping, just a clock cycle too early, and the jump instruction appeared to have never been sent. Perhaps, if I lower
end // the clock period, I will be able to see that the jump instruction does get sent and does not get overwritten by the instruction
// that it is jumping to. Although, I am confused because this means that there is something that I don't understand about
// sensitivity lists and non-blocking assignments. I will be more careful in the future.
assign PCJump = {PCPlus4F[31:28], WAinstrF};
assign PCPlus4F = PCPrime + 32'h4;
initial begin
PC = 32'h00000000;
PCPrime = 32'h00000000;
$display(PC);
$display(PCPrime);
end
endmodule
|
`timescale 1ns / 1ps
module SHDCluster #(parameter DNA_DATA_WIDTH = 128, NUM_PES = 8) (
input clk,
input rst,
//Scheduler Interface
input[DNA_DATA_WIDTH - 1:0] dna_in,
input[DNA_DATA_WIDTH*NUM_PES - 1:0] dna_ref_in,
input dna_valid_in,
output dna_rd_en,
//Collector Interface
input coll_clk,
input coll_rd_en,
output[NUM_PES - 1:0] coll_dna_err,
output coll_valid
);
//Register Input
reg[DNA_DATA_WIDTH - 1:0] dna_r;
reg dna_valid_r;
wire pe_fifo_full, pe_fifo_empty;
always@(posedge clk) begin
if(rst) begin
dna_valid_r <= 1'b0;
dna_r <= 0;
end
else begin
if(~pe_fifo_full) begin
dna_valid_r <= dna_valid_in;
dna_r <= dna_in;
end
end
end
wire[NUM_PES - 1:0] dna_err;
genvar i;
generate
for(i = 0; i < NUM_PES; i = i + 1) begin
SHD #(.LENGTH(DNA_DATA_WIDTH)) i_SHD(
.DNA_read(dna_r),
.DNA_ref(dna_ref_in[DNA_DATA_WIDTH*i +: DNA_DATA_WIDTH]),
.DNA_MinErrors(dna_err[i])
);
end
endgenerate
shd_pe_fifo i_pe_fifo (
.wr_clk(clk), // input wire wr_clk
.rd_clk(coll_clk),
.rst(rst), // input wire srst
.din(dna_err), // input wire [7 : 0] din
.wr_en(~pe_fifo_full && dna_valid_r), // input wire wr_en
.rd_en(coll_rd_en & coll_valid), // input wire rd_en
.dout(coll_dna_err), // output wire [7 : 0] dout
.full(pe_fifo_full), // output wire full
.empty(pe_fifo_empty) // output wire empty
);
assign dna_rd_en = ~pe_fifo_full;
assign coll_valid = ~pe_fifo_empty;
endmodule
|
module test
(output reg a,
output reg b,
input wire [1:0] sel,
input wire d
/* */);
always @* begin
b = d;
case (sel)
0:
begin
a = 0;
b = 1;
end
1:
begin
a = 1;
//b = 0; // Pick up input from d instead.
end
default:
begin
a = d;
end
endcase // case (sel)
end // always @ *
endmodule // test
module main;
reg [1:0] sel;
reg d;
wire a, b;
test dut (.a(a), .b(b), .sel(sel), .d(d));
initial begin
d = 0;
sel = 0;
#1 if (a!==0 || b!==1) begin
$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
$finish;
end
sel = 1;
#1 if (a!==1 || b!==0) begin
$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
$finish;
end
sel = 2;
#1 if (a!==0 || b!==0) begin
$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
$finish;
end
d = 1;
#1 if (a!==1 || b!==1) begin
$display("FAILED -- sel=%b, d=%b, a=%b, b=%b", sel, d, a, b);
$finish;
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_SYMBOL_V
`define SKY130_FD_SC_MS__DECAP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { vector<vector<int> > grid; int h, w; cin >> h >> w; grid.assign(h, vector<int>(w, 0)); for (int i = 0; i < h; i++) { for (int j = 0; j < w; j++) { scanf( %d , &grid[i][j]); } } int diff1 = 0; int diff2 = 0; for (int j = 0; j < w; j++) { diff1 += grid[h / 2 - 1][j] - grid[h / 2][j]; diff2 += grid[0][j] - grid[h - 1][j]; } if (abs(diff1) > abs(diff2)) cout << YES << endl; else cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using ll = long long; using namespace std; int n, k, a[110]; int main() { ios::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < k; ++i) cin >> a[i]; vector<int> s; for (int i = 1; i <= n; ++i) s.push_back(i); int curr_leader = 0; for (int i = 0; i < k; ++i) { int elim = (curr_leader + a[i]) % n; cout << s[elim] << ; s.erase(s.begin() + elim); curr_leader = elim; n--; } cout << endl; return 0; }
|
#include <bits/stdc++.h> long long mod = 1e9 + 7, mod2 = 998244353; const int N = int(3e5) + 999; using namespace std; long long fac[10000000]; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long fexp(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % m; b /= 2; a = a * a % m; } return ans; } long long inverse(long long a, long long p) { return fexp(a, p - 2, p); } long long ncr(long long n, long long r, long long p) { if (r == 0) return 1; return (fac[n] * inverse(fac[n - r], p) % p * inverse(fac[r], p) % p) % p; } vector<long long> za(string s) { long long n = s.size(); vector<long long> z(n); long long x = 0, y = 0, p = 0; for (long long i = 1; i < n; i++) { z[i] = max(p, min(z[i - x], y - i + 1)); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) { x = i; y = i + z[i]; z[i]++; } } return z; } void subset(long long a[], long long k) { for (int i = 1; i < pow(2, k); i++) { for (int j = 0; j < k; j++) { if (i & 1 << j) { cout << a[j] << ; } } cout << endl; } } vector<long long> pr(string s) { long long n = s.length(); vector<long long> pi(n); for (int i = 1; i < n; i++) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) j = pi[j - 1]; if (s[i] == s[j]) j++; pi[i] = j; } return pi; } int main() { ios::sync_with_stdio(0); cin.tie(0); long long n, val; cin >> n; long long a[n], c1 = 0, c2 = 0, ans = 0, t = 0; for (long long i = 0; i < n; i++) { cin >> a[i]; if (t % 2 == 0) c1++; else c2++; if (a[i] < 0) t++; if (t % 2 == 0) ans += c1; else ans += c2; } cout << n * (n + 1) / 2 - ans << << ans; return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfrtn (
RESET_B,
CLK_N ,
D ,
Q ,
VPWR ,
VGND
);
// Module ports
input RESET_B;
input CLK_N ;
input D ;
output Q ;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTN_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m; long long mypow(int n, int m) { long long ans = 1, a = 3; while (n > 0) { if (n & 1) ans = ans * a % m; a = a * a % m; n >>= 1; } return ans; } int main() { while (~scanf( %d%d , &n, &m)) { long long ans = mypow(n, m) % m; ans = (ans - 1) % m; ans = (ans + m) % m; printf( %d n , (int)ans); } return 0; }
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "bd_350b_slot_0_w_0,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "bd_350b_slot_0_w_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WI\
DTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_350b_slot_0_w_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__dfxbp (
CLK ,
D ,
Q ,
Q_N ,
VPWR,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_BEHAVIORAL_V
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: udp_jkff.v,v 1.2 2007/08/29 00:01:22 stevewilliams Exp $
module test_jkff;
reg cp;
reg j, k;
reg s, r;
reg qq;
integer errors;
initial errors = 0;
initial
begin
cp <= 0;
#10 {s,r, qq} <= 3'b 10_1;
#10 {s,r, qq} <= 3'b 00_1;
#10 {s,r, qq} <= 3'b x0_1;
#10 {s,r, qq} <= 3'b 00_1;
#10 {s,r, qq} <= 3'b 01_0;
#10 {s,r, qq} <= 3'b 00_0;
#10 {s,r, qq} <= 3'b x0_x;
#10 {s,r, qq} <= 3'b 00_x;
#10 {s,r, qq} <= 3'b 10_1;
#10 {s,r, qq} <= 3'b 11_x;
#10 {s,r, qq} <= 3'b 01_0;
#10 {s,r, qq} <= 3'b 00_0;
#10 {s,r, qq} <= 3'b 01_0;
#10 {s,r, qq} <= 3'b 11_x;
#10 {s,r, qq} <= 3'b 01_0;
#10 {s,r, qq} <= 3'b 00_0;
#10 {cp, j,k, qq} <= 4'b 0_00_0;
#10 {cp, j,k, qq} <= 4'b 1_00_0;
#10 {cp, j,k, qq} <= 4'b 0_01_0;
#10 {cp, j,k, qq} <= 4'b 1_01_0;
#10 {cp, j,k, qq} <= 4'b 0_11_0;
#10 {cp, j,k, qq} <= 4'b 1_11_1;
#10 {cp, j,k, qq} <= 4'b 0_11_1;
#10 {cp, j,k, qq} <= 4'b 1_11_0;
#10 {cp, j,k, qq} <= 4'b 0_00_0;
#10 {cp, j,k, qq} <= 4'b x_00_0;
#10 {cp, j,k, qq} <= 4'b 0_10_0;
#10 {cp, j,k, qq} <= 4'b 1_10_1;
#10 {cp, j,k, qq} <= 4'b x_10_1;
#10 {cp, j,k, qq} <= 4'b 1_10_1;
#10 {cp, j,k, qq} <= 4'b 0_10_1;
#10 {cp, j,k, qq} <= 4'b x_10_1;
#10 {cp, j,k, qq} <= 4'b 0_01_1;
#10 {cp, j,k, qq} <= 4'b x_01_x;
#10 {cp, j,k, qq} <= 4'b 1_01_x;
#10 {cp, j,k, qq} <= 4'b 0_11_x;
#10 {cp, j,k, qq} <= 4'b 1_11_x;
#10 {cp, j,k, qq} <= 4'b 0_01_x;
#10 {cp, j,k, qq} <= 4'b 1_01_0;
#10 {cp, j,k, qq} <= 4'b x_11_0;
#10 {cp, j,k, qq} <= 4'b 1_11_x;
#10 {cp, j,k, qq} <= 4'b 0_10_x;
#10 {cp, j,k, qq} <= 4'b 1_10_1;
#10 {cp, j,k, qq} <= 4'b 0_00_1;
#10;
if (errors > 0)
$display("FAILED");
else
$display("PASSED");
#10 $finish;
end
wire q;
`ifdef FAKE_UDP
// to get a vvp template, from which to build a UDP test vvp
and ff (q, j, k, s, r);
`else
jkff ff (q, cp, j, k, s, r);
`endif
always @(cp or j or k or s or r)
begin
#2;
$display("cp=%b j=%b k=%b s=%b r=%b q=%b", cp, j, k, s, r, q);
if (q !== qq && $time > 2)
begin
$display("FAILED: expect q=%b (time=%t)", qq, $time);
errors = errors + 1;
end
end
endmodule
`ifdef FAKE_UDP
`else
primitive jkff(q, cp, j, k, s, r);
output q;
input cp, j, k, s, r;
reg q;
table
// (cp) jk s r : q : q ;
? ?? (?0) 0 : ? : - ;
? ?? 0 (?0) : ? : - ;
? *? 0 0 : ? : - ;
? ?* 0 0 : ? : - ;
? ?? 1 0 : ? : 1 ;
? ?? 0 1 : ? : 0 ;
? ?? x 0 : 1 : 1 ;
? ?? 0 x : 0 : 0 ;
(?0) ?? 0 0 : ? : - ;
(1x) ?? 0 0 : ? : - ;
(?1) 0? 0 0 : 0 : 0 ;
(?1) ?0 0 0 : 1 : 1 ;
(0x) 0? 0 0 : 0 : 0 ;
(0x) ?0 0 0 : 1 : 1 ;
(01) 1? 0 0 : 0 : 1 ;
(01) ?1 0 0 : 1 : 0 ;
(01) 10 0 0 : x : 1 ;
(01) 01 0 0 : x : 0 ;
endtable
endprimitive
`endif
|
#include <bits/stdc++.h> using namespace std; multiset<long long> buckets[30]; long long bsum[30]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int q, tot = 0; cin >> q; while (q--) { char c; long long x; cin >> c >> x; int p = 31 - __builtin_clz(x), ans = 0; if (c == + ) buckets[p].insert(x), bsum[p] += x, tot++; else buckets[p].erase(buckets[p].find(x)), bsum[p] -= x, tot--; long long sm = 0; for (int i = 0; i < 30; i++) if (buckets[i].size()) { if (*buckets[i].begin() > 2 * sm) ans++; sm += bsum[i]; } cout << tot - ans << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int present(int *lib, int k, int x) { int i; for (i = 0; i < k; i++) { if (lib[i] == x) return 1; } return 0; } int findMax(int *lib, int k, queue<int> *q, int n) { int i, max = -1, maxi = 0; for (i = 0; i < k; i++) { if (q[lib[i]].empty()) return i; if (max < q[lib[i]].front()) { max = q[lib[i]].front(); maxi = i; } } return maxi; } int main() { int n, k, i, ans = 0, size = 0, z; scanf( %d%d , &n, &k); int *lib = (int *)calloc(k, sizeof(int)); int *arr = (int *)calloc(n, sizeof(int)); queue<int> q[n + 1]; for (i = 0; i < n; i++) { scanf( %d , &arr[i]); q[arr[i]].push(i); } for (i = 0; i < n; i++) { if (present(lib, k, arr[i]) == 0) { if (size < k) { q[arr[i]].pop(); lib[size++] = arr[i]; ans++; } else { q[arr[i]].pop(); z = findMax(lib, k, q, n); lib[z] = arr[i]; ans++; } } else { q[arr[i]].pop(); } } printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; vector<pair<int, int>> adj[N], fish[N]; int n, m, now, depth[N]; struct node_t { int x, d, v; node_t(int x, int d, int v, int t = 0) : x(x - d * t), d(d), v(v) {} bool operator<(const node_t &b) const { int p = x + now * d, q = b.x + now * b.d; return p == q ? d < b.d : p < q; } }; struct collision_t { node_t x, y; int when; collision_t(node_t x, node_t y) : x(x), y(y) { when = y.x - x.x >> 1; } bool operator<(const collision_t &b) const { if (when != b.when) { return when < b.when; } else { return make_tuple(x.x, x.v, y.x, y.v) < make_tuple(b.x.x, b.x.v, b.y.x, b.y.v); } } }; struct info_t { set<collision_t> collisions; set<node_t> nodes; void insert_collision(node_t x, node_t y) { if (x.d > 0 && y.d < 0) { collisions.insert(collision_t(x, y)); } } void erase_collision(node_t x, node_t y) { if (x.d > 0 && y.d < 0) { collisions.erase(collision_t(x, y)); } } void insert(node_t x) { if (!x.v) { return; } if (nodes.find(x) != nodes.end()) { x.v += nodes.find(x)->v; erase(*nodes.find(x)); } auto it = nodes.insert(x).first, next = it; ++next; if (it != nodes.begin()) { auto prev = it; --prev; if (next != nodes.end()) { erase_collision(*prev, *next); } insert_collision(*prev, x); } if (next != nodes.end()) { insert_collision(x, *next); } } void erase(node_t x) { auto it = nodes.find(x), next = it; ++next; if (next != nodes.end()) { erase_collision(x, *next); } if (it != nodes.begin()) { auto prev = it; --prev; erase_collision(*prev, x); if (next != nodes.end()) { insert_collision(*prev, *next); } } nodes.erase(it); } int reset(int x, int y) { node_t l(x + 1, -1, y, now), r(x - 1, 1, y, now); return max(0, y - max(nodes.find(l) == nodes.end() ? 0 : nodes.find(l)->v, nodes.find(r) == nodes.end() ? 0 : nodes.find(r)->v)); } node_t cancel(node_t x, node_t y) { if (x.v > y.v) { return node_t(x.x, x.d, x.v - y.v); } else { return node_t(y.x, y.d, y.v - x.v); } } void collide(collision_t x) { erase(x.x); erase(x.y); insert(cancel(x.x, x.y)); } void maintain(int x) { while (!collisions.empty() && collisions.begin()->when <= x) { collide(*collisions.begin()); } } void merge(info_t &b) { if (nodes.size() < b.nodes.size()) { swap(nodes, b.nodes); swap(collisions, b.collisions); } for (auto x : b.nodes) { insert(x); } } int query() { int answer = 0; for (auto x : nodes) { if (x.d > 0) { answer += x.v; } } return answer; } } info[N]; void dfs(int x, int parent) { for (auto e : adj[x]) { int y = e.first, w = e.second; if (y != parent) { depth[y] = depth[x] + w; dfs(y, x); } } } void solve(int x, int parent) { for (auto e : adj[x]) { int y = e.first, w = e.second; if (y != parent) { solve(y, x); now = -depth[y]; info[y].maintain(-(depth[x] + 1)); now = -(depth[x] + 1); info[x].merge(info[y]); } } now = -(depth[x] + 1); for (auto &e : fish[x]) { e.second = info[x].reset(e.first, e.second); } info[x].maintain(-depth[x]); now = -depth[x]; for (auto e : fish[x]) { info[x].insert(node_t(e.first, -1, e.second, now)); info[x].insert(node_t(e.first, 1, e.second, now)); } } int main() { scanf( %d , &n); for (int i = 1; i < n; ++i) { int x, y, w; scanf( %d %d %d , &x, &y, &w); --x; --y; w <<= 1; adj[x].emplace_back(y, w); adj[y].emplace_back(x, w); } scanf( %d , &m); for (int i = 1; i <= m; ++i) { int day, value, where; scanf( %d %d %d , &day, &value, &where); day <<= 1; --where; fish[where].emplace_back(day, value); } dfs(0, -1); solve(0, -1); info[0].maintain(INT_MAX); printf( %d n , info[0].query()); return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg [40:0] quad; initial quad = 41'ha_bbbb_cccc;
reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678;
reg [8:0] nine; initial nine = 12;
reg signed [40:0] quads; initial quads = -(41'sha_bbbb_cccc);
reg signed [80:0] wides; initial wides = -(81'shabc_1234_5678_1234_5678);
reg signed [8:0] nines; initial nines = -12;
reg [31:0] str; initial str = "\000\277\021\n";
reg [47:0] str2; initial str2 = "\000what!";
reg [79:0] str3; initial str3 = "\000hmmm!1234";
string svs = "sv-str";
sub sub ();
sub2 sub2 ();
initial begin
$write("[%0t] In %m: Hi\n", $time);
sub.write_m;
sub2.write_m;
// Escapes
$display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line.
// Display formatting - constants
$display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time,
9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc),
81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc),
-(81'shabc_1234_5678_1234_5678), -(81'shabc_1234_5678_1234_5678));
// Display formatting
$display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
nines, nines, quads, quads, wides, wides);
$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
nines, nines, quads, quads, wides, wides);
//
// verilator lint_off WIDTH
$display("[%0t] %%C=%C %%0C=%0C", $time,
"a"+nine, "a"+nine);
$display("[%0t] %%c=%c %%0c=%0c", $time,
"a"+nine, "a"+nine);
// verilator lint_on WIDTH
$display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v <", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V <", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time,
nine, nine, quad, quad, wide, wide);
$display("[%0t] %%P=%P", $time,
svs);
$display("[%0t] %%u=%u %%0u=%0u", $time,
{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
$display("[%0t] %%U=%U %%0U=%0U", $time,
{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
// %z is tested in t_sys_sformat.v
$display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time,
nine, nine, nine, nine, nine);
$display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time,
$time, $time, $time);
$display;
// Not testing %0s, it does different things in different simulators
$display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
str2[7:0], str2, str3);
$display("[%0t] %s%s%s", $time,
"hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
$display("hel", "lo, fr", "om a concatenated string.");
$write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time);
$display("extra argument: ", $time);
$display($time, ": pre argument");
$write("[%0t] Embedded \r return\n", $time);
$display("[%0t] Embedded\
multiline", $time);
// Str check
`ifndef NC // NC-Verilog 5.3 chokes on this test
if (str !== 32'h00_bf_11_0a) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub;
task write_m;
begin
$write("[%0t] In %m (%l)\n", $time);
begin : subblock
$write("[%0t] In %M (%L)\n", $time); // Uppercase %M test
end
end
endtask
endmodule
module sub2;
// verilator no_inline_module
task write_m;
begin
$write("[%0t] In %m (%l)\n", $time);
begin : subblock2
$write("[%0t] In %m (%L)\n", $time);
end
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
`define SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BLACKBOX_V
|
#include <bits/stdc++.h> #define testCase int T; cin>>T; while(T--) #define int long long #define Endl endl using namespace std; /* */ const int N = 1e5+13, LMAX = 3e18 + 13, IMAX = 1e9 + 5, mod = 1e9 + 7; //998244353; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); testCase { int mn = 101; int n, x; cin >> n; for (int i = 0; i < n; ++i) { cin >> x; mn = min(mn, x); } if (mn < 0) cout << NO n ; else { cout << YES n ; cout << 101 n ; for (int i = 0; i <=100; ++i) { cout << i << ; }cout << n ; } } return 0; }
|
#include <bits/stdc++.h> int main() { long long a, b; scanf( %I64d %I64d , &a, &b); printf( %I64d n , (6LL * a - 1LL) * b); for (long long i = 1; i <= a; i++) { printf( %I64d %I64d %I64d %I64d n , (6LL * i - 5LL) * b, (6LL * i - 4LL) * b, (6LL * i - 3LL) * b, (6LL * i - 1LL) * b); } return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`ifdef VERILATOR
`define c(v,vs) ($c(vs)) // Don't constify a value
`else
`define c(v,vs) (v)
`endif
module t (/*AUTOARG*/
// Outputs
ow4_u
);
bit fail;
reg signed [3:0] w4_s;
reg signed [4:0] w5_s;
reg [2:0] w3_u;
reg [3:0] w4_u;
reg [4:0] w5_u;
reg [5:0] w6_u;
reg [15:0] w16a_u;
reg [15:0] w16_u;
reg [31:0] w32_u;
real r;
reg signed [4:0] bug754_a;
integer i;
//verilator lint_off WIDTH
wire a = (5'b0 == (5'sb11111 >>> 3'd7));
wire b = (5'sb11111 == (5'sb11111 >>> 3'd7));
wire c = (1'b0+(5'sb11111 >>> 3'd7));
wire d = (1'sb0+(5'sb11111 >>> 3'd7));
wire e = (5'b0 == (5'sb11111 / 5'sd3));
wire f = (5'sb0 == (5'sb11111 / 5'sd3));
wire g = (5'b01010 == (5'b11111 / 5'sd3));
initial begin
// verilator lint_off STMTDLY
#1;
`ifdef VCS // I-2014.03
`checkh({a, b, c, d, e, f, g}, 7'b1101111);
`else
`checkh({a, b, c, d, e, f, g}, 7'b1101011);
`endif
//======================================================================
if ((-1 >>> 3) != -1) $stop; // Decimals are signed
i = 3'sb111 >>> 3;
`checkh(i, -1);
i = -1 >>> 3;
`checkh(i, -1);
bug754_a = -1;
w4_u = |0 != (bug754_a >>> 3'd7);
`checkh(w4_u, 4'b0);
// Sanity check: -1>>7 == -1
w5_u = (5'sb11111 >>> 3'd7);
`checkh(w5_u, 5'b11111);
// bug756
w4_u = (5'b0 == (5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b0001);
w4_u = ((5'b0 == (5'sb11111 >>> 3'd7))); // Exp 0 Vlt 0
`checkh(w4_u, 4'b0001);
w4_u = ((5'b01111 == (5'sb11111 / 5'sd2))); // Strength-reduces to >>>
`ifdef VCS // I-2014.03
`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
`else
`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
`endif
// Does == sign propagate from lhs to rhs? Yes, but not in VCS
w4_u = ((5'b01010 == (5'sb11111 / 5'sd3))); // Exp 0 Vlt 0 // Must be signed result (-1/3) to make this result zero
`ifdef VCS // I-2014.03
`checkh(w4_u, 4'b0000); // Wrong, gets 5'b0==..., unsigned does not propagate
// Somewhat questionable, as spec says division signed depends on only LHS and RHS, however differs from others
`else
`checkh(w4_u, 4'b0001); // NC-Verilog, Modelsim, XSim, ...
`endif
w4_u = (1'b0+(5'sb11111 >>> 3'd7)); // Exp 00000 Vlt 000000 Actually the signedness of result does NOT matter
`checkh(w4_u, 4'b0000);
w4_u = (5'sb0 == (5'sb11111 / 5'sd3)); // Must be signed result (-1/3) to make this result zero
`checkh(w4_u, 4'b0001);
// Does == width propagate from lhs to rhs? Yes
w4_u = (3'b100==(3'b111 << 2));
`checkh(w4_u, 4'b0001);
w4_u = (4'b100==(3'b111 << 2));
`checkh(w4_u, 4'b0000);
w4_u = (4'b1100==(3'b111 << 2));
`checkh(w4_u, 4'b0001);
// Does >>> sign propagate from input same as for +? Yes
w4_u = (1'b0+(5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b0000);
w4_u = (1'sb0+(5'sb11111 >>> 3'd7));
`checkh(w4_u, 4'b1111);
// Does << width propagate from input same as for +? Yes
w4_u = (3'b0+(3'b111 << 2));
`checkh(w4_u, 4'b1100); // width 4 =='s LHS
w4_u = (4'b0+(3'b111 << 2));
`checkh(w4_u, 4'b1100);
w4_u = (5'sb11111 == (5'sb11111 >>> 3'd7)); // WHAT? Signedness does propagate across ==?????
`checkh(w4_u, 4'b0001);
w4_u = ((5'b0 == (5'sb11111 >>> 3'd7)));
`checkh(w4_u, 4'b0001);
// bug756
w5_s = -1;
w3_u = 7;
w4_u = |0 != (w5_s >>> w3_u);
`checkh(w4_u, 4'b0000);
// bug763
w3_u = 2;
w4_u = (w3_u >> 2'b11) >> 1;
`checkh(w4_u, 4'b0000);
// bug766
w16a_u = 16'h1234;
w16_u = (w16a_u >> 16) >>> 32'h7ffffff1;
`checkh(w16_u, 16'h0000);
// bug768
w4_s = 4'sd4;
w4_u = $signed(5'd1 > w4_s-w4_s);
`checkh(w4_u, 4'b1111);
w4_s = `c(4,"4"); // Eval at runtime
w4_u = $signed(5'd1 > w4_s-w4_s);
`checkh(w4_u, 4'b1111);
// bug772
w4_s = w4_u << 1 <<< 0/0;
`ifndef VERILATOR // In v4 can't check value as not 4-state
`checkh(w4_s, 4'bxxxx);
`endif
// bug773
w5_u = `c(31, 31);
w5_s = w5_u >> ((w5_u ? 1 : 2) << w5_u);
`checkh(w5_s, 5'b0);
// bug774
w4_u = `c(4, 5);
w6_u = `c(6, 35);
w4_u = 64'd0 | (w4_u << w6_u);
`checkh(w4_u, 0);
// bug776
w4_u = `c(4, 1);
w4_u = (w4_u >> w4_u) ^~ (w4_u >> w4_u);
`checkh(w4_u, 4'b1111);
// bug828
// verilator lint_off WIDTH
w32_u = 32'(signed'({4'b0001,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0180);
w32_u = 32'(signed'({4'b0011,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0380);
w32_u = signed'(32'({4'b0001,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0180);
w32_u = signed'(32'({4'b0011,5'b10000}) << 3);
`checkh(w32_u, 32'h0000_0380);
// verilator lint_on WIDTH
w32_u = 32'(signed'({4'b0011,5'b10000})) << 3; // Check no width warning
`checkh(w32_u, 32'h0000_0380);
if (fail) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
// bug775
output [3:0] ow4_u; // Must be consumed
assign ow4_u = ((0/0) ? 1 : 2) % 0;
endmodule
|
// Computer_System_Video_In_Subsystem_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_Video_In_Subsystem_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 16,
parameter inUsePackets = 1,
parameter inDataWidth = 16,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 1,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 16,
parameter outChannelWidth = 0,
parameter outErrorWidth = 0,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [15:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
input wire in_0_startofpacket, // .startofpacket
input wire in_0_endofpacket, // .endofpacket
input wire in_0_empty, // .empty
output wire [15:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire out_0_startofpacket, // .startofpacket
output wire out_0_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 16)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_Video_In_Subsystem_avalon_st_adapter_001_data_format_adapter_0 data_format_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.in_startofpacket (in_0_startofpacket), // .startofpacket
.in_endofpacket (in_0_endofpacket), // .endofpacket
.in_empty (in_0_empty), // .empty
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_startofpacket (out_0_startofpacket), // .startofpacket
.out_endofpacket (out_0_endofpacket) // .endofpacket
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200010; long long a[N], b[N], p[N], money; int top, n, m, ans, st[N]; vector<long long> v[N]; priority_queue<long long> q; void get_sale_day() { for (int i = 1; i <= n; ++i) { while (top && a[i] >= a[st[top]]) --top; st[++top] = i; } for (int i = 1; i <= m; ++i) { if (b[i] > a[st[1]]) continue; int l = 1, r = top, ans = 0; while (l <= r) { int mid = (l + r) >> 1; if (a[st[mid]] >= b[i]) ans = mid, l = mid + 1; else r = mid - 1; } v[st[ans]].push_back(p[i]); } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) scanf( %lld , &a[i]); for (int i = 1; i <= m; ++i) scanf( %lld , &b[i]); for (int i = 1; i <= m; ++i) scanf( %lld , &p[i]); get_sale_day(); for (int i = 1; i <= n; ++i) { money += a[i]; sort(v[i].begin(), v[i].end()); for (int j = 0; j < v[i].size(); ++j) if (v[i][j] <= money) { money -= v[i][j]; q.push(v[i][j]); ans++; } else { if (q.empty()) continue; long long tmp = q.top(); if (tmp > v[i][j]) { q.pop(); q.push(v[i][j]); money += tmp - v[i][j]; } } } printf( %d n , ans); return 0; }
|
/* lab3_part5.v - 16-bit latch
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
Range of hex:
1111-1111-1111-1111
0 - FFFF (65535)
HEX 7 6 5 4
+---+ +---+ +---+ +---+
| | | | | | | |
| F | | F | | F | | F |
+-+-+ +-+-+ +-+-+ +-+-+
+-----+ | +----+ |---------+
+----+-----++-----+----++-----+----++-----+-----+
|+--+--+--++++--+--+--++++--+--+--++++--+-++--+ |
|| | | |||| | | |||| | | |||| | | | |
|1 1 1 1||1 1 1 1||1 1 1 1||1 1 1 1 |
+----------++----------++----------++-----------+
SW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+-----+--+ 0
|0000 | 0| +-----+
|0001 | 1| 5 | | 1
|0010 | 2| | 6 |
|0011 | 3| +-----+
|0100 | 4| 4 | | 2
|0101 | 5| | |
|0110 | 6| +-----+
|0111 | 7| 3
|1000 | 8|
|1001 | 9|
|1010 | A|
|1011 | B|
|1100 | C|
|1101 | D|
|1110 | E|
|1111 | F|
+-----+--+
| | | | | | | |
S +-+--+---+---+----+---+---+---++
--+D7 D6 D5 D4 D3 D2 D1 D0|
Clk--+ |
| |
R --+Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0|
+-+---+---+--+---+---+---+---+-+
| | | | | | | |
*/
module lab3_part5 (SW, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, KEY);
input [3:0] KEY;
input [17:0] SW;
output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
reg [15:0] R;
wire [15:0] Q;
D_ff_with_sync_clr F0 (~KEY[1], SW[0], Q[0], ~KEY[0]);
D_ff_with_sync_clr F1 (~KEY[1], SW[1], Q[1], ~KEY[0]);
D_ff_with_sync_clr F2 (~KEY[1], SW[2], Q[2], ~KEY[0]);
D_ff_with_sync_clr F3 (~KEY[1], SW[3], Q[3], ~KEY[0]);
D_ff_with_sync_clr F4 (~KEY[1], SW[4], Q[4], ~KEY[0]);
D_ff_with_sync_clr F5 (~KEY[1], SW[5], Q[5], ~KEY[0]);
D_ff_with_sync_clr F6 (~KEY[1], SW[6], Q[6], ~KEY[0]);
D_ff_with_sync_clr F7 (~KEY[1], SW[7], Q[7], ~KEY[0]);
D_ff_with_sync_clr F8 (~KEY[1], SW[8], Q[8], ~KEY[0]);
D_ff_with_sync_clr F9 (~KEY[1], SW[9], Q[9], ~KEY[0]);
D_ff_with_sync_clr F10 (~KEY[1], SW[10], Q[10], ~KEY[0]);
D_ff_with_sync_clr F11 (~KEY[1], SW[11], Q[11], ~KEY[0]);
D_ff_with_sync_clr F12 (~KEY[1], SW[12], Q[12], ~KEY[0]);
D_ff_with_sync_clr F13 (~KEY[1], SW[13], Q[13], ~KEY[0]);
D_ff_with_sync_clr F14 (~KEY[1], SW[14], Q[14], ~KEY[0]);
D_ff_with_sync_clr F15 (~KEY[1], SW[15], Q[15], ~KEY[0]);
always
R = Q;
hex_ssd H0 (SW[3:0], HEX0);
hex_ssd H1 (SW[7:4], HEX1);
hex_ssd H2 (SW[11:8], HEX2);
hex_ssd H3 (SW[15:12], HEX3);
hex_ssd H4 (R[3:0], HEX4);
hex_ssd H5 (R[7:4], HEX5);
hex_ssd H6 (R[11:8], HEX6);
hex_ssd H7 (R[15:12], HEX7);
endmodule
module D_ff_with_sync_clr (Clk, D, Q, Clr);
input Clk, D, Clr;
output reg Q;
always @ ( posedge Clk or posedge Clr)
if (Clr)
begin
Q <= 1'b0;
end else
begin
Q <= D;
end
endmodule
module hex_ssd (BIN, SSD);
input [15:0] BIN;
output reg [0:6] SSD;
always begin
case(BIN)
0:SSD=7'b0000001;
1:SSD=7'b1001111;
2:SSD=7'b0010010;
3:SSD=7'b0000110;
4:SSD=7'b1001100;
5:SSD=7'b0100100;
6:SSD=7'b0100000;
7:SSD=7'b0001111;
8:SSD=7'b0000000;
9:SSD=7'b0001100;
10:SSD=7'b0001000;
11:SSD=7'b1100000;
12:SSD=7'b0110001;
13:SSD=7'b1000010;
14:SSD=7'b0110000;
15:SSD=7'b0111000;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3 (
VPWR,
VGND,
X ,
A ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , C, A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_FUNCTIONAL_V
|
#include <bits/stdc++.h> long long z; int l, r, i, j, k, ans; short p; std::vector<short> prm; std::vector<int> to; short dp[3000111]; bool done[3000111]; void dfs(long long now, char cnt) { to.push_back(now); for (; cnt < prm.size() && now * prm[cnt] <= r; ++cnt) dfs(now * prm[cnt], cnt); } int main() { prm.reserve(29); to.reserve(3000111); scanf( %d %d %hd , &l, &r, &p); for (i = 2; i < p; ++i) { for (j = 2; j * j <= i; ++j) if (i % j == 0) break; if (j * j > i) prm.push_back(i); } dfs(1, 0); std::sort(to.begin(), to.end()); memset(dp, 0x3f, sizeof(dp)); dp[0] = 0; for (i = 2; i < p; ++i) for (j = 0, k = 1; j < to.size(); ++j) { for (z = to[j] * i; k < to.size() && to[k] < z; ++k) ; if (to[k] == z && dp[k] > dp[j] + 1) { dp[k] = dp[j] + 1; if (i + dp[k] <= p) done[k] = true; } } r = std::min(r, to.back()); for (i = 0; i < to.size() && to[i] < l; ++i) ; for (; i < to.size() && to[i] <= r; ++i) if (done[i]) ++ans; printf( %d n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count() * ((uint64_t) new char | 1)); int K, N; vector<int> A, B, Z; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> K; N = 1 << K; Z.resize(N); int all_xor = 0; for (auto &z : Z) { cin >> z; all_xor ^= z; } if (all_xor != 0) { cout << Fou << n ; return 0; } A.resize(N); B.resize(N); vector<int> location(N); for (int i = 0; i < N; i++) A[i] = B[i] = i; shuffle(A.begin(), A.end(), rng); shuffle(B.begin(), B.end(), rng); for (int i = 0; i < N; i++) location[B[i]] = i; for (int i = 0; i < N; i++) { int u = i; while (Z[u] != (A[u] ^ B[u])) { int v = location[A[u] ^ Z[u]]; swap(B[u], B[v]); swap(location[B[u]], location[B[v]]); if (v > i) { break; } else { swap(A[v], A[i + 1]); u = v; } } } cout << Shi << n ; for (int i = 0; i < N; i++) cout << A[i] << (i < N - 1 ? : n ); for (int i = 0; i < N; i++) cout << B[i] << (i < N - 1 ? : n ); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, l, r, x, res = 0; vector<int> subset; void search(int k, const vector<int>& v) { if (k == n) { long long count = accumulate(subset.begin(), subset.end(), 0); if (count >= l && count <= r && (subset.back() - subset.front()) >= x) ++res; } else { subset.push_back(v[k]); search(k + 1, v); subset.pop_back(); search(k + 1, v); } } int main() { cin >> n >> l >> r >> x; vector<int> c(n); for (int i = 0; i < n; ++i) cin >> c[i]; sort(c.begin(), c.end()); search(0, c); cout << res; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2005; bool vis[N]; pair<int, int> pt[N]; int dp[N]; int main() { memset(dp, 0x3f, sizeof(dp)); int a, m, n; cin >> a >> n >> m; for (int i = 1; i <= n; i++) { int l, r; scanf( %d %d , &l, &r); for (int j = l + 1; j <= r; j++) { vis[j] = true; } } for (int i = 1; i <= m; i++) { scanf( %d %d , &pt[i].first, &pt[i].second); } sort(pt + 1, pt + 1 + m); for (int i = 1; i <= pt[1].first; i++) { if (vis[i] == true) { puts( -1 ); return 0; } } dp[0] = 0; int cnt = 1; for (int i = 1; i <= a; i++) { while (cnt <= m && pt[cnt].first < i) cnt++; if (vis[i] == false) dp[i] = dp[i - 1]; else { for (int j = 1; j < cnt; j++) { dp[i] = min(dp[i], dp[pt[j].first] + pt[j].second * (i - pt[j].first)); } } } printf( %d n , dp[a]); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename... T> void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << , ; err(++it, args...); } const long long inf = 1LL << 60; const long long md = 1000000007; vector<long long> adj[200005]; long long vis[200005] = {0}; void bfs(long long s) { queue<long long> q; vis[s] = 1; q.push(s); while (!q.empty()) { long long s = q.front(); q.pop(); for (auto i : adj[s]) { if (vis[i]) continue; vis[i] = vis[s] + 1; q.push(i); } } } long long vis2[200005] = {0}; void bfs2(long long s) { queue<long long> q; vis2[s] = 1; q.push(s); while (!q.empty()) { long long s = q.front(); q.pop(); for (auto i : adj[s]) { if (vis2[i]) continue; vis2[i] = vis2[s] + 1; q.push(i); } } } bool comp(pair<long long, long long> a, pair<long long, long long> b) { return a.first - a.second < b.first - b.second; } void solve() { long long n, m, k; cin >> n >> m >> k; long long a[k]; for (long long i = 0; i < k; i++) { cin >> a[i]; } for (long long i = 0; i < m; i++) { long long x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } bfs(1); bfs2(n); pair<long long, long long> d[k]; for (long long i = 0; i < k; i++) { d[i] = {vis[a[i]], vis2[a[i]]}; } sort(d, d + k, comp); long long ans = 0; long long mx = -inf; for (long long i = 0; i < k; i++) { ans = max(ans, mx + d[i].second); mx = max(mx, d[i].first); } cout << min(vis[n] - 1, ans - 1); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; for (long long i = 1; i <= t; i++) { solve(); cout << n ; } }
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gray_send
#(parameter WIDTH = 8)
(input clk_in, input [WIDTH-1:0] addr_in,
input clk_out, output reg [WIDTH-1:0] addr_out);
reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
wire [WIDTH-1:0] gray, bin;
bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
always @(posedge clk_in)
gray_clkin <= gray;
always @(posedge clk_out)
gray_clkout <= gray_clkin;
always @(posedge clk_out)
gray_clkout_d1 <= gray_clkout;
gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
// FIXME we may not need the next register, but it may help timing
always @(posedge clk_out)
addr_out <= bin;
endmodule // gray_send
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK /* or `BSV_RESET_EDGE RST */ )
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK /* or `BSV_RESET_EDGE RST */)
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> mp; string s; long long n, m, k, ans; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(0)); cin >> n; vector<long long> a(n + 1, 0); for (long long i = 1; i <= n; ++i) cin >> a[i]; for (long long i = n; i >= 1; --i) if (a[i] && !m) m = i; else if (!a[i] && !k) k = i; cout << min(m, k); }
|
module LZC #(
parameter width = 8,
parameter word = 4
)(
input wire CLK,
input wire RST_N,
input wire MODE,
input wire IVALID,
input wire [width-1:0] DATA,
output reg OVALID,
output reg [8:0] ZEROS
);
parameter INPUT = 1'b0;
parameter OUTPUT = 1'b1;
integer i;
wire have_one;
reg state, state_next;
reg findOne, flag;
reg already_have_one;
reg [8:0] zero_cnt;
reg [5:0] WORDS;
assign have_one = (findOne) ? 1 : 0;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
state <= INPUT;
ZEROS <= 0;
OVALID <= 0;
WORDS <= 0;
flag <= 0;
already_have_one <= 0;
end else begin
state <= state_next;
if (IVALID) begin
WORDS <= WORDS + 1;
ZEROS <= ZEROS + ((already_have_one) ? 0 : zero_cnt);
already_have_one <= (have_one) ? 1 : already_have_one;
end
if (state_next == OUTPUT) begin
OVALID <= 1;
end else begin
OVALID <= 0;
end
if (state == OUTPUT) begin
ZEROS <= 0;
WORDS <= 0;
already_have_one <= 0;
end
end
end
always @* begin
if (IVALID) begin
zero_cnt = 0;
findOne = 0;
for (i = width-1; i >= 0; i = i - 1) begin
if (!findOne && DATA[i] == 0) begin
zero_cnt = zero_cnt + 1;
end else begin
findOne = 1;
end
end
end
end
always @* begin
case (state)
INPUT: begin
if (!IVALID) begin
state_next = INPUT;
end else begin
if ((MODE && (have_one || already_have_one)) || WORDS == word - 1) begin
state_next = OUTPUT;
end else begin
state_next = INPUT;
end
end
end
OUTPUT: begin
state_next = INPUT;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR3B_FUNCTIONAL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or3b (
X ,
A ,
B ,
C_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_2_V
`define SKY130_FD_SC_HS__A41OI_2_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, sum = 0; cin >> n >> x >> y; sum = (n * y) / 100; if ((n * y) % 100 != 0) { sum += 1; } if (sum <= x) cout << 0; else cout << abs(sum - x); return 0; }
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_sincos_s5(clock, resetn, dataa, result_a, result_b, enable);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result_a; // sin
output [31:0] result_b; // cos
fp_sincos_s5 fused(
.clk(clock),
.areset(1'b0),
.en(enable),
.a(dataa),
.s(result_a),
.c(result_b));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_1_V
`define SKY130_FD_SC_HVL__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_1_V
|
Require Import Coq.Setoids.Setoid.
Require Import Coq.Classes.Morphisms.
Require Import Coq.Arith.Arith_base.
(***
*** Domains (which are just pre-orders with a fancy name)
***)
Class DomainOrder (A:Type) : Type :=
approx : relation A.
(* Notation for approx *)
Notation "x '<<<' y" := (approx x y) (at level 80, no associativity).
Class Domain (A:Type) {DomainOrder:DomainOrder A} : Prop :=
{
domain_preorder :> PreOrder approx
}.
(* For setoid_rewrite using approx *)
Add Parametric Relation `{Domain} : A approx
reflexivity proved by PreOrder_Reflexive
transitivity proved by PreOrder_Transitive
as Domain_morphism.
(* The restriction of an approximation relation to an equivalence *)
Definition approxEq `{DomainOrder} : relation A :=
fun a1 a2 => approx a1 a2 /\ approx a2 a1.
(* Notation for approxEq *)
Notation "m1 '==' m2" := (approxEq m1 m2) (at level 80, no associativity).
(* approxEq is always an equivalence *)
Instance approxEq_Equivalence `{Domain} : Equivalence approxEq.
constructor.
intro m; split; reflexivity.
intros m1 m2 H1; destruct H1; split; assumption.
intros m1 m2 m3 H1 H2; destruct H1; destruct H2; split; transitivity m2; assumption.
Qed.
(* For setoid_rewrite using approxEq *)
Add Parametric Relation `{Domain} : A approxEq
reflexivity proved by Equivalence_Reflexive
symmetry proved by Equivalence_Symmetric
transitivity proved by Equivalence_Transitive
as approxEq_morphism.
(* For rewriting the arguments of approx using approxEq *)
Instance proper_approxEq_approx `{Domain} : Proper (approxEq ==> approxEq ==> iff) approx.
intros x1 y1 eq1 x2 y2 eq2; destruct eq1; destruct eq2; split; intro.
transitivity x1; [ assumption | ]; transitivity x2; assumption.
transitivity y1; [ assumption | ]; transitivity y2; assumption.
Qed.
(***
*** Some useful domains
***)
(* Domains for pairs *)
Instance Pair_DomainOrder A {_:DomainOrder A} B {_:DomainOrder B} :
DomainOrder (A*B) :=
fun p1 p2 => approx (fst p1) (fst p2) /\ approx (snd p1) (snd p2).
Instance Pair_Domain A `{Domain A} B `{Domain B} : Domain (prod A B).
repeat constructor; try reflexivity; destruct H1; destruct H2.
transitivity (fst y); assumption.
transitivity (snd y); assumption.
Qed.
(***
*** Complete Partial Orders
***
*** Technically, these are omega-complete preorders, since cpo_sup only deals
*** with countable chains and we drop antisymmetry.
***)
(* States that a is an upper bound of chain *)
Definition upper_bound {A} (R: relation A) (chain: nat -> A) a :=
forall n, R (chain n) a.
(* States that a is no greater than any upper bound of chain *)
Definition below_upper_bounds {A} (R: relation A) (chain: nat -> A) a :=
forall a', upper_bound R chain a' -> R a a'.
(* The supremum function, which works on any countable set of A's *)
Class CPOSupremum (A:Type) {DomainOrder:DomainOrder A} : Type :=
cpo_sup : (nat -> A) -> A.
(* The definition of a directed countable set *)
Definition directed `{CPOSupremum} (chain: nat -> A) : Prop :=
forall n1 n2, exists n',
approx (chain n1) (chain n') /\ approx (chain n2) (chain n').
(* (Omega)-CPO = preorder with least upper bounds of directed countable sets *)
Class CPO (A:Type) {DomainOrder:DomainOrder A}
{CPOSupremum:@CPOSupremum A DomainOrder} : Prop :=
{
cpo_preorder :> Domain A;
cpo_sup_upper_bound :
forall chain, directed chain -> upper_bound approx chain (cpo_sup chain);
cpo_sup_least :
forall chain,
directed chain -> below_upper_bounds approx chain (cpo_sup chain)
}.
(* Two supremums are equivalent iff the chains dominate each other *)
Lemma supremums_equivalent `{CPO} chain1 chain2 :
directed chain1 -> directed chain2 ->
(forall n1, exists n2, approx (chain1 n1) (chain2 n2)) ->
(forall n2, exists n1, approx (chain2 n2) (chain1 n1)) ->
approxEq (cpo_sup chain1) (cpo_sup chain2).
intros; split; apply cpo_sup_least; try assumption; intro n.
destruct (H2 n) as [ n' ]; transitivity (chain2 n'); [ assumption | ].
apply cpo_sup_upper_bound; assumption.
destruct (H3 n) as [ n' ]; transitivity (chain1 n'); [ assumption | ].
apply cpo_sup_upper_bound; assumption.
Qed.
(***
*** Scott-Continuous Functions
***)
(* Scott-continuity = monotonicity + preservation of cpo_sup
NOTE: We put monotonicity as part of the definition of Scott-continuity because
we don't include antisymmetry in our definition of CPO, and the proof that
Scott-continuity implies monotonicity requires a congruence closure step to
prove that (f a2) = (f (cpo_sup (fun n => match n with | 0 => a1 | S _ => a2)))
and this does not work when we only know that a2 is equivalent up to R to this
supremum, not that it is equal. *)
Definition scott_continuous `{CPO} (f : A -> A) : Prop :=
Proper (approx ==> approx) f /\
(forall chain,
directed chain ->
approxEq (f (cpo_sup chain)) (cpo_sup (fun n => f (chain n)))).
(***
*** Pointed (omega-)CPOs
***)
(* The bottom of a PCPO *)
Class PCPOBottom (A:Type) {DomainOrder:DomainOrder A} : Type :=
pcpo_bottom : A.
(* PCPO = CPO + a bottom *)
Class PCPO (A:Type) {DomainOrder:DomainOrder A}
{CPOSupremum:CPOSupremum A (DomainOrder:=DomainOrder)}
{PCPOBottom:PCPOBottom A (DomainOrder:=DomainOrder)} : Prop :=
{
pcpo_cpo :> CPO A (CPOSupremum:=CPOSupremum);
pcpo_least_element : forall a, approx pcpo_bottom a
}.
(***
*** Every Scott-continuous function has a least fixed-point
***)
(* Fixed-points of f, modulo the symmetric closure of R *)
Definition fixed_point `{DomainOrder} (f: A -> A) a :=
approxEq (f a) a.
(* Least fixed-points of f, modulo the symmetric closure of R *)
Definition least_fixed_point `{DomainOrder} (f: A -> A) a :=
fixed_point f a /\
forall a', fixed_point f a' -> approx a a'.
(* Iterate a function n times *)
Fixpoint iterate_f {A} n (f: A -> A) :=
match n with
| 0 => fun x => x
| S n' => fun x => f (iterate_f n' f x)
end.
(* (f^n _|_) `R` (f^(n+1) _|_) for monotone f *)
Lemma iterate_f_increases1 `{PCPO} n f :
Proper (approx ==> approx) f ->
approx (iterate_f n f pcpo_bottom) (iterate_f (S n) f pcpo_bottom).
intro mono; induction n.
apply pcpo_least_element.
unfold iterate_f; fold (@iterate_f A).
apply mono. assumption.
Qed.
(* Similar to above, but for arbitrary n1 <= n2 *)
Lemma iterate_f_increases `{PCPO} n1 n2 f :
n1 <= n2 -> Proper (approx ==> approx) f ->
approx (iterate_f n1 f pcpo_bottom) (iterate_f n2 f pcpo_bottom).
intro l; induction l; intros.
reflexivity.
transitivity (iterate_f m f pcpo_bottom).
apply IHl; assumption.
apply iterate_f_increases1; assumption.
Qed.
(* Building the least fixed-point of a Scott-continuous function f *)
Definition leastFP `{DomainOrder} {_:CPOSupremum A} {_:PCPOBottom A} f : A :=
cpo_sup (fun n => iterate_f n f pcpo_bottom).
(* Proof that leastFP gives a fixed-point *)
Lemma leastFP_correct `{PCPO} f :
scott_continuous f -> least_fixed_point f (leastFP f).
intro sc; destruct sc.
(* Helper lemma 1 *)
assert (directed (fun n : nat => iterate_f n f pcpo_bottom)).
intros n1 n2; exists (max n1 n2).
split; apply iterate_f_increases;
first [ assumption | apply Nat.le_max_l | apply Nat.le_max_r ].
(* Helper lemma 2 *)
assert (directed (fun n : nat => f (iterate_f n f pcpo_bottom))).
intros n1 n2; exists (max n1 n2).
unfold iterate_f; fold (@iterate_f A (S n1) f pcpo_bottom);
fold (@iterate_f A (S n2) f pcpo_bottom);
fold (@iterate_f A (S (max n1 n2)) f pcpo_bottom).
split; apply iterate_f_increases; try (apply le_n_S);
first [ assumption | apply Nat.le_max_l | apply Nat.le_max_r ].
split; unfold leastFP, fixed_point.
(* Proof that leastFP is a fixed-point *)
transitivity (cpo_sup (fun n => f (iterate_f n f pcpo_bottom))).
apply H1; assumption.
apply supremums_equivalent; try assumption; intro.
exists (S n1); reflexivity.
exists n2. apply iterate_f_increases1; assumption.
(* Proof that leastFP is a least fixed-point *)
intros fp is_fp.
apply cpo_sup_least; try assumption.
intro n; induction n.
apply pcpo_least_element.
transitivity (f fp).
apply H0; assumption.
destruct is_fp; assumption.
Qed.
|
/*
for a elctric speed control, we will be generationg
1 - 1.5MS plus width: rolling speed from -max to 0, 0.1ms as 1 step
1.5 - 2MS plus width: rolling speed from 0 to +max
the pwm period is 18--22ms here we defined it as 20MS, 50 HZ
*/
module quadpwm(rst_n, freq_clk, enable, mode, led);
input rst_n;
input freq_clk;
input enable;
input mode;
output pwm0;
output pwm1;
output pwm2;
output pwm3;
reg pwm0_reg;
reg pwm1_reg;
reg pwm2_reg;
reg pwm3_reg;
reg[31:0] engine_reg;
//debug led
reg led;
// generate 2500 Hz from 50 MHz
reg [31:0] count_reg;
reg pwm_clk;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
pwm_clk <= 0;
end
else if (enable)
begin
if (count_reg < 999999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
pwm_clk <= ~pwm_clk;
end
end
end
reg[31:0] pwm_load_register;
/*process the pwm0 signal period*/
always @ (posedge pwm_clk or negedge rst_n)
begin
if (!rst_n)
begin
pwm_load_register <= 1'b0;
end
else if (out_div)
begin
case (pha_reg)
1'd1:
begin
pha_reg <= 1'd0;
end
1'd0:
begin
pha_reg <= 1'd1;
end
endcase
end
end
assign pwm0 = pwm0_reg;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Thu Aug 25 17:34:14 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/8-way/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int left, right, size; } t[600000]; int n; int a[200005], b[200005], sa[200005], sb[200005], s[200005], ans[200005]; int readint() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } void build(int id, int l, int r, int x) { t[id].left = l, t[id].right = r; if (l == r) return (void)(t[id].size = x); int mid = (l + r) / 2; build(id << 1, l, mid, x); build(id << 1 | 1, mid + 1, r, x); t[id].size = t[id << 1].size + t[id << 1 | 1].size; } int query(int id, int x) { if (t[id].left == t[id].right) return t[id].size; if (x <= t[id << 1].right) return query(id << 1, x); else return query(id << 1 | 1, x) + t[id << 1].size; } void change(int id, int x, int c) { if (t[id].left == t[id].right) return (void)(t[id].size = c); if (x <= t[id << 1].right) change(id << 1, x, c); else change(id << 1 | 1, x, c); t[id].size = t[id << 1].size + t[id << 1 | 1].size; } int find(int id, int x) { if (t[id].left == t[id].right) return t[id].left; if (x <= t[id << 1].size) return find(id << 1, x); else return find(id << 1 | 1, x - t[id << 1].size); } int main() { n = readint(); for (int i = 1; i <= n; i++) a[i] = readint() + 1; for (int i = 1; i <= n; i++) b[i] = readint() + 1; build(1, 1, n, 0); for (int i = n; i >= 1; i--) { sa[i] = query(1, a[i]); change(1, a[i], 1); } build(1, 1, n, 0); for (int i = n; i >= 1; i--) { sb[i] = query(1, b[i]); change(1, b[i], 1); } for (int i = n; i >= 1; i--) { s[i] += sa[i] + sb[i]; if (s[i] >= n - i + 1) s[i] -= n - i + 1, s[i - 1]++; } build(1, 1, n, 1); for (int i = 1; i <= n; i++) { ans[i] = find(1, s[i] + 1); change(1, ans[i], 0); } for (int i = 1; i <= n; i++) printf( %d , ans[i] - 1); printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int c, v0, v1, a, l; cin >> c >> v0 >> v1 >> a >> l; int ans = 1; c -= min(v0, v1); int p = 0; while (c > 0) { v0 = v0 + a; p = min(v0, v1); p -= l; c -= p; ans++; } cout << ans << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int BinSea(vector<long long int>& a, long long int low, long long int high, long long int n) { long long int ct = high; long long int ans = high; while (low <= high) { long long int mid = low + ((high - low) / 2); long long int val = a[ct] - a[mid]; if (val <= n) { ans = mid; high = mid - 1; } else { low = mid + 1; } } return ans; } int main() { long long int n, k; cin >> n >> k; vector<long long int> a(2 * n + 1); vector<long long int> p1(2 * n + 1), p2(2 * n + 1); for (long long int i = 0; i < n; i++) { cin >> a[i]; a[n + i] = a[i]; } long long int v1 = 0, v2 = 0; for (long long int i = 0; i < 2 * n; i++) { v1 += (a[i] * (a[i] + 1)) / 2; v2 += a[i]; p1[i] = v1; p2[i] = v2; } long long int mx = 0; for (long long int i = 2 * n - 1; i > n - 1; i--) { long long int val = BinSea(p2, 0, i, k); long long int fullmt = p1[i] - p1[val]; long long int remdy = a[val] - (k - (p2[i] - p2[val])); long long int sumrem = remdy * (remdy + 1) / 2; long long int sum = a[val] * (a[val] + 1) / 2; fullmt += (sum - sumrem); mx = max(mx, fullmt); } cout << mx << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long t, d, ct, q, ans, l, m, r, n, mx, mn, i, j, k, x, y, z, s; char ch; string ss = , str = ; long long a[200003], b[200003]; int main() { ios_base::sync_with_stdio(false), cin.tie(nullptr); s = k = d = l = mx = m = mn = r = q = i = j = z = x = y = ct = ans = 0; stack<long long> st; cin >> ss; n = ss.length(); long long dp[n + 2]; memset(dp, 0, sizeof(dp)); for (i = 0; i < n; i++) { if (ss[i] == ( ) { st.push(i); continue; } if (st.empty()) continue; long long lft = st.top(); st.pop(); if (lft) dp[i] = dp[lft - 1] + i - lft + 1; else dp[i] = i - lft + 1; mx = max(mx, dp[i]); } for (i = 0; i < n; i++) if (dp[i] == mx) ct++; if (!mx) return cout << 0 1 , 0; cout << mx << << ct; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2000; int n, i, j; char s[maxn]; long long F[maxn][maxn]; long long P[maxn]; int main() { scanf( %d , &n); scanf( %s , s); P[1] = 1; for (i = 2; i <= 18; ++i) P[i] = 10LL * P[i - 1]; memset(F, 0, sizeof F); for (i = 0; i <= n; ++i) for (j = 0; j <= n; ++j) { if (i) F[i][j] = max(F[i][j], F[i - 1][j] + P[i - 1] * (s[n + n - i - j] - 0 )); if (j) F[i][j] = max(F[i][j], F[i][j - 1] + P[j - 1] * (s[n + n - i - j] - 0 )); } i = n, j = n; while (i || j) { if (i && F[i][j] == (F[i - 1][j] + P[i - 1] * (s[n + n - i - j] - 0 ))) putchar( H ), --i; else putchar( M ), --j; } printf( n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; set<int> s[100005]; int color[100005]; int main() { int n, m; while (~scanf( %d%d , &n, &m)) { int i, j, tmp = 0; int u, v, ans; for (i = 1; i <= n; i++) scanf( %d , &color[i]); for (j = 0; j < m; j++) { scanf( %d%d , &u, &v); if (color[u] != color[v]) { s[color[v]].insert(color[u]); s[color[u]].insert(color[v]); } } ans = color[1]; for (i = 1; i <= n; i++) { if (s[color[i]].size() > tmp || (s[color[i]].size() == tmp && color[i] < ans)) { tmp = s[color[i]].size(); ans = color[i]; } } printf( %d n , ans); } return 0; }
|
#include <bits/stdc++.h> using namespace std; vector<set<int> > arr; long long res = 0; void dfs(int vertex, int prev, int level) { for (int v : arr[vertex]) { if (v == prev) { continue; } if (level == 2) { res++; continue; } else { dfs(v, vertex, level + 1); } } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; arr = vector<set<int> >(n + 1); for (int i = 0; i < n; ++i) { int a, b; cin >> a >> b; arr[a].insert(b); arr[b].insert(a); } for (int i = 1; i <= n; ++i) { dfs(i, -1, 1); } cout << res / 2 << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> a; int cnt = 0; int sum = 0; for (int i = 0; i < 2 * n - 1; ++i) { int x; cin >> x; a.push_back(abs(x)); if (x < 0) cnt++; sum += abs(x); } cnt %= n; queue<int> q; vector<bool> used(n + 1, false); used[cnt] = 1; q.push(cnt); int c = cnt; while (!q.empty()) { int u = q.front(); q.pop(); if (!used[n - u]) { used[n - u] = 1; q.push(n - u); c = min(c, n - u); } for (int i = 1; i <= u; ++i) { int to = u - i + n - i; to %= n; if (to >= 0 && !used[to]) { used[to] = 1; q.push(to); c = min(c, to); } } } sort(a.begin(), a.end()); if (c == 0) { cout << sum; } else { for (int i = 0; i < c; ++i) { sum -= 2 * a[i]; } cout << sum; } return 0; }
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rotate.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: A simple module to perform to rotate the input data
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rotate
#(
parameter C_DIRECTION = "LEFT",
parameter C_WIDTH = 4
)
(
input [C_WIDTH-1:0] WR_DATA,
input [clog2s(C_WIDTH)-1:0] WR_SHIFTAMT,
output [C_WIDTH-1:0] RD_DATA
);
`include "functions.vh"
wire [2*C_WIDTH-1:0] wPreShiftR;
wire [2*C_WIDTH-1:0] wPreShiftL;
wire [2*C_WIDTH-1:0] wShiftR;
wire [2*C_WIDTH-1:0] wShiftL;
assign wPreShiftL = {WR_DATA,WR_DATA};
assign wPreShiftR = {WR_DATA,WR_DATA};
assign wShiftL = wPreShiftL << WR_SHIFTAMT;
assign wShiftR = wPreShiftR >> WR_SHIFTAMT;
generate
if(C_DIRECTION == "LEFT") begin
assign RD_DATA = wShiftL[2*C_WIDTH-1:C_WIDTH];
end else if (C_DIRECTION == "RIGHT") begin
assign RD_DATA = wShiftR[C_WIDTH-1:0];
end
endgenerate
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Apod.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Apod (
address,
clock,
q);
input [10:0] address;
input clock;
output [63:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "apod"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Apod.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Apod.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=apod"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL address[10..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Apod_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> int main() { char p[1000001]; int n, m, y2; int y1 = -1; long long ans = 1; scanf( %d %d , &n, &m); scanf( %s , p); int plen = strlen(p); for (int i = 0; i < m; ++i) { scanf( %d , &y2); if (-1 == y1) { n -= plen; } else if (y2 - y1 < plen) { if (p[y2 - y1] != p[0]) { printf( 0 n ); return 0; } n -= y2 - y1; } else { n -= plen; } y1 = y2; } for (int i = 0; i < n; ++i) { ans = ans * 26 % 1000000007; } printf( %I64d n , ans); return 0; }
|
/**
* This file is part of pyBAR.
*
* pyBAR is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* pyBAR is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with pyBAR. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
// modified for 12MHz CmdClk and 12MHz Do Clk
// replace any existing file with this file
`timescale 1ns / 1ps
`default_nettype none
module clk_gen_12mhz (
U1_CLKIN_IN,
U1_USER_RST_IN,
U1_CLKIN_IBUFG_OUT,
U1_CLK0_OUT,
U1_STATUS_OUT,
U2_CLKFX_OUT,
U2_CLKDV_OUT,
U2_CLK0_OUT,
U2_CLK2X_OUT,
U2_LOCKED_OUT,
U2_STATUS_OUT
);
input wire U1_CLKIN_IN;
input wire U1_USER_RST_IN;
output wire U2_CLKFX_OUT;
output wire U1_CLKIN_IBUFG_OUT;
output wire U1_CLK0_OUT;
output wire [7:0] U1_STATUS_OUT;
output wire U2_CLKDV_OUT;
output wire U2_CLK0_OUT;
output wire U2_CLK2X_OUT;
output wire U2_LOCKED_OUT;
output wire [7:0] U2_STATUS_OUT;
wire GND_BIT;
wire U1_CLKIN_IBUFG;
wire U1_CLK0_BUF;
wire U1_LOCKED_INV_IN;
wire U1_RST_IN;
wire U2_CLKDV_BUF;
wire U2_CLKFB_IN;
wire U2_CLKFX_BUF;
wire U2_CLK0_BUF;
wire U2_CLK2X_BUF;
wire U2_LOCKED_INV_RST;
wire U2_RST_IN;
wire CLKFX_OUT;
wire CLKFX_OUT_IBUFG;
assign GND_BIT = 0;
assign U1_CLKIN_IBUFG_OUT = U1_CLKIN_IBUFG;
assign U2_CLK0_OUT = U2_CLKFB_IN;
assign U2_CLKFX_OUT = U2_CLKFB_IN;
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(12),
.CLKFX_MULTIPLY(10), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_INST1 (
.CLKFB(U1_CLK0_OUT),
.CLKIN(U1_CLKIN_IBUFG), // 48MHz
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(U1_RST_IN),
.CLKDV(CLKFX_OUT), // 12MHz
.CLKFX(),
.CLKFX180(),
.CLK0(U1_CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(U1_LOCKED_INV_IN),
.PSDONE(),
.STATUS(U1_STATUS_OUT[7:0]));
DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(10.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(2), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(83.333), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_INST2 (
.CLKFB(U2_CLKFB_IN),
.CLKIN(CLKFX_OUT_IBUFG), // 12MHz
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(U2_RST_IN),
.CLKDV(U2_CLKDV_BUF), // 1.2MHz
.CLKFX(),
.CLKFX180(),
.CLK0(U2_CLK0_BUF), // 12MHz
.CLK2X(U2_CLK2X_BUF), // 24MHz
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(U2_LOCKED_OUT),
.PSDONE(),
.STATUS(U2_STATUS_OUT[7:0]));
IBUFG U1_CLKIN_IBUFG_INST (.I(U1_CLKIN_IN),
.O(U1_CLKIN_IBUFG));
BUFG U1_CLK0_BUFG_INST (.I(U1_CLK0_BUF),
.O(U1_CLK0_OUT));
BUFG U2_CLKDV_BUFG_INST (.I(U2_CLKDV_BUF),
.O(U2_CLKDV_OUT));
//BUFG U2_CLKFX_BUFG_INST (.I(U2_CLKFX_BUF),
// .O(U2_CLKFX_OUT));
BUFG U2_CLK0_BUFG_INST (.I(U2_CLK0_BUF),
.O(U2_CLKFB_IN));
BUFG U2_CLK2X_BUFG_INST (.I(U2_CLK2X_BUF),
.O(U2_CLK2X_OUT));
BUFG U1_CLK_OUT_BUFG_INST (.I(CLKFX_OUT),
.O(CLKFX_OUT_IBUFG));
wire U1_FDS_Q_OUT;
wire U1_FD1_Q_OUT;
wire U1_FD2_Q_OUT;
wire U1_FD3_Q_OUT;
wire U1_OR3_O_OUT;
FDS U1_FDS_INST (.C(U1_CLKIN_IBUFG),
.D(GND_BIT),
.S(GND_BIT),
.Q(U1_FDS_Q_OUT));
FD U1_FD1_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FDS_Q_OUT),
.Q(U1_FD1_Q_OUT));
FD U1_FD2_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FD1_Q_OUT),
.Q(U1_FD2_Q_OUT));
FD U1_FD3_INST (.C(U1_CLKIN_IBUFG),
.D(U1_FD2_Q_OUT),
.Q(U1_FD3_Q_OUT));
INV U1_INV_INST (.I(U1_LOCKED_INV_IN),
.O(U2_LOCKED_INV_RST));
OR2 U1_OR2_INST (.I0(U1_USER_RST_IN),
.I1(U1_OR3_O_OUT),
.O(U1_RST_IN));
OR3 U1_OR3_INST (.I0(U1_FD3_Q_OUT),
.I1(U1_FD2_Q_OUT),
.I2(U1_FD1_Q_OUT),
.O(U1_OR3_O_OUT));
wire U2_FDS_Q_OUT;
wire U2_FD1_Q_OUT;
wire U2_FD2_Q_OUT;
wire U2_FD3_Q_OUT;
wire U2_OR3_O_OUT;
FDS U2_FDS_INST (.C(CLKFX_OUT_IBUFG),
.D(GND_BIT),
.S(GND_BIT),
.Q(U2_FDS_Q_OUT));
FD U2_FD1_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FDS_Q_OUT),
.Q(U2_FD1_Q_OUT));
FD U2_FD2_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FD1_Q_OUT),
.Q(U2_FD2_Q_OUT));
FD U2_FD3_INST (.C(CLKFX_OUT_IBUFG),
.D(U2_FD2_Q_OUT),
.Q(U2_FD3_Q_OUT));
OR2 U2_OR2_INST (.I0(U2_LOCKED_INV_RST),
.I1(U2_OR3_O_OUT),
.O(U2_RST_IN));
OR3 U2_OR3_INST (.I0(U2_FD3_Q_OUT),
.I1(U2_FD2_Q_OUT),
.I2(U2_FD1_Q_OUT),
.O(U2_OR3_O_OUT));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_SYMBOL_V
`define SKY130_FD_SC_HD__A21O_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_V
|
#include <bits/stdc++.h> int temp[500000], a[500000], indices[500000], increments[500000], previous_appearance[500000], numbers_equal_c[500000]; void mergesort(int Array[], int indices[], int first, int last) { if (first == last) return; int middle = (first + last) / 2; mergesort(Array, indices, first, middle); mergesort(Array, indices, middle + 1, last); int i, j, k; for (i = first, j = first, k = middle + 1; i <= last; i++) { if (j == middle + 1) temp[i] = indices[k++]; else if (k == last + 1) temp[i] = indices[j++]; else if (Array[indices[k]] < Array[indices[j]]) temp[i] = indices[k++]; else temp[i] = indices[j++]; } for (i = first; i <= last; i++) { indices[i] = temp[i]; } } int main() { int n, i, one_counter = 0, c, maximum_increament = 0, number_equal_to_c = 0; scanf( %d %d , &n, &c); for (i = 0; i < n; i++) { scanf( %d , &a[i]); indices[i] = i; previous_appearance[i] = -1; numbers_equal_c[i] = 0; increments[i] = 0; } mergesort(a, indices, 0, n - 1); for (i = 1; i < n; i++) { if (a[indices[i]] == a[indices[i - 1]]) { previous_appearance[indices[i]] = indices[i - 1]; } } for (i = 0; i < n; i++) { if (a[i] == c) { number_equal_to_c++; } else { if (previous_appearance[i] == -1 || increments[previous_appearance[i]] - number_equal_to_c + numbers_equal_c[previous_appearance[i]] + 1 <= 0) increments[i] = 1; else increments[i] = increments[previous_appearance[i]] - number_equal_to_c + numbers_equal_c[previous_appearance[i]] + 1; if (maximum_increament < increments[i]) maximum_increament = increments[i]; } numbers_equal_c[i] = number_equal_to_c; } printf( %d , number_equal_to_c + maximum_increament); return 0; }
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#include <bits/stdc++.h> static const int MaxSize = 1e5; int tree[4 * MaxSize][2]; static void build(std::vector<int> &v, int vertex, int tl, int tr) { if (tl == tr) tree[vertex][0] = v[tl]; else { int tm = (tl + tr) / 2; build(v, 2 * vertex + 1, tl, tm + 0); build(v, 2 * vertex + 2, tm + 1, tr); tree[vertex][0] = std::min(tree[2 * vertex + 1][0], tree[2 * vertex + 2][0]); } } static void update(int vertex, int tl, int tr, int l, int r, int x) { if (l > r) return; if (l == tl && tr == r) tree[vertex][1] += x; else { int tm = (tl + tr) / 2; update(2 * vertex + 1, tl, tm + 0, l, std::min(r, tm + 0), x); update(2 * vertex + 2, tm + 1, tr, std::max(l, tm + 1), r, x); tree[vertex][0] = std::min(tree[2 * vertex + 1][0] + tree[2 * vertex + 1][1], tree[2 * vertex + 2][0] + tree[2 * vertex + 2][1]); } } static int get(int vertex, int tl, int tr, int l, int r, int x) { if (l == tl && tr == r) return tree[vertex][0] + tree[vertex][1]; x += tree[vertex][1]; int tm = (tl + tr) / 2; return std::min( x + get(2 * vertex + 1, tl, tm + 0, l, std::min(r, tm + 0), x), x + get(2 * vertex + 2, tm + 1, tr, std::max(l, tm + 1), r, x)); } static void build(std::vector<int> &v, int n) { build(v, 0, 0, n - 1); } static void update(int n, int l, int r, int x) { update(0, 0, n - 1, l, r, x); } static int get(int n, int l, int r) { return get(0, 0, n - 1, l, r, 0); } int main(int argc, const char *argv[]) { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int n, m; std::cin >> n >> m; std::vector<int> v(n), tree(4 * n); for (int i = 0; i < n; i++) std::cin >> v[i]; std::vector<std::pair<int, int>> p(m); for (int i = 0; i < m; i++) { std::cin >> p[i].first >> p[i].second; p[i].first--; p[i].second--; } build(v, n); std::vector<bool> used(m); std::vector<int> t(4 * n), r; int result = 0; for (int i = 0; i < n; i++) { std::vector<int> intervals; for (int j = 0; j < m; j++) { if (p[j].first <= i && i <= p[j].second) { if (used[j]) { used[j] = false; update(n, p[j].first, p[j].second, 1); } } else { if (!used[j]) update(n, p[j].first, p[j].second, -1); intervals.push_back(j + 1); used[j] = true; } } int curr = v[i] - get(n, 0, n - 1); if (result < curr) { result = curr; std::swap(r, intervals); } } std::cout << result << std::endl; std::cout << r.size() << std::endl; if (r.size() > 0) { for (int number : r) std::cout << number << ; std::cout << std::endl; } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 21 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_21 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_21 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21_V
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#include <bits/stdc++.h> using namespace std; struct Lem { int m, v, id; bool operator<(Lem b) const { return m < b.m || (m == b.m && v < b.v); } }; int n, k, h; Lem a[(100000 + 10)]; bool can(double t) { int j = k; for (int i(n - 1), _l(0); i >= _l; --i) { if (j > 0 && (double)j * h / a[i].v - t <= -1e-10) j--; } return j == 0; } void putAns(double t) { int ans[(100000 + 10)]; int j = k; for (int i(n - 1), _l(0); i >= _l; --i) { if (j > 0 && (double)j * h / a[i].v - t <= -1e-10) ans[--j] = a[i].id; } for (int i(0), _n(k - 1); i < _n; ++i) printf( %d , ans[i]); printf( %d n , (ans[k - 1])); } int main() { scanf( %d , &(n)), scanf( %d , &(k)), scanf( %d , &(h)); for (int i(0), _n(n); i < _n; ++i) scanf( %d , &(a[i].m)), a[i].id = i + 1; for (int i(0), _n(n); i < _n; ++i) scanf( %d , &(a[i].v)); sort(a, a + n); double l = 1e-10, r = 1e10; int cnt = 100; while (cnt--) { double mid = (l + r) / 2.0; if (can(mid)) r = mid; else l = mid; } putAns(r); return 0; }
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#include <bits/stdc++.h> using namespace std; int times, used[200010], t[200010], first[200010], last[200010], d[200010], n, a[200010]; vector<vector<int> > g(200010); void dfs(int v, int pr) { used[v] = 1; first[v] = ++times; d[v] = d[pr] + 1; for (int i = 0; i < g[v].size(); i++) { if (!used[g[v][i]]) dfs(g[v][i], v); } last[v] = times; } int f(int i) { return (i & (-i)); } void in(int i, int val) { while (i <= n) { t[i] += val; i = i + f(i); } } int gget(int i) { int res = 0; while (i > 0) { res += t[i]; i = i - f(i); } return res; } int main() { int m, i, x, y, val, q; cin >> n >> m; for (i = 1; i <= n; i++) { cin >> a[i]; } for (i = 0; i < n - 1; i++) { cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs(1, 0); for (i = 0; i < m; i++) { scanf( %d , &q); scanf( %d , &x); if (q == 1) { scanf( %d , &val); in(first[x], val * (d[x] % 2 == 0 ? 1 : -1)); in(last[x] + 1, val * (d[x] % 2 == 0 ? -1 : 1)); } else { int ans = gget(first[x]) * (d[x] % 2 == 0 ? 1 : -1) + a[x]; printf( %d n , ans); } } return 0; }
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#include <bits/stdc++.h> FILE *in = stdin, *out = stdout; using namespace std; int n; vector<int> son[5005]; int tot; vector<int> edge[5005]; int dy[5005][2][5005]; int leaf[5005]; int visit[5005]; void input() { fscanf(in, %d , &n); for (int i = (1); i <= (n - 1); i++) { int x, y; fscanf(in, %d , &x), fscanf(in, %d , &y); edge[x].push_back(y); edge[y].push_back(x); } } int temp[2][5005]; void go(int x) { visit[x] = 1; int flag = 0; for (auto &i : edge[x]) { if (visit[i]) continue; go(i); if (flag == 0) dy[x][0][0] = dy[x][1][0] = 0; flag = 1; for (int j = (0); j <= (leaf[x] + leaf[i]); j++) temp[0][j] = temp[1][j] = 0x7fffffff; for (int p1 = (0); p1 <= (1); p1++) for (int p2 = (0); p2 <= (1); p2++) for (int j = (0); j <= (leaf[x]); j++) for (int k = (0); k <= (leaf[i]); k++) if (dy[x][p1][j] != 0x7fffffff && dy[i][p2][k] != 0x7fffffff) temp[p1][j + k] = min(temp[p1][j + k], dy[x][p1][j] + dy[i][p2][k] + (p1 == p2 ? 0 : 1)); for (int j = (0); j <= (leaf[x] + leaf[i]); j++) for (int k = (0); k <= (1); k++) dy[x][k][j] = temp[k][j]; leaf[x] += leaf[i]; } if (flag == 0) { leaf[x] = 1; dy[x][0][0] = 0; dy[x][1][1] = 0; tot++; } } void pro() { for (int i = (0); i <= (n); i++) for (int j = (0); j <= (n); j++) dy[i][0][j] = dy[i][1][j] = 0x7fffffff; for (int i = (1); i <= (n); i++) if (edge[i].size() > 1) { go(i); fprintf(out, %d , dy[i][1][tot / 2]); return; } } int main() { input(); if (n == 2) fprintf(out, 1 ); else pro(); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d%d , &n, &m); if (n < 2) printf( %d n , n); else if (n / 2 < m) printf( %d n , m - 1); else printf( %d n , m + 1); }
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; long long int a = 0, b = 0, c = 0; for (int i = 0; i < s.length(); i++) { if (i > 0 && s[i - 1] == v && s[i] == v ) { a++; c += b; } else if (s[i] == o ) { b += a; } } cout << c; return 0; }
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// ============================================================================
module iserdes_idelay_histogram #
(
parameter UART_PRESCALER = 868, // UART prescaler
parameter ISERDES_MODE = "DDR",
parameter ISERDES_WIDTH = 8
)
(
// Closk & reset
input wire CLK,
input wire RST,
// UART
input wire UART_RX,
output wire UART_TX,
// Input and output pins
output wire O,
input wire I,
// Signals at the input of the comparator (for monitoring)
output wire REF_O,
output wire REF_I,
output wire REF_C,
// IDELAY delay setting output
output wire [4:0] DELAY
);
// ============================================================================
// Data generator
// Serialized data clock generator
reg [2:0] ce_cnt;
wire ce_x2_p;
wire ce_x2_n;
wire ce_x1_p;
wire ce_x1_n;
initial ce_cnt <= 0;
always @(posedge CLK)
ce_cnt <= ce_cnt + 1;
assign ce_x2_p = (ce_cnt[0:0] == 0) && !ce_cnt[1];
assign ce_x2_n = (ce_cnt[0:0] == 0) && ce_cnt[1];
assign ce_x1_p = (ce_cnt[1:0] == 0) && !ce_cnt[2];
assign ce_x1_n = (ce_cnt[1:0] == 0) && ce_cnt[2];
// LFSR
wire [15:0] lfsr_r;
lfsr lfsr
(
.clk (CLK),
.rst (RST),
.ce ((ISERDES_MODE == "SDR") ? ce_x1_p : ce_x2_p),
.r (lfsr_r)
);
// Data serializer
reg o_clk;
reg o_stb;
wire o_dat;
always @(posedge CLK)
if (RST)
o_clk <= 1'b0;
else if (ce_x1_p)
o_clk <= 1'b1;
else if (ce_x1_n)
o_clk <= 1'b0;
always @(posedge CLK)
if (RST)
o_stb <= 1'b0;
else begin
if (ISERDES_MODE == "SDR")
o_stb <= ce_x1_p;
else if (ISERDES_MODE == "DDR")
o_stb <= ce_x2_p;
end
assign o_dat = lfsr_r[0];
// Output the data, the clock is routed internally.
assign O = o_dat;
// ============================================================================
// Data input with IDELAY and ISERDES
wire dly_dat;
wire dly_ld;
wire [4:0] dly_cnt;
wire [7:0] ser_dat;
wire ser_dat_ref;
wire ser_rst;
reg ser_clk;
wire ser_clkdiv;
// Delay the ISERDES clock by 1 CLK. This aligns serialized clock and data
// edges and allow to expose influende of differend IDELAY settings.
always @(posedge CLK)
ser_clk <= o_clk;
// ISERDES reset generator (required for it to work properly!)
reg [3:0] ser_rst_sr;
initial ser_rst_sr <= 4'hF;
always @(posedge ser_clkdiv or posedge RST)
if (RST) ser_rst_sr <= 4'hF;
else ser_rst_sr <= ser_rst_sr >> 1;
assign ser_rst = ser_rst_sr[0];
// BUFR - generation of CLKDIV
localparam DIVIDE = (ISERDES_MODE == "SDR" && ISERDES_WIDTH == 2) ? "2" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 3) ? "3" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 4) ? "4" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 5) ? "5" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 6) ? "6" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 7) ? "7" :
(ISERDES_MODE == "SDR" && ISERDES_WIDTH == 8) ? "8" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 4) ? "2" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 6) ? "3" :
(ISERDES_MODE == "DDR" && ISERDES_WIDTH == 8) ? "4" : "BYPASS";
BUFR #
(
.BUFR_DIVIDE (DIVIDE)
)
bufr
(
.I (ser_clk),
.O (ser_clkdiv),
.CLR (RST),
.CE (1'd1)
);
// IDELAY
IDELAYE2 #
(
.IDELAY_TYPE ("VAR_LOAD"),
.DELAY_SRC ("IDATAIN")
)
idelay
(
.IDATAIN (I),
.DATAOUT (dly_dat),
.C (CLK),
.LD (dly_ld),
.CNTVALUEIN (dly_cnt),
.CNTVALUEOUT (DELAY)
);
// ISERDES
ISERDESE2 #
(
.DATA_RATE (ISERDES_MODE),
.DATA_WIDTH (ISERDES_WIDTH),
.INTERFACE_TYPE ("NETWORKING"),
.NUM_CE (1),
.IOBDELAY ("BOTH"),
.IS_CLKB_INVERTED (1)
)
iserdes
(
.DDLY (dly_dat),
.O (ser_dat_ref),
.Q1 (ser_dat[0]),
.Q2 (ser_dat[1]),
.Q3 (ser_dat[2]),
.Q4 (ser_dat[3]),
.Q5 (ser_dat[4]),
.Q6 (ser_dat[5]),
.Q7 (ser_dat[6]),
.Q8 (ser_dat[7]),
.CLK (ser_clk),
.CLKB (ser_clk),
.CLKDIV (ser_clkdiv),
.CE1 (1'b1),
.RST (ser_rst),
.BITSLIP (1'b0)
);
// ============================================================================
// Data serializer
// ISERDES clock edge detector
reg ser_clk_r;
reg ser_clkdiv_r;
always @(posedge CLK)
ser_clk_r <= ser_clk;
always @(posedge CLK)
ser_clkdiv_r <= ser_clkdiv;
wire ser_clk_e = (ISERDES_MODE == "SDR") ? (ser_clk && !ser_clk_r) :
(ISERDES_MODE == "DDR") ? (ser_clk ^ ser_clk_r) : 0;
wire ser_clkdiv_e = ser_clkdiv && !ser_clkdiv_r;
// Data serializer
reg [7:0] ser2_sr;
wire ser2_stb;
wire ser2_dat;
always @(posedge CLK)
if (ser_clk_e && ser_clkdiv_e)
ser2_sr <= ser_dat;
else if (ser_clk_e)
ser2_sr <= ser2_sr << 1;
assign ser2_stb = ser_clk_e;
assign ser2_dat = ser2_sr[ISERDES_WIDTH-1];
// ============================================================================
// Output data delay needed to compensate ISERDES latency
reg [23:0] bit_sr;
reg bit_stb;
wire bit_dat;
always @(posedge CLK)
bit_stb <= o_stb;
always @(posedge CLK)
if (o_stb) bit_sr <= (bit_sr << 1) | o_dat;
localparam BIT_DELAY = (ISERDES_MODE == "SDR") ? (ISERDES_WIDTH * 2 - 2) :
/*(ISERDES_MODE == "DDR")*/ (ISERDES_WIDTH + 4);
assign bit_dat = bit_sr[BIT_DELAY];
// ============================================================================
// Data comparator
reg cmp_s0_stb;
reg cmp_s0_o_dat;
reg cmp_s0_i_dat;
reg cmp_s1_stb;
reg cmp_s1_err;
always @(posedge CLK)
if (RST)
cmp_s0_stb <= 1'b0;
else
cmp_s0_stb <= bit_stb;
always @(posedge CLK)
if (o_stb)
cmp_s0_o_dat <= bit_dat;
always @(posedge CLK)
if (o_stb)
cmp_s0_i_dat <= ser2_dat;
always @(posedge CLK)
if (RST)
cmp_s1_stb <= 1'b0;
else
cmp_s1_stb <= cmp_s0_stb;
always @(posedge CLK)
cmp_s1_err <= cmp_s0_o_dat ^ cmp_s0_i_dat;
reg o_dat_r;
always @(posedge CLK)
o_dat_r <= o_dat;
// Reference output
assign REF_O = o_dat_r;
assign REF_I = ser_dat_ref;
assign REF_C = ser_clk;
// ============================================================================
// Error counter
wire cnt_stb;
wire [32*24-1:0] cnt_dat;
error_counter #
(
.COUNT_WIDTH (24),
.DELAY_TAPS (32),
.TRIGGER_INTERVAL (50000000),
.HOLDOFF_TIME (100),
.MEASURE_TIME (10000)
)
error_counter
(
.CLK (CLK),
.RST (RST),
.I_STB (cmp_s1_stb),
.I_ERR (cmp_s1_err),
.DLY_LD (dly_ld),
.DLY_CNT(dly_cnt),
.O_STB (cnt_stb),
.O_DAT (cnt_dat)
);
// ============================================================================
// Message formatter
wire uart_x_stb;
wire [7:0] uart_x_dat;
message_formatter #
(
.WIDTH (24),
.COUNT (32),
.TX_INTERVAL (UART_PRESCALER * 11) // 10 bits plus one more.
)
message_formatter
(
.CLK (CLK),
.RST (RST),
.I_STB (cnt_stb),
.I_DAT (cnt_dat),
.O_STB (uart_x_stb),
.O_DAT (uart_x_dat)
);
// ============================================================================
// UART
// Baudrate prescaler initializer
reg [7:0] reg_div_we_sr;
wire reg_div_we;
always @(posedge CLK)
if (RST) reg_div_we_sr <= 8'h01;
else reg_div_we_sr <= {reg_div_we_sr[6:0], 1'd0};
assign reg_div_we = reg_div_we_sr[7];
// The UART
simpleuart uart
(
.clk (CLK),
.resetn (!RST),
.ser_rx (UART_RX),
.ser_tx (UART_TX),
.reg_div_we ({reg_div_we, reg_div_we, reg_div_we, reg_div_we}),
.reg_div_di (UART_PRESCALER),
.reg_div_do (),
.reg_dat_we (uart_x_stb),
.reg_dat_re (1'd0),
.reg_dat_di ({24'd0, uart_x_dat}),
.reg_dat_do (),
.reg_dat_wait ()
);
// Debug
always @(posedge CLK)
if (uart_x_stb)
$display("%c", uart_x_dat);
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n, k; cin >> n >> k; vector<pair<int, pair<int, int> > > ans; int v[4][n]; for (int i = 0; i < 4; ++i) { for (int j = 0; j < n; ++j) { cin >> v[i][j]; } } for (int i = 1; i < 3; i++) { for (int j = 0; j < n; j++) { if (v[i][j] > 0) { int x = 0; if (i == 2) x = 3; if (v[x][j] == v[i][j]) { ans.push_back({v[i][j], {x + 1, j + 1}}); v[i][j] = 0; } } } } int koln = 0; for (int i = 1; i < 3; i++) { for (int j = 0; j < n; j++) { if (v[i][j] > 0) koln++; } } if (koln == 2 * n) { cout << -1; return 0; } int fl = 0; while (fl < koln) { for (int i = 1; i < 3; ++i) { for (int j = 0; j < n; ++j) { if (v[i][j] > 0) { if (i == 1) { if (j < n - 1) { if (v[i][j + 1] == 0) { swap(v[i][j], v[i][j + 1]); ans.push_back({v[i][j + 1], {i + 1, j + 2}}); } if (v[0][j + 1] == v[i][j + 1]) { ans.push_back({v[i][j + 1], {1, j + 2}}); v[i][j + 1] = 0; fl++; } } else if (v[2][j] == 0) { ans.push_back({v[i][j], {3, j + 1}}); swap(v[i][j], v[2][j]); if (v[2][j] == v[3][j]) { ans.push_back({v[2][j], {4, j + 1}}); v[2][j] = 0; fl++; } } } else { if (j > 0) { if (v[i][j - 1] == 0) { swap(v[i][j], v[i][j - 1]); ans.push_back({v[i][j - 1], {i + 1, j}}); } if (v[3][j - 1] == v[i][j - 1]) { ans.push_back({v[i][j - 1], {4, j}}); v[i][j - 1] = 0; fl++; } } else { if (v[1][j] == 0) { ans.push_back({v[i][j], {2, j + 1}}); swap(v[1][j], v[i][j]); } if (v[1][j] == v[0][j]) { ans.push_back({v[1][j], {1, j + 1}}); v[1][j] = 0; fl++; } } } } } } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { cout << ans[i].first << << ans[i].second.first << << ans[i].second.second << endl; } }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); long long n = 0, m = 0, mn = 0, mx = 0, l = 1, r = 0, k = 0, j = 1, i = 0, ans = 0; cin >> n; vector<int> a(n); for (auto &x : a) cin >> x; bool got = true; while (got) { while (i < l) { if (a[i] > l) { l = a[i]; } i++; } l = i + 1; m++; if (l == n + 1) { break; } } cout << m << endl; }
|
#include <bits/stdc++.h> using namespace std; const int N = (int)2e5 + 50, LOGN = 17; const int INF = (int)1e9; int n, k; int ord[N], in[N], tim = 0; char las[N]; int lc[N], rc[N]; int res[N]; string str; void dfs(int v) { if (lc[v] != -1) dfs(lc[v]); ord[tim] = v; in[v] = tim++; if (rc[v] != -1) dfs(rc[v]); } void solve(int v, int& rem) { int la = -1; int cur = v; for (int i = 0; i < (rem); ++i) { if (cur == -1) break; if (las[cur] != && las[cur] > str[cur]) { la = i; } cur = lc[cur]; } cur = v; vector<int> vs; for (int i = 0; i < (la + 1); ++i) { res[cur] = 1; rem--; vs.push_back(cur); cur = lc[cur]; } while (!vs.empty()) { if (rc[vs.back()] != -1) solve(rc[vs.back()], rem); vs.pop_back(); } } void print_ans(int v) { if (lc[v] != -1) print_ans(lc[v]); cout << str[v]; if (res[v]) cout << str[v]; if (rc[v] != -1) print_ans(rc[v]); } int pos[256]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> k; cin >> str; for (int i = 0; i < (n); ++i) { cin >> lc[i] >> rc[i]; lc[i]--, rc[i]--; } dfs(0); fill(pos, pos + 256, INF); for (int i = n - 1; i >= 0; i--) { pos[str[ord[i]]] = i; char f = ; for (char c = a ; c <= z ; c++) { if (c != str[ord[i]] && pos[f] > pos[c]) f = c; } las[ord[i]] = f; } solve(0, k); assert(k >= 0); print_ans(0); }
|
#include <bits/stdc++.h> using namespace std; vector<vector<int>> dg, og; vector<bool> vist; vector<int> dist; void bfs(int begin) { vist[begin] = true; dist[begin] = 0; queue<int> pq; pq.push(begin); while (!pq.empty()) { int a = pq.front(); pq.pop(); for (int i = 0; i < dg[a].size(); i++) { if (!vist[dg[a][i]]) { vist[dg[a][i]] = true; dist[dg[a][i]] = dist[a] + 1; pq.push(dg[a][i]); } } } } int distcounter(int a) { int count = 0; for (int i = 0; i < og[a].size(); i++) { if (dist[og[a][i]] == dist[a] - 1) count++; } return count; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; dg.resize(n + 1); dist.resize(n + 1); og.resize(n + 1); vist.assign(n + 1, false); int u, v; for (int i = 1; i <= m; i++) { cin >> u >> v; og[u].push_back(v); dg[v].push_back(u); } int k; cin >> k; vector<int> p; p.resize(k + 1); for (int i = 1; i <= k; i++) cin >> p[i]; bfs(p[k]); int small = 0, large = 0; for (int i = 1; i < k; i++) { int count = distcounter(p[i]); if (dist[p[i + 1]] != dist[p[i]] - 1) { small++; large++; } else { if (count > 1) { large++; } } } cout << small << << large << endl; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:14 04/19/2014
// Design Name:
// Module Name: Image_viewer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Image_viewer_top(ClkPort,
Hsync, Vsync, vgaRed, vgaGreen, vgaBlue,
MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE,
MemAdr, data,
An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp, Led,
btnC, btnR, btnL, btnU, btnD
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input ClkPort;
output MemOE, MemWR, MemClk, RamCS, RamUB, RamLB, RamAdv, RamCRE;
output [26:1] MemAdr;
inout [15:0] data;
//Button
input btnC, btnR, btnL, btnU, btnD;
//Light/Display
output An0, An1, An2, An3, Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp;
output Vsync, Hsync;
output [2:0] vgaRed;
output [2:0] vgaGreen;
output [2:1] vgaBlue;
output [1:0] Led;
reg [2:0] _vgaRed;
reg [2:0] _vgaGreen;
reg [1:0] _vgaBlue;
wire inDisplayArea;
wire [9:0] CounterX;
wire [9:0] CounterY;
reg [5:0] bitCounter;
assign vgaRed = _vgaRed;
assign vgaGreen = _vgaGreen;
assign vgaBlue = _vgaBlue;
assign Led = readImage;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
//Global Stuff
wire ClkPort, sys_clk, Reset;
reg [26:0] DIV_CLK;
assign sys_clk = ClkPort;
assign MemClk = DIV_CLK[0];
//Memory Stuff
reg [22:0] address;
reg [15:0] dataRegister[0:127];
reg [22:0] imageRegister[0:3];
always@(posedge sys_clk)
begin
imageRegister[2'b00][22:0] <= 23'b00000000000000000000000;
imageRegister[2'b01][22:0] <= 23'b00000000000000010000000;
imageRegister[2'b10][22:0] <= 23'b00000000000000100000000;
imageRegister[2'b11][22:0] <= 23'b00000000000000110000000;
end
wire [7:0] uByte;
wire [7:0] lByte;
reg [1:0] readImage;
reg [6:0] readAddress;
reg [6:0] writePointer;
reg [6:0] readRow;
assign uByte = data[15:8];
assign lByte = data[7:0];
//Button Stuff
wire BtnR_Pulse, BtnL_Pulse, BtnU_Pulse, BtnD_Pulse;
assign Reset = btnC;
//-------------------------------------------------------------------//
always @ (posedge sys_clk, posedge Reset)
begin : CLOCK_DIVIDER
if (Reset)
DIV_CLK <= 0;
else
DIV_CLK <= DIV_CLK + 1;
end
//--------------------Debounce Controllers--------------------//
ee201_debouncer #(.N_dc(20)) ee201_debouncer_left
(.CLK(MemClk), .RESET(Reset), .PB(btnL), .DPB( ),
.SCEN(BtnL_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_right
(.CLK(MemClk), .RESET(Reset), .PB(btnR), .DPB( ),
.SCEN(BtnR_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_up
(.CLK(MemClk), .RESET(Reset), .PB(btnU), .DPB( ),
.SCEN(BtnU_Pulse), .MCEN( ), .CCEN( ));
ee201_debouncer #(.N_dc(20)) ee201_debouncer_down
(.CLK(MemClk), .RESET(Reset), .PB(btnD), .DPB( ),
.SCEN(BtnD_Pulse), .MCEN( ), .CCEN( ));
//--------------------Display Controller--------------------//
DisplayCtrl display (.Clk(DIV_CLK), .reset(Reset), .memoryData(dataRegister[readRow][15:0]),
.An0(An0), .An1(An1), .An2(An2), .An3(An3),
.Ca(Ca), .Cb(Cb), .Cc(Cc), .Cd(Cd), .Ce(Ce), .Cf(Cf), .Cg(Cg), .Dp(Dp)
);
//--------------------Memory Controller--------------------//
MemoryCtrl memory(.Clk(MemClk), .Reset(Reset), .MemAdr(MemAdr), .MemOE(MemOE), .MemWR(MemWR),
.RamCS(RamCS), .RamUB(RamUB), .RamLB(RamLB), .RamAdv(RamAdv), .RamCRE(RamCRE), .writeData(writeData),
.AddressIn(address), .BtnU_Pulse(BtnU_Pulse), .BtnD_Pulse(BtnD_Pulse)
);
//--------------------VGA Controller--------------------//
VGACtrl vga(.clk(DIV_CLK[1]), .reset(Reset), .vga_h_sync(Hsync),
.vga_v_sync(Vsync), .inDisplayArea(inDisplayArea),
.CounterX(CounterX), .CounterY(CounterY)
);
reg toggleByte;
always @(posedge DIV_CLK[1], posedge Reset)
begin
if(Reset)
begin
bitCounter <= 0;
toggleByte <= 0;
readAddress <= 0;
end
else if(CounterY > 192 && CounterY < 288)
begin
if(CounterX == 0)
begin
bitCounter <= 0;
toggleByte <= 1'b0;
end
else if(CounterX > 284 && bitCounter < 35)
begin
if(toggleByte == 1'b0)
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][7:0];
toggleByte <= 1'b1;
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= dataRegister[readAddress][15:8];
toggleByte <= 1'b0;
bitCounter <= bitCounter + 1;
readAddress <= readAddress + 1;
end
end
else
begin
{_vgaRed, _vgaGreen, _vgaBlue} <= 0;
end
end
else if (CounterY == 288)
readAddress <= 0;
end
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readImage <= 0;
else if(BtnU_Pulse)
readImage <= readImage + 1;
else if(BtnD_Pulse)
readImage <= readImage - 1;
else
address <= imageRegister[readImage][22:0];
end
//--------------------Process Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
begin
writePointer <= 0;
end
else
if(writeData == 1'b1)
begin
dataRegister[writePointer][15:0] <= {lByte, uByte};
writePointer <= writePointer + 1;
end
else
writePointer <= 0;
end
//--------------------SSD Display Data--------------------//
always@(posedge MemClk, posedge Reset)
begin
if(Reset)
readRow <= 0;
else if(BtnR_Pulse)
readRow <= readRow + 1;
else if(BtnL_Pulse)
readRow <= readRow - 1;
end
endmodule
|
module hi_sniffer(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_clk
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
output ssp_frame, ssp_din, ssp_clk;
// We are only snooping, all off.
assign pwr_hi = 1'b0;
assign pwr_lo = 1'b0;
assign pwr_oe1 = 1'b0;
assign pwr_oe2 = 1'b0;
assign pwr_oe3 = 1'b0;
assign pwr_oe4 = 1'b0;
reg ssp_frame;
reg [7:0] adc_d_out = 8'd0;
reg [2:0] ssp_cnt = 3'd0;
assign adc_clk = ck_1356meg;
assign ssp_clk = ~ck_1356meg;
always @(posedge ssp_clk)
begin
if(ssp_cnt[2:0] == 3'd7)
ssp_cnt[2:0] <= 3'd0;
else
ssp_cnt <= ssp_cnt + 1;
if(ssp_cnt[2:0] == 3'b000) // set frame length
begin
adc_d_out[7:0] <= adc_d;
ssp_frame <= 1'b1;
end
else
begin
adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
ssp_frame <= 1'b0;
end
end
assign ssp_din = adc_d_out[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; class Graph { long long n; vector<long long> f, par, ans, sz, depth, value, size, fst, to, next; long long l; void swapUtil(long long &, long long &); long long getP(long long); long long dfsUtil(long long); void setDFS(); void setsz(); void setf(); void setAns(long long); public: Graph(); Graph(long long); void addEdge(long long, long long); void setSolve(long long); void solve(long long, long long, long long); void printAns(); }; void Graph ::swapUtil(long long &u, long long &v) { long long t = u; u = v; v = t; } long long Graph ::getP(long long u) { if (f[u] == u) return f[u]; else { f[u] = getP(f[u]); return f[u]; } } long long Graph ::dfsUtil(long long u) { depth[u] = depth[par[u]] + 1; for (long long i = fst[u]; i; i = next[i]) if (to[i] != par[u]) { par[to[i]] = u; long long t = dfsUtil(to[i]); value[u] += size[u] * t * 2; size[u] += t; } value[u] += size[u] * (n - size[u] - 1) * 2; ans[0] += value[u]; size[u]++; return size[u]; } void Graph ::setDFS() { dfsUtil(1); } void Graph ::setsz() { for (long long i = 1; i < n + 1; i++) sz[i] = 1; } void Graph ::setf() { for (long long i = 1; i < n + 1; i++) f[i] = i; } void Graph ::setAns(long long M) { ans.resize(M + 1); } Graph ::Graph() {} Graph ::Graph(long long N) { n = N - 1; f.resize(N); par.resize(N); ans.resize(N); sz.resize(N); depth.resize(N); value.resize(N); size.resize(N); fst.resize(N); to.resize(2 * N); next.resize(2 * N); l = 0; } void Graph ::addEdge(long long u, long long v) { to[++l] = v; next[l] = fst[u]; fst[u] = l; to[++l] = u; next[l] = fst[v]; fst[v] = l; } void Graph ::setSolve(long long m) { setAns(m); setf(); setsz(); setDFS(); } void Graph ::solve(long long u, long long v, long long i) { ans[i] = ans[i - 1]; u = getP(u); v = getP(v); while (u != v) { if (depth[u] < depth[v]) swap(u, v); long long t = getP(par[u]); ans[i] += sz[t] * sz[u] * (size[u] - sz[u]) * 2 + sz[t] * sz[u] * (sz[u] - 1); ans[i] += sz[u] * sz[t] * (n - size[u] - sz[t]) * 2 + sz[u] * sz[t] * (sz[t] - 1); ans[i] += sz[t] * (value[u] - (n - size[u]) * (size[u] - sz[u]) * 2); ans[i] += sz[u] * (value[t] - size[u] * (n - size[u] - sz[t]) * 2); value[t] = value[t] - sz[u] * (n - size[u] - sz[t]) * 2 + value[u] - (size[u] - sz[u]) * (n - size[u]) * 2; sz[t] += sz[u]; f[u] = t; u = t; } } void Graph ::printAns() { for (long long i = 0; i < ans.size(); i++) cout << ans[i] << endl; } signed main() { long long n; cin >> n; Graph g(n + 1); for (long long i = 0; i < n - 1; i++) { long long u, v; cin >> u >> v; g.addEdge(u, v); } long long m; cin >> m; g.setSolve(m); for (long long i = 0; i < m; i++) { long long u, v; cin >> u >> v; g.solve(u, v, i + 1); } g.printAns(); return 0; }
|
//****************************************************************************************************
//*----------------Copyright (c) 2016 C-L-G.FPGA1988.Roger Wang. All rights reserved------------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : sys_led_module.v
//Project Name : gt0000
//Description : The system led ctrl module.
//Github Address : https://github.com/C-L-G/gt0000/trunk/ic/digital/rtl/sys_aux_module/sys_led_module.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 29-08-2016 17:00(1th Fri,July,2016)
//First Author : Roger Wang
//Modify Date : 29-08-2016 14:20(1th Sun,July,2016)
//Last Author : Roger Wang
//Version Number : 001
//Last Commit : 29-08-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//dd.mm.yyyy - Author - Your log of change
//****************************************************************************************************
//29.08.2016 - Roger Wang - Add the led control logic.
//29.08.2016 - Roger Wang - The initial version.
//*---------------------------------------------------------------------------------------------------
`timescale 1ns/1ps
module sys_led_module(
led_clk ,//01 In
led_rst_n ,//01 In
led_in ,//01 In
led_out //08 Out
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
input led_clk ;//the led module clk = 20MHz
input led_rst_n ;//the led module reset,low active
input [07:00] led_in ;//the led module data input signals
output [07:00] led_out ;//the led module data output signals
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the system led module wire
//------------------------------------------------------------------------------------------------
reg [09:00] led_cnt ;//led count
wire led_clk ;
wire led_rst_n ;
wire [07:00] led_in ;
wire [07:00] led_out ;
//************************************************************************************************
// 4.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the led ctrl logic
//------------------------------------------------------------------------------------------------
always @(posedge led_clk or negedge led_rst_n) begin : SYS_LED_CTRL
if(!led_rst_n)
begin
led_cnt <= 'd0;
end
else
begin
led_cnt <= led_cnt + 1'b1;
end
end
assign led_out[00] = &led_in ;
assign led_out[01] = |led_in ;
assign led_out[02] = ~&led_in ;
assign led_out[03] = ~|led_in ;
assign led_out[04] = led_cnt[06] ;
assign led_out[05] = led_cnt[07] ;
assign led_out[06] = led_cnt[08] ;
assign led_out[07] = led_cnt[09] ;
//------------------------------------------------------------------------------------------------
// 4.2 the xxx module assignment
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 5.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 5.1 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.2 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.3 the xxx module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Mopdule
//****************************************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A32OI_PP_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; stack<int> s; int a[(int)(1e+6) * 5]; bool b[(int)(1e+6) * 5]; int main() { ios_base::sync_with_stdio(0); int n, i, t, x; cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; cin >> t; while (t > 0) cin >> x, b[x] = 1, t--; for (i = n; i > 0; i--) { x = -1; if (!s.empty()) x = s.top(); if (x != -1 && !b[i] && a[i] == a[x]) a[x] *= -1, s.pop(); else s.push(i); } if (!s.empty()) { cout << NO ; return 0; } cout << YES n ; for (i = 1; i <= n; i++) cout << a[i] << ; return 0; }
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dac_buf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dac_buf (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [8:0] rdaddress;
input [10:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL "rdaddress[8..0]"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_buf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int a[3]; int main() { cin >> a[0] >> a[1] >> a[2]; sort(a + 0, a + 3); int res = 0; while ((a[0] + a[1]) <= a[2]) { a[0]++; res++; } cout << res; }
|
`timescale 1ns/10ps
module vga_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("65.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; if (n & 1) { vector<int> v1, v2; bool flag = true; for (int i = 1; i <= 2 * n; i++) { if (flag) { v1.push_back(i); flag = !flag; } else { v2.push_back(i); flag = !flag; } } for (int i = 1; i < n; i += 2) { swap(v1[i], v2[i]); } cout << YES << endl; for (int i = 0; i < n; i++) cout << v1[i] << ; for (int i = 0; i < n; i++) cout << v2[i] << ; } else cout << NO << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, r1 = -1, p1 = -1, p2 = INT_MAX, x, a, b; cin >> n; while (n--) cin >> x, r1 = max(r1, x); cin >> n; while (n--) cin >> x, p1 = max(p1, x); cin >> n; while (n--) cin >> x, p2 = min(p2, x); cin >> a >> b; long double q = ((long long)(b * p1) / (long double)(a * p2 + b * p1)); q = sqrt(q); q *= r1; printf( %.12Lf n , q); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:05 10/11/2015
// Design Name:
// Module Name: UART_fifo_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_fifo_interface #(parameter bits_depth=4)(
input write_flag,
input read_next,
input [7:0] data_in,
input clock,
input reset,
output reg [7:0] data_out,
output reg empty_flag,
output reg full_flag
);
localparam depth= 1<<(bits_depth);
reg [7:0] FIFO [depth-1:0];
reg [(bits_depth-1):0] read_pointer,
write_pointer;
reg [(bits_depth):0] free_space;
always @* begin
full_flag = (free_space==0);
empty_flag = (free_space==depth);
end
always @(posedge clock, posedge reset) begin
if(reset) begin
write_pointer <= 0;
read_pointer <= 0;
free_space <= depth;
data_out <= 0;
end
else begin
data_out <= FIFO[read_pointer];
if(read_next) begin
if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
free_space <= free_space + 'b1;
end
end
if(write_flag) begin
FIFO[write_pointer] <= data_in;
write_pointer <= write_pointer + 'b1;
if(!full_flag) begin
free_space <= (free_space - 'b1) ;
end
else if(!empty_flag) begin
read_pointer <= read_pointer + 'b1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e3 + 5, mum = 1e9 + 7; int Pow(int A, long long B) { int num = 1; while (B) { if (B & 1) num = 1LL * num * A % mum; A = 1LL * A * A % mum; B >>= 1; } return num; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, m, k, r, c, ax, ay, bx, by; cin >> n >> m >> k >> r >> c >> ax >> ay >> bx >> by; cout << (ax == bx && ay == by ? Pow(k, 1LL * n * m) : Pow(k, 1LL * n * m - 1LL * r * c)) << n ; return 0; }
|
// DESCRIPTION: Example pli file for vpassert program
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2012 by Wilson Snyder.
`timescale 1ns/1ns
module pli;
// A module called PLI is required, to contain the error counts
// This is required with the vpassert --nostop option, which this example uses
// By default (--stop), this file isn't needed at all
integer errors; initial errors = 0;
integer warnings; initial warnings = 0;
// Normally this would be 0 at startup, then become 1 after reset deasserts
// This prevents false assertion checks during reset
integer message_on; initial message_on = 1;
always @ (errors or warnings) begin
`ifdef OPTIONAL_EXIT_ON_WARNING
if (errors!=0 || warnings!=0) begin
$uinfo (0, "Errors/warnings found, exiting!\n");
$finish;
end
`else
if (errors!=0) begin
$uinfo (0, "Errors found, exiting!\n");
$finish;
end
else if (warnings!=0) begin
$uinfo (0, {"Warnings found, ","consider stopping!\n"});
end
`endif
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int M = 1e9; int ask(int x, int y) { cout << ? << x << << y << endl; cin >> x; return x; } int main() { int s = ask(1, 1), k; int u, v, l = 1, r = M, mid; while (r > l + 1) { mid = l + r >> 1; k = ask(1, mid); if (k + mid - 1 != s) r = mid; else l = mid; } u = ask(1, l) + 1; v = l; printf( ! %d %d %d %d , u, v, v - 1 + M - ask(M, 1), u - 1 + M - ask(1, M)); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; int a[101]; int res = 0; void solve() { for (int i = 2; i < n; ++i) { if (a[i] == 0) { if (a[i - 1] == 1 && a[i + 1] == 1 && a[i + 2] == 0 && a[i + 3] == 1 && i - 1 > 0) { a[i + 1] = 0; ++res; i += 2; } else if (a[i + 1] == 1 && a[i - 1] == 1 && i - 1 > 0) { a[i + 1] = 0; ++res; ++i; } } } cout << res << endl; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; bool F[2001][2001]; bool D[2001][2001]; int C[2001]; vector<int> V[2001]; int n; void f(int v, int c) { if (C[v]) return; C[v] = c; V[c].push_back(v); for (int i = 1; i <= n; ++i) if (F[v][i]) f(i, c); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; int k; cin >> k; while (k--) { int a, b; cin >> a >> b; F[a][b] = 1; F[b][a] = 1; } cin >> k; while (k--) { int a, b; cin >> a >> b; D[a][b] = 1; D[b][a] = 1; } int ans = 0; for (int i = 1; i <= n; ++i) { f(i, i); int t = V[i].size(); for (int j = 0; j < t; ++j) for (int l = 0; l < t; ++l) if (D[V[i][j]][V[i][l]]) goto skip; ans = max(ans, t); skip:; } cout << ans << endl; return 0; }
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#include<bits/stdc++.h> using namespace std; #define FOR(i, j, k) for(int i = j; i <= k; i++) #define ROF(i, j, k) for(int i = j; i >= k; i--) #define PB push_back #define MEM(n, val) memset((n), val, sizeof(n)) #define FastIO ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); #define F first #define S second #define MP make_pair #define LL long long #define MOD 1000000007 #define MX 200010 #define INFL 1000000000000000000LL #define INF 1000000000 typedef pair<int, int> PII; typedef pair<LL, LL> PLL; int fx[] = {0, 0, 1, -1}; int fy[] = {1, -1, 0, 0}; int n, x; vector<int> adjl[100010]; int mxlev; int mxfreq; int lev_freq[100010]; int freq[100010]; vector<PII> frv; bool is_lev_a[100010]; int lev[100010]; vector<int> ultalv[100010]; void func(int u, int lv) { mxlev = max(lv, mxlev); lev_freq[lv]++; lev[u] = lv; ultalv[ lv ].PB(u); for(int v: adjl[u]) { func(v, lv + 1); } } int dp[450][100001]; //PII bt[320][100001]; map<int, int> mp_cnt; int main() { // freopen( in.txt , r , stdin); // freopen( out.txt , w , stdout); FastIO; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); cin >> n >> x; FOR(v, 2, n) { int u; cin >> u; adjl[u].PB(v); // cout << u << : << v << n ; } func(1, 1); FOR(i, 1, mxlev) { freq[ lev_freq[i] ]++; mxfreq = max(mxfreq, lev_freq[i]); } FOR(i, 1, mxfreq) { if(freq[i]) { frv.PB({i, freq[i]}); } } // FOR(i, 1, mxlev) { // cout << i << : << lev_freq[i] << n ; // } // cout << n ; // FOR(i, 1, mxfreq) { // cout << i << : << freq[i] << n ; // } // cout << n ; // for(PII val: frv) { // cout << val.F << : << val.S << n ; // } // if(x == 237) { // cout << sz : << frv.size() << endl; // } MEM(dp, -1); // MEM(bt, -1); int turn = 0; for(int i = 0; i < frv.size(); i++) { int val = frv[i].F; int fr = frv[i].S; dp[i][0] = 0; for(int j = 1; j <= x; j++) { if(i != 0 && dp[i - 1][j] >= 0) { dp[i][ j ] = 0; // bt[i][j] = {i - 1, j}; continue; } if((j - val >= 0) && (dp[i][j - val] >= 0) && (dp[i][j - val] < fr)) { dp[i][j] = dp[i][j - val] + 1; // bt[i][j] = {i, j - val}; } } } // cout << dp : n ; // for(int i = 0; i < frv.size(); i++) { // for(int j = 0; j <= x; j++) { // cout << dp[i][j] << ; // } // cout << n ; // } // cout << n ; // // cout << dp[ (int)frv.size() - 1 ][x] << n n ; if(dp[ (int)frv.size() - 1 ][x] >= 0) { int a = frv.size() - 1, b = x; while(a != -1 && b != -1) { if(dp[a][b]) { // cout << frv[a].F << : << dp[a][b] << n ; mp_cnt[ frv[a].F ] = max(mp_cnt[ frv[a].F ], dp[a][b]); } // cout << a << << b << : << frv[a].F << : << dp[a][b] << n ; PII nn = {-1, -1}; if(a != 0 && dp[a][b] == 0 && dp[a - 1][b] >= 0) { nn = {a - 1, b}; } int val = frv[a].F; int fr = frv[a].S; if((b - val >= 0) && (dp[a][b - val] >= 0) && (dp[a][b - val] < fr) && (dp[a][b] == dp[a][b - val] + 1)) { // dp[i][j] = dp[i][j - val] + 1; nn = {a, b - val}; // bt[i][j] = {i, j - val}; } a = nn.F; b = nn.S; } FOR(i, 1, mxlev) { if(mp_cnt[ lev_freq[i] ]) { mp_cnt[ lev_freq[i] ]--; is_lev_a[i] = 1; } } cout << mxlev << n ; FOR(i, 1, n) { if(is_lev_a[ lev[i] ]) { cout << a ; } else { cout << b ; } } return 0; } map<int, int> exp; int sum = n; FOR(i, 1, mxlev) { if(lev_freq[i] <= x) { is_lev_a[i] = 1; x -= lev_freq[i]; sum -= lev_freq[i]; } else if(lev_freq[i] <= sum - x) { sum -= lev_freq[i]; } else { vector<int> leaf, nonleaf; for(int u: ultalv[i]) { if(adjl[u].size() > 0) { nonleaf.PB(u); } else { leaf.PB(u); } } if(x >= nonleaf.size()) { /// use all x sum -= x; for(int u: nonleaf) { exp[u] = 1; } x -= nonleaf.size(); for(int j = 0; j < x; j++) { int u = leaf[j]; exp[u] = 1; } sum -= leaf.size() - x; x = 0; } else { /// use all sum - x // sum = x; // x = lev_freq[i] - (sum - x); sum -= nonleaf.size(); int leafbaki = (int)leaf.size() - (sum - x); for(int j = 0; j < leafbaki; j++) { int u = leaf[j]; exp[u] = 1; } x -= leafbaki; sum = x; } } } cout << mxlev + 1 << n ; FOR(i, 1, n) { if(exp[i]) { cout << a ; continue; } if(is_lev_a[ lev[i] ]) { cout << a ; } else { cout << b ; } } return 0; } /** 2000000000000 */
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#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const int N = 1e5 + 5, inf = 1e9 + 5; long long add(long long x, long long y) { x += y; if (x >= MOD) return x - MOD; return x; } long long sub(long long x, long long y) { x -= y; if (x < 0) return x + MOD; return x; } long long mult(long long x, long long y) { return (x * y) % MOD; } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int T; cin >> T; while (T--) { int n, m; cin >> n >> m; vector<int> row_sum(n), col_sum(m); vector<vector<bool>> a(n, vector<bool>(m)); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char c; cin >> c; row_sum[i] += c == * ; col_sum[j] += c == * ; a[i][j] = c == * ; } } int ans = inf; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { ans = min(ans, n - row_sum[i] + m - col_sum[j] - (!a[i][j])); } } cout << ans << endl; } }
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#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; long long dp[n + 3][2 * t + 3][5]; for (int i = 1; i <= 4; i++) { dp[n][2 * t - 1][i] = 1; for (int j = 0; j < 2 * t - 1; j++) { dp[n][j][i] = 0; } for (int j = 1; j <= n; j++) { dp[j][2 * t][i] = 0; } } for (int i = n - 1; i >= 1; i--) { for (int j = 2 * t - 1; j >= 0; j--) { for (int k = 1; k <= 4; k++) { dp[i][j][k] = 0; if (j % 2 == 0) { for (int p = 1; p < k; p++) { dp[i][j][k] = dp[i][j][k] + dp[i + 1][j + 1][p]; } for (int p = k + 1; p <= 4; p++) { dp[i][j][k] = dp[i][j][k] + dp[i + 1][j][p]; } } else { for (int p = 1; p < k; p++) { dp[i][j][k] = dp[i][j][k] + dp[i + 1][j][p]; } for (int p = k + 1; p <= 4; p++) { dp[i][j][k] = dp[i][j][k] + dp[i + 1][j + 1][p]; } } } } } long long ans = 0; for (int i = 1; i <= 4; i++) { ans = ans + (i - 1) * dp[2][0][i]; } cout << ans; return 0; }
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#include <bits/stdc++.h> using namespace std; const int MAXN = 100100; int N; long long K; int ar[MAXN]; int main() { cin >> N >> K; for (int i = 0; i < N; i++) cin >> ar[i]; --K; sort(ar, ar + N); for (int i = 0; i < N;) { int cur = i; int cnt = 0; while (i < N && ar[i] == ar[cur]) { ++i; ++cnt; } if (K < (long long)cnt * N) { cout << ar[cur] << << ar[(int)(K / cnt)] << endl; break; } K -= (long long)cnt * N; } return 0; }
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#include <bits/stdc++.h> using namespace std; template <typename T> void maxtt(T& t1, T t2) { t1 = max(t1, t2); } template <typename T> void mintt(T& t1, T t2) { t1 = min(t1, t2); } bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = URDL ; const long long MOD2 = (long long)1000000007 * (long long)1000000007; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? YES : NO ); exit(0); } void addmod(int& x, int y, int mod = 1000000007) { x += y; if (x >= mod) x -= mod; if (x < 0) x += mod; assert(x >= 0 && x < mod); } void et(int x = -1) { printf( %d n , x); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { return y ? gcd1(y, x % y) : x; } char s[3001335]; int id[3001335], cnt; int mt[3001335]; inline vector<int> cal(int l, int r) { vector<int> ans; if (l + 2 == r) { assert(s[l + 1] == * ); ans.push_back(id[l + 1]); return ans; } bool fg = 1; for (int i = l + 1; i < r;) { vector<int> tmp = cal(i, mt[i]); if (fg) { if (tmp.size() > ans.size()) swap(ans, tmp); for (int z : tmp) ans.push_back(z); } else { if (tmp.size() < ans.size()) swap(ans, tmp); } i = mt[i] + 1; if (i < r) { assert(s[i] == P || s[i] == S ); if (s[i] == S ) fg = 0; i++; } } return ans; } void fmain(int tid) { int r; scanf( %d , &r); n = 0; cnt = 0; while (1) { char x = getchar(); if (x == n ) break; if (x == ) continue; if (x == * ) { s[++n] = ( ; s[++n] = * ; id[n] = ++cnt; s[++n] = ) ; } else s[++n] = x; } vector<int> vp; for (int(i) = 1; (i) <= (int)(n); (i)++) { if (s[i] == ( ) vp.push_back(i); else if (s[i] == ) ) { int x = vp.back(); vp.pop_back(); mt[x] = i; mt[i] = x; } } vector<int> ans = cal(1, n); vector<bool> vis(cnt + 1, 0); for (int z : ans) vis[z] = 1; printf( REVOLTING ); for (int(i) = 1; (i) <= (int)(cnt); (i)++) if (vis[i]) { printf( %lld , (long long)r * ans.size()); } else printf( 0 ); puts( ); } int main() { int t = 1; scanf( %d , &t); for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; }
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_TB_V
`define SKY130_FD_SC_HDLL__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hdll__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_TB_V
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#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 5; const int MOD = 1000000007; int a[300005]; int main() { int n, p; cin >> n >> p; for (int i = 1; i <= n; i++) cin >> a[i]; while (p--) { int l, r, x; cin >> l >> r >> x; int lar = r - x; int num = a[x]; int count = 0; for (int i = l; i <= r; i++) { if (a[i] > num) { count++; } } if (count == lar) { cout << Yes << endl; } else cout << No << endl; } }
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