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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_1_V
`define SKY130_FD_SC_LS__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_1_V
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module RAMSpartan3StarterKit(
// Clock Sources
CLK50MHZ,
SOCKET,
// Fast, Asynchronous SRAM
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
// Four-Digit, Saven-Segment LED Display
LED_AN,
LED_A,
LED_B,
LED_C,
LED_D,
LED_E,
LED_F,
LED_G,
LED_DP,
// Switch
SW,
// Button
BTN,
// LED
LD,
// VGA Port
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
// PS2
PS2C,
PS2D,
// RS-232 Serial Port
RXD,
TXD,
RXDA,
TXDA,
// Platform Flash (XCF02S Serial PROM)
DIN,
INIT_B,
RCLK);
input CLK50MHZ;
input SOCKET;
output [17:0] SRAM_A;
output SRAM_WE_X;
output SRAM_OE_X;
inout [15:0] SRAM_IO_A;
output SRAM_CE_A_X;
output SRAM_LB_A_X;
output SRAM_UB_A_X;
inout [15:0] SRAM_IO_B;
output SRAM_CE_B_X;
output SRAM_LB_B_X;
output SRAM_UB_B_X;
output [ 3:0] LED_AN;
output LED_A;
output LED_B;
output LED_C;
output LED_D;
output LED_E;
output LED_F;
output LED_G;
output LED_DP;
input [ 7:0] SW;
input [ 3:0] BTN;
output [ 7:0] LD;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
input PS2C;
input PS2D;
input RXD;
output TXD;
input RXDA;
output TXDA;
input DIN;
output INIT_B;
output RCLK;
wire clk;
wire rst_x;
wire w_clk49khz;
wire [ 7:0] w_data;
reg [ 9:0] r_clock;
reg [15:0] r_addr;
reg r_enable_x;
reg r_write_x;
reg r_ram_init;
reg r_read;
reg r_read_d;
reg [ 7:0] r_read_data;
assign LD = SW | { 1'b0, BTN, PS2D, PS2C, SOCKET };
assign VGA_R = 1'b0;
assign VGA_G = 1'b0;
assign VGA_B = 1'b0;
assign VGA_HS = 1'b1;
assign VGA_VS = 1'b1;
assign TXD = RXD;
assign TXDA = RXDA;
assign INIT_B = DIN;
assign RCLK = DIN;
assign clk = CLK50MHZ;
assign rst_x = !BTN[3];
assign w_clk49khz = r_clock[9];
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_clock <= 10'h000;
end else begin
r_clock <= r_clock + 10'h001;
end
end
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_addr <= 16'h0000;
r_enable_x <= 1'b0;
r_write_x <= 1'b0;
r_ram_init <= 1'b1;
r_read <= 1'b0;
r_read_d <= 1'b0;
r_read_data <= 8'h00;
end else begin
if (r_ram_init) begin
if (r_addr == 16'hffff) begin
r_ram_init <= 1'b0;
r_write_x <= 1'b1;
end else begin
r_addr <= r_addr + 16'h0001;
end
end else begin
if (!r_read & BTN[0]) begin
r_addr <= { SW, SW };
end
if (!r_read_d & r_read) begin
r_read_data <= w_data;
end
r_read <= BTN[0];
r_read_d <= r_read;
end // else (r_ram_init)
end
end
RAM_64Kx8 ram(
.SRAM_A (SRAM_A ),
.SRAM_WE_X (SRAM_WE_X ),
.SRAM_OE_X (SRAM_OE_X ),
.SRAM_IO_A (SRAM_IO_A ),
.SRAM_CE_A_X(SRAM_CE_A_X ),
.SRAM_LB_A_X(SRAM_LB_A_X ),
.SRAM_UB_A_X(SRAM_UB_A_X ),
.SRAM_IO_B (SRAM_IO_B ),
.SRAM_CE_B_X(SRAM_CE_B_X ),
.SRAM_LB_B_X(SRAM_LB_B_X ),
.SRAM_UB_B_X(SRAM_UB_B_X ),
.i_addr (r_addr ),
.i_enable_x (r_enable_x ),
.i_write_x (r_write_x ),
.i_data (r_addr[7:0] ),
.o_data (w_data ));
FourDigitSevenSegmentLED led(
.clk (w_clk49khz ),
.rst_x (rst_x ),
.i_data3 (4'h0 ),
.i_data2 (4'h0 ),
.i_data1 (r_read_data[7:4]),
.i_data0 (r_read_data[3:0]),
.i_dp3 (1'b1 ),
.i_dp2 (1'b1 ),
.i_dp1 (1'b1 ),
.i_dp0 (r_ram_init ),
.o_a (LED_A ),
.o_b (LED_B ),
.o_c (LED_C ),
.o_d (LED_D ),
.o_e (LED_E ),
.o_f (LED_F ),
.o_g (LED_G ),
.o_dp (LED_DP ),
.o_select (LED_AN ));
endmodule // RAMSpartan3StarterKit
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 11:30:30
// Design Name:
// Module Name: rca_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rca_dataflow_tb(
);
reg [3:0] a;
reg [3:0] b;
reg cin;
wire cout;
wire [3:0] s;
integer i;
integer j;
rca_dataflow DUT (.a(a), .b(b), .cin(cin), .cout(cout), .s(s));
initial begin
#4000 $finish;
end
initial begin
a = 0; b = 0; cin = 0;
for (i = 0 ; i < 16; i = i + 1) begin
#2 a = i;
for (j = 0; j < 16; j = j + 1) begin
#2 b = j;
#5;
if ({cout, s} == (a + b + cin)) $display("Test Passed");
else $display("Test Failed: %b + %b + %b != %b%b", a, b, cin, cout, s);
end
end
#2 cin = 1;
#2
for (i = 0 ; i < 16; i = i + 1) begin
#2 a = i;
for (j = 0; j < 16; j = j + 1) begin
#2 b = j;
#5;
if ({cout, s} == (a + b + cin)) $display("Test Passed");
else $display("Test Failed: %b + %b + %b != %b%b", a, b, cin, cout, s);
end
end
#20;
end
endmodule
|
module step_id(inst, ena_, cond_dout,
rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_clr_, rdy_im_, rdy_tce_, rdy_ts_, rdy_add_, rdy_sub_);
input[7:0] inst;
input ena_;
input cond_dout;
output rdy_nop_, rdy_cpf_, rdy_cpt_, rdy_ld_, rdy_st_, rdy_clr_, rdy_im_, rdy_tce_, rdy_ts_, rdy_add_, rdy_sub_;
wire cond_ = inst[7] ^ cond_dout;
wire[6:0] inst_cond = inst[6:0] & {7{~(cond_ | ena_)}};
assign rdy_nop_ = inst_cond[6:0] != 7'b0000000 || ena_;
assign rdy_cpf_ = inst_cond[6:4] != 3'b010 || inst_cond[3:0] == 4'b0000;
assign rdy_cpt_ = inst_cond[6:4] != 3'b011 || inst_cond[3:0] == 4'b0000;
assign rdy_ld_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b0};
assign rdy_st_ = {inst_cond[6:2], inst_cond[0]} != {5'b10001, 1'b1};
assign rdy_clr_ = inst_cond != 7'b1010000;
assign rdy_im_ = inst_cond[6:5] != 2'b11;
assign rdy_tce_ = inst_cond != 7'b0001100;
assign rdy_ts_ = {inst_cond[6], inst_cond[3:0]} != {1'b0, 4'b0000} || inst_cond[5:4] == 2'b00;
assign rdy_add_ = inst_cond != 7'b1010110;
assign rdy_sub_ = inst_cond != 7'b1010111;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, q; scanf( %d , &n); bool grid[n + 1][n + 1], ans = false; string s; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) scanf( %d , &grid[i][j]); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { ans ^= (grid[j][i] && grid[i][j]); } } scanf( %d , &q); while (q--) { int t; scanf( %d , &t); if (t == 1 || t == 2) { scanf( %d , &t); ans ^= 1; } else s += (ans + 0 ); } printf( %s , s.c_str()); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:46 06/13/2016
// Design Name:
// Module Name: LZD_8bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LZD_8bit( in, out, valid
);
input [7:0]in;
output reg [2:0]out;
output reg valid;
wire v1,v2;
wire [1:0]l1, l2;
initial
begin
out<=3'b000;
valid<=0;
end
LZD_4bit d3( .in(in[3:0]), .out(l1), .valid(v1));
LZD_4bit d4( .in(in[7:4]), .out(l2), .valid(v2));
always@(in,v1,v2,l1,l2)
begin
if(v2==0&&v1==1)
begin
out<={{~v2},{l1}} ;
end
/*
even this one works same as 4bit LZD
here l1, l2 are 2 bits each and v1,v2 are 1bit
when v2=0
v2 is 0 => l2= 2'b00
in that case we see for v1
if v1=0 => l1= 2'b00
we get out=4'b0000, valid=0
if v1=1 => l1= xx
we take ~v2 in 2^2 position and l1 in 2^1,2^0 position to get no of leading zero terms
eg- 00001000
v2=0,l2=2'b00, v1=1, l1=2'b00
out= {{1},{00}}= {100}=4 there are 4 leading zeros
*/
else if( v2==0&&v1==0)
begin
out<=0;
end
else
begin
out<={{~v2},{l2}};
end
/*eg- 00100000
v2=1,l2=2'b10, v1=0, l1=2'b00
out= {{0},{10}}= {010}=2 there are 2 leading zeros in 00100000
*/
valid<= v1|v2 ; // valid = in[7]|in[6]|in[5]|in[4]|in[3]|in[2]|in[1]|in[0]
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1111111111; const long long MOD = 1e9 + 7; int pref[5001][5001]; int nxt[5001][5001]; int dp(int i, int j) { int x; if (i > 0) { x = pref[i][j] - pref[i - 1][j]; } else { x = pref[0][j]; } x %= MOD; if (x < 0) { x += MOD; } return x; } int digits[5001]; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; string x; cin >> x; for (int i = 1; i <= n; i++) { digits[i] = x.at(i - 1) - 0 ; } for (int i = 0; i < 5001; i++) { for (int j = 0; j < 5001; j++) { if (j == 0) { pref[j][i] = 0; } else if (i == 0) { pref[j][i] = 0; } else { pref[j][i] = 1; } } } for (int i = n; i >= 1; i--) { for (int j = n; j >= i; j--) { if (digits[i] == digits[j]) { if (j == n) { nxt[i][j] = INF; } else { nxt[i][j] = nxt[i + 1][j + 1] + 1; } } else { nxt[i][j] = 0; } } } int a; int next; for (int b = 2; b <= n; b++) { for (int c = b; c <= n; c++) { if (digits[b] == 0) { pref[b][c] = pref[b - 1][c]; } else { a = max(1, 2 * b - c); pref[b][c] = (pref[b - 1][c] % MOD + pref[b - 1][b - 1] % MOD - pref[a - 1][b - 1] % MOD) % MOD; if (2 * b - c - 1 > 0) { a = 2 * b - c - 1; next = nxt[a][b]; if (next < INF) { if (next + a < b && next + b <= c && digits[next + a] < digits[next + b]) { pref[b][c] += dp(a, b - 1); pref[b][c] %= MOD; } } } } } } int ans = 0; for (int i = 1; i <= n; i++) { ans += dp(i, n); ans %= MOD; } if (ans < 0) { ans += MOD; } cout << ans; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:46:04 07/12/2015
// Design Name:
// Module Name: Data_Ram
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Data_Ram(
input [6:0] Offset_in,
input [3:0] Index_in,
input [31:0] CPU_Data_in,
input [4095:0] MEM_Data_in,
input Clock_in,
input [3:0] Write_Data_in,
output [31:0] CPU_Data_out,
output [4095:0] MEM_Data_out,
input Fill_in
);
wire [127:0] Write_Data_Offset;
wire [7:0] Data0 [127:0];
wire [7:0] Data1 [127:0];
wire [7:0] Data2 [127:0];
wire [7:0] Data3 [127:0];
genvar i,j;
generate
for (i=0; i<128; i=i+1) begin : DATA_RAM
Distributed_RAM #(4,8,16) DATA_RAM_0(
.Clock_in (Clock_in),
.Write_Enable_in ((Fill_in) ? 1'b1 : (Write_Data_Offset[i] && Write_Data_in[0])),
.Address_in (Index_in),
.Data_in ((Fill_in) ? MEM_Data_in[(32*i)+:8] : CPU_Data_in[0+:8]),
.Data_out (Data0 [i])
);
Distributed_RAM #(4,8,16) DATA_RAM_1(
.Clock_in (Clock_in),
.Write_Enable_in ((Fill_in) ? 1'b1 : (Write_Data_Offset[i] && Write_Data_in[1])),
.Address_in (Index_in),
.Data_in ((Fill_in) ? MEM_Data_in[((32*i)+8)+:8] : CPU_Data_in[8+:8]),
.Data_out (Data1 [i])
);
Distributed_RAM #(4,8,16) DATA_RAM_2(
.Clock_in (Clock_in),
.Write_Enable_in ((Fill_in) ? 1'b1 : (Write_Data_Offset[i] && Write_Data_in[2])),
.Address_in (Index_in),
.Data_in ((Fill_in) ? MEM_Data_in[((32*i)+16)+:8] : CPU_Data_in[16+:8]),
.Data_out (Data2 [i])
);
Distributed_RAM #(4,8,16) DATA_RAM_3(
.Clock_in (Clock_in),
.Write_Enable_in ((Fill_in) ? 1'b1 : (Write_Data_Offset[i] && Write_Data_in[3])),
.Address_in (Index_in),
.Data_in ((Fill_in) ? MEM_Data_in[((32*i)+24)+:8] : CPU_Data_in[24+:8]),
.Data_out (Data3 [i])
);
assign MEM_Data_out[(32*i)+:32] = {Data3[i], Data2[i], Data1[i], Data0[i]};
end
endgenerate
assign Write_Data_Offset = (1 << Offset_in);
assign CPU_Data_out = {Data3[Offset_in],Data2[Offset_in],Data1[Offset_in],Data0[Offset_in]};
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long linf = 1e18 + 5; const int mod = (int)1e9 + 7; const int logN = 17; const int inf = 1e9; const int N = 1e6 + 5; int way[N][2], size[N], all[N][30][2], n, m, a[N], S = 1; void insert(int x) { int node = 1; for (int i = 29; i >= 0; i--) { int t = (x >> i) & 1; if (!way[node][t]) way[node][t] = ++S; node = way[node][t]; size[node]++; for (int j = 0; j <= 29; j++) all[node][j][((x & (1 << j)) != 0)]++; } } int hm(int x, int big) { int node = 1; int ans = 0; for (int i = 29; i >= 0; i--) { if (!node) break; int t = 0; if ((x & (1 << i)) ^ (big & (1 << i))) t = 1; if (big & (1 << i)) ; else ans += size[way[node][!t]]; node = way[node][t]; } ans += size[node]; return ans; } int molla(int node, int x) { long long ans = 0; for (int i = 0; i <= 29; i++) { ans += (long long)all[node][i][!(x & (1 << i))] * (1 << i) % mod; ans %= mod; } return ans; } long long sum(int x, int big) { int node = 1; long long ans = 0; for (int i = 29; i >= 0; i--) { if (!node) break; int t = 0; if ((x & (1 << i)) ^ (big & (1 << i))) t = 1; if (big & (1 << i)) ; else { ans += molla(way[node][!t], x); ans %= mod; } node = way[node][t]; } ans += (long long)size[node] * big % mod; ans %= mod; return ans; } int get(int x) { long long cur = 0; for (int i = 1; i <= n; i++) cur += hm(a[i], x); return cur / 2; } long long sum(int x) { long long cur = 0; for (int i = 1; i <= n; i++) cur = (cur + sum(a[i], x)) % mod; if (cur & 1) cur += mod; return cur / 2LL; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); insert(a[i]); } int bas = 0, son = (1 << 30) - 1; if (!m) { cout << 0 << n ; return 0; } while (bas < son) { int orta = bas + son >> 1; if (bas == orta) orta++; if (get(orta) >= m) bas = orta; else son = orta - 1; } long long ans = (sum(bas + 1) + (m - get(bas + 1)) * (long long)bas % mod) % mod; cout << ans << n ; return 0; }
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=25 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgd6m
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [24:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [24:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [24:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 25,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "MAXIMIZE_SPEED=5,LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgd6m
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; ; const int inf = 1e9 + 5; const int mod = 1e9 + 7; const int logN = 17; int x, y, n, m, a[N], b[N], w[N], p[N], score[N]; vector<int> v[N]; long long ans[N], upsum[N], downsum[N]; bool cmp(int x, int y) { return score[x] < score[y]; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d %d , &a[i], &b[i]); score[i] = a[i] - b[i]; p[i] = i; } sort(p + 1, p + n + 1, cmp); for (int i = 1; i <= n; i++) { w[p[i]] = i; } for (int i = 1; i <= m; i++) { scanf( %d %d , &x, &y); v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; i++) upsum[i] = upsum[i - 1] + a[p[i]]; for (int i = n; i >= 1; i--) downsum[i] = downsum[i + 1] + b[p[i]]; for (int i = 1; i <= n; i++) { int up = i - 1; int down = n - i; long long ups = upsum[i - 1]; long long dws = downsum[i + 1]; int cur = p[i]; for (auto go : v[cur]) { if (w[go] > i) { down--; dws -= b[go]; } else { up--; ups -= a[go]; } } ans[cur] = ups + dws + up * (long long)b[cur] + down * (long long)a[cur]; } for (int i = 1; i <= n; i++) printf( %lld , ans[i]); cout << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1500010; int n, cnt, ans; int a[N], bug[N], v[N]; map<pair<int, int>, int> vis; bool check(int i) { if (!(i & 1)) { if (i < n) return a[i - 1] < a[i] && a[i + 1] < a[i]; else return a[i - 1] < a[i]; } else if (i > 1 && i < n) return a[i - 1] > a[i] && a[i + 1] > a[i]; else if (i == 1) return a[i + 1] > a[i]; else return a[i - 1] > a[i]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i += 2) { if (i == 1 && a[i] >= a[i + 1]) { if (!v[i]) bug[++cnt] = i, v[i] = 1; if (!v[i + 1]) bug[++cnt] = i + 1, v[i + 1] = 1; } else if (i == n && a[i] >= a[i - 1]) { if (!v[i]) bug[++cnt] = i, v[i] = 1; if (!v[i - 1]) bug[++cnt] = i - 1, v[i - 1] = 1; } else if (i > 1 && i < n) { if (a[i] >= a[i + 1] && a[i] >= a[i - 1]) { if (!v[i]) bug[++cnt] = i, v[i] = 1; if (!v[i + 1]) bug[++cnt] = i + 1, v[i + 1] = 1; if (!v[i - 1]) bug[++cnt] = i - 1, v[i - 1] = 1; } else { if (a[i] >= a[i + 1]) { if (!v[i]) bug[++cnt] = i, v[i] = 1; if (!v[i + 1]) bug[++cnt] = i + 1, v[i + 1] = 1; } if (a[i] >= a[i - 1]) { if (!v[i]) bug[++cnt] = i, v[i] = 1; if (!v[i - 1]) bug[++cnt] = i - 1, v[i - 1] = 1; } } } } if (cnt > 6) { puts( 0 ); return 0; } for (int i = 1; i <= cnt; i++) for (int j = 1; j <= n; j++) { if (a[j] == a[bug[i]]) continue; swap(a[j], a[bug[i]]); bool fl = 1; for (int k = 1; k <= cnt; k++) if (!check(bug[k])) fl = 0; if (!check(j)) fl = 0; if (fl) { pair<int, int> p = make_pair(min(bug[i], j), max(bug[i], j)); if (!vis[p]) { ans++; vis[p] = 1; } } swap(a[j], a[bug[i]]); } printf( %d n , ans); return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000000 + 7; const long long int N = 10000000 + 6; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int a, b; cin >> a >> b; vector<pair<int, int> > bb, aa; for (int i = 1; i < 1000; i++) { for (int j = 1; j < 1000; j++) { if (i * i + j * j == a * a) aa.push_back(make_pair(i, j)); if (i * i + j * j == b * b) bb.push_back(make_pair(i, j)); } } bool flag = false; for (int i = 0; i < aa.size(); i++) { for (int j = 0; j < bb.size(); j++) { int p = aa[i].first; int q = aa[i].second; int r = bb[j].first; int s = bb[j].second; if (p * s == q * r) { if (p != s) { cout << YES n << 0 0 n << p << << q << n << s << << -r; flag = true; break; } } } if (flag == true) break; } if (flag == false) cout << NO n << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; string str; int make(int star, int en) { if (en - star >= 7) return -1e7; if (en - star >= 1 && str[star] == 0 ) return -1e7; if (str[star] == 0 && str[en] != 0 ) return -1e7; int sum = 0; for (int i = star; i <= en; i++) { sum = sum * 10 + (str[i] - 0 ); } if (sum > 1e6) return -1e7; return sum; } int main() { int m = -1, i, j, len, a, b, c; cin >> str; len = str.length(); for (i = 0; i < len - 2; i++) { for (j = i + 1; j < len - 1; j++) { a = make(0, i); b = make(i + 1, j); c = make(j + 1, len - 1); m = max(m, a + b + c); } } if (m < 0) printf( -1 ); else printf( %d , m); return 0; }
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//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.2.1 (lin64) Build Wed Aug 5 13:06:02 MDT 2015
//Date : Wed Aug 17 16:30:57 2016
//Host : HomeMegaUbuntu running 64-bit Ubuntu 16.04.1 LTS
//Command : generate_target elink2_top_wrapper.bd
//Design : elink2_top_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module elink2_top_wrapper
(CCLK_N,
CCLK_P,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
DSP_RESET_N,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_N,
GPIO_P,
HDMI_CLK,
HDMI_D,
HDMI_DE,
HDMI_HSYNC,
HDMI_INT,
HDMI_SPDIF,
HDMI_VSYNC,
I2C_SCL,
I2C_SDA,
RX_data_n,
RX_data_p,
RX_frame_n,
RX_frame_p,
RX_lclk_n,
RX_lclk_p,
RX_rd_wait_n,
RX_rd_wait_p,
RX_wr_wait_n,
RX_wr_wait_p,
TX_data_n,
TX_data_p,
TX_frame_n,
TX_frame_p,
TX_lclk_n,
TX_lclk_p,
TX_wr_wait_n,
TX_wr_wait_p,
TXi_rd_wait_n,
TXi_rd_wait_p);
output CCLK_N;
output CCLK_P;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output [0:0]DSP_RESET_N;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [11:0]GPIO_N;
inout [11:0]GPIO_P;
output HDMI_CLK;
output [15:0]HDMI_D;
output HDMI_DE;
output HDMI_HSYNC;
input [0:0]HDMI_INT;
output HDMI_SPDIF;
output HDMI_VSYNC;
inout I2C_SCL;
inout I2C_SDA;
input [7:0]RX_data_n;
input [7:0]RX_data_p;
input RX_frame_n;
input RX_frame_p;
input RX_lclk_n;
input RX_lclk_p;
output RX_rd_wait_n;
output RX_rd_wait_p;
output RX_wr_wait_n;
output RX_wr_wait_p;
output [7:0]TX_data_n;
output [7:0]TX_data_p;
output TX_frame_n;
output TX_frame_p;
output TX_lclk_n;
output TX_lclk_p;
input TX_wr_wait_n;
input TX_wr_wait_p;
input TXi_rd_wait_n;
input TXi_rd_wait_p;
wire CCLK_N;
wire CCLK_P;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire [0:0]DSP_RESET_N;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [11:0]GPIO_N;
wire [11:0]GPIO_P;
wire HDMI_CLK;
wire [15:0]HDMI_D;
wire HDMI_DE;
wire HDMI_HSYNC;
wire [0:0]HDMI_INT;
wire HDMI_SPDIF;
wire HDMI_VSYNC;
wire I2C_SCL;
wire I2C_SDA;
wire [7:0]RX_data_n;
wire [7:0]RX_data_p;
wire RX_frame_n;
wire RX_frame_p;
wire RX_lclk_n;
wire RX_lclk_p;
wire RX_rd_wait_n;
wire RX_rd_wait_p;
wire RX_wr_wait_n;
wire RX_wr_wait_p;
wire [7:0]TX_data_n;
wire [7:0]TX_data_p;
wire TX_frame_n;
wire TX_frame_p;
wire TX_lclk_n;
wire TX_lclk_p;
wire TX_wr_wait_n;
wire TX_wr_wait_p;
wire TXi_rd_wait_n;
wire TXi_rd_wait_p;
elink2_top elink2_top_i
(.CCLK_N(CCLK_N),
.CCLK_P(CCLK_P),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.DSP_RESET_N(DSP_RESET_N),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GPIO_N(GPIO_N),
.GPIO_P(GPIO_P),
.HDMI_CLK(HDMI_CLK),
.HDMI_D(HDMI_D),
.HDMI_DE(HDMI_DE),
.HDMI_HSYNC(HDMI_HSYNC),
.HDMI_INT(HDMI_INT),
.HDMI_SPDIF(HDMI_SPDIF),
.HDMI_VSYNC(HDMI_VSYNC),
.I2C_SCL(I2C_SCL),
.I2C_SDA(I2C_SDA),
.RX_data_n(RX_data_n),
.RX_data_p(RX_data_p),
.RX_frame_n(RX_frame_n),
.RX_frame_p(RX_frame_p),
.RX_lclk_n(RX_lclk_n),
.RX_lclk_p(RX_lclk_p),
.RX_rd_wait_n(RX_rd_wait_n),
.RX_rd_wait_p(RX_rd_wait_p),
.RX_wr_wait_n(RX_wr_wait_n),
.RX_wr_wait_p(RX_wr_wait_p),
.TX_data_n(TX_data_n),
.TX_data_p(TX_data_p),
.TX_frame_n(TX_frame_n),
.TX_frame_p(TX_frame_p),
.TX_lclk_n(TX_lclk_n),
.TX_lclk_p(TX_lclk_p),
.TX_wr_wait_n(TX_wr_wait_n),
.TX_wr_wait_p(TX_wr_wait_p),
.TXi_rd_wait_n(TXi_rd_wait_n),
.TXi_rd_wait_p(TXi_rd_wait_p));
endmodule
|
module memif(
input wire clk,
input wire reset,
// Avalon Slave
input wire [1:0] s_address,
input wire s_write,
input wire s_read,
input wire [31:0] s_writedata,
output reg [31:0] s_readdata,
output wire s_waitrequest,
// 36 bit Avalon Master
output wire [17:0] m_address,
output reg m_write,
output reg m_read,
output wire [35:0] m_writedata,
input wire [35:0] m_readdata,
input wire m_waitrequest
);
reg [17:0] addr;
reg [35:0] word;
assign m_address = addr;
assign m_writedata = word;
wire write_edge, read_edge;
edgedet e0(clk, reset, s_write, write_edge);
edgedet e1(clk, reset, s_read, read_edge);
reg waiting;
wire req = (write_edge|read_edge) & s_address == 2'h2;
assign s_waitrequest = req | waiting;
always @(posedge clk or negedge reset) begin
if(~reset) begin
m_write <= 0;
m_read <= 0;
waiting <= 0;
addr <= 0;
word <= 0;
end else begin
if(write_edge) begin
case(s_address)
2'h0: addr <= s_writedata[17:0];
2'h1: word[17:0] <= s_writedata[17:0];
2'h2: word[35:18] <= s_writedata[17:0];
endcase
end
if(req) begin
waiting <= 1;
if(s_write)
m_write <= 1;
else if(s_read)
m_read <= 1;
end
if(m_write & ~m_waitrequest) begin
m_write <= 0;
waiting <= 0;
end
if(m_read & ~m_waitrequest) begin
m_read <= 0;
waiting <= 0;
word <= m_readdata;
end
end
end
always @(*) begin
case(s_address)
2'h1: s_readdata <= { 14'b0, word[17:0] };
2'h2: s_readdata <= { 14'b0, word[35:18] };
default: s_readdata <= 32'b0;
endcase
end
endmodule
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#include <bits/stdc++.h> using namespace std; int main() { long n, sum = 1e6; cin >> n; long a[n]; for (long i = 0; i < n; cin >> a[i++]) ; long opt; for (long i = 1; i <= 1000; ++i) { long s = 0; for (long j = 0; j < n; ++j) { if (i != a[j]) s += abs(i - a[j]) - 1; } if (s < sum) { sum = s; opt = i; } } cout << opt << << sum << endl; }
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#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long n, k, dp[N], sum, pos, s1, s2, deep[N], mndp[N], ans, ss, ss1; vector<pair<long long, long long> > g[N]; void dfs(long long x, long long p) { dp[x] = 0; for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y == p) continue; dfs(y, x); dp[x] = max(dp[x], dp[y] + g[x][i].second); } } void get_ans(long long x, long long p, long long s) { if (max(dp[x], s) <= sum) { sum = max(dp[x], s); pos = x; } vector<long long> a(g[x].size(), 0), b(g[x].size(), 0); for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y != p) a[i] = b[i] = dp[y] + g[x][i].second; else a[i] = b[i] = 0; if (i > 0) a[i] = max(a[i], a[i - 1]); } for (long long i = (long long)b.size() - 2; i >= 0; --i) { b[i] = max(b[i], b[i + 1]); } for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y == p) continue; long long mx = 0; if (i > 0) mx = max(mx, a[i - 1]); if (i + 1 < b.size()) mx = max(mx, b[i + 1]); get_ans(y, x, max(s, mx) + g[x][i].second); } } void dfs1(long long x, long long p, long long s) { deep[x] = deep[p] + 1; mndp[deep[x]] = min(mndp[deep[x]], max(s, dp[x])); ans = min(ans, max(mndp[deep[x]], ss1)); vector<long long> a(g[x].size(), 0), b(g[x].size(), 0); for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y != p) a[i] = b[i] = dp[y] + g[x][i].second; else a[i] = b[i] = 0; if (i > 0) a[i] = max(a[i], a[i - 1]); } for (long long i = (long long)b.size() - 2; i >= 0; --i) { b[i] = max(b[i], b[i + 1]); } for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y == p) continue; long long mx = 0; if (i > 0) mx = max(mx, a[i - 1]); if (i + 1 < b.size()) mx = max(mx, b[i + 1]); dfs1(y, x, max(mx, s)); } } void dfs2(long long x, long long p, long long s) { deep[x] = deep[p] + 1; ans = min(ans, max(max(s, dp[x]), ss1)); if (k - deep[x] - 1 > 0) { ans = min(ans, max(mndp[k - deep[x] - 1], max(s, dp[x]))); } vector<long long> a(g[x].size(), 0), b(g[x].size(), 0); for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y != p) a[i] = b[i] = dp[y] + g[x][i].second; else a[i] = b[i] = 0; if (i > 0) a[i] = max(a[i], a[i - 1]); } for (long long i = (long long)b.size() - 2; i >= 0; --i) { b[i] = max(b[i], b[i + 1]); } for (long long i = 0; i < g[x].size(); ++i) { long long y = g[x][i].first; if (y == p) continue; long long mx = 0; if (i > 0) mx = max(mx, a[i - 1]); if (i + 1 < b.size()) mx = max(mx, b[i + 1]); dfs2(y, x, max(mx, s)); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (long long i = 0; i <= n; ++i) { mndp[i] = 1e18; } if (n == 1) return cout << 0, 0; if (n == 2) { long long x, y, z; cin >> x >> y >> z; if (k == 2) z = 0; cout << z; return 0; } for (long long i = 1; i < n; ++i) { long long x, y, z; cin >> x >> y >> z; g[x].push_back(make_pair(y, z)); g[y].push_back(make_pair(x, z)); } dfs(1, 0); sum = 1e18; pos = 0; get_ans(1, 0, 0); if (k == 1) return cout << sum, 0; dfs(pos, 0); vector<pair<long long, long long> > a(g[pos].size()); for (long long i = 0; i < g[pos].size(); ++i) { a[i] = make_pair(dp[g[pos][i].first] + g[pos][i].second, g[pos][i].first); } sort(a.begin(), a.end()); reverse(a.begin(), a.end()); long long s = 0; if (a.size() > 2) ss = a[2].first; else ss = 0; s1 = a[0].second; s2 = a[1].second; mndp[0] = a[0].first; deep[pos] = 0; ans = sum; ss1 = a[1].first; dfs1(s1, pos, ss); for (int i = 1; i <= n; ++i) { mndp[i] = min(mndp[i], mndp[i - 1]); } ss1 = a[0].first; dfs2(s2, pos, ss); cout << ans; }
|
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dport_axi
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input axi_awready_i
,input axi_wready_i
,input axi_bvalid_i
,input [ 1:0] axi_bresp_i
,input axi_arready_i
,input axi_rvalid_i
,input [ 31:0] axi_rdata_i
,input [ 1:0] axi_rresp_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output axi_awvalid_o
,output [ 31:0] axi_awaddr_o
,output axi_wvalid_o
,output [ 31:0] axi_wdata_o
,output [ 3:0] axi_wstrb_o
,output axi_bready_o
,output axi_arvalid_o
,output [ 31:0] axi_araddr_o
,output axi_rready_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire write_complete_w;
wire read_complete_w;
reg request_pending_q;
wire req_pop_w = read_complete_w | write_complete_w;
wire req_valid_w;
wire [69-1:0] req_w;
// Push on transaction and other FIFO not full
wire req_push_w = (mem_rd_i || mem_wr_i != 4'b0) && res_accept_w;
dport_axi_fifo
#(
.WIDTH(32+32+4+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = (mem_rd_i || mem_wr_i != 4'b0) && req_accept_w;
dport_axi_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
assign mem_ack_o = axi_bvalid_i || axi_rvalid_i;
assign mem_error_o = axi_bvalid_i ? (axi_bresp_i != 2'b0) : (axi_rresp_i != 2'b0);
wire request_in_progress_w = request_pending_q & !mem_ack_o;
//-------------------------------------------------------------
// Write Request
//-------------------------------------------------------------
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
reg awvalid_inhibit_q;
reg wvalid_inhibit_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
awvalid_inhibit_q <= 1'b0;
else if (axi_awvalid_o && axi_awready_i && axi_wvalid_o && !axi_wready_i)
awvalid_inhibit_q <= 1'b1;
else if (axi_wvalid_o && axi_wready_i)
awvalid_inhibit_q <= 1'b0;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
wvalid_inhibit_q <= 1'b0;
else if (axi_wvalid_o && axi_wready_i && axi_awvalid_o && !axi_awready_i)
wvalid_inhibit_q <= 1'b1;
else if (axi_awvalid_o && axi_awready_i)
wvalid_inhibit_q <= 1'b0;
assign axi_awvalid_o = req_is_write_w && !awvalid_inhibit_q;
assign axi_awaddr_o = {req_w[31:2], 2'b0};
assign axi_wvalid_o = req_is_write_w && !wvalid_inhibit_q;
assign axi_wdata_o = req_w[63:32];
assign axi_wstrb_o = req_w[67:64];
assign axi_bready_o = 1'b1;
assign write_complete_w = (awvalid_inhibit_q || axi_awready_i) &&
(wvalid_inhibit_q || axi_wready_i) && req_is_write_w;
//-------------------------------------------------------------
// Read Request
//-------------------------------------------------------------
assign axi_arvalid_o = req_is_read_w;
assign axi_araddr_o = {req_w[31:2], 2'b0};
assign axi_rready_o = 1'b1;
assign mem_data_rd_o = axi_rdata_i;
assign read_complete_w = axi_arvalid_o && axi_arready_i;
//-------------------------------------------------------------
// Outstanding Request Tracking
//-------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (write_complete_w || read_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
endmodule
//-----------------------------------------------------------------
// dport_axi_fifo: FIFO
//-----------------------------------------------------------------
module dport_axi_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 2,
parameter ADDR_W = 1
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
module top;
reg pass;
wire [2:-1] vec;
assign vec = 4'bxxxx;
initial begin
pass = 1'b1;
force vec[1'bx] = 1'b1;
if (vec !== 4'bxxx) begin
$display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx];
force vec[1'bx:0] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx:0];
force vec[0:1'bx] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[0:1'bx];
force vec[1'bx:1'bx] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx:1'bx];
force vec[1'bx+:1] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx+:1];
force vec[1'bx+:2] = 2'b01;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx+:2];
force vec[1'bx-:1] = 1'b1;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx-:1];
force vec[1'bx-:2] = 2'b01;
if (vec !== 4'bxxxx) begin
$display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
pass = 1'b0;
end
release vec[1'bx-:2];
if (pass) $display("PASSED");
end
endmodule
|
// bsg_fifo_tracker
//
// MBT 7/7/16
//
`include "bsg_defines.v"
module bsg_fifo_tracker #(parameter `BSG_INV_PARAM(els_p )
, ptr_width_lp = `BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input reset_i
, input enq_i
, input deq_i
, output [ptr_width_lp-1:0] wptr_r_o
, output [ptr_width_lp-1:0] rptr_r_o
, output [ptr_width_lp-1:0] rptr_n_o
, output full_o
, output empty_o
);
// one read pointer, one write pointer;
logic [ptr_width_lp-1:0] rptr_r, rptr_n, wptr_r;
assign wptr_r_o = wptr_r;
assign rptr_r_o = rptr_r;
assign rptr_n_o = rptr_n;
// Used to latch last operation, to determine fifo full or empty
logic enq_r, deq_r;
// internal signals
logic empty, full, equal_ptrs;
bsg_circular_ptr #(.slots_p (els_p)
,.max_add_p(1 )
) rptr
( .clk (clk_i )
, .reset_i(reset_i)
, .add_i (deq_i )
, .o (rptr_r )
, .n_o (rptr_n)
);
bsg_circular_ptr #(.slots_p (els_p)
,.max_add_p(1 )
) wptr
( .clk (clk_i )
, .reset_i(reset_i)
, .add_i (enq_i )
, .o (wptr_r )
, .n_o ()
);
// registering last operation
// for reset, last op is deque, so
// equal w and r pointers signal empty FIFO
always_ff @(posedge clk_i)
if (reset_i)
begin
enq_r <= 1'b0;
deq_r <= 1'b1;
end
else
begin
// update "last operation" when
// either enque or dequing
if (enq_i | deq_i)
begin
enq_r <= enq_i;
deq_r <= deq_i;
end
end // else: !if(reset_i)
// if read and write pointers are equal
// empty or fullness is determined by whether
// the last request was a deque or enque.
// no need to check both enque and deque for each of the
// empty and full signals, since during full or empty state one
// of the enque or deque cannot be asserted (no enque when it is
// not ready and no yumi when no data is valid to be sent out)
// Moreover, other than full or empty state only one of deque or
// enque signals would not make the counters equal
assign equal_ptrs = (rptr_r == wptr_r);
assign empty = equal_ptrs & deq_r;
assign full = equal_ptrs & enq_r;
assign full_o = full;
assign empty_o = empty;
endmodule // bsg_fifo_tracker
`BSG_ABSTRACT_MODULE(bsg_fifo_tracker)
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 123; const int MINN = 1e3 + 123; const int mod = 1e9 + 7; const int INF = 1e9 + 1; pair<int, int> a[MINN]; bool cmp(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return 1; if (a.first == b.first) if (a.second > b.second) return 1; return 0; } int main() { int n, sum; cin >> sum >> n; for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].first, &a[i].second); sort(a + 1, a + n + 1, &cmp); for (int i = 1; i <= n; i++) { if (sum <= a[i].first) { cout << NO ; return 0; } sum += a[i].second; } cout << YES ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Anton Potocnik
//
// Create Date: 07.01.2017 22:50:51
// Design Name:
// Module Name: frequency_counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Reciprotial method
//
// Dependencies:
//
// Revision:
// Revision 0.1 - Reciprotial method implemented
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_counter #
(
parameter ADC_WIDTH = 14,
parameter AXIS_TDATA_WIDTH = 32,
parameter COUNT_WIDTH = 32,
parameter HIGH_THRESHOLD = -100,
parameter LOW_THRESHOLD = -150
)
(
(* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_IN_tdata,
input S_AXIS_IN_tvalid,
input clk,
input rst,
input [COUNT_WIDTH-1:0] Ncycles,
output [AXIS_TDATA_WIDTH-1:0] M_AXIS_OUT_tdata,
output M_AXIS_OUT_tvalid,
output [COUNT_WIDTH-1:0] counter_output
);
wire signed [ADC_WIDTH-1:0] data;
reg state, state_next;
reg [COUNT_WIDTH-1:0] counter=0, counter_next=0;
reg [COUNT_WIDTH-1:0] counter_output=0, counter_output_next=0;
reg [COUNT_WIDTH-1:0] cycle=0, cycle_next=0;
// Wire AXIS IN to AXIS OUT
assign M_AXIS_OUT_tdata[ADC_WIDTH-1:0] = S_AXIS_IN_tdata[ADC_WIDTH-1:0];
assign M_AXIS_OUT_tvalid = S_AXIS_IN_tvalid;
// Extract only the 14-bits of ADC data
assign data = S_AXIS_IN_tdata[ADC_WIDTH-1:0];
// Handling of the state buffer for finding signal transition at the threshold
always @(posedge clk)
begin
if (~rst)
state <= 1'b0;
else
state <= state_next;
end
always @* // logic for state buffer
begin
if (data > HIGH_THRESHOLD)
state_next = 1;
else if (data < LOW_THRESHOLD)
state_next = 0;
else
state_next = state;
end
// Handling of counter, counter_output and cycle buffer
always @(posedge clk)
begin
if (~rst)
begin
counter <= 0;
counter_output <= 0;
cycle <= 0;
end
else
begin
counter <= counter_next;
counter_output <= counter_output_next;
cycle <= cycle_next;
end
end
always @* // logic for counter, counter_output, and cycle buffer
begin
counter_next = counter + 1; // increment on each clock cycle
counter_output_next = counter_output;
cycle_next = cycle;
if (state < state_next) // high to low signal transition
begin
cycle_next = cycle + 1; // increment on each signal transition
if (cycle >= Ncycles-1)
begin
counter_next = 0;
counter_output_next = counter;
cycle_next = 0;
end
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "functions.vh"
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:16:18 05/22/2016
// Design Name:
// Module Name: MUX_DECO_FF
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////
module MUX_DECO_FF(
input rst,
input clk,
input listo,
input listo_lee,
input listo_escribe,
input [7:0]seleccion,
input [7:0]tecla,
input [7:0]tecla2,
input [7:0] tecla3,
input [7:0]RG1,
input [7:0]RG2,
input [7:0]RG3,
output [7:0]salida_picoblaze
);
wire [7:0]salida_mux_deco;
MUX_DECO MUX_DECO (
.seleccion(seleccion),
.listo(listo),
.listo_lee(listo_lee),
.listo_escribe(listo_escribe),
.salida_mux_deco(salida_mux_deco),
.tecla(tecla),
.tecla2(tecla2),
.tecla3(tecla3),
.RG1(RG1),
.RG2(RG2),
.RG3(RG3)
);
FFD FFD (
.rst(rst),
.clk(clk),
.dato_mux(salida_mux_deco),
.salida_picoblaze(salida_picoblaze)
);
endmodule
|
module mux16 #( parameter W = 1 ) (
sel,
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000,
o
);
input [3:0] sel;
input [W-1:0]
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000;
output [W-1:0] o;
reg [W-1:0] o;
always @ (
sel,
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000
) begin
case (sel)
0: o = i0000;
1: o = i0001;
2: o = i0010;
3: o = i0011;
4: o = i0100;
5: o = i0101;
6: o = i0110;
7: o = i0111;
8: o = i1000;
9: o = i1001;
10: o = i1010;
11: o = i1011;
12: o = i1100;
13: o = i1101;
14: o = i1110;
default o = i1111;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int Z = 3 * (int)1e3 + 111; const int N = 3 * (int)1e5 + 111; const int INF = (int)1e9 + 111; const int MOD = (int)1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; double l, d, v, g, r; cin >> l >> d >> v >> g >> r; double t(0); t = d / v; if (int(t + 1) % int(g + r) <= g) { if (int(t) % int(g + r) >= g) t = int(t) + 1; } else { t += (g + r) - int(t); } t += (l - d) / v; cout << setprecision(20) << t; }
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_impctl_pullup.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_impctl_pullup(rclk ,so ,z ,deltabit ,hard_reset_n ,
clk_dis_l ,from_csr ,we_csr ,si ,se ,ctu_io_sscan_se ,vdd18 ,
ctu_io_sscan_in ,ctu_io_sscan_out ,ctu_io_sscan_update ,pad ,to_csr
,ctu_global_snap ,tclk );
output [7:0] z ;
output [7:0] to_csr ;
input [7:0] from_csr ;
output so ;
output deltabit ;
output ctu_io_sscan_out ;
input rclk ;
input hard_reset_n ;
input clk_dis_l ;
input we_csr ;
input si ;
input se ;
input ctu_io_sscan_se ;
input vdd18 ;
input ctu_io_sscan_in ;
input ctu_io_sscan_update ;
input ctu_global_snap ;
input tclk ;
inout pad ;
supply1 vdd ;
wire [7:0] z_post ;
wire [7:0] d ;
wire [7:0] net67 ;
wire clk ;
wire net086 ;
wire net091 ;
wire net092 ;
wire above ;
wire global_reset_n ;
wire sodr_l ;
wire sos_l ;
wire bypass ;
wire oe_out ;
wire net055 ;
wire updclk ;
wire clk_en_l ;
wire sclk ;
wire avgcntr_rst ;
bw_u1_inv_4x I28_1_ (
.z (net67[6] ),
.a (z_post[6] ) );
bw_u1_inv_10x I29_7_ (
.z (z[7] ),
.a (net67[0] ) );
bw_u1_inv_10x I29_0_ (
.z (z[0] ),
.a (net67[7] ) );
bw_u1_inv_4x I28_2_ (
.z (net67[5] ),
.a (z_post[5] ) );
bw_io_impctl_ddr_uprcn I241 (
.cbu ({d[0] ,d[1] ,d[2] ,d[3] ,d[4] ,d[5] ,d[6] ,d[7] }
),
.oe (oe_out ),
.vdd18 (vdd18 ),
.si_l (net091 ),
.so_l (sodr_l ),
.pad (pad ),
.sclk (sclk ),
.above (above ),
.clk (clk ),
.se (se ),
.global_reset_n (global_reset_n ) );
bw_u1_inv_10x I29_1_ (
.z (z[1] ),
.a (net67[6] ) );
bw_u1_inv_4x I28_3_ (
.z (net67[4] ),
.a (z_post[4] ) );
bw_u1_inv_10x I29_2_ (
.z (z[2] ),
.a (net67[5] ) );
bw_u1_inv_4x I28_4_ (
.z (net67[3] ),
.a (z_post[3] ) );
bw_u1_inv_10x I29_3_ (
.z (z[3] ),
.a (net67[4] ) );
bw_u1_inv_4x I28_5_ (
.z (net67[2] ),
.a (z_post[2] ) );
bw_io_impctl_smachine_new I23 (
.z_post ({z_post } ),
.from_csr ({from_csr } ),
.to_csr ({to_csr } ),
.d ({d } ),
.deltabit (deltabit ),
.ctu_io_sscan_se (ctu_io_sscan_se ),
.updclk (updclk ),
.we_csr (we_csr ),
.l2clk (rclk ),
.ctu_io_sscan_in (ctu_io_sscan_in ),
.above (above ),
.bypass (bypass ),
.config_pmos (vdd ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.ctu_global_snap (ctu_global_snap ),
.sclk (sclk ),
.avgcntr_rst (avgcntr_rst ),
.so (net055 ),
.se (se ),
.si_l (sodr_l ),
.io_ctu_sscan_out (ctu_io_sscan_out ),
.tclk (tclk ),
.ctu_io_sscan_update (ctu_io_sscan_update ),
.clk_en_l (clk_en_l ) );
bw_io_impctl_clkgen I24 (
.se (se ),
.oe_out (oe_out ),
.updclk (updclk ),
.so_l (net086 ),
.si_l (sos_l ),
.clk (clk ), ///changed from rclk
.synced_upd_imped (ctu_io_sscan_update ),
.bypass (bypass ),
.global_reset_n (global_reset_n ),
.hard_reset_n (hard_reset_n ),
.sclk (sclk ),
.reset_l (vdd ),
.avgcntr_rst (avgcntr_rst ) );
bw_u1_inv_10x I29_4_ (
.z (z[4] ),
.a (net67[3] ) );
bw_u1_inv_4x I28_6_ (
.z (net67[1] ),
.a (z_post[1] ) );
bw_u1_ckenbuf_6x I30 (
.clk (clk ),
.rclk (rclk ),
.en_l (clk_en_l ),
.tm_l (net092 ) );
bw_u1_inv_4x I33 (
.z (so ),
.a (net086 ) );
bw_u1_inv_4x I34 (
.z (net091 ),
.a (si ) );
bw_u1_inv_4x I36 (
.z (sos_l ),
.a (net055 ) );
bw_u1_inv_10x I29_5_ (
.z (z[5] ),
.a (net67[2] ) );
bw_u1_inv_4x I28_7_ (
.z (net67[0] ),
.a (z_post[0] ) );
bw_u1_inv_10x I46 (
.z (clk_en_l ),
.a (clk_dis_l ) );
bw_u1_inv_4x I48 (
.z (net092 ),
.a (se ) );
bw_u1_inv_4x I28_0_ (
.z (net67[7] ),
.a (z_post[7] ) );
bw_u1_inv_10x I29_6_ (
.z (z[6] ),
.a (net67[1] ) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_PP_V
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// mem512b is 512 bytes synchronous memory, which maps directly to the EAB memory block of ACEX1K.
// rdaddr is read address, dataout is the data read. Data is read with 1-clock latency, i.e. it
// appears after the positive clock edge, which locked rdaddr.
// wraddr is write address, datain is data to be written. we enables write to memory: when it
// locks as being 1 at positive clock edge, data contained at datain is written to wraddr location.
//
// clk __/``\__/``\__/``\__/``\__/``
// rdaddr |addr1|addr2|
// dataout |data1|data2|
// wraddr |addr3|addr4|
// datain |data3|data4|
// we _________/```````````\_______
//
// data1 is the data read from addr1, data2 is read from addr2
// data3 is written to addr3, data4 is written to addr4
//
// simultaneous write and read to the same memory address lead to undefined read data.
module mem512b(
rdaddr, // read address
wraddr, // write address
datain, // write data
dataout, // read data
we, // write enable
clk
);
input [8:0] rdaddr;
input [8:0] wraddr;
input [7:0] datain;
output reg [7:0] dataout;
input we;
input clk;
reg [7:0] mem[0:511]; // memory block
always @(posedge clk)
begin
dataout <= mem[rdaddr]; // reading data
if( we ) // writing data
begin
mem[wraddr] <= datain;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O2111A_BEHAVIORAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_BEHAVIORAL_V
|
#include <bits/stdc++.h> using namespace std; int n, m, k, a[1003][1003], row[1003], col[1003]; int main() { scanf( %d%d%d , &n, &m, &k); int i, j; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) scanf( %d , &a[i][j]); for (i = 0; i <= n; i++) row[i] = i; for (i = 0; i <= m; i++) col[i] = i; char s; int x, y; for (i = 0; i < k; i++) { scanf( n%c %d %d , &s, &x, &y); if (s == g ) printf( %d n , a[row[x]][col[y]]); if (s == c ) { j = col[x]; col[x] = col[y]; col[y] = j; } if (s == r ) { j = row[x]; row[x] = row[y]; row[y] = j; } } return 0; }
|
/*
Copyright (c) 2016-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2c_master_wbs_8
*/
module test_i2c_master_wbs_8;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [2:0] wbs_adr_i = 0;
reg [7:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire [7:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
wbs_adr_i,
wbs_dat_i,
wbs_we_i,
wbs_stb_i,
wbs_cyc_i,
i2c_scl_i,
i2c_sda_i
);
$to_myhdl(
wbs_dat_o,
wbs_ack_o,
i2c_scl_o,
i2c_scl_t,
i2c_sda_o,
i2c_sda_t
);
// dump file
$dumpfile("test_i2c_master_wbs_8.lxt");
$dumpvars(0, test_i2c_master_wbs_8);
end
i2c_master_wbs_8 #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_i(wbs_we_i),
.wbs_stb_i(wbs_stb_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_code_distance (clock, reset, enable, test_expr1, test_expr2, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min = 1;
parameter max = 1;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] test_expr1;
input [width-1 : 0] test_expr2;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_CODE_DISTANCE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_code_distance_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_code_distance
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_hdr_fifo.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_hdr_fifo module implements a simple fifo for a packet
// (WR_TX_HDR) header and three metadata signals: WR_TX_HDR_ABLANKS,
// WR_TX_HDR_LEN, WR_TX_HDR_NOPAYLOAD. NOPAYLOAD indicates that the header is not
// followed by a payload. HDR_LEN indicates the length of the header in
// dwords. The ABLANKS signal indicates how many dwords should be inserted between
// the header and payload.
//
// The intended use for this module is between the interface specific tx formatter
// (TXC or TXR) and the alignment pipeline, in parallel with the tx_data_pipeline
// which contains a fifo for payloads.
//
// Author: Dustin Richmond (@darichmond)
// Co-Authors:
//----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_hdr_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_PIPELINE_INPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR_TX_HDR
input WR_TX_HDR_VALID,
input [(C_MAX_HDR_WIDTH)-1:0] WR_TX_HDR,
input [`SIG_LEN_W-1:0] WR_TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] WR_TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] WR_TX_HDR_PACKET_LEN,
input WR_TX_HDR_NOPAYLOAD,
output WR_TX_HDR_READY,
// Interface: RD_TX_HDR
output RD_TX_HDR_VALID,
output [(C_MAX_HDR_WIDTH)-1:0] RD_TX_HDR,
output [`SIG_LEN_W-1:0] RD_TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] RD_TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] RD_TX_HDR_PACKET_LEN,
output RD_TX_HDR_NOPAYLOAD,
input RD_TX_HDR_READY
);
// Size of the header, plus the three metadata signals
localparam C_WIDTH = (C_MAX_HDR_WIDTH) + `SIG_NONPAY_W + `SIG_PACKETLEN_W + 1 + `SIG_LEN_W;
wire RST;
wire wWrTxHdrReady;
wire wWrTxHdrValid;
wire [(C_MAX_HDR_WIDTH)-1:0] wWrTxHdr;
wire [`SIG_NONPAY_W-1:0] wWrTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wWrTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wWrTxHdrPayloadLen;
wire wWrTxHdrNoPayload;
wire wRdTxHdrReady;
wire wRdTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wRdTxHdr;
wire [`SIG_NONPAY_W-1:0] wRdTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wRdTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wRdTxHdrPayloadLen;
wire wRdTxHdrNoPayload;
assign RST = RST_IN;
pipeline
#(
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
input_pipeline_inst
(
// Outputs
.WR_DATA_READY (WR_TX_HDR_READY),
.RD_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.RD_DATA_VALID (wWrTxHdrValid),
// Inputs
.WR_DATA ({WR_TX_HDR,WR_TX_HDR_NONPAY_LEN,WR_TX_HDR_PACKET_LEN,WR_TX_HDR_PAYLOAD_LEN,WR_TX_HDR_NOPAYLOAD}),
.WR_DATA_VALID (WR_TX_HDR_VALID),
.RD_DATA_READY (wWrTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
fifo
#(
// Parameters
.C_DELAY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH_PACKETS))
fifo_inst
(
// Outputs
.RD_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_READY (wWrTxHdrReady),
.RD_VALID (wRdTxHdrValid),
// Inputs
.WR_DATA ({wWrTxHdr,wWrTxHdrNonpayLen,wWrTxHdrPacketLen,wWrTxHdrPayloadLen,wWrTxHdrNoPayload}),
.WR_VALID (wWrTxHdrValid),
.RD_READY (wRdTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_USE_MEMORY (0),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
output_pipeline_inst
(
// Outputs
.WR_DATA_READY (wRdTxHdrReady),
.RD_DATA ({RD_TX_HDR,RD_TX_HDR_NONPAY_LEN,RD_TX_HDR_PACKET_LEN,RD_TX_HDR_PAYLOAD_LEN,RD_TX_HDR_NOPAYLOAD}),
.RD_DATA_VALID (RD_TX_HDR_VALID),
// Inputs
.WR_DATA ({wRdTxHdr,wRdTxHdrNonpayLen,wRdTxHdrPacketLen,wRdTxHdrPayloadLen,wRdTxHdrNoPayload}),
.WR_DATA_VALID (wRdTxHdrValid),
.RD_DATA_READY (RD_TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
#include <bits/stdc++.h> using namespace std; void code() { long long n, k; cin >> n >> k; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long ans = 0; for (long long i = 0; i < n; i++) { if ((a[i] - a[0]) % k != 0) { cout << -1 << endl; return; } ans += ((a[i] - a[0]) / k); } cout << ans << endl; } signed main() { code(); }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll inf = 1e9 + 10; const ll inf_ll = 1e18 + 10; ll qry(ll t, ll i, ll j, ll k) { cout << t << << i << << j << << k << endl; ll r; cin >> r; return r; } int main() { ll n; cin >> n; ll b = 2; for (ll i = 2; i <= n; i++) if (i != b && qry(2, 1, i, b) > 0) b = i; vector<ll> h(n + 5), ord(n - 2), l, r; for (ll i = 2; i <= n; i++) if (i != b) h[i] = qry(1, 1, i, b); iota((ord).begin(), (ord).end(), 3); for (ll& i : ord) if (i == b) i = 2; sort((ord).begin(), (ord).end(), [&](ll i, ll j) { return h[i] < h[j]; }); ll c = ord.back(); for (ll i : ord) { if (i != c && qry(2, 1, c, i) > 0) l.push_back(i); else r.push_back(i); } cout << 0 1 << b; for (ll i : r) cout << << i; reverse((l).begin(), (l).end()); for (ll i : l) cout << << i; cout << endl; }
|
#include <bits/stdc++.h> int p, v, n, s, t; int main(int argc, char** argv) { scanf( %d%d%d , &p, &v, &n); int aux = v; s = 0; t = 0; while (aux >= n) { int i; i = (aux / 50) % 475; for (int j = 0; j < 25; j++) { i = (i * 96 + 42) % 475; if (i + 26 == p) { printf( 0 n ); return 0; } } aux -= 50; } aux = v; t = 0; s = 0; while (aux <= 1000000) { int i; i = (aux / 50) % 475; for (int j = 0; j < 25; j++) { i = (i * 96 + 42) % 475; if (i + 26 == p) { printf( %d n , s); return 0; } } aux += 50; t++; t = t % 2; if (t == 1) { s++; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; int t, n, m, a[15], ans, b[10010]; char s[15][10010]; struct P { int val, id; } p[10010]; inline bool cmp(P x, P y) { return x.val < y.val; } int main() { scanf( %d , &t); while (t--) { scanf( %d%d , &n, &m); ans = 0; for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i < n; i++) scanf( %s , s[i] + 1); for (int i = 0; i < 1 << n; i++) { int sum = 0; for (int j = 1; j <= m; j++) { p[j].val = 0; p[j].id = j; } for (int j = 0; j < n; j++) { if (i & (1 << j)) { sum += a[j]; for (int k = 1; k <= m; k++) if (s[j][k] == 1 ) p[k].val--; } else { sum -= a[j]; for (int k = 1; k <= m; k++) if (s[j][k] == 1 ) p[k].val++; } } sort(p + 1, p + m + 1, cmp); for (int j = 1; j <= m; j++) sum += j * p[j].val; if (sum >= ans) { ans = sum; for (int j = 1; j <= m; j++) b[p[j].id] = j; } } for (int i = 1; i <= m; i++) printf( %d , b[i]); printf( n ); } return 0; }
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2017 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file constants_mem.v when simulating
// the core, constants_mem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module constants_mem(
clka,
addra,
douta
);
input clka;
input [9 : 0] addra;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(1),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("constants_mem.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(1),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a[n], b[n]; for (int i = 0; i < n; i++) scanf( %lld , a + i); for (int i = 0; i < n; i++) { scanf( %lld , b + i); } long long count = 0, index = 0; set<long long> s; for (int i = 0; i < n; i++) { long long count = 0; while (!s.count(b[i])) { s.insert(a[index]); index++; count++; } cout << count << ; } cout << endl; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:53:19 10/26/2014
// Design Name:
// Module Name: tb_uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_uart;
reg clk;
reg reset;
reg tx;
// Outputs
reg rx;
parameter CLK_PERIOD=20; //clock period in ns. 20 ns = 50 MHZ
parameter UUT_PERIOD=8'h1A; //57600 baudrate
parameter CLK16X_PERIOD=(CLK_PERIOD*(UUT_PERIOD+1)*2);
parameter CHARACTER_PERIOD = (CLK16X_PERIOD * 16 * 10);
uart u1(
.clk (clk),
.reset (reset),
.rxin (rx),
.txout (tx)
);
`define FSIZE 1024
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer errors;
initial begin
clk = 0;
#100 //reset delay
forever #10 clk = ~clk;
end
reg [9:0] shiftdata;
integer i;
task putserialdata;
input [8:0] outdata;
begin
infifo[head] = outdata;
head = head + 1;
if (head == `FSIZE) head = 0;
shiftdata ={1'b1,outdata[7:0],1'b0};
i = 0;
while (i != 10) begin
rx = shiftdata[0];
#(CLK16X_PERIOD*16) //wait one bit time
i = i + 1;
shiftdata = {1'b1,shiftdata[9:1]};
end
end
endtask
initial begin
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
#50;
putserialdata(9'h039);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { int a[3]; cin >> a[0] >> a[1] >> a[2]; sort(a, a + 3); if (a[0] + a[1] >= a[2] - 1) { cout << Yes n ; } else cout << No n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; if (t <= 203) { int dp[n * t + 1][301]; memset(dp, 0, sizeof(dp)); int ar[n * t]; int N = n * t; for (int ctr1 = 0; ctr1 < N; ctr1++) { if (ctr1 < n) cin >> ar[ctr1]; else ar[ctr1] = ar[ctr1 - n]; } for (int ctr1 = 1; ctr1 <= N; ctr1++) { for (int ctr2 = 0; ctr2 <= ar[ctr1 - 1]; ctr2++) { dp[ctr1][ar[ctr1 - 1]] = max(dp[ctr1][ar[ctr1 - 1]], 1 + dp[ctr1 - 1][ctr2]); } for (int ctr2 = 0; ctr2 <= 300; ctr2++) dp[ctr1][ctr2] = max(dp[ctr1][ctr2], dp[ctr1 - 1][ctr2]); } int r = 0; for (int ctr1 = 0; ctr1 <= 300; ctr1++) r = max(r, dp[N][ctr1]); cout << r << endl; return 0; } else { int dp[n * 101 + 1][301]; memset(dp, 0, sizeof(dp)); int ar[n * 101]; int N = n * 101; int poj[301]; memset(poj, 0, sizeof(poj)); for (int ctr1 = 0; ctr1 < N; ctr1++) { if (ctr1 < n) { cin >> ar[ctr1]; poj[ar[ctr1]]++; } else ar[ctr1] = ar[ctr1 - n]; } for (int ctr1 = 1; ctr1 <= N; ctr1++) { for (int ctr2 = 0; ctr2 <= ar[ctr1 - 1]; ctr2++) { dp[ctr1][ar[ctr1 - 1]] = max(dp[ctr1][ar[ctr1 - 1]], 1 + dp[ctr1 - 1][ctr2]); } for (int ctr2 = 0; ctr2 <= 300; ctr2++) dp[ctr1][ctr2] = max(dp[ctr1][ctr2], dp[ctr1 - 1][ctr2]); } int dp2[n * 101 + 1][301]; memset(dp2, 0, sizeof(dp2)); for (int ctr1 = N - 1; ctr1 >= 0; ctr1--) { for (int ctr2 = 300; ctr2 >= ar[ctr1]; ctr2--) { dp2[ctr1][ar[ctr1]] = max(dp2[ctr1][ar[ctr1]], 1 + dp2[ctr1 + 1][ctr2]); } for (int ctr2 = 1; ctr2 <= 300; ctr2++) dp2[ctr1][ctr2] = max(dp2[ctr1][ctr2], dp2[ctr1 + 1][ctr2]); } int r = 0; int nt = t - 202; for (int ctr1 = 1; ctr1 <= 300; ctr1++) r = max(r, dp[N][ctr1] + dp2[0][ctr1] + nt * poj[ctr1]); cout << r << endl; } return 0; }
|
`timescale 1ns / 100ps
module uartlib(
input UART_CLK, output reg UART_TX
);
integer counter;
initial
UART_TX = 1;
task write_byte;
input [7:0] data;
begin
//start bit
$display("write_byte: 0x%x (0b%b) [%c]", data, data, data);
repeat(2) @(posedge UART_CLK) UART_TX <= 1;
@(posedge UART_CLK) UART_TX <= 0;
//data
@(posedge UART_CLK) UART_TX <= data[0];
@(posedge UART_CLK) UART_TX <= data[1];
@(posedge UART_CLK) UART_TX <= data[2];
@(posedge UART_CLK) UART_TX <= data[3];
@(posedge UART_CLK) UART_TX <= data[4];
@(posedge UART_CLK) UART_TX <= data[5];
@(posedge UART_CLK) UART_TX <= data[6];
@(posedge UART_CLK) UART_TX <= data[7];
//stop bit
@(posedge UART_CLK) UART_TX <= 1;
repeat(2) @(posedge UART_CLK);
end
endtask
task write;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h77); //0x77 = w
repeat(40) @(posedge UART_CLK) ;
end
endtask
task read;
input [31:0] addr;
input [31:0] size;
begin
repeat (40) @(posedge UART_CLK);
write_byte(8'h61); // 0x61 = a
write_byte(addr[7:0]);
write_byte(addr[15:8]);
write_byte(addr[23:16]);
write_byte(addr[31:24]);
repeat(40) @(posedge UART_CLK) ;
write_byte(8'h6c); // 0x6c = l
write_byte(size[7:0]);
write_byte(size[15:8]);
write_byte(size[23:16]);
write_byte(size[31:24]);
repeat(40) @(posedge UART_CLK) ;//wait for receiving OK
write_byte(8'h72); // 0x72 = r
repeat(40) @(posedge UART_CLK) ;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n, h, x, r = 0; cin >> n >> h; for (int i = 0; i < n; i++) { cin >> x; if (x > h) { r += 2; } else { r += 1; } } cout << r << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int dp[160][160]; int main() { int n; scanf( %d , &n); dp[1][1] = 1; dp[0][0] = 1; for (int i = 2; i <= n; i++) { for (int j = 0; j <= n; j++) { if (j == 0) dp[i][j] = dp[i - 2][j]; else dp[i][j] = (dp[i - 2][j] + dp[i - 1][j - 1]) % 2; } } cout << n << endl; for (int i = 0; i <= n; i++) cout << dp[n][i] << ; cout << endl; cout << n - 1 << endl; for (int i = 0; i <= n - 1; i++) cout << dp[n - 1][i] << ; return 0; }
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:50:09 06/01/2015
// Design Name: mixColumnsAll
// Module Name: F:/Projects/Xilinx/Rijndael/test_mixcolumnsall.v
// Project Name: Rijndael
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mixColumnsAll
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mixcolumnsall;
// Inputs
reg [127:0] mixIn;
reg clk;
reg inverse;
// Outputs
wire [127:0] mixOut;
// Instantiate the Unit Under Test (UUT)
mixColumnsAll uut (
.mixOut(mixOut),
.mixIn(mixIn),
.clk(clk),
.inverse(inverse)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
// Initialize Inputs
inverse = 0;
mixIn = 128'h6353e08c0960e104cd70b751bacad0e7;
#20 mixIn = 128'ha7be1a6997ad739bd8c9ca451f618b61;
#20 mixIn = 128'h3bd92268fc74fb735767cbe0c0590e2d;
#20 mixIn = 128'h2d6d7ef03f33e334093602dd5bfb12c7;
#20 mixIn = 128'h36339d50f9b539269f2c092dc4406d23;
#100
// Test Inverse MixColumns
inverse = 1;
#20 mixIn = 128'hbd6e7c3df2b5779e0b61216e8b10b689;
#20 mixIn = 128'hfde3bad205e5d0d73547964ef1fe37f1;
#20 mixIn = 128'hd1876c0f79c4300ab45594add66ff41f;
#20 mixIn = 128'hc62fe109f75eedc3cc79395d84f9cf5d;
#20 mixIn = 128'hc81677bc9b7ac93b25027992b0261996;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, l, t, a[3000010], gx; double Ans; signed main() { scanf( %lld%lld%lld , &n, &l, &t); t *= 2; gx = t / l, t %= l; for (long long i = 1; i <= n; i++) scanf( %lld , &a[i + n]); for (long long i = 1; i <= n; i++) a[i] = a[i + n] - l; for (long long i = 1; i <= n; i++) a[i + n + n] = a[i + n] + l; for (long long i = 1, j1 = 1, j2 = i + 1; i <= n; i++) { while (a[i + n] - a[j1] > t) j1++; while (a[j2 + 1] - a[i + n] <= t && j2 + 1 <= 3 * n) j2++; Ans += 0.25 * ((n - 1) * gx + i + n - j1 + (n - 1) * gx + j2 - i - n); } printf( %.6lf n , Ans / 2); }
|
// clockgen.v
// clock generator
module clockgen
(
input clk,
input reset,
input [5:0]clkdiv,
input shift,
input stretch,
output reg sync,
output reg phase,
output reg adcclk,
output reg adcsync
);
// --- main counter (phase register) --------------------
reg [5:0]counter;
always @(posedge clk or posedge reset)
begin
if (reset) counter <= 6'd0;
else if (!shift) counter <= counter + 6'd1;
end
// --- adc sync/phase generator -------------------------
reg adcfsel;
always @(*)
begin
case (clkdiv[5:3])
0: adcfsel <= counter[0];
1: adcfsel <= counter[1];
2: adcfsel <= counter[2];
3: adcfsel <= counter[3];
4: adcfsel <= counter[4];
default: adcfsel = counter[5];
endcase
end
wire adcgen_sync;
wire adcgen_phase;
clocksm adcgen
(
.clk(clk),
.reset(reset),
.syncin(adcfsel),
.veto(1'b0),
.sync(adcgen_sync),
.phase(adcgen_phase)
);
always @(posedge clk or posedge reset)
begin
if (reset)
begin
adcsync <= 0;
adcclk <= 0;
end
else
begin
adcsync <= adcgen_sync;
adcclk <= adcgen_phase;
end
end
// --- sync/phase generator -----------------------------
reg fsel;
always @(*)
begin
case (clkdiv[2:0])
0: fsel <= counter[0];
1: fsel <= counter[1];
2: fsel <= counter[2];
3: fsel <= counter[3];
4: fsel <= counter[4];
default: fsel = counter[5];
endcase
end
wire clkgen_sync;
wire clkgen_phase;
clocksm clkgen
(
.clk(clk),
.reset(reset),
.syncin(fsel),
.veto(stretch),
.sync(clkgen_sync),
.phase(clkgen_phase)
);
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sync <= 0;
phase <= 0;
end
else
begin
sync <= clkgen_sync;
phase <= clkgen_phase;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const double eps = 1e-12; int n, k, h; struct lemming { int w, v, id; bool operator<(const lemming &rhs) const { if (w != rhs.w) return w < rhs.w; return v < rhs.v; } } a[maxn]; vector<int> ans; int dcmp(double x) { if (fabs(x) < eps) return x; return x > 0 ? 1 : -1; } bool ok(double t) { vector<int> v; for (int i = 1, j = 1; i <= n; i++) { if (dcmp(t - (double)h * j / a[i].v) < 0) continue; v.emplace_back(a[i].id); j++; if (j > k) break; } if (v.size() < k) return 0; ans = v; return 1; } int main() { scanf( %d %d %d , &n, &k, &h); for (int i = 1; i <= n; i++) scanf( %d , &a[i].w), a[i].id = i; for (int i = 1; i <= n; i++) scanf( %d , &a[i].v); sort(a + 1, a + 1 + n); double l = 0, r = 1e9; for (int i = 0; i < 150; i++) { double mid = (l + r) / 2; if (ok(mid)) r = mid; else l = mid; } for (auto i : ans) printf( %d , i); }
|
/*
This is a simple SPI slave to GPIO bridge. It has a clock input, a synchronous
reset input, an SPI slave interface which is supposed to be hooked up to an SPI
master and an 8-bit output register. The contents of the output register is
updated by doing a one byte SPI transaction. A bit is registered every time
there is a falling edge on sclk and cs_n is deasserted.
*/
module spi_slave
#(parameter INIT_VALUE = 8'd0)
(
input clk,
input rst,
input sclk_i,
input mosi_i,
output miso_o = 1'b0,
input cs_n_i,
output reg [7:0] gpio_o);
reg sclk_r;
wire sclk_edge = ~cs_n_i & sclk_r & ~sclk_i;
reg [2:0] cnt;
always @(posedge clk) begin
sclk_r <= sclk_i;
if (cs_n_i)
cnt <= 3'd0;
else if (sclk_edge) begin
cnt <= cnt + 1'd1;
gpio_o[cnt] <= mosi_i;
end
if (rst) begin
cnt <= 3'd0;
sclk_r <= 1'd1;
gpio_o <= INIT_VALUE;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : ui_cmd.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
// User interface command port.
module ui_cmd #
(
parameter TCQ = 100,
parameter ADDR_WIDTH = 33,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter RANKS = 4,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
rd_accepted, wr_accepted, data_buf_addr,
// Inputs
rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
);
input rst;
input clk;
input accept_ns;
input rd_buf_full;
input wr_req_16;
wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
//synthesis attribute max_fanout of app_rdy_r is 10;
reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */;
always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
reg app_rdy_inv_r;
always @(posedge clk) app_rdy_inv_r <= #TCQ ~app_rdy_ns;
output wire app_rdy;
assign app_rdy = app_rdy_r;
input [ADDR_WIDTH-1:0] app_addr;
input [2:0] app_cmd;
input app_sz;
input app_hi_pri;
input app_en;
reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
reg [2:0] app_cmd_r1;
reg [2:0] app_cmd_r2;
reg app_sz_r1;
reg app_sz_r2;
reg app_hi_pri_r1;
reg app_hi_pri_r2;
reg app_en_r1;
reg app_en_r2;
wire [ADDR_WIDTH-1:0] app_addr_ns1 = ({ADDR_WIDTH{app_rdy_r}} & {ADDR_WIDTH{app_en}} & app_addr) | ({ADDR_WIDTH{app_rdy_inv_r}} & app_addr_r1);
wire [ADDR_WIDTH-1:0] app_addr_ns2 = ({ADDR_WIDTH{app_rdy_r}} & app_addr_r1) | ({ADDR_WIDTH{app_rdy_inv_r}} & app_addr_r2);
wire [2:0] app_cmd_ns1 = ({3{app_rdy_r}} & app_cmd) | ({3{app_rdy_inv_r}} & app_cmd_r1);
wire [2:0] app_cmd_ns2 = ({3{app_rdy_r}} & app_cmd_r1) | ({3{app_rdy_inv_r}} & app_cmd_r2);
wire app_sz_ns1 = (app_rdy_r & app_sz) | (app_rdy_inv_r & app_sz_r1);
wire app_sz_ns2 = (app_rdy_r & app_sz_r1) | (app_rdy_inv_r & app_sz_r2);
wire app_hi_pri_ns1 = (app_rdy_r & app_hi_pri) | (app_rdy_inv_r & app_hi_pri_r1);
wire app_hi_pri_ns2 = (app_rdy_r & app_hi_pri_r1) | (app_rdy_inv_r & app_hi_pri_r2);
wire app_en_ns1 = ~rst && ((app_rdy_r & app_en )| (app_rdy_inv_r & app_en_r1));
wire app_en_ns2 = ~rst && ((app_rdy_r & app_en_r1 )| (app_rdy_inv_r & app_en_r2));
always @(posedge clk) begin
app_addr_r1 <= #TCQ app_addr_ns1;
app_addr_r2 <= #TCQ app_addr_ns2;
app_cmd_r1 <= #TCQ app_cmd_ns1;
app_cmd_r2 <= #TCQ app_cmd_ns2;
app_sz_r1 <= #TCQ app_sz_ns1;
app_sz_r2 <= #TCQ app_sz_ns2;
app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
app_en_r1 <= #TCQ app_en_ns1;
app_en_r2 <= #TCQ app_en_ns2;
end // always @ (posedge clk)
wire use_addr_lcl = app_en_r2 && app_rdy_r;
output wire use_addr;
assign use_addr = use_addr_lcl;
output wire [RANK_WIDTH-1:0] rank;
output wire [BANK_WIDTH-1:0] bank;
output wire [ROW_WIDTH-1:0] row;
output wire [COL_WIDTH-1:0] col;
output wire size;
output wire [2:0] cmd;
output wire hi_priority;
assign col = ({COL_WIDTH{app_rdy_r}} & app_addr_r1[0+:COL_WIDTH]) |
({COL_WIDTH{app_rdy_inv_r}} & app_addr_r2[0+:COL_WIDTH]);
generate
begin
if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
begin
assign row = ({ROW_WIDTH{app_rdy_r}} & app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]) |
({ROW_WIDTH{app_rdy_inv_r}} & app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]);
assign bank = ({BANK_WIDTH{app_rdy_r}} & app_addr_r1[COL_WIDTH+:BANK_WIDTH]) |
({BANK_WIDTH{app_rdy_inv_r}} & app_addr_r2[COL_WIDTH+:BANK_WIDTH]);
end
else
begin
assign row = ({ROW_WIDTH{app_rdy_r}} & app_addr_r1[COL_WIDTH+:ROW_WIDTH]) |
({ROW_WIDTH{app_rdy_inv_r}} & app_addr_r2[COL_WIDTH+:ROW_WIDTH]);
assign bank = ({BANK_WIDTH{app_rdy_r}} & app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]) |
({BANK_WIDTH{app_rdy_inv_r}} & app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]);
end
end
endgenerate
assign rank = (RANKS == 1)
? 1'b0
: (({RANK_WIDTH{app_rdy_r}} & app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]) |
({RANK_WIDTH{app_rdy_inv_r}} & app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]));
assign size = (app_rdy_r & app_sz_r1) | (app_rdy_inv_r & app_sz_r2);
assign cmd = ({3{app_rdy_r}} & app_cmd_r1) | ({3{app_rdy_inv_r}} & app_cmd_r2);
assign hi_priority = (app_rdy_r & app_hi_pri_r1) | (app_rdy_inv_r & app_hi_pri_r2);
wire request_accepted = use_addr_lcl && app_rdy_r;
wire rd = app_cmd_r2[1:0] == 2'b01;
wire wr = app_cmd_r2[1:0] == 2'b00;
wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
wire write = wr || wr_bytes;
output wire rd_accepted;
assign rd_accepted = request_accepted && rd;
output wire wr_accepted;
assign wr_accepted = request_accepted && write;
input [3:0] wr_data_buf_addr;
input [3:0] rd_data_buf_addr_r;
output wire [3:0] data_buf_addr;
assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
endmodule // ui_cmd
// Local Variables:
// verilog-library-directories:(".")
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); bool val = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { int a; scanf( %d , &a); if (i == j) { val ^= a; } } } int q; scanf( %d , &q); while (q--) { int t; scanf( %d , &t); if (t == 3) { printf( %d , val); } else { int i; scanf( %d , &i); val ^= 1; } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 10, mod = 1e9 + 9; const int maxn = 500010; const long double eps = 1e-5; const int EPS = 500 * 500; template <typename T> void read(T &x) { x = 0; char ch = getchar(); long long first = 1; while (!isdigit(ch)) { if (ch == - ) first *= -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 48; ch = getchar(); } x *= first; } template <typename T, typename... Args> void read(T &first, Args &...args) { read(first); read(args...); } int main() { std::ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int _; cin >> _; while (_--) { int n, second; cin >> n >> second; cout << second / (n / 2 + 1) << n ; } }
|
////////////////////////////////////////////////////////////////////////////////////
// File: sram_wrapper.v
// Author: B. Brown
// About: Abstracts the Altera DE2 SRAM signals away with a basic RAM interface.
////////////////////////////////////////////////////////////////////////////////////
module sram_wrapper
(
// Clock and Reset
input wire clk,
input wire aresetn,
// Wrapper Signals
input wire wen,
input wire [19:0] addr,
input wire [15:0] din,
output wire [15:0] dout,
// SRAM Signals
output wire [19:0] SRAM_ADDR,
output wire SRAM_CE_N,
inout wire [15:0] SRAM_DQ,
output wire SRAM_LB_N,
output wire SRAM_OE_N,
output wire SRAM_UB_N,
output wire SRAM_WE_N
);
reg [15:0] a;
reg [15:0] b;
reg wen_latch;
reg [19:0] addr_latch;
wire output_enable;
// Latch write enable and address to account for bidir delay
always @(posedge clk) wen_latch <= wen;
always @(posedge clk) addr_latch <= addr;
// Enable the output if you're in read mode
assign output_enable = ~wen_latch;
// From Altera Bidirectional Example
// https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_bidirec.tablet.highResolutionDisplay.html
always @(posedge clk) begin
a <= din;
b <= SRAM_DQ;
end
assign SRAM_DQ = ~output_enable ? a : 16'bZ;
assign dout = b;
// Write enable
assign SRAM_WE_N = ~wen_latch;
// If not resetting, enable the chip (invert for active-low)
assign SRAM_CE_N = ~aresetn;
// Invert signal described above for active-low
assign SRAM_OE_N = ~output_enable;
// Upper and Lower Byte: Set active-low for read or write
assign SRAM_LB_N = 1'b0;
assign SRAM_UB_N = 1'b0;
// Pass address for read or write
assign SRAM_ADDR = addr_latch;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 405; const int inf = 0x3f3f3f3f; int n, m; int a[maxn]; int f[maxn][maxn][maxn]; template <typename T> inline void minimize(T &target, const T &value) { if (target > value) { target = value; } } void divide(int a[], int f[], int g[], int l, int r, int pl, int pr) { if (l > r) { return; } int m = (l + r) / 2; int ptr = l; for (int i = pl; i < min(m, pr + 1); ++i) { int tmp = max(f[i], a[m] - a[i]); if (tmp < g[m]) { g[m] = tmp; ptr = i; } } divide(a, f, g, l, m - 1, pl, ptr); divide(a, f, g, m + 1, r, ptr, pr); } void compute(int a[], int n, int f[maxn][maxn]) { f[0][0] = 0; for (int i = 1; i < n; ++i) { divide(a, f[i - 1], f[i], 0, n - 1, 0, n - 1); } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d , a + i); } memset(f, inf, sizeof(f)); compute(a, n, f[0]); for (int i = 0; i < n; ++i) { compute(a + i, n - i, f[i]); } long long ans = 0; while (m--) { int s, f, c, r; scanf( %d%d%d%d , &s, &f, &c, &r), s--, f--; r++; r = min(r, f - s); r = max(r, 1); ans = max(ans, (long long)c * ::f[s][r][f - s]); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; string s; getline(cin, s); set<char> st; for (int i = 0; i < s.length(); i++) { if (s[i] == { || s[i] == } || s[i] == , || s[i] == ) { continue; } else { st.insert(s[i]); } } cout << st.size(); }
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int main() { fast(); long long n; cin >> n; if (n % 4 == 1) cout << 0 << << A << endl; else if (n % 4 == 0) cout << 1 << << A << endl; else if (n % 4 == 2) cout << 1 << << B << endl; else if (n % 4 == 3) cout << 2 << << A << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_TB_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_TB_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bomb.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bomb (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bomb.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bomb.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bomb_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: redDiskWin.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module redDiskWin (
address,
clock,
q);
input [7:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "redDiskWin.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "225"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "redDiskWin.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "225"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL redDiskWin_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; long long int mod1 = 1000000007; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int t; t = 1; for (long long int f = 0; f < t; f++) { int n; cin >> n; string A; cin >> A; int i; int x = n - 11; int in = -1, c = 0; int y = 0; int r = ceil(x / 2.0); x = x / 2; for (i = 0; i < n; i++) { if (in == -1 && A[i] == 8 ) in = i + 1; if (A[i] == 8 ) c++; if (c == x + 1 && y == 0) y = i + 1; } if (in - 1 > r) { cout << NO << endl; continue; } if (c <= x) { cout << NO << endl; continue; } else { y = y - x; y--; if (y <= r) { cout << YES << endl; continue; } cout << NO << endl; } } }
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.1 (lin64) Build Fri Apr 8 15:45:23 MDT 2016
//Date : Mon Jun 6 23:44:13 2016
//Host : edinburgh running 64-bit Ubuntu 15.04
//Command : generate_target opl3_cpu_wrapper.bd
//Design : opl3_cpu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module opl3_cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
ac_mclk,
ac_mute_n,
clk125,
i2s_sclk,
i2s_sd,
i2s_ws,
iic_0_scl_io,
iic_0_sda_io,
led);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output ac_mclk;
output ac_mute_n;
input clk125;
output i2s_sclk;
output i2s_sd;
output i2s_ws;
inout iic_0_scl_io;
inout iic_0_sda_io;
output [3:0]led;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire ac_mclk;
wire ac_mute_n;
wire clk125;
wire i2s_sclk;
wire i2s_sd;
wire i2s_ws;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire [3:0]led;
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
opl3_cpu opl3_cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.ac_mclk(ac_mclk),
.ac_mute_n(ac_mute_n),
.clk125(clk125),
.i2s_sclk(i2s_sclk),
.i2s_sd(i2s_sd),
.i2s_ws(i2s_ws),
.led(led));
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_pixelfeed();
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
reg vga_rst;
wire pixel_valid;
wire fml_stb;
wire [25:0] fml_adr;
initial begin
sys_rst = 1'b1;
vga_rst = 1'b1;
#20 sys_rst = 1'b0;
#20 vga_rst = 1'b0;
end
vgafb_pixelfeed dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(18'd100),
.baseaddress(26'd1024),
.baseaddress_ack(),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_stb),
.fml_di(64'hcafebabedeadbeef),
.pixel_valid(pixel_valid),
.pixel(),
.pixel_ack(pixel_valid)
);
always @(posedge sys_clk) $display("%x", fml_adr);
initial #600 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; unordered_set<int> si; int fff = 0; int fj = 2; void mmin(int &t) { for (int j = fj; 1;) { int fflag = 0; vector<int> pr; for (int i = 2; i < sqrt(j) + 1; i++) { if (j % i == 0) { if (si.find(i) == si.end() && si.find(j / i) == si.end()) { pr.push_back(i); pr.push_back(j / i); } else { fflag = 2; break; } } } if (fflag == 0 && si.find(j) == si.end()) { for (auto tt : pr) si.insert(tt); si.insert(j); t = j; fj = j + 1; fff = 1; break; } if (j % 2 == 0) j++; else j += 2; } } void check(int &t) { vector<int> prime; int flag = 0; for (int i = 2; i < sqrt(t) + 1; i++) { if (t % i == 0) { if (si.find(i) == si.end()) prime.push_back(i); else { flag = 1; break; } if (si.find(t / i) == si.end()) prime.push_back(t / i); else { flag = 1; break; } } } if (si.find(t) == si.end()) prime.push_back(t); else { flag = 1; } if (flag) { for (int j = t + 1; 1; j++) { int fflag = 0; for (int i = 2; i < sqrt(j) + 1; i++) { if (j % i == 0) { if (si.find(i) == si.end() && si.find(j / i) == si.end()) ; else { fflag = 2; break; } } } if (fflag == 0 && si.find(j) == si.end()) { for (int i = 2; i < max((int)sqrt(j) + 1, j); i++) if (j % i == 0) { si.insert(i); si.insert(j / i); } si.insert(j); t = j; fff = 1; break; } } } else { for (auto tt : prime) si.insert(tt); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<int> ans; for (int i = 0; i < n; i++) { int t; cin >> t; if (t == 1) { ans.push_back(t); continue; } if (fff == 1) mmin(t); else check(t); ans.push_back(t); } for (auto t : ans) cout << t << ; cout << endl; }
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 29 14:16:28 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.v
// Design : dcfifo_32in_32out_16kb
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_16kb(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[0:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [0:0]wr_data_count;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long tree[4000005]; long long level[4000005]; long long num[1000005]; long long build(long long at, long long L, long long R) { if (L == R) { tree[at] = num[L]; level[at] = 1; return num[L]; } long long mid = (L + R) / 2, a, b, p; a = build(at * 2, L, mid); b = build(at * 2 + 1, mid + 1, R); level[at] = p = level[at * 2] + 1; if (p % 2) tree[at] = a ^ b; else tree[at] = a | b; return tree[at]; } long long update(long long at, long long L, long long R, long long i, long long x) { if (L == R) { tree[at] = x; return tree[at]; } long long mid = (L + R) / 2, a, b; if (L <= i && mid >= i) a = update(at * 2, L, mid, i, x), b = tree[at * 2 + 1]; else a = update(at * 2 + 1, mid + 1, R, i, x), b = tree[at * 2]; if (level[at] % 2) tree[at] = a ^ b; else tree[at] = a | b; return tree[at]; } int main() { long long n, m; long long a, i, j; long long x, y; cin >> n >> m; n = pow(2, n); for (a = 1; a <= n; a++) cin >> num[a]; build(1, 1, n); for (a = 0; a < m; a++) { cin >> x >> y; update(1, 1, n, x, y); cout << tree[1] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2 * 100000 + 10; int _min(int a, int b) { if (a < b) return a; else return b; } int _max(int a, int b) { if (a > b) return a; else return b; } char s[1005]; int col[4] = {0}; int row[4] = {0}; int main() { scanf( %s , s); int len = strlen(s); for (int i = 0; i < len; i++) { if (s[i] == 0 ) { for (int j = 0; j < 4; j++) { if (col[j] == 0) { col[j] = 1; printf( %d %d n , 1, j + 1); break; } } } else { for (int j = 0; j < 4; j++) { if (row[j] == 0) { row[j] = 1; if (j == 0) printf( 3 1 n ); if (j == 1) printf( 3 3 n ); if (j == 2) printf( 4 1 n ); if (j == 3) printf( 4 3 n ); break; } } } int flag = 0; for (int j = 0; j < 4; j++) { if (col[j] == 0) { flag = 1; break; } } if (flag == 0) { for (int j = 0; j < 4; j++) col[j] = 0; } if (row[0] == 1 && row[1] == 1) { row[0] = 0; row[1] = 0; } if (row[2] == 1 && row[3] == 1) { row[2] = 0; row[3] = 0; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_1_V
`define SKY130_FD_SC_HDLL__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_1_V
|
`define MSBI 9 // Most significant Bit of DAC input
// this is a delta-sigma digital to analog converter
module dac (o, i, clock, reset);
output o; // this is the average output that feeds low pass filter
input [`MSBI:0] i; // dac input (excess 2**msbi)
input clock;
input reset;
reg o; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(i or DeltaB) DeltaAdder = i + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clock or posedge reset)
begin
if(reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
o <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
o <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
|
`timescale 1ns / 1ps
module DMA_Controller #(
parameter N = 6,
parameter WIDTH = 16,
parameter ADDR = 12,
parameter M_WIDTH = 2*WIDTH+N-1
)(
input clk,
input start,
// MATRIX MEMORY A
output reg A_rd,
output reg [ADDR-1:0] A_addr,
input [N*WIDTH-1:0] A_dout,
// MATRIX MEMORY B
output reg B_rd,
output reg [ADDR-1:0] B_addr,
input [N*WIDTH-1:0] B_dout,
// MATRIX MEMORY C
output reg C_wr,
output reg [ADDR-1:0] C_addr,
output reg [N*M_WIDTH-1:0] C_din,
// MAC BASE INTERFACE
output reg sof,
output reg [N*WIDTH-1:0] A,
output reg [WIDTH-1:0] B,
input [N*M_WIDTH-1:0] C,
input [N-1:0] valid
);
reg state;
parameter
IDLE = 1'b0,
FETCH = 1'b1;
initial begin
A <= 0;
B <= 0;
sof <= 1'b0;
state <= IDLE;
A_rd <= 1'b0;
B_rd <= 1'b0;
C_wr <= 1'b0;
A_addr <= 0;
B_addr <= 0;
C_addr <= 0;
C_din <= 0;
end
always@(posedge clk) begin
case(state)
IDLE: begin
A_addr <= 0;
B_addr <= 0;
A_rd <= 1'b0;
B_rd <= 1'b0;
sof <= 1'b0;
if(start) begin
A_addr <= 0;
B_addr <= 0;
A_rd <= 1'b1;
B_rd <= 1'b1;
sof <= 1'b0;
state <= FETCH;
end
end
FETCH: begin
if(B_addr!= N) begin
B_rd <= 1'b1;
if(A_addr != N) begin
A_rd <= 1'b1;
A_addr <= A_addr + 1;
A <= A_dout;
B <= (B_dout >> WIDTH*A_addr);
sof <= 1'b1;
if(A_addr == N-1) begin
B_addr <= B_addr + 1;
A_addr <= 0;
end
if(A_addr == 0) begin
// sof <= 1'b0;
end
end
end
else
state <= IDLE;
end
endcase
end
always@(posedge clk) begin
if(&valid) begin
C_wr <= 1'b1;
C_addr <= C_addr + 1;
C_din <= C;
end
else begin
C_wr <= 1'b0;
C_din <= 0;
end
end
/*genvar i;
generate for (i = 0; i < N; i = i + 1) begin
always@(posedge clk) begin
if(valid[i]) begin
C_wr <= 1'b1;
C_addr <= C_addr + 1;
C_din <= C_din && M_WIDTH{1'b1};
end
end endgenerate
*/
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc3_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc3_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int i = 0, j = 0, cs = 0, in; int n; cin >> n; vector<int> v; int sum = 0, s = 0; for (int i = 1; i < n; i++) { cout << ? << i << << n << n ; int x; cin >> x; if (i > 1) { v.push_back(sum - x - s); s += v.back(); } else sum = x; } cout << ? << 1 << << n - 1 << n ; int x; cin >> x; cout << ! ; for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << x - s << << sum - x << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; struct Segment { int left, right; } seg[N / 2 + 5]; map<int, bool> m; int a[N]; int n, ans; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); m.clear(); ans = 1; seg[ans].left = 1; m[a[1]] = true; int i = 2; while (i <= n) { if (m[a[i]]) { seg[ans].right = i; if (i == n) break; ans++; i++; seg[ans].left = i; m.clear(); } m[a[i]] = true; i++; } if (i > n) { if (ans == 1) { printf( -1 n ); return 0; } ans--; seg[ans].right = n; } printf( %d n , ans); for (int i = 1; i <= ans; i++) printf( %d %d n , seg[i].left, seg[i].right); return 0; }
|
/**
* Frame buffer
* 800x480 ( / 16 = 24000) for hack screen of 512 x 256
*
* Translate pixel positions to ram addresses then uses ram.
*/
module frame_buffer(
input clk, // the system clock
input [15:0] read_value,
input [7:0] keyboard, // debug the current keypress on the vga
input [14:0] pc, // debug the current program count on the vga
input [15:0] instruction, // debug the current instruction register on the vga
input [15:0] data_register, // debug the current instruction register on the vga
input [15:0] areg, // debug the ARegister
input [15:0] dreg, // debug the DRegister
input [10:0] vga_h, // the current vertical pixel count being displayed
input [10:0] vga_v, // the current horizontal pixel count being displayed
output [23:0] pixel_out, // The requested pixel value at vga_h x vga_v
output [12:0] read_address
);
reg [2:0] out;
wire [4:0] pixel_bit;
wire [15:0] pixel_bit_calc;
wire [31:0] pixel_addr;
assign pixel_addr = ((vga_h - 11'd144) + ((vga_v - 11'd112) * 32'd512)) >> 4;
assign pixel_bit_calc = (vga_h - 11'd144) + (vga_v - 11'd112);
assign pixel_bit = pixel_bit_calc[3:0];
assign read_address = pixel_addr[12:0];
assign pixel_out[23:16] = {8{out[2]}}; // translate the single bit to 8 bits
assign pixel_out[15:8] = {8{out[1]}}; // translate the single bit to 8 bits
assign pixel_out[7:0] = {8{out[0]}}; // translate the single bit to 8 bits
// Keyboard debug
wire [2:0] kb_display_out;
wire kb_display_on;
register_display #(.START_H(11'd10), .START_V(11'd10)) kb_display (
.clk(clk), .data_in({8'd0, keyboard}),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(kb_display_out), .display_on(kb_display_on)
);
// program counter debug
wire [2:0] pc_display_out;
wire pc_display_on;
register_display #(.START_H(11'd10), .START_V(11'd20)) pc_display (
.clk(clk), .data_in(pc),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(pc_display_out), .display_on(pc_display_on)
);
// Instruction debug
wire [2:0] instruction_display_out;
wire instruction_display_on;
register_display #(.START_H(11'd10), .START_V(11'd30)) instruction_display (
.clk(clk), .data_in(instruction),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(instruction_display_out), .display_on(instruction_display_on)
);
// data_register debug
wire [2:0] data_register_display_out;
wire data_register_display_on;
register_display #(.START_H(11'd10), .START_V(11'd40)) data_register_display (
.clk(clk), .data_in(data_register),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(data_register_display_out), .display_on(data_register_display_on)
);
// ARegister debug
wire [2:0] areg_display_out;
wire areg_display_on;
register_display #(.START_H(11'd200), .START_V(11'd10)) areg_display (
.clk(clk), .data_in({8'd0, areg}),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(areg_display_out), .display_on(areg_display_on)
);
// DRegister debug
wire [2:0] dreg_display_out;
wire dreg_display_on;
register_display #(.START_H(11'd200), .START_V(11'd20)) dreg_display (
.clk(clk), .data_in({8'd0, dreg}),
.vga_h(vga_h), .vga_v(vga_v),
.bg(3'b001), .pixel_out(dreg_display_out), .display_on(dreg_display_on)
);
always @ (posedge clk) begin
// border surrounding the hack screen of 512 x 256
// on the 800 x 480 vga screen
if (vga_h < 11'd144 || vga_h > 11'd655
|| vga_v < 11'd112 || vga_v > 11'd367) begin
if (kb_display_on) begin
out <= kb_display_out;
end else if (instruction_display_on) begin
out <= instruction_display_out;
end else if (data_register_display_on) begin
out <= data_register_display_out;
end else if (pc_display_on) begin
out <= pc_display_out;
end else if (areg_display_on) begin
out <= areg_display_out;
end else if (dreg_display_on) begin
out <= dreg_display_out;
end else begin
out <= 3'b001;
end
end else begin
// hack screen contents from the screen ram
if (read_value[pixel_bit]) begin
out <= 3'b000;
end else begin
out <= 3'b111;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { bool x = false; string s; cin >> s; string b; for (int i = 0; i < s.size(); i++) { if (s[i] == d && s[i + 1] == o && s[i + 2] == t && i != 0 && i + 2 < s.size() - 1) { b += . ; s[i + 1] = ; s[i + 2] = ; } else if (x == false && s[i] == a && s[i + 1] == t && i != 0 && i + 1 < s.size() - 1) { b += @ ; s[i + 1] = ; x = true; } else if (s[i] != ) { b += s[i]; } } cout << b; return 0; }
|
#include <bits/stdc++.h> using namespace std; queue<pair<int, int> > L, R; int **M; int ori, n, m; bool play(pair<int, int> &p, int &ori) { for (int i = 0; i < 2; i++) { if (ori == 0) { if (M[p.first + 1][p.second] > 0) ori++; else { p = {p.first + 1, p.second}; return 1; } } if (ori == 1) { if (M[p.first][p.second + 1] > 0) ori++; else { p = {p.first, p.second + 1}; return 1; } } if (ori == 2) { if (M[p.first - 1][p.second] > 0) ori++; else { p = {p.first - 1, p.second}; return 1; } } if (ori == 3) { if (M[p.first][p.second - 1] > 0) ori = 0; else { p = {p.first, p.second - 1}; return 1; } } } return 0; } void f(pair<int, int> l, pair<int, int> r, int oril, int orir) { L.push(l); if (l != r) R.push(r); else return; M[l.first][l.second] = 1; M[r.first][r.second] = 2; if (play(l, oril) == 0) return; if (play(r, orir) == 0) return; f(l, r, oril, orir); } int main() { scanf( %d%d , &n, &m); M = new int *[n + 2]; for (int i = 0; i < n + 2; i++) { M[i] = new int[m + 2]; for (int j = 0; j < m + 2; j++) M[i][j] = 0; } for (int i = 0; i < n + 2; i++) M[i][0] = M[i][m + 1] = 1; for (int i = 0; i < m + 2; i++) M[0][i] = M[n + 1][i] = 1; f({1, 1}, {n, m}, 0, 2); while (!L.empty()) { printf( %d %d n , L.front().first, L.front().second); L.pop(); if (!R.empty()) { printf( %d %d n , R.front().first, R.front().second); R.pop(); } } }
|
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int MAX = 1000007; int n; long long a, b; vector<int> primes(int x) { vector<int> p; for (int i = 2; i * i <= x; ++i) if (x % i == 0) { p.push_back(i); while (x % i == 0) { x /= i; } } if (x != 1) p.push_back(x); return p; } long long dp[MAX][3]; long long solve(vector<int> c) { vector<int> p = primes(c[0]); vector<int> p1 = primes(c[0] - 1); for (int i = (0); i < (p1.size()); i++) p.push_back(p1[i]); p1 = primes(c[0] + 1); for (int i = (0); i < (p1.size()); i++) p.push_back(p1[i]); p1 = primes(c.back()); for (int i = (0); i < (p1.size()); i++) p.push_back(p1[i]); p1 = primes(c.back() + 1); for (int i = (0); i < (p1.size()); i++) p.push_back(p1[i]); p1 = primes(c.back() - 1); for (int i = (0); i < (p1.size()); i++) p.push_back(p1[i]); sort(p.begin(), p.end()); p.resize(unique(p.begin(), p.end()) - p.begin()); long long res = 1LL * INF * INF; for (int t = (0); t < (p.size()); t++) { int pr = p[t]; dp[0][0] = dp[0][1] = dp[0][2] = 0; for (int i = (0); i < (n); i++) { int val = min(c[i] % pr, pr - c[i] % pr); dp[i + 1][0] = dp[i + 1][1] = dp[i + 1][2] = 1LL * INF * INF; if (val <= 1) { dp[i + 1][2] = min(dp[i][2] + a * val, min(dp[i][1] + a * val, dp[i][0] + a * val)); } dp[i + 1][1] = min(dp[i][0], dp[i][1]) + b; if (val <= 1) { dp[i + 1][0] = dp[i][0] + a * val; } } long long r = min(dp[n][2], min(dp[n][1], dp[n][0])); res = min(res, r); } return res; } int main() { cin >> n >> a >> b; swap(a, b); vector<int> c(n); for (int i = (0); i < (n); i++) { scanf( %d , &c[i]); } long long res = solve(c); cout << res << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { double a, b, c, d, k; cin >> a >> b >> c >> d >> k; double pen = a / c; double pencil = b / d; pen = ceil(pen); pencil = ceil(pencil); if ((pen + pencil) <= k) { double diff = k - pen - pencil; cout << pen + diff << << pencil << n ; } else cout << -1 << n ; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int inpt1[300000], inpt2[300000]; int main() { priority_queue<int> q; int n, k, x, sm; scanf( %d %d , &n, &k); sm = 0; for (int i = 0; i < n; i++) scanf( %d , &inpt1[i]); for (int i = 0; i < n; i++) { scanf( %d , &x); sm += x; inpt2[i] = x - inpt1[i]; q.push(inpt2[i]); } while (!q.empty()) { x = q.top(); if (x < 0) break; q.pop(); sm -= x; --k; } while (k > 0) { k--; x = q.top(); q.pop(); sm -= x; } cout << sm << endl; return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { os << { << p.first << , << p.second << } ; return os; } const int N = 3e5 + 5; const int oo = 1e9 + 7; double s, a, b, c; double func(double x, double y, double z) { return a * log(x) + b * log(y) + c * log(z); } double ans2(double x, double S, double &y) { double l = 1e-9, r = S; for (int i = 0; i < 500; i++) { double l1 = (l * 2 + r) / 3; double l2 = (l + 2 * r) / 3; if (func(x, l1, S - l1) > func(x, l2, S - l2)) r = l2; else l = l1; } y = l; return func(x, l, S - l); } pair<double, pair<double, double> > ans1(double S) { double l = 1e-9, r = S; double y; for (int i = 0; i < 500; i++) { double l1 = (l * 2 + r) / 3; double l2 = (l + 2 * r) / 3; if (ans2(l1, S - l1, y) > ans2(l2, S - l2, y)) r = l2; else l = l1; } ans2(l, S - l, y); return {l, {y, S - l - y}}; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s >> a >> b >> c; auto x = ans1(s); cout << fixed << setprecision(15) << x.first << << x.second.first << << x.second.second << n ; }
|
#include <bits/stdc++.h> using namespace std; long long ar[500005 + 5]; int main() { long long i, j, k, n; cin >> n; if (n <= 2) cout << 1 << endl; else if (n == 3) cout << 2 << endl; else { long long lo = 1LL, hi = n, ans = 1LL; while (lo <= hi) { long long md = (lo + hi) / 2LL; if (md * 3LL <= n) { ans = max(ans, md); lo = md + 1LL; } else hi = md - 1LL; } if (ans * 3 + 1 <= n) { cout << (ans * 2) + 1 << endl; } else cout << ans * 2 << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int A[n + 1]; A[0] = 0; for (int i = 1; i < n + 1; i++) { cin >> A[i]; } int dollar = A[1]; int cou = 0; for (int i = 1; i < n; i++) { cou = cou + A[i] - A[i + 1]; if (cou < 0) { dollar = dollar + abs(cou); cou = 0; } } cout << dollar; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_PP_SYMBOL_V
|
//#############################################################################
//# Function: Generic counter #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_counter #(parameter DW = 32 // width of data inputs
)
(
//inputs
input clk, // clk input
input in, // input to count
input en, // enable counter
input dir,//0=increment, 1=decrement
input autowrap, //auto wrap around
input load, // load counter
input [DW-1:0] load_data, // input data to load
//outputs
output [DW-1:0] count, // count value
output wraparound // wraparound indicator
);
// local variables
reg [DW-1:0] count;
wire [DW-1:0] count_in;
//Select count direction
assign count_in[DW-1:0] = dir ? count[DW-1:0] - in :
count[DW-1:0] + in ;
// counter
always @(posedge clk)
if(load)
count[DW-1:0] <= load_data[DW-1:0];
else if (en & ~(wraparound & ~autowrap))
count[DW-1:0] <= count_in[DW-1:0];
// counter expired
assign wraparound = (dir & en & ~(|count[DW-1:0])) |
(~dir & en & (&count[DW-1:0]));
endmodule // oh_counter
|
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
TODO
TEST PROCEDURE:
TODO
*/
module Count12(dout);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P20" *)
output wire dout;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Oscillators
//The 25 kHz RC oscillator
wire clk_6khz_cnt; //dedicated output to hard IP only
wire clk_6khz; //general fabric output
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("25k"),
.HARDIP_DIV(4),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_6khz_cnt),
.CLKOUT_FABRIC(clk_6khz)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// A counter with a pre-divider of 12
GP_COUNT8 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(32),
.CLKIN_DIVIDE(12)
) cnt (
.CLK(clk_6khz_cnt),
.RST(1'b0),
.OUT(dout)
);
endmodule
|
`timescale 1 ns / 1 ps
module gpio_debouncer #
(
parameter integer DATA_WIDTH = 8,
parameter integer CNTR_WIDTH = 22
)
(
input wire aclk,
inout wire [DATA_WIDTH-1:0] gpio_data,
output wire [DATA_WIDTH-1:0] deb_data,
output wire [DATA_WIDTH-1:0] raw_data
);
reg [DATA_WIDTH-1:0] int_data_reg [2:0];
reg [CNTR_WIDTH-1:0] int_cntr_reg [DATA_WIDTH-1:0];
wire [DATA_WIDTH-1:0] int_data_wire;
genvar j;
generate
for(j = 0; j < DATA_WIDTH; j = j + 1)
begin : GPIO
IOBUF gpio_iobuf (.O(int_data_wire[j]), .IO(gpio_data[j]), .I(1'b0), .T(1'b1));
always @(posedge aclk)
begin
if(int_data_reg[2][j] == int_data_reg[1][j])
begin
int_cntr_reg[j] <= {(CNTR_WIDTH){1'b0}};
end
else
begin
int_cntr_reg[j] <= int_cntr_reg[j] + 1'b1;
if(&int_cntr_reg[j]) int_data_reg[2][j] <= ~int_data_reg[2][j];
end
end
end
endgenerate
always @(posedge aclk)
begin
int_data_reg[0] <= int_data_wire;
int_data_reg[1] <= int_data_reg[0];
end
assign deb_data = int_data_reg[2];
assign raw_data = int_data_reg[1];
endmodule
|
#include <bits/stdc++.h> std::mt19937 rnd(time(0)); const int N = 200005; int n, m, a[N], c[N]; int v; int ans; int p[N << 1]; void updAns(int x) { if (v == x) { return; } for (int i = 0; i <= 2 * n; ++i) { p[i] = -1; } int now = n; p[now] = 0; for (int i = 1; i <= n; ++i) { if (a[i] == v) { ++now; } else if (a[i] == x) { --now; } if (p[now] == -1) { p[now] = i; } else { ans = std::max(ans, i - p[now]); } } } int wnext(int i, int t) { if (t == 0) { return rnd() % i; } else if (t < 0) { return std::min<int>(rnd() % i, wnext(i, t + 1)); } else { return std::max<int>(rnd() % i, wnext(i, t - 1)); } } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); std::cin >> n; for (int i = 1; i <= n; ++i) { std::cin >> a[i]; ++c[a[i]]; m = std::max(m, a[i]); } std::vector<std::pair<int, int>> val; v = 0; for (int i = 1; i <= m; ++i) { if (!v || c[i] > c[v]) { v = i; } if (c[i]) { val.push_back({c[i], i}); } } std::sort(val.begin(), val.end()); std::reverse(val.begin(), val.end()); const int B = 200; for (int i = 0; i < B && i < (int)val.size(); ++i) { updAns(val[i].second); } if ((int)val.size() > B) { for (int i = 0; i < B; ++i) { int x = wnext(val.size() - B, 0) + B; updAns(val[x].second); } } std::cout << ans << n ; }
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// This module takes the settings bus on one clock domain and crosses it over to another domain
// Typically it will be used with the input settings bus on the wishbone clock, and either
// the system or dsp clock on the output side
module settings_bus_crossclock
#(parameter FLOW_CTRL=0)
(input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
wire full, empty;
fifo_xlnx_16x40_2clk settings_fifo
(.rst(rst_i),
.wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
.rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
endmodule // settings_bus_crossclock
|
/*
* Copyright (c) 1998-2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
parameter PARM08 = 8;
parameter PARM04 = PARM08 >> 1;
parameter PARM16 = PARM08 << 1;
parameter PARM10 = ((PARM08 <=2) ? 1:
((PARM08 <=4) ? 2:
((PARM08 <=8) ? 3:4)));
// this parameterized input compiles ok
wire [PARM04 : 0] in04;
wire [PARM16 : 0] in05;
reg [PARM08 : 0] out00;
reg [PARM04 : 0] out04;
reg [PARM16 : 0] out05;
// this parameterized doesn't compile, stack dump
wire [PARM10:0] in99;
initial begin
if (PARM08 !== 8) begin
$display("FAILED -- PARM08 == %b", PARM08);
$finish;
end
if (PARM04 !== 4) begin
$display("FAILED -- PARM04 == %b", PARM04);
$finish;
end
if (PARM16 !== 16) begin
$display("FAILED -- PARM16 == %b", PARM16);
$finish;
end
if (PARM10 !== 3) begin
$display("FAILED -- PARM10 == %b", PARM10);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; int i, j; cin >> n >> k; int arr[n]; for (i = 0; i < n; i++) cin >> arr[i]; int one, two; int m = 0; for (i = 0; i < k; i++) { one = 0, two = 0; for (j = i; j < n; j = j + k) { if (arr[j] == 1) one++; else two++; } m = m + min(one, two); } cout << m << endl; }
|
`default_nettype none
`include "common.h"
module execute_debugger(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Debugger Port
input wire iDEBUG_CTRL_REQ,
input wire iDEBUG_CTRL_STOP,
input wire iDEBUG_CTRL_START,
output wire oDEBUG_CTRL_ACK,
output wire [31:0] oDEBUG_REG_OUT_FLAGR,
//Pipeline
output wire oPIPELINE_STOP,
//Registers
input wire [4:0] iREGISTER_FLAGR,
//Busy
input wire iBUSY
);
localparam L_PARAM_DEBUG_IDLE = 2'h0;
localparam L_PARAM_DEBUG_START_REQ = 2'h1;
localparam L_PARAM_DEBUG_STOP_REQ = 2'h2;
//Debugger
reg [1:0] b_debug_state;
reg b_debug_stop;
reg b_debug_cmd_ack;
//Debug Module Enable
`ifdef MIST1032ISA_STANDARD_DEBUGGER
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_debug_state <= L_PARAM_DEBUG_IDLE;
b_debug_stop <= 1'b0;
b_debug_cmd_ack <= 1'b0;
end
else if(iRESET_SYNC)begin
b_debug_state <= L_PARAM_DEBUG_IDLE;
b_debug_stop <= 1'b0;
b_debug_cmd_ack <= 1'b0;
end
else begin
case(b_debug_state)
L_PARAM_DEBUG_IDLE:
begin
b_debug_cmd_ack <= 1'b0;
if(iDEBUG_CTRL_REQ && iDEBUG_CTRL_STOP)begin
b_debug_state <= L_PARAM_DEBUG_START_REQ;
end
else if(iDEBUG_CTRL_REQ && iDEBUG_CTRL_START)begin
b_debug_state <= L_PARAM_DEBUG_STOP_REQ;
end
end
L_PARAM_DEBUG_START_REQ:
begin
b_debug_stop <= 1'b0;
b_debug_cmd_ack <= 1'b1;
b_debug_state <= L_PARAM_DEBUG_IDLE;
end
L_PARAM_DEBUG_STOP_REQ:
begin
if(!iBUSY)begin
b_debug_stop <= 1'b1;
b_debug_cmd_ack <= 1'b1;
b_debug_state <= L_PARAM_DEBUG_IDLE;
end
end
endcase
end
end
`else
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_debug_state <= L_PARAM_DEBUG_IDLE;
b_debug_stop <= 1'b0;
b_debug_cmd_ack <= 1'b0;
end
else if(iRESET_SYNC)begin
b_debug_state <= L_PARAM_DEBUG_IDLE;
b_debug_stop <= 1'b0;
b_debug_cmd_ack <= 1'b0;
end
else begin
b_debug_state <= b_debug_state;
b_debug_stop <= b_debug_stop;
b_debug_cmd_ack <= b_debug_cmd_ack;
end
end
`endif
//Debug Module Enable
`ifdef MIST1032ISA_STANDARD_DEBUGGER
assign oDEBUG_CTRL_ACK = b_debug_cmd_ack;
assign oDEBUG_REG_OUT_FLAGR = {27'h0, iREGISTER_FLAGR};
`else
//Disable
assign oDEBUG_CTRL_ACK = 32'h0;
assign oDEBUG_REG_OUT_FLAGR = 32'h0;
`endif
assign oPIPELINE_STOP = b_debug_stop;
endmodule // execute_debugger
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_bottom_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ctu_bottom_rptr(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; int o = 0, t = 0, to = 0; int n = s.length(); for (int i = 0; i < n; i++) { if (s.substr(i, 3) == one ) { o++; i++; } else if (s.substr(i, 5) == twone ) { to++; i += 3; } else if (s.substr(i, 3) == two ) { t++; i++; } } cout << to + o + t << endl; for (int i = 0; i < n; i++) { if (s.substr(i, 3) == one ) { cout << i + 2 << ; i++; } else if (s.substr(i, 5) == twone ) { cout << i + 3 << ; i += 3; } else if (s.substr(i, 3) == two ) { cout << i + 2 << ; i++; } } cout << endl; } }
|
#include <bits/stdc++.h> using namespace std; int t, n, a[5], ans[5], f1[19491001], cxk, f2[19491001]; int mod1 = 19260817, mod2 = 233317; string s; inline int Read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + ch - 0 ; ch = getchar(); } return x * f; } void Write(int x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) Write(x / 10); putchar(x % 10 + 0 ); } inline int HAsh1() { long long last = 0; for (int i = 1; i <= 4; ++i) { last = last * 13331 + a[i]; last %= mod1; } return last; } inline int HAsh2() { long long last = 0; for (int i = 1; i <= 4; ++i) { last = last * 13331 + a[i]; last %= mod2; } return last; } void dfs(int k, int now) { if (f1[HAsh1()] && f2[HAsh2()]) return; f1[HAsh1()] = f2[HAsh2()] = 1; if (cxk) return; if (k == n + 1) { int minn = 2147482647; for (register int i = 1; i <= 4; ++i) { if (minn > a[i]) minn = a[i]; } for (register int i = 1; i <= 4; ++i) { if (a[i] == minn) { ans[i] = 1; } } int flag = 1; for (register int i = 1; i <= 4; ++i) if (!ans[i]) flag = 0; if (flag) cxk = 1; return; } if (s[k - 1] == G ) { a[1]++; dfs(k + 1, 1); } else if (s[k - 1] == H ) { a[2]++; dfs(k + 1, 2); } else if (s[k - 1] == R ) { a[3]++; dfs(k + 1, 3); } else if (s[k - 1] == S ) { a[4]++; dfs(k + 1, 4); } else { int minn = 2147482647; for (register int i = 1; i <= 4; ++i) { if (minn > a[i]) minn = a[i]; } for (register int i = 1; i <= 4; ++i) { if (a[i] == minn) { int a1 = a[1], a2 = a[2], a3 = a[3], a4 = a[4]; a[i]++; dfs(k + 1, i); a[1] = a1, a[2] = a2, a[3] = a3, a[4] = a4; } } } } int main() { n = Read(); cin >> s; memset(a, 0, sizeof(a)); memset(ans, 0, sizeof(ans)); memset(f1, 0, sizeof(f1)); memset(f2, 0, sizeof(f2)); cxk = 0; dfs(1, 0); if (ans[1]) puts( Gryffindor ); if (ans[2]) puts( Hufflepuff ); if (ans[3]) puts( Ravenclaw ); if (ans[4]) puts( Slytherin ); putchar( n ); }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; struct Event { int t, L, R, on; Event(int t = 0, int L = 0, int R = 0, int on = 0) : t(t), L(L), R(R), on(on) {} bool operator<(const Event &rh) const { return t < rh.t; } } E[maxn * 2]; int V[maxn * 2], cnt; int Pre[maxn * 2], P[maxn * 2]; long long Ans[maxn]; int ID(int v) { int L = 1, R = cnt; while (L < R) { int mid = (L + R) >> 1; if (V[mid] < v) L = mid + 1; else R = mid; } return L; } int main() { int n, k; cin >> n >> k; for (int i = 1; i <= n; i++) { static int x, y; scanf( %d%d , &x, &y); E[2 * i - 1] = Event(x - k + 1, y, y + k - 1, 1); E[2 * i] = Event(x + 1, y, y + k - 1, -1); V[++cnt] = y; V[++cnt] = y + k; } sort(V + 1, V + 1 + cnt); cnt = unique(V + 1, V + 1 + cnt) - V - 1; sort(E + 1, E + 1 + 2 * n); for (int i = 1; i <= 2 * n; i++) { int id = ID(E[i].L); for (; id < cnt && V[id] <= E[i].R; id++) { Ans[P[id]] += ((long long)(E[i].t - Pre[id])) * (V[id + 1] - V[id]); P[id] += E[i].on; Pre[id] = E[i].t; } } for (int i = 1; i <= n; i++) cout << Ans[i] << (i == n ? n : ); return 0; }
|
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