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// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____21.477______0.000______50.0______336.805____300.388
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (47.250),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (44.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
#include <bits/stdc++.h> using namespace std; long n, s[1 << 10]; vector<long> v[1 << 10]; long spre, slim, found; long trem, tail; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> s[i]; for (int j = 0; j < 666; j++) v[i].push_back(0); } for (int j = 0; j < 666; j++) v[0].push_back(0); for (int i = 1; i <= n; i++) { v[i] = v[i - 1]; spre = s[i - 1]; slim = 0; found = 0; for (int j = 665; j >= 0; --j) { if (found) break; spre -= v[i][j]; for (int q = v[i][j] + 1; q <= 9 && found == 0; q++) { trem = spre + q; tail = s[i] - trem; if (tail >= 0 && tail <= slim) { v[i][j] = q; for (int t = 665; t > j; t--) { if (tail > 9) { v[i][t] = 9; tail -= 9; } else { v[i][t] = tail; tail = 0; } } found = 1; v[i][j] = q; } } slim += 9; } } for (int i = 1; i <= n; i++) { reverse(v[i].begin(), v[i].end()); while (v[i].size() > 1 && v[i].back() == 0) v[i].pop_back(); reverse(v[i].begin(), v[i].end()); for (int j = 0; j < v[i].size(); j++) { cout << v[i][j]; } cout << endl; } cin.get(); cin.get(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e6 + 10; long long a[maxn], sum[maxn], n, m, big = 0, tmp; int main() { scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld , &m); a[m]++; big = max(big, m); } for (int i = 0; i <= big; i++) { for (int j = 0; j <= big; j++) { if ((long long)i * j > maxn - 10) break; sum[i * j] += a[i] * a[j]; if (i == j) sum[i * j] -= a[i]; } } for (int i = 1; i < maxn; i++) sum[i] += sum[i - 1]; scanf( %lld , &m); for (int i = 0; i < m; i++) { scanf( %lld , &tmp); printf( %lld n , n * (n - 1) - sum[tmp - 1]); } }
|
//datae:2016/3/20
//engineer:zhaoshaomin
//module name: return address stack which is used to predict indirect branch target ,
// in MIPS such as JR or JALR(which i didn't implemente)
module core_ras(//input
clk,
rst,
//inst fetch stage prediction
en_call_in, //in my previous version ,it equals en_ret_addr_in
en_ret_in,//in my previous version ,it equals en_ret_addr_out
ret_addr_in,// which is gened by call inst
// decode stage recover something wrong,which caused by misprediction in btb, in RAS.
recover_push,//previous inst was preded as a JR inst incorrectly.
recover_push_addr,//push back the top return addr to RAs
recover_pop,// previous inst was preded as a jal inst incorrectly.
////output
//inst fetch stage poping top addr
ret_addr_out
);
//parameter
parameter ps2=2'b00;
parameter ps1=2'b01;
parameter pp1=2'b10;
parameter pp2=2'b11;
//input
input clk;
input rst;
input en_call_in;
input en_ret_in;
input [29:0] ret_addr_in;
input recover_push;
input [29:0] recover_push_addr;
input recover_pop;
//output
output [31:0] ret_addr_out;
reg en_RAS_ret;
reg en_RAS_rec;
reg en_pointer;
reg [1:0] ret_addr_out_src;
//reg of RAS
reg [29:0] RAS_1;
reg [29:0] RAS_2;
reg [29:0] RAS_3;
reg [29:0] RAS_4;
reg [29:0] RAS_5;
reg [29:0] RAS_6;
reg [29:0] RAS_7;
reg [29:0] RAS_8;
reg [2:0] pointer;
reg [1:0] pointer_src;
always@(posedge clk)
begin
if(rst)
pointer<=3'b000;
else if(en_pointer&&(pointer_src==ps2))
pointer<=pointer-3'b010;
else if(en_pointer&&(pointer_src==ps1))
pointer<=pointer-3'b001;
else if(en_pointer&&(pointer_src==pp1))
pointer<=pointer+3'b001;
else if(en_pointer&&(pointer_src==pp2))
pointer<=pointer+3'b010;
end
// reg of en vector
reg [7:0] en_pointer_P0;
reg [7:0] en_pointer_P1;
reg [7:0] en_pointer_P2;
//en vector functions
always@(*)
begin
//en_pointer_p0 means enable of pinter
case(pointer)
3'b000:en_pointer_P0=8'b00000001;
3'b001:en_pointer_P0=8'b00000010;
3'b010:en_pointer_P0=8'b00000100;
3'b011:en_pointer_P0=8'b00001000;
3'b100:en_pointer_P0=8'b00010000;
3'b101:en_pointer_P0=8'b00100000;
3'b110:en_pointer_P0=8'b01000000;
3'b111:en_pointer_P0=8'b10000000;
default:en_pointer_P0=8'b00000000;
endcase
//en_pointer_p1 means enable of pinter+1
case(pointer)
3'b111:en_pointer_P1=8'b00000001;
3'b000:en_pointer_P1=8'b00000010;
3'b001:en_pointer_P1=8'b00000100;
3'b010:en_pointer_P1=8'b00001000;
3'b011:en_pointer_P1=8'b00010000;
3'b100:en_pointer_P1=8'b00100000;
3'b101:en_pointer_P1=8'b01000000;
3'b110:en_pointer_P1=8'b10000000;
default:en_pointer_P1=8'b00000000;
endcase
//en_pointer_p2 means enable of pinter+2
case(pointer)
3'b111:en_pointer_P2=8'b00000010;
3'b000:en_pointer_P2=8'b00000100;
3'b001:en_pointer_P2=8'b00001000;
3'b010:en_pointer_P2=8'b00010000;
3'b011:en_pointer_P2=8'b00100000;
3'b100:en_pointer_P2=8'b01000000;
3'b101:en_pointer_P2=8'b10000000;
3'b110:en_pointer_P2=8'b00000001;
default:en_pointer_P2=8'b00000000;
endcase
end
//control signals for RAS
//reg of en_RAS_ret and en_RAS_rec
always@(*)
begin
//default values
en_RAS_ret=1'b0;
en_RAS_rec=1'b0;
pointer_src=pp2;
en_pointer=1'b0;
ret_addr_out_src=2'b11;
//////////////////////////////////
// when call_in meets recover_push
if(en_call_in&&recover_push)
begin
en_RAS_ret=1'b1;
en_RAS_rec=1'b1;
pointer_src=pp2;
en_pointer=1'b1;
end
else if(en_call_in&&!recover_push&&!recover_pop) //i'm not sure there is nothing wrong
begin
en_RAS_ret=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_push)
begin
en_RAS_rec=1'b1;
pointer_src=pp1;
en_pointer=1'b1;
end
///////////////////////////////////
//when ret_in meets recover_push
if(en_ret_in&&recover_push)
begin
ret_addr_out_src=2'b00;
end
else if(en_ret_in&&!recover_push&&!recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
ret_addr_out_src=2'b10;
end
////////////////////////////////////
///when call_in meets recover_pop
if(en_call_in&&recover_pop)
begin
en_RAS_ret=1'b1;
end
else if(!en_ret_in&&!en_call_in&&recover_pop)
begin
pointer_src=ps1;
en_pointer=1'b1;
end
////////////////////////////////////
//when ret_in meets recover_pop
if(en_ret_in&&recover_pop)
begin
ret_addr_out_src=2'b01;
pointer_src=ps2;
en_pointer=1'b1;
end
end
///////////////////////////////////
//write RAS_num
//RAS_1
always@(posedge clk)
begin
if(rst)
RAS_1<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[0]||en_pointer_P1[0]||en_pointer_P2[0]))
RAS_1<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[0]||en_pointer_P1[0]))
RAS_1<=recover_push_addr;
end
//RAS_2
always@(posedge clk)
begin
if(rst)
RAS_2<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[1]||en_pointer_P1[1]||en_pointer_P2[1]))
RAS_2<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[1]||en_pointer_P1[1]))
RAS_2<=recover_push_addr;
end
//RAS_3
always@(posedge clk)
begin
if(rst)
RAS_3<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[2]||en_pointer_P1[2]||en_pointer_P2[2]))
RAS_3<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[2]||en_pointer_P1[2]))
RAS_3<=recover_push_addr;
end
//RAS_4
always@(posedge clk)
begin
if(rst)
RAS_4<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[3]||en_pointer_P1[3]||en_pointer_P2[3]))
RAS_4<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[3]||en_pointer_P1[3]))
RAS_4<=recover_push_addr;
end
//RAS_5
always@(posedge clk)
begin
if(rst)
RAS_5<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[4]||en_pointer_P1[4]||en_pointer_P2[4]))
RAS_5<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[4]||en_pointer_P1[4]))
RAS_5<=recover_push_addr;
end
//RAS_6
always@(posedge clk)
begin
if(rst)
RAS_6<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[5]||en_pointer_P1[5]||en_pointer_P2[5]))
RAS_6<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[5]||en_pointer_P1[5]))
RAS_6<=recover_push_addr;
end
//RAS_7
always@(posedge clk)
begin
if(rst)
RAS_7<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[6]||en_pointer_P1[6]||en_pointer_P2[6]))
RAS_7<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[6]||en_pointer_P1[6]))
RAS_7<=recover_push_addr;
end
//RAS_8
always@(posedge clk)
begin
if(rst)
RAS_8<=30'h00000000;
else if(en_RAS_ret&&(en_pointer_P0[7]||en_pointer_P1[7]||en_pointer_P2[7]))
RAS_8<=ret_addr_in;
else if(en_RAS_rec&&(en_pointer_P2[7]||en_pointer_P1[7]))
RAS_8<=recover_push_addr;
end
//read RAS port of pointer
reg [29:0] pointer_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointer_rd_ras=RAS_1;
3'b001:pointer_rd_ras=RAS_2;
3'b010:pointer_rd_ras=RAS_3;
3'b011:pointer_rd_ras=RAS_4;
3'b100:pointer_rd_ras=RAS_5;
3'b101:pointer_rd_ras=RAS_6;
3'b110:pointer_rd_ras=RAS_7;
3'b111:pointer_rd_ras=RAS_8;
default:pointer_rd_ras=30'hzzzzzzzz;
endcase
end
//read RAS port of pointere+1
reg [29:0] pointerP1_rd_ras;
always@(*)
begin
case(pointer)
3'b000:pointerP1_rd_ras=RAS_2;
3'b001:pointerP1_rd_ras=RAS_3;
3'b010:pointerP1_rd_ras=RAS_4;
3'b011:pointerP1_rd_ras=RAS_5;
3'b100:pointerP1_rd_ras=RAS_6;
3'b101:pointerP1_rd_ras=RAS_7;
3'b110:pointerP1_rd_ras=RAS_8;
3'b111:pointerP1_rd_ras=RAS_1;
default:pointerP1_rd_ras=30'hzzzzzzzz;
endcase
end
wire [29:0] ret_addr_out_temp;
assign ret_addr_out_temp=(ret_addr_out_src==2'b00)?recover_push_addr:
(ret_addr_out_src==2'b01)?pointer_rd_ras:
(ret_addr_out_src==2'b10)?pointerP1_rd_ras:30'hzzzzzzzz;
assign ret_addr_out={ret_addr_out_temp,2'b00};
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_mux_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_0_axis_tdata = 0;
reg input_0_axis_tvalid = 0;
reg input_0_axis_tlast = 0;
reg input_0_axis_tuser = 0;
reg [7:0] input_1_axis_tdata = 0;
reg input_1_axis_tvalid = 0;
reg input_1_axis_tlast = 0;
reg input_1_axis_tuser = 0;
reg [7:0] input_2_axis_tdata = 0;
reg input_2_axis_tvalid = 0;
reg input_2_axis_tlast = 0;
reg input_2_axis_tuser = 0;
reg [7:0] input_3_axis_tdata = 0;
reg input_3_axis_tvalid = 0;
reg input_3_axis_tlast = 0;
reg input_3_axis_tuser = 0;
reg output_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire input_0_axis_tready;
wire input_1_axis_tready;
wire input_2_axis_tready;
wire input_3_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_0_axis_tdata,
input_0_axis_tvalid,
input_0_axis_tlast,
input_0_axis_tuser,
input_1_axis_tdata,
input_1_axis_tvalid,
input_1_axis_tlast,
input_1_axis_tuser,
input_2_axis_tdata,
input_2_axis_tvalid,
input_2_axis_tlast,
input_2_axis_tuser,
input_3_axis_tdata,
input_3_axis_tvalid,
input_3_axis_tlast,
input_3_axis_tuser,
output_axis_tready,
enable,
select);
$to_myhdl(input_0_axis_tready,
input_1_axis_tready,
input_2_axis_tready,
input_3_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_mux_4.lxt");
$dumpvars(0, test_axis_mux_4);
end
axis_mux_4 #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.input_0_axis_tdata(input_0_axis_tdata),
.input_0_axis_tvalid(input_0_axis_tvalid),
.input_0_axis_tready(input_0_axis_tready),
.input_0_axis_tlast(input_0_axis_tlast),
.input_0_axis_tuser(input_0_axis_tuser),
.input_1_axis_tdata(input_1_axis_tdata),
.input_1_axis_tvalid(input_1_axis_tvalid),
.input_1_axis_tready(input_1_axis_tready),
.input_1_axis_tlast(input_1_axis_tlast),
.input_1_axis_tuser(input_1_axis_tuser),
.input_2_axis_tdata(input_2_axis_tdata),
.input_2_axis_tvalid(input_2_axis_tvalid),
.input_2_axis_tready(input_2_axis_tready),
.input_2_axis_tlast(input_2_axis_tlast),
.input_2_axis_tuser(input_2_axis_tuser),
.input_3_axis_tdata(input_3_axis_tdata),
.input_3_axis_tvalid(input_3_axis_tvalid),
.input_3_axis_tready(input_3_axis_tready),
.input_3_axis_tlast(input_3_axis_tlast),
.input_3_axis_tuser(input_3_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<long long, long long> a[1000005]; bool fl1, fl2, fl3, fl4; long long dist(pair<long long, long long> a, pair<long long, long long> b) { return abs(a.first - b.first) + abs(a.second - b.second); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long i, j, k, l, m, n, t, r, cnt; long long flag = 0; long long an = 0, ans = 0; t = 1; while (t--) { cin >> n; long long x, y; for (i = 0; i < n; i++) { cin >> x >> y; a[i] = make_pair(x, y); } long long xmi, xma, yma, ymi; xmi = 1LL * 1e18; ymi = 1LL * 1e18; yma = -1LL * 1e18; xma = -1LL * 1e18; for (i = 0; i < n; i++) { xmi = min(xmi, a[i].first); xma = max(xma, a[i].first); ymi = min(ymi, a[i].second); yma = max(yma, a[i].second); } ans = 2LL * (xma - xmi + yma - ymi); vector<pair<long long, long long> > b; for (i = 0; i < n; i++) { if (a[i].first == xmi && !fl1) { fl1 = true; b.push_back(a[i]); } if (a[i].first == xma && !fl2) { fl2 = true; b.push_back(a[i]); } if (a[i].second == ymi && !fl3) { fl3 = true; b.push_back(a[i]); } if (a[i].second == yma && !fl4) { fl4 = true; b.push_back(a[i]); } } b.push_back(make_pair(xmi, ymi)); b.push_back(make_pair(xmi, yma)); b.push_back(make_pair(xma, yma)); b.push_back(make_pair(xma, ymi)); an = -1LL * 1e18; for (i = 0; i < n; i++) { for (j = 0; j < 4; j++) { for (k = 0; k < 4; k++) { if (b[j] == a[i] || b[k] == a[i]) continue; an = max(an, dist(a[i], b[j]) + dist(b[k], a[i]) + dist(b[j], b[k])); } } } cout << an << ; for (i = 4; i <= n; i++) { cout << ans << ; } cout << endl; } }
|
`define GLBL
module prbs_gen (
input ck,
input rst,
input i_req,
output o_rdy,
output o_vld,
output [63:0] o_res_lower,
output [63:0] o_res_upper
);
reg r_init_active;
reg [6:0] r_init_cnt;
reg r_init_done;
always @(posedge ck) begin
if (rst) begin
r_init_active <= 1'b0;
r_init_done <= 1'b0;
end
else if (r_init_cnt == 7'h7f) begin
r_init_active <= 1'b0;
r_init_done <= 1'b1;
end
else begin
r_init_active <= 1'b1;
r_init_done <= 1'b0;
end
end
always @(posedge ck) begin
if (rst) begin
r_init_cnt <= 7'b0;
end
else if (r_init_active && r_init_cnt != 7'h7f) begin
r_init_cnt <= r_init_cnt + 1;
end
else begin
r_init_cnt <= r_init_cnt;
end
end
reg [127:0] r_seed;
always @(posedge ck) begin
if (rst) begin
r_seed <= 128'h0123456789ABCDEFFEDCBA9876543210;
end
else if (r_init_active) begin
r_seed <= {r_seed[126:0], r_seed[127]};
end
else begin
r_seed <= r_seed;
end
end
assign o_rdy = r_init_done;
wire [127:0] r_vld, r_res;
genvar i;
generate for (i=0; i<128; i=i+1) begin : g0
wire init_vld = r_init_active && (r_init_cnt == i);
prbs_lfsr_tx prbs_lfsr_tx (
.ck(ck),
.i_init(init_vld),
.i_init_clk(r_init_active),
.i_seed(r_seed[127:96]),
.i_req(i_req),
.o_vld(r_vld[i]),
.o_res(r_res[i])
);
end endgenerate
// Cheat and just use valid from 0...they are always valid at the same time
assign o_vld = r_vld[0];
assign o_res_lower = r_res[63:0];
assign o_res_upper = r_res[127:64];
endmodule
module prbs_lfsr_tx (
input ck,
input i_init,
input i_init_clk,
input [31:0] i_seed,
input i_req,
output o_vld,
output o_res
);
reg [31:0] r_lfsr;
wire c_xor_in = r_lfsr[31] ^ r_lfsr[21] ^ r_lfsr[1] ^ r_lfsr[0];
always @(posedge ck) begin
if (i_init) begin
r_lfsr <= i_seed;
end
else if (i_req | i_init_clk) begin
r_lfsr <= {r_lfsr[30:0], c_xor_in};
end
else begin
r_lfsr <= r_lfsr;
end
end
reg r_t2_vld;
reg r_t2_res;
always @(posedge ck) begin
r_t2_vld <= i_req;
r_t2_res <= r_lfsr[31];
end
assign o_vld = r_t2_vld;
assign o_res = r_t2_res;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:13:47 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_3_stub.v
// Design : zqynq_lab_1_design_auto_pc_3
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const int maxn = 21; const int dx[4] = {0, 0, 1, -1}; const int dy[4] = {1, -1, 0, 0}; int Map[maxn][maxn], Value[maxn], X[maxn], Y[maxn], XX[maxn], YY[maxn]; int vis[maxn][maxn][260][129], VV[maxn][maxn][260][129], inq[maxn][maxn][260][129]; int ans, num, N, M, D; const int Maxn = 3020120; char s[30]; struct Point { int x, y, z, value, num; } Q[Maxn]; void BFS(int sx, int sy) { int x, y, z, V, u, v, w, NOW, value, NNN, head, tail; Q[head = tail = 1] = (Point){sx, sy, 0, 0, 0}; memset(vis, 0, sizeof(vis)); vis[sx][sy][0][0] = 1; while (head <= tail) { x = Q[head].x; y = Q[head].y; z = Q[head].z; V = Q[head].value; NOW = Q[head].num; inq[x][y][z][V] = 0; ++head; V--; for (int i = 0; i < 4; i++) { u = x + dx[i], v = y + dy[i], w = z, value = V, NNN = NOW; if (!u || !v || u > N || v > M) continue; if (!Map[u][v]) continue; for (int k = 1; k <= D; k++) if (u == X[k] && v > Y[k] && x == X[k] + 1 || u == X[k] + 1 && v > Y[k] && x == X[k]) { w = w ^ (1 << k - 1); if (w & (1 << k - 1)) value += Value[k]; else value -= Value[k]; } for (int k = 1; k <= num; k++) { if (u == XX[k] && v > YY[k] && x == XX[k] + 1) NNN = NNN ^ (1 << k - 1); if (u == XX[k] + 1 && v > YY[k] && x == XX[k]) NNN = NNN ^ (1 << k - 1); } if (NNN == 1) NNN = 1; if (value > VV[u][v][w][NNN]) VV[u][v][w][NNN] = value; else continue; if (!vis[u][v][w][NNN]) Q[++tail] = (Point){u, v, w, value, NNN}; else continue; if (u == sx && v == sy && value > ans && NNN == 0) ans = max(ans, value); inq[u][v][w][NNN] = 1; } } } int main() { cin >> N >> M; memset(VV, 235, sizeof(VV)); for (int i = 1; i <= N; i++) { scanf( %s , s + 1); for (int j = 1; j <= M; j++) { if (s[j] > 0 && s[j] != # && s[j] != . && s[j] != S && s[j] != B ) X[s[j] - 48] = i, Y[s[j] - 48] = j, D = max(D, s[j] - 48); if (s[j] == . ) Map[i][j] = 1; if (s[j] == S ) Map[i][j] = 2; if (s[j] == B ) { XX[++num] = i; YY[num] = j; } } } for (int i = 1; i <= D; i++) scanf( %d , &Value[i]); for (int i = 1; i <= N; i++) for (int j = 1; j <= M; j++) if (Map[i][j] == 2) BFS(i, j); cout << ans; return 0; }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : alt_mem_ddrx_mm_st_converter
//
// File : alt_mem_ddrx_mm_st_converter.v
//
// Abstract : take in Avalon MM interface and convert it to single cmd and
// multiple data Avalon ST
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_mm_st_converter # (
parameter
AVL_SIZE_WIDTH = 3,
AVL_ADDR_WIDTH = 25,
AVL_DATA_WIDTH = 32,
LOCAL_ID_WIDTH = 8,
CFG_DWIDTH_RATIO = 4,
CFG_MM_ST_CONV_REG = 0
)
(
ctl_clk, // controller clock
ctl_reset_n, // controller reset_n, synchronous to ctl_clk
ctl_half_clk, // controller clock, half-rate
ctl_half_clk_reset_n, // controller reset_n, synchronous to ctl_half_clk
// Avalon data slave interface
avl_ready, // Avalon wait_n
avl_read_req, // Avalon read
avl_write_req, // Avalon write
avl_size, // Avalon burstcount
avl_burstbegin, // Avalon burstbegin
avl_addr, // Avalon address
avl_rdata_valid, // Avalon readdata_valid
avl_rdata, // Avalon readdata
avl_wdata, // Avalon writedata
avl_be, // Avalon byteenble
local_rdata_error, // Avalon readdata_error
local_multicast, // In-band multicast
local_autopch_req, // In-band auto-precharge request signal
local_priority, // In-band priority signal
// cmd channel
itf_cmd_ready,
itf_cmd_valid,
itf_cmd,
itf_cmd_address,
itf_cmd_burstlen,
itf_cmd_id,
itf_cmd_priority,
itf_cmd_autopercharge,
itf_cmd_multicast,
// write data channel
itf_wr_data_ready,
itf_wr_data_valid,
itf_wr_data,
itf_wr_data_byte_en,
itf_wr_data_begin,
itf_wr_data_last,
itf_wr_data_id,
// read data channel
itf_rd_data_ready,
itf_rd_data_valid,
itf_rd_data,
itf_rd_data_error,
itf_rd_data_begin,
itf_rd_data_last,
itf_rd_data_id
);
localparam AVL_BE_WIDTH = AVL_DATA_WIDTH / 8;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output avl_ready;
input avl_read_req;
input avl_write_req;
input [AVL_SIZE_WIDTH-1:0] avl_size;
input avl_burstbegin;
input [AVL_ADDR_WIDTH-1:0] avl_addr;
output avl_rdata_valid;
output [3:0] local_rdata_error;
output [AVL_DATA_WIDTH-1:0] avl_rdata;
input [AVL_DATA_WIDTH-1:0] avl_wdata;
input [AVL_BE_WIDTH-1:0] avl_be;
input local_multicast;
input local_autopch_req;
input local_priority;
input itf_cmd_ready;
output itf_cmd_valid;
output itf_cmd;
output [AVL_ADDR_WIDTH-1:0] itf_cmd_address;
output [AVL_SIZE_WIDTH-1:0] itf_cmd_burstlen;
output [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
output itf_cmd_priority;
output itf_cmd_autopercharge;
output itf_cmd_multicast;
input itf_wr_data_ready;
output itf_wr_data_valid;
output [AVL_DATA_WIDTH-1:0] itf_wr_data;
output [AVL_BE_WIDTH-1:0] itf_wr_data_byte_en;
output itf_wr_data_begin;
output itf_wr_data_last;
output [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
output itf_rd_data_ready;
input itf_rd_data_valid;
input [AVL_DATA_WIDTH-1:0] itf_rd_data;
input itf_rd_data_error;
input itf_rd_data_begin;
input itf_rd_data_last;
input [LOCAL_ID_WIDTH-1:0] itf_rd_data_id;
reg [AVL_SIZE_WIDTH-1:0] burst_count;
wire int_ready;
wire itf_cmd; // high is write
wire itf_wr_if_ready;
wire [LOCAL_ID_WIDTH-1:0] itf_cmd_id;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [LOCAL_ID_WIDTH-1:0] itf_wr_data_id;
reg data_pass;
reg [AVL_SIZE_WIDTH-1:0] burst_counter;
reg avl_read_req_reg;
reg avl_write_req_reg;
reg [AVL_SIZE_WIDTH-1:0] avl_size_reg;
reg avl_burstbegin_reg;
reg [AVL_ADDR_WIDTH-1:0] avl_addr_reg;
reg [AVL_DATA_WIDTH-1:0] avl_wdata_reg;
reg [AVL_DATA_WIDTH/8-1:0] avl_be_reg;
reg itf_rd_data_valid_reg;
reg [AVL_DATA_WIDTH-1:0] itf_rd_data_reg;
reg [3:0] itf_rd_data_error_reg;
reg local_multicast_reg;
reg local_autopch_req_reg;
reg local_priority_reg;
generate
if (CFG_MM_ST_CONV_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
avl_read_req_reg <= 1'b0;
avl_write_req_reg <= 1'b0;
avl_size_reg <= {AVL_SIZE_WIDTH{1'b0}};
avl_burstbegin_reg <= 1'b0;
avl_addr_reg <= {AVL_ADDR_WIDTH{1'b0}};
avl_wdata_reg <= {AVL_DATA_WIDTH{1'b0}};
avl_be_reg <= {AVL_BE_WIDTH{1'b0}};
itf_rd_data_valid_reg <= 1'b0;
itf_rd_data_reg <= {AVL_DATA_WIDTH{1'b0}};
itf_rd_data_error_reg <= 4'b0;
local_multicast_reg <= 1'b0;
local_autopch_req_reg <= 1'b0;
local_priority_reg <= 1'b0;
end else
begin
if (int_ready)
begin
avl_read_req_reg <= avl_read_req;
avl_write_req_reg <= avl_write_req;
avl_size_reg <= avl_size;
avl_burstbegin_reg <= avl_burstbegin;
avl_addr_reg <= avl_addr;
avl_wdata_reg <= avl_wdata;
avl_be_reg <= avl_be;
local_multicast_reg <= local_multicast;
local_autopch_req_reg <= local_autopch_req;
local_priority_reg <= local_priority;
end
itf_rd_data_valid_reg <= itf_rd_data_valid;
itf_rd_data_reg <= itf_rd_data;
itf_rd_data_error_reg <= itf_rd_data_error;
end
end
end else
begin
always @ (*)
begin
avl_read_req_reg = avl_read_req;
avl_write_req_reg = avl_write_req;
avl_size_reg = avl_size;
avl_burstbegin_reg = avl_burstbegin;
avl_addr_reg = avl_addr;
avl_wdata_reg = avl_wdata;
avl_be_reg = avl_be;
itf_rd_data_valid_reg = itf_rd_data_valid;
itf_rd_data_reg = itf_rd_data;
itf_rd_data_error_reg = {4{itf_rd_data_error}};
local_multicast_reg = local_multicast;
local_autopch_req_reg = local_autopch_req;
local_priority_reg = local_priority;
end
end
endgenerate
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when avl_write_req = 1'b1,
// take this write req and then then drive avl_ready until receive # of beats = avl_size?
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
// when cmd_ready = 1'b1, avl_ready = 1'b1;
// when local_ready_req = 1'b1,
// take this read_req
// we will look at cmd_ready, if cmd_ready = 1'b0, avl_ready = 1'b0
assign itf_cmd_valid = avl_read_req_reg | itf_wr_if_ready;
assign itf_wr_if_ready = itf_wr_data_ready & avl_write_req_reg & ~data_pass;
assign avl_ready = int_ready;
assign itf_rd_data_ready = 1'b1;
assign itf_cmd_address = avl_addr_reg ;
assign itf_cmd_burstlen = avl_size_reg ;
assign itf_cmd_autopercharge = local_autopch_req_reg ;
assign itf_cmd_priority = local_priority_reg ;
assign itf_cmd_multicast = local_multicast_reg ;
assign itf_cmd = avl_write_req_reg;
assign itf_cmd_id = {LOCAL_ID_WIDTH{1'b0}};
assign itf_wr_data_begin = 1'b0;
assign itf_wr_data_last = 1'b0;
assign itf_wr_data_id = {LOCAL_ID_WIDTH{1'b0}};
// write data channel
assign itf_wr_data_valid = (data_pass) ? avl_write_req_reg : itf_cmd_ready & avl_write_req_reg;
assign itf_wr_data = avl_wdata_reg ;
assign itf_wr_data_byte_en = avl_be_reg ;
// read data channel
assign avl_rdata_valid = itf_rd_data_valid_reg;
assign avl_rdata = itf_rd_data_reg;
assign local_rdata_error = itf_rd_data_error_reg;
assign int_ready = (data_pass) ? itf_wr_data_ready : ((itf_cmd) ? (itf_wr_data_ready & itf_cmd_ready) : itf_cmd_ready);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
burst_counter <= {AVL_SIZE_WIDTH{1'b0}};
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
burst_counter <= avl_size_reg - 1'b1;
else if (avl_write_req_reg && itf_wr_data_ready)
burst_counter <= burst_counter - 1'b1;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
data_pass <= 1'b0;
else
begin
if (itf_wr_if_ready && avl_size_reg > 1 && itf_cmd_ready)
data_pass <= 1'b1;
else if (burst_counter == 1 && avl_write_req_reg && itf_wr_data_ready)
data_pass <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long cal(long long x) { return (x + 1) * (x + 2) >> 1; } int main() { int a, b, c, l; while (scanf( %d%d%d%d , &a, &b, &c, &l) != EOF) { long long ans = 0; for (int i = 0; i <= l; i++) ans += 1LL * (i + 1) * (i + 2) / 2; for (long long i = 0; i <= l; i++) { if (a + i >= b + c) ans -= cal(min(l - i, a + i - b - c)); if (b + i >= a + c) ans -= cal(min(l - i, b + i - a - c)); if (c + i >= a + b) ans -= cal(min(l - i, c + i - a - b)); } cout << ans << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; int ost(int k, int res) { int ans = 0; while (k < (double)res / 2) { ans++; k *= 2; } return ans; } int main() { int n, k; cin >> n >> k; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); int ans = 0; for (int i = 0; i < n; i++) { if (k < ((double)a[i]) / 2) ans += ost(k, a[i]); k = max(k, a[i]); } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e5 + 5; const long long MOD = 1e9 + 7; const long long INF = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, x, y; cin >> n >> x >> y; set<double> s; int count = 0; while (n--) { double m; double a, b; cin >> a >> b; a -= x; b -= y; if (a != 0) { m = b / a; s.insert(m); } else { count++; } } cout << (count > 0) + s.size() << endl; }
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* sequential detector
*/
// Import the modules that will be tested for in this testbench
`include "seq_detect.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f seq_detector.f +gui
module tb_seq_detect();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the seq_detector
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire error,match_op;
// Declare "reg" signals: inputs to the DUT
reg inp,clock,reset;
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
seq_detect sqd (
// instance_name(signal name),
// Signal name can be the same as the instance name
inp,clock,reset,error,match_op);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/seq_detect.sdf",sqd,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
inp = 1'd0;
reset = 1'd0;
// @ t=10,
#10
inp = 1'd0;
reset = 1'd1;
// @ t=20
#10
inp = 1'd0;
reset = 1'd0;
// @ t=30
#10
inp = 1'd1;
reset = 1'd0;
// @ t=40
#10
inp = 1'd1;
reset = 1'd0;
// @ t=50
#10
inp = 1'dx;
reset = 1'd0;
// @ t=60
#10
inp = 1'd0;
reset = 1'd0;
// @ t=70
#10
inp = 1'dz;
reset = 1'd0;
// @ t=80
#10
inp = 1'd0;
reset = 1'd0;
// @ t=90
#10
inp = 1'd1;
reset = 1'd0;
// @ t=100
#10
inp = 1'd1;
reset = 1'd0;
// @ t=110
#10
inp = 1'd0;
reset = 1'd0;
// @ t=120
#10
inp = 1'd1;
reset = 1'd0;
// @ t=130
#10
// Start of correct sequence
$display($time, " << Start of correct sequence >>");
inp = 1'd1;
reset = 1'd0;
// @ t=140
#10
inp = 1'd0;
reset = 1'd0;
// @ t=150
#10
inp = 1'd0;
reset = 1'd0;
// @ t=160
#10
inp = 1'd1;
reset = 1'd0;
// @ t=170
#10
inp = 1'd1;
reset = 1'd0;
// @ t=180
#10
inp = 1'd0;
reset = 1'd0;
// @ t=190
#10
inp = 1'd1;
reset = 1'd0;
// @ t=200
#10
inp = 1'd1;
reset = 1'd0;
// End of correct sequence
$display($time, " << End of correct sequence >>");
// @ t=210
#10
inp = 1'd1;
reset = 1'd0;
// @ t=220
#10
inp = 1'd1;
reset = 1'd0;
// @ t=230
#10
inp = 1'd0;
reset = 1'd0;
// @ t=240; reset the sequence detector
#10
inp = 1'd1;
reset = 1'd0;
// @ t=250
#10
inp = 1'd0;
reset = 1'd0;
// @ t=260
#10
inp = 1'd1;
reset = 1'd0;
// @ t=270
#10
inp = 1'd1;
reset = 1'd1;
// @ t=280
#10
inp = 1'd0;
reset = 1'd0;
// @ t=290
#10
inp = 1'd1;
reset = 1'd0;
// @ t=300
#10
inp = 1'dx;
reset = 1'd0;
// @ t=310
#10
inp = 1'd1;
reset = 1'd0;
// @ t=320
#10
inp = 1'd0;
reset = 1'd0;
// @ t=330
#10
inp = 1'd1;
reset = 1'd0;
// @ t=340
#10
inp = 1'dx;
reset = 1'd0;
// @ t=350
#10
inp = 1'dx;
reset = 1'd0;
// @ t=360
#10
inp = 1'dz;
reset = 1'd0;
// @ t=370
#10
inp = 1'd0;
reset = 1'd0;
// @ t=380
#10
inp = 1'd1;
reset = 1'd0;
// @ t=390
#10
inp = 1'd0;
reset = 1'd0;
// @ t=400
#10
inp = 1'd1;
reset = 1'd0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_top.v
// Title : Top-level of CPU.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : removed SPI - 04/12/07
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_top (
// ----- Inputs -------
clk_i,
rst_i,
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
at_debug,
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
interrupt,
`endif
// From user logic
`ifdef CFG_USER_ENABLED
user_result,
user_complete,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
`ifdef CFG_EXTERNAL_BREAK_ENABLED
ext_break,
`endif
// Data Wishbone master
D_DAT_I,
D_ACK_I,
D_ERR_I,
D_RTY_I,
// ----- Outputs -------
`ifdef CFG_USER_ENABLED
user_valid,
user_opcode,
user_operand_0,
user_operand_1,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_O,
I_ADR_O,
I_CYC_O,
I_SEL_O,
I_STB_O,
I_WE_O,
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
// Data Wishbone master
D_DAT_O,
D_ADR_O,
D_CYC_O,
D_SEL_O,
D_STB_O,
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
input at_debug; // GPIO input that maps EBA to DEBA
`endif
`endif
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
`endif
`ifdef CFG_USER_ENABLED
input [`LM32_WORD_RNG] user_result; // User-defined instruction result
input user_complete; // Indicates the user-defined instruction result is valid
`endif
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
input I_ACK_I; // Instruction Wishbone interface acknowledgement
input I_ERR_I; // Instruction Wishbone interface error
input I_RTY_I; // Instruction Wishbone interface retry
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
input D_RTY_I; // Data Wishbone interface retry
`ifdef CFG_EXTERNAL_BREAK_ENABLED
input ext_break;
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_USER_ENABLED
output user_valid; // Indicates that user_opcode and user_operand_* are valid
wire user_valid;
output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
reg [`LM32_USER_OPCODE_RNG] user_opcode;
output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_0;
output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_1;
`endif
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
wire [`LM32_WORD_RNG] I_DAT_O;
output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
wire [`LM32_WORD_RNG] I_ADR_O;
output I_CYC_O; // Instruction Wishbone interface cycle
wire I_CYC_O;
output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
output I_STB_O; // Instruction Wishbone interface strobe
wire I_STB_O;
output I_WE_O; // Instruction Wishbone interface write enable
wire I_WE_O;
output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] I_CTI_O;
output I_LOCK_O; // Instruction Wishbone interface lock bus
wire I_LOCK_O;
output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
wire [`LM32_WORD_RNG] D_ADR_O;
output D_CYC_O; // Data Wishbone interface cycle
wire D_CYC_O;
output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
output D_STB_O; // Data Wishbone interface strobe
wire D_STB_O;
output D_WE_O; // Data Wishbone interface write enable
wire D_WE_O;
output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] D_CTI_O;
output D_LOCK_O; // Date Wishbone interface lock bus
wire D_LOCK_O;
output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] D_BTE_O;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
`ifdef CFG_JTAG_ENABLED
// Signals between JTAG interface and CPU
wire [`LM32_BYTE_RNG] jtag_reg_d;
wire [`LM32_BYTE_RNG] jtag_reg_q;
wire jtag_update;
wire [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_q;
wire jtck;
wire jrstn;
`endif
// TODO: get the trace signals out
`ifdef CFG_TRACE_ENABLED
// PC trace signals
wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
wire trace_pc_valid; // Indicates that a new trace PC is valid
wire trace_exception; // Indicates an exception has occured
wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
wire trace_eret; // Indicates an eret instruction has been executed
`ifdef CFG_DEBUG_ENABLED
wire trace_bret; // Indicates a bret instruction has been executed
`endif
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// LM32 CPU
lm32_cpu cpu (
// ----- Inputs -------
.clk_i (clk_i),
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
.clk_n_i (clk_n),
`endif
.rst_i (rst_i),
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
.at_debug (at_debug),
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
.interrupt (interrupt),
`endif
// From user logic
`ifdef CFG_USER_ENABLED
.user_result (user_result),
.user_complete (user_complete),
`endif
`ifdef CFG_JTAG_ENABLED
// From JTAG
.jtag_clk (jtck),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
`endif
`ifdef CFG_EXTERNAL_BREAK_ENABLED
.ext_break (ext_break),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
`endif
// Data Wishbone master
.D_DAT_I (D_DAT_I),
.D_ACK_I (D_ACK_I),
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
// ----- Outputs -------
`ifdef CFG_TRACE_ENABLED
.trace_pc (trace_pc),
.trace_pc_valid (trace_pc_valid),
.trace_exception (trace_exception),
.trace_eid (trace_eid),
.trace_eret (trace_eret),
`ifdef CFG_DEBUG_ENABLED
.trace_bret (trace_bret),
`endif
`endif
`ifdef CFG_JTAG_ENABLED
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d),
`endif
`ifdef CFG_USER_ENABLED
.user_valid (user_valid),
.user_opcode (user_opcode),
.user_operand_0 (user_operand_0),
.user_operand_1 (user_operand_1),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
.I_CYC_O (I_CYC_O),
.I_SEL_O (I_SEL_O),
.I_STB_O (I_STB_O),
.I_WE_O (I_WE_O),
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
`endif
// Data Wishbone master
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
.D_CYC_O (D_CYC_O),
.D_SEL_O (D_SEL_O),
.D_STB_O (D_STB_O),
.D_WE_O (D_WE_O),
.D_CTI_O (D_CTI_O),
.D_LOCK_O (D_LOCK_O),
.D_BTE_O (D_BTE_O)
);
`ifdef CFG_JTAG_ENABLED
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
// ----- Outputs -----
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
.jtck (jtck),
.jrstn (jrstn)
);
`endif
endmodule
|
`include "../module/controller.v"
// Controller testbench: Supplies test vectors and dumps the results to file and
// standard output. Do not modify!
module controller_tb;
reg ph1, ph2, reset;
reg [5:0] opcode;
reg zero;
wire memread;
wire memwrite;
wire [3:0] irwrite;
wire pcen;
wire regwrite;
wire [1:0] aluop;
wire alusrca;
wire [1:0] alusrcb;
wire [1:0] pcsource;
wire iord;
wire memtoreg;
wire regdst;
wire pcwritecond;
wire pcwrite;
// instatiate device under test and connect the signals
controller U0(
// inputs
.ph1 (ph1),
.ph2 (ph2),
.reset (reset),
.op5 (opcode[5]), .op4 (opcode[4]), .op3 (opcode[3]),
.op2 (opcode[2]), .op1 (opcode[1]), .op0 (opcode[0]),
.zero (zero),
// ouputs
.memread (memread),
.memwrite (memwrite),
.irwrite3 (irwrite[3]), .irwrite2 (irwrite[2]),
.irwrite1 (irwrite[1]), .irwrite0 (irwrite[0]),
.pcen (pcen),
.regwrite (regwrite),
.aluop1 (aluop[1]), .aluop0 (aluop[0]),
.alusrca (alusrca),
.alusrcb1 (alusrcb[1]), .alusrcb0 (alusrcb[0]),
.pcsource1 (pcsource[1]), .pcsource0 (pcsource[0]),
.iord (iord),
.memtoreg (memtoreg),
.regdst (regdst));
// initialization (reset is high)
initial
begin
ph1 <= 0;
ph2 <= 0;
reset <= 1;
zero = 0;
end
// generate a two-phase non-overlapping clock (period is 8 units)
always begin
#2 ph1 = 1;
#2 ph1 = 0;
#4 ph1 = 0;
end
always begin
#6 ph2 = 1;
#2 ph2 = 0;
end
// dump all the signals info file. use with a waveform viewer to see the signals
initial begin
$dumpfile("controller.vcd");
$dumpvars;
end
initial begin
// bring out of reset and supply the first opcode lb
#2 reset = 0; opcode = 6'b100000;
$display("%s %s %s %s %s %s %s %s %s %s %s %s", "memread", "alusrca", "iord", "irwrite",
"alusrcb", "aluop", "pcen", "pcsource", "regdst", "regwrite",
"memtoreg", "memwrite");
$display("opcode = %b", opcode);
// sb
#72 opcode = 6'b101000;
$display("opcode = %b", opcode);
// r-type instructions
#56 opcode = 6'b000000;
$display("opcode = %b", opcode);
// beq
#56 opcode = 6'b000100;
$display("opcode = %b", opcode);
#40 zero = 1'b1; // check that zero works in BEQEX
// jump
#8 opcode = 6'b000010;
$display("opcode = %b", opcode);
// addi
#48 opcode = 6'b001000;
$display("opcode = %b", opcode);
// terminate simulation
#56 $finish;
end
// print the values of all relevant signals every clock period
always
#8 $display("%5b %6b %6b %6b %7b %5b %4b %8b %7b %6b %8b %7b", memread, alusrca, iord, irwrite, alusrcb, aluop,
pcen, pcsource, regdst, regwrite, memtoreg, memwrite);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[2 * 50004]; int main(void) { int n, k; cin >> n >> k; for (int i = 1; i <= 2 * n; i++) { a[i] = i; } for (int i = 1; i <= k; i++) { swap(a[2 * i], a[2 * i - 1]); } for (int i = 1; i <= 2 * n; i++) { cout << a[i] << ; } cout << endl; return 0; }
|
module scratch_pad_synthesis(clk, in, out, sel);
parameter PORTS = 8;
parameter WIDTH = 64;
parameter FRAGMENT_DEPTH = 512;
parameter REORDER_DEPTH = 32;
parameter FIFO_DEPTH = 32;
parameter REORDER_BITS = log2(REORDER_DEPTH-1) + 1;
parameter DEPTH = FRAGMENT_DEPTH * PORTS;
parameter ADDR_WIDTH = log2(DEPTH-1);
parameter PORTS_ADDR_WIDTH = log2(PORTS-1);
input clk, in, sel;
output reg out;
reg rst;
reg [0:PORTS-1] rd_en;
reg [0:PORTS-1] wr_en;
reg [WIDTH*PORTS-1:0] d;
wire [WIDTH*PORTS-1:0] q;
reg [ADDR_WIDTH*PORTS-1:0] addr;
wire [0:PORTS-1] full;
reg [0:PORTS-1]stall;
wire [0:PORTS-1]valid;
scratch_pad #(PORTS, WIDTH) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
always @(posedge clk) begin
rst <= in;
rd_en[0] <= rst;
rd_en[1:PORTS - 1] <= rd_en[0:PORTS - 2];
wr_en[0] <= rd_en[PORTS - 1];
wr_en[1:PORTS - 1] <= wr_en[0:PORTS - 2];
d[0] <= wr_en[PORTS - 1];
d[WIDTH * PORTS - 1:1] <= d[WIDTH * PORTS - 2:0];
addr[0] <= d[WIDTH * PORTS - 1];
addr[PORTS * ADDR_WIDTH - 1:1] <= addr[PORTS * ADDR_WIDTH - 2:0];
stall[0] <= addr[PORTS * ADDR_WIDTH - 1];
stall[1:PORTS - 1] <= stall[0:PORTS - 2];
end
reg [0:WIDTH * PORTS + 2 * PORTS - 1] output_shift;
always @(posedge clk) begin
if(sel == 1) begin
output_shift[0:PORTS * WIDTH - 1] <= q;
output_shift[PORTS * WIDTH +: PORTS] <= full;
output_shift[PORTS * WIDTH + PORTS +: PORTS] <= valid;
end else begin
output_shift[1:PORTS * WIDTH + 2 * PORTS - 1] <= output_shift[0:PORTS * WIDTH + 2 * PORTS - 2];
out <= output_shift[PORTS * WIDTH + 2 * PORTS - 1];
end
end
`include "common.vh"
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_V
|
#include <bits/stdc++.h> long long mod = 1000000007; using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } void solve() { long long n; cin >> n; vector<long long> a(n); priority_queue<pair<long long, long long> > pq; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > 0) pq.push({a[i], i + 1}); } vector<pair<long long, long long> > ans; while (pq.size() >= 2) { auto tp1 = pq.top(); pq.pop(); auto tp2 = pq.top(); pq.pop(); tp1.first--, tp2.first--; ans.push_back({tp1.second, tp2.second}); if (tp1.first > 0) pq.push(tp1); if (tp2.first > 0) pq.push(tp2); } cout << ans.size() << endl; for (auto x : ans) cout << x.first << << x.second << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long int ara[1000000]; int wow[7 * 22000]; void make_wow(int x) { int xx; int l; int k = 1; stack<int> s; for (int i = 1; i <= x; i++) { xx = i; while (xx != 0) { l = xx % 10; xx /= 10; s.push(l); } while (!s.empty()) { wow[k++] = s.top(); s.pop(); } } } int find_block(int x, int b) { for (int i = 1; i <= b; i++) { if (ara[i] >= x) return i - 1; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int q; cin >> q; int k = 1; int i = 1; int b = 1; long long int sum = 0, x, lb; while (ara[b - 1] <= 1000000000) { sum += log10(i++) + 1; ara[b] = ara[b - 1] + sum; b++; } make_wow(b); while (q--) { cin >> x; cout << wow[x - ara[find_block(x, b)]] << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; const ll INF = 1e16 + 2; signed main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); vector<pair<ll, ll>> pts; pts.emplace_back(); ll ax, ay, bx, by; cin >> pts[0].first >> pts[0].second >> ax >> ay >> bx >> by; ll x, y, t; cin >> x >> y >> t; while (pts.back().first < INF && pts.back().second < INF) pts.emplace_back(pts.back().first * ax + bx, pts.back().second * ay + by); int m = pts.size(); vector<int> dp(m); for (int i = 0; i < m; i++) { ll len; len = abs(pts[i].first - x) + abs(pts[i].second - y); ll cur_t = t; if (len > cur_t) { dp[i] = 0; continue; } cur_t -= len; dp[i] = 1; for (int j = i - 1; j >= 0; j--) { len = abs(pts[j].first - pts[j + 1].first) + abs(pts[j].second - pts[j + 1].second); if (cur_t >= len) dp[i] = i - j + 1; cur_t -= len; } len = abs(pts[i].first - x) + abs(pts[i].second - y); cur_t = t - len; len = abs(pts[i].first - pts[0].first) + abs(pts[i].second - pts[0].second); if (cur_t < 2 * len) continue; cur_t -= 2 * len; dp[i] = max(dp[i], i + 1); for (int j = i + 1; j < m; j++) { ll len = abs(pts[j].first - pts[j - 1].first) + abs(pts[j].second - pts[j - 1].second); if (cur_t >= len) dp[i] = max(dp[i], i + 1 + j - i); cur_t -= len; } } ll ans = *max_element(dp.begin(), dp.end()); cout << ans << n ; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:29:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: BCD_Segment_Decoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: BCD to Seven Segment Decoder
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module BCD_Segment_Decoder
#(
parameter BCD_DIGITS = 1
)
(
// BCD Input (Packed Array)
input [BCD_DIGITS*4-1:0] BCD_IN,
// Seven-Segment Output (Packed Array)
output reg [BCD_DIGITS*7-1:0] SEG_OUT,
// System Signals
input CLK
);
//
// Initialize Output
//
initial
begin
SEG_OUT <= {BCD_DIGITS*7{1'b0}};
end
//
// Select Segment Output using BCD index for each Digit
//
// !! Lab 4: Add SEG_OUT Registered Multiplexers for each BCD Digit here !!
//wire [3:0] bcd_0, bcd_1, bcd_2, bcd_3, bcd_4;
//wire [6:0] seg_0, seg_1, seg_2, seg_3, seg_4;
// Packing the Array
// assign { bcd_4, bcd_3, bcd_2, bcd_1, bcd_0 } = BCD_IN ;
// Unpacking the Array
// assign { seg_4, seg_3, seg_2, seg_1, seg_0 } = SEG_OUT;
//step 2 generate
genvar i;
generate
begin
for (i=0; i < BCD_DIGITS; i=i+1)
begin : bcd_to_seg_mapping
// Registered Multiplexer for each BCD Digit
always @(posedge CLK)
begin
case (BCD_IN[i*4 +: 4])
0: SEG_OUT[i*7 +: 7] <= 7'b0111111;
1: SEG_OUT[i*7 +: 7] <= 7'b0000110;
2: SEG_OUT[i*7 +: 7] <= 7'b1011011;
3: SEG_OUT[i*7 +: 7] <= 7'b1001111;
4: SEG_OUT[i*7 +: 7] <= 7'b1100110;
5: SEG_OUT[i*7 +: 7] <= 7'b1101101;
6: SEG_OUT[i*7 +: 7] <= 7'b1111101;
7: SEG_OUT[i*7 +: 7] <= 7'b0000111;
8: SEG_OUT[i*7 +: 7] <= 7'b1111111;
9: SEG_OUT[i*7 +: 7] <= 7'b1100111;
default: SEG_OUT[i*7 +: 7] <= 7'b0000000;
endcase
end
end
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: gsensor_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 153 11/29/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module gsensor_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output [3:0] rdusedw;
output wrfull;
output [3:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "1"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "OFF"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsensor_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module single_register(datain, dataout, clk, clr, WE);
input [31:0] datain;
output [31:0] dataout;
input clk, clr, WE;
reg [31:0] register;
always @(posedge clk or posedge clr)
begin
if(clr)
register = 0;
else
if(WE == 1)
register = datain;
end
assign dataout = register;
endmodule
module single_register_Testbench;
reg [31:0] inputA;
wire [31:0] result;
reg clk, clr, WE;
single_register UUT(inputA,result, clk, clr, WE);
initial begin
clk = 0;
clr = 0;
WE = 1;
#20 inputA = 12;
clk = !clk;
#40 inputA = 24;
clk = !clk;
#40 inputA = 36;
clk = !clk;
WE = 0;
#40 inputA = 48;
clk = !clk;
clr = 1;
#40 inputA = 1024;
clk = !clk;
clr = 0;
#40 inputA = 2048;
clk = !clk;
WE = 1;
#40 inputA = 4096;
clk = !clk;
#40 inputA = 12345;
clk = !clk;
end
endmodule
module mux4to1(datain0, datain1, datain2, datain3, dataout, select);
input [31:0] datain0, datain1, datain2, datain3;
input[1:0] select;
output [31:0] dataout;
reg [31:0] dataout;
always@(datain0 or datain1 or datain2 or datain3 or select)
begin
case(select)
2'b00: dataout = datain0;
2'b01: dataout = datain1;
2'b10: dataout = datain2;
2'b11: dataout = datain3;
endcase
end
endmodule
module mux4to1_Testbench;
reg [31:0] inputA;
reg [31:0] inputB;
reg [31:0] inputC;
reg [31:0] inputD;
reg [1:0] select;
wire [31:0] result;
mux4to1 UUT(inputA,inputB, inputC, inputD, result, select);
initial begin
inputA = 1;
inputB = 2;
inputC = 3;
inputD = 4;
#20 select = 0;
#40 select = 1;
#40 select = 2;
#40 select = 3;
end
endmodule
module signextd(datain, dataout);
input [15:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
integer i;
always @ (datain)
begin
dataout = $signed(datain);
end
endmodule
module signextd_Testbench;
reg [15:0] inputA;
wire [31:0] result;
signextd UTT(inputA,result);
initial begin
#20 inputA = 1234;
#40 inputA = 64000;
#40 inputA = 35;
end
endmodule
module shiftleft2(datain, dataout);
input [31:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
always @ (datain)
begin
dataout = datain * 4;
end
endmodule
module shiftleft2_Testbench;
reg [31:0] inputA;
wire [31:0] result;
shiftleft2 UUT(inputA,result);
initial begin
#20 inputA = 32'b0000_0000_0000_0000_1010_1010_1010_1010;
#40 inputA = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
#40 inputA = 32'b1110_1110_1110_1110_1110_1110_1110_1110;
#40 inputA = 32'b1001_1001_1001_1001_0110_0110_0110_0110;
#40 inputA = 32'b0000_1000_0001_0000_0100_0010_0010_0101;
#40 inputA = 32'b0000_1111_0000_1111_0000_1111_0000_1111;
#40 inputA = 32'b1111_0000_1111_0000_1111_0000_1111_0000;
#40 inputA = 32'b0110_0011_1100_0110_0011_1100_0110_0011;
end
initial
#340 $stop;
endmodule
/* concatenate pcin[31-28] with datain[27-0] to form a jump address*/
module concatenate4to28(datain, pcin, pcout);
input [31:0] datain, pcin;
output [31:0] pcout;
reg [31:0] pcout;
always @ (datain or pcin)
begin
pcout = {pcin[31:28],datain[27:0]};
end
endmodule
module concatenate4to28_Testbench;
reg [31:0] inputA, inputB;
wire [31:0] result;
concatenate4to28 UUT(inputA, inputB, result);
initial begin
#20 inputA = 32'b0000_0000_0000_0000_1010_1010_1010_1010;
inputB = 32'b0000_0000_0000_0000_1111_1111_1111_1111;
#40 inputA = 32'b1110_1110_1110_1110_1110_1110_1110_1110;
inputB = 32'b1001_1001_1001_1001_0110_0110_0110_0110;
#40 inputA = 32'b0000_1000_0001_0000_0100_0010_0010_0101;
inputB = 32'b0000_1111_0000_1111_0000_1111_0000_1111;
#40 inputA = 32'b1111_0000_1111_0000_1111_0000_1111_0000;
inputB = 32'b0110_0011_1100_0110_0011_1100_0110_0011;
end
endmodule
module Adder(dataA, dataB, dataOut);
input [31:0] dataA, dataB;
output dataOut;
reg [31:0] dataOut;
always @ (dataA or dataB)
begin
dataOut = dataA + dataB;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, k; cin >> n >> k; if (k == 1) { cout << Yes << endl; return; } vector<int> divs; for (int i = 2; i < k; ++i) if (!(k % i)) { cerr << i << endl; divs.push_back(1); while (!(k % i)) k /= i, divs.back() *= i; } if (k > 1) divs.push_back(k); set<int> div(divs.begin(), divs.end()); int a; for (int i = 0; i < n; ++i) { cin >> a; set<int>::iterator it = div.begin(); while (it != div.end()) { if (a % (*it)) ++it; else it = div.erase(it); } } if (div.size()) cout << No << endl; else cout << Yes << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long inf = (1LL << 60); const double pi = acos(-1); long long powmod(long long a, long long b) { long long res = 1; a %= mod; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } inline void pcas(int ca) { printf( Case %d: , ca); } const int maxn = 1e5 + 10; int nex[maxn]; char s[maxn], t[maxn]; int dp[maxn], cnt[maxn]; int lens, lent; void kmp() { nex[0] = -1; int j = -1; int i = 0; while (i < lent) { while (j != -1 && t[i] != t[j]) j = nex[j]; nex[++i] = ++j; } } int main() { scanf( %s , s); scanf( %s , t); lens = strlen(s), lent = strlen(t); kmp(); if (lens < lent) { cout << 0; return 0; } bool flag; for (int i = lent - 1; i < lens; ++i) { flag = 1; for (int j = 0; j < lent; ++j) { if (s[i - j] != t[lent - j - 1] && s[i - j] != ? ) { flag = 0; break; } } dp[i] = dp[i - 1]; if (flag) { cnt[i] = dp[i - lent]; for (int j = nex[lent]; ~j; j = nex[j]) { cnt[i] = max(cnt[i], cnt[i - lent + j]); } cnt[i]++; dp[i] = max(cnt[i], dp[i]); } } printf( %d n , dp[lens - 1]); return 0; }
|
/*!
* <b>Module:</b>drp_other_registers
* @file drp_other_registers.v
* @date 2016-03-13
* @author Andrey Filippov
*
* @brief Additional registers controlled/read back over DRP
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* drp_other_registers.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module drp_other_registers#(
parameter DRP_ABITS = 8,
parameter DRP_REG0 = 8,
parameter DRP_REG1 = 9,
parameter DRP_REG2 = 10,
parameter DRP_REG3 = 11
)(
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [DRP_ABITS-1:0] drp_addr,
input [15:0] drp_di,
output reg drp_rdy,
output reg [15:0] drp_do,
output [15:0] drp_register0,
output [15:0] drp_register1,
output [15:0] drp_register2,
output [15:0] drp_register3
);
reg [DRP_ABITS-1:0] drp_addr_r;
reg drp_wr_r;
reg [ 1:0] drp_rd_r;
reg [15:0] drp_di_r;
reg drp_reg0_set;
reg drp_reg1_set;
reg drp_reg2_set;
reg drp_reg3_set;
reg drp_reg0_get;
reg drp_reg1_get;
reg drp_reg2_get;
reg drp_reg3_get;
reg [15:0] drp_register0_r;
reg [15:0] drp_register1_r;
reg [15:0] drp_register2_r;
reg [15:0] drp_register3_r;
assign drp_register0 = drp_register0_r;
assign drp_register1 = drp_register1_r;
assign drp_register2 = drp_register2_r;
assign drp_register3 = drp_register3_r;
// DRP interface
always @ (posedge drp_clk) begin
drp_addr_r <= drp_addr;
drp_wr_r <= drp_we && drp_en;
drp_rd_r <= {drp_rd_r[0],~drp_we & drp_en};
drp_di_r <= drp_di;
drp_reg0_set <= drp_wr_r && (drp_addr_r == DRP_REG0);
drp_reg1_set <= drp_wr_r && (drp_addr_r == DRP_REG1);
drp_reg2_set <= drp_wr_r && (drp_addr_r == DRP_REG2);
drp_reg3_set <= drp_wr_r && (drp_addr_r == DRP_REG3);
drp_reg0_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG0);
drp_reg1_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG1);
drp_reg2_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG2);
drp_reg3_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG3);
drp_rdy <= drp_wr_r || drp_rd_r[1];
drp_do <= ({16{drp_reg0_get}} & drp_register0_r) |
({16{drp_reg1_get}} & drp_register1_r) |
({16{drp_reg2_get}} & drp_register2_r) |
({16{drp_reg3_get}} & drp_register3_r);
if (drp_rst) drp_register0_r <= 0;
else if (drp_reg0_set) drp_register0_r <= drp_di_r;
if (drp_rst) drp_register1_r <= 0;
else if (drp_reg1_set) drp_register1_r <= drp_di_r;
if (drp_rst) drp_register2_r <= 0;
else if (drp_reg2_set) drp_register2_r <= drp_di_r;
if (drp_rst) drp_register3_r <= 0;
else if (drp_reg3_set) drp_register3_r <= drp_di_r;
end
endmodule
|
(** Extraction : tests of optimizations of pattern matching *)
(** First, a few basic tests *)
Definition test1 b :=
match b with
| true => true
| false => false
end.
Extraction test1. (** should be seen as the identity *)
Definition test2 b :=
match b with
| true => false
| false => false
end.
Extraction test2. (** should be seen a the always-false constant function *)
Inductive hole (A:Set) : Set := Hole | Hole2.
Definition wrong_id (A B : Set) (x:hole A) : hole B :=
match x with
| Hole => @Hole _
| Hole2 => @Hole2 _
end.
Extraction wrong_id. (** should _not_ be optimized as an identity *)
Definition test3 (A:Type)(o : option A) :=
match o with
| Some x => Some x
| None => None
end.
Extraction test3. (** Even with type parameters, should be seen as identity *)
Inductive indu : Type := A : nat -> indu | B | C.
Definition test4 n :=
match n with
| A m => A (S m)
| B => B
| C => C
end.
Extraction test4. (** should merge branchs B C into a x->x *)
Definition test5 n :=
match n with
| A m => A (S m)
| B => B
| C => B
end.
Extraction test5. (** should merge branches B C into _->B *)
Inductive indu' : Type := A' : nat -> indu' | B' | C' | D' | E' | F'.
Definition test6 n :=
match n with
| A' m => A' (S m)
| B' => C'
| C' => C'
| D' => C'
| E' => B'
| F' => B'
end.
Extraction test6. (** should merge some branches into a _->C' *)
(** NB : In Coq, "| a => a" corresponds to n, hence some "| _ -> n" are
extracted *)
Definition test7 n :=
match n with
| A m => Some m
| B => None
| C => None
end.
Extraction test7. (** should merge branches B,C into a _->None *)
(** Script from bug #2413 *)
Set Implicit Arguments.
Section S.
Definition message := nat.
Definition word := nat.
Definition mode := nat.
Definition opcode := nat.
Variable condition : word -> option opcode.
Section decoder_result.
Variable inst : Type.
Inductive decoder_result : Type :=
| DecUndefined : decoder_result
| DecUnpredictable : decoder_result
| DecInst : inst -> decoder_result
| DecError : message -> decoder_result.
End decoder_result.
Definition decode_cond_mode (mode : Type) (f : word -> decoder_result mode)
(w : word) (inst : Type) (g : mode -> opcode -> inst) :
decoder_result inst :=
match condition w with
| Some oc =>
match f w with
| DecInst i => DecInst (g i oc)
| DecError m => @DecError inst m
| DecUndefined => @DecUndefined inst
| DecUnpredictable => @DecUnpredictable inst
end
| None => @DecUndefined inst
end.
End S.
Extraction decode_cond_mode.
(** inner match should not be factorized with a partial x->x (different type) *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_LP_V
`define SKY130_FD_SC_LP__XNOR3_LP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor3_lp (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor3_lp (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_LP_V
|
// file: clk_wiz_1.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____5.000______0.000______50.0______631.442____346.848
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_1_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_1),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (32.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (128.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_1),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_1),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_1),
.CLKIN1 (clk_in1_clk_wiz_1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_1),
.I (clkfbout_clk_wiz_1));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_1));
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014,2015,2016
//
// NMI generation
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module znmi
(
input wire rst_n,
input wire fclk,
input wire zpos,
input wire zneg,
input wire int_start, // when INT starts
input wire [ 1:0] set_nmi, // NMI requests from slavespi and #BF port
input wire imm_nmi, // immediate NMI from breakpoint
input wire clr_nmi, // clear nmi: from zports, pulsed at out to #xxBE
input wire rfsh_n,
input wire m1_n,
input wire mreq_n,
input wire csrom,
input wire [15:0] a,
output wire drive_00, // drive nop to Z80 databus
output reg in_nmi, // when 1, there must be last (#FF) ram page in 0000-3FFF
output wire gen_nmi, // NMI generator: when 1, NMI_N=0, otherwise NMI_N=Z
output wire nmi_buf_clr // clear ram read buffer in zmem during nmi entry
);
reg [1:0] set_nmi_r;
wire set_nmi_now;
reg imm_nmi_r;
wire imm_nmi_now;
reg pending_nmi;
reg in_nmi_2; // active (=1) when NMIed to ROM, after 0066 M1 becomes 0,
// but in_nmi becomes 1 -- ROM switches to #FF RAM
reg [2:0] nmi_count;
reg [1:0] clr_count;
reg pending_clr;
reg last_m1_rom;
reg last_m1_0066;
wire nmi_start;
//remember whether last M1 opcode read was from ROM or RAM
reg m1_n_reg, mreq_n_reg;
reg [1:0] rfsh_n_reg;
always @(posedge fclk) if( zpos )
rfsh_n_reg[0] <= rfsh_n;
always @(posedge fclk)
rfsh_n_reg[1] <= rfsh_n_reg[0];
always @(posedge fclk) if( zpos )
m1_n_reg <= m1_n;
always @(posedge fclk) if( zneg )
mreq_n_reg <= mreq_n;
wire was_m1 = ~(m1_n_reg | mreq_n_reg);
reg was_m1_reg;
always @(posedge fclk)
was_m1_reg <= was_m1;
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_rom <= csrom && (a[15:14]==2'b00);
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_0066 <= ( a[15:0]==16'h0066 );
always @(posedge fclk)
set_nmi_r <= set_nmi;
//
assign set_nmi_now = | (set_nmi_r & (~set_nmi) );
always @(posedge fclk)
imm_nmi_r <= imm_nmi;
//
assign imm_nmi_now = | ( (~imm_nmi_r) & imm_nmi );
always @(posedge fclk, negedge rst_n)
if( !rst_n )
pending_nmi <= 1'b0;
else // posedge clk
begin
if( int_start )
pending_nmi <= 1'b0;
else if( set_nmi_now )
pending_nmi <= 1'b1;
end
// actual nmi start
assign nmi_start = (pending_nmi && int_start) || imm_nmi_now;
always @(posedge fclk)
if( clr_nmi )
clr_count <= 2'd3;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && clr_count[1] )
clr_count <= clr_count - 2'd1;
always @(posedge fclk)
if( clr_nmi )
pending_clr <= 1'b1;
else if( !clr_count[1] )
pending_clr <= 1'b0;
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi_2 <= 1'b0;
else // posedge fclk
begin
if( nmi_start && (!in_nmi) /*&& last_m1_rom*/ ) // fix for NMI page after execution of 0066 opcode everywhere
in_nmi_2 <= 1'b1;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 )
in_nmi_2 <= 1'b0;
end
assign drive_00 = in_nmi_2 && (!m1_n) && (!mreq_n) && (a[15:0]==16'h0066); // && last_m1_0066;
assign nmi_buf_clr = last_m1_0066 && in_nmi_2;
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi <= 1'b0;
else // posedge clk
begin
if( pending_clr && (!clr_count[1]) )
in_nmi <= 1'b0;
else if( /*(nmi_start && (!in_nmi) && (!last_m1_rom)) ||*/
(rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 && in_nmi_2) )
in_nmi <= 1'b1;
end
always @(posedge fclk, negedge rst_n)
if( !rst_n )
nmi_count <= 3'b000;
else if( nmi_start && (!in_nmi) )
nmi_count <= 3'b111;
else if( nmi_count[2] && zpos )
nmi_count <= nmi_count - 3'd1;
assign gen_nmi = nmi_count[2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[105][105], v[105][105], dp[105][105]; long long slove(int x, int y, int n, int m) { long long t = a[x][y] - (x + y - 2); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { v[i][j] = a[i][j] - (t + i + j - 2); } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { dp[i][j] = -1; if (v[i][j] < 0) continue; if (i == 1 && j == 1) dp[i][j] = v[i][j]; else if (i == 1) { long long t = dp[i][j - 1]; if (t != -1) dp[i][j] = t + v[i][j]; } else if (j == 1) { long long t = dp[i - 1][j]; if (t != -1) dp[i][j] = t + v[i][j]; } else { long long t1 = dp[i - 1][j], t2 = dp[i][j - 1]; if (t1 != -1) dp[i][j] = t1 + v[i][j]; if (t2 != -1) { if (dp[i][j] == -1) dp[i][j] = t2 + v[i][j]; else dp[i][j] = min(dp[i][j], t2 + v[i][j]); } } } } if (dp[n][m] != -1) return dp[n][m]; else return 1e18; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; } } long long ans = 1e18; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { ans = min(ans, slove(i, j, n, m)); } } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; bool isprime(int a) { for (int i = 2; i <= sqrt((double)a); i++) { if (a % i == 0) return false; } return true; } int main() { int n; cin >> n; if (n <= 7) cout << 1 << endl << n; else { cout << 3 << endl << 3 << ; n -= 3; for (int i = 2; i <= n; i++) { if (isprime(i) && isprime(n - i)) { cout << i << << n - i; return 0; } } } }
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#include <bits/stdc++.h> using namespace std; int main() { int t = 0, counterarr[3] = {5, 7, 5}, c = 0; string x; bool arr[3] = {}; while (t < 3) { getline(cin, x); for (int i = 0; i < x.length(); i++) { if (x[i] == a || x[i] == e || x[i] == u || x[i] == i || x[i] == o ) c++; } if (c == counterarr[t]) { arr[t] = true; } c = 0; t++; } if (arr[0] == 1 && arr[1] == 1 && arr[2] == 1) cout << YES n ; else cout << NO n ; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, k, x; int A[200010] = {0}, L[200010] = {0}, R[200010] = {0}; scanf( %d%d%d , &n, &k, &x); for (int i = 1; i <= n; i++) { scanf( %d , A + i); } sort(A + 1, A + 1 + n); for (int i = 1; i <= n; i++) { L[i] = A[i] | L[i - 1]; } for (int i = n; i >= 1; i--) { R[i] = A[i] | R[i + 1]; } long long ret = 0, m = 1; for (int i = 1; i <= k; i++) { m *= x; } for (int i = 1; i <= n; i++) { long long ans = A[i] * m | L[i - 1] | R[i + 1]; if (ans > ret) { ret = ans; } } printf( %I64d n , ret); }
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#include <bits/stdc++.h> const long long int MOD = 1000000007ll; const int mxsz = 200005; using namespace std; int main() { std::ios_base::sync_with_stdio(false); long long int n, m, a; cin >> n >> m >> a; int ar1[n + 1], ar2[m + 1]; for (int i = 1; i <= n; i++) { cin >> ar1[i]; } for (int i = 1; i <= m; i++) { cin >> ar2[i]; } sort(ar1 + 1, ar1 + n + 1); sort(ar2 + 1, ar2 + m + 1); vector<long long int> b, p; for (int i = 1; i <= min(n, m); i++) { b.push_back(ar1[n - i + 1]); p.push_back(ar2[i]); } int l = 0, r = min(n, m); int ans = 0; while (l <= r) { int mid = (l + r) / 2; long long int tmp = a; for (int i = 0; i < mid; i++) { tmp -= (long long int)max(0LL, p[mid - i - 1] - b[i]); if (tmp < 0) { break; } } if (tmp >= 0) { l = mid + 1; ans = mid; } else { r = mid - 1; } } cout << ans << ; long long int tmp = 0; for (int i = 0; i < ans; i++) { tmp += (long long int)p[i]; } cout << max(0LL, tmp - a); return 0; }
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#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, vmx; long long seed; struct node { int l, r; mutable long long val; bool operator<(const node &x) const { return l < x.l; } }; set<node> tr; set<node>::iterator split(int pos) { set<node>::iterator iter = tr.lower_bound((node){pos}); if (iter != tr.end() && iter->l == pos) return iter; iter--; int L = iter->l, R = iter->r; long long Val = iter->val; tr.erase(iter); tr.insert((node){L, pos - 1, Val}); return tr.insert((node){pos, R, Val}).first; } void assign(int l, int r, long long val) { set<node>::iterator R = split(r + 1), L = split(l); tr.erase(L, R); tr.insert((node){l, r, val}); return; } void add(int l, int r, long long val) { set<node>::iterator R = split(r + 1), L = split(l); for (; L != R; ++L) L->val = L->val + val; return; } struct Lsh { long long val; int sum; } ls[N]; inline bool Lscmp(Lsh a, Lsh b) { return a.val < b.val; } inline long long rnk(int l, int r, int x) { set<node>::iterator R = split(r + 1), L = split(l); int tot = 0; for (; L != R; ++L) ls[++tot].val = L->val, ls[tot].sum = (L->r - L->l + 1); sort(ls + 1, ls + tot + 1, Lscmp); for (int i = 1; i <= tot; i++) { x -= ls[i].sum; if (x <= 0) return ls[i].val; } } inline long long ksm(long long a, long long b, long long mod) { a %= mod; long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; a = a * a % mod; b >>= 1; } return ans; } inline long long calc(int l, int r, int x, int y) { set<node>::iterator R = split(r + 1), L = split(l); long long ans = 0; for (; L != R; ++L) ans = (ans + ksm(L->val, x, y) * (L->r - L->l + 1) % y) % y; return ans; } inline int rnd() { int ret = seed; seed = (seed * 7 + 13) % 1000000007; return ret; } int op, l, r, x, y; int tot; int main() { scanf( %d%d%lld%d , &n, &m, &seed, &vmx); for (int i = 1; i <= n; i++) tr.insert((node){i, i, rnd() % vmx + 1}); tr.insert((node){n + 1, n + 1, 0}); for (int i = 1; i <= m; i++) { op = rnd() % 4 + 1; l = rnd() % n + 1; r = rnd() % n + 1; if (l > r) swap(l, r); if (op == 3) x = rnd() % (r - l + 1) + 1; else x = rnd() % vmx + 1; if (op == 4) y = rnd() % vmx + 1; if (op == 1) add(l, r, x); else if (op == 2) assign(l, r, x); else if (op == 3) printf( %lld n , rnk(l, r, x)); else printf( %lld n , calc(l, r, x, y)); } return 0; }
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#include <bits/stdc++.h> using namespace std; const int maxn = 100; int a[maxn], s[maxn], f[maxn], n, ans; int pmin, pmax; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , a + i), f[i] = -1; sort(a, a + n); swap(a[0], a[n - 1]); for (int i = 0; i < n; i++) printf( %d , a[i]); printf( n ); return 0; }
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_1 (
CLK,
read_0,
write_0,
EN_write_0
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign read_0 = wire_0;
always @(posedge CLK) begin
r <= wire_1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NSR (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 0x3f3f3f3f; const double eps = 1e-6; const long long mod = 1000000007; inline string getstr(string &s, long long l, long long r) { string ret = ; for (long long i = l; i <= r; i++) ret.push_back(s[i]); return ret; } long long modpow(long long x, long long y, long long md = mod) { long long ret = 1; do { if (y & 1) ret = (long long)ret * x % md; x = (long long)x * x % md; } while (y >>= 1); return ret; } long long n, mn; vector<pair<long long, long long> > g[3003]; long long dfs(long long x, long long p, long long cur, long long mv) { long long ret = 0; mn = min(mn, cur - mv); for (auto to : g[x]) if (to.first != p) { ret += (to.second > 0); ret += dfs(to.first, x, cur - to.second, max(mv, cur - to.second)); } return ret; } signed main() { cin >> n; for (long long i = 1; i < n; i++) { long long x, y; cin >> x >> y; g[x].push_back(make_pair(y, -1)); g[y].push_back(make_pair(x, 1)); } long long ans = 1e9; for (long long i = 1; i <= n; i++) { mn = inf; ans = min(ans, dfs(i, -1, 0, 0) + mn); } cout << ans << endl; return 0; }
|
#include <bits/stdc++.h> int n, m, k; char s[2505][2505]; long long a[2505][2505]; inline long long sum(int r1, int c1, int r2, int c2) { return a[r2][c2] - a[r1 - 1][c2] - a[r2][c1 - 1] + a[r1 - 1][c1 - 1]; } inline long long go(int r1, int c1, int r2, int c2) { if (r1 == r2 && c1 == c2) return sum(r1, c1, r2, c2) == k; if (r2 - r1 > c2 - c1) { long long cnt = 0; int m = r1 + r2 >> 1; int up[k + 1], dw[k + 1]; for (int i = c1; i <= c2; i++) { for (int x = 0; x <= k; x++) up[x] = m - r1 + 1, dw[x] = r2 - m; for (int j = i; j <= c2; j++) { for (int x = 0; x <= k; x++) { while (up[x] && sum(m - up[x] + 1, i, m, j) > x) up[x]--; while (dw[x] && sum(m + 1, i, m + dw[x], j) > x) dw[x]--; } for (int x = 0; x <= k; x++) { cnt += (long long)(up[x] - (x ? up[x - 1] : 0)) * (dw[k - x] - (k - x ? dw[k - x - 1] : 0)); } } } return cnt + go(r1, c1, m, c2) + go(m + 1, c1, r2, c2); } else { long long cnt = 0; int m = c1 + c2 >> 1; int up[k + 1], dw[k + 1]; for (int i = r1; i <= r2; i++) { for (int x = 0; x <= k; x++) up[x] = m - c1 + 1, dw[x] = c2 - m; for (int j = i; j <= r2; j++) { for (int x = 0; x <= k; x++) { while (up[x] && sum(i, m - up[x] + 1, j, m) > x) up[x]--; while (dw[x] && sum(i, m + 1, j, m + dw[x]) > x) dw[x]--; } for (int x = 0; x <= k; x++) { cnt += (long long)(up[x] - (x ? up[x - 1] : 0)) * (dw[k - x] - (k - x ? dw[k - x - 1] : 0)); } } } return cnt + go(r1, c1, r2, m) + go(r1, m + 1, r2, c2); } } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %s , &s[i][1]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { a[i][j] = a[i - 1][j] + a[i][j - 1] - a[i - 1][j - 1] + s[i][j] - 0 ; } } printf( %I64d n , go(1, 1, n, m)); }
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module altera_wait_generate
//#(
//This code only works when wait_cycle =1, if need other case, you need to modify this code.
//please set wait_cycle default value as 1 to keep old design works.
// parameter wait_cycle =1
// )
(
input wire rst,
input wire clk,
input wire launch_signal,
output wire wait_req
);
reg launch_reg = 0;
reg wait_reg = 0;
always @ (posedge clk, posedge rst) begin
if(rst) launch_reg <= 1'b0;
else launch_reg <= launch_signal;
end
always @ (posedge clk, posedge rst) begin
if(rst) wait_reg <= 1'b0;
else wait_reg <= launch_signal & launch_reg & (! wait_reg & !wait_req);
end
// waitrequest should be asserted during reset - note that in the reconfig
// controller, reset is locally synchronized. If you are using this module
// outside the reconfig controller, you may want to ensure that the reset
// signal is synchronized to prevent glitches, as waitrequest is not
// necessarily a registered output.
wire reset_sync;
alt_xcvr_resync #(.INIT_VALUE (1)) rst_sync (.clk(clk),.reset(rst),.d(1'b0),.q(reset_sync));
assign wait_req = reset_sync | (launch_signal & ~launch_reg) | (wait_reg & launch_signal ) ;
endmodule
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#include <bits/stdc++.h> using namespace std; string s; int ans, pre, cnt; int main() { cin >> s; for (int i = 0; i < s.size(); i++) { pre += s[i] - 0 ; cnt++; if (cnt == 3 || (s[i] - 0 ) % 3 == 0 || pre % 3 == 0) ans++, pre = 0, cnt = 0; } cout << ans << endl; return 0; }
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#include <bits/stdc++.h> using namespace std; inline int read() { int ans = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) ans = (ans << 1) + (ans << 3) + (ch ^ 48), ch = getchar(); return ans; } inline long long L_read() { long long ans = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) ch = getchar(); while (ch >= 0 && ch <= 9 ) ans = (ans << 1) + (ans << 3) + (ch ^ 48), ch = getchar(); return ans; } int dx[5] = {0, -1, 1, 0, 0}; int dy[5] = {0, 0, 0, -1, 1}; struct cz { long long Time; bool Initial; }; cz state[1050][1050]; bool mp[1050][1050]; long long p; string s; struct pos { int x; int y; }; pos ww; inline bool check(int x, int y, int n, int m) { for (int i = 1; i <= 4; i++) { int nowx = x + dx[i], nowy = y + dy[i]; if (nowx >= 1 && nowx <= n && nowy >= 1 && nowy <= m) if (mp[nowx][nowy] == mp[x][y]) return true; } return false; } int n, m, k, x, y; bool vis[1050][1050]; queue<pos> qwq; inline void bfs() { while (!qwq.empty()) { int nowx = qwq.front().x; int nowy = qwq.front().y; qwq.pop(); for (int i = 1; i <= 4; i++) { if (nowx + dx[i] >= 1 && nowx + dx[i] <= n && nowy + dy[i] >= 1 && nowy + dy[i] <= m) { if (!vis[nowx + dx[i]][nowy + dy[i]]) { vis[nowx + dx[i]][nowy + dy[i]] = 1; state[nowx + dx[i]][nowy + dy[i]].Time = state[nowx][nowy].Time + 1; ww.x = nowx + dx[i]; ww.y = nowy + dy[i]; qwq.push(ww); } } } } } int Odd(long long i) { return (i & 1) != 0; } int main() { bool ff = 0; n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) { cin >> s; for (int j = 0; j < m; j++) { if (s[j] == 1 ) state[i][j + 1].Initial = 1, mp[i][j + 1] = 1; } } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (check(i, j, n, m)) { ww.x = i, ww.y = j; vis[i][j] = 1; qwq.push(ww); ff = 1; } if (!ff) { for (int i = 1; i <= k; i++) { x = read(), y = read(), p = L_read(); cout << mp[x][y] << n ; } return 0; } bfs(); for (int i = 1; i <= k; i++) { x = read(), y = read(); p = L_read(); if (p <= state[x][y].Time) { cout << state[x][y].Initial << n ; continue; } if (!Odd(p - state[x][y].Time)) cout << state[x][y].Initial << n ; else { if (state[x][y].Initial == 0) cout << 1 << n ; else cout << 0 n ; } } return 0; }
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#include <bits/stdc++.h> using namespace std; int addOne(int x) { return x + 1; } int main() { int a, b; cin >> a >> b; while (b) { a = addOne(a); b--; } cout << a << endl; }
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#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b); long long int gcd(long long int a, long long int b); int prime(int n); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; while (t--) { long long int n, m, sum; cin >> n >> m; long long int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n, greater<int>()); for (int k = 1; k <= n; k++) { sum = 0; for (int i = 0; i < n; i++) { sum += max(0LL, a[i] - (i / k)); } if (sum >= m) { cout << k << endl; break; } } if (sum < m) cout << -1 << endl; } } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } int prime(int n) { int flag = 1; for (int i = 2; i <= sqrt(n); i++) { if (n % i == 0) { flag = 0; break; } } return flag; }
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#include <bits/stdc++.h> using namespace std; void dbg() { std::cout << # n ; } template <typename T, typename... Args> void dbg(T a, Args... args) { std::cout << a << ; dbg(args...); } const long long maxn = 2e5 + 10; const long long MAX = 1000; const long long inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; long long n, d, m; long long a[maxn]; long long b[maxn]; multiset<long long> small; void solve() { cin >> n >> d >> m; for (long long i = (1); i <= (n); ++i) { cin >> a[i]; } sort(a + 1, a + 1 + n); long long pos = upper_bound(a + 1, a + 1 + n, m) - a; long long cans = 0; long long ans = 0; for (long long i = (1); i <= (pos - 1); ++i) small.insert(a[i]), cans += a[i]; long long forsmall = n - 1; ans = max(cans, ans); for (long long i = (1); i <= (n - pos + 1); ++i) { if (forsmall < 0) break; while (small.size() > forsmall) { cans -= *small.begin(); small.erase(small.begin()); } cans += a[n - i + 1]; ans = max(ans, cans); forsmall -= (d + 1); } cout << (ans) << endl; } signed main() { long long TestCase = 1; while (TestCase--) { solve(); } char EndFile = getchar(); EndFile = getchar(); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP
);
// Module ports
output VIRTPWR;
input SLEEP ;
// Local signals
wire vgnd;
wire vpwr;
// Name Output Other arguments
pulldown pulldown0 (vgnd );
bufif0 bufif00 (VIRTPWR, vpwr, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_FUNCTIONAL_V
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#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t-- > 0) { int n, m; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int i = 0, t = 0, f = 0; while (i < n - 1) { if (a[0] != 1) { f = 1; cout << First n ; break; } else if (a[0] == 1) { while (i < n - 1 && a[i] == 1) { t++; i++; } break; } i++; } if (t % 2 == 0 && f == 0) { cout << First n ; } else if (t % 2 == 1 && f == 0) { cout << Second n ; } } return 0; }
|
#include <bits/stdc++.h> const int INF = 1000000; using namespace std; int main() { int a, b, m; vector<int> r(1); scanf( %d %d %d %d , &a, &b, &m, &r[0]); for (int i = 1; i < 2 * m + 2; i++) { r.push_back((a * r[i - 1] + b) % m); } vector<int> ans(2 * m + 2, INF); int res = 1; for (int i = 1; i < m + 1; i++) { for (int t = 1; t < m + 1; t++) if (r[i] == r[i + t]) { ans[i] = min(t, ans[i - 1]); res = ans[i]; cout << res; return 0; } } cout << res; return 0; }
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 29312 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w4,
w261,
w32,
w229,
w29312;
assign w1 = i_data0;
assign w229 = w261 - w32;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w261 = w257 + w4;
assign w29312 = w229 << 7;
assign w32 = w1 << 5;
assign w4 = w1 << 2;
assign o_data0 = w29312;
//multiplier_block area estimate = 4204.56962668382;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[1500][1500]; int visited[1500][1500]; int n, m; struct node { int x, y; }; node vis[1500][1500]; int main() { int sx, sy; char x; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( n ); for (int j = 0; j < m; j++) { scanf( %c , &x); if (x == # ) a[i][j] = 0; else if (x == . ) a[i][j] = 1; else { a[i][j] = 1; sx = i; sy = j; } } } bool flag = false; visited[sx][sy] = 1; vis[sx][sy].x = sx; vis[sx][sy].y = sy; queue<node> q; node tmp; tmp.x = sx; tmp.y = sy; q.push(tmp); while (!q.empty()) { tmp = q.front(); q.pop(); node tmp1, tmp2; tmp1.x = tmp.x; tmp1.y = tmp.y - 1; tmp2 = tmp1; tmp1.x = tmp1.x % n; tmp1.y = tmp1.y % m; if (tmp1.x < 0) tmp1.x += n; if (tmp1.y < 0) tmp1.y += m; if (visited[tmp1.x][tmp1.y] == 0 && a[tmp1.x][tmp1.y] == 1) { visited[tmp1.x][tmp1.y] = 1; vis[tmp1.x][tmp1.y] = tmp2; q.push(tmp2); } else if (visited[tmp1.x][tmp1.y] == 1 && (vis[tmp1.x][tmp1.y].x != tmp2.x || vis[tmp1.x][tmp1.y].y != tmp2.y)) { flag = true; } tmp1.x = tmp.x; tmp1.y = tmp.y + 1; tmp2 = tmp1; tmp1.x = tmp1.x % n; tmp1.y = tmp1.y % m; if (tmp1.x < 0) tmp1.x += n; if (tmp1.y < 0) tmp1.y += m; if (visited[tmp1.x][tmp1.y] == 0 && a[tmp1.x][tmp1.y] == 1) { visited[tmp1.x][tmp1.y] = 1; vis[tmp1.x][tmp1.y] = tmp2; q.push(tmp2); } else if (visited[tmp1.x][tmp1.y] == 1 && (vis[tmp1.x][tmp1.y].x != tmp2.x || vis[tmp1.x][tmp1.y].y != tmp2.y)) { flag = true; } tmp1.x = tmp.x - 1; tmp1.y = tmp.y; tmp2 = tmp1; tmp1.x = tmp1.x % n; tmp1.y = tmp1.y % m; if (tmp1.x < 0) tmp1.x += n; if (tmp1.y < 0) tmp1.y += m; if (visited[tmp1.x][tmp1.y] == 0 && a[tmp1.x][tmp1.y] == 1) { visited[tmp1.x][tmp1.y] = 1; vis[tmp1.x][tmp1.y] = tmp2; q.push(tmp2); } else if (visited[tmp1.x][tmp1.y] == 1 && (vis[tmp1.x][tmp1.y].x != tmp2.x || vis[tmp1.x][tmp1.y].y != tmp2.y)) { flag = true; } tmp1.x = tmp.x + 1; tmp1.y = tmp.y; tmp2 = tmp1; tmp1.x = tmp1.x % n; tmp1.y = tmp1.y % m; if (tmp1.x < 0) tmp1.x += n; if (tmp1.y < 0) tmp1.y += m; if (visited[tmp1.x][tmp1.y] == 0 && a[tmp1.x][tmp1.y] == 1) { visited[tmp1.x][tmp1.y] = 1; vis[tmp1.x][tmp1.y] = tmp2; q.push(tmp2); } else if (visited[tmp1.x][tmp1.y] == 1 && (vis[tmp1.x][tmp1.y].x != tmp2.x || vis[tmp1.x][tmp1.y].y != tmp2.y)) { flag = true; } } if (flag) printf( Yes n ); else printf( No n ); return 0; }
|
`timescale 1ns / 1ps
/*
Group Members: Kevin Ingram and Warren Seto
Lab Name: Traffic Light Controller (Lab 3)
Project Name: eng312_proj3
Design Name: Traffic_Test_E_eng312_proj3.v
Design Description: Verilog Test Bench to Implement Test E (1 PM)
*/
module Traffic_Test;
// Inputs
reg NS_VEHICLE_DETECT;
reg EW_VEHICLE_DETECT;
// Outputs
wire NS_RED;
wire NS_YELLOW;
wire NS_GREEN;
wire EW_RED;
wire EW_YELLOW;
wire EW_GREEN;
// Clock
reg clk;
// Counters
wire[4:0] count1;
wire[3:0] count2;
wire[1:0] count3;
// Counter Modules
nsCounter clock1(clk, count1); // Count a total of 32 seconds
ewCounter clock2(clk, count2); // Counts a total of 16 seconds
yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
// Main Traffic Module
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 1;
$display(" NS | EW ");
$display(" (Time) | R Y G R Y G ");
$monitor("%d | %h %h %h %h %h %h", $time, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin
#1 clk = ~clk;
end
always @ (clk) begin
if ($time % 2 == 0) begin
NS_VEHICLE_DETECT = ~NS_VEHICLE_DETECT;
end
if ($time % 15 == 0) begin
EW_VEHICLE_DETECT = ~EW_VEHICLE_DETECT;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; int main() { string s; cin >> s; int index = s.size() - 1; vector<char> din3(s.size(), 0); vector<char> din2(s.size(), 0); if (index - 2 >= 5) din3[index - 2] = 1; if (index - 1 >= 5) din2[index - 1] = 1; index -= 3; set<string> res; while (index >= 5) { if (din2[index + 2] == 1 and s.substr(index, 2) != s.substr(index + 2, 2)) { din2[index] = 1; } if (din3[index + 3] == 1 and s.substr(index, 3) != s.substr(index + 3, 3)) { din3[index] = 1; } if (din2[index + 3] == 1) { din3[index] = 1; } if (din3[index + 2] == 1) { din2[index] = 1; } --index; } for (auto i(0); i < din2.size(); ++i) { if (din2[i] == 1) { res.insert(s.substr(i, 2)); } } for (auto i(0); i < din3.size(); ++i) { if (din3[i] == 1) { res.insert(s.substr(i, 3)); } } cout << res.size() << endl; while (!res.empty()) { cout << *res.begin() << endl; res.erase(res.begin()); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int k1, k2, k3, count[6], min_elt = INT_MAX; memset(count, 0, sizeof(count)); scanf( %d%d%d , &k1, &k2, &k3); count[k1 >= 5 ? 5 : k1]++; count[k2 >= 5 ? 5 : k2]++; count[k3 >= 5 ? 5 : k3]++; min_elt = min(k3, min(k1, k2)); if (min_elt >= 4) printf( NO n ); else if (min_elt == 1) printf( YES n ); else if (min_elt == 2) { if (count[2] >= 2) printf( YES n ); else if (count[4] == 2) printf( YES n ); else printf( NO n ); } else if (count[3] == 3) printf( YES n ); else printf( NO n ); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m; long long f[305][305][5]; struct point { int x, y; point(int x = 0, int y = 0) : x(x), y(y) {} } a[305]; struct edge { int u, v; double w; edge(int u = 0, int v = 0, double w = 0) : u(u), v(v), w(w) {} bool operator<(const edge b) const { return w < b.w; } } s[305 * 305]; int read() { char c = getchar(); int x = 0, s = 1; while (!isdigit(c)) { if (c == - ) s = -1; c = getchar(); } while (isdigit(c)) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } return x * s; } int main() { n = read(); for (int i = 1; i <= n; ++i) { a[i].x = read(); a[i].y = read(); } for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) if (i != j) s[++m] = edge(i, j, atan2(a[i].y - a[j].y, a[i].x - a[j].x)); sort(s + 1, s + m + 1); for (int i = 1; i <= m; ++i) { int u = s[i].u, v = s[i].v; f[u][v][0] = 1; for (int k = 1; k <= 4; ++k) for (int j = 1; j <= n; ++j) f[j][v][k] += f[j][u][k - 1]; } long long ans = 0; for (int i = 1; i <= n; ++i) ans += f[i][i][4]; printf( %I64d n , ans); }
|
#include <bits/stdc++.h> using namespace std; int n, m; int team[101]; char c[101]; int dp[21][(1 << 20) + 5]; int a[1001]; int solve(int pos, int mask) { if (pos == n) return 0; if (dp[pos][mask] != -1) return dp[pos][mask]; int ans; if (team[pos] == 1) { ans = -(1 << 30); for (int i = 0; i < m; i++) { if (mask & (1 << i)) { if (c[pos] == p ) ans = max(ans, a[i] + solve(pos + 1, mask ^ (1 << i))); else ans = max(ans, solve(pos + 1, mask ^ (1 << i))); } } } else { ans = (1 << 30); for (int i = 0; i < m; i++) { if (mask & (1 << i)) { if (c[pos] == p ) ans = min(ans, solve(pos + 1, mask ^ (1 << i)) - a[i]); else ans = min(ans, solve(pos + 1, mask ^ (1 << i))); } } } return dp[pos][mask] = ans; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); reverse(a, a + n); cin >> m; n = m; memset(dp, -1, sizeof(dp)); for (int i = 0; i < m; i++) { cin >> c[i] >> team[i]; } cout << solve(0, (1 << m) - 1) << endl; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long LINF = LLONG_MAX; int main() { std::ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; vector<int> a(n, 0); int ind = 0, length = n + 1; for (int i = 0; i < m; i++) { int l, r; cin >> l >> r; if (length > r - l + 1) { length = r - l + 1; ind = l - 1; } } for (int i = ind, j = 0; i < n; i++, j++) { a[i] = j % length; } for (int i = ind - 1, j = length - 1; i >= 0; i--, j = (j - 1 + length) % length) a[i] = j; cout << length << endl; for (auto k : a) cout << k << ; return 0; }
|
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-13; int ROUND(double x) { return (int)(x + 0.5); } bool ISINT(double x) { return fabs(ROUND(x) - x) <= EPS; } bool ISEQUAL(double x, double y) { return fabs(x - y) <= EPS * max(1.0, max(fabs(x), fabs(y))); } double SQSUM(double x, double y) { return x * x + y * y; } template <class T> bool INRANGE(T x, T a, T b) { return a <= x && x <= b; } int main() { long long n, l, t; scanf( %lld %lld %lld n , &n, &l, &t); vector<long long> a(n); for (int i = 0; i < n; i++) { scanf( %lld n , &a[i]); } long long count = 0; long long base = 2 * t / l; long long boundary = (2 * t) % l; { int x = 1; for (int y = 0; y < n - 1; y++) { x = max(x, y + 1); while (x < n) { if (a[x] - a[y] > boundary) { break; } x++; } count += (x - (y + 1)); } } { int x = 1; for (int y = 0; y < n - 1; y++) { x = max(x, y + 1); while (x < n) { if (l - (a[x] - a[y]) <= boundary) { break; } x++; } count += (n - x); } } double ans = 0.0; double masu = n * (n - 1) * 0.5; ans += (double)base * masu * 2; ans += 1.0 * count; ans /= 4; printf( %.16f n , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_4_V
`define SKY130_FD_SC_MS__O2BB2A_4_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2a_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_4_V
|
/**
* This is written by Andrew Mattheisen
* and Zhiyang Ong
*/
module conv_encoder (output [1:0] c, input b, input clk, input reset);
// Output signals for the design module
// Input signals for the design module
// Declare "reg" signals...
// Output bus that will be assigned values
reg [1:0] c;
/*
* Output of flip-flops in the convolutional encoder
* D_0 is the output of the first flip-flop
* D_1 is the output of the second flip-flop
*/
reg D_0, D_1;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// First flip-flop of the convolutional encoder
always @ (posedge clk)
begin
// If the reset signal is HIGH
if (reset)
begin
// Ground the output signal of the first flip-flop
D_0 <= 1'b0;
end
else
begin
// Assign the output of the 1st flip-flop to the signal b
D_0 <= b;
end
end
// Second flip-flop of the convolutional encoder
always @ (posedge clk)
begin
// If the reset signal is HIGH
if (reset)
begin
// Ground the output signal of the 2nd flip-flop
D_1 <= 1'b0;
end
else
begin
// Assign the output of the 2nd flip-flop to the signal b
D_1 <= D_0;
end
end
always @ (D_0 or D_1 or b)
begin
// 3-input XOR gate of the convolutional encoder
c[0] <= b^D_0^D_1;
// 2-input XOR gate of the convolutional encoder
c[1] <= b^D_1;
end // always @ (D_0 or D_1 or b)
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; int f(vector<int>& a, int x) { if (a[x] == x) return x; a[x] = f(a, a[x]); return a[x]; } bool mer(vector<int>& a, int x, int y) { if (f(a, x) == f(a, y)) return true; else return false; } void uni(vector<int>& a, int x, int y) { if (mer(a, x, y)) return; else a[f(a, y)] = f(a, x); } bool s[100005]; int main() { int n, ma, mb, x, y; cin >> n >> ma >> mb; vector<int> a(n + 1), b(n + 1); for (int i = 0; i <= n; i++) a[i] = b[i] = i; for (int i = 0; i < ma; i++) { cin >> x >> y; uni(a, x, y); } for (int i = 0; i < mb; i++) { cin >> x >> y; uni(b, x, y); } vector<pair<int, int>> c; vector<int> e, f; for (int i = 1; i <= n; i++) { if (!mer(a, 1, i) && !mer(b, 1, i)) { c.push_back(pair<int, int>(1, i)); uni(a, 1, i); uni(b, 1, i); } } int i, j; i = j = 2; while (1) { while (i <= n && mer(a, 1, i)) i++; if (i > n) break; while (j <= n && mer(b, 1, j)) j++; if (j > n) break; uni(a, i, j); uni(b, i, j); c.push_back(pair<int, int>(i, j)); i++; j++; } cout << c.size() << endl; for (int i = 0; i < c.size(); i++) { cout << c[i].first << << c[i].second << endl; } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTP_1_V
`define SKY130_FD_SC_MS__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTP_1_V
|
//-------------------------------------------------------------------
//-- inv_tb.v Banco de pruebas para el inversor
//-------------------------------------------------------------------
//-- (c) BQ August 2015. Written by Juan Gonzalez
//-------------------------------------------------------------------
//-- GPL LICENSE
//-------------------------------------------------------------------
//-- Pruebas del inversor. Se instancia el inversor. Se conecta un
//-- cable a su salida y un registro a su entrada. Desde el programa
//-- principal se dan valores a las entradas (mediante din) y se
//-- comprueba si la salida es la correcta
//-------------------------------------------------------------------
module inv_tb();
//-- Registro de 1 bit conectado a la entrada del inversor
reg din;
//-- Cable conectado a la salida del inversor
wire dout;
//-- Instaciar el inversor, conectado din a la entrada A, y dout a la salida B
inv NOT1 (
.IN (din),
.LED8 (dout)
);
//-- Comenzamos las pruebas
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("inv_tb.vcd");
$dumpvars(0, inv_tb);
//-- Ponemos la entrada del inversor a 0
//-- OJO! Esto lo estamos haciendo a partir del instante 5.
//-- Antes su estado es indefinido, por lo que la salida tambien
//-- estará en un estado indefinido
#5 din = 0;
//-- Tras 5 unidades de tiempo comprobamos la salida
# 5 if (dout != 1)
$display("---->¡ERROR! Esperado: 1. Leido: %d", dout);
//-- Tras otras 5 unidades ponemos un 1 en la entrada
# 5 din = 1;
//-- Tras 5 unidades comprobamos si hay un 0 en la entrada
# 5 if (dout != 0)
$display("---> ¡ERROR! Esperado: 0. Leido: %d", dout);
# 5 $display("FIN de la simulacion");
//-- Terminar la simulacion 10 unidades de tiempo
//-- despues
# 10 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s; static int x[27]; int n, k; cin >> n >> k; cin >> s; for (int i = 0; i < k; i++) { char r; cin >> r; x[r - a ] = 1; } long long res = 0, tr = 0; for (int i = 0; s[i]; i++) { if (x[s[i] - a ]) tr++; else { res += (tr * (tr + 1)) / 2; tr = 0; } } res += (tr * (tr + 1)) / 2; cout << res; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long t, a, b; cin >> t; while (t--) { cin >> a >> b; int f = 0; long long area = a * a - b * b; if ((a - b) != 1) cout << NO ; else { area = a + b; for (int i = 2; i <= sqrt(a + b); i++) { if (area % i == 0) { cout << NO ; f = 1; break; } } if (f == 0) cout << YES ; } cout << endl; } }
|
`timescale 1ns / 100ps
// File name : p3hw3fall2015DataUnit.v
// Jianjian Song
// Data Unit of a 4-bit serial multiplier with adder and shift regissters
module DataUnit(Product, Multiplicant, Multiplier, Shift1, Shift0, reset, clock);
input clock, reset;
input [3:0] Multiplicant, Multiplier;
input [2:0] Shift1, Shift0;
output [7:0] Product;
//Multiplier shift register
wire [3:0] MultiplierOut;
SN74194 MultiplierRegister(Multiplier,MultiplierOut,1'b0,1'b0,Shift1[2],Shift0[2],reset,clock);
SN74157 MultiplicantMux(Multiplicant[3],1'b0,Multiplicant[2],1'b0,Multiplicant[1],1'b0,Multiplicant[0],1'b0,1'b0,MultiplierOut[0],QA,QB,QC,QD);
//upper product
wire [3:0] Sum;
reg CarryOut;
SN74194 UpperProductRegister(Sum,Product[7:4],1'b0,CarryOut,Shift1[1],Shift0[1],reset,clock);
//lower product
SN74194 LowerProductRegister(4'd0,Product[3:0],1'b0,Product[4],Shift1[0],Shift0[0],reset,clock);
wire CO;
SN7483 Adder({QA,QB,QC,QD},Product[7:4],1'b0,CO,Sum);
always@(posedge clock or negedge reset)
if(reset==0) CarryOut<=0;
else CarryOut<=CO;
endmodule
|
#include <bits/stdc++.h> using namespace std; int T; long long r, b, k, g; long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { scanf( %d , &T); while (T--) { scanf( %lld%lld%lld , &r, &b, &k); if (r > b) swap(r, b); g = gcd(r, b); r /= g, b /= g; if ((k - 1) * r + 1 >= b) printf( OBEY n ); else printf( REBEL n ); } return 0; }
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [2:0] res [0:7];
reg [2:0] in [0:7];
reg [7:0] dummy [0:6];
time run_time [0:7];
time exp_time [0:7];
integer i;
initial begin
pass = 1'b1;
#1;
// Initialize the input array.
for (i=0; i<8; i=i+1) begin
in[i] = i[2:0];
end
#1;
for (i=0; i<8; i=i+1) begin
exp_time[i] = $time-1;
end
check;
// We only have 6 dummy items, check that each triggers correctly.
for (i=0; i<7; i=i+1) begin
dummy[i] = 1'b0;
#1;
exp_time[i] = $time-1;
check;
end
if (pass) $display("PASSED");
end
// Check that the value and time are correct.
task check;
integer j;
begin
for (j=0; j<8; j=j+1) begin
if (res[j] !== j[2:0]) begin
$display("FAILED: index %0d value, at %2t, expexted %b, got %b.",
j, $time, j[2:0], res[j]);
pass = 1'b0;
end
if (run_time[j] !== exp_time[j]) begin
$display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.",
j, $time, exp_time[j], run_time[j]);
pass = 1'b0;
end
end
end
endtask
genvar m;
generate
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
for (m=0; m<=7; m=m+1) begin: idac_loop
`else
for (m=0; m<=6; m=m+1) begin: idac_loop
`endif
// This should complain that dummy[7] is out of bounds.
always @ (in[m] or dummy[m]) begin
res[m] = in[m];
run_time[m] = $time;
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, n1, ans, m, per1, per2, add; const int maxn = 1000007; long long tree[maxn * 4][4]; void build() { for (int j = n1 - 1; j < n1 + n - 1; j++) { tree[j][0] = j - n1 + 2; tree[j][1] = j - n1 + 2; tree[j][2] = 0; tree[j][3] = 0; } for (int j = n1 + n - 1; j < 2 * n1 - 1; j++) { tree[j][0] = j - n1 + 2; tree[j][1] = j - n1 + 2; tree[j][2] = 0; tree[j][3] = 0; } for (int j = n1 - 2; j > -1; j -= 1) { tree[j][0] = tree[j * 2 + 1][0]; tree[j][1] = tree[j * 2 + 2][1]; tree[j][2] = 0; tree[j][3] = 0; } } void push(int node) { tree[2 * node + 1][3] += tree[node][3]; tree[2 * node + 2][3] += tree[node][3]; tree[node][3] = 0; } void update(int node, int a, int b, int val) { int l, r; l = tree[node][0]; r = tree[node][1]; if (l == a and r == b) { tree[node][3] += val; } else if (r >= a and b >= l) { push(node); update(2 * node + 1, a, min(b, (l + r) / 2), val); update(2 * node + 2, max(a, (l + r) / 2 + 1), b, val); tree[node][2] = (tree[node * 2 + 1][2] + tree[node * 2 + 1][3] + tree[node * 2 + 2][2] + tree[node * 2 + 2][3]); } } int query(int node, int a, int b) { int l, r; l = tree[node][0]; r = tree[node][1]; if (r < a || b < l) { return 0; } if (l == a && r == b) { return tree[node][2] + tree[node][3]; } push(node); ans = (query(node * 2 + 1, a, min(b, (l + r) / 2)) + query(node * 2 + 2, max(a, (l + r) / 2 + 1), b)); tree[node][2] = (tree[2 * node + 1][2] + tree[2 * node + 1][3] + tree[2 * node + 2][2] + tree[2 * node + 2][3]); return ans; } int main() { cin >> n >> k; n1 = pow(2, ceil(log2(n))); ; build(); long long answer = 1; int now = 1; for (int j = 0; j < n; j++) { update(0, now, now, 1); per1 = 0; per2 = 0; if (now + k > n) { if (k - 1 <= (n - 2) / 2) { if (now != n) { per2 = query(0, now + 1, n); } if (now + k - n >= 2) { per1 = query(0, 1, now + k - 1 - n); } answer += (1 + per1 + per2); } else { answer += (query(0, now + 1 + k - n, now - 1) + 1); } now = now + k - n; } else { if (k - 1 <= (n - 2) / 2) answer += (query(0, now + 1, now + k - 1) + 1); else { if (now + k != n) { per2 = query(0, now + k + 1, n); } if (now >= 2) { per1 = query(0, 1, now - 1); } answer += (1 + per1 + per2); } now += k; } cout << answer << ; update(0, now, now, 1); } return 0; }
|
#include <bits/stdc++.h> const int N = 500500; std::vector<int> g[N]; int d[N]; int n, maxM, maxD; void go(int cur, int par = -1, int dist = 0) { if (dist > maxD) maxD = dist; bool f = false; for (auto v : g[cur]) if (v != par) { go(v, cur, dist + 1); f = true; } if (!f) ++d[dist]; } int main() { scanf( %d , &n); for (int i = 1; i < n; ++i) { int x, y; scanf( %d%d , &x, &y); g[x].push_back(y); g[y].push_back(x); } for (auto v : g[1]) { for (int i = 0; i <= maxD; ++i) d[i] = 0; maxD = 0; go(v, 1); int p = -1; for (int i = 0; i <= maxD; ++i) if (d[i] > 0) { if (i > p) p = i + d[i] - 1; else p += d[i]; } if (p + 1 > maxM) maxM = p + 1; } printf( %d n , maxM); return 0; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FILL_FUNCTIONAL_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor2b (
Y ,
A ,
B_N
);
// Module ports
output Y ;
input A ;
input B_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y, not0_out, B_N );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAHCIN_TB_V
`define SKY130_FD_SC_HS__FAHCIN_TB_V
/**
* fahcin: Full adder, inverted carry in.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fahcin.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 B = 1'b1;
#160 CIN = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 B = 1'b0;
#260 CIN = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 CIN = 1'b1;
#380 B = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 CIN = 1'bx;
#480 B = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hs__fahcin dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAHCIN_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1000; int dist[N * N], memo[N * N]; vector<pair<int, int>> H, T; vector<int> ladj[N * N]; int vis[N * N]; inline int f(int x, int y) { return x * N + y; } int bfs(int start) { int n = N * N; fill(dist, dist + n, INT_MAX); fill(memo, memo + n, -1); dist[start] = 0; queue<int> Q; Q.push(start); while (!Q.empty()) { int u = Q.front(); Q.pop(); for (int i = 0; i < (int)ladj[u].size(); i++) { int v = ladj[u][i]; if (dist[v] > dist[u] + 1) { dist[v] = dist[u] + 1; Q.push(v); } } } return dist[0]; } bool hasCycle(int start) { if (vis[start] == -1) return true; if (vis[start]) return false; vis[start] = -1; for (int i = 0; i < (int)ladj[start].size(); i++) { int u = ladj[start][i]; if (hasCycle(u)) return true; } vis[start] = 1; return false; } int dp(int u) { int &ans = memo[u]; if (ans != -1) return ans; ans = 0; if (ladj[u].empty()) return 0; for (int i = 0; i < (int)ladj[u].size(); i++) { int v = ladj[u][i]; ans = max(ans, dp(v)); } return ++ans; } int main() { int h, t, r; cin >> h >> t >> r; int n; cin >> n; H.resize(n); for (int i = 0; i < n; i++) cin >> H[i].first >> H[i].second; int m; cin >> m; T.resize(m); for (int i = 0; i < m; i++) cin >> T[i].first >> T[i].second; for (int i = 0; i <= r; i++) for (int j = 0; j <= r; j++) if (i + j <= r) { for (int k = 1; k <= n && k <= i; k++) ladj[f(i, j)].push_back( f(i - k + H[k - 1].first, j + H[k - 1].second)); for (int k = 1; k <= m && k <= j; k++) ladj[f(i, j)].push_back( f(i + T[k - 1].first, j - k + T[k - 1].second)); } int start = f(h, t), ans = bfs(start); if (ans < INT_MAX) cout << Ivan << endl << ans << endl; else if (hasCycle(start)) cout << Draw << endl; else cout << Zmey << endl << dp(start) << endl; return 0; }
|
#include <bits/stdc++.h> char buf[1 << 21], *p1 = buf, *p2 = buf; using namespace std; template <class T> void rd(T &k) { char c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); int f = 1; k = 0; while (c < 0 || c > 9 ) { if (c == - ) f *= -1; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } while (c >= 0 && c <= 9 ) { k = k * 10 + c - 0 ; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } k *= f; } const int N = 300005; int n, m, k, t, x, a[N], f[N]; int c[N], d[N]; long long ans; char p[N]; queue<int> q; int ok(int x) { if (a[x] > 0 && c[x - 1] + 1 <= 9 && c[x] + 1 <= 9) return 1; if (a[x] < 0 && c[x - 1] - 1 >= 0 && c[x] - 1 >= 0) return 1; return 0; } int main() { cin >> n; cin >> p + 1; for (int i = 1; i <= n; ++i) c[i] = p[i] - 48; cin >> p + 1; for (int i = 1; i <= n; ++i) d[i] = p[i] - 48; for (register int i = 1; i < n; ++i) { a[i + 1] = d[i] - (c[i] + a[i]); ans += abs(a[i + 1]); } if (c[n] + a[n] != d[n]) return cout << -1, 0; cout << ans << n ; int xx = min(ans, 100000ll); for (register int i = 2; i <= n; ++i) { if (a[i] > 0 && c[i - 1] + 1 <= 9 && c[i] + 1 <= 9) q.push(i), f[i] = 1; if (a[i] < 0 && c[i - 1] - 1 >= 0 && c[i] - 1 >= 0) q.push(i), f[i] = 1; } int x; while (xx--) { x = q.front(); q.pop(); while (f[x] == 0) { x = q.front(); q.pop(); } if (a[x] > 0) { cout << x - 1 << 1 n ; ++c[x - 1]; ++c[x]; --a[x]; } else { cout << x - 1 << -1 n ; --c[x - 1]; --c[x]; ++a[x]; } if (ok(x)) q.push(x); else f[x] = 0; if (x >= 3) { if (ok(x - 1)) { if (f[x - 1] == 0) q.push(x - 1); f[x - 1] = 1; } else f[x - 1] = 0; } if (x <= n - 1) { if (ok(x + 1)) { if (f[x + 1] == 0) q.push(x + 1); f[x + 1] = 1; } else f[x + 1] = 0; } } }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:43:32 09/23/2013
// Design Name:
// Module Name: Data_Parameters
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Data_Parameters(clock, reset, mem_address, write_value_reg_en, write_data_selector, write_value);
input clock, reset, write_value_reg_en;
input [3:0] mem_address;
input [1:0] write_data_selector;
output reg [3:0] write_value;
// Valores que pueden escribirse en memoria
parameter CINCOH = 4'b0101;
parameter AH = 4'b1010;
parameter FH = 4'b1111;
//Valor obtenido del mux. Es el valor que se va a escribir
wire [3:0] mux_output;
//
initial
begin
write_value <= 4'b0000;
end
//El mux que selecciona el valor que se va a escribir en memoria
Mux_4x1 mod_selector_dato(mem_address, CINCOH, AH, FH ,write_data_selector, mux_output);
//Se guarda la salida del mux siempre que se active la escritura
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
write_value <= 4'b0000;
end
else if(write_value_reg_en)
begin
write_value <= mux_output;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct problem { int score1, score2; int time1, time2; double fail; long long expscore1, expscore2; double ratio; }; int N, T; problem P[1010]; long long dpscore[1010][1600]; double dppenal[1010][1600]; void update(int n, int t, long long score, double penal) { if (n <= N && t <= T && (score > dpscore[n][t] || (score == dpscore[n][t] && penal < dppenal[n][t]))) { dpscore[n][t] = score; dppenal[n][t] = penal; } } int main(void) { int i, j; cin >> N >> T; for ((i) = 0; (i) < (int)(N); (i)++) { cin >> P[i].score1 >> P[i].score2 >> P[i].time1 >> P[i].time2 >> P[i].fail; P[i].expscore1 = (long long)P[i].score1 * (long long)1000000; int tmp = (int)(P[i].fail * 1000000 + 0.5); P[i].expscore2 = (long long)P[i].score2 * (long long)(1000000 - tmp); P[i].ratio = ((tmp == 1000000) ? (1.0E+18) : (P[i].time2 * P[i].fail / (1.0 - P[i].fail))); } for ((i) = 0; (i) < (int)(N + 5); (i)++) for ((j) = 0; (j) < (int)(N - 1); (j)++) if (P[j].ratio > P[j + 1].ratio) swap(P[j], P[j + 1]); for ((i) = 0; (i) < (int)(N + 1); (i)++) for ((j) = 0; (j) < (int)(T + 1); (j)++) dpscore[i][j] = -1; dpscore[0][0] = 0; for ((i) = 0; (i) < (int)(N); (i)++) for ((j) = 0; (j) < (int)(T + 1); (j)++) if (dpscore[i][j] != -1) { long long score = dpscore[i][j]; double penal = dppenal[i][j]; update(i + 1, j, score, penal); update(i + 1, j + P[i].time1, score + P[i].expscore1, penal + P[i].time1); double fail_penalty = penal + P[i].time1; double ac_penalty = j + P[i].time1 + P[i].time2; update(i + 1, j + P[i].time1 + P[i].time2, score + P[i].expscore1 + P[i].expscore2, fail_penalty * P[i].fail + ac_penalty * (1.0 - P[i].fail)); } long long score = 0; double penal = 0.0; for ((i) = 0; (i) < (int)(T + 1); (i)++) { long long score2 = dpscore[N][i]; double penal2 = dppenal[N][i]; if (score2 > score || (score2 == score && penal2 < penal)) { score = score2; penal = penal2; } } printf( %.12f %.12f n , score / 1000000.0, penal); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n, m, c, a, b; int main() { scanf( %d , &n); while (n--) { scanf( %d%d , &a, &b); if (a != b) if (a > b) m++; else c++; } if (m != c) if (m > c) printf( Mishka ); else printf( Chris ); else printf( Friendship is magic!^^ ); return 0; }
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: unused_reg.v
// Project: NetFPGA
// Description: Unused register block
//
///////////////////////////////////////////////////////////////////////////////
module unused_reg
#(
parameter REG_ADDR_WIDTH = 5
)
(
// Register interface signals
input reg_req,
output reg_ack,
input reg_rd_wr_L,
input [REG_ADDR_WIDTH - 1:0] reg_addr,
output [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
reg reg_req_d1;
assign reg_rd_data = 'h dead_beef;
// Only generate an ack on a new request
assign reg_ack = reg_req && !reg_req_d1;
always @(posedge clk)
begin
reg_req_d1 <= reg_req;
end
endmodule // unused_reg
|
#include <bits/stdc++.h> using namespace std; const int N = 100100; const int BIT = 17; int n, m; int P[N]; int pot2[33]; set<int> S[18]; set<int>::iterator it; long long sol; inline int find(int bit, int pos) { if (S[bit].empty()) return 0; it = S[bit].lower_bound(pos); if (it == S[bit].begin()) return 0; it--; return *it + 1; } inline int find2(int bit, int pos) { if (S[bit].empty()) return n - 1; it = S[bit].lower_bound(pos); if (it == S[bit].end()) return n - 1; return *it - 1; } inline void load() { pot2[0] = 1; for (int i = 1; i <= BIT; i++) pot2[i] = (pot2[i - 1] << 1); scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { int x; scanf( %d , &P[i]); x = P[i]; for (int j = BIT; j >= 0; j--) { if (x & (1 << j)) { sol += (long long)pot2[j] * (i - find(j, i) + 1); } else S[j].insert(i); } } } inline void print() { printf( SADRZAJ NA MJESTU == %d n , 1); for (set<int>::iterator it = S[0].begin(); it != S[0].end(); it++) { printf( %d , *it); } printf( n ); system( pause ); } inline void solve() { for (; m; m--) { int pos, val; scanf( %d %d , &pos, &val); pos--; for (int j = BIT; j >= 0; j--) { if (val & (1 << j)) { if ((P[pos] & (1 << j)) == 0) { S[j].erase(pos); sol += (long long)pot2[j] * (pos - find(j, pos) + 1) * (find2(j, pos) - pos + 1); } } else { if ((P[pos] & (1 << j))) { int gore = pos - find(j, pos) + 1; int dole = find2(j, pos) - pos; sol -= (long long)pot2[j] * dole * gore; sol -= (long long)pot2[j] * gore; S[j].insert(pos); } } } P[pos] = val; cout << sol << endl; } } int main(void) { load(); solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int a; cin >> a; string s; cin >> s; map<int, int> Freq; for (int i = 0; i < s.size(); i++) { int sum = 0; bool zero = false; for (int j = i; j < s.size(); j++) { sum += (s[j] - 0 ); Freq[sum]++; } } long long ans = 0; if (a == 0) { for (int i = 0; i < s.size(); i++) { int sum = 0; for (int j = i; j < s.size(); j++) { sum += s[j] - 0 ; if (sum == 0) ans += (s.size() * (s.size() + 1)) / 2; else ans += Freq[0]; } } cout << ans; return 0; } for (auto &x : Freq) { if (x.first && a % x.first == 0) ans += (long long)Freq[a / x.first] * x.second; } cout << ans; return 0; }
|
#include <bits/stdc++.h> using namespace std; int x[7]; int y[7]; bool inside1(float x1, float y1) { if (x1 + .5 >= x[3] && x1 + .5 <= x[4] && y1 + .5 >= y[3] && y1 + .5 <= y[4]) return 1; return 0; } bool inside2(float x1, float y1) { if (x1 + .5 >= x[5] && x1 + .5 <= x[6] && y1 + .5 >= y[5] && y1 + .5 <= y[6]) return 1; return 0; } int main() { for (int i = 0; i < (int)(6); ++i) cin >> x[i + 1] >> y[i + 1]; for (int i = (y[1]); i < (int)(y[2]); ++i) { for (int j = (x[1]); j < (int)(x[2]); ++j) { if (inside1(j, i) && inside2(j, i)) { j = max(x[4], x[6]); if (j < x[2]) { cout << YES << endl; return 0; } } else if (inside1(j, i)) { j = x[4]; if (!inside2(j, i) && j < x[2]) { cout << YES << endl; return 0; } } else if (inside2(j, i)) { j = x[6]; if (!inside1(j, i) && j < x[2]) { cout << YES << endl; return 0; } } else { cout << YES << endl; return 0; } } } cout << NO << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O32A_PP_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; string a, ar, b, fi; int i, j, ans, o1[3000], o2[3000]; int main() { ios_base::sync_with_stdio(0); cin >> a >> b; ar = a; reverse(ar.begin(), ar.end()); for (; i < b.size(); ++i) { if (a.find(b[i]) == string::npos) { cout << -1 n ; return 0; } } for (i = 0; i < b.size();) { for (j = 1; i + j <= b.length(); ++j) { fi = b.substr(i, j); if (a.find(fi) == string::npos && ar.find(fi) == string::npos) { if (a.find(b.substr(i, j - 1)) == string::npos) { o1[ans] = a.length() - ar.find(b.substr(i, j - 1)); o2[ans] = a.length() - ar.find(b.substr(i, j - 1)) - j + 2; } else { o1[ans] = a.find(b.substr(i, j - 1)) + 1; o2[ans] = a.find(b.substr(i, j - 1)) + j - 1; } i += j - 1; ++ans; break; } else if (i + j == b.length()) { if (a.find(b.substr(i, j)) == string::npos) { o1[ans] = a.length() - ar.find(b.substr(i, j)); o2[ans] = a.length() - ar.find(b.substr(i, j)) - j + 1; } else { o1[ans] = a.find(b.substr(i, j)) + 1; o2[ans] = a.find(b.substr(i, j)) + j; } i += j; ++ans; } } } cout << ans << n ; for (i = 0; i < ans; ++i) cout << o1[i] << << o2[i] << n ; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAH_BLACKBOX_V
`define SKY130_FD_SC_MS__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAH_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; multimap<long long int, long long int> par; char en = n ; long long int inf = pow(10, 14); long long int mod = 1e9 + 7; long long int parent[2][500005]; long long int findRoot(long long int a, long long int which) { if (parent[which][a] == a) return a; parent[which][a] = findRoot(parent[which][a], which); return parent[which][a]; } void union1(long long int a, long long int b) { long long int root1 = findRoot(a, 0); long long int root2 = findRoot(b, 0); if (root1 == root2) return; long long int root11 = findRoot(a, 1); long long int root21 = findRoot(b, 1); if (root1 < root2) { parent[0][root1] = root2; } else { parent[0][root2] = root1; } if (root11 > root21) { parent[1][root11] = root21; } else { parent[1][root21] = root11; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n, m, p; cin >> n >> m >> p; string s; cin >> s; char arr[500005]; for (long long int i = 1; i < n + 1; i += 1) { arr[i] = s[i - 1]; parent[0][i] = parent[1][i] = i; } bool visited[500005]; memset(visited, (false), sizeof(visited)); string s1; cin >> s1; long long int curr = p; for (long long int i = 0; i < s1.length(); i += 1) { if (s1[i] == R ) { if (visited[curr + 1]) curr = findRoot(curr + 1, 0) + 1; else curr++; } else if (s1[i] == L ) { if (visited[curr - 1]) curr = findRoot(curr - 1, 1) - 1; else curr--; } else { if (arr[curr] == ( ) { stack<char> st; while (curr <= n) { visited[curr] = true; if (visited[curr - 1]) union1(curr - 1, curr); if (visited[curr + 1]) union1(curr + 1, curr); if (arr[curr] == ( ) { st.push( ( ); } else { st.pop(); } if (st.empty()) { long long int temp; temp = findRoot(curr, 0) + 1; if (temp > n) { temp = findRoot(curr, 1) - 1; } curr = temp; break; } curr = findRoot(curr, 0) + 1; } } else { stack<char> st; while (curr >= 1) { visited[curr] = true; if (visited[curr - 1]) union1(curr - 1, curr); if (visited[curr + 1]) union1(curr + 1, curr); if (arr[curr] == ) ) { st.push( ) ); } else { st.pop(); } if (st.empty()) { long long int temp; temp = findRoot(curr, 0) + 1; if (temp > n) { temp = findRoot(curr, 1) - 1; } curr = temp; break; } curr = findRoot(curr, 1) - 1; } } } } for (long long int i = 1; i < n + 1; i += 1) { if (!visited[i]) cout << arr[i]; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long fpm(long long b, long long e, long long m) { long long t = 1; for (; e; e >>= 1, b = b * b % m) e & 1 ? t = t * b % m : 0; return t; } template <class T> inline bool chkmin(T &a, T b) { return a > b ? a = b, true : false; } template <class T> inline bool chkmax(T &a, T b) { return a < b ? a = b, true : false; } template <class T> inline T sqr(T x) { return x * x; } template <class edge> struct Graph { vector<vector<edge> > adj; Graph(int n) { adj.clear(); adj.resize(n + 5); } Graph() { adj.clear(); } void resize(int n) { adj.resize(n + 5); } void add(int s, edge e) { adj[s].push_back(e); } void del(int s, edge e) { adj[s].erase(find((adj[s]).begin(), (adj[s]).end(), e)); } int deg(int v) { return adj[v].size(); } vector<edge> &operator[](int t) { return adj[t]; } }; struct crd { long double x, y, z; void read() { cin >> x >> y >> z; } void out() { cerr << ( << x << , << y << , << z << ) ; } crd operator^(crd &w) { return (crd){y * w.z - w.y * z, z * w.x - w.z * x, x * w.y - y * w.x}; } long double operator*(crd &w) { return x * w.x + y * w.y + z * w.z; } crd operator+(crd &w) { return (crd){x + w.x, y + w.y, z + w.z}; } crd operator-(crd &w) { return (crd){x - w.x, y - w.y, z - w.z}; } crd operator*(long double &w) { return (crd){x * w, y * w, z * w}; } long double len() { return sqrt(x * x + y * y + z * z); } }; crd A, p, O, v; long double R, r; long double sphere(crd o, long double r) { o = o - A; crd plane = o ^ v; crd vert = v ^ plane; long double mindis = o * vert / vert.len(); if (mindis > R + r || o * v < 0) return 1e300; o.out(), vert.out(), plane.out(), ({}); long double dist = o.len(); long double run = sqrt(sqr(dist) - sqr(mindis)) - sqrt(sqr(R + r) - sqr(mindis)); return run / v.len(); } int main() { ios_base::sync_with_stdio(false); long double ans = 1e300; A.read(), v.read(); v.out(), cerr << endl; int n, m; cin >> R >> n; for (int i = 1; i <= n; ++i) { O.read(); cin >> r >> m; ans = min(ans, sphere(O, r)); for (; m--;) p.read(), ans = min(ans, sphere(O + p, 0)); } cout << setprecision(15) << (ans > 1e200 ? -1 : ans) << endl; return 0; }
|
module fetch (clk, stall, busy, pc, rw, access_size, enable, j_addr, jump, br_addr, branch);
parameter START_ADDR = 32'h8002_0000;
// input
input clk;
input stall;
input busy;
input [31:0] j_addr;
input jump;
input [31:0] br_addr;
input branch;
// output
output [31:0] pc;
output [2:0] access_size;
output rw; //1 is write, 0 is read
output enable;
// local
reg [31:0] pc_reg = 32'h8001_FFFC; // current address
reg [2:0] access_size_reg = 3'b000;
reg rw_reg = 1'b0;
reg enable_reg = 1'b1;
// comb
assign pc = pc_reg;
assign access_size = access_size_reg;
assign rw = rw_reg;
assign enable = enable_reg;
// proc
always @(posedge clk)
begin
if(stall != 1 & busy != 1)
begin
if(jump != 1 & branch != 1)
begin
pc_reg = pc_reg + 32'h0000_0004;
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD(1000000007); const int INF((1 << 30) - 1); const int MAXN(); map<string, int> d; int main() { d[ void ] = 0; int n; scanf( %d , &n); for (int i = 0; i < n; i++) { string a, b, c; cin >> a; if (a == typedef ) { cin >> b >> c; int k1 = 0, k2 = b.size() - 1, m = 0; while (k1 < b.size() && b[k1] == & ) k1++, m--; while (k2 >= 0 && b[k2] == * ) k2--, m++; string t = b.substr(k1, k2 - k1 + 1); if (!d.count(t) || d[t] == -1 || d[t] + m < 0) d[c] = -1; else d[c] = d[t] + m; } else { cin >> b; int k1 = 0, k2 = b.size() - 1, m = 0; while (k1 < b.size() && b[k1] == & ) k1++, m--; while (k2 >= 0 && b[k2] == * ) k2--, m++; string t = b.substr(k1, k2 - k1 + 1); if (!d.count(t) || d[t] == -1 || d[t] + m < 0) printf( errtype n ); else { printf( void ); int l = d[t]; for (int j = 0; j < l + m; j++) printf( * ); printf( n ); } } } }
|
#include <bits/stdc++.h> using namespace std; int output(int n) { int sum = 0; while (n != 1) { int i; for (i = 2; i * i <= n; i++) if (n % i == 0) { sum += n; n /= i; break; } if (i * i > n) { sum += n; break; } } return ++sum; } int main() { int t; t = 1; while (t--) { int n; cin >> n; cout << output(n) << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; void solve() { string ss, tt; cin >> ss >> tt; int l = ss.size(); vector<int> s(30); vector<int> t(30); for (int i = 0; i < l; i++) { s[ss[i] - a ]++; t[tt[i] - a ]++; } bool ok = false; for (int i = 0; i < s.size(); i++) { if (s[i] && t[i]) { ok = true; } } cout << (ok ? YES n : NO n ); return; } int main() { int q; cin >> q; while (q--) { solve(); } }
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; double sqrDist(double x1, double y1, double x2, double y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } double dist(double x1, double y1, double x2, double y2) { return sqrt(sqrDist(x1, y1, x2, y2)); } const double PI = acos(-1.0); int main() { int x0, y0, v, t; scanf( %d%d%d%d , &x0, &y0, &v, &t); double r0 = 1.0 * v * t; int n; scanf( %d , &n); vector<pair<double, int> > a; for (int i = 0; i < n; i++) { int x, y, r; scanf( %d%d%d , &x, &y, &r); double d = sqrDist(x, y, x0, y0); if (d < 1.0 * r * r + eps) { printf( %.11f , 1.0); return 0; } d = sqrt(d); if (r + r0 < d - eps) { continue; } double angL, angR, ang; double angM = atan2(y - y0, x - x0); if (angM < 0) { angM += 2 * PI; } double tLen = sqrt(d * d - 1.0 * r * r); if (tLen < r0 + eps) { ang = asin(r / d); } else { ang = acos((d * d + r0 * r0 - 1.0 * r * r) / (2 * d * r0)); } angL = angM - ang; angR = angM + ang; if (angL < 0) { a.push_back(make_pair(angL + 2 * PI, 1)); a.push_back(make_pair(2 * PI, -1)); a.push_back(make_pair(0.0, 1)); a.push_back(make_pair(angR, -1)); } else if (angR > 2 * PI) { a.push_back(make_pair(angL, 1)); a.push_back(make_pair(2 * PI, -1)); a.push_back(make_pair(0.0, 1)); a.push_back(make_pair(angR - 2 * PI, -1)); } else { a.push_back(make_pair(angL, 1)); a.push_back(make_pair(angR, -1)); } } sort(a.begin(), a.end()); double last = 0; int c = 0; double ans = 0; for (auto& p : a) { if (c > 0) { ans += p.first - last; } c += p.second; last = p.first; } ans /= 2 * PI; printf( %.11f , ans); return 0; }
|
#include <bits/stdc++.h> #pragma GCC target( sse,sse2,sse3,ssse3,sse4,avx ) using namespace std; const int MAXSIZE = 10000020; int bufpos; char buf[MAXSIZE]; void init() { buf[fread(buf, 1, MAXSIZE, stdin)] = 0 ; bufpos = 0; } int readint() { int val = 0; for (; !isdigit(buf[bufpos]); bufpos++) ; for (; isdigit(buf[bufpos]); bufpos++) val = val * 10 + buf[bufpos] - 0 ; return val; } char readchar() { for (; isspace(buf[bufpos]); bufpos++) ; return buf[bufpos++]; } int readstr(char *s) { int cur = 0; for (; isspace(buf[bufpos]); bufpos++) ; for (; !isspace(buf[bufpos]); bufpos++) s[cur++] = buf[bufpos]; s[cur] = 0 ; return cur; } char bf[1 << 25], st[20], *w = bf; void flush() { fwrite(bf, 1, w - bf, stdout); w = bf; } inline void pc(register char c) { *w++ = c; } void print(register int n) { register char *t = st; do { *t++ = n % 10 + 48; } while (n /= 10); while (t-- > st) pc(*t); } int n, q, fa[66666], aa[66666], kh[66666], a[66666], p[66666], fp[66666], siz[66666], ck, pa[66666]; vector<int> edge[66666]; int dd[66666]; void dfs(int u) { siz[u] = 1; p[++ck] = u; fp[u] = ck; pa[ck] = fp[fa[u]]; dd[ck] = dd[pa[ck]] + 1; for (auto v : edge[u]) { dfs(v); siz[u] += siz[v]; } } int main() { init(); n = readint(); q = readint(); for (int i = 1; i <= n; ++i) { aa[i] = readint(); } for (int i = 2; i <= n; ++i) { fa[i] = readint(); edge[fa[i]].push_back(i); } dfs(1); for (int i = 1; i <= n; ++i) { a[fp[i]] = aa[i]; kh[i] = -50001; } for (int i = 1; i <= q; ++i) { int x = readint(); int y = siz[x]; x = fp[x]; int pp = i + 1, gg = y >> 3, *jj = kh + x, *diao = dd + x, *aa = a + x; int ans = 0, cnt = 0; for (int j = 0; j < gg; ++j, jj += 8, diao += 8, aa += 8) { int w; w = jj[0] + aa[0] < pp, jj[0] = w ? i : jj[0], ans += w * diao[0], cnt += w; w = jj[1] + aa[1] < pp, jj[1] = w ? i : jj[1], ans += w * diao[1], cnt += w; w = jj[2] + aa[2] < pp, jj[2] = w ? i : jj[2], ans += w * diao[2], cnt += w; w = jj[3] + aa[3] < pp, jj[3] = w ? i : jj[3], ans += w * diao[3], cnt += w; w = jj[4] + aa[4] < pp, jj[4] = w ? i : jj[4], ans += w * diao[4], cnt += w; w = jj[5] + aa[5] < pp, jj[5] = w ? i : jj[5], ans += w * diao[5], cnt += w; w = jj[6] + aa[6] < pp, jj[6] = w ? i : jj[6], ans += w * diao[6], cnt += w; w = jj[7] + aa[7] < pp, jj[7] = w ? i : jj[7], ans += w * diao[7], cnt += w; } gg <<= 3; for (int j = gg; j < y; ++j) { int w; w = jj[j - gg] + aa[j - gg] < pp, jj[j - gg] = w ? i : jj[j - gg], ans += w * diao[j - gg], cnt += w; ; } ans = ans - cnt * dd[x]; print(ans); pc( ); print(cnt); pc( n ); } flush(); }
|
#include <bits/stdc++.h> using namespace std; const long long nmax = (long long)1e6 + 10; inline long long up(char ch) { return z - ch; } inline long long lo(char ch) { return ch - a ; } inline long long eq(char ch) { return 1; } long long dp[2002][2002]; long long tmp[2002]; signed main() { ios_base ::sync_with_stdio(false); cin.tie(0); long long n, k; cin >> n >> k; string s; cin >> s; memset(dp, 0, sizeof dp); dp[n][0] = 1; for (long long i = n - 1; i >= 0; i--) { for (long long j = 0; j <= k; j++) { if (j - (n - i) >= 0) dp[i][j] = (up(s[i]) * dp[i + 1][j - (n - i)]) % 1000000007; dp[i][j] += (lo(s[i]) * dp[i + 1][j]) % 1000000007; dp[i][j] %= 1000000007; long long last = i; for (long long t = i + 1; t < n; t++) { if (j - (n - t) * (t - i + 1) >= 0) { dp[i][j] += (up(s[t]) * dp[t + 1][j - (n - t) * (t - i + 1)]) % 1000000007; dp[i][j] %= 1000000007; last = t; } else { break; } } for (long long t = n - 1; t > last; t--) { if (j - (n - t) * (t - i + 1) >= 0) { dp[i][j] += (up(s[t]) * dp[t + 1][j - (n - t) * (t - i + 1)]) % 1000000007; dp[i][j] %= 1000000007; } else { break; } } dp[i][j] += tmp[j]; dp[i][j] %= 1000000007; if (j == 0) { dp[i][j]++; dp[i][j] %= 1000000007; } tmp[j] = tmp[j] + (lo(s[i]) * dp[i + 1][j]) % 1000000007; tmp[j] %= 1000000007; } } cout << dp[0][k] << endl; return 0; }
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