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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_WIDTH = 18;
parameter B_WIDTH = 18;
parameter Y_WIDTH = 36;
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
MULT18X18D _TECHMAP_REPLACE_ (
.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]),
.B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]),
.C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0),
.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0),
.P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35])
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n >> x; int s = 0; for (int i = 0; i < n; ++i) { int a; cin >> a; s += a; } s += n - 1; if (s == x) { cout << YES << endl; } else { cout << NO << endl; } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long n, m, ans; int main() { scanf( %I64d%I64d , &n, &m); if (n > m) swap(n, m); if (n == 2) { if (m <= 2) ans = 0; else { ans = n * m; if (m == 3) ans -= 2; else if (m == 7) ans -= 2; } } else if (n == 1) { ans = n * m; long long t = ans % 6; if (t <= 3) ans -= t; else if (t == 4) ans -= 2; else if (t == 5) --ans; } else { ans = (n * m) - ((n * m) & 1); } printf( %I64d n , ans); return 0; }
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output [23:0] io_led, // LEDs on IO Shield
output [7:0] io_seg, // 7-segment LEDs on IO Shield
output [3:0] io_sel, // Digit select on IO Shield
input [3:0] F,
input en,
input [23:0] io_dip,
output [3:0] D,
output [3:0] Q,
output A,
output B,
output A_latch,
output B_latch
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
reg [26:0] slow_clk_d, slow_clk_q;
always @(slow_clk_q) begin
if (~io_dip[23] & ~io_dip[22]) begin
slow_clk_d = slow_clk_q + 2'b1;
end else if (io_dip[23] & ~io_dip[22]) begin
slow_clk_d = slow_clk_q + 2'b10;
end else if (~io_dip[23] & io_dip[22]) begin
slow_clk_d = slow_clk_q + 3'b100;
end else begin
slow_clk_d = slow_clk_q + 4'b1000;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 27'b0;
end
else begin
slow_clk_q <= slow_clk_d;
end
end
assign led[7:4] = {4{slow_clk_q[26]}};
assign io_led[23:0] = {24{slow_clk_q[26]}};
assign io_sel[3:0] = 4'b0000;
elevator real_deal (
.clk(slow_clk_q[26]),
.reset(rst),
.en(~en),
.F(F),
.D(D),
.Q(Q),
.A(A),
.B(B),
.A_latch(A_latch),
.B_latch(B_latch),
.LED(led[3:0]),
.io_seg(io_seg)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int c[100004], i, n, t, q, w, nr, r, d, s; char a[100004], b[100004]; int main() { scanf( %d %d n , &n, &t); for (i = 1; i <= n; i++) scanf( %c , &a[i]); scanf( n ); for (i = 1; i <= n; i++) scanf( %c , &b[i]); for (i = 1; i <= n; i++) { if (a[i] == b[i]) c[++nr] = i; } if ((n - nr) <= t) { for (i = 1; i <= n; i++) { if (a[i] != b[i]) { if (a[i] != a && b[i] != a ) printf( a ); else if (a[i] != b && b[i] != b ) printf( b ); else printf( c ); } else if (r < (n - t)) { printf( %c , a[i]); r++; } else { if (a[i] != a ) printf( a ); else printf( b ); } } } else { q = n - nr; if (q > (2 * t)) printf( %d , -1); else { s = (n - nr - t) * 2; if (s > q) printf( %d , s); else { for (i = 1; i <= n; i++) { if (a[i] != b[i]) { if (d < s) { if (d % 2 == 0) printf( %c , a[i]); else printf( %c , b[i]); d++; } else { if (a[i] != a && b[i] != a ) printf( a ); else if (a[i] != b && b[i] != b ) printf( b ); else printf( c ); } } else printf( %c , a[i]); } } } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const double PI = 3.141592653589793238463; const int N = 1e5 + 100; vector<int> v[N]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; int x; cin >> x; int r, l; for (int i = 1; i < x; i++) { cin >> r >> l; v[r].push_back(l); v[l].push_back(r); } bool ans = true; for (int i = 1; i <= x; i++) { if (v[i].size() == 2) { ans = false; break; } } cout << (ans ? YES : NO ); return 0; }
|
#include <bits/stdc++.h> using namespace std; signed main() { string s; cin >> s; char zero = 0 ; s = 00 + s; long long n = (long long)s.size(); for (long long i = 0; i < n - 2; i++) { long long temp = 100 * (s[i] - zero); for (long long j = i + 1; j < n - 1; j++) { temp += (10 * (s[j] - zero)); for (long long k = j + 1; k < n; k++) { temp += (s[k] - zero); if (temp % 8 == 0) { cout << YES << n ; cout << temp << n ; return 0; } temp -= (s[k] - zero); } temp -= (10 * (s[j] - zero)); } } cout << NO << n ; }
|
#include <bits/stdc++.h> using namespace std; map<long long, vector<long long> > mp; long long a[200005]; long long t[200005]; set<long long> s; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n; cin >> n; for (long long i = 0; i < n; i++) cin >> a[i], s.insert(a[i]); for (long long i = 0; i < n; i++) { cin >> t[i]; mp[a[i]].push_back(t[i]); } for (auto i : s) sort(mp[i].begin(), mp[i].end()); long long ans = 0; multiset<long long> temp; long long sum = 0; while (s.size()) { long long v = *s.begin(); s.erase(s.begin()); for (auto i : mp[v]) temp.insert(i), sum += i; auto p = s.lower_bound(v); long long nex = 1e18; if (p != s.end()) nex = *p; long long d = nex - v; long long siz = min(d, (long long)temp.size()); long long c = 0; while (siz--) { auto po = prev(temp.end()); ans += (*po) * c; c++; sum -= (*po); temp.erase(po); } ans += sum * c; } cout << ans; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long p, d, i, j, tmp, res; cin >> p >> d; res = p; for (i = 999999999999999999ll; i; i /= 10) { j = i + 1; if (i > p) continue; if (i == p) break; if (p % j == i) { tmp = (p / j) * j + i; if (p - tmp <= d) { res = tmp; break; } } else { tmp = (p / j - 1) * j + i; if (p - tmp <= d) { res = tmp; break; } } } cout << res << endl; return 0; }
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:51:11 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top RAT_xlslice_0_0 -prefix
// RAT_xlslice_0_0_ RAT_slice_1_0_0_stub.v
// Design : RAT_slice_1_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "xlslice,Vivado 2016.4" *)
module RAT_xlslice_0_0(Din, Dout)
/* synthesis syn_black_box black_box_pad_pin="Din[17:0],Dout[9:0]" */;
input [17:0]Din;
output [9:0]Dout;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// //
// Copyright 2006, 2007 Dennis van Weeren //
// //
// This file is part of Minimig //
// //
// Minimig is free software; you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published by //
// the Free Software Foundation; either version 3 of the License, or //
// (at your option) any later version. //
// //
// Minimig is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This is the bitplane parallel to serial converter & scroller //
// //
////////////////////////////////////////////////////////////////////////////////
module denise_bitplane_shifter
(
input wire clk, // 35ns pixel clock
input wire clk7_en, // 7MHz clock enable
input wire c1, // clock phase signals
input wire c3, // clock phase signals
input wire load, // load shift register signal
input wire hires, // high resolution select
input wire shres, // super high resolution select (takes priority over hires)
input wire [ 2-1:0] fmode, // AGA fetch mode
input wire [ 64-1:0] data_in, // parallel load data input
input wire [ 8-1:0] scroll, // scrolling value
output wire out // shift register output
);
// local signals
reg [ 6-1:0] fmode_mask; // fetchmode mask
reg [64-1:0] shifter; // main shifter
reg [64-1:0] scroller; // scroller shifter
reg shift; // shifter enable
reg [ 6-1:0] select; // shifter pixel select
wire scroller_out; // scroller output
reg [ 8-1:0] sh_scroller; // superhires scroller
reg [ 3-1:0] sh_select; // superhires scroller pixel select
// fetchmode mask
always @ (*) begin
case(fmode[1:0])
2'b00 : fmode_mask = 6'b00_1111;
2'b01,
2'b10 : fmode_mask = 6'b01_1111;
2'b11 : fmode_mask = 6'b11_1111;
endcase
end
// main shifter and scroller control
always @ (*) begin
if (shres) begin
// super hires mode
shift = 1'b1; // shifter always enabled
select[5:0] = scroll[5:0] & fmode_mask;
end else if (hires) begin
// hires mode
shift = ~c1 ^ c3; // shifter enabled every other clock cycle
select[5:0] = scroll[6:1] & fmode_mask;
end else begin
// lowres mode
shift = ~c1 & ~c3; // shifter enabled once every 4 clock cycles
select[5:0] = scroll[7:2] & fmode_mask;
end
end
// main shifter
always @ (posedge clk) begin
if (load && !c1 && !c3) begin
// load new data into shifter
shifter[63:0] <= data_in[63:0];
end else if (shift) begin
// shift already loaded data
shifter[63:0] <= {shifter[62:0],1'b0};
end
end
// main scroller
always @ (posedge clk) begin
if (shift) begin
// shift scroller data
scroller[63:0] <= {scroller[62:0],shifter[63]};
end
end
// main scroller output
assign scroller_out = scroller[select];
// superhires scroller control // TODO test if this is correct
always @ (*) begin
if (shres) begin
sh_select = 3'b011;
end else if (hires) begin
sh_select = {1'b1, scroll[0], 1'b1}; // MSB bit should probably be 0, this is a hack for kickstart screen ...
end else begin
sh_select = {1'b0, scroll[1:0]};
end
end
// superhires scroller
always @ (posedge clk) begin
sh_scroller[7:0] <= {sh_scroller[6:0], scroller_out};
end
// superhires scroller output
assign out = sh_scroller[sh_select];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_PP_BLACKBOX_V
|
//======================================================================
//
// avalanche_entropy.v
// -------------------
// Top level wrapper of the entropy provider core based on an external
// avalanche noise based source. (or any other source that can
// toggle a single bit input).
//
// Currently the design consists of a free running counter. At every
// positive flank detected the LSB of the counter is pushed into
// a 32bit shift register.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module avalanche_entropy(
input wire clk,
input wire reset_n,
input wire noise,
input wire cs,
input wire we,
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
input wire discard,
input wire test_mode,
output wire security_error,
output wire entropy_enabled,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h10;
parameter CTRL_ENABLE_BIT = 0;
parameter ADDR_STATUS = 8'h11;
parameter STATUS_ENABLE_VALID_BIT = 0;
parameter ADDR_ENTROPY = 8'h20;
parameter ADDR_DELTA = 8'h30;
parameter CORE_NAME0 = 32'h6578746e; // "extn"
parameter CORE_NAME1 = 32'h6f697365; // "oise"
parameter CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg enable_reg;
reg enable_new;
reg enable_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [31 : 0] delta;
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
assign security_error = 0;
assign entropy_enabled = enable_reg;
//----------------------------------------------------------------
// Core instantiation.
//----------------------------------------------------------------
avalanche_entropy_core core(
.clk(clk),
.reset_n(reset_n),
.noise(noise),
.enable(enable_reg),
.entropy_data(entropy_data),
.entropy_valid(entropy_valid),
.entropy_ack(entropy_ack),
.delta(delta),
.debug(debug),
.debug_update(debug_update)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
enable_reg <= 1;
end
else
begin
if (enable_we)
begin
enable_reg <= enable_new;
end
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//----------------------------------------------------------------
always @*
begin : api_logic
tmp_read_data = 32'h00000000;
tmp_error = 1'b0;
enable_new = 0;
enable_we = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
ADDR_CTRL:
begin
enable_new = write_data[CTRL_ENABLE_BIT];
enable_we = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_CTRL:
begin
tmp_read_data = {31'h00000000, enable_reg};
end
ADDR_STATUS:
begin
tmp_read_data = {31'h00000000, entropy_valid};
end
ADDR_ENTROPY:
begin
tmp_read_data = entropy_data;
end
ADDR_DELTA:
begin
tmp_read_data = delta;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // else: !if(we)
end // if (cs)
end // api_logic
endmodule // avalanche_entropy
//======================================================================
// EOF avalanche_entropy.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; int arr[100][100]; int row[100]; vector<pair<pair<int, int>, pair<int, int> > > v; int pos[30000][2]; int main() { int n; int sum = 0; while (scanf( %d , &n) == 1) { v.clear(); sum = 0; for (int i = 1; i <= n; i++) scanf( %d , &row[i]); for (int i = 1; i <= n; i++) { for (int j = 1; j <= row[i]; j++) { scanf( %d , &arr[i][j]); pos[arr[i][j]][0] = i; pos[arr[i][j]][1] = j; } sum += row[i]; } int cnt = 1; int swcnt = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= row[i]; j++) { if (arr[i][j] != cnt) { swcnt++; int r = pos[cnt][0]; int c = pos[cnt][1]; int val = arr[i][j]; arr[i][j] = cnt; arr[r][c] = val; pos[val][0] = r; pos[val][1] = c; pos[cnt][0] = i; pos[cnt][1] = j; v.push_back(make_pair(make_pair(i, j), make_pair(r, c))); } cnt++; } } printf( %d n , swcnt); for (int i = 0; i < ((int)v.size()); i++) printf( %d %d %d %d n , v[i].first.first, v[i].first.second, v[i].second.first, v[i].second.second); } }
|
#include <bits/stdc++.h> using namespace std; int main() { int n, count = 0; cin >> n; int home[n], guest[n]; for (int i = 0; i < n; ++i) { cin >> home[i] >> guest[i]; } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (home[i] == guest[j]) count++; } } cout << count; }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_PP_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire GATE ;
wire buf_Q ;
wire GATE_N_delayed;
wire D_delayed ;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
not not0 (GATE , GATE_N );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_FUNCTIONAL_PP_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e17; const int MAXM = 1e5 + 5; const int MAXN = 1e6 + 4; long long fact[MAXM]; long long nChoosek(long long n, long long k) { if (k > n) return 0; if (k * 2 > n) k = n - k; if (k == 0) return 1; long long result = n; for (long long i = 2; i <= k; ++i) { result *= (n - i + 1); result /= i; } return result; } int main() { long long n; cin >> n; long long Ans = 0; for (long long i = 5; i <= 7; i++) { Ans += nChoosek(n, i); } cout << Ans << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; long long M[110000 * 4]; long long lazy[110000 * 4]; void down(int x) { if (lazy[x] != -1) { M[x * 2] = max(M[x * 2], lazy[x]); M[x * 2 + 1] = max(M[x * 2 + 1], lazy[x]); lazy[x * 2] = max(lazy[x], lazy[x * 2]); lazy[x * 2 + 1] = max(lazy[x], lazy[x * 2 + 1]); lazy[x] = -1; } } void up(int x) { M[x] = max(M[x * 2], M[x * 2 + 1]); } void cover(int now, int l, int r, int x, int y, long long v) { down(now); if (x <= l && r <= y) { M[now] = v; lazy[now] = v; return; } int mid = (l + r) >> 1; if (x <= mid) cover(now * 2, l, mid, x, y, v); if (y > mid) cover(now * 2 + 1, mid + 1, r, x, y, v); up(now); } long long ask(int now, int l, int r, int x, int y) { down(now); if (x <= l && r <= y) return M[now]; int mid = (l + r) >> 1; long long res = 0; if (x <= mid) res = max(res, ask(now * 2, l, mid, x, y)); if (y > mid) res = max(res, ask(now * 2 + 1, mid + 1, r, x, y)); return res; } int main() { memset(lazy, -1, sizeof lazy); int n, m; scanf( %d , &n); for (int i = 1; i <= n; i++) { int v; scanf( %d , &v); cover(1, 1, n, i, i, v); } scanf( %d , &m); for (int i = 1; i <= m; i++) { int w, h; scanf( %d%d , &w, &h); long long res = ask(1, 1, n, 1, w); printf( %I64d n , res); cover(1, 1, n, 1, w, h + res); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; if (n == 1 || n == 2) { cout << -1 ; return 0; } else if (n % 2 == 1) { long long k = (n - 1) / 2; cout << 2 * k * k + 2 * k << << 2 * k * k + 2 * k + 1; } else { long long k = n / 2; cout << k * k - 1 << << k * k + 1; } return 0; }
|
//==================================================================================================
// Filename : KOA_c_v2.v
// Created On : 2016-10-06 00:34:18
// Last Modified : 2016-10-24 23:31:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: RKOA
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.03
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
//////////////////////////////////////////////////////////////////////////////////
module RKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
// localparam i;
// i = Stop_I;
////////////////////////////////////
`define STOP_SW1 3
`define STOP_SW2 4
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
RKOA #(.SW(SW/2) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
RKOA #(.SW(SW/2)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
`ifndef STRAT1
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
`endif
`ifdef STRAT2
assign result_A_adder = (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
assign result_B_adder = (Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2]);
`endif
RKOA #(.SW(SW/2+1) ) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
`ifndef STRAT1
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
`endif
`ifdef STRAT2
assign S_B = ((Q_middle[2*(SW/2)+1:0] - Q_left) - {zero1,Q_right[2*(SW/2)-1:0]});
`endif
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
assign sgf_result_o = Result[2*SW-1:0];
// assign sgf_result_o = {Q_left,Q_right[2*(SW/2)-1:0]} + {S_B[2*(SW/2)+1:0],rightside1};
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
RKOA #(.SW(SW/2) ) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
RKOA #(.SW((SW/2)+1) ) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
`ifndef STRAT3
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
`endif
`ifdef STRAT4
assign result_A_adder = (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
assign result_B_adder = Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
`endif
//multiplication for middle
RKOA #(.SW(SW/2+2) ) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
`ifndef STRAT3
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
`endif
`ifdef STRAT4
assign S_B = ((Q_middle - Q_left) - Q_right);
`endif
//Final adder
`ifndef STRAT3
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
`endif
`ifdef STRAT4
assign Result[4*(SW/2)+2:0] = {S_B,rightside2} + {Q_left,Q_right};
`endif
assign sgf_result_o = Result[2*SW-1:0];
//assign sgf_result_o = ({Q_left,Q_right} + {S_B,rightside2});
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:1024000000,1024000000 ) template <typename T> T Max(T a, T b) { return a > b ? a : b; } template <typename T> T Min(T a, T b) { return a < b ? a : b; } template <typename T> T Abs(T A) { return A > 0 ? A : -1 * A; } template <typename T> void Swap(T &a, T &b) { T tmp = a; a = b; b = tmp; } const long long LINF = 0x3FFFFFFFFFFFFFFLL; const int INF = 0X3FFFFFFF; const int MAXN = 1e5 + 5; long long sum[MAXN << 2][5]; int cnt[MAXN << 2]; char opt[MAXN][5]; int a[MAXN], c[MAXN]; inline void PushUp(int rt) { for (int i = 0; i < 5; i++) sum[rt][i] = sum[rt << 1][i] + sum[rt << 1 | 1][((i - cnt[rt << 1]) % 5 + 5) % 5]; } void Build(int l, int r, int rt) { cnt[rt] = 0; fill(sum[rt], sum[rt] + 5, 0); if (l == r) return; int m = (l + r) >> 1; Build(l, m, rt << 1); Build(m + 1, r, rt << 1 | 1); } void update(int pos, int val, int col, int l, int r, int rt) { if (col) cnt[rt]++; else cnt[rt]--; if (l == r) { sum[rt][0] = (long long)col * val; return; } int m = (l + r) >> 1; if (pos <= m) update(pos, val, col, l, m, rt << 1); else update(pos, val, col, m + 1, r, rt << 1 | 1); PushUp(rt); } int main() { int n; while (~scanf( %d , &n)) { int id = 0; for (int i = 1; i <= n; i++) { scanf( %s , opt[i]); if (opt[i][0] != s ) { scanf( %d , c + i); a[id++] = c[i]; } } sort(a, a + id); int num = unique(a, a + id) - a; if (num) Build(1, num, 1); else sum[1][2] = 0; for (int i = 1; i <= n; i++) { int pos = lower_bound(a, a + num, c[i]) - a + 1; if (opt[i][0] == a ) update(pos, c[i], 1, 1, num, 1); else if (opt[i][0] == d ) { if (cnt[1]) update(pos, c[i], 0, 1, num, 1); } else { if (cnt[1] == 0) sum[1][2] = 0; printf( %I64d n , sum[1][2]); } } } return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 10; const int INF = 1e9; int n; char s[maxn]; int P, M; struct node { int l, r; int left, right; } Tree[maxn]; int cur; vector<int> stk; void addNode(int x, bool flag) { ++cur; Tree[cur].l = x; if (!stk.empty()) { int par = stk.back(); if (!Tree[par].left) Tree[par].left = cur; else { assert(!Tree[par].right); Tree[par].right = cur; } } if (flag) stk.push_back(cur); else Tree[cur].r = x; } void buildTree() { for (int i = 0; i < n; ++i) { if (s[i] == ( || (s[i] != ? && s[i] != ) )) addNode(i, s[i] == ( ); else if (s[i] == ) ) { int v = stk.back(); Tree[v].r = i; stk.pop_back(); } } } long long dp[2][maxn][105]; bool mrk[2][maxn][105]; bool flag; long long f(int type, int v, int op) { if (!mrk[type][v][op]) { mrk[type][v][op] = true; if (!type) { if (Tree[v].l == Tree[v].r) return dp[type][v][op] = (!op) ? (s[Tree[v].l] - 0 ) : (-INF); dp[type][v][op] = -INF; int L = Tree[v].left; int R = Tree[v].right; if (op) { for (int x = 0; x <= 1; ++x) for (int y = 0; y <= 1; ++y) for (int i = 0; i <= op - 1; ++i) { if (abs(f(x, L, i)) == INF || abs(f(y, R, op - i - 1)) == INF) continue; if (flag) dp[type][v][op] = max(dp[type][v][op], f(x, L, i) - f(y, R, op - i - 1)); else dp[type][v][op] = max(dp[type][v][op], f(x, L, i) + f(y, R, op - i - 1)); } } for (int x = 0; x <= 1; ++x) for (int y = 0; y <= 1; ++y) for (int i = 0; i <= op; ++i) { if (abs(f(x, L, i)) == INF || abs(f(y, R, op - i)) == INF) continue; if (flag) dp[type][v][op] = max(dp[type][v][op], f(x, L, i) + f(y, R, op - i)); else dp[type][v][op] = max(dp[type][v][op], f(x, L, i) - f(y, R, op - i)); } } else { if (Tree[v].l == Tree[v].r) return dp[type][v][op] = (!op) ? (s[Tree[v].l] - 0 ) : (INF); dp[type][v][op] = INF; int L = Tree[v].left; int R = Tree[v].right; if (op) { for (int x = 0; x <= 1; ++x) for (int y = 0; y <= 1; ++y) for (int i = 0; i <= op - 1; ++i) { if (abs(f(x, L, i)) == INF || abs(f(y, R, op - i - 1)) == INF) continue; if (flag) dp[type][v][op] = min(dp[type][v][op], f(x, L, i) - f(y, R, op - i - 1)); else dp[type][v][op] = min(dp[type][v][op], f(x, L, i) + f(y, R, op - i - 1)); } } for (int x = 0; x <= 1; ++x) for (int y = 0; y <= 1; ++y) for (int i = 0; i <= op; ++i) { if (abs(f(x, L, i)) == INF || abs(f(y, R, op - i)) == INF) continue; if (flag) dp[type][v][op] = min(dp[type][v][op], f(x, L, i) + f(y, R, op - i)); else dp[type][v][op] = min(dp[type][v][op], f(x, L, i) - f(y, R, op - i)); } } } return dp[type][v][op]; } long long solve() { n = strlen(s); if (n == 1) return s[0] - 0 ; if (P > M) { flag = true; swap(P, M); } buildTree(); return f(0, 1, P); } int main() { scanf( %s %d %d , s, &P, &M); printf( %lld n , solve()); return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:38:55 02/11/2016
// Design Name:
// Module Name: PC_counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PC_counter
#(
parameter B=32 // ancho de la direccion (PC)
)
(
input wire clk,
input wire reset,
input wire ena,
input wire disa,
input wire [B-1:0] pc_branch, //PC para tomar el salto
input wire [B-1:0] pc_jump,
input wire PCSrc, //Senial de control para elegir el PC
input wire jump,
output wire [B-1:0] pc_out,
output wire [B-1:0] pc_incrementado
);
reg [B-1:0] pc; //registro PC
//mux mux_pc_src(.item_a(pc_incrementado), .item_b(pc_branch), .select(PCSrc), .signal(pc_wire));
adder add (
.value1(pc),
.value2(4),
.result(pc_incrementado)
);
always@(posedge clk)
if (reset)
pc <= 0; //Si entro por reset, resetea el PC
else
if (ena)
begin
if (disa == 1)
pc <= pc;//do nothing
else
begin
if (PCSrc == 1) pc <= pc_branch;
else if (jump == 1) pc <= pc_jump;
else pc <= pc_incrementado; //Si entro por clk, actualiza el PC con el nuevo valor
end
end
assign pc_out = pc;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100; char s[maxn]; int l; long long make(int x, long long u) { int z = l - x; long long k = 1, u1 = 0; for (int i = 0; i < z; i++) { u1 += (s[l - 1 - i] - 0 ) * k; k *= 10; } u1 += u / k * k; if (u1 <= u) u1 += k; return u1; } int main() { int t; cin >> t; while (t--) { scanf( %s , s); l = strlen(s); long long u = 1988; for (int i = l - 1; i >= 4; i--) { u = make(i, u); } cout << u << endl; } return 0; }
|
/*
* Phase accumulator clock generator:
* Output Frequency Fo = Fc * N / 2^bits
* Output Jitter = 1/Fc
*
* Copyright (c) 2009,2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module clk_gen #(
parameter res = 20, // bits - bit resolution
parameter phase = 1 // N - phase value for the counter
)(
input clk_i, // Fc - input frequency
input rst_i,
output clk_o // Fo - output frequency
);
// Registers and nets
reg [res-1:0] cnt;
// Continuous assignments
assign clk_o = cnt[res-1];
// Behaviour
always @(posedge clk_i)
cnt <= rst_i ? {res{1'b0}} : (cnt + phase);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:26 02/26/2016
// Design Name: signExt
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab4/test_signExt.v
// Project Name: lab4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: signExt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_signExt;
// Inputs
reg [15:0] inst;
// Outputs
wire [31:0] data;
// Instantiate the Unit Under Test (UUT)
signExt uut (
.inst(inst),
.data(data)
);
initial begin
// Initialize Inputs
inst = 0;
// Wait 100 ns for global reset to finish
#100;
inst = 16'b0000000011111010;
#100;
inst = 16'b1111111111111111;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int test, n; long long f[2000001][2]; const int P = 1000000007; int main() { memset(f, 0, sizeof(f)); f[3][0] = 0; f[3][1] = 4; for (int i = 4; i <= 2000000; i++) f[i][0] = max(f[i - 1][0], f[i - 1][1]) + max(f[i - 2][0], f[i - 2][1]) * 2, f[i][0] %= P, f[i][1] = 4 + f[i - 1][0] + 2 * f[i - 2][0], f[i][1] %= P; scanf( %d , &test); for (; test--;) { scanf( %d , &n); printf( %lld n , max(f[n][0], f[n][1])); } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4BB_FUNCTIONAL_V
|
#include <bits/stdc++.h> inline long long Input() { long long ret = 0; bool isN = 0; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) isN = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { ret = ret * 10 + c - 0 ; c = getchar(); } return isN ? -ret : ret; } inline void Output(long long x) { if (x < 0) { putchar( - ); x = -x; } int len = 0, data[20]; while (x) { data[len++] = x % 10; x /= 10; } if (!len) data[len++] = 0; while (len--) putchar(data[len] + 48); putchar( n ); } #pragma comment(linker, /STACK:124000000,124000000 ) const long double PI = acos(-1.0); using namespace std; int num[100005]; int shit[100005]; int a[100005], n; long long work1(int id) { memset(shit, 0, sizeof(shit)); if (num[a[(n + 1) / 2]] & 1) { int i; for (i = n / 2; i; i--) { if (a[i] != a[n + 1 - i]) break; } for (int j = id; j <= i; j++) { shit[a[j]]++; shit[a[n - j + 1]]--; } int j, cnt = 0; bool flag = 1; for (j = 0; j <= n; j++) { if (shit[j] != 0) { flag = 0; if (shit[j] < 0) cnt++; } } if (cnt == 0) return 1LL * id * (n - id + 1 - i); for (j = i + 1; j < n - i + 1; j++) { shit[a[j]] += 1; if (shit[a[j]] >= 0 && shit[a[j]] - 2 < 0) cnt--; if (cnt == 0) { return 1LL * id * (n - id + 1 - j); } } for (j = n - i + 1; j <= n; j++) { shit[a[j]] += 2; if (shit[a[j]] >= 0 && shit[a[j]] - 2 < 0) cnt--; if (cnt == 0) { return 1LL * id * (n - id + 1 - j); } } } else { for (int j = id; j <= (n + 1) / 2; j++) { shit[a[j]]++; shit[a[n - j + 1]]--; } shit[a[(n + 1) / 2]]++; int j, cnt = 0; bool flag = 1; for (j = 0; j <= n; j++) { if (shit[j] != 0) { if (shit[j] < 0) cnt++; } } if (cnt == 0) return 1LL * id * (n - id + 1 - (n + 1) / 2); for (j = n + 2 - (n + 1) / 2; j <= n; j++) { shit[a[j]] += 2; if (shit[a[j]] >= 0 && shit[a[j]] - 2 < 0) cnt--; if (cnt == 0) { return 1LL * id * (n - id + 1 - j); } } } } long long work2(int id) { memset(shit, 0, sizeof(shit)); int i; for (i = n / 2; i; i--) { if (a[i] != a[n + 1 - i]) break; } for (int j = id; j <= i; j++) { shit[a[j]]++; shit[a[n - j + 1]]--; } int j, cnt = 0; bool flag = 1; for (j = 0; j <= n; j++) { if (shit[j] != 0) { flag = 0; if (shit[j] < 0) cnt++; } } if (cnt == 0) return 1LL * id * (n - id + 1 - i); for (j = i + 1; j < n - i + 1; j++) { shit[a[j]] += 1; if (shit[a[j]] >= 0 && shit[a[j]] - 2 < 0) cnt--; if (cnt == 0) { return 1LL * id * (n - id + 1 - j); } } for (j = n - i + 1; j <= n; j++) { shit[a[j]] += 2; if (shit[a[j]] >= 0 && shit[a[j]] - 2 < 0) cnt--; if (cnt == 0) { return 1LL * id * (n - id + 1 - j); } } } long long solve() { long long ans = 0; int i, id; for (i = 1; i <= n; i++) { if (a[i] != a[n + 1 - i]) { ans = ans + 1LL * i * i; id = i; break; } } if (i == n + 1) return 1LL * n * (n + 1) / 2; if (n & 1) { ans = ans + work1(id); for (int i = 1; i <= n / 2; i++) swap(a[i], a[n + 1 - i]); ans = ans + work1(id); } else { ans = ans + work2(id); for (int i = 1; i <= n / 2; i++) swap(a[i], a[n + 1 - i]); ans = ans + work2(id); } return ans; } int main() { while (scanf( %d , &n) != EOF) { memset(num, 0, sizeof(num)); for (int i = 1; i <= n; i++) { scanf( %d , a + i); num[a[i]]++; } int cnt = 0; for (int i = 1; i <= n; i++) { if (num[i] & 1) cnt++; } if (cnt >= 2) { printf( 0 n ); continue; } printf( %I64d n , solve()); } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_1_V
`define SKY130_FD_SC_HVL__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; int a[3]; while (t--) { memset(a, 0, sizeof(a)); int n; cin >> n; for (int i = 0; i < n; i++) { int in; cin >> in; a[in % 3]++; } if (a[2] >= a[1]) { cout << a[0] + a[1] + ((a[2] - a[1]) / 3) << endl; } else { cout << a[0] + a[2] + ((a[1] - a[2]) / 3) << endl; } } return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_HD__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_BLACKBOX_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Barrier that handles multiple in-flight workgroups
//
// Partition Reorder fifo (actually just a RAM) into separate DEPTH sized
// spaces. When all the live workitems for a group id has arrived, tell the
// fifo to start emitting workitems for that hw group.
//
// Assumptions about data_entry:
// - data_entry[31:0]: hardware work-group id (in range [0, MAX_SIMULTANEOUS_WORKGROUPS-1])
// - data_entry[63:32]: local linear id (in range [0, workgroup_size-1])
//===----------------------------------------------------------------------===//
module acl_barrier (
clock,
resetn,
valid_entry,
data_entry,
stall_entry,
valid_exit,
data_exit,
stall_exit,
workgroup_size
);
parameter DATA_WIDTH=1024;
parameter DEPTH=256; // Does not have to be a power of 2
parameter MAX_SIMULTANEOUS_WORKGROUPS=2; // Does not have to be a power of 2
parameter WORKGROUP_SIZE_BITS = 10;
localparam LOG2_MAX_SIMULTANEOUS_WORKGROUPS=$clog2(MAX_SIMULTANEOUS_WORKGROUPS);
localparam WG_ID_BITS = LOG2_MAX_SIMULTANEOUS_WORKGROUPS > 0 ? LOG2_MAX_SIMULTANEOUS_WORKGROUPS : 1;
input clock;
input resetn;
input valid_entry;
input [DATA_WIDTH-1:0] data_entry;
output stall_entry;
output valid_exit;
output [DATA_WIDTH-1:0] data_exit;
input stall_exit;
input [WORKGROUP_SIZE_BITS-1:0] workgroup_size;
reg [WORKGROUP_SIZE_BITS-1:0] num_current_workitems[MAX_SIMULTANEOUS_WORKGROUPS-1:0];
wire [WORKGROUP_SIZE_BITS-1:0] num_current_workitems_[MAX_SIMULTANEOUS_WORKGROUPS-1:0]; //Create a copy that is a "wire" so that Modelsim will log it automatically
reg [WORKGROUP_SIZE_BITS-1:0] num_exiting_workitems;
wire valid_in;
wire valid_out;
wire stall_in;
wire stall_out;
wire [DATA_WIDTH-1:0] data_out;
wire [31:0] live_workitem_count_offset [MAX_SIMULTANEOUS_WORKGROUPS-1:0];
localparam s_IDLE=1'b0; //not outputing a workgroup
localparam s_LOCKED=1'b1;
reg present_state;
reg next_state;
reg valid_exit_pre, stall_in_pre;
// Force group id widths to 1-bit if only 1 SIMULTANEOUS_WORKGROUP
wire [WG_ID_BITS-1:0] hw_group_entering;
reg [WG_ID_BITS-1:0] hw_group_exiting;
generate
if (LOG2_MAX_SIMULTANEOUS_WORKGROUPS>0)
begin
assign hw_group_entering = data_entry[WG_ID_BITS-1:0];
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
hw_group_exiting <= '0;
else if (next_state==s_IDLE)
begin
// MAX_SIMULTANEOUS_WORKGROUPS might not be a power of 2 - handle
// wrap-around
if (hw_group_exiting == MAX_SIMULTANEOUS_WORKGROUPS - 1)
hw_group_exiting <= '0;
else
hw_group_exiting <= hw_group_exiting + 'd1;
end
end
assign data_exit = data_out;
end
else
begin
assign hw_group_entering=1'b0;
always @(posedge clock) hw_group_exiting=1'b0;
assign data_exit = data_out[DATA_WIDTH-1:0];
end
endgenerate
acl_fifo_reorder barrier_fifo_reorder (
.clock(clock),
.resetn(resetn),
.valid_in(valid_in),
.stall_in(stall_in),
.valid_out(valid_out),
.stall_out(stall_out),
.hw_group_exiting(hw_group_exiting),
.num_exiting_workitems(num_exiting_workitems),
.data_in(data_entry),
.data_out(data_out)
);
defparam barrier_fifo_reorder.WORKGROUP_SIZE_BITS = WORKGROUP_SIZE_BITS;
defparam barrier_fifo_reorder.DEPTH = DEPTH ;
defparam barrier_fifo_reorder.DATA_WIDTH = DATA_WIDTH;
defparam barrier_fifo_reorder.ADDR_WIDTH = 64; // 64-bits used by hw_wg_id and local_linear_id
defparam barrier_fifo_reorder.MAX_SIMULTANEOUS_WORKGROUPS = MAX_SIMULTANEOUS_WORKGROUPS;
// Compute num_current_workitems for each HW group
generate
genvar i;
for (i=0; i<MAX_SIMULTANEOUS_WORKGROUPS; i=i+1)
begin : numcur_gen
assign live_workitem_count_offset[i] = i*WORKGROUP_SIZE_BITS;
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
num_current_workitems[i] <= {WORKGROUP_SIZE_BITS{1'b0}};
end
else
begin
if (((valid_in && (~stall_out) && hw_group_entering==i) && ~(valid_out && ~stall_in && (hw_group_exiting==i))))
num_current_workitems[i] <= (num_current_workitems[i] + 2'b01);
else if (~((valid_in && (~stall_out) && hw_group_entering==i)) && (valid_out && ~stall_in && (hw_group_exiting==i)))
num_current_workitems[i] <= (num_current_workitems[i] - 2'b01);
end
end
//Modelsim by default ignores 2D reg's, so assign to an unconnected wire
assign num_current_workitems_[i] = num_current_workitems[i];
end
endgenerate
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
present_state <= s_IDLE;
else
present_state <= next_state;
end
always @(*)
begin
case (present_state)
s_IDLE:
next_state = ((|num_current_workitems[hw_group_exiting]) & (num_current_workitems[hw_group_exiting] == workgroup_size)) ?
s_LOCKED : s_IDLE;
s_LOCKED:
next_state = ((num_exiting_workitems == {{(WORKGROUP_SIZE_BITS-1){1'b0}},1'b1}) &&
valid_out && ~stall_in) ?
s_IDLE : s_LOCKED;
endcase
end
always @(posedge clock or negedge resetn)
begin
if (~(resetn)) begin
num_exiting_workitems <= {WORKGROUP_SIZE_BITS{1'b0}};
valid_exit_pre <= 1'b0;
stall_in_pre <= 1'b1;
end
else begin
case (present_state)
s_IDLE:
if (next_state==s_LOCKED) begin
num_exiting_workitems <= num_current_workitems[hw_group_exiting];
valid_exit_pre <= |num_current_workitems[hw_group_exiting]; // to help P&R
stall_in_pre <= ~|num_current_workitems[hw_group_exiting]; // to help P&R
end
else begin
num_exiting_workitems <= {WORKGROUP_SIZE_BITS{1'b0}};
valid_exit_pre <= 1'b0;
stall_in_pre <= 1'b1;
end
s_LOCKED:
if (valid_out && ~stall_in) begin
num_exiting_workitems <= (num_exiting_workitems - 2'b01);
valid_exit_pre <= num_exiting_workitems != 1;
stall_in_pre <= num_exiting_workitems == 1;
end
endcase
end
end
assign valid_in = valid_entry;
assign stall_entry = 1'b0; // If this ever stalls the program is broken
assign valid_exit = valid_out && valid_exit_pre;
assign stall_in = stall_exit | stall_in_pre;
endmodule
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the large XOR gate
*/
module large_xor (a,b,out);
// Output vector
output reg [14:0] out;
// Input vector
input [14:0] a;
// Another input vector
input [15:1] b;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=a[0]^b[1];
out[1]=a[1]^b[2];
out[2]=a[2]^b[3];
out[3]=a[3]^b[4];
out[4]=a[4]^b[5];
out[5]=a[5]^b[6];
out[6]=a[6]^b[7];
out[7]=a[7]^b[8];
out[8]=a[8]^b[9];
out[9]=a[9]^b[10];
out[10]=a[10]^b[11];
out[11]=a[11]^b[12];
out[12]=a[12]^b[13];
out[13]=a[13]^b[14];
out[14]=a[14]^b[15];
end
endmodule
module parity_stripper (in,out);
// Output vector
output reg [10:0] out;
// Input vector
input [14:0] in;
// Declare "reg" signals...
//reg [3:0] in_bar;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
out[0]=in[2];
out[1]=in[4];
out[2]=in[5];
out[3]=in[6];
out[4]=in[8];
out[5]=in[9];
out[6]=in[10];
out[7]=in[11];
out[8]=in[12];
out[9]=in[13];
out[10]=in[14];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); long long t; cin >> t; while (t--) { vector<vector<long long> > a(2); vector<long long> ans; long long n; string b; cin >> n >> b; long long cou = 1; for (char c : b) { long long x = c - 0 ; if (a[x].size() == 0) a[x].push_back(cou++); ans.push_back(a[x].back()); a[!x].push_back(a[x].back()); a[x].pop_back(); } cout << cou - 1 << n ; for (long long i : ans) cout << i << ; cout << n ; } return 0; }
|
// $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description :
// / /
// /__/ /\ Filename : MUXF9.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/unified/chen/g2ltw/g2ltw.pl
// Revision: 1.0
// 09/26/12 - 680234 - ncsim compile error
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MUXF9
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I0,
input I1,
input S
);
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_on GENCLK
reg [31:0] long;
reg [63:0] quad;
wire [31:0] longout;
wire [63:0] quadout;
wire [7:0] narrow = long[7:0];
sub sub (/*AUTOINST*/
// Outputs
.longout (longout[31:0]),
.quadout (quadout[63:0]),
// Inputs
.narrow (narrow[7:0]),
.quad (quad[63:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
long <= 32'h12345678;
quad <= 64'h12345678_abcdef12;
end
if (cyc==2) begin
if (longout !== 32'h79) $stop;
if (quadout !== 64'h12345678_abcdef13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
assign longout = $c32("(",narrow,"+1)");
assign quadout = $c64("(",quad,"+1)");
`else
assign longout = narrow + 8'd1;
assign quadout = quad + 64'd1;
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, k; cin >> n >> k; vector<long long int> a(n); for (long long int i = 0; i < n; i++) cin >> a[i]; long long int ans = -1e18; for (long long int i = 0; i < n; i++) { for (long long int j = i; j < n; j++) { vector<long long int> in, out; long long int sum = 0; for (long long int k = 0; k < n; k++) { if (k < i || k > j) out.push_back(a[k]); else in.push_back(a[k]), sum += a[k]; } sort((in).begin(), (in).end()); sort((out).rbegin(), (out).rend()); long long int l = 0, r = 0, s = k; while (l < (long long int)in.size() && r < (long long int)out.size() && s-- > 0) { if (in[l] < out[r]) sum += out[r] - in[l]; l++, r++; } ans = max(ans, sum); } } cout << ans << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int test_cases = 1; while (test_cases--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; template <typename T> void print(vector<T> v) { for (T &i : v) cout << i << ; cout << n ; } void solve() { unsigned long long int n, x; cin >> n >> x; vector<unsigned long long int> v(n); for (unsigned long long int &i : v) cin >> i; sort(v.begin(), v.end()); unsigned long long int sum = 0; for (unsigned long long int i : v) { sum += i * x; if (x > 1) x--; } cout << sum << n ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int tcs = 1; while (tcs--) solve(); return 0; }
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { static char _c; static bool _f; x = 0; _f = 0; _c = getchar(); while (_c < 0 || 9 < _c) { if (_c == - ) _f = true; _c = getchar(); } while ( 0 <= _c && _c <= 9 ) { x = (x << 1) + (x << 3) + (_c & 15); _c = getchar(); } if (_f) x = -x; } template <typename T> inline void Min(T &x, T y) { if (y < x) x = y; } template <typename T> inline void Max(T &x, T y) { if (x < y) x = y; } const int INF = 0x3f3f3f3f; const double pi = (double)acos(-1.0); const double eps = (double)1e-8; const int e5 = (int)1e5 + 5; const int MOD = (int)1e9 + 7; inline int sig(double x) { return x < -eps ? -1 : eps < x; } long long fp(long long a, long long n, long long mod = MOD) { if (n < 0) a = fp(a, mod - 2, mod), n = -n; long long res = 1; for (; n; n >>= 1, a = a * a % mod) if (n & 1) res = res * a % mod; return res; } struct Mint { int x; Mint() { x = 0; } Mint(int _x) : x(_x) { if (x < 0 || x >= MOD) x = (x % MOD + MOD) % MOD; } Mint(long long _x) : x(_x) { if (x < 0 || x >= MOD) x = (x % MOD + MOD) % MOD; } Mint operator-() const { return Mint(MOD - x); } Mint operator+(const Mint &rhs) const { return Mint(x + rhs.x >= MOD ? x + rhs.x - MOD : x + rhs.x); } Mint operator-(const Mint &rhs) const { return Mint(x - rhs.x < 0 ? x - rhs.x + MOD : x - rhs.x); } Mint operator*(const Mint &rhs) const { return Mint((long long)x * rhs.x % MOD); } Mint operator/(const Mint &rhs) const { return Mint(x * fp(rhs.x, -1) % MOD); } Mint &operator+=(const Mint &rhs) { x += rhs.x; if (x >= MOD) x -= MOD; return *this; } Mint &operator*=(const Mint &rhs) { x = ((long long)x * rhs.x) % MOD; return *this; } bool operator==(const Mint &rhs) const { return x == rhs.x; } bool operator!=(const Mint &rhs) const { return x != rhs.x; } friend ostream &operator<<(ostream &out, const Mint &rhs) { return out << rhs.x; } friend istream &operator>>(istream &in, Mint &rhs) { return in >> rhs.x; } }; const int maxn = (int)2e5 + 20; const int maxm = (int)1e6 + 20; const int N = 500 + 5; struct PQ_tree { int n, tot; int fail; vector<int> G[N << 2]; int ty[N << 2]; int sz[N << 2]; int szc[N << 2]; bool s[N]; inline int getstate(int u) { if (szc[u] == 0) return 0; if (szc[u] == sz[u]) return 2; return 1; } void addson(int x, int y) { if (y) G[x].push_back(y); } void join(int x, int y) { for (auto v : G[y]) G[x].push_back(v); } int mergeP(vector<int> &vec) { if (vec.size() == 0) return 0; if (vec.size() == 1) return vec[0]; G[++tot] = vec; return tot; } void init(int _n) { n = _n; tot = n + 1; memset(ty, 0, sizeof(ty)); for (int i = 1; i <= n; i++) G[n + 1].push_back(i); fail = 0; } void dfs(int u) { sz[u] = u <= n; szc[u] = u <= n && s[u]; for (auto v : G[u]) { dfs(v); sz[u] += sz[v]; szc[u] += szc[v]; } } int check(int u, int t) { if (fail) return 0; vector<int> vec[3]; for (auto v : G[u]) vec[getstate(v)].push_back(v); if (vec[1].size() > 2 || (t && vec[1].size() > 1)) return fail = 1, 0; if (t == 0 && vec[1].size() == 1 && vec[2].size() == 0) return check(vec[1][0], 0); if (ty[u] == 0) { int p2 = mergeP(vec[2]); if (t == 0) { G[u] = vec[0]; if (vec[1].size() == 0) addson(u, p2); else { int tmp1 = check(vec[1][0], 2); addson(tmp1, p2); if (vec[1].size() == 2) join(tmp1, check(vec[1][1], 1)); addson(u, tmp1); } return u; } else { ty[u] = 1; G[u].clear(); addson(u, p2); if (vec[1].size() == 1) join(u, check(vec[1][0], 1)); addson(u, mergeP(vec[0])); if (t == 2) reverse(G[u].begin(), G[u].end()); } return u; } else { if (getstate(G[u].front()) > getstate(G[u].back())) reverse(G[u].begin(), G[u].end()); int flag = 0; vector<int> tG; for (auto v : G[u]) { int sta = getstate(v); if (sta == 0) { if (flag == 1) flag = 2; tG.push_back(v); } else if (sta == 2) { if (flag == 0) flag = 1; else if (flag == 2) return fail = 2, 0; tG.push_back(v); } else { int p1; if (flag == 0) flag = 1, p1 = check(v, 2); else if (flag == 1) flag = 2, p1 = check(v, 1); else return fail = 3, 0; for (auto x : G[v]) tG.push_back(x); } } if (t && flag == 2) return fail = 4, 0; if (t == 1) reverse(tG.begin(), tG.end()); G[u] = tG; return u; } } void dfs_permutation(int u, vector<int> &per) { if (u <= n) per.push_back(u); for (auto v : G[u]) dfs_permutation(v, per); } vector<int> get_permutation() { vector<int> res; dfs_permutation(n + 1, res); return res; } void restrict(vector<int> res) { for (int i = 1; i <= n; i++) s[i] = 0; for (auto x : res) s[x] = 1; dfs(n + 1); check(n + 1, 0); } }; void work() { int n; cin >> n; PQ_tree *pq = new PQ_tree; pq->init(n); vector<string> s(n); for (int i = 0; i < n; i++) { cin >> s[i]; vector<int> res; for (int j = 0; j < n; j++) if (s[i][j] == 1 ) res.push_back(j + 1); pq->restrict(res); } if (pq->fail) { cout << NO << endl; } else { cout << YES << endl; vector<int> perm = pq->get_permutation(); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cout << s[i][perm[j] - 1]; cout << endl; } } delete pq; } int main(int argc, char **argv) { int tc = 1; for (int ca = 1; ca <= tc; ca++) { work(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; int n = s.length(); if (n <= 10) { cout << s << endl; } else { cout << s.at(0); cout << n - 2; cout << s.at(n - 1) << endl; } } }
|
#include <bits/stdc++.h> using namespace std; const int N = 400, D = 8; int vis[N][N]; int T[30]; bool used[N][N][D][6][31]; struct obj { int x, y, d, t, i; void move() { if (d == 0 || d == 1 || d == 7) x++; if (d == 5 || d == 4 || d == 3) x--; if (d == 1 || d == 2 || d == 3) y++; if (d == 5 || d == 6 || d == 7) y--; t--; } obj splitL() { return {x, y, (d + 1) % D, T[i + 1], i + 1}; } obj splitR() { return {x, y, (d + D - 1) % D, T[i + 1], i + 1}; } bool check(bool set = false) { if (set) used[x][y][d][t][i] = true; return used[x][y][d][t][i]; } }; queue<obj> q; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; for (int i = 0; i < n; i++) cin >> T[i]; q.push({N / 2, N / 2, 0, T[0] - 1, 0}); while (not q.empty()) { auto curr = q.front(); q.pop(); if (curr.check()) continue; curr.check(true); vis[curr.x][curr.y] = 1; if (curr.t == 0) { if (curr.i == n) continue; q.push(curr.splitL()); q.push(curr.splitR()); continue; } curr.move(); q.push(curr); } int ans = 0; for (int x = 0; x < N; x++) { for (int y = 0; y < N; y++) { ans += vis[x][y]; } } cout << ans << n ; return 0; }
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:31:46 04/05/2017
// Design Name:
// Module Name: DSP48E_1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DSP48E_1(
input signed [20:0] charge_in,
input signed [14:0] signal_in,
input delay_en,
input clk,
input store_strb,
output reg [12:0] DSPout,
input bunch_strb
);
(* equivalent_register_removal = "no"*) reg [7:0] j;
reg signed [47:0] DSPout_temp, DSPout_temp2,DSPout_temp4,DSPout_temp5;
reg signed [47:0] delayed =48'b0;
reg signed [47:0] delayed_a =48'b0;
reg signed [47:0] delayed_b =48'b0;
reg signed [12:0] DSPout_temp6;
//reg signed [47:0] delayed_c =48'b0;
initial DSPout=0;
//reg signed [20:0] charge_in_a;
//reg signed [14:0] signal_in_a;
always @ (posedge clk) begin
if (delay_en==1 & j<14) begin
//charge_in_a<=charge_in;
//signal_in_a<=signal_in;
DSPout_temp <= (charge_in*signal_in);
DSPout_temp2<=DSPout_temp;
DSPout_temp4<=DSPout_temp2;
DSPout_temp5<=DSPout_temp4+delayed;
DSPout_temp6 <= DSPout_temp5[24:12];
DSPout<=DSPout_temp6;
end
else begin
//charge_in_a<=charge_in;
//signal_in_a<=signal_in;
DSPout_temp <= (charge_in*signal_in);
DSPout_temp2<=DSPout_temp;
DSPout_temp4<=DSPout_temp2;
DSPout_temp5<=DSPout_temp4;
DSPout_temp6 <= DSPout_temp5[24:12];
DSPout<=DSPout_temp6;
end
end
// ***** Clk Counter after strobe *****
always @ (posedge clk) begin
//j<=j_a;
if (~bunch_strb) j<=j+1;
else j<=0;
end
always @ (posedge clk) begin
delayed<=delayed_a;
delayed_a<=delayed_b;
if (~store_strb) begin
delayed_b<=0;
end
else if (j==1) delayed_b<=DSPout_temp5;
else delayed_b<=delayed_b;
end
endmodule
|
//------------------------------------------------------------------------------
// File : tri_mode_eth_mac_v5_2_mod.v
// Author : Xilinx Inc.
//------------------------------------------------------------------------------
// Description: This package holds the top level component declaration
// for the Tri-Mode Ethernet MAC core.
// -----------------------------------------------------------------------------
// (c) Copyright 2002-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
module tri_mode_eth_mac_v5_2
(
//---------------------------------------
// asynchronous reset
input glbl_rstn,
input rx_axi_rstn,
input tx_axi_rstn,
//---------------------------------------
// Receiver Interface
input rx_axi_clk,
output rx_reset_out,
output [7:0] rx_axis_mac_tdata,
output rx_axis_mac_tvalid,
output rx_axis_mac_tlast,
output rx_axis_mac_tuser,
// Receiver Statistics
output [27:0] rx_statistics_vector,
output rx_statistics_valid,
//---------------------------------------
// Transmitter Interface
input tx_axi_clk,
output tx_reset_out,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
input tx_axis_mac_tuser,
output tx_axis_mac_tready,
output tx_retransmit,
output tx_collision,
input [7:0] tx_ifg_delay,
// Transmitter Statistics
output [31:0] tx_statistics_vector,
output tx_statistics_valid,
//---------------------------------------
// MAC Control Interface
input pause_req,
input [15:0] pause_val,
//---------------------------------------
// Current Speed Indication
output speed_is_100,
output speed_is_10_100,
//---------------------------------------
// Physical Interface of the core
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
input gmii_col,
input gmii_crs,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
// MDIO Interface
output mdc_out,
input mdio_in,
output mdio_out,
output mdio_tri,
//---------------------------------------
// IPIC Interface
input bus2ip_clk,
input bus2ip_reset,
input [31:0] bus2ip_addr,
input bus2ip_cs,
input bus2ip_rdce,
input bus2ip_wrce,
input [31:0] bus2ip_data,
output [31:0] ip2bus_data,
output ip2bus_wrack,
output ip2bus_rdack,
output ip2bus_error,
output mac_irq
);
endmodule // tri_mode_eth_mac_v5_2
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_TB_V
`define SKY130_FD_SC_HD__XOR3_TB_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__xor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_TB_V
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [16:0] c;
// Output of stage 2
wire [16:0] cx;
// Output of stage 3
wire [12:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [12:0] b;
reg [12:0] r_b;
reg [16:0] e;
reg [16:0] r_e;
// 2nd stage
reg [16:0] r_c;
reg [16:0] rr_e;
reg [12:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [16:0] cx;
//reg [10:0] qx;
reg [16:0] r_qx;
reg [12:0] rb;
reg clk,reset;
reg [16:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000100000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000001000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 17'b00000000000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
module Mux2(select,data_i00,data_i01,data_o);
parameter Size = 8;
input wire [('d1) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
output reg [(Size) - ('b1):0] data_o;
always @ (select or data_i00 or data_i01) begin
case (select)
'b0:data_o = data_i00;
'b1:data_o = data_i01;
endcase // case (select)
end
endmodule // Mux2
module Mux4(select,data_i00,data_i01,data_i02,data_i03,data_o);
parameter Size = 8;
input wire [('d2) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03) begin
case (select)
'b00: data_o = data_i00;
'b01: data_o = data_i01;
'b10: data_o = data_i02;
'b11: data_o = data_i03;
endcase
end
endmodule // Mux4
module Mux8(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_o);
parameter Size = 8;
input wire [('d3) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07) begin
case (select)
'b000: data_o = data_i00;
'b001: data_o = data_i01;
'b010: data_o = data_i02;
'b011: data_o = data_i03;
'b100: data_o = data_i04;
'b101: data_o = data_i05;
'b110: data_o = data_i06;
'b111: data_o = data_i07;
endcase
end
endmodule // Mux8
module Mux16(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_o);
parameter Size = 8;
input wire [('d4) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15) begin
case (select)
'b0000: data_o = data_i00;
'b0001: data_o = data_i01;
'b0010: data_o = data_i02;
'b0011: data_o = data_i03;
'b0100: data_o = data_i04;
'b0101: data_o = data_i05;
'b0110: data_o = data_i06;
'b0111: data_o = data_i07;
'b1000: data_o = data_i08;
'b1001: data_o = data_i09;
'b1010: data_o = data_i10;
'b1011: data_o = data_i11;
'b1100: data_o = data_i12;
'b1101: data_o = data_i13;
'b1110: data_o = data_i14;
'b1111: data_o = data_i15;
endcase
end
endmodule // Mux16
module Mux32(select,data_i00,data_i01,data_i02,data_i03,data_i04,data_i05,data_i06,data_i07,data_i08,data_i09,data_i10,data_i11,data_i12,data_i13,data_i14,data_i15,data_i16,data_i17,data_i18,data_i19,data_i20,data_i21,data_i22,data_i23,data_i24,data_i25,data_i26,data_i27,data_i28,data_i29,data_i30,data_i31,data_o);
parameter Size = 8;
input wire [('d5) - ('b1):0] select;
input wire [(Size) - ('b1):0] data_i00;
input wire [(Size) - ('b1):0] data_i01;
input wire [(Size) - ('b1):0] data_i02;
input wire [(Size) - ('b1):0] data_i03;
input wire [(Size) - ('b1):0] data_i04;
input wire [(Size) - ('b1):0] data_i05;
input wire [(Size) - ('b1):0] data_i06;
input wire [(Size) - ('b1):0] data_i07;
input wire [(Size) - ('b1):0] data_i08;
input wire [(Size) - ('b1):0] data_i09;
input wire [(Size) - ('b1):0] data_i10;
input wire [(Size) - ('b1):0] data_i11;
input wire [(Size) - ('b1):0] data_i12;
input wire [(Size) - ('b1):0] data_i13;
input wire [(Size) - ('b1):0] data_i14;
input wire [(Size) - ('b1):0] data_i15;
input wire [(Size) - ('b1):0] data_i16;
input wire [(Size) - ('b1):0] data_i17;
input wire [(Size) - ('b1):0] data_i18;
input wire [(Size) - ('b1):0] data_i19;
input wire [(Size) - ('b1):0] data_i20;
input wire [(Size) - ('b1):0] data_i21;
input wire [(Size) - ('b1):0] data_i22;
input wire [(Size) - ('b1):0] data_i23;
input wire [(Size) - ('b1):0] data_i24;
input wire [(Size) - ('b1):0] data_i25;
input wire [(Size) - ('b1):0] data_i26;
input wire [(Size) - ('b1):0] data_i27;
input wire [(Size) - ('b1):0] data_i28;
input wire [(Size) - ('b1):0] data_i29;
input wire [(Size) - ('b1):0] data_i30;
input wire [(Size) - ('b1):0] data_i31;
output reg [(Size) - ('b1):0] data_o;
always @ (select or
data_i00 or data_i01 or data_i02 or data_i03 or data_i04 or data_i05 or data_i06 or data_i07 or
data_i08 or data_i09 or data_i10 or data_i11 or data_i12 or data_i13 or data_i14 or data_i15 or
data_i16 or data_i17 or data_i18 or data_i19 or data_i20 or data_i21 or data_i22 or data_i23 or
data_i24 or data_i25 or data_i26 or data_i27 or data_i28 or data_i29 or data_i30 or data_i31) begin
case (select)
'b00000: data_o = data_i00;
'b00001: data_o = data_i01;
'b00010: data_o = data_i02;
'b00011: data_o = data_i03;
'b00100: data_o = data_i04;
'b00101: data_o = data_i05;
'b00110: data_o = data_i06;
'b00111: data_o = data_i07;
'b01000: data_o = data_i08;
'b01001: data_o = data_i09;
'b01010: data_o = data_i10;
'b01011: data_o = data_i11;
'b01100: data_o = data_i12;
'b01101: data_o = data_i13;
'b01110: data_o = data_i14;
'b01111: data_o = data_i15;
'b10000: data_o = data_i16;
'b10001: data_o = data_i17;
'b10010: data_o = data_i18;
'b10011: data_o = data_i19;
'b10100: data_o = data_i20;
'b10101: data_o = data_i21;
'b10110: data_o = data_i22;
'b10111: data_o = data_i23;
'b11000: data_o = data_i24;
'b11001: data_o = data_i25;
'b11010: data_o = data_i26;
'b11011: data_o = data_i27;
'b11100: data_o = data_i28;
'b11101: data_o = data_i29;
'b11110: data_o = data_i30;
'b11111: data_o = data_i31;
endcase
end
endmodule // Mux32
|
/**
* tb_draw_fifo.v: test bench for draw fifo
*/
module tb_draw_fifo;
localparam STEP = 2;
localparam REG_FIFO = 32'h0;
localparam REG_STATUS = 32'h4;
wire [15:0] x1, y1, x2, y2, x3, c1, c2, c3;
wire ap_rstn, ap_start;
reg ap_done;
wire ap_idle;
reg ap_clk;
reg s00_axi_aclk;
reg s00_axi_aresetn;
reg [2:0] s00_axi_awaddr;
reg [2:0] s00_axi_awprot = 3'h0;
reg s00_axi_awvalid;
wire s00_axi_awready;
reg [31:0] s00_axi_wdata;
reg [3:0] s00_axi_wstrb = 4'b1111;
reg s00_axi_wvalid;
wire s00_axi_wready;
wire [1:0] s00_axi_bresp;
wire s00_axi_bvalid;
reg s00_axi_bready;
reg [2:0] s00_axi_araddr;
reg [2:0] s00_axi_arprot = 3'h0;
reg s00_axi_arvalid;
wire s00_axi_arready;
wire [2:0] s00_axi_rdata;
wire [1:0] s00_axi_rresp;
wire s00_axi_rvalid;
reg s00_axi_rready;
reg [31:0] rdata = 32'h0;
reg [4:0] done_count = 5'd0;
reg ap_start_diff = 'b0;
reg [4:0] counter_start = 5'd30;
// connect to the draw fifo
draw_fifo_v1_0 draw_fifo_v1_0 (
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.x3(x3),
.c1(c1),
.c2(c2),
.c3(c3),
.ap_rstn(ap_rstn),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_ready(ap_done),
.ap_idle(ap_idle),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
// task for writing data
task write_data;
input [31:0] awaddr;
input [31:0] wdata;
begin
s00_axi_awaddr <= awaddr;
s00_axi_wdata <= wdata;
s00_axi_bready <= 'b0;
#(STEP);
s00_axi_awvalid <= 'b1;
s00_axi_wvalid <= 'b1;
#(STEP);
while (s00_axi_bvalid == 'b0) begin
#(STEP);
end
s00_axi_bready <= 'b1;
s00_axi_awvalid <= 'b0;
s00_axi_wvalid <= 'b0;
#(STEP)
s00_axi_bready <= 'b0;
end
endtask
// task for reading data
task read_data;
input [31:0] araddr;
begin
s00_axi_araddr = araddr;
s00_axi_rready <= 'b0;
#(STEP);
s00_axi_arvalid <= 'b1;
while (s00_axi_rvalid == 'b0) begin
#(STEP);
end
s00_axi_rready <= 'b1;
rdata = s00_axi_rdata;
#(STEP);
s00_axi_arvalid <= 'b0;
s00_axi_rready <= 'b0;
end
endtask
always @(posedge s00_axi_aclk) begin
ap_start_diff <= ap_start;
end
// mimic the end of the draw engine task
always @(posedge s00_axi_aclk) begin
if (~s00_axi_aresetn) begin
ap_done <= 'b0;
end
else if (~ap_done && ap_start && done_count == 5'd1) begin
ap_done <= 'b1;
end
else begin
ap_done <= 'b0;
end
end
always @(posedge s00_axi_aclk) begin
if (~s00_axi_aresetn)
done_count <= counter_start;
else if (ap_done && ap_start)
done_count <= counter_start;
else if (ap_start && ~ap_start_diff)
done_count <= counter_start;
else if (ap_start)
done_count <= (done_count == 5'd0) ? 5'd0 : (done_count - 5'd1);
else
done_count <= done_count;
end
assign ap_idle = ~ap_start && ~ap_done;
// clocks
always begin
s00_axi_aclk <= 'b0;
#(STEP / 2);
s00_axi_aclk = 'b1;
#(STEP / 2);
end
// start simulation
initial begin
s00_axi_aresetn <= 'b0;
counter_start <= 5'd30;
#(STEP * 2);
s00_axi_aresetn <= 'b1;
#(STEP * 2);
// wake up the engine
write_data(REG_STATUS, 32'h80000000);
#(STEP * 2);
// write 15 test data
write_data(REG_FIFO, 32'h00020001);
write_data(REG_FIFO, 32'h00040003);
write_data(REG_FIFO, 32'h00060005);
write_data(REG_FIFO, 32'h00080007);
write_data(REG_FIFO, 32'h00120011);
write_data(REG_FIFO, 32'h00140013);
write_data(REG_FIFO, 32'h00160015);
write_data(REG_FIFO, 32'h00180017);
write_data(REG_FIFO, 32'h00220021);
write_data(REG_FIFO, 32'h00240023);
write_data(REG_FIFO, 32'h00260025);
write_data(REG_FIFO, 32'h00280027);
write_data(REG_FIFO, 32'h00320031);
write_data(REG_FIFO, 32'h00340033);
write_data(REG_FIFO, 32'h00360035);
write_data(REG_FIFO, 32'h00380037);
write_data(REG_FIFO, 32'h00520051);
write_data(REG_FIFO, 32'h00540053);
write_data(REG_FIFO, 32'h00560055);
write_data(REG_FIFO, 32'h00580057);
#(STEP * 40);
write_data(REG_FIFO, 32'h00620061);
write_data(REG_FIFO, 32'h00640063);
write_data(REG_FIFO, 32'h00660065);
#(STEP * 10);
write_data(REG_FIFO, 32'h00680067);
counter_start <= 5'd1;
write_data(REG_FIFO, 32'h00820081);
write_data(REG_FIFO, 32'h00840083);
write_data(REG_FIFO, 32'h00860085);
write_data(REG_FIFO, 32'h00880087);
write_data(REG_FIFO, 32'h00920091);
write_data(REG_FIFO, 32'h00940093);
write_data(REG_FIFO, 32'h00960095);
write_data(REG_FIFO, 32'h00980097);
write_data(REG_FIFO, 32'h00a200a1);
write_data(REG_FIFO, 32'h00a400a3);
write_data(REG_FIFO, 32'h00a600a5);
write_data(REG_FIFO, 32'h00a800a7);
write_data(REG_FIFO, 32'h00b200b1);
write_data(REG_FIFO, 32'h00b400b3);
write_data(REG_FIFO, 32'h00b600b5);
write_data(REG_FIFO, 32'h00b800b7);
// wait fifo_next asserts
#(STEP * 20 * 4);
read_data(REG_FIFO);
// end of the simulation
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long f[500005]; int main() { string s; cin >> s; for (int i = 1; i <= s.size(); i++) f[i] = (s[i - 1] == I || s[i - 1] == O || s[i - 1] == E || s[i - 1] == A || s[i - 1] == U || s[i - 1] == Y ); for (int i = 1; i <= s.size(); i++) f[i] = f[i - 1] + f[i]; long long cur = 0; long double ans = 0; for (int i = 1; i <= s.size(); i++) cur += (f[s.size() - i + 1] - f[i - 1]), ans += (long double)cur / (long double)i; printf( %.10Lf , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; int n; void solve_1() { if (n < 6) { printf( -1 n ); return; } puts( 1 2 ); puts( 2 3 ); puts( 2 4 ); puts( 4 5 ); puts( 4 6 ); for (int i = 7; i <= n; i++) { printf( 2 %d n , i); } } void solve_2() { for (int i = 2; i <= n; i++) { printf( 1 %d n , i); } } int main() { scanf( %d , &n); solve_1(); solve_2(); }
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#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<tuple<int, int, int, int> > v(n); vector<int> used(n, 0); for (int i = 0; i < n; i++) { int a, b, c; cin >> a >> b >> c; v[i] = make_tuple(a, b, c, i); } sort(v.begin(), v.end()); map<pair<int, int>, vector<int> > m; for (int i = 0; i < n; i++) { pair<int, int> t = {get<0>(v[i]), get<1>(v[i])}; if (m.find(t) == m.end()) m[t] = vector<int>(); m[t].push_back(i); } for (auto t : m) { for (int i = 0; i + 1 < t.second.size(); i += 2) { cout << get<3>(v[t.second[i]]) + 1 << << get<3>(v[t.second[i + 1]]) + 1 << n ; used[get<3>(v[t.second[i]])] = 1; used[get<3>(v[t.second[i + 1]])] = 1; } } vector<tuple<int, int, int, int> > v1; for (int i = 0; i < v.size(); i++) { if (used[get<3>(v[i])] == 0) v1.push_back(v[i]); } map<int, vector<int> > m1; for (int i = 0; i < v1.size(); i++) { if (m1.find(get<0>(v1[i])) == m1.end()) { m1[get<0>(v1[i])] = vector<int>(); } m1[get<0>(v1[i])].push_back(i); } for (auto t : m1) { for (int i = 0; i + 1 < t.second.size(); i += 2) { cout << get<3>(v1[t.second[i]]) + 1 << << get<3>(v1[t.second[i + 1]]) + 1 << n ; used[get<3>(v1[t.second[i]])] = 1; used[get<3>(v1[t.second[i + 1]])] = 1; } } vector<tuple<int, int, int, int> > v2; for (int i = 0; i < v1.size(); i++) { if (used[get<3>(v1[i])] == 0) { v2.push_back(v1[i]); } } for (int i = 0; i < v2.size(); i += 2) { cout << get<3>(v2[i]) + 1 << << get<3>(v2[i + 1]) + 1 << n ; } }
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#include bits/stdc++.h using namespace std; #define ll long long #define Rip_classic_loki_for_glorious_purpose ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL) #pragma GCC target ( avx2 ) #pragma GCC optimization ( O3 ) #pragma GCC optimization ( unroll-loops ) // need for speed int main() { Rip_classic_loki_for_glorious_purpose; int t; cin >> t; while(t--){ int n,k,check; cin >> n >> k; int w = 0; for(int i = 0;i < n;i++){ cout << (i ^ w) << endl; cin >> check; if(check == 1){ break; } w = i; } } return 0; }
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_clkgen (
// mmcm reset
mmcm_rst,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ack_t,
drp_locked,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_VERSION = 32'h00040062;
parameter PCORE_ID = 0;
// mmcm reset
output mmcm_rst;
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ack_t;
input drp_locked;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_drp_sel_t = 'd0;
reg up_drp_rwn = 'd0;
reg [11:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg drp_sel_t_m1 = 'd0;
reg drp_sel_t_m2 = 'd0;
reg drp_sel_t_m3 = 'd0;
reg drp_sel = 'd0;
reg drp_wr = 'd0;
reg [11:0] drp_addr = 'd0;
reg [15:0] drp_wdata = 'd0;
reg up_drp_ack_t_m1 = 'd0;
reg up_drp_ack_t_m2 = 'd0;
reg up_drp_ack_t_m3 = 'd0;
reg up_drp_sel_t_d = 'd0;
reg up_drp_status = 'd0;
reg [15:0] up_drp_rdata = 'd0;
reg up_drp_locked_m1 = 'd0;
reg up_drp_locked = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire up_preset_s;
wire up_mmcm_preset_s;
wire drp_sel_t_s;
wire up_drp_ack_t_s;
wire up_drp_sel_t_s;
// decode block select
assign up_sel_s = (up_addr[13:8] == 6'h00) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_preset_s = ~up_resetn;
assign up_mmcm_preset_s = ~up_mmcm_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_drp_sel_t <= 'd0;
up_drp_rwn <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h10)) begin
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h1c)) begin
up_drp_sel_t <= ~up_drp_sel_t;
up_drp_rwn <= up_wdata[28];
up_drp_addr <= up_wdata[27:16];
up_drp_wdata <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h17: up_rdata <= {31'd0, up_drp_locked};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
8'h1d: up_rdata <= {15'd0, up_drp_status, up_drp_rdata};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// MMCM CONTROL
FDPE #(.INIT(1'b1)) i_mmcm_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_mmcm_preset_s),
.C (drp_clk),
.Q (mmcm_rst));
// DRP CONTROL
FDPE #(.INIT(1'b1)) i_drp_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (drp_clk),
.Q (drp_rst));
// drp control transfer
assign drp_sel_t_s = drp_sel_t_m2 ^ drp_sel_t_m3;
always @(posedge drp_clk) begin
if (drp_rst == 1'b1) begin
drp_sel_t_m1 <= 'd0;
drp_sel_t_m2 <= 'd0;
drp_sel_t_m3 <= 'd0;
end else begin
drp_sel_t_m1 <= up_drp_sel_t;
drp_sel_t_m2 <= drp_sel_t_m1;
drp_sel_t_m3 <= drp_sel_t_m2;
end
if (drp_sel_t_s == 1'b1) begin
drp_sel <= 1'b1;
drp_wr <= ~up_drp_rwn;
drp_addr <= up_drp_addr;
drp_wdata <= up_drp_wdata;
end else begin
drp_sel <= 1'b0;
drp_wr <= 1'b0;
drp_addr <= 12'd0;
drp_wdata <= 16'd0;
end
end
// drp status transfer
assign up_drp_ack_t_s = up_drp_ack_t_m3 ^ up_drp_ack_t_m2;
assign up_drp_sel_t_s = up_drp_sel_t ^ up_drp_sel_t_d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_drp_ack_t_m1 <= 'd0;
up_drp_ack_t_m2 <= 'd0;
up_drp_ack_t_m3 <= 'd0;
up_drp_sel_t_d <= 'd0;
up_drp_status <= 'd0;
up_drp_rdata <= 'd0;
up_drp_locked_m1 <= 'd0;
up_drp_locked <= 'd0;
end else begin
up_drp_ack_t_m1 <= drp_ack_t;
up_drp_ack_t_m2 <= up_drp_ack_t_m1;
up_drp_ack_t_m3 <= up_drp_ack_t_m2;
up_drp_sel_t_d <= up_drp_sel_t;
if (up_drp_ack_t_s == 1'b1) begin
up_drp_status <= 1'b0;
end else if (up_drp_sel_t_s == 1'b1) begin
up_drp_status <= 1'b1;
end
if (up_drp_ack_t_s == 1'b1) begin
up_drp_rdata <= drp_rdata;
end
up_drp_locked_m1 <= drp_locked;
up_drp_locked <= up_drp_locked_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
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#include <bits/stdc++.h> using namespace std; int n; int a[200005]; int mv; int main() { scanf( %d , &n); mv = n / 2; if (n % 2 == 0) mv--; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } sort(a + 1, a + n + 1); int ret = 2000000000; for (int i = 0; i <= mv; i++) { ret = min(ret, a[n - (mv - i)] - a[i + 1]); } printf( %d n , ret); return 0; }
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#include <bits/stdc++.h> using namespace std; int main() { int n, a = 0, b = 0, count = 0; char ch, c; cin >> n >> c; if (c == U ) b++; else a++; n--; while (n--) { cin >> ch; if (a == b && ch != c) { count++; c = ch; } if (ch == U ) b++; else a++; } cout << count; }
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#include <bits/stdc++.h> using namespace std; const int mx = 1e6 + 10, inf = 1e9 + 10; long long int t, n, ans, a[mx]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> t; while (t--) { cin >> n; cout << (n + 1) / 10 << endl; } return 0; }
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#include <bits/stdc++.h> using namespace std; using ll = long long; const ll N = 1e6 + 10; ll n, m, q, v; ll kl, ke; ll l[N]; ll e[N]; void umin(ll &a, ll b) { a = min(a, b); } signed main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> m; cin >> kl >> ke; cin >> v; for (ll i = 0; i < kl; ++i) { cin >> l[i]; } for (ll i = 0; i < ke; ++i) { cin >> e[i]; } sort(l, l + kl); sort(e, e + ke); cin >> q; while (q--) { ll x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (y1 > y2) { swap(x1, x2); swap(y1, y2); } ll ans = (ll)1e18; auto it = lower_bound(l, l + kl, y1); if (it != l + kl) { umin(ans, abs(y1 - *it) + abs(y2 - *it) + abs(x1 - x2)); } it = upper_bound(l, l + kl, y2); if (it != l) { --it; umin(ans, abs(y1 - *it) + abs(y2 - *it) + abs(x1 - x2)); } it = lower_bound(e, e + ke, y1); if (it != e + ke) { umin(ans, abs(y1 - *it) + abs(y2 - *it) + (abs(x1 - x2) + v - 1) / v); } it = upper_bound(e, e + ke, y2); if (it != e) { --it; umin(ans, abs(y1 - *it) + abs(y2 - *it) + (abs(x1 - x2) + v - 1) / v); } if (x1 == x2) { ans = abs(y1 - y2); } cout << ans << n ; } return 0; }
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#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long infinity = 1000000000000000000; const int inf = 1e9 + 5; bool do_debug = false; template <typename T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto element : v) { os << element << ; } return os; } template <typename T, typename S> ostream& operator<<(ostream& os, pair<T, S>& p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename T> ostream& operator<<(ostream& os, set<T>& v) { if (v.size() == 0) { os << empty set n ; return os; } auto endit = v.end(); endit--; os << [ ; for (auto it = v.begin(); it != v.end(); it++) { os << *it; if (it != endit) { os << , ; } } os << ] ; return os; } template <typename T> ostream& operator<<(ostream& os, multiset<T>& v) { if (v.size() == 0) { os << empty multiset n ; return os; } auto endit = v.end(); endit--; os << [ ; for (auto it = v.begin(); it != v.end(); it++) { os << *it; if (it != endit) { os << , ; } } os << ] ; return os; } template <typename T, typename S> ostream& operator<<(ostream& os, map<T, S>& v) { if (v.size() == 0) { os << empty map n ; return os; } auto endit = v.end(); endit--; os << { ; for (auto it = v.begin(); it != v.end(); it++) { os << ( << (*it).first << : << (*it).second << ) ; if (it != endit) { os << , ; } } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, vector<vector<T>>& v) { for (auto& subv : v) { for (auto& e : subv) { os << e << ; } os << n ; } return os; } const int maxn = 3e5 + 5; int n_nodes, n_edges, target; vector<vector<int>> adj; vector<array<int, 4>> edges; long long dist[maxn]; long long depth[maxn]; int incoming[maxn]; int added[maxn]; set<int> ans; long long ans_w; void dijkstra() { int node = target; priority_queue<pair<long long, long long>> pq; pq.push(make_pair(0, target)); while (!pq.empty()) { long long w = -pq.top().first; node = pq.top().second; pq.pop(); if (w > dist[node]) { continue; } for (int e : adj[node]) { int next = edges[e][1]; if (next == node) next = edges[e][2]; if (dist[node] + edges[e][0] < dist[next]) { if (incoming[next] != -1) { ans_w -= edges[incoming[next]][0]; ans.erase(incoming[next]); } incoming[next] = e; ans_w += edges[incoming[next]][0]; ans.insert(incoming[next]); dist[next] = dist[node] + edges[e][0]; pq.push(make_pair(-dist[next], next)); } else if (dist[node] + edges[e][0] == dist[next]) { if (edges[e][0] < edges[incoming[next]][0]) { ans_w -= edges[incoming[next]][0]; ans.erase(incoming[next]); incoming[next] = e; ans_w += edges[incoming[next]][0]; ans.insert(incoming[next]); } } } } } void mst() { int node = target; priority_queue<pair<long long, long long>> pq; for (int e : adj[node]) { int u = edges[e][1], v = edges[e][2]; if (u != node) swap(u, v); depth[v] = edges[e][0]; incoming[v] = e; ans_w += edges[e][0]; ans.insert(e); pq.push(make_pair(-edges[e][0], v)); } while (!pq.empty()) { long long d = -pq.top().first; node = pq.top().second; pq.pop(); for (int e : adj[node]) { long long w = edges[e][0]; int u = edges[e][1], v = edges[e][2]; if (u != node) swap(u, v); if (depth[u] + w == dist[v]) { if (incoming[v] == -1) { ans_w += w; ans.insert(e); incoming[v] = e; } else { if (w < edges[incoming[v]][0]) { ans_w -= edges[incoming[v]][0]; ans.erase(incoming[v]); incoming[v] = e; ans_w += edges[incoming[v]][0]; ans.insert(incoming[v]); } } depth[v] = dist[v]; } } } } void solve() { for (int i = 0; i < maxn; i++) { incoming[i] = -1; dist[i] = infinity; depth[i] = infinity; added[i] = 0; } cin >> n_nodes >> n_edges; adj.resize(n_nodes); for (int i = 0; i < n_edges; i++) { int w, u, v; cin >> u >> v >> w; u--; v--; adj[u].push_back(i); adj[v].push_back(i); edges.push_back({w, u, v, i}); } cin >> target; target--; dist[target] = 0; depth[target] = 0; ans_w = 0; dijkstra(); cout << ans_w << n ; for (int a : ans) { cout << a + 1 << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int q = 1; while (q-- > 0) { solve(); } return 0; }
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#include <bits/stdc++.h> const int N = 120005; int n, p[N], m; int stack1[N], top1, stack2[N], top2; struct query { int l, r, id; } q[N]; bool operator<(query a, query b) { return a.r < b.r; } int min[N << 2], num[N << 2], tag0[N << 2], tag1[N << 2]; long long sum[N << 2], ans[N]; void build(int o = 1, int l = 1, int r = n) { min[o] = l, num[o] = 1; if (l == r) return; int mid = l + r >> 1; build(o << 1, l, mid), build(o << 1 | 1, mid + 1, r); } void settag0(int o, int v) { tag0[o] += v, min[o] += v; } void settag1(int o, int v) { sum[o] += (long long)v * num[o], tag1[o] += v; } void pushdown(int o) { if (tag0[o]) settag0(o << 1, tag0[o]), settag0(o << 1 | 1, tag0[o]), tag0[o] = 0; if (tag1[o]) { if (min[o] == min[o << 1]) settag1(o << 1, tag1[o]); if (min[o] == min[o << 1 | 1]) settag1(o << 1 | 1, tag1[o]); tag1[o] = 0; } } void pushup(int o) { min[o] = std::min(min[o << 1], min[o << 1 | 1]); num[o] = 0; if (min[o] == min[o << 1]) num[o] += num[o << 1]; if (min[o] == min[o << 1 | 1]) num[o] += num[o << 1 | 1]; sum[o] = sum[o << 1] + sum[o << 1 | 1]; } void modify(int L, int R, int v, int o = 1, int l = 1, int r = n) { if (L <= l && R >= r) return settag0(o, v); int mid = l + r >> 1; pushdown(o); if (L <= mid) modify(L, R, v, o << 1, l, mid); if (R > mid) modify(L, R, v, o << 1 | 1, mid + 1, r); pushup(o); } long long query(int L, int o = 1, int l = 1, int r = n) { if (L == l) return sum[o]; int mid = l + r >> 1; pushdown(o); if (L <= mid) return query(L, o << 1, l, mid) + sum[o << 1 | 1]; else return query(L, o << 1 | 1, mid + 1, r); } int main() { std::ios::sync_with_stdio(0), std::cin.tie(0); std::cin >> n; for (int i = 1; i <= n; ++i) std::cin >> p[i]; std::cin >> m; for (int i = 0; i < m; ++i) std::cin >> q[i].l >> q[i].r, q[i].id = i; build(), std::sort(q, q + m); int t = 0; for (int i = 1; i <= n; ++i) { while (top1 && p[stack1[top1]] < p[i]) modify(stack1[top1 - 1] + 1, stack1[top1], p[i] - p[stack1[top1]]), --top1; while (top2 && p[stack2[top2]] > p[i]) modify(stack2[top2 - 1] + 1, stack2[top2], p[stack2[top2]] - p[i]), --top2; stack1[++top1] = stack2[++top2] = i, settag1(1, 1); while (t < m && q[t].r == i) ans[q[t].id] = query(q[t].l), ++t; } for (int i = 0; i < m; ++i) std::cout << ans[i] << n ; return 0; }
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#include <bits/stdc++.h> using namespace std; inline int read() { long long f = 1; long long x = 0; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * f; }; const int maxn = 1e4 + 5; int res[maxn]; int main() { int n = read(), d = read(), l = read(); int up, dw; up = (n / 2 + (n & 1)) * l - (n / 2); dw = (n / 2 + (n & 1)) - (n / 2) * l; if (d < dw || d > up) { printf( -1 ); return 0; } for (int i = 1, now = up; i <= n; ++i) { if (now == d) { printf( %d , i & 1 ? l : 1); continue; } int del = min(now - d, l - 1); if (i & 1) { printf( %d , l - del); now -= del; } else { printf( %d , 1 + del); now -= del; } } return 0; }
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// MBT 11/9/2014
//
// Synchronous 2-port ram.
//
// When read and write with the same address, the behavior depends on which
// clock arrives first, and the read/write clock MUST be separated at least
// twrcc, otherwise will incur indeterminate result.
//
// See "TSN45GS2PRF: TSMC 45nm (=N40G) General Purpose Superb Two-Port
// Register File Compiler Databook"
//
`define bsg_mem_1r1w_sync_macro_rf(words,bits,lgEls,newBits,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
wire [newBits-1:0] tmp_lo,tmp_li; \
assign r_data_o = tmp_lo[bits-1:0]; \
assign tmp_li = newBits ' (w_data_i); \
\
tsmc40_2rf_lg``lgEls``_w``bits``_m``mux``_all mem \
( \
.AA ( w_addr_i ) \
,.D ( tmp_li ) \
,.BWEB ( {``newBits``{1'b0}} ) \
,.WEB ( ~w_v_i ) \
,.CLKW ( clk_i ) \
\
,.AB ( r_addr_i ) \
,.REB ( ~r_v_i ) \
,.CLKR ( clk_i ) \
,.Q ( tmp_lo ) \
\
,.RDELAY ( 2'b00 ) \
,.WDELAY ( 2'b00 ) \
); \
end
module bsg_mem_1r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=$clog2(els_p)
// whether to substitute a 1r1w
, parameter read_write_same_addr_p= 0
, parameter substitute_1r1w_p=1)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_macro_rf(128,74,7,74,2) else
`bsg_mem_1r1w_sync_macro_rf(128,73,7,74,2) else
`bsg_mem_1r1w_sync_macro_rf(128,72,7,72,2) else
`bsg_mem_1r1w_sync_macro_rf(128,71,7,72,2) else
`bsg_mem_1r1w_sync_macro_rf(128,70,7,70,2) else
`bsg_mem_1r1w_sync_macro_rf(128,69,7,70,2) else
`bsg_mem_1r1w_sync_macro_rf(128,68,7,68,2) else
`bsg_mem_1r1w_sync_macro_rf(128,67,7,68,2) else
`bsg_mem_1r1w_sync_macro_rf(128,66,7,66,2) else
`bsg_mem_1r1w_sync_macro_rf(128,65,7,66,2) else
`bsg_mem_1r1w_sync_macro_rf(128,64,7,64,2) else
`bsg_mem_1r1w_sync_macro_rf(128,63,7,64,2) else
`bsg_mem_1r1w_sync_macro_rf(128,62,7,62,2) else
`bsg_mem_1r1w_sync_macro_rf(128,61,7,62,2) else
`bsg_mem_1r1w_sync_macro_rf(128,16,7,16,2) else
`bsg_mem_1r1w_sync_macro_rf(64 ,48,6,48,2) else
begin : z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1r1w synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(0)
) mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (w_v_i & w_v_i)
,.w_addr_i (w_addr_i)
,.w_data_i (w_data_i)
,.r_addr_i (r_addr_i)
,.r_v_i (r_v_i & ~r_v_i)
,.r_data_o (data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i)
r_data_o <= data_lo;
end // block: subst
else
begin: notmacro
bsg_mem_1r1w_sync_synth
# (.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
assert ( read_write_same_addr_p == 0) else begin
$error("## The hard memory do not support read write the same address. (%m)");
$finish;
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync)
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s = 0; cin >> n; int a[n]; for (int x = 0; x < n; ++x) { cin >> a[x]; s += a[x] * (x + 1); } cout << s << endl; return 0; }
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long a = 0, b = 1; char c = getchar(); while (!isdigit(c)) { if (c == - ) b = -1; c = getchar(); } while (isdigit(c)) { a = a * 10 + c - 0 ; c = getchar(); } return a * b; } const long long N = 3e5 + 50, M = 6e5 + 50; long long n, m, w[N], tot, h[N], nx[M], ver[M], ed[M], dat[N * 8], lazy[N * 8], ans; void add(long long u, long long v, long long z) { ver[++tot] = v; ed[tot] = z; nx[tot] = h[u]; h[u] = tot; } void spread(long long p) { if (lazy[p]) { dat[(p << 1)] += lazy[p]; dat[(p << 1 | 1)] += lazy[p]; lazy[(p << 1)] += lazy[p]; lazy[(p << 1 | 1)] += lazy[p]; lazy[p] = 0; } } void change(long long p, long long l, long long r, long long u, long long v, long long z) { if (l >= u && r <= v) { dat[p] += z; lazy[p] += z; return; } spread(p); long long mid = (l + r) >> 1; if (u <= mid) change((p << 1), l, mid, u, v, z); if (v > mid) change((p << 1 | 1), mid + 1, r, u, v, z); dat[p] = max(dat[(p << 1)], dat[(p << 1 | 1)]); } signed main() { n = read(); m = read(); for (register long long i = 1; i <= n; i++) { w[i] = read(); } for (register long long i = 1, u, v, z; i <= m; i++) { u = read(); v = read(); z = read(); add(v, u, z); } for (register long long i = 1; i <= n; i++) { change(1, 1, n, i, i, ans); change(1, 1, n, 1, i, -w[i]); for (register long long j = h[i]; j; j = nx[j]) { change(1, 1, n, 1, ver[j], ed[j]); } ans = max(ans, dat[1]); } printf( %lld n , ans); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int M = 1e6 + 10; int n, ans; void swap(int &x, int &y) { int t = x; x = y; y = t; } int main() { cin >> n; vector<char> x(n), y(n); for (auto &i : x) cin >> i; for (auto &i : y) cin >> i; for (int i = 0; i < n - 1; ++i) { if (x[i] == y[i]) continue; if (x[i + 1] == y[i + 1]) { ans++; continue; } if (x[i] == y[i + 1] && x[i + 1] == y[i]) swap(x[i], x[i + 1]), ans++; else ans++; } if (x[n - 1] != y[n - 1]) ans++; cout << ans; return 0; }
|
`default_nettype none
// Copyright 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module manual_macro_placement_test(
clk1,
clk2,
rst1,
rst2,
x1,
x2,
y1,
y2,
p1,
p2
);
parameter size = 32;
input clk1, rst1;
input clk2, rst2;
input y1;
input y2;
input[size-1:0] x1;
input[size-1:0] x2;
output p1;
output p2;
spm spm_inst_0 (.clk(clk1), .rst(rst1), .x(x1), .y(y1), .p(p1));
spm spm_inst_1 (.clk(clk2), .rst(rst2), .x(x2), .y(y2), .p(p2));
endmodule
(* blackbox *)
module spm(clk, rst, x, y, p);
parameter size = 32;
input clk, rst;
input y;
input[size-1:0] x;
output p;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a, b, t, p, i; int main() { cin >> n >> a >> b; p = b * n; while (n > 1) { t += 2 * a + 1; n--; } cout << t << << p; return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5, inf = 1e9; int a[maxn]; struct segtree { int lb, rb; int mn = 0; segtree *l, *r; segtree(int _lb, int _rb) { lb = _lb, rb = _rb; if (lb == rb) mn = a[lb]; else { int t = (lb + rb) / 2; l = new segtree(lb, t); r = new segtree(t + 1, rb); mn = min(l->mn, r->mn); } } int rmq(int lq, int rq) { if (lb >= lq && rb <= rq) return mn; else if (lb > rq || rb < lq) return inf; return min(l->rmq(lq, rq), r->rmq(lq, rq)); } }; segtree *p; vector<pair<int, int> > ans; void solve(int l, int r, int d) { if (l > r) return; int mn = p->rmq(l, r); while (mn > d) ans.push_back({l + 1, r + 1}), d++; int lb = l, rb = r; while (lb != rb) { int t = (lb + rb) / 2; if (p->rmq(l, t) == d) rb = t; else lb = t + 1; } solve(l, lb - 1, d); solve(lb + 1, r, d); } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; p = new segtree(0, n - 1); solve(0, n - 1, 0); cout << ans.size() << n ; for (auto x : ans) cout << x.first << << x.second << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int x = 0, y = 0, z = 0; for (int i = 0; i < n; i++) { int a, b, c; cin >> a >> b >> c; x += a; y += b; c += z; } if (!x && !y && !z) cout << YES ; else cout << NO ; }
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T maxs(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T mins(T& a, T1 b) { if (b < a) a = b; return a; } const long long N = (1 << 21); const long long M = N - 1; pair<long long, long long> dp[N]; long long solve() { long long n; cin >> n; vector<long long> a(n + 1); auto add = [&](long long mask, long long j) { if (dp[mask].first == -1) dp[mask].first = j; else if (dp[mask].second == -1) { dp[mask].second = j; if (dp[mask].second < dp[mask].first) swap(dp[mask].first, dp[mask].second); } else if (dp[mask].second < j) { dp[mask].first = dp[mask].second; dp[mask].second = j; } else if (dp[mask].first < j && j != dp[mask].second) { dp[mask].first = j; } }; for (long long i = 1; i < n + 1; i++) { cin >> a[i]; add(a[i], i); } for (long long i = 0; i < 21; i++) { for (long long mask = 0; mask < N; mask++) { if ((mask) & (1 << i)) { if (dp[mask].first != -1) add(mask ^ (1 << i), dp[mask].first); if (dp[mask].second != -1) add(mask ^ (1 << i), dp[mask].second); } } } long long ans = 0; for (long long i = 1; i < n + 1; i++) { long long rev_mask = M - a[i]; long long best = 0; for (long long j = 20; j >= 0; j--) { if (rev_mask & (1 << j)) { if (dp[best ^ (1 << j)].second != -1 && dp[best ^ (1 << j)].first > i) { best ^= (1 << j); } } } if (i + 2 <= n) maxs(ans, a[i] + best); } cout << ans << n ; return 0; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; }
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; template <class T> inline void smin(T &a, T b) { if (a > b) a = b; } template <class T> inline void smax(T &a, T b) { if (a < b) a = b; } int qf, qb, q[11111111]; long long res[555], a[555][555], dst[555][555]; int r[555], first[555]; int main() { int N, ii, i, j, nn, u, st; scanf( %d , &N); for (i = 0; i < N; i++) for (j = 0; j < N; j++) scanf( %I64d , &dst[i][j]); for (i = 0; i < N; i++) { scanf( %d , r + i); r[i]--; } nn = 0; for (ii = N - 1; ii >= 0; ii--) { st = r[ii]; for (i = 0; i < nn; i++) { for (j = 0; j < nn; j++) { smin(dst[st][first[j]], dst[st][first[i]] + dst[first[i]][first[j]]); smin(dst[first[j]][st], dst[first[j]][first[i]] + dst[first[i]][st]); } } for (i = 0; i < nn; i++) for (j = 0; j < nn; j++) smin(dst[first[i]][first[j]], dst[first[i]][st] + dst[st][first[j]]); first[nn++] = st; res[ii] = 0; for (i = 0; i < nn; i++) for (j = 0; j < nn; j++) res[ii] += dst[first[i]][first[j]]; } for (i = 0; i < N; i++) { if (i) printf( ); printf( %I64d , res[i]); } puts( ); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 27, maxm = 5e4 + 20, inf = 1e9; vector<int> ar[maxn][maxn][maxn][maxn]; int q, a[maxm], bs[4], bs2[4]; string s, qs, qss; map<pair<string, string>, int> mp; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> s >> q; for (int i = 0; i < s.size(); i++) a[i] = (int)s[i] - a , ar[(int)s[i] - a ][26][26][26].push_back(i); for (int i = 0; i < (int)s.size() - 1; i++) ar[a[i]][a[i + 1]][26][26].push_back(i); for (int i = 0; i < (int)s.size() - 2; i++) ar[a[i]][a[i + 1]][a[i + 2]][26].push_back(i); for (int i = 0; i < (int)s.size() - 3; i++) ar[a[i]][a[i + 1]][a[i + 2]][a[i + 3]].push_back(i); while (q--) { cin >> qs >> qss; if (qss < qs) swap(qss, qs); fill(bs, bs + 4, 26), fill(bs2, bs2 + 4, 26); for (int i = 0; i < qs.size(); i++) bs[i] = qs[i] - a ; for (int i = 0; i < qss.size(); i++) bs2[i] = qss[i] - a ; if (ar[bs[0]][bs[1]][bs[2]][bs[3]].size() > ar[bs2[0]][bs2[1]][bs2[2]][bs2[3]].size()) swap(qs, qss), swap(bs, bs2); if (mp.count(make_pair(qs, qss))) { cout << mp[make_pair(qs, qss)] << endl; continue; } int ans = inf, j; for (int i : ar[bs[0]][bs[1]][bs[2]][bs[3]]) { auto it = upper_bound(ar[bs2[0]][bs2[1]][bs2[2]][bs2[3]].begin(), ar[bs2[0]][bs2[1]][bs2[2]][bs2[3]].end(), i); if (it != ar[bs2[0]][bs2[1]][bs2[2]][bs2[3]].end()) { j = *it; ans = min(ans, max(i + (int)qs.size(), j + (int)qss.size()) - i); } if (it != ar[bs2[0]][bs2[1]][bs2[2]][bs2[3]].begin()) { it--; j = *it; ans = min(ans, max(i + (int)qs.size(), j + (int)qss.size()) - j); } } if (ans == inf) ans = -1; mp[make_pair(qs, qss)] = ans; cout << ans << endl; } }
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 100; long long x[maxn]; char type[maxn], t; vector<long long> B, R, G; long long szR, szB, n, pos; void Put(long long st, long long en) { R.clear(); B.clear(); for (int i = st; i <= en; ++i) { if (type[i] == 1) R.push_back(i); else if (type[i] == 2) B.push_back(i); } szR = R.size(); szB = B.size(); } int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> pos >> t; x[i] = pos; if (t == P ) type[i] = 0, G.push_back(i); else if (t == R ) type[i] = 1; else type[i] = 2; } long long ans = 0; int sz = G.size(); if (sz == 0) { Put(1, n); if (szR > 0) ans += x[R[szR - 1]] - x[R[0]]; if (szB > 0) ans += x[B[szB - 1]] - x[B[0]]; } else { Put(1, G[0] - 1); if (szR > 0) ans += x[G[0]] - x[R[0]]; if (szB > 0) ans += x[G[0]] - x[B[0]]; Put(G[sz - 1] + 1, n); if (szR > 0) ans += x[R[szR - 1]] - x[G[sz - 1]]; if (szB > 0) ans += x[B[szB - 1]] - x[G[sz - 1]]; for (int i = 0; i < sz - 1; ++i) { long long x1 = G[i], x2 = G[i + 1]; long long tmp1 = 0, tmp2 = 0; Put(x1 + 1, x2 - 1); if (szR > 0) { tmp1 = x[R[0]] - x[x1]; for (int p = 1; p < szR; ++p) tmp1 = max(tmp1, x[R[p]] - x[R[p - 1]]); tmp1 = max(tmp1, x[x2] - x[R[szR - 1]]); } else tmp1 = x[x2] - x[x1]; if (szB > 0) { tmp2 = x[B[0]] - x[x1]; for (int p = 1; p < szB; ++p) tmp2 = max(tmp2, x[B[p]] - x[B[p - 1]]); tmp2 = max(tmp2, x[x2] - x[B[szB - 1]]); } else tmp2 = x[x2] - x[x1]; ans += min((x[x2] - x[x1]) * 2, (x[x2] - x[x1]) * 3 - tmp1 - tmp2); } } cout << ans << endl; return 0; }
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v1_9_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
`timescale 1ns / 1ps
module Print(
input mclk,
input [15:0] num,
output reg [7:0] display,
output reg [3:0] an
);
reg [3:0] tmp;
reg [15:0] counter;
parameter [15:0] MAX_COUNTER = 16'D5_0000;
initial begin
an = 4'B0111;
counter = 0;
end
always@(posedge mclk) begin
counter = counter + 1;
if (counter == MAX_COUNTER) begin
an = (an >> 1) + 4'B1000;
if (an == 4'B1111) begin
an = 4'B0111;
end
counter = 0;
case(an)
4'B0111: tmp = num[15:12];
4'B1011: tmp = num[11:8];
4'B1101: tmp = num[7:4];
4'B1110: tmp = num[3:0];
endcase
case(tmp)
4'H0: display = 8'B0000_0011;
4'H1: display = 8'B1001_1111;
4'H2: display = 8'B0010_0101;
4'H3: display = 8'B0000_1101;
4'H4: display = 8'B1001_1001;
4'H5: display = 8'B0100_1001;
4'H6: display = 8'B0100_0001;
4'H7: display = 8'B0001_1111;
4'H8: display = 8'B0000_0001;
4'H9: display = 8'B0000_1001;
4'Ha: display = 8'B0001_0001;
4'Hb: display = 8'B1100_0001;
4'Hc: display = 8'B0110_0011;
4'Hd: display = 8'B1000_0101;
4'He: display = 8'B0110_0001;
4'Hf: display = 8'B0111_0001;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void processTest(int n, int64_t m, int64_t k) { vector<int64_t> path(n); int64_t bag = m; for (auto &v : path) { cin >> v; } for (int i = 1; i < path.size(); ++i) { auto toEq = max(path[i] - k, int64_t(0)); bag += path[i - 1] - toEq; if (bag < 0) { cout << NO << endl; return; } } cout << YES << endl; } int main() { int t; cin >> t; for (int i = 0; i < t; ++i) { int64_t n, m, k; cin >> n >> m >> k; processTest(n, m, k); } return 0; }
|
module uart_divider
#(parameter COUNT = 0, CLK2_MUL = 5)
(input sys_clk,
input reset,
output reg outclk,
output reg outclk2);
// COUNT values:
// 2.88MHz:
// Input @ 144MHz, COUNT = 25
// 576kHz:
// Input @ 144MHz, COUNT = 125
// 115.2kHz:
// Input @ 28.8MHz, COUNT = 125
// Input @ 144MHz, COUNT = 625
// 57.6kHz:
// Input @ 144MHz, COUNT = 1250
// TODO test:
// Input @ 28.8MHz, Output @ 57.6kHz, COUNT = 250
// Input @ 28.8MHz, Output @ 28.8kHz, COUNT = 500
// Input @ 144MHz, Output @ 115.2kHz, COUNT = 625
// TODO values:
// 1200, 2400, 4800, 9600, 19200, 28800, 38400, 57600, and 115200.
localparam BITS = $clog2(COUNT);
reg [(BITS-1):0] counter;
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
counter <= 'b0;
outclk <= 'b0;
end else begin
if(counter == (COUNT - 1)) begin
counter <= 'b0;
outclk <= ~outclk;
end else
counter <= counter + 1'b1;
end
end
// counter2 produces a clock that is a multiple of the uart clock.
// this clock is used to oversample the rx line
localparam COUNT2 = COUNT / CLK2_MUL;
localparam BITS2 = $clog2(COUNT2);
reg [(BITS2-1):0] counter2;
always @(posedge sys_clk or posedge reset)
begin
if(reset) begin
counter2 <= 'b0;
outclk2 <= 'b0;
end else begin
if(counter2 == (COUNT2 - 1)) begin
counter2 <= 'b0;
outclk2 <= ~outclk2;
end else
counter2 <= counter2 + 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cout.precision(10); int n; cin >> n; set<string> st; while (n--) { string s, ss; cin >> s; for (int i = s.size() - 1; i >= 0; i--) { if (s[i] == u ) { ss += oo ; } else if (s[i] == h ) { ss += h ; while (i > 0 && s[i - 1] == k ) { i--; } } else { ss += s[i]; } } reverse(ss.begin(), ss.end()); st.insert(ss); } cout << st.size() << n ; return 0; }
|
#include <bits/stdc++.h> using namespace std; int number[1003][1003][2]; int n, m, sum; int part = -1; int parts[1000003]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; string s[1003]; bool isvalid(int x, int y) { if (x >= 0 && x < n && y >= 0 && y < m) return 1; return 0; } int findsum(int x, int y) { int ans = 0; int anses[4]; int point = 0; for (int i = 0; i < 4; i++) { if (isvalid(x + dx[i], y + dy[i]) && s[x + dx[i]][y + dy[i]] == . ) { bool flag = 0; int p = number[x + dx[i]][y + dy[i]][1]; for (int j = 0; j < point; j++) { if (p == anses[j]) { flag = 1; } } if (flag == 0) { ans += parts[p]; } anses[point] = p; point++; } } return ans + 1; } void dfs(int x, int y) { if (number[x][y][0] == 0) { sum++; number[x][y][0] = 1; number[x][y][1] = part; for (int i = 0; i < 4; i++) { if (isvalid(x + dx[i], y + dy[i])) { if (s[x + dx[i]][y + dy[i]] == . ) { dfs(x + dx[i], y + dy[i]); } } } } } int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> s[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == . ) { if (number[i][j][0] == 0) { part++; dfs(i, j); parts[part] = sum; sum = 0; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (s[i][j] == * ) { s[i][j] = 0 + findsum(i, j) % 10; } } } for (int i = 0; i < n; i++) { cout << s[i] << endl; } }
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41A_BEHAVIORAL_PP_V
|
#include <bits/stdc++.h> using namespace std; template <class T> using vec = vector<T>; template <typename Iter> ostream &_IterOutput_(ostream &o, Iter b, Iter e, const string ss = , const string se = ) { o << ss; for (auto it = b; it != e; it++) o << (it == b ? : , ) << *it; return o << se; } template <typename T1, typename T2> ostream &operator<<(ostream &o, const pair<T1, T2> &pair) { return o << ( << pair.first << , << pair.second << ) ; } template <typename T> ostream &operator<<(ostream &o, const vector<T> &vec) { return _IterOutput_(o, begin(vec), end(vec), [ , ] ); } template <typename T> ostream &operator<<(ostream &o, const set<T> &st) { return _IterOutput_(o, begin(st), end(st), { , } ); } template <typename T, size_t N> ostream &operator<<(ostream &o, const array<T, N> &arr) { return _IterOutput_(o, begin(arr), end(arr), | , | ); } template <typename T1, typename T2> ostream &operator<<(ostream &o, const map<T1, T2> &mp) { o << { ; for (auto it = mp.begin(); it != mp.end(); it++) { o << (it == mp.begin() ? : , ) << it->first << : << it->second; } o << } ; return o; } using A3 = array<long long, 3>; inline long long get(long long x, long long i) { return (x & (63LL << (i * 6))) >> (i * 6); } inline long long se(long long x, long long i, long long w) { long long sh = (i * 6); (x &= ~(63LL << sh)) ^= w << sh; return x; } inline long long del(long long x, long long i) { long long sh = i * 6; long long rm = x & ((1LL << sh) - 1); ((x >>= sh + 6) <<= sh) |= rm; return x; } A3 dec(long long x) { return {x & 3, (x >> 2) & 3, (x >> 4) & 3}; } inline long long enc(A3 a) { if (a[2] > a[0]) swap(a[2], a[0]); return a[0] + (a[1] << 2) + (a[2] << 4); } unordered_map<long long, double> mem; const double INF = 1e9; long long norm(long long x) { static long long Z[30]; long long i = 1, p; for (; p = get(x, i); i++) { Z[i] = p; } sort(Z + 1, Z + i); for (long long j = 1; j < i; j++) { x = se(x, j, Z[j]); } return x; } long long zz = 0; double dp(long long st) { if (mem.count(st)) return mem[st]; double ex[4] = {0, INF, INF, INF}; for (long long i = 1, p; p = get(st, i); i++) { auto a = dec(p); if (!a[1] or (!a[0] and !a[2])) continue; for (long long j = 0; j < 3; j++) { if (!a[j]) continue; if (a[2] == 0 and j == 1) continue; long long cl = a[j]; auto b = a; b[j] = 0; long long nx; if (!b[1] or (!b[0] and !b[2])) { nx = del(st, i); } else { nx = se(st, i, enc(b)); } long long top = get(nx, 0); auto c = dec(top); if (c[0] and c[1] and c[2]) { top <<= 6; nx <<= 6; c = dec(top); } for (long long k = 0; k < 3; k++) if (!c[k]) { auto d = c; d[k] = cl; long long fn = norm(se(nx, 0, enc(d))); ex[cl] = min(ex[cl], dp(fn)); } } } if (ex[1] >= INF and ex[2] >= INF and ex[3] >= INF) { return (mem[st]) = 0; } else { double zzprob = 1.0 / 6; if (ex[1] == INF) zzprob += 1.0 / 6, ex[1] = 0; if (ex[2] == INF) zzprob += 2.0 / 6, ex[2] = 0; if (ex[3] == INF) zzprob += 2.0 / 6, ex[3] = 0; (mem[st]) = (ex[1] * 1.0 / 6 + ex[2] * 2.0 / 6 + ex[3] * 2.0 / 6 + 1) / (1.0 - zzprob); return (mem[st]); } } int32_t main() { do { ios_base::sync_with_stdio(0); cin.tie(0); } while (0); long long N; cin >> N; cout << fixed << setprecision(10); long long t = 0; for (long long i = 0; i < N; i++) { string s; cin >> s; A3 a; for (long long j = 0; j < 3; j++) { long long z = s[j] == R ? 1 : s[j] == G ? 2 : 3; a[j] = z; } (t <<= 6) += enc(a); } cout << dp(t) << endl; return 0; }
|
`default_nettype none
/****
HOLD
0 START
1 MOVE_K2U
1 MOVE_UK
2 EMD
****/
module execute_exception(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Event CTRL
input wire iEVENT_HOLD,
input wire iEVENT_START,
input wire iEVENT_IRQ_FRONT2BACK,
input wire iEVENT_IRQ_BACK2FRONT,
input wire iEVENT_END,
//Execute Module State
input wire iPREV_STATE_NORMAL,
input wire iPREV_STATE_LDST,
//Previous Instruxtion
input wire iPREV_VALID,
input wire iPREV_KERNEL_ACCESS,
input wire [31:0] iPREV_PC,
//Instruction Exception
input wire iEXCEPT_INST_VALID,
input wire [6:0] iEXCEPT_INST_NUM,
//Load Store Exception
input wire iEXCEPT_LDST_VALID,
input wire [6:0] iEXCEPT_LDST_NUM,
//Output Exception
output wire oEXCEPT_VALID,
output wire [6:0] oEXCEPT_NUM,
output wire [31:0] oEXCEPT_FI0R,
output wire [31:0] oEXCEPT_FI1R
);
reg [31:0] b_pc;
reg b_kernel_access;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_pc <= 32'h0;
b_kernel_access <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD)begin
b_pc <= 32'h0;
b_kernel_access <= 1'b0;
end
else begin
if(iPREV_VALID && iPREV_STATE_NORMAL)begin
b_pc <= iPREV_PC;
b_kernel_access <= iPREV_KERNEL_ACCESS;
end
end
end
/**************************************************************************************************
General Instruction Exception
**************************************************************************************************/
function [31:0] func_exception_fi0r;
input [6:0] func_error_code;
input [31:0] func_pc;
begin
if(func_error_code == `INT_NUM_PAGEFAULT || func_error_code == `INT_NUM_PRIVILEGE_ERRPR ||
func_error_code == `INT_NUM_INSTRUCTION_INVALID || func_error_code == `INT_NUM_DIVIDER_ERROR)begin
func_exception_fi0r = func_pc - 32'h4;
end
else begin
func_exception_fi0r = 32'h0;
end
end
endfunction
function [31:0] func_exception_fi1r;
input [6:0] func_error_code;
input [31:0] func_pc;
input func_kernel_access;
begin
if(func_error_code == `INT_NUM_PAGEFAULT)begin
func_exception_fi1r = {28'h0, 1'b1, !func_kernel_access, 1'b0, 1'b1};
end
else if(func_error_code == `INT_NUM_PRIVILEGE_ERRPR)begin
func_exception_fi1r = 32'h0;
end
else if(func_error_code == `INT_NUM_INSTRUCTION_INVALID)begin
func_exception_fi1r = func_pc - 32'h4;
end
else if(func_error_code == `INT_NUM_DIVIDER_ERROR)begin
func_exception_fi1r = func_pc - 32'h4;
end
else begin
func_exception_fi1r = 32'h0;
end
end
endfunction
/**************************************************************************************************
Exception D-FF
**************************************************************************************************/
wire instruction_enable_condition = iPREV_STATE_NORMAL && iPREV_VALID && iEXCEPT_INST_VALID;
wire ldst_enable_condition = iPREV_STATE_LDST && iEXCEPT_LDST_VALID;
reg b_state;
localparam PL_STT_IDLE = 1'b0;
localparam PL_STT_HOLD = 1'b1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= PL_STT_IDLE;
end
else if(iRESET_SYNC || iEVENT_HOLD)begin
b_state <= PL_STT_IDLE;
end
else begin
case(b_state)
PL_STT_IDLE:
begin
if(instruction_enable_condition || ldst_enable_condition)begin
b_state <= PL_STT_HOLD;
end
end
PL_STT_HOLD:
begin
b_state <= b_state;
end
endcase
end
end
reg b_exception_valid;
reg [6:0] b_exception_num;
reg [31:0] b_fi0r;
reg [31:0] b_fi1r;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_exception_valid <= 1'b0;
end
else if(iRESET_SYNC || iEVENT_HOLD)begin
b_exception_valid <= 1'b0;
end
else begin
if(instruction_enable_condition)begin
b_exception_valid <= 1'b1;
end
else if(ldst_enable_condition)begin
b_exception_valid <= 1'b1;
end
else begin
b_exception_valid <= 1'b0;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_exception_num <= 7'h0;
b_fi0r <= 32'h0;
b_fi0r <= 32'h1;
end
else if(iRESET_SYNC || iEVENT_HOLD)begin
b_exception_num <= 7'h0;
b_fi0r <= 32'h0;
b_fi0r <= 32'h1;
end
else begin
if(instruction_enable_condition)begin
b_exception_num <= iEXCEPT_INST_NUM;
b_fi0r <= func_exception_fi0r(iEXCEPT_INST_NUM, iPREV_PC);
b_fi1r <= func_exception_fi1r(iEXCEPT_INST_NUM, iPREV_PC, iPREV_KERNEL_ACCESS);
end
else if(ldst_enable_condition)begin
b_exception_num <= iEXCEPT_LDST_NUM;
b_fi0r <= b_pc - 32'h4;
b_fi1r <= {28'h0, 1'b0, !b_kernel_access, 1'b0, 1'b0};
end
end
end
assign oEXCEPT_VALID = b_exception_valid;
assign oEXCEPT_NUM = b_exception_num;
assign oEXCEPT_FI0R = b_fi0r;
assign oEXCEPT_FI1R = b_fi1r;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:200000 ) const int INF = 1e9 + 7; const double EPS = 1e-6; const double pi = acos(-1); const int MOD = 1e9 + 7; const int N = 1e5 + 1000; using namespace std; double mid; struct node { int pos, val; node() { pos = val = 0; } node(int a, int b) { pos = a; val = b; } bool operator<(node a) const { if (val != a.val) return val < a.val; if (abs(mid - pos * 1.0) != abs(mid - a.pos * 1.0)) return abs(mid - pos * 1.0) < abs(mid - a.pos * 1.0); return pos < a.pos; } }; int n, m, ans[N]; set<node> st; int main() { cin >> n >> m; mid = (m + 1) * 0.5; for (int i = 1; i <= m; i++) { st.insert(node(i, 0)); } for (int i = 1; i <= n; i++) { auto it = *st.begin(); st.erase(it); it.val++; ans[i] = it.pos; st.insert(it); } for (int i = 1; i <= n; i++) cout << ans[i] << n ; return 0; }
|
/**
* bsg_mem_1rw_sync_mask_write_bit_banked.v
*
* This module has the same interface/functionality as
* bsg_mem_1rw_sync_mask_write_bit.
*
* This module can be used for breaking a big SRAM block into
* smaller blocks. This might be useful, if the SRAM generator does not
* support sizes of SRAM that are too wide or too deep.
* It is also useful for power and delay perspective, since only one depth
* bank is activated while reading or writing.
*
*
* - width_p : width of the total memory
* - els_p : depth of the total memory
*
* - num_width_bank_p : Number of banks for the memory's width. width_p has
* to be a multiple of this number.
* - num_depth_bank_p : Number of banks for the memory's depth. els_p has to
* be a multiple of this number.
*
*
*/
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit_banked
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
// bank parameters
, parameter num_width_bank_p=1
, parameter num_depth_bank_p=1
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter bank_depth_lp=(els_p/num_depth_bank_p)
, parameter bank_addr_width_lp=`BSG_SAFE_CLOG2(bank_depth_lp)
, parameter depth_bank_idx_width_lp=`BSG_SAFE_CLOG2(num_depth_bank_p)
, parameter bank_width_lp=(width_p/num_width_bank_p)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [width_p-1:0] w_mask_i
, output [width_p-1:0] data_o
);
if (num_depth_bank_p==1) begin: db1
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_i)
,.addr_i(addr_i)
,.data_i(data_i[bank_width_lp*i+:bank_width_lp])
,.w_mask_i(w_mask_i[bank_width_lp*i+:bank_width_lp])
,.data_o(data_o[bank_width_lp*i+:bank_width_lp])
);
end
end
else begin: dbn
wire [depth_bank_idx_width_lp-1:0] depth_bank_idx_li = addr_i[0+:depth_bank_idx_width_lp];
wire [bank_addr_width_lp-1:0] bank_addr_li = addr_i[depth_bank_idx_width_lp+:bank_addr_width_lp];
logic [num_depth_bank_p-1:0] bank_v_li;
logic [num_depth_bank_p-1:0][width_p-1:0] bank_data_lo;
bsg_decode_with_v #(
.num_out_p(num_depth_bank_p)
) demux_v (
.i(depth_bank_idx_li)
,.v_i(v_i)
,.o(bank_v_li)
);
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
for (genvar j = 0; j < num_depth_bank_p; j++) begin: db
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(bank_v_li[j])
,.w_i(w_i)
,.addr_i(bank_addr_li)
,.data_i(data_i[i*bank_width_lp+:bank_width_lp])
,.w_mask_i(w_mask_i[i*bank_width_lp+:bank_width_lp])
,.data_o(bank_data_lo[j][i*bank_width_lp+:bank_width_lp])
);
end
end
logic [depth_bank_idx_width_lp-1:0] depth_bank_idx_r;
bsg_dff_en #(
.width_p(depth_bank_idx_width_lp)
) depth_bank_idx_dff (
.clk_i(clk_i)
,.en_i(v_i & ~w_i)
,.data_i(depth_bank_idx_li)
,.data_o(depth_bank_idx_r)
);
bsg_mux #(
.els_p(num_depth_bank_p)
,.width_p(width_p)
) data_out_mux (
.data_i(bank_data_lo)
,.sel_i(depth_bank_idx_r)
,.data_o(data_o)
);
end
// synopsys translate_off
initial begin
assert(els_p % num_depth_bank_p == 0)
else $error("[BSG_ERROR] num_depth_bank_p does not divide even with els_p. %m");
assert(width_p % num_width_bank_p == 0)
else $error("[BSG_ERROR] num_width_bank_p does not divide even with width_p. %m");
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit_banked)
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } inline long long int max(long long int a, long long int b, long long int c) { return max(max(a, b), c); } inline long long int min(long long int a, long long int b, long long int c) { return min(min(a, b), c); } inline long long int max(long long int a, long long int b) { return (a > b) ? a : b; } inline long long int min(long long int a, long long int b) { return (a < b) ? a : b; } inline long long int mul(long long int x, long long int y, long long int mod_) { return ((x % mod_) * 1LL * (y % mod_)) % mod_; } long long int power(long long int a, long long int n) { long long int p = 1; while (n > 0) { if (n % 2) { p = p * a; } n >>= 1; a *= a; } return p; } long long int powm(long long int a, long long int n, long long int mod_) { long long int p = 1; while (n) { if (n % 2) { p = mul(p, a, mod_); } n >>= 1; a = mul(a, a, mod_); } return p % mod_; } long long int powi(long long int a, long long int mod_) { return powm(a, mod_ - 2, mod_); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; long long int mn, mx; long long int n, m, t, k, i, j, sum = 0, flag = 0, cnt = 0; long long int x = 0, y = 0, z, l = 0, r = 0, q; int TC = 1; while (TC--) { cin >> q; cin >> n >> m; vector<pair<pair<long long int, long long int>, pair<long long int, long long int>>> sofa(q); for (i = 0; i < q; ++i) { cin >> sofa[i].first.first >> sofa[i].first.second >> sofa[i].second.first >> sofa[i].second.second; } long long int cr, cl, ct, cb; cin >> cl >> cr >> ct >> cb; vector<long long int> prx(n + 2), pry(m + 2), sux(n + 2), suy(m + 2); for (i = 0; i < q; ++i) { pair<long long int, long long int> p1, p2; tie(p1, p2) = sofa[i]; long long int xl = min(p1.first, p2.first); long long int xr = max(p1.first, p2.first); long long int yt = max(p1.second, p2.second); long long int yd = min(p1.second, p2.second); prx[xl]++; sux[xr]++; pry[yd]++; suy[yt]++; } for (i = 1; i < n + 2; ++i) { prx[i] += prx[i - 1]; } for (i = n; i >= 0; --i) { sux[i] += sux[i + 1]; } for (i = 1; i < m + 2; ++i) { pry[i] += pry[i - 1]; } for (i = m; i >= 0; --i) { suy[i] += suy[i + 1]; } for (i = 0; i < q; ++i) { pair<long long int, long long int> p1, p2; tie(p1, p2) = sofa[i]; long long int xl = min(p1.first, p2.first); long long int xr = max(p1.first, p2.first); long long int yt = max(p1.second, p2.second); long long int yd = min(p1.second, p2.second); ; if (cl == (prx[xr - 1] - (xl != xr)) and cr == (sux[xl + 1] - (xl != xr)) and cb == (suy[yd + 1] - (yt != yd)) and ct == (pry[yt - 1] - (yt != yd))) { cout << i + 1; return 0; } } cout << -1; }; return 0; }
|
/*
rom_init_rtl.v
Altera "Recommended HDL Coding Styles"
ROM с инициализацией и разрешением такта
*/
//`include "vconst_lib.v"
module rom_init_rtl(clk, clk_ena, addr_a, q_a);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
input clk, clk_ena;
input [ADDR_WIDTH-1:0] addr_a;
output reg [DATA_WIDTH-1:0] q_a;
// local
reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];
// init ///
initial
begin
$readmemb("rs_255_inv.vec", rom);
end
// logic
always @ (posedge clk)
begin
if(clk_ena)
q_a <= rom[addr_a];
end
endmodule
/**
single_clock_wr_ram lable_store( // память для fifo
.q(), .d(),
.write_address(), .read_address(),
.we(), .rde(), .clk(), .clk_ena() // последний нужен ли
);
*/
module single_clock_wr_ram(
q, d,
write_address, read_address,
we, rde, clk, clk_ena // последний нужен ли
);
parameter WIDTH = 8;
parameter LEN_ADDR = 8;
parameter DEPTH = 2**LEN_ADDR;
output reg [WIDTH-1:0] q;
input [WIDTH-1:0] d;
input [LEN_ADDR-1:0] write_address, read_address;
input we, rde, clk, clk_ena;
// local
reg [WIDTH-1:0] mem [DEPTH-1:0];
always @ (posedge clk) begin
//if()
if (we)
mem[write_address] <= d;
if(rde)
q <= mem[read_address]; // q does get d in this clock cycle if
// we is high
end
endmodule
|
//
// .. hwt-autodoc::
//
module FullAdder (
input wire a,
input wire b,
input wire ci,
output reg co,
output reg s
);
always @(a, b, ci) begin: assig_process_co
co = a & b | (a & ci) | (b & ci);
end
always @(a, b, ci) begin: assig_process_s
s = a ^ b ^ ci;
end
endmodule
//
// .. hwt-autodoc::
//
module RippleAdder3 #(
parameter p_wordlength = 4
) (
input wire[3:0] a,
input wire[3:0] b,
input wire ci,
output wire co,
output reg[3:0] s
);
reg sig_fa_0_a;
reg sig_fa_0_b;
wire sig_fa_0_ci;
wire sig_fa_0_co;
wire sig_fa_0_s;
reg sig_fa_1_a;
reg sig_fa_1_b;
wire sig_fa_1_ci;
wire sig_fa_1_co;
wire sig_fa_1_s;
reg sig_fa_2_a;
reg sig_fa_2_b;
wire sig_fa_2_ci;
wire sig_fa_2_co;
wire sig_fa_2_s;
reg sig_fa_3_a;
reg sig_fa_3_b;
wire sig_fa_3_ci;
wire sig_fa_3_co;
wire sig_fa_3_s;
FullAdder fa_0_inst (
.a(sig_fa_0_a),
.b(sig_fa_0_b),
.ci(sig_fa_0_ci),
.co(sig_fa_0_co),
.s(sig_fa_0_s)
);
FullAdder fa_1_inst (
.a(sig_fa_1_a),
.b(sig_fa_1_b),
.ci(sig_fa_1_ci),
.co(sig_fa_1_co),
.s(sig_fa_1_s)
);
FullAdder fa_2_inst (
.a(sig_fa_2_a),
.b(sig_fa_2_b),
.ci(sig_fa_2_ci),
.co(sig_fa_2_co),
.s(sig_fa_2_s)
);
FullAdder fa_3_inst (
.a(sig_fa_3_a),
.b(sig_fa_3_b),
.ci(sig_fa_3_ci),
.co(sig_fa_3_co),
.s(sig_fa_3_s)
);
assign co = sig_fa_3_co;
always @(sig_fa_0_s, sig_fa_1_s, sig_fa_2_s, sig_fa_3_s) begin: assig_process_s
s = {{{sig_fa_3_s, sig_fa_2_s}, sig_fa_1_s}, sig_fa_0_s};
end
always @(a) begin: assig_process_sig_fa_0_a
sig_fa_0_a = a[0];
end
always @(b) begin: assig_process_sig_fa_0_b
sig_fa_0_b = b[0];
end
assign sig_fa_0_ci = ci;
always @(a) begin: assig_process_sig_fa_1_a
sig_fa_1_a = a[1];
end
always @(b) begin: assig_process_sig_fa_1_b
sig_fa_1_b = b[1];
end
assign sig_fa_1_ci = sig_fa_0_co;
always @(a) begin: assig_process_sig_fa_2_a
sig_fa_2_a = a[2];
end
always @(b) begin: assig_process_sig_fa_2_b
sig_fa_2_b = b[2];
end
assign sig_fa_2_ci = sig_fa_1_co;
always @(a) begin: assig_process_sig_fa_3_a
sig_fa_3_a = a[3];
end
always @(b) begin: assig_process_sig_fa_3_b
sig_fa_3_b = b[3];
end
assign sig_fa_3_ci = sig_fa_2_co;
generate if (p_wordlength != 4)
$error("%m Generated only for this param value");
endgenerate
endmodule
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module rx_control_data_rdy(
input posedge_clk,
input rx_resetn,
input rx_error_c,
input rx_error_d,
input [2:0] control,
input [2:0] control_l_r,
input is_control,
input [5:0] counter_neg,
input last_is_control,
output reg rx_error,
output reg ready_control_p_r,
output reg ready_data_p_r,
output reg rx_got_fct_fsm
);
always@(posedge posedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
rx_got_fct_fsm <= 1'b0;
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
rx_error <= 1'b0;
end
else
begin
rx_error <= rx_error_c | rx_error_d;
if(counter_neg == 6'd4 && is_control)
begin
ready_control_p_r <= 1'b1;
ready_data_p_r <= 1'b0;
end
else if(counter_neg == 6'd32)
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b1;
end
else
begin
ready_control_p_r <= 1'b0;
ready_data_p_r <= 1'b0;
end
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
rx_got_fct_fsm <= 1'b1;
else
rx_got_fct_fsm <= rx_got_fct_fsm;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int MOD = 1e9 + 7; long long int INF = 1e18; long long int power(long long int base, long long int exp) { long long int res = 1; while (exp > 0) { if (exp % 2 == 1) res = (res * base); base = (base * base); exp /= 2; } return res; } long long int bitc(long long int n, long long int x) { return ((n >> x) & 1); } long long int __gcd(long long int a, long long int b) { return b == 0 ? a : __gcd(b, a % b); } long long int fsub(long long int a, long long int b, long long int p = MOD) { return ((a % p) - (b % p) + p) % p; } long long int fmult(long long int a, long long int b, long long int p = MOD) { return ((a % p) * (b % p)) % p; } long long int fadd(long long int a, long long int b, long long int p = MOD) { return (a % p + b % p) % p; } long long int fpow(long long int n, long long int k, long long int p = MOD) { long long int r = 1; while (k > 0) { if (k & 1) r = r * n % p; n = n * n % p; k = k >> 1; } return r; } long long int inv(long long int a, long long int p = MOD) { return fpow(a, p - 2, p); } long long int fdiv(long long int a, long long int b, long long int p = MOD) { long long int yinv = inv(b); long long int ans = (a * yinv) % p; return ans; } template <typename T> istream &operator>>(istream &in, vector<T> &a) { for (auto &item : a) { in >> item; } return in; } template <typename T, typename U> ostream &operator<<(ostream &out, pair<T, U> &a) { cout << a.first << << a.second; return out; } template <typename T, typename U> istream &operator>>(istream &out, pair<T, U> &a) { cin >> a.first >> a.second; return out; } template <typename T, typename U> ostream &operator<<(ostream &out, map<T, U> &a) { for (auto &item : a) { out << item << n ; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<T> &a) { for (auto &item : a) { out << item << ; } return out; } template <typename T> ostream &operator<<(ostream &out, vector<vector<T>> &a) { for (auto &item : a) { out << item << n ; } return out; } template <int D, typename T> struct Vec : public vector<Vec<D - 1, T>> { static_assert(D >= 1, Vector dimension must be greater than zero! ); template <typename... Args> Vec(int n = 0, Args... args) : vector<Vec<D - 1, T>>(n, Vec<D - 1, T>(args...)) {} }; template <typename T> struct Vec<1, T> : public vector<T> { Vec(int n = 0, T val = T()) : vector<T>(n, val) {} }; std::vector<bool> is_prime; std::vector<long long int> primes; void sieve(long long int n) { is_prime.resize(n + 2, true); primes.clear(); long long int p; for (p = 2; p * p <= n; p++) { if (is_prime[p]) { long long int i; for (i = p * p; i <= n; i += p) { is_prime[i] = false; } } } is_prime[0] = is_prime[1] = false; long long int i; for (i = 2; i <= n; i++) { if (is_prime[i]) { primes.emplace_back(i); } } } map<long long int, long long int> prime_factors(long long int n) { map<long long int, long long int> s; long long int i; long long int tc = 0; while (n % 2 == 0) { tc++; n /= 2; } if (tc > 0) { s[2] = tc; } for (i = 3; i <= sqrt(n); i += 2) { tc = 0; while (n % i == 0) { tc++; n /= i; } if (tc > 0) { s[i] = tc; } } if (n > 2) { s[n] += 1; } return s; } std::vector<long long int> fact_vec; void fact_fun(long long int n) { fact_vec.resize(n + 10); long long int i; fact_vec[0] = 1; for (i = 1; i <= n + 2; i++) { fact_vec[i] = (fact_vec[i - 1] * i) % MOD; } } std::vector<long long int> p2; void power_2(long long int n, long long int m = MOD) { long long int i; MOD = m; p2.emplace_back(1); for (i = 0; i < n; i++) { p2.emplace_back(fmult(p2.back(), 2)); } } long long int ncr(long long int n, long long int r) { if (r > n) return 0; return fdiv(fact_vec[n], fmult(fact_vec[r], fact_vec[n - r])); } std::vector<long long int> spf; void sieve2(long long int MAXN) { MAXN += 10; spf.resize(MAXN, 0); spf[1] = 1; for (long long int i = 2; i < MAXN; i++) spf[i] = i; for (long long int i = 4; i < MAXN; i += 2) spf[i] = 2; for (long long int i = 3; i * i < MAXN; i++) { if (spf[i] == i) { for (long long int j = i * i; j < MAXN; j += i) { if (spf[j] == j) spf[j] = i; } } } } std::vector<long long int> getFactorization(long long int x) { std::vector<long long int> ret; while (x != 1) { ret.emplace_back(spf[x]); x = x / spf[x]; } return ret; } int main() { long long int i, j; ios::sync_with_stdio(false); cin.tie(0); long long int ti; ti = 1; while (ti--) { long long int n, m; cin >> n >> m; Vec<2, long long int> mat(n + 2, m + 2), left, right, up, down, uvis, lvis, vis; uvis = lvis = vis = left = right = up = down = mat; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { char c; cin >> c; if (c == * ) { mat[i][j] = 1; } } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (mat[i][j] && mat[i][j - 1]) { left[i][j] = left[i][j - 1] + 1; } } for (j = m; j >= 1; j--) { if (mat[i][j] && mat[i][j + 1]) { right[i][j] = right[i][j + 1] + 1; } } } for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { if (mat[i][j] && mat[i - 1][j]) { up[i][j] = up[i - 1][j] + 1; } } for (i = n; i >= 1; i--) { if (mat[i][j] && mat[i + 1][j]) { down[i][j] = down[i + 1][j] + 1; } } } vector<pair<pair<long long int, long long int>, long long int>> ans; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { std::vector<long long int> tv = {up[i][j], down[i][j], left[i][j], right[i][j]}; long long int mn = *min_element((tv).begin(), (tv).end()); if (mn != 0) { ans.emplace_back(make_pair(make_pair(i, j), mn)); long long int lr = j - mn; long long int rr = j + mn + 1; lvis[i][lr]++; lvis[i][rr]--; uvis[i - mn][j]++; uvis[i + mn + 1][j]--; } } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { vis[i][j] = lvis[i][j] + vis[i][j - 1]; if (mat[i][j] && vis[i][j] > 0) { mat[i][j] = 0; } } } vis.clear(); vis.resize(n + 2, m + 2); for (j = 1; j <= m; j++) { for (i = 1; i <= n; i++) { vis[i][j] = uvis[i][j] + vis[i - 1][j]; if (mat[i][j] && vis[i][j] > 0) { mat[i][j] = 0; } } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { if (mat[i][j]) { cout << -1 << n ; return 0; } } } cout << ans.size() << n ; for (auto p : ans) { cout << p.first.first << << p.first.second << << p.second << n ; } } }
|
#include <bits/stdc++.h> using namespace std; using namespace std; const long long mod2 = 998244353; long long fpow(long long x, long long y) { x = x % 1000000007; long long sum = 1; while (y) { if (y & 1) sum = sum * x; sum %= 1000000007; y = y >> 1; x = x * x; x %= 1000000007; } return sum; } long long inv(long long a, long long m = 1000000007) { long long c = m; long long y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long q = a / m; long long t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += c; return x; } long long gcd(long long a, long long b) { if (!a) return b; return gcd(b % a, a); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); long long n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; i++) cin >> a[i]; long long res = 1; for (int i = 0; i < 10; i++) { long long ele = a[rng() % n]; vector<long long> div, cnt; for (long long j = 1; j * j <= ele; j++) { if ((ele % j) == 0) { if (j * j == ele) { div.push_back(j); cnt.push_back(0); } else { div.push_back(j); cnt.push_back(0); div.push_back(ele / j); cnt.push_back(0); } } } sort(div.begin(), div.end()); for (int j = 0; j < n; j++) { long long g = gcd(ele, a[j]); cnt[lower_bound(div.begin(), div.end(), g) - div.begin()]++; } for (int j = 0; j < div.size(); j++) { for (int k = j + 1; k < div.size(); k++) { if (div[k] % div[j] == 0) cnt[j] += cnt[k]; } if (2 * cnt[j] >= n) res = max(res, div[j]); } } cout << res << n ; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000 * 100 * 3 + 10; long long int mod = 998244353; long long int x[MAXN]; long long int y[MAXN]; pair<long long int, long long int> p[MAXN]; long long int f(long long int n) { long long int m = 1; for (int i = 1; i <= n; i++) { m *= i % mod; m = m % mod; } return m % mod; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; p[i].first = x[i]; p[i].second = y[i]; } sort(x, x + n); sort(y, y + n); sort(p, p + n); long long int k1 = 1; long long int k2 = 1; long long int c = 1; for (int i = 0; i < n - 1; i++) { long long int t = i, cnt = 1; bool bol = false; while (i < n && x[t] == x[i + 1]) { bol = true; cnt++; i++; } if (bol) { i--; } k1 *= f(cnt); k1 = k1 % mod; } for (int i = 0; i < n - 1; i++) { long long int t = i, cnt = 1; bool bol = false; while (i < n && y[t] == y[i + 1]) { bol = true; cnt++; i++; } if (bol) { i--; } k2 *= f(cnt); k2 = k2 % mod; } bool fl = false; for (int i = 1; i < n; i++) { if (p[i].second < p[i - 1].second) { fl = true; } } if (fl) { c = 0; } else { for (int i = 0; i < n - 1; i++) { long long int t = i, cnt = 1; bool bol = false; while (i < n && p[t].first == p[i + 1].first && p[t].second == p[i + 1].second) { bol = true; cnt++; i++; } if (bol) { i--; } c *= f(cnt); c = c % mod; } } cout << ((f(n) % mod - (k1 + k2) % mod + mod) % mod + c % mod) % mod << endl; return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_4_V
`define SKY130_FD_SC_HDLL__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_4_V
|
#include <bits/stdc++.h> using lint = long long int; using pii = std::pair<int, int>; using std::vector; int ve[200100]; bool check[200100]; int main(void) { int N, hol = 0; scanf( %d , &N); for (int i = 1; i <= N; i++) { int temp; scanf( %d , &temp); ve[i] = temp; } for (int i = 1; i <= N; i++) { int temp; scanf( %d , &temp); hol += temp; } int cou = 0; for (int i = 1; i <= N; i++) { if (!check[i]) { int ind = i; cou++; while (!check[ind]) { check[ind] = true; ind = ve[ind]; } } } int ans = 1 - (hol % 2); if (cou != 1) { ans += cou; } printf( %d , ans); return 0; }
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_TB_V
`define SKY130_FD_SC_HS__HA_TB_V
/**
* ha: Half adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ha.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline bool chkmin(T& x, T y) { return x > y ? x = y, true : false; } template <class T> inline bool chkmax(T& x, T y) { return x < y ? x = y, true : false; } inline int read(void) { int x, f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (x = 0; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return x * f; } template <typename T> struct Graph { enum { maxn = 305, maxm = 200000 }; struct Edge { int to, nxt; T w, cap, flow; } v[maxm]; int h[maxn], cnt; Graph() { memset(h, -1, sizeof(h)); } void add1(int x, int y, T w, T cap) { v[cnt] = Edge{y, h[x], w, cap, 0}; h[x] = cnt++; } void add(int x, int y, T w, T cap) { add1(x, y, w, cap); add1(y, x, -w, 0); } }; Graph<int> G; int Ss, Se; static int f[305]; int dfs(int x, int re) { if (x == Se || re <= 0) return re; int s1 = 0, t; for (int i = G.h[x]; i != -1; i = G.v[i].nxt) { int to = G.v[i].to; if (f[to] != f[x] + 1) continue; t = dfs(to, min(re, G.v[i].cap - G.v[i].flow)); G.v[i].flow += t; G.v[i ^ 1].flow -= t; s1 += t; re -= t; if (re == 0) break; } return s1; } bool bfs(int x) { queue<int> Q; memset(f, -1, sizeof(f)); Q.push(x); f[x] = 0; while (!Q.empty()) { int u = Q.front(); Q.pop(); for (int i = G.h[u]; i != -1; i = G.v[i].nxt) { if (G.v[i].flow >= G.v[i].cap) continue; int to = G.v[i].to; if (f[to] != -1) continue; f[to] = f[u] + 1; Q.push(to); } } return f[Se] != -1; } int dinic() { int ans = 0; while (bfs(Ss)) ans += dfs(Ss, 1000000000); return ans; } bool vi[305]; int n, lk[305], v, x, ans, w; vector<int> V[305]; bool dfs(int x) { vi[x] = 1; for (int i = 0; i <= V[x].size() - 1; ++i) { int to = V[x][i]; if (!lk[to] || (!vi[lk[to]] && dfs(lk[to]))) { lk[to] = x; return 1; } } return 0; } int main(void) { n = read(); for (int i = 1; i <= n; ++i) { v = read(); while (v--) { x = read(); V[i].push_back(x); } } for (int i = 1; i <= n; ++i) { memset(vi, 0, sizeof(vi)); dfs(i); } for (int i = 1; i <= n; ++i) for (int j = 0; j <= V[i].size() - 1; ++j) G.add(i, lk[V[i][j]], 0, 1000000000); Ss = n + 1; Se = n + 2; for (int i = 1; i <= n; ++i) { w = -read(); if (w < 0) G.add(i, Se, 0, -w); else G.add(Ss, i, 0, w), ans += w; } printf( %d n , -(ans - dinic())); return 0; }
|
#include <bits/stdc++.h> using namespace std; inline int getint() { int res = 0, fh = 1; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) fh = -1, ch = getchar(); while (ch <= 9 && ch >= 0 ) res = res * 10 + ch - 0 , ch = getchar(); return res * fh; } int n, m, A, B, out[23], mp[23][23]; double p[23], G[23][23], a[485][485], b[485], ans[485]; void gauss() { for (int i = 1; i <= n * n; i++) { int id = i; for (int j = i + 1; j <= n * n; j++) if (fabs(a[j][i]) > fabs(a[id][i])) id = j; for (int j = i; j <= n * n; j++) swap(a[i][j], a[id][j]); swap(b[i], b[id]); if (a[i][i]) { for (int j = i + 1; j <= n * n; j++) { double p = a[j][i] / a[i][i]; for (int k = i; k <= n * n; k++) a[j][k] -= a[i][k] * p; b[j] -= b[i] * p; } } } for (int i = n * n; i >= 1; i--) { if (a[i][i]) ans[i] = b[i] / a[i][i]; else ans[i] = 0; for (int j = i - 1; j >= 1; j--) b[j] -= a[j][i] * ans[i]; } } int main() { n = getint(); m = getint(); A = getint(); B = getint(); for (int i = 1; i <= m; i++) { int x = getint(), y = getint(); mp[x][y] = mp[y][x] = 1; out[x]++; out[y]++; } for (int i = 1; i <= n; i++) scanf( %lf , &p[i]), G[i][i] = p[i]; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (mp[i][j]) G[i][j] = (1 - p[i]) / (double)out[i]; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { a[((i - 1) * n + j)][((i - 1) * n + j)] = -1; for (int k = 1; k <= n; k++) for (int l = 1; l <= n; l++) if (k != l) a[((i - 1) * n + j)][((k - 1) * n + l)] += G[k][i] * G[l][j]; } b[((A - 1) * n + B)] = -1; gauss(); for (int i = 1; i <= n; i++) printf( %.10lf , ans[((i - 1) * n + i)]); return 0; }
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 3e5 + 100; const long long INF = 1e13; int u, v, c, b, laz[MAXN], C[MAXN], n, m, st[MAXN]; bool vis[MAXN]; multiset<pair<int, int> > Q[MAXN]; multiset<pair<int, int> >::iterator it; vector<pair<int, int> > W[MAXN]; vector<int> G[MAXN]; pair<int, int> k; void merg(int v, int u) { if (Q[v].size() >= Q[u].size()) { while (!(Q[u].empty())) { it = Q[u].begin(); int i = (*(it)).second; C[i] += laz[u] - laz[v]; c = (*it).first; Q[v].insert({c + laz[u] - laz[v], i}); Q[u].erase(it); } return; } merg(u, v); Q[v].swap(Q[u]); laz[v] = laz[u]; return; } long long ans = 0; int TIM = 0; bool dfs(int v, int f = -1) { st[v] = TIM; TIM++; for (auto u : G[v]) { if (u == f) { continue; } bool r = dfs(u, v); if (!r) { return 0; } merg(v, u); } for (auto k : W[v]) { if (st[k.first] < st[v]) { C[k.second] -= laz[v]; Q[v].insert({C[k.second], k.second}); } else { Q[v].erase({C[k.second], k.second}); } } if (!v) { return 1; } if (!(Q[v].size())) { return 0; } int h = (*(Q[v].begin())).first; ans += (h + laz[v]); laz[v] -= (h + laz[v]); return 1; } int main() { cin >> n >> m; for (int i = 0; i < n - 1; i++) { cin >> u >> v; u--; v--; G[u].push_back(v); G[v].push_back(u); } for (int i = 0; i < m; i++) { cin >> u >> v >> C[i]; u--; v--; W[u].push_back({v, i}); W[v].push_back({u, i}); } bool r = dfs(0); if (!r) { cout << -1 << endl; return 0; } cout << ans << endl; }
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